windows_vm: windows-2019
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
- ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220105-10Jan2022
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
- script: |
sfx.exe -y -o%CD:~0,2%\
%CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu"
+ %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Su"
displayName: 'Update MSYS2'
- script: |
- %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel"
+ %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
displayName: 'Install Toolchain'
- script: |
echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
pool:
vmImage: $(macos_vm)
steps:
- - script: brew install make
+ - script: brew install make ossp-uuid
displayName: Brew install dependencies
- script: |
gmake tools-only_config tools-only NO_SDL=1 \
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20220105-10Jan2022
+image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
# We run some tests in different order, to catch some failures quicker.
stages:
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
- default 0x4020000 if ARCH_SUNXI && !MACH_SUN8I_V3S
default 0x200000 if ARCH_BMIPS || X86
- default 0x220000 if ARCH_SUNXI && MACH_SUN8I_V3S
+ default 0x120000 if MACH_SUNIV
+ default 0x220000 if MACH_SUN8I_V3S
+ default 0x4020000 if ARCH_SUNXI
default 0x400000
help
This defines memory to be allocated for Dynamic allocation
used to generate a combined image with SPL and main U-Boot
proper as one single image.
+config REMAKE_ELF
+ bool "Recreate an ELF image from raw U-Boot binary"
+ help
+ Enable this to recreate an ELF image (u-boot.elf) from the raw
+ U-Boot binary (u-boot.bin), which may already have been statically
+ relocated and may already have a device-tree appended to it.
+
config BUILD_TARGET
string "Build target special images"
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
hex "Address in memory to use by default"
default 0x01000000 if ARCH_SOCFPGA
default 0x02000000 if PPC || X86
+ default 0x81000000 if MACH_SUNIV
default 0x22000000 if MACH_SUN9I
- default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
+ default 0x42000000 if ARCH_SUNXI
default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mvebu/
F: drivers/ata/ahci_mvebu.c
+F: drivers/clk/mvebu/
F: drivers/ddr/marvell/
F: drivers/gpio/mvebu_gpio.c
+F: drivers/i2c/mvtwsi.c
+F: drivers/mmc/xenon_sdhci.c
+F: drivers/phy/marvell/
+F: drivers/pinctrl/mvebu/
+F: drivers/rtc/armada38x.c
F: drivers/spi/kirkwood_spi.c
+F: drivers/spi/mvebu_a3700_spi.c
F: drivers/pci/pcie_dw_mvebu.c
+F: drivers/watchdog/armada-37xx-wdt.c
F: drivers/watchdog/orion_wdt.c
+F: include/configs/mv-common.h
ARM MARVELL PCIE CONTROLLER DRIVERS
M: Pali Rohár <pali@kernel.org>
M: Tom Rini <trini@konsulko.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-ti.git
+F: arch/arm/dts/am57xx*
+F: arch/arm/dts/dra7*
F: arch/arm/mach-davinci/
F: arch/arm/mach-k3/
F: arch/arm/mach-keystone/
F: drivers/phy/phy-ti-am654.c
F: drivers/phy/ti-pipe3-phy.c
F: drivers/ram/k3*
+F: drivers/remoteproc/ipu_rproc.c
F: drivers/remoteproc/k3_system_controller.c
F: drivers/remoteproc/pruc_rpoc.c
F: drivers/remoteproc/ti*
+F: drivers/reset/reset-dra7.c
F: drivers/reset/reset-ti-sci.c
F: drivers/rtc/davinci.c
F: drivers/serial/serial_omap.c
F: drivers/net/phy/xilinx_phy.c
F: drivers/net/zynq_gem.c
F: drivers/phy/phy-zynqmp.c
+F: drivers/power/domain/zynqmp-power-domain.c
F: drivers/serial/serial_zynq.c
F: drivers/reset/reset-zynqmp.c
F: drivers/rtc/zynqmp_rtc.c
T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git
F: doc/api/efi.rst
F: doc/develop/uefi/*
+F: doc/mkeficapsule.1
F: doc/usage/bootefi.rst
F: drivers/rtc/emul_rtc.c
F: include/capitalization.h
T: git https://source.denx.de/u-boot/custodians/u-boot-sh.git
F: arch/sh/
+SL28CLPD
+M: Michael Walle <michael@walle.cc>
+S: Maintained
+F: drivers/gpio/sl28cpld-gpio.c
+F: drivers/misc/sl28cpld.c
+F: drivers/watchdog/sl28cpld-wdt.c
+
SPI
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
VERSION = 2022
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@# is enable to tell 'deprecated' that one of these symbols exists
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
+ $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
@# options are whitelisted, so new ones should not be added.
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl31-path=${BL31} \
+ -a tee-os-path=${TEE} \
-a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
$(if $(KEYDIR),-k $(KEYDIR))
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
- -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -A $(ARCH) -T pblimage
ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
UBOOT_BIN := u-boot-with-dtb.bin
ifeq ($(CONFIG_BINMAN),y)
flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
$(call if_changed,binman)
- $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
else
flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
-I$(srctree)/arch/$(ARCH)/include \
$< -o $@; \
else \
- echo -n >$@ ; \
+ touch $@ ; \
fi
include/generated/env.in: include/generated/env.txt FORCE
$(call cmd,gen_envp)
elif [ -n "$(ENV_SOURCE_FILE)" ]; then \
echo "Missing file $(ENV_FILE_CFG)"; \
else \
- echo -n >$@ ; \
+ touch $@ ; \
fi
include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE
-o -name '*.asn1.[ch]' \
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
- -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
+ -o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
+ -o -name 'dsdt_generated.c' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f
CONFIG_SCSI) you must configure support for at
least one non-MTD partition type as well.
-- IDE Reset method:
- CONFIG_IDE_RESET - is this is defined, IDE Reset will
- be performed by calling the function
- ide_set_reset(int reset)
- which has to be defined in a board specific file
-
-- ATAPI Support:
- CONFIG_ATAPI
-
- Set this to enable ATAPI support.
-
- LBA48 Support
CONFIG_LBA48
When enabled, makes the IDE subsystem use 64bit sector addresses.
Default is 32bit.
-- SCSI Support:
- CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
- CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
- CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
- maximum numbers of LUNs, SCSI ID's and target
- devices.
-
- The environment variable 'scsidevs' is set to the number of
- SCSI devices found during the last scan.
-
- NETWORK Support (PCI):
CONFIG_E1000_SPI
Utility code for direct access to the SPI bus on Intel 8257x.
If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
forced to a value that ensures that CCSR is not relocated.
-- CONFIG_IDE_AHB:
- Most IDE controllers were designed to be connected with PCI
- interface. Only few of them were designed for AHB interface.
- When software is doing ATA command and data transfer to
- IDE devices through IDE-AHB controller, some additional
- registers accessing to these kind of IDE-AHB controller
- is required.
-
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
#include <common.h>
#include <api_public.h>
#include <part.h>
+#include <scsi.h>
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
#include <usb.h>
specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_SCSI)
- specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
+ specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
imply FIRMWARE
imply HASH_VERIFY
imply LZMA
- imply SCSI
imply TEE
imply AVB_VERIFY
imply LIBAVB
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
values, then choose this option, and create a file included as
<asm/arch/boot0.h> which contains the required assembler code.
-config ARM_CORTEX_CPU_IS_UP
- bool
-
config USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy"
default y if !ARM64
select DM
select DM_GPIO
select DM_KEYBOARD
+ select DM_MAILBOX
+ select DM_RESET
select DM_SERIAL
+ select DM_SPI
select DM_USB
select DM_VIDEO
select IOMMU
select POSITION_INDEPENDENT
select POWER_DOMAIN
select REGMAP
+ select SPI
select SYSCON
select SYSRESET
select SYSRESET_WATCHDOG
select DM_MMC if MMC
select DM_SERIAL
select GICV3
- select GPIO_EXTRA_HEADER
select OF_CONTROL
select SOC_DEVICE
imply BOARD_LATE_INIT
select CLK
select CLK_ZYNQ
select CPU_V7A
+ select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
- select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPI
select SPL_BOARD_INIT if SPL
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
- select GPIO_EXTRA_HEADER
select OF_CONTROL
imply CMD_DM
imply DM_USB_GADGET
select ARM64
select CLK
select DM
+ select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM_ETH if NET
select DM_MAILBOX
select DM_MMC if MMC
select DM_SPI_FLASH if DM_SPI
imply FIRMWARE
select GICV2
- select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
help
Support for Kontron SMARC-sAL28 board.
+config TARGET_TEN64
+ bool "Support ten64"
+ select ARCH_LS1088A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select FSL_DDR_INTERACTIVE if !SD_BOOT
+ select GPIO_EXTRA_HEADER
+ help
+ Support for Traverse Technologies Ten64 board, based
+ on NXP LS1088A.
+
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA27X
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
+source "board/traverse/ten64/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
# some files can only build in ARM or THUMB2, not THUMB1
static void cache_flush(void);
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
int cleanup_before_linux (void)
{
/*
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
- LOAD IVT 0x8000 0x1000
- CALL HAB 0x8000 0x0
+ LOAD IVT 0xE000 0x1000
+ CALL HAB 0xE000 0x0
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
- LOAD IVT 0x8000 0x1000
- CALL HAB 0x8000 0x0
+ LOAD IVT 0xE000 0x1000
+ CALL HAB 0xE000 0x0
LOAD 0x40002000 u-boot.bin
- LOAD IVT 0x8000 0x40002000
- CALL HAB 0x8000 0x0
+ LOAD IVT 0xE000 0x40002000
+ CALL HAB 0xE000 0x0
mxs_power_init_dcdc_4p2_source();
- writel(vdddctrl, &power_regs->hw_power_vdddctrl);
+ writel(vddioctrl, &power_regs->hw_power_vddioctrl);
early_delay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
early_delay(20);
- writel(vddioctrl, &power_regs->hw_power_vddioctrl);
+ writel(vdddctrl, &power_regs->hw_power_vdddctrl);
/*
* Check if FET is enabled on either powerout and if so,
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
+#include <linux/linkage.h>
/*
*************************************************************************
*/
.globl reset
+ .globl save_boot_params_ret
+ .type save_boot_params_ret,%function
reset:
+ /* Allow the board to save important registers */
+ b save_boot_params
+save_boot_params_ret:
/*
* set the cpu to SVC32 mode
*/
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+
+/*************************************************************************
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+ * __attribute__((weak));
+ *
+ * Stack pointer is not yet initialized at this moment
+ * Don't save anything to stack even if compiled with -O0
+ *
+ *************************************************************************/
+WEAK(save_boot_params)
+ b save_boot_params_ret /* back to my caller */
+ENDPROC(save_boot_params)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+
+obj-y += fel_utils.o
+CFLAGS_fel_utils.o := -marm
--- /dev/null
+# Build a combined spl + u-boot image
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ALL-y += u-boot-sunxi-with-spl.bin
+endif
+endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ ldr r0, =fel_stash
+ str sp, [r0, #0]
+ str lr, [r0, #4]
+ mrs lr, cpsr @ Read CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
+ str lr, [r0, #12]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+ mov sp, r0
+ mov lr, r1
+ ldr r0, =fel_stash
+ ldr r1, [r0, #16]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
+ ldr r1, [r0, #12]
+ msr cpsr, r1 @ Write CPSR
+ bx lr
+ENDPROC(return_to_fel)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
+ */
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ *(.text*)
+ } > .sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .sdram
+}
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config SPL_ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
+
endif
*
*************************************************************************/
ENTRY(cpu_init_cp15)
+
+#if CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN)
+ /*
+ * The Arm Cortex-A7 TRM says this bit must be enabled before
+ * "any cache or TLB maintenance operations are performed".
+ */
+ mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
+ orr r0, r0, #1 << 6 @ set SMP bit to enable coherency
+ mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register
+#endif
+
/*
* Invalidate L1 I/D
*/
# Based on some other Makefile
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += timer.o
obj-$(CONFIG_MACH_SUN6I) += tzpc.o
obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o
+obj-$(CONFIG_MACH_SUN6I) += sram.o
+obj-$(CONFIG_MACH_SUN8I) += sram.o
+
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SRAM init for older sunxi SoCs.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+
+void sunxi_sram_init(void)
+{
+ /*
+ * Undocumented magic taken from boot0, without this DRAM
+ * access gets messed up (seems cache related).
+ * The boot0 sources describe this as: "config ema for cache sram"
+ * Newer SoCs (A83T, H3 and anything beyond) don't need this anymore.
+ */
+ if (IS_ENABLED(CONFIG_MACH_SUN6I))
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+
+ if (IS_ENABLED(CONFIG_MACH_SUN8I)) {
+ uint version = sunxi_get_sram_id();
+
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_A23)) {
+ if (version == 0x1650)
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+ else /* 0x1661 ? */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
+ } else if (IS_ENABLED(CONFIG_MACH_SUN8I_A33)) {
+ if (version != 0x1667)
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
+ }
+ }
+}
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
-obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
obj-$(CONFIG_XEN) += xen/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * A lowlevel_init function that sets up the stack to call a C function to
- * perform further init.
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
- /*
- * Setup a temporary stack. Global data is not available yet.
- */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
- ldr w0, =CONFIG_SPL_STACK
-#else
- ldr w0, =CONFIG_SYS_INIT_SP_ADDR
-#endif
- bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
-
- /*
- * Save the old LR(passed in x29) and the current LR to stack
- */
- stp x29, x30, [sp, #-16]!
-
- /*
- * Call the very early init function. This should do only the
- * absolute bare minimum to get started. It should not:
- *
- * - set up DRAM
- * - use global_data
- * - clear BSS
- * - try to start a console
- *
- * For boards with SPL this should be empty since SPL can do all of
- * this init in the SPL board_init_f() function which is called
- * immediately after this.
- */
- bl s_init
- ldp x29, x30, [sp]
- ret
-ENDPROC(lowlevel_init)
pie_fixup_done:
#endif
-#ifdef CONFIG_SYS_RESET_SCTRL
- bl reset_sctrl
-#endif
-
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
.macro set_vbar, regname, reg
msr \regname, \reg
master_cpu:
bl _main
-#ifdef CONFIG_SYS_RESET_SCTRL
-reset_sctrl:
- switch_el x1, 3f, 2f, 1f
-3:
- mrs x0, sctlr_el3
- b 0f
-2:
- mrs x0, sctlr_el2
- b 0f
-1:
- mrs x0, sctlr_el1
-
-0:
- ldr x1, =0xfdfffffa
- and x0, x0, x1
-
- switch_el x1, 6f, 5f, 4f
-6:
- msr sctlr_el3, x0
- b 7f
-5:
- msr sctlr_el2, x0
- b 7f
-4:
- msr sctlr_el1, x0
-
-7:
- dsb sy
- isb
- b __asm_invalidate_tlb_all
- ret
-#endif
-
/*-----------------------------------------------------------------------*/
WEAK(apply_core_errata)
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
+
+#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER
+#include "linux-kernel-image-header-vars.h"
+#endif
}
fsl-ls1028a-kontron-sl28-var3.dtb \
fsl-ls1028a-kontron-sl28-var4.dtb \
+dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
+
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
stm32h743i-eval.dtb \
stm32h750i-art-pi.dtb
+dtb-$(CONFIG_MACH_SUNIV) += \
+ suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-var-som-symphony.dtb \
+ imx8mn-venice.dtb \
+ imx8mn-venice-gw7902.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
+ imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
imx8mp-evk.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
- imx8mq-pico-pi.dtb
+ imx8mp-verdin.dtb \
+ imx8mq-pico-pi.dtb \
+ imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
- k3-j7200-r5-common-proc-board.dtb
+ k3-j7200-r5-common-proc-board.dtb \
+ k3-j721e-sk.dtb \
+ k3-j721e-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
+ k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
-dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
-
-dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
+ imx8mm-cl-iot-gate-ied.dtbo \
+ imx8mm-cl-iot-gate-ied-adc0.dtbo \
+ imx8mm-cl-iot-gate-ied-adc1.dtbo \
+ imx8mm-cl-iot-gate-ied-can0.dtbo \
+ imx8mm-cl-iot-gate-ied-can1.dtbo \
+ imx8mm-cl-iot-gate-ied-tpm0.dtbo \
+ imx8mm-cl-iot-gate-ied-tpm1.dtbo
+
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \
+ imx8mm-cl-iot-gate-ied.dtbo \
+ imx8mm-cl-iot-gate-ied-adc0.dtbo \
+ imx8mm-cl-iot-gate-ied-adc1.dtbo \
+ imx8mm-cl-iot-gate-ied-can0.dtbo \
+ imx8mm-cl-iot-gate-ied-can1.dtbo \
+ imx8mm-cl-iot-gate-ied-tpm0.dtbo \
+ imx8mm-cl-iot-gate-ied-tpm1.dtbo
+
+ifneq ($(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)$(CONFIG_TARGET_IMX8MP_RSB3720A1_6G),)
+dtb-y += imx8mp-rsb3720-a1.dtb
+endif
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
#include "am33xx-u-boot.dtsi"
-/ {
- ocp {
- u-boot,dm-pre-reloc;
- };
-};
-
&l4_wkup {
u-boot,dm-pre-reloc;
+ segment@200000 {
+
+ target-module@10000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
};
&l4_per {
+ u-boot,dm-pre-reloc;
+ segment@100000 {
+ u-boot,dm-pre-reloc;
+
+ target-module@a6000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
segment@300000 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
/ {
xtal25mhz: xtal25mhz {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 371x family of SoCs
* (also named 88F3710)
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-37xx.dtsi"
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 3720 development board
* (DB-88F3720-DDR3)
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * This file is compatible with the version 1.4 and the version 2.0 of
+ * the board, however the CON numbers are different between the 2
+ * version
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
stdout-path = "serial0:115200n8";
};
- aliases {
- ethernet0 = ð0;
- i2c0 = &i2c0;
- spi0 = &spi0;
- };
-
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
-};
-&comphy {
- phy0 {
- phy-type = <COMPHY_TYPE_USB3_HOST0>;
- phy-speed = <COMPHY_SPEED_5G>;
+ exp_usb3_vbus: usb3-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb3_phy: usb3-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&exp_usb3_vbus>;
};
- phy1 {
- phy-type = <COMPHY_TYPE_PEX0>;
- phy-speed = <COMPHY_SPEED_2_5G>;
+ vcc_sd_reg1: regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
+
+ vcc_sd_reg2: regulator-vmcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sd2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
};
};
+/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
ð0 {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ status = "okay";
+};
+
+/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
+ð1 {
+ phy-mode = "sgmii";
+ phy = <&phy1>;
status = "okay";
- phy-mode = "rgmii";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
+
+ gpio_exp: pca9555@22 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ reg = <0x22>;
+ /*
+ * IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT
+ * IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE
+ * IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN
+ * IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN
+ * IO0_4: PWR_EN_SD
+ * IO0_5: PWR_EN_EMMC
+ * IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL
+ * IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS
+ */
+ };
+
+ rtc@68 {
+ /* PT7C4337A from pericom fully compatible with the ds1337 */
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
};
-/* CON3 */
-&sata {
+&mdio {
status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
};
-&sdhci0 {
- bus-width = <4>;
+/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
+&pcie0 {
pinctrl-names = "default";
- pinctrl-0 = <&sdio_pins>;
+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
-&sdhci1 {
+/* CON3 */
+&sata {
+ status = "okay";
+};
+
+&sdhci0 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc_pins>;
status = "okay";
+};
- #address-cells = <1>;
- #size-cells = <0>;
- mmccard: mmccard@0 {
- compatible = "mmc-card";
- reg = <0>;
- };
+/* SD slot module on CON14(V2.0)/CON15(V1.4) */
+&sdhci1 {
+ wp-inverted;
+ cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ marvell,pad-type = "sd";
+ vqmmc-supply = <&vcc_sd_reg1>;
+ vmmc-supply = <&vcc_sd_reg2>;
+ status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p128", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <50000000>;
- m25p,fast-read;
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0 0x200000>;
+ };
+ partition@200000 {
+ label = "U-boot Env";
+ reg = <0x200000 0x10000>;
+ };
+ partition@210000 {
+ label = "Linux";
+ reg = <0x210000 0xDF0000>;
+ };
+ };
};
};
-/* Exported on the micro USB connector CON32 through an FTDI */
+/*
+ * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
+ * an FTDI (also on CON24(V2.0)/CON26(V1.4)).
+ */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
-/* CON29 */
-&usb2 {
+/* CON26(V2.0)/CON28(V1.4) */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
status = "okay";
};
-/* CON31 */
-&usb3 {
+/* CON27(V2.0)/CON29(V1.4) */
+&usb2 {
status = "okay";
};
-/* CON17 */
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
- reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+/* CON29(V2.0)/CON31(V1.4) */
+&usb3 {
status = "okay";
+ usb-phy = <&usb3_phy>;
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+&spi0 {
+ spi-flash@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@firmware {
+ reg = <0 CONFIG_ENV_OFFSET>;
+ label = "firmware";
+ };
+
+ partition@u-boot-env {
+ reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
+ label = "u-boot-env";
+ };
+ };
+ };
+};
+#endif
+
+/*
+ * U-Boot requires to have this eMMC node by default in "okay" status. U-Boot
+ * at runtime changes status to "disabled" if eMMC is not present on the board.
+ */
+&sdhci0 {
+ status = "okay";
+};
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Device Tree file for Marvell Armada 3720 community board
- * (ESPRESSOBin)
+ * Device Tree file for Globalscale Marvell ESPRESSOBin Board
* Copyright (C) 2016 Marvell
*
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Konstantin Porotchkin <kostap@marvell.com>
+ * Romain Perier <romain.perier@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
*/
/dts-v1/;
-#include "armada-372x.dtsi"
+#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board";
compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- ethernet0 = ð0;
- i2c0 = &i2c0;
- spi0 = &spi0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
- };
-
- vcc_sd_reg0: regulator@0 {
- compatible = "regulator-gpio";
- regulator-name = "vcc_sd0";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-type = "voltage";
- states = <1800000 0x1
- 3300000 0x0>;
- gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
- };
-};
-
-ð0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
- phy-mode = "rgmii";
- phy_addr = <0x1>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
-};
-
-/* CON3 */
-&sata {
- status = "okay";
- phys = <&comphy2 0>;
-};
-
-&sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdio_pins>;
- bus-width = <4>;
- cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vcc_sd_reg0>;
- status = "okay";
-};
-
-/* U11 */
-&sdhci1 {
- non-removable;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
- marvell,xenon-emmc;
- marvell,xenon-tun-count = <9>;
- marvell,pad-type = "fixed-1-8v";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mmc_pins>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
- mmccard: mmccard@0 {
- compatible = "mmc-card";
- reg = <0>;
- };
-};
-
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi_quad_pins>;
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p128", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <50000000>;
- m25p,fast-read;
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@firmware {
- reg = <0 CONFIG_ENV_OFFSET>;
- label = "firmware";
- };
-
- partition@u-boot-env {
- reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
- label = "u-boot-env";
- };
- };
-#endif
- };
-};
-
-/* Exported on the micro USB connector CON32 through an FTDI */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
- status = "okay";
-};
-
-/* CON29 */
-&usb2 {
- status = "okay";
-};
-
-/* CON31 */
-&usb3 {
- status = "okay";
- phys = <&comphy0 0>;
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
- reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
- status = "okay";
- phys = <&comphy1 0>;
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Globalscale Marvell ESPRESSOBin Board
+ * Copyright (C) 2016 Marvell
+ *
+ * Romain Perier <romain.perier@free-electrons.com>
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-372x.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = ð0;
+ /* for dsa slave device */
+ ethernet1 = &switch0port1;
+ ethernet2 = &switch0port2;
+ ethernet3 = &switch0port3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+ };
+
+ vcc_sd_reg1: regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
+
+ led2: gpio-led2 {
+ /* led2 is working only on v7 board */
+ status = "disabled";
+
+ compatible = "gpio-leds";
+
+ led2 {
+ label = "led2";
+ gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+/* J9 */
+&pcie0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+};
+
+/* J6 */
+&sata {
+ status = "okay";
+};
+
+/* U11 */
+&sdhci0 {
+ /* Main DTS file for Espressobin is without eMMC */
+ status = "disabled";
+
+ non-removable;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ marvell,xenon-emmc;
+ marvell,xenon-tun-count = <9>;
+ marvell,pad-type = "fixed-1-8v";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmccard: mmccard@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+ };
+};
+
+/* J1 */
+&sdhci1 {
+ wp-inverted;
+ bus-width = <4>;
+ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
+ marvell,pad-type = "sd";
+ vqmmc-supply = <&vcc_sd_reg1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <104000000>;
+ m25p,fast-read;
+ };
+};
+
+/* Exported on the micro USB connector J5 through an FTDI */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+/*
+ * Connector J17 and J18 expose a number of different features. Some pins are
+ * multiplexed. This is the case for instance for the following features:
+ * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
+ * how to enable it. Beware that the signals are 1.8V TTL.
+ * - I2C
+ * - SPI
+ * - MMC
+ */
+
+/* J7 */
+&usb3 {
+ status = "okay";
+};
+
+/* J8 */
+&usb2 {
+ status = "okay";
+};
+
+&mdio {
+ switch0: switch0@1 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0port0: port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <ð0>;
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ switch0port1: port@1 {
+ reg = <1>;
+ label = "wan";
+ phy-handle = <&switch0phy0>;
+ };
+
+ switch0port2: port@2 {
+ reg = <2>;
+ label = "lan0";
+ phy-handle = <&switch0phy1>;
+ };
+
+ switch0port3: port@3 {
+ reg = <3>;
+ label = "lan1";
+ phy-handle = <&switch0phy2>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0@11 {
+ reg = <0x11>;
+ };
+ switch0phy1: switch0phy1@12 {
+ reg = <0x12>;
+ };
+ switch0phy2: switch0phy2@13 {
+ reg = <0x13>;
+ };
+ };
+ };
+};
+
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
-// SPDX-License-Identifier: GPL-2.0+ or X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for CZ.NIC Turris Mox Board
- * 2018 by Marek Behun <marek.behun@nic.cz>
- *
- * Based on armada-3720-espressobin.dts by:
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Konstantin Porotchkin <kostap@marvell.com>
+ * 2019 by Marek Behún <kabel@kernel.org>
*/
/dts-v1/;
+#include <dt-bindings/bus/moxtet.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
#include "armada-372x.dtsi"
/ {
compatible = "cznic,turris-mox", "marvell,armada3720",
"marvell,armada3710";
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
aliases {
+ spi0 = &spi0;
ethernet0 = ð0;
ethernet1 = ð1;
- i2c0 = &i2c0;
- spi0 = &spi0;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
-
- led {
+ red {
+ label = "mox:red:activity";
gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_ACTIVITY;
+ linux,default-trigger = "default-on";
};
};
compatible = "gpio-keys";
reset {
- compatible = "gpio-keys";
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
};
};
- reg_usb3_vbus: usb3_vbus@0 {
+ exp_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- startup-delay-us = <2000000>;
- shutdown-delay-us = <1000000>;
- gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
- regulator-boot-on;
+ regulator-always-on;
+ gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
};
vsdc_reg: vsdc-reg {
enable-active-high;
};
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
+ vsdio_reg: vsdio-reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vsdio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
- eth_phy1: ethernet-phy@1 {
- reg = <1>;
- };
+ gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
};
-};
-ð0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
- phy-mode = "rgmii";
- phy = <ð_phy1>;
-};
+ sdhci1_pwrseq: sdhci1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
-ð1 {
- phy-mode = "2500base-x";
- phys = <&comphy0 1>;
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <3000>;
+
+ /* enabled by U-Boot if SFP module is present */
+ status = "disabled";
+ };
+
+ firmware {
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
+ };
+ };
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ /delete-property/ mrvl,i2c-fast-mode;
status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
rtc@6f {
- compatible = "microchip,mcp7941x";
+ compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};
-&sdhci1 {
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+ status = "okay";
+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+ /*
+ * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
+ * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
+ * 2 size cells and also expects that the second range starts at 16 MB offset. If these
+ * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
+ * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
+ * for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping.
+ * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
+ * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
+ * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
+ * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
+ * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
+ */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
+ 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
+
+ /* enabled by U-Boot if PCIe module is present */
+ status = "disabled";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy1>;
+ status = "okay";
+};
+
+ð1 {
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ phys = <&comphy0 1>;
+};
+
+&sdhci0 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
status = "okay";
};
-&pinctrl_nb {
- spi_cs1_pins: spi-cs1-pins {
- groups = "spi_cs1";
- function = "spi";
- };
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_pins>;
+ non-removable;
+ bus-width = <4>;
+ marvell,pad-type = "sd";
+ vqmmc-supply = <&vsdio_reg>;
+ mmc-pwrseq = <&sdhci1_pwrseq>;
+ /* forbid SDR104 for FCC purposes */
+ sdhci-caps-mask = <0x2 0x0>;
+ status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&spi_cs1_pins>;
+ pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
assigned-clocks = <&nb_periph_clk 7>;
assigned-clock-parents = <&tbg 1>;
assigned-clock-rates = <20000000>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "st,s25fl064l", "jedec,spi-nor";
+ compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
- m25p,fast-read;
partitions {
compatible = "fixed-partitions";
};
};
- moxtet@1 {
+ moxtet: moxtet@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cznic,moxtet";
reg = <1>;
reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
- spi-max-frequency = <1000000>;
+ spi-max-frequency = <10000000>;
spi-cpol;
spi-cpha;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gpiosb>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+
+ moxtet_sfp: gpio@0 {
+ compatible = "cznic,moxtet-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0>;
+ status = "disabled";
+ };
};
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
+&usb2 {
status = "okay";
};
-&usb2 {
- status = "okay";
+&comphy2 {
+ connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&exp_usb3_vbus>;
+ };
};
&usb3 {
- vbus-supply = <®_usb3_vbus>;
status = "okay";
phys = <&comphy2 0>;
};
-&pcie0 {
+&mdio {
pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
- reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
- status = "disabled";
- phys = <&comphy1 0>;
+ pinctrl-0 = <&smi_pins>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ /* switch nodes are enabled by U-Boot if modules are present */
+ switch0@10 {
+ compatible = "marvell,mv88e6190";
+ reg = <0x10 0>;
+ dsa,member = <0 0>;
+ interrupt-parent = <&moxtet>;
+ interrupts = <MOXTET_IRQ_PERIDOT(0)>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy1: switch0phy1@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy2: switch0phy2@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy3: switch0phy3@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy4: switch0phy4@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy5: switch0phy5@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy6: switch0phy6@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy7: switch0phy7@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy8: switch0phy8@8 {
+ reg = <0x8>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0x1>;
+ label = "lan1";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@2 {
+ reg = <0x2>;
+ label = "lan2";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@3 {
+ reg = <0x3>;
+ label = "lan3";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@4 {
+ reg = <0x4>;
+ label = "lan4";
+ phy-handle = <&switch0phy4>;
+ };
+
+ port@5 {
+ reg = <0x5>;
+ label = "lan5";
+ phy-handle = <&switch0phy5>;
+ };
+
+ port@6 {
+ reg = <0x6>;
+ label = "lan6";
+ phy-handle = <&switch0phy6>;
+ };
+
+ port@7 {
+ reg = <0x7>;
+ label = "lan7";
+ phy-handle = <&switch0phy7>;
+ };
+
+ port@8 {
+ reg = <0x8>;
+ label = "lan8";
+ phy-handle = <&switch0phy8>;
+ };
+
+ port@9 {
+ reg = <0x9>;
+ label = "cpu";
+ ethernet = <ð1>;
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ };
+
+ switch0port10: port@a {
+ reg = <0xa>;
+ label = "dsa";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ link = <&switch1port9 &switch2port9>;
+ status = "disabled";
+ };
+
+ port-sfp@a {
+ reg = <0xa>;
+ label = "sfp";
+ sfp = <&sfp>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "disabled";
+ };
+ };
+ };
+
+ switch0@2 {
+ compatible = "marvell,mv88e6085";
+ reg = <0x2 0>;
+ dsa,member = <0 0>;
+ interrupt-parent = <&moxtet>;
+ interrupts = <MOXTET_IRQ_TOPAZ>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy1_topaz: switch0phy1@11 {
+ reg = <0x11>;
+ };
+
+ switch0phy2_topaz: switch0phy2@12 {
+ reg = <0x12>;
+ };
+
+ switch0phy3_topaz: switch0phy3@13 {
+ reg = <0x13>;
+ };
+
+ switch0phy4_topaz: switch0phy4@14 {
+ reg = <0x14>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0x1>;
+ label = "lan1";
+ phy-handle = <&switch0phy1_topaz>;
+ };
+
+ port@2 {
+ reg = <0x2>;
+ label = "lan2";
+ phy-handle = <&switch0phy2_topaz>;
+ };
+
+ port@3 {
+ reg = <0x3>;
+ label = "lan3";
+ phy-handle = <&switch0phy3_topaz>;
+ };
+
+ port@4 {
+ reg = <0x4>;
+ label = "lan4";
+ phy-handle = <&switch0phy4_topaz>;
+ };
+
+ port@5 {
+ reg = <0x5>;
+ label = "cpu";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ ethernet = <ð1>;
+ };
+ };
+ };
+
+ switch1@11 {
+ compatible = "marvell,mv88e6190";
+ reg = <0x11 0>;
+ dsa,member = <0 1>;
+ interrupt-parent = <&moxtet>;
+ interrupts = <MOXTET_IRQ_PERIDOT(1)>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch1phy1: switch1phy1@1 {
+ reg = <0x1>;
+ };
+
+ switch1phy2: switch1phy2@2 {
+ reg = <0x2>;
+ };
+
+ switch1phy3: switch1phy3@3 {
+ reg = <0x3>;
+ };
+
+ switch1phy4: switch1phy4@4 {
+ reg = <0x4>;
+ };
+
+ switch1phy5: switch1phy5@5 {
+ reg = <0x5>;
+ };
+
+ switch1phy6: switch1phy6@6 {
+ reg = <0x6>;
+ };
+
+ switch1phy7: switch1phy7@7 {
+ reg = <0x7>;
+ };
+
+ switch1phy8: switch1phy8@8 {
+ reg = <0x8>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0x1>;
+ label = "lan9";
+ phy-handle = <&switch1phy1>;
+ };
+
+ port@2 {
+ reg = <0x2>;
+ label = "lan10";
+ phy-handle = <&switch1phy2>;
+ };
+
+ port@3 {
+ reg = <0x3>;
+ label = "lan11";
+ phy-handle = <&switch1phy3>;
+ };
+
+ port@4 {
+ reg = <0x4>;
+ label = "lan12";
+ phy-handle = <&switch1phy4>;
+ };
+
+ port@5 {
+ reg = <0x5>;
+ label = "lan13";
+ phy-handle = <&switch1phy5>;
+ };
+
+ port@6 {
+ reg = <0x6>;
+ label = "lan14";
+ phy-handle = <&switch1phy6>;
+ };
+
+ port@7 {
+ reg = <0x7>;
+ label = "lan15";
+ phy-handle = <&switch1phy7>;
+ };
+
+ port@8 {
+ reg = <0x8>;
+ label = "lan16";
+ phy-handle = <&switch1phy8>;
+ };
+
+ switch1port9: port@9 {
+ reg = <0x9>;
+ label = "dsa";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ link = <&switch0port10>;
+ };
+
+ switch1port10: port@a {
+ reg = <0xa>;
+ label = "dsa";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ link = <&switch2port9>;
+ status = "disabled";
+ };
+
+ port-sfp@a {
+ reg = <0xa>;
+ label = "sfp";
+ sfp = <&sfp>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "disabled";
+ };
+ };
+ };
+
+ switch1@2 {
+ compatible = "marvell,mv88e6085";
+ reg = <0x2 0>;
+ dsa,member = <0 1>;
+ interrupt-parent = <&moxtet>;
+ interrupts = <MOXTET_IRQ_TOPAZ>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch1phy1_topaz: switch1phy1@11 {
+ reg = <0x11>;
+ };
+
+ switch1phy2_topaz: switch1phy2@12 {
+ reg = <0x12>;
+ };
+
+ switch1phy3_topaz: switch1phy3@13 {
+ reg = <0x13>;
+ };
+
+ switch1phy4_topaz: switch1phy4@14 {
+ reg = <0x14>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0x1>;
+ label = "lan9";
+ phy-handle = <&switch1phy1_topaz>;
+ };
+
+ port@2 {
+ reg = <0x2>;
+ label = "lan10";
+ phy-handle = <&switch1phy2_topaz>;
+ };
+
+ port@3 {
+ reg = <0x3>;
+ label = "lan11";
+ phy-handle = <&switch1phy3_topaz>;
+ };
+
+ port@4 {
+ reg = <0x4>;
+ label = "lan12";
+ phy-handle = <&switch1phy4_topaz>;
+ };
+
+ port@5 {
+ reg = <0x5>;
+ label = "dsa";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ link = <&switch0port10>;
+ };
+ };
+ };
+
+ switch2@12 {
+ compatible = "marvell,mv88e6190";
+ reg = <0x12 0>;
+ dsa,member = <0 2>;
+ interrupt-parent = <&moxtet>;
+ interrupts = <MOXTET_IRQ_PERIDOT(2)>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch2phy1: switch2phy1@1 {
+ reg = <0x1>;
+ };
+
+ switch2phy2: switch2phy2@2 {
+ reg = <0x2>;
+ };
+
+ switch2phy3: switch2phy3@3 {
+ reg = <0x3>;
+ };
+
+ switch2phy4: switch2phy4@4 {
+ reg = <0x4>;
+ };
+
+ switch2phy5: switch2phy5@5 {
+ reg = <0x5>;
+ };
+
+ switch2phy6: switch2phy6@6 {
+ reg = <0x6>;
+ };
+
+ switch2phy7: switch2phy7@7 {
+ reg = <0x7>;
+ };
+
+ switch2phy8: switch2phy8@8 {
+ reg = <0x8>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0x1>;
+ label = "lan17";
+ phy-handle = <&switch2phy1>;
+ };
+
+ port@2 {
+ reg = <0x2>;
+ label = "lan18";
+ phy-handle = <&switch2phy2>;
+ };
+
+ port@3 {
+ reg = <0x3>;
+ label = "lan19";
+ phy-handle = <&switch2phy3>;
+ };
+
+ port@4 {
+ reg = <0x4>;
+ label = "lan20";
+ phy-handle = <&switch2phy4>;
+ };
+
+ port@5 {
+ reg = <0x5>;
+ label = "lan21";
+ phy-handle = <&switch2phy5>;
+ };
+
+ port@6 {
+ reg = <0x6>;
+ label = "lan22";
+ phy-handle = <&switch2phy6>;
+ };
+
+ port@7 {
+ reg = <0x7>;
+ label = "lan23";
+ phy-handle = <&switch2phy7>;
+ };
+
+ port@8 {
+ reg = <0x8>;
+ label = "lan24";
+ phy-handle = <&switch2phy8>;
+ };
+
+ switch2port9: port@9 {
+ reg = <0x9>;
+ label = "dsa";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ link = <&switch1port10 &switch0port10>;
+ };
+
+ port-sfp@a {
+ reg = <0xa>;
+ label = "sfp";
+ sfp = <&sfp>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "disabled";
+ };
+ };
+ };
+
+ switch2@2 {
+ compatible = "marvell,mv88e6085";
+ reg = <0x2 0>;
+ dsa,member = <0 2>;
+ interrupt-parent = <&moxtet>;
+ interrupts = <MOXTET_IRQ_TOPAZ>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch2phy1_topaz: switch2phy1@11 {
+ reg = <0x11>;
+ };
+
+ switch2phy2_topaz: switch2phy2@12 {
+ reg = <0x12>;
+ };
+
+ switch2phy3_topaz: switch2phy3@13 {
+ reg = <0x13>;
+ };
+
+ switch2phy4_topaz: switch2phy4@14 {
+ reg = <0x14>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0x1>;
+ label = "lan17";
+ phy-handle = <&switch2phy1_topaz>;
+ };
+
+ port@2 {
+ reg = <0x2>;
+ label = "lan18";
+ phy-handle = <&switch2phy2_topaz>;
+ };
+
+ port@3 {
+ reg = <0x3>;
+ label = "lan19";
+ phy-handle = <&switch2phy3_topaz>;
+ };
+
+ port@4 {
+ reg = <0x4>;
+ label = "lan20";
+ phy-handle = <&switch2phy4_topaz>;
+ };
+
+ port@5 {
+ reg = <0x5>;
+ label = "dsa";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ link = <&switch1port10 &switch0port10>;
+ };
+ };
+ };
};
};
};
-&sdhci1 {
+&sdhci0 {
u-boot,dm-pre-reloc;
};
* Device tree for the uDPU board.
* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
* Copyright (C) 2016 Marvell
- * Copyright (C) 2018 Methode
- * Copyright (C) 2018 Telus
+ * Copyright (C) 2019 Methode Electronics
+ * Copyright (C) 2019 Telus
*
* Vladimir Vid <vladimir.vid@sartura.hr>
*/
/dts-v1/;
-#include "armada-37xx.dtsi"
-#include "armada-3720-uDPU-u-boot.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-372x.dtsi"
/ {
model = "Methode uDPU Board";
- compatible = "methode,udpu";
+ compatible = "methode,udpu", "marvell,armada3720";
chosen {
stdout-path = "serial0:115200n8";
- bootargs = "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000";
- };
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- spi0 = &spi0;
};
memory@0 {
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
- mdio: mdio@32004 {
- #address-cells = <1>;
- #size-cells = <0>;
- ethphy0: ethernet-phy@0 {
- reg = <0>;
+ leds {
+ pinctrl-names = "default";
+ compatible = "gpio-leds";
+
+ power1 {
+ label = "udpu:green:power";
+ gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
- ethphy1: ethernet-phy@1 {
- reg = <1>;
+
+ power2 {
+ label = "udpu:red:power";
+ gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
- };
- scsi: scsi {
- compatible = "marvell,mvebu-scsi";
- #address-cells = <1>;
- #size-cells = <1>;
- max-id = <1>;
- max-lun = <1>;
- status = "okay";
- };
+ network1 {
+ label = "udpu:green:network";
+ gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
+ };
- i2c1: i2c@11080 {
- compatible = "marvell,armada-3700-i2c", "simple-bus";
- reg = <0x0 0x11080 0x0 0x80>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- #address-cells = <2>;
- #size-cells = <2>;
- status = "okay";
- };
+ network2 {
+ label = "udpu:red:network";
+ gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
+ };
- uart1: serial@12200 {
- compatible = "marvell,armada-3700-uart-ext";
- reg = <0x0 0x12200 0x0 0x30>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
- #address-cells = <2>;
- #size-cells = <2>;
- };
+ alarm1 {
+ label = "udpu:green:alarm";
+ gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
+ };
- vcc_sd_reg0: regulator@0 {
- compatible = "regulator-gpio";
- regulator-name = "vcc_sd0";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-type = "voltage";
- states = <1800000 0x1
- 3300000 0x0>;
- gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
+ alarm2 {
+ label = "udpu:red:alarm";
+ gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
+ };
};
sfp_eth0: sfp-eth0 {
mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <3000>;
};
sfp_eth1: sfp-eth1 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
- sfp,ethernet = <ð1>;
los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <3000>;
};
};
-ð0 {
- pinctrl-0 = <&pcie_pins>;
- status = "okay";
- phy-mode = "sgmii";
- managed = "in-band-status";
- phy = <ðphy0>;
- phys = <&comphy1 0>;
-};
-
-ð1 {
+&sdhci0 {
status = "okay";
- phy-mode = "sgmii";
- managed = "in-band-status";
- phy = <ðphy1>;
- phys = <&comphy0 1>;
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ marvell,pad-type = "fixed-1-8v";
+ non-removable;
+ no-sd;
+ no-sdio;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q1024a","n25q512a";
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <4>;
- m25p,fast-read;
-
- partition@0 {
- label = "uboot";
- reg = <0 0x400000>;
+ spi-max-frequency = <54000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* only bootloader is located on the SPI */
+ partition@0 {
+ label = "uboot";
+ reg = <0 0x400000>;
+ };
};
};
};
-&sdhci1 {
- non-removable;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- bus-width = <4>;
- vqmmc-supply = <&vcc_sd_reg0>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio_pins>;
+&pinctrl_nb {
+ i2c1_recovery_pins: i2c1-recovery-pins {
+ groups = "i2c1";
+ function = "gpio";
+ };
+
+ i2c2_recovery_pins: i2c2-recovery-pins {
+ groups = "i2c2";
+ function = "gpio";
+ };
+};
+
+&i2c0 {
status = "okay";
+ pinctrl-names = "default", "recovery";
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&i2c1_recovery_pins>;
+ /delete-property/mrvl,i2c-fast-mode;
+ scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
- #address-cells = <1>;
- #size-cells = <0>;
- mmccard: mmccard@0 {
- compatible = "mmc-card";
- reg = <0>;
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default", "recovery";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_recovery_pins>;
+ /delete-property/mrvl,i2c-fast-mode;
+ scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ lm75@48 {
+ status = "okay";
+ compatible = "lm75";
+ reg = <0x48>;
+ };
+
+ lm75@49 {
+ status = "okay";
+ compatible = "lm75";
+ reg = <0x49>;
};
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
+ð0 {
+ phy-mode = "sgmii";
+ status = "okay";
+ managed = "in-band-status";
+ phys = <&comphy1 0>;
+ sfp = <&sfp_eth0>;
+};
+
+ð1 {
+ phy-mode = "sgmii";
status = "okay";
+ managed = "in-band-status";
+ phys = <&comphy0 1>;
+ sfp = <&sfp_eth1>;
};
&usb3 {
status = "okay";
+ phys = <&usb2_utmi_otg_phy>;
+ phy-names = "usb2-utmi-otg-phy";
+};
+
+&uart0 {
+ status = "okay";
};
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 372x family of SoCs
* (also named 88F3720)
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-37xx.dtsi"
compatible = "marvell,armada3720", "marvell,armada3710";
cpus {
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x1>;
+ clocks = <&nb_periph_clk 16>;
enable-method = "psci";
};
};
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 37xx family of SoCs.
*
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/comphy/comphy_data.h>
-#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 37xx SoC";
aliases {
serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * The PSCI firmware region depicted below is the default one
+ * and should be updated by the bootloader.
+ */
+ psci-area@4000000 {
+ reg = <0 0x4000000 0 0x200000>;
+ no-map;
+ };
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0>;
+ clocks = <&nb_periph_clk 16>;
enable-method = "psci";
};
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#size-cells = <2>;
ranges;
- internal-regs {
+ internal-regs@d0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
+ wdt: watchdog@8300 {
+ compatible = "marvell,armada-3700-wdt";
+ reg = <0x8300 0x40>;
+ marvell,system-controller = <&cpu_misc>;
+ clocks = <&xtalclk>;
+ };
+
+ cpu_misc: system-controller@d000 {
+ compatible = "marvell,armada-3700-cpu-misc",
+ "syscon";
+ reg = <0xd000 0x1000>;
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,armada-3700-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10600 0xA00>;
+ clocks = <&nb_periph_clk 7>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <4>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11000 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11000 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&nb_periph_clk 10>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11080 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11080 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&nb_periph_clk 9>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ avs: avs@11500 {
+ compatible = "marvell,armada-3700-avs",
+ "syscon";
+ reg = <0x11500 0x40>;
+ };
+
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
- reg = <0x12000 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12000 0x18>;
+ clocks = <&xtalclk>;
+ interrupts =
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart-sum", "uart-tx", "uart-rx";
status = "disabled";
};
- wdt: watchdog-timer@8300 {
- compatible = "marvell,armada-3700-wdt";
- reg = <0xd064 0x4>,
- <0x8300 0x40>;
+ uart1: serial@12200 {
+ compatible = "marvell,armada-3700-uart-ext";
+ reg = <0x12200 0x30>;
+ clocks = <&xtalclk>;
+ interrupts =
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uart-tx", "uart-rx";
+ status = "disabled";
};
nb_periph_clk: nb-periph-clk@13000 {
- compatible = "marvell,armada-3700-periph-clock-nb";
+ compatible = "marvell,armada-3700-periph-clock-nb",
+ "syscon";
reg = <0x13000 0x100>;
- clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
+ clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
+ <&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
sb_periph_clk: sb-periph-clk@18000 {
compatible = "marvell,armada-3700-periph-clock-sb";
reg = <0x18000 0x100>;
- clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
+ clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
+ <&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
tbg: tbg@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x100>;
+ clocks = <&xtalclk>;
#clock-cells = <1>;
};
- pinctrl_nb: pinctrl-nb@13800 {
+ pinctrl_nb: pinctrl@13800 {
compatible = "marvell,armada3710-nb-pinctrl",
- "syscon", "simple-mfd";
+ "syscon", "simple-mfd";
reg = <0x13800 0x100>, <0x13C00 0x20>;
- gpionb: gpionb {
+ /* MPP1[19:0] */
+ gpionb: gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_nb 0 0 36>;
gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
interrupts =
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ xtalclk: xtal-clk {
+ compatible = "marvell,armada-3700-xtal-clock";
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
};
spi_quad_pins: spi-quad-pins {
function = "spi";
};
+ spi_cs1_pins: spi-cs1-pins {
+ groups = "spi_cs1";
+ function = "spi";
+ };
+
i2c1_pins: i2c1-pins {
groups = "i2c1";
function = "i2c";
};
};
- pinctrl_sb: pinctrl-sb@18800 {
+ nb_pm: syscon@14000 {
+ compatible = "marvell,armada-3700-nb-pm",
+ "syscon";
+ reg = <0x14000 0x60>;
+ };
+
+ comphy: phy@18300 {
+ compatible = "marvell,comphy-a3700";
+ reg = <0x18300 0x300>,
+ <0x1F000 0x400>,
+ <0x5C000 0x400>,
+ <0xe0178 0x8>;
+ reg-names = "comphy",
+ "lane1_pcie_gbe",
+ "lane0_usb3_gbe",
+ "lane2_sata_usb3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&xtalclk>;
+ clock-names = "xtal";
+
+ comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ comphy2: phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ pinctrl_sb: pinctrl@18800 {
compatible = "marvell,armada3710-sb-pinctrl",
- "syscon", "simple-mfd";
+ "syscon", "simple-mfd";
reg = <0x18800 0x100>, <0x18C00 0x20>;
- gpiosb: gpiosb {
+ /* MPP2[23:0] */
+ gpiosb: gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
function = "sdio";
};
- pcie_pins: pcie-pins {
- groups = "pcie1";
+ pcie_reset_pins: pcie-reset-pins {
+ groups = "pcie1"; /* this actually controls "pcie1_reset" */
function = "gpio";
};
+
+ pcie_clkreq_pins: pcie-clkreq-pins {
+ groups = "pcie1_clkreq";
+ function = "pcie";
+ };
+ };
+
+ eth0: ethernet@30000 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x30000 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sb_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@40000 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x40000 0x4000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sb_periph_clk 7>;
+ status = "disabled";
};
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
reg = <0x58000 0x4000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,usb-misc-reg = <&usb32_syscon>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sb_periph_clk 12>;
+ phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
+ phy-names = "usb3-phy", "usb2-utmi-otg-phy";
status = "disabled";
};
+ usb2_utmi_otg_phy: phy@5d000 {
+ compatible = "marvell,a3700-utmi-otg-phy";
+ reg = <0x5d000 0x800>;
+ marvell,usb-misc-reg = <&usb32_syscon>;
+ #phy-cells = <0>;
+ };
+
+ usb32_syscon: system-controller@5d800 {
+ compatible = "marvell,armada-3700-usb2-host-device-misc",
+ "syscon";
+ reg = <0x5d800 0x800>;
+ };
+
usb2: usb@5e000 {
- compatible = "marvell,armada3700-ehci";
- reg = <0x5e000 0x450>;
+ compatible = "marvell,armada-3700-ehci";
+ reg = <0x5e000 0x1000>;
+ marvell,usb-misc-reg = <&usb2_syscon>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_utmi_host_phy>;
+ phy-names = "usb2-utmi-host-phy";
status = "disabled";
};
+ usb2_utmi_host_phy: phy@5f000 {
+ compatible = "marvell,a3700-utmi-host-phy";
+ reg = <0x5f000 0x800>;
+ marvell,usb-misc-reg = <&usb2_syscon>;
+ #phy-cells = <0>;
+ };
+
+ usb2_syscon: system-controller@5f800 {
+ compatible = "marvell,armada-3700-usb2-host-misc",
+ "syscon";
+ reg = <0x5f800 0x800>;
+ };
+
xor@60900 {
compatible = "marvell,armada-3700-xor";
- reg = <0x60900 0x100
- 0x60b00 0x100>;
+ reg = <0x60900 0x100>,
+ <0x60b00 0x100>;
xor10 {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
};
- sdhci0: sdhci@d0000 {
+ crypto: crypto@90000 {
+ compatible = "inside-secure,safexcel-eip97ies";
+ reg = <0x90000 0x20000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clocks = <&nb_periph_clk 15>;
+ };
+
+ rwtm: mailbox@b0000 {
+ compatible = "marvell,armada-3700-rwtm-mailbox";
+ reg = <0xb0000 0x100>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
+ sdhci1: sdhci@d0000 {
compatible = "marvell,armada-3700-sdhci",
- "marvell,sdhci-xenon";
- reg = <0xd0000 0x300
- 0x1e808 0x4>;
+ "marvell,sdhci-xenon";
+ reg = <0xd0000 0x300>,
+ <0x1e808 0x4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
status = "disabled";
};
- sdhci1: sdhci@d8000 {
+ sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
- "marvell,sdhci-xenon";
- reg = <0xd8000 0x300
- 0x17808 0x4>;
+ "marvell,sdhci-xenon";
+ reg = <0xd8000 0x300>,
+ <0x17808 0x4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
status = "disabled";
};
sata: sata@e0000 {
compatible = "marvell,armada-3700-ahci";
- reg = <0xe0000 0x2000>;
+ reg = <0xe0000 0x178>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 1>;
+ phys = <&comphy2 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
- <0x1d40000 0x40000>; /* GICR */
- };
-
- eth0: neta@30000 {
- compatible = "marvell,armada-3700-neta";
- reg = <0x30000 0x20>;
- status = "disabled";
- };
-
- eth1: neta@40000 {
- compatible = "marvell,armada-3700-neta";
- reg = <0x40000 0x20>;
- status = "disabled";
- };
-
- i2c0: i2c@11000 {
- compatible = "marvell,armada-3700-i2c";
- reg = <0x11000 0x100>;
- status = "disabled";
- };
-
- spi0: spi@10600 {
- compatible = "marvell,armada-3700-spi";
- reg = <0x10600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- spi-max-frequency = <50000000>;
- clocks = <&nb_periph_clk 7>;
- status = "disabled";
- };
-
- comphy: comphy@18300 {
- compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
- reg = <0x18300 0x28>,
- <0x1f300 0x3d000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- comphy0: phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- comphy1: phy@1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- comphy2: phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
+ <0x1d40000 0x40000>, /* GICR */
+ <0x1d80000 0x2000>, /* GICC */
+ <0x1d90000 0x2000>, /* GICH */
+ <0x1da0000 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
pcie0: pcie@d0070000 {
compatible = "marvell,armada-3700-pcie";
+ device_type = "pci";
+ status = "disabled";
reg = <0 0xd0070000 0 0x20000>;
#address-cells = <3>;
#size-cells = <2>;
- device_type = "pci";
- num-lanes = <1>;
- status = "disabled";
-
- bus-range = <0 0xff>;
+ bus-range = <0x00 0xff>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ msi-parent = <&pcie0>;
+ msi-controller;
/*
* The 128 MiB address range [0xe8000000-0xf0000000] is
* dedicated for PCIe and can be assigned to 8 windows
* IO at the end and the remaining seven windows
* (totaling 127 MiB) for MEM.
*/
- ranges = <0x82000000 0 0xe8000000
- 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
- 0x81000000 0 0xeff00000
- 0 0xeff00000 0 0x100000>; /* Port 0 IO*/
+ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
+ 0x81000000 0 0xeff00000 0 0xeff00000 0 0x00100000>; /* Port 0 IO*/
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ max-link-speed = <2>;
+ phys = <&comphy1 0>;
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ firmware {
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware";
+ mboxes = <&rwtm 0>;
+ status = "okay";
};
};
};
*/
#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/ {
+ chosen {
+ firmware-loader = &fs_loader0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc1 1>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ u-boot,dm-spl;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ u-boot,dm-spl;
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ u-boot,dm-spl;
+ };
+
+ ipu1_pgtbl: ipu1-pgtbl@95700000 {
+ reg = <0x0 0x95700000 0x0 0x40000>;
+ no-map;
+ u-boot,dm-spl;
+ };
+
+ ipu2_pgtbl: ipu2-pgtbl@95740000 {
+ reg = <0x0 0x95740000 0x0 0x40000>;
+ no-map;
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&timer3 {
+ u-boot,dm-spl;
+};
+
+&timer4 {
+ u-boot,dm-spl;
+};
+
+&timer7 {
+ u-boot,dm-spl;
+};
+
+&timer8 {
+ u-boot,dm-spl;
+};
+
+&timer9 {
+ u-boot,dm-spl;
+};
+
+&timer11 {
+ u-boot,dm-spl;
+};
+
+&mmu_ipu1 {
+ u-boot,dm-spl;
+};
+
+&mmu_ipu2 {
+ u-boot,dm-spl;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_memory_region>;
+ pg-tbl = <&ipu1_pgtbl>;
+ u-boot,dm-spl;
+};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_memory_region>;
+ pg-tbl = <&ipu2_pgtbl>;
+ u-boot,dm-spl;
+};
+
+&l4_wkup {
+ u-boot,dm-spl;
+};
+
+&prm {
+ u-boot,dm-spl;
+};
+
+&ipu1_rst {
+ u-boot,dm-spl;
+};
+
+&ipu2_rst {
+ u-boot,dm-spl;
+};
d_can0 = &dcan1;
d_can1 = &dcan2;
spi0 = &qspi;
+ remoteproc0 = &ipu1;
+ remoteproc1 = &ipu2;
};
timer {
};
prm: prm@6000 {
- compatible = "ti,dra7-prm";
+ compatible = "ti,dra7-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
prm_clockdomains: clockdomains {
};
+
+ ipu1_rst: ipu1_rst@510 {
+ compatible = "ti,dra7-reset";
+ reg = <0x510 0x8>;
+ ti,nresets = <3>;
+ #reset-cells = <1>;
+ };
+
+ ipu2_rst: ipu2_rst@910 {
+ compatible = "ti,dra7-reset";
+ reg = <0x910 0x8>;
+ ti,nresets = <3>;
+ #reset-cells = <1>;
+ };
};
scm_wkup: scm_conf@c000 {
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
+
+ ipu1: ipu@58820000 {
+ compatible = "ti,dra7-ipu";
+ reg = <0x58820000 0x10000>;
+ reg-names = "l2ram";
+ ti,hwmods = "ipu1";
+ resets = <&ipu1_rst 0>, <&ipu1_rst 1>, <&ipu1_rst 2>;
+ iommus = <&mmu_ipu1>;
+ ti,rproc-standby-info = <0x4a005520>;
+ timers = <&timer11>;
+ watchdog-timers = <&timer7>, <&timer8>;
+ };
+
+ ipu2: ipu@55020000 {
+ compatible = "ti,dra7-ipu";
+ reg = <0x55020000 0x10000>;
+ reg-names = "l2ram";
+ ti,hwmods = "ipu2";
+ resets = <&ipu2_rst 0>, <&ipu2_rst 1>, <&ipu2_rst 2>;
+ iommus = <&mmu_ipu2>;
+ ti,rproc-standby-info = <0x4a008920>;
+ timers = <&timer3>;
+ watchdog-timers = <&timer4>, <&timer9>;
+ };
};
thermal_zones: thermal-zones {
*/
#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;
*/
#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;
*/
#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
&cpsw_emac0 {
phy-handle = <&dp83867_0>;
>;
};
+ /* On Module I2C */
+ pinctrl_i2c0: i2c0grp {
+ fsl,pins = <
+ SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
+ SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
+ >;
+ };
+
/* Off Module I2C */
pinctrl_i2c1: i2c1grp {
fsl,pins = <
};
};
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "okay";
+
+ /* GPIO expander */
+ gpio_expander_43: gpio-expander@43 {
+ compatible = "fcs,fxl6408";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x43>;
+ initial_io_dir = <0xff>;
+ initial_output = <0x05>;
+ };
+};
+
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
fit {
offset = <CONFIG_SPL_PAD_TO>;
description = "FIT image with multiple configurations";
+ fit,fdt-list = "of-list";
images {
uboot {
};
};
- fdt-1 {
- description = "fsl-ls1028a-kontron-sl28";
+ @fdt-SEQ {
+ description = "NAME";
type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28.dtb";
- };
- };
-
- fdt-2 {
- description = "fsl-ls1028a-kontron-sl28-var1";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dtb";
- };
- };
-
- fdt-3 {
- description = "fsl-ls1028a-kontron-sl28-var2";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dtb";
- };
- };
-
- fdt-4 {
- description = "fsl-ls1028a-kontron-sl28-var3";
- type = "flat_dt";
- arch = "arm";
compression = "none";
-
- blob {
- filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dtb";
- };
- };
-
- fdt-5 {
- description = "fsl-ls1028a-kontron-sl28-var4";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dtb";
- };
};
};
configurations {
- default = "conf-1";
-
- conf-1 {
- description = "fsl-ls1028a-kontron-sl28";
- firmware = "uboot";
- fdt = "fdt-1";
- };
-
- conf-2 {
- description = "fsl-ls1028a-kontron-sl28-var1";
- firmware = "uboot";
- fdt = "fdt-2";
- };
-
- conf-3 {
- description = "fsl-ls1028a-kontron-sl28-var2";
- firmware = "uboot";
- fdt = "fdt-3";
- };
-
- conf-4 {
- description = "fsl-ls1028a-kontron-sl28-var3";
- firmware = "uboot";
- loadables = "uboot";
- fdt = "fdt-4";
- };
+ default = "@config-DEFAULT-SEQ";
- conf-5 {
- description = "fsl-ls1028a-kontron-sl28-var4";
+ @config-SEQ {
+ description = "NAME";
firmware = "uboot";
- loadables = "uboot";
- fdt = "fdt-5";
+ fdt = "fdt-SEQ";
};
};
};
};
configurations {
- conf-1 {
- firmware = "bl31";
- loadables = "uboot";
- };
-
- conf-2 {
- firmware = "bl31";
- loadables = "uboot";
- };
-
- conf-3 {
- firmware = "bl31";
- loadables = "uboot";
- };
-
- conf-4 {
- firmware = "bl31";
- loadables = "uboot";
- };
-
- conf-5 {
+ @config-SEQ {
firmware = "bl31";
loadables = "uboot";
};
};
configurations {
- conf-1 {
- loadables = "uboot", "bl32";
- };
-
- conf-2 {
- loadables = "uboot", "bl32";
- };
-
- conf-3 {
- loadables = "uboot", "bl32";
- };
-
- conf-4 {
- loadables = "uboot", "bl32";
- };
-
- conf-5 {
+ @config-SEQ {
loadables = "uboot", "bl32";
};
};
&enetc_port0 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&enetc_port0 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port0 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
};
&mscc_felix_port2 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
&mscc_felix_port0 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
};
&mscc_felix_port2 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
&mscc_felix_port0 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
};
&mscc_felix_port0 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
};
&mscc_felix_port1 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
};
&mscc_felix_port2 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
};
&mscc_felix_port3 {
status = "okay";
+ managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
};
status = "okay";
rtc@51 {
- compatible = "pcf2127-rtc";
+ compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2021 NXP */
+
+/*
+ * u-boot will enable the device in the linux device tree in place. Because
+ * we are using the linux device tree, we have to enable the PCI controller
+ * ourselves.
+ */
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * NXP ls1028ARDB device tree source
+ * Device Tree file for NXP LS1028A RDB Board.
*
- * Copyright 2019 NXP
+ * Copyright 2018-2021 NXP
+ *
+ * Harninder Rai <harninder.rai@nxp.com>
*
*/
/dts-v1/;
-
#include "fsl-ls1028a.dtsi"
/ {
- model = "NXP Layerscape 1028a RDB Board";
+ model = "LS1028A RDB Board";
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
+
aliases {
+ crypto = &crypto;
+ serial0 = &duart0;
+ serial1 = &duart1;
+ mmc0 = &esdhc;
+ mmc1 = &esdhc1;
+ rtc1 = &ftm_alarm0;
spi0 = &fspi;
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port2;
ethernet4 = &mscc_felix_port2;
ethernet5 = &mscc_felix_port3;
};
-};
-&dspi0 {
- status = "okay";
-};
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
-&dspi1 {
- status = "okay";
-};
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x0000000>;
+ };
-&dspi2 {
- status = "okay";
-};
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
-&esdhc {
- status = "okay";
-};
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
-&esdhc1 {
- status = "okay";
- mmc-hs200-1_8v;
-};
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
-&fspi {
- status = "okay";
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai4>;
+ frame-master;
+ bitclock-master;
+ };
- mt35xu02g0: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- spi-rx-bus-width = <8>;
- spi-tx-bus-width = <1>;
+ simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <25000000>;
+ };
};
};
-&i2c0 {
+&can0 {
status = "okay";
- i2c-mux@77 {
-
- compatible = "nxp,pca9547";
- reg = <0x77>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x3>;
-
- rtc@51 {
- compatible = "pcf2127-rtc";
- reg = <0x51>;
- };
- };
+ can-transceiver {
+ max-bitrate = <5000000>;
};
};
-&i2c1 {
+&can1 {
status = "okay";
-};
-&i2c2 {
- status = "okay";
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
};
-&i2c3 {
+&duart0 {
status = "okay";
};
-&i2c4 {
+&duart1 {
status = "okay";
};
-&i2c5 {
- status = "okay";
-};
+&enetc_mdio_pf3 {
+ sgmii_phy0: ethernet-phy@2 {
+ reg = <0x2>;
+ };
-&i2c6 {
- status = "okay";
-};
+ /* VSC8514 QSGMII quad PHY */
+ qsgmii_phy0: ethernet-phy@10 {
+ reg = <0x10>;
+ };
-&i2c7 {
- status = "okay";
-};
+ qsgmii_phy1: ethernet-phy@11 {
+ reg = <0x11>;
+ };
-&sata {
- status = "okay";
-};
+ qsgmii_phy2: ethernet-phy@12 {
+ reg = <0x12>;
+ };
-&duart0 {
- status = "okay";
+ qsgmii_phy3: ethernet-phy@13 {
+ reg = <0x13>;
+ };
};
-&duart1 {
+&enetc_port0 {
+ phy-handle = <&sgmii_phy0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
status = "okay";
};
-&pcie1 {
+&enetc_port2 {
status = "okay";
};
-&pcie2 {
+&esdhc {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
status = "okay";
};
-&usb0 {
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
status = "okay";
};
-&usb1 {
+&fspi {
status = "okay";
-};
-&enetc_port0 {
- status = "okay";
- phy-mode = "sgmii";
- phy-handle = <&rdb_phy0>;
+ mt35xu02g0: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
+ spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+ reg = <0>;
+ };
};
-&enetc_port2 {
+&i2c0 {
status = "okay";
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9847";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ sgtl5000: audio-codec@a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ VDDA-supply = <®_1p8v>;
+ VDDIO-supply = <®_1p8v>;
+ clocks = <&sys_mclk>;
+ sclk-strength = <3>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x02>;
+
+ current-monitor@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <500>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@4c {
+ compatible = "nxp,sa56004";
+ reg = <0x4c>;
+ vcc-supply = <&sb_3v3>;
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+ };
+ };
};
&mscc_felix {
&mscc_felix_port0 {
label = "swp0";
- phy-handle = <&sw_phy0>;
+ managed = "in-band-status";
+ phy-handle = <&qsgmii_phy0>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port1 {
label = "swp1";
- phy-handle = <&sw_phy1>;
+ managed = "in-band-status";
+ phy-handle = <&qsgmii_phy1>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port2 {
label = "swp2";
- phy-handle = <&sw_phy2>;
+ managed = "in-band-status";
+ phy-handle = <&qsgmii_phy2>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port3 {
label = "swp3";
- phy-handle = <&sw_phy3>;
+ managed = "in-band-status";
+ phy-handle = <&qsgmii_phy3>;
phy-mode = "qsgmii";
status = "okay";
};
status = "okay";
};
-&enetc_mdio_pf3 {
+&optee {
status = "okay";
- rdb_phy0: phy@2 {
- reg = <2>;
- };
+};
- /* VSC8514 QSGMII PHY */
- sw_phy0: phy@10 {
- reg = <0x10>;
- };
+&sai4 {
+ status = "okay";
+};
- sw_phy1: phy@11 {
- reg = <0x11>;
- };
+&sata {
+ status = "okay";
+};
- sw_phy2: phy@12 {
- reg = <0x12>;
- };
+&usb0 {
+ status = "okay";
+};
- sw_phy3: phy@13 {
- reg = <0x13>;
- };
+&usb1 {
+ dr_mode = "otg";
+ status = "okay";
};
reg = <0x3>;
rtc@51 {
- compatible = "pcf2127-rtc";
+ compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
reg = <0x3>;
rtc@51 {
- compatible = "pcf2127-rtc";
+ compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Travese Ten64 (LS1088) board
+ * Based on fsl-ls1088a-rdb.dts
+ * Copyright 2017-2020 NXP
+ * Copyright 2019-2021 Traverse Technologies
+ *
+ * Author: Mathew McBride <matt@traverse.com.au>
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Traverse Ten64";
+ compatible = "traverse,ten64", "fsl,ls1088a";
+
+ aliases {
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+
+ /* Fired by system controller when
+ * external power off (e.g ATX Power Button)
+ * asserted
+ */
+ powerdn {
+ label = "External Power Down";
+ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_POWER>;
+ };
+
+ /* Rear Panel 'ADMIN' button (GPIO_H) */
+ admin {
+ label = "ADMIN button";
+ gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
+ interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sfp1down {
+ label = "ten64:green:sfp1:down";
+ gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp2up {
+ label = "ten64:green:sfp2:up";
+ gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ admin {
+ label = "ten64:admin";
+ gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sfp_xg0: dpmac2-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfplower_i2c>;
+ tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp_xg1: dpmac1-sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfpupper_i2c>;
+ tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+/* XG1 - Upper SFP */
+&dpmac1 {
+ sfp = <&sfp_xg1>;
+ phy-connection-type = "10gbase-r";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+/* XG0 - Lower SFP */
+&dpmac2 {
+ sfp = <&sfp_xg0>;
+ phy-connection-type = "10gbase-r";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+/* DPMAC3..6 is GE4 to GE8 */
+&dpmac3 {
+ phy-handle = <&mdio1_phy5>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&dpmac4 {
+ phy-handle = <&mdio1_phy6>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&dpmac5 {
+ phy-handle = <&mdio1_phy7>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&dpmac6 {
+ phy-handle = <&mdio1_phy8>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+/* DPMAC7..10 is GE0 to GE3 */
+&dpmac7 {
+ phy-handle = <&mdio1_phy1>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&dpmac8 {
+ phy-handle = <&mdio1_phy2>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&dpmac9 {
+ phy-handle = <&mdio1_phy3>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&dpmac10 {
+ phy-handle = <&mdio1_phy4>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&emdio1 {
+ status = "okay";
+
+ mdio1_phy5: ethernet-phy@c {
+ reg = <0xc>;
+ };
+
+ mdio1_phy6: ethernet-phy@d {
+ reg = <0xd>;
+ };
+
+ mdio1_phy7: ethernet-phy@e {
+ reg = <0xe>;
+ };
+
+ mdio1_phy8: ethernet-phy@f {
+ reg = <0xf>;
+ };
+
+ mdio1_phy1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ mdio1_phy2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ mdio1_phy3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ mdio1_phy4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+&esdhc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ sfpgpio: gpio@76 {
+ compatible = "ti,tca9539";
+ reg = <0x76>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ admin_led_lower {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ at97sc: tpm@29 {
+ compatible = "atmel,at97sc3204t";
+ reg = <0x29>;
+ };
+
+ uc: board-controller@7e {
+ compatible = "traverse,ten64-controller";
+ reg = <0x7e>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ rx8035: rtc@32 {
+ compatible = "epson,rx8035";
+ reg = <0x32>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9540";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ sfpupper_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ sfplower_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+
+ en25s64: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "bl3";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "mcfirmware";
+ reg = <0x300000 0x200000>;
+ };
+
+ partition@500000 {
+ label = "ubootenv";
+ reg = <0x500000 0x80000>;
+ };
+
+ partition@580000 {
+ label = "dpl";
+ reg = <0x580000 0x40000>;
+ };
+
+ partition@5C0000 {
+ label = "dpc";
+ reg = <0x5C0000 0x40000>;
+ };
+
+ partition@600000 {
+ label = "devicetree";
+ reg = <0x600000 0x40000>;
+ };
+ };
+ };
+
+ nand: flash@1 {
+ compatible = "spi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* reserved for future boot direct from NAND flash
+ * (this would use the same layout as the 8MiB NOR flash)
+ */
+ partition@0 {
+ label = "nand-boot-reserved";
+ reg = <0 0x800000>;
+ };
+
+ /* recovery / install environment */
+ partition@800000 {
+ label = "recovery";
+ reg = <0x800000 0x2000000>;
+ };
+
+ /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
+ partition@2800000 {
+ label = "ubia";
+ reg = <0x2800000 0x6C00000>;
+ };
+
+ /* ubib (second OpenWrt) */
+ partition@9400000 {
+ label = "ubib";
+ reg = <0x9400000 0x6C00000>;
+ };
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
reg = <0x3>;
rtc@51 {
- compatible = "pcf2127-rtc";
+ compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
status = "okay";
rtc@51 {
- compatible = "pcf2127-rtc";
+ compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
enable-active-high;
regulator-boot-on;
};
+
+ reg_usb_5v: regulator-usb-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&mac0 {
spi-max-frequency = <40000000>;
reg = <0>;
- partition@0 {
- label = "SPL (spi)";
- reg = <0x0 0x10000>;
- read-only;
- };
- partition@1 {
- label = "u-boot (spi)";
- reg = <0x10000 0x70000>;
- read-only;
- };
- partition@2 {
- label = "uboot-env (spi)";
- reg = <0x80000 0x20000>;
- };
- partition@3 {
- label = "kernel (spi)";
- reg = <0x100000 0x400000>;
- };
- partition@4 {
- label = "swupdate (spi)";
- reg = <0x50000 0x800000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "SPL";
+ reg = <0x0 0x10000>;
+ read-only;
+ };
+ partition@10000 {
+ label = "u-boot";
+ reg = <0x10000 0x70000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "uboot-env1";
+ reg = <0x80000 0x10000>;
+ };
+ partition@90000 {
+ label = "uboot-env2";
+ reg = <0x90000 0x10000>;
+ };
+ partition@A0000 {
+ label = "rescue";
+ reg = <0xA0000 0xF40000>;
+ };
+ partition@FE0000 {
+ label = "spl-boot-data1";
+ reg = <0xFE0000 0x10000>;
+ };
+ partition@FF0000 {
+ label = "spl-boot-data2";
+ reg = <0xFF0000 0x10000>;
+ };
};
};
};
+
+&usb0 {
+ vbus-supply = <®_usb_5v>;
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
/dts-v1/;
#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
#include "imx6qdl-dhcom-pdk2.dtsi"
/ {
-// SPDX-License-Identifier: (GPL-2.0+)
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2015-2019 DH electronics GmbH
+ * Copyright (C) 2015-2021 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
+ * DHCOM PCB number: 493-300 or newer
+ * PDK2 PCB number: 516-400 or newer
*/
-
/dts-v1/;
#include "imx6q.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
#include "imx6qdl-dhcom-pdk2.dtsi"
/ {
- model = "Freescale i.MX6 Quad/Dual DHCOM Premium Developer Kit (2)";
- compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom", "fsl,imx6q";
+ model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)";
+ compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som",
+ "fsl,imx6q";
};
&sata {
status = "okay";
};
-
};
&fec {
- phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <10>;
-// SPDX-License-Identifier: (GPL-2.0+)
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2015-2019 DH electronics GmbH
+ * Copyright (C) 2015-2021 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*/
-#include "imx6qdl-dhcom.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
/ {
chosen {
- stdout-path = &uart1;
+ stdout-path = "serial0:115200n8";
};
clk_ext_audio_codec: clock-codec {
- compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
+ compatible = "fixed-clock";
+ };
+
+ display_bl: display-bl {
+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+ compatible = "pwm-backlight";
+ default-brightness-level = <8>;
+ enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
+ pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
+ status = "okay";
+ };
+
+ lcd_display: disp0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "rgb24";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ gpio-keys {
+ #size-cells = <0>;
+ compatible = "gpio-keys";
+
+ button-0 {
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
+ label = "TA1-GPIO-A";
+ linux,code = <KEY_A>;
+ pinctrl-0 = <&pinctrl_dhcom_a>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-1 {
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
+ label = "TA2-GPIO-B";
+ linux,code = <KEY_B>;
+ pinctrl-0 = <&pinctrl_dhcom_b>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-2 {
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
+ label = "TA3-GPIO-C";
+ linux,code = <KEY_C>;
+ pinctrl-0 = <&pinctrl_dhcom_c>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+
+ button-3 {
+ gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
+ label = "TA4-GPIO-D";
+ linux,code = <KEY_D>;
+ pinctrl-0 = <&pinctrl_dhcom_d>;
+ pinctrl-names = "default";
+ wakeup-source;
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+
+ /*
+ * Disable led-5, because GPIO E is
+ * already used as touch interrupt.
+ */
+ led-5 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
+ pinctrl-0 = <&pinctrl_dhcom_e>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ led-6 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
+ pinctrl-0 = <&pinctrl_dhcom_f>;
+ pinctrl-names = "default";
+ };
+
+ led-7 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
+ pinctrl-0 = <&pinctrl_dhcom_h>;
+ pinctrl-names = "default";
+ };
+
+ led-8 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ pinctrl-0 = <&pinctrl_dhcom_i>;
+ pinctrl-names = "default";
+ };
+ };
+
+ panel {
+ backlight = <&display_bl>;
+ compatible = "edt,etm0700g0edh6";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
};
sound {
- compatible = "fsl,imx-audio-sgtl5000";
- model = "imx-sgtl5000";
- ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT";
- mux-int-port = <1>;
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx-sgtl5000";
mux-ext-port = <3>;
+ mux-int-port = <1>;
+ ssi-controller = <&ssi1>;
};
};
&audmux {
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_ext>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "disabled";
+};
+
+/* 1G ethernet */
+/delete-node/ ðphy0;
+&fec {
+ phy-mode = "rgmii";
+ phy-handle = <ðphy7>;
+ pinctrl-0 = <&pinctrl_enet_1G>;
+ pinctrl-names = "default";
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy7: ethernet-phy@7 { /* KSZ 9021 */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ethphy7>;
+ pinctrl-names = "default";
+ reg = <7>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+ rxc-skew-ps = <3000>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ rxdv-skew-ps = <0>;
+ txc-skew-ps = <3000>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ };
+ };
};
&hdmi {
&i2c2 {
sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>;
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
VDDA-supply = <®_3p3v>;
- VDDIO-supply = <®_3p3v>;
+ VDDIO-supply = <&sw2_reg>;
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+ pinctrl-0 = <&pinctrl_dhcom_e>;
+ pinctrl-names = "default";
+ reg = <0x38>;
};
};
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
- pinctrl_hog: hog-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0
- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0
- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0
- MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0
- MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0
- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0
- MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0
- MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0
- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0
- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0
+&pcie {
+ pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
+ reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&usdhc2 { /* SD card */
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <
+ /*
+ * The following DHCOM GPIOs are used on this board.
+ * Therefore, they have been removed from the list below.
+ * A: key TA1
+ * B: key TA2
+ * C: key TA3
+ * D: key TA4
+ * E: touchscreen
+ * F: led6
+ * G: backlight enable
+ * H: led7
+ * I: led8
+ * J: PCIe reset
+ */
+ &pinctrl_hog_base
+ &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+ &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
>;
- };
+ pinctrl-names = "default";
pinctrl_audmux_ext: audmux-ext-grp {
fsl,pins = <
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
>;
};
pinctrl_enet_1G: enet-1G-grp {
fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1
- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
>;
};
- pinctrl_pcie: pcie-grp {
+ pinctrl_ethphy7: ethphy7-grp {
fsl,pins = <
- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
>;
};
-};
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&ssi1 {
- status = "okay";
-};
-
-&usdhc3 {
- status = "okay";
+ pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
+ >;
+ };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2021 DH electronics GmbH
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc4;
+ mmc3 = &usdhc1;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ serial0 = &uart1;
+ serial1 = &uart5;
+ serial2 = &uart4;
+ serial3 = &uart2;
+ serial4 = &uart3;
+ };
+
+ memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ reg_3p3v: regulator-3P3V {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "3P3V";
+ };
+
+ reg_eth_vio: regulator-eth-vio {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 7 0>;
+ pinctrl-0 = <&pinctrl_enet_vio>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_vio";
+ vin-supply = <&sw2_reg>;
+ };
+
+ /* OE pin of the latch is low active */
+ reg_latch_oe_on: regulator-latch-oe-on {
+ compatible = "regulator-fixed";
+ gpio = <&gpio3 22 0>;
+ regulator-always-on;
+ regulator-name = "latch_oe_on";
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 31 0>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "usb_h1_vbus";
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "usb_otg_vbus";
+ };
+};
+
+&can1 {
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/*
+ * Special SoM hardware required which uses the pins from micro SD card. The
+ * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
+ * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on
+ * the board device tree file, the micro SD card must be disabled and the uart1
+ * rts/cts must be disabled or output on other DHCOM pins.
+ */
+&can2 {
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 { /* S25FL116K */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&fec {
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ pinctrl-0 = <&pinctrl_enet_100M>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio4>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ethphy0>;
+ pinctrl-names = "default";
+ reg = <0>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
+ "", "", "", "", "", "", "", "",
+ "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "DHCOM-G", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
+ "DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
+ "", "", "", "", "DHCOM-F", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
+ "", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio7 {
+ gpio-line-names =
+ "DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
+ "", "", "", "", "", "DHCOM-P", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ /*
+ * Info: According to erratum ERR007805 clock frequency limit is 375000.
+ * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
+ * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
+ * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c2 {
+ /* Info: Clock frequency limit is 375000 (for details see i2c1) */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ /* Info: Clock frequency limit is 375000 (for details see i2c1) */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ ltc3676: pmic@3c {
+ compatible = "lltc,ltc3676";
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ pinctrl-names = "default";
+ reg = <0x3c>;
+
+ regulators {
+ sw1_reg: sw1 {
+ lltc,fb-voltage-divider = <100000 110000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1527272>;
+ regulator-min-microvolt = <787500>;
+ regulator-ramp-delay = <7000>;
+ regulator-suspend-mem-microvolt = <1040000>;
+ };
+
+ sw2_reg: sw2 {
+ lltc,fb-voltage-divider = <100000 28000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3657142>;
+ regulator-min-microvolt = <1885714>;
+ regulator-ramp-delay = <7000>;
+ };
+
+ sw3_reg: sw3 {
+ lltc,fb-voltage-divider = <100000 110000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1527272>;
+ regulator-min-microvolt = <787500>;
+ regulator-ramp-delay = <7000>;
+ regulator-suspend-mem-microvolt = <980000>;
+ };
+
+ sw4_reg: sw4 {
+ lltc,fb-voltage-divider = <100000 93100>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1659291>;
+ regulator-min-microvolt = <855571>;
+ regulator-ramp-delay = <7000>;
+ };
+
+ ldo1_reg: ldo1 {
+ lltc,fb-voltage-divider = <102000 29400>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3240306>;
+ regulator-min-microvolt = <3240306>;
+ };
+
+ ldo2_reg: ldo2 {
+ lltc,fb-voltage-divider = <100000 41200>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2484708>;
+ regulator-min-microvolt = <2484708>;
+ };
+ };
+ };
+
+ touchscreen@49 { /* TSC2004 */
+ compatible = "ti,tsc2004";
+ interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&pinctrl_tsc2004>;
+ pinctrl-names = "default";
+ reg = <0x49>;
+ vio-supply = <®_3p3v>;
+ status = "disabled";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+
+ rtc_i2c: rtc@56 {
+ compatible = "microcrystal,rv3029";
+ interrupt-parent = <&gpio7>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&pinctrl_rtc>;
+ pinctrl-names = "default";
+ reg = <0x56>;
+ };
+};
+
+&pcie {
+ pinctrl-0 = <&pinctrl_pcie>;
+ pinctrl-names = "default";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pinctrl_pwm1>;
+ pinctrl-names = "default";
+};
+
+®_arm {
+ vin-supply = <&sw3_reg>;
+};
+
+®_pu {
+ vin-supply = <&sw1_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1_reg>;
+};
+
+®_vdd1p1 {
+ vin-supply = <&sw2_reg>;
+};
+
+®_vdd2p5 {
+ vin-supply = <&sw2_reg>;
+};
+
+&uart1 { /* DHCOM UART1 */
+ dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 { /* DHCOM UART3 */
+ pinctrl-0 = <&pinctrl_uart4>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart5 { /* DHCOM UART2 */
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ dr_mode = "host";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ pinctrl-names = "default";
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ disable-over-current;
+ dr_mode = "otg";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ pinctrl-names = "default";
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usdhc2 { /* External SD card via DHCOM */
+ cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&usdhc3 { /* Micro SD card on module */
+ cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+ fsl,wp-controller;
+ keep-power-in-suspend;
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usdhc4 { /* eMMC on module */
+ bus-width = <8>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&weim {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ fsl,weim-cs-gpr = <&gpr>;
+ pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
+ pinctrl-names = "default";
+ /* It is necessary to setup 2x 64MB otherwise setting gpr fails */
+ ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
+ <1 0 0x0c000000 0x04000000>; /* CS1 */
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl-0 = <
+ &pinctrl_hog_base
+ &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+ &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+ &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+ >;
+ pinctrl-names = "default";
+
+ pinctrl_hog_base: hog-base-grp {
+ fsl,pins = <
+ /* GPIOs for memory coding */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
+ /* GPIOs for hardware coding */
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
+ >;
+ };
+
+ /* DHCOM GPIOs */
+ pinctrl_dhcom_a: dhcom-a-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>;
+ };
+
+ pinctrl_dhcom_b: dhcom-b-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>;
+ };
+
+ pinctrl_dhcom_c: dhcom-c-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>;
+ };
+
+ pinctrl_dhcom_d: dhcom-d-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>;
+ };
+
+ pinctrl_dhcom_e: dhcom-e-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>;
+ };
+
+ pinctrl_dhcom_f: dhcom-f-grp {
+ fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
+ };
+
+ pinctrl_dhcom_g: dhcom-g-grp {
+ fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>;
+ };
+
+ pinctrl_dhcom_h: dhcom-h-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>;
+ };
+
+ pinctrl_dhcom_i: dhcom-i-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>;
+ };
+
+ pinctrl_dhcom_j: dhcom-j-grp {
+ fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>;
+ };
+
+ pinctrl_dhcom_k: dhcom-k-grp {
+ fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>;
+ };
+
+ pinctrl_dhcom_l: dhcom-l-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>;
+ };
+
+ pinctrl_dhcom_m: dhcom-m-grp {
+ fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>;
+ };
+
+ pinctrl_dhcom_n: dhcom-n-grp {
+ fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>;
+ };
+
+ pinctrl_dhcom_o: dhcom-o-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;
+ };
+
+ pinctrl_dhcom_p: dhcom-p-grp {
+ fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>;
+ };
+
+ pinctrl_dhcom_q: dhcom-q-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>;
+ };
+
+ pinctrl_dhcom_r: dhcom-r-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>;
+ };
+
+ pinctrl_dhcom_s: dhcom-s-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>;
+ };
+
+ pinctrl_dhcom_t: dhcom-t-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>;
+ };
+
+ pinctrl_dhcom_u: dhcom-u-grp {
+ fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>;
+ };
+
+ pinctrl_dhcom_v: dhcom-v-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>;
+ };
+
+ pinctrl_dhcom_w: dhcom-w-grp {
+ fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>;
+ };
+
+ pinctrl_dhcom_int: dhcom-int-grp {
+ fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>;
+ };
+
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet_100M: enet-100M-grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
+ };
+
+ pinctrl_enet_vio: enet-vio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
+ >;
+ };
+
+ pinctrl_ethphy0: ethphy0-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pcie-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
+ >;
+ };
+
+ pinctrl_pmic: pmic-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_rtc: rtc-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0
+ >;
+ };
+
+ pinctrl_tsc2004: tsc2004-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
+ MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
+ >;
+ };
+
+ pinctrl_usbh1: usbh1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotg-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_weim: weim-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
+ MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */
+ >;
+ };
+
+ pinctrl_weim_cs0: weim-cs0-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_cs1: weim-cs1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
+ >;
+ };
+};
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
- regulator-1p1 {
+ reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
-#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_H */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Foundries.io
+ */
+
+&iomuxc1 {
+ u-boot,dm-spl;
+};
+
+&ahbbridge0 {
+ u-boot,dm-spl;
+};
+
+&ahbbridge1 {
+ u-boot,dm-spl;
+};
+
+&lpuart4 {
+ u-boot,dm-spl;
+};
+
+&usbotg1 {
+ extcon = <&usbphy1>;
+ u-boot,dm-spl;
+};
+
+&usbphy1 {
+ u-boot,dm-spl;
+};
+
+&usdhc0 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
/dts-v1/;
#include "imx7ulp.dtsi"
+#include "imx7ulp-com-u-boot.dtsi"
/ {
model = "Embedded Artists i.MX7ULP COM";
enable-active-high;
};
+ reg_usbotg1: regulator-usbotg1 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_otg1>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
- clock-names = "xclk";
DCVDD-supply = <®_audio>;
DBVDD-supply = <®_audio>;
AVDD-supply = <®_audio>;
status = "okay";
};
+&usbotg1 {
+ vbus-supply = <®_usbotg1>;
+ disable-over-current;
+ dr_mode="otg";
+ status = "okay";
+};
+
+&usbotg2 {
+ pinctrl-names = "default";
+ disable-over-current;
+ dr_mode="host";
+ status = "okay";
+};
+
+&usbphynop2 {
+ reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
+};
+
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>;
};
+ pinctrl_reg_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
+ >;
+ };
+
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
u-boot,dm-spl;
};
+&usbotg1 {
+ dr_mode="host";
+};
+
&usdhc2 {
u-boot,dm-spl;
};
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
- spi-tx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
non-removable;
cap-power-off-card;
- pm-ignore-notify;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc1_pwrseq>;
status = "okay";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_adc";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2400000>;
+ regulator-always-on;
+ };
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc0: adc@0 {
+ compatible = "maxim,max11108";
+ reg = <0>;
+ vref-supply = <&vref_adc>;
+ spi-max-frequency = <20000000>;
+ status = "okay";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_adc";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2400000>;
+ regulator-always-on;
+ };
+};
+
+&ecspi3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc1: adc@0 {
+ compatible = "maxim,max11108";
+ reg = <0>;
+ vref-supply = <&vref_adc>;
+ spi-max-frequency = <20000000>;
+ status = "okay";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clk40m: clk@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ clock-output-names = "clk40m";
+ };
+ };
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ can0: can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ microchip,rx-int = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <20000000>;
+ clocks = <&clk40m>;
+ status = "okay";
+ };
+};
+
+&iomuxc {
+ pinctrl_can0: can0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x00
+ MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clk40m: clk@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ clock-output-names = "clk40m";
+ };
+ };
+};
+
+&ecspi3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ can1: can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ microchip,rx-int = <&gpio5 28 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <20000000>;
+ clocks = <&clk40m>;
+ status = "okay";
+ };
+};
+
+&iomuxc {
+ pinctrl_can1: can1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x00
+ MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x00
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+ regulatot-tpm0-rst {
+ compatible = "regulator-fixed";
+ regulator-name = "tpm0-rst";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ enable-active-high;
+ };
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm0: tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm0>;
+ spi-max-frequency = <5000000>;
+ status = "okay";
+ };
+};
+
+&iomuxc {
+ pinctrl_tpm0: tpm0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x0
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+ regulator-tpm1-rst {
+ compatible = "regulator-fixed";
+ regulator-name = "tpm1-rst";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ enable-active-high;
+ };
+};
+
+&ecspi3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm1: tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm1>;
+ spi-max-frequency = <5000000>;
+ status = "disabled";
+ };
+};
+
+&iomuxc {
+ pinctrl_tpm1: tpm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x0
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,spi-num-chipselects = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,spi-num-chipselects = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&ecspi3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,spi-num-chipselects = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1cs {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x02
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x02
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x102
+ >;
+ };
+
+ pinctrl_ecspi2_cs: ecspi2_csgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x02
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x02
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x102
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3_csgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-n801x-u-boot.dtsi"
* Copyright (C) 2019 Kontron Electronics GmbH
*/
-#include "imx8mm-u-boot.dtsi"
-
-/ {
- aliases {
- usb0 = &usbotg1;
- usb1 = &usbotg2;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdog1>;
- u-boot,dm-spl;
- };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-};
-
-&fec1 {
- phy-mode = "rgmii-rxid";
-};
-
-&i2c1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&i2c2 {
- status = "okay";
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_ecspi1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_pmic {
- u-boot,dm-spl;
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
- /* Disable Pullup for SD_VSEL */
- MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
- >;
-};
-
-&pinctrl_uart3 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_usdhc1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc1_100mhz {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc1_200mhz {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
- u-boot,dm-spl;
-};
-
-&pca9450 {
- u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
- u-boot,dm-spl;
-};
-
-&ecspi1 {
- u-boot,dm-spl;
-};
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart3 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&usdhc1 {
- u-boot,dm-spl;
-};
-
-&usdhc2 {
- u-boot,dm-spl;
-};
-
-&wdog1 {
- u-boot,dm-spl;
-};
+#include "imx8mm-kontron-n801x-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&fec1 {
+ phy-mode = "rgmii-rxid";
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&i2c2 {
+ status = "okay";
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ecspi1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ /* Disable Pullup for SD_VSEL */
+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
+ >;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pca9450 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&ecspi1 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
-#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
type = "blob-ext";
};
- 1d_dmem {
+ 1d-dmem {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
- 2d_imem {
+ 2d-imem {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 2d_dmem {
+ 2d-dmem {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
- uboot_blob {
+ uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
load = <0x920000>;
type = "firmware";
- atf_blob {
+ atf-blob {
filename = "bl31.bin";
type = "blob-ext";
};
description = "NAME";
type = "flat_dt";
- uboot_fdt_blob {
+ uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* M2_RST# */
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
};
gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
reg = <0x32e50200 0x200>;
};
+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx8mm-pcie-phy";
+ reg = <0x32f00000 0x10000>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ clock-names = "ref";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ assigned-clock-rates = <100000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY>;
+ reset-names = "pciephy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
dma_apbh: dma-controller@33000000 {
status = "disabled";
};
+ pcie0: pcie@33800000 {
+ compatible = "fsl,imx8mm-pcie";
+ reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ linux,pci-domain = <0>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ status = "disabled";
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
};
};
};
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x58000>;
+ filename = "u-boot.itb";
+ };
+ };
};
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
fsl,magic-packet;
status = "okay";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&aips1 {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&aips4 {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&osc_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart4 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
+&uart4 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "ddr4_imem_1d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = "ddr4_dmem_1d.bin";
+ size = <0x4000>;
+ type = "blob-ext";
+ };
+
+ 2d_imem {
+ filename = "ddr4_imem_2d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 2d_dmem {
+ filename = "ddr4_dmem_2d.bin";
+ size = <0x4000>;
+ type = "blob-ext";
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_SYS_TEXT_BASE>;
+ type = "standalone";
+
+ uboot_blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
+ };
+
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x960000>;
+ load = <0x960000>;
+ type = "firmware";
+
+ atf_blob {
+ filename = "bl31.bin";
+ type = "blob-ext";
+ };
+ };
+
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
+
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
+
+ uboot_fdt_blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ binman_configuration: @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
+ loadables = "atf";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl {
+ filename = "spl.bin";
+ offset = <0x0>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.itb";
+ offset = <0x58000>;
+ type = "blob-ext";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019-2020 Variscite Ltd.
+ * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "imx8mn-var-som.dtsi"
+
+/ {
+ model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
+ compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ back {
+ label = "Back";
+ gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BACK>;
+ };
+
+ home {
+ label = "Home";
+ gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ };
+
+ menu {
+ label = "Menu";
+ gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MENU>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led {
+ label = "Heartbeat";
+ gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+ðphy {
+ reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pca9534: gpio@20 {
+ compatible = "nxp,pca9534";
+ reg = <0x20>;
+ gpio-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9534>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ #gpio-cells = <2>;
+ wakeup-source;
+
+ /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
+ usb3-sata-sel-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "usb3_sata_sel";
+ };
+
+ som-vselect-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "som_vselect";
+ };
+
+ enet-sel-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "enet_sel";
+ };
+ };
+
+ extcon_usbotg1: typec@3d {
+ compatible = "nxp,ptn5150";
+ reg = <0x3d>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ptn5150>;
+ status = "okay";
+ };
+};
+
+&i2c3 {
+ /* Capacitive touch controller */
+ ft5x06_ts: touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_captouch>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+};
+
+/* Header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* Header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ disable-over-current;
+ extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
+};
+
+&pinctrl_fec1 {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
+ >;
+};
+
+&pinctrl_fec1_sleep {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
+ MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
+ MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
+ MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
+ MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
+ MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
+ MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
+ MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
+ MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
+ MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
+ MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
+ MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
+ MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
+ MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
+ /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
+ >;
+};
+
+&iomuxc {
+ pinctrl_captouch: captouchgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pca9534: pca9534grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
+ >;
+ };
+
+ pinctrl_ptn5150: ptn5150grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2019-2020 Variscite Ltd.
+ * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "Variscite VAR-SOM-MX8MN module";
+ compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x40000000>;
+ };
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eth_phy>;
+ regulator-name = "eth_phy_pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
+ <&gpio1 0 GPIO_ACTIVE_LOW>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+ status = "okay";
+
+ /* Resistive touch controller */
+ touchscreen@0 {
+ reg = <0>;
+ compatible = "ti,ads7846";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_restouch>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+
+ spi-max-frequency = <1500000>;
+ pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+ ti,x-min = /bits/ 16 <125>;
+ touchscreen-size-x = /bits/ 16 <4008>;
+ ti,y-min = /bits/ 16 <282>;
+ touchscreen-size-y = /bits/ 16 <3864>;
+ ti,x-plate-ohms = /bits/ 16 <180>;
+ touchscreen-max-pressure = /bits/ 16 <255>;
+ touchscreen-average-samples = /bits/ 16 <10>;
+ ti,debounce-tol = /bits/ 16 <3>;
+ ti,debounce-rep = /bits/ 16 <1>;
+ ti,settle-delay-usec = /bits/ 16 <150>;
+ ti,keep-vref-on;
+ wakeup-source;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-1 = <&pinctrl_fec1_sleep>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy>;
+ phy-supply = <®_eth_phy>;
+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-compatible = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ /* TODO: configure audio, as of now just put a placeholder */
+ wm8904: codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ status = "disabled";
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* Bluetooth */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MN_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* Console */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+/* WIFI */
+&usdhc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <4>;
+ non-removable;
+ keep-power-in-suspend;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD */
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
+ MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
+ MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
+ MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
+ MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_fec1_sleep: fec1sleepgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
+ MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
+ MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
+ MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
+ MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
+ MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
+ MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
+ MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
+ MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
+ MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
+ MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
+ MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
+ MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
+ MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
+ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicirqgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
+ >;
+ };
+
+ pinctrl_reg_eth_phy: regethphygrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
+ >;
+ };
+
+ pinctrl_restouch: restouchgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
+ MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
+ MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include "imx8mn-venice-u-boot.dtsi"
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+};
+
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7902 i.MX8MN board";
+ compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
+
+ aliases {
+ usb0 = &usbotg1;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ can20m: can20m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ clock-output-names = "can20m";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "panel1";
+ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "panel2";
+ gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "panel3";
+ gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "panel4";
+ gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "panel5";
+ gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb1_vbus: regulator-usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_usb1_vbus";
+ gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wifi";
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&can20m>;
+ oscillator-frequency = <20000000>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ gw,voltage-offset-microvolt = <700000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vin_4p0";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_0p9";
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_soc";
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_arm";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_1p8";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_dram";
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_1p0";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ /* vdd_soc: 0.805-0.900V (typ=0.8V) */
+ BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* vdd_arm: 0.805-1.0V (typ=0.9V) */
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
+ BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_3p3 */
+ BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_1p8 */
+ BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_dram */
+ BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* nvcc_snvs_1p8 */
+ LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_snvs_0p8 */
+ LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdda_1p8 */
+ LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+
+ secure-element@60 {
+ compatible = "nxp,se050";
+ reg = <0x60>;
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* off-board header */
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+/* off-board header */
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
+/* RS232/RS485/RS422 selectable */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
+ status = "okay";
+};
+
+/* RS232 console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* bluetooth HCI */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
+ rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ vbus-supply = <®_usb1_vbus>;
+ disable-over-current;
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wifi>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
+ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
+ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
+ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
+ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
+ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
+ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
+ MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
+ MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
+ MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
+ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
+ MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
+ MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
+ MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
+ MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
+ MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
+ MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
+ >;
+ };
+
+ pinctrl_reg_usb1: regusb1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
+ MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ >;
+ };
+
+ pinctrl_spi1: spi1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
+ MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
+ MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
+ MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
+ MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart1_gpio: uart1gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
+ MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
+ MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3_gpio: uart3_gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
+ MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ type = "blob-ext";
+ };
+
+ 2d_imem {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 2d_dmem {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ type = "blob-ext";
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_SYS_TEXT_BASE>;
+ type = "standalone";
+
+ uboot_blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
+ };
+
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x960000>;
+ load = <0x960000>;
+ type = "firmware";
+
+ atf_blob {
+ filename = "bl31.bin";
+ type = "blob-ext";
+ };
+ };
+
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
+
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
+
+ uboot_fdt_blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ binman_configuration: @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
+ loadables = "atf";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl {
+ filename = "spl.bin";
+ offset = <0x0>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.itb";
+ offset = <0x58000>;
+ type = "blob-ext";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "Gateworks Venice i.MX8MM board";
+ compatible = "gw,imx8mn-venice", "fsl,imx8mn";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Linaro
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&binman {
+ itb {
+ fit {
+ images {
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x40310000>;
+
+ fip_blob: blob-ext{
+ filename = "fip.bin";
+ };
+ };
+ };
+
+ configurations {
+ conf {
+ loadables = "atf", "fip";
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Linaro
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mp.dtsi"
+
+/ {
+ model = "Advantech i.MX8MPlus RSB3720A1 board";
+ compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
+
+ aliases {
+ rtc0 = &s35390a;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0xc0000000>,
+ <0x1 0x00000000 0 0xc0000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rpmsg_reserved: rpmsg@0x55800000 {
+ no-map;
+ reg = <0 0x55800000 0 0x800000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ user {
+ label = "user";
+ gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ default-state = "off"; /* LED BLUE */
+ };
+ };
+
+ reg_usb1_host_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_host_vbus";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usdhc1_vmmc: regulator-usdhc1 {
+ compatible = "regulator-fixed";
+ regulator-name = "WLAN_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ //gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+
+ lvds_backlight0: lvds_backlight@0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 5000000>;
+ status = "disabled";
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <80>;
+ };
+
+ lvds_backlight1: lvds_backlight@1 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 5000000>;
+ status = "disabled";
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <80>;
+ };
+
+ rtl8367 {
+ compatible = "realtek,rtl8367b";
+ pinctrl-names = "default";
+ gpio-sda = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+ gpio-sck = <&gpio5 11 GPIO_ACTIVE_HIGH>;
+ realtek,extif0 = <1 0 1 1 1 1 1 1 2>;
+ };
+};
+
+&clk {
+ init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pmic: pca9450@25 {
+ reg = <0x25>;
+ compatible = "nxp,pca9450c", "nxp,pca9450b", "nxp,pca9450";
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+ pinctrl-0 = <&pinctrl_pmic>;
+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "buck1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "buck2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "buck4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "buck5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "buck6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ s35390a: s35390a@30 {
+ compatible = "sii,s35390a", "sii,s35392a";
+ reg = <0x30>;
+ status = "okay";
+ };
+
+ gpio_exp2: tca9538@71 {
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio_exp1: tca9538@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ 24c02@50 {
+ compatible = "fsl,24c02";
+ reg = <0x50>;
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ fsl,phy-tx-vref-tune = <6>;
+ fsl,phy-tx-rise-tune = <0>;
+ fsl,phy-tx-preemp-amp-tune = <3>;
+ fsl,phy-comp-dis-tune = <7>;
+ fsl,pcs-tx-deemph-3p5db = <0x21>;
+ fsl,phy-pcs-tx-swing-full = <0x7f>;
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ fsl,phy-tx-preemp-amp-tune = <2>;
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ cqe-disabled;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
+ >;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
+ >;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4_gpio_grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
+ MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usb1_vbus: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ u-boot,dm-spl;
+ wdt = <&wdog1>;
+ };
+};
+
+&clk {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+
+};
+
+&eqos {
+ compatible = "fsl,imx-eqos";
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+ u-boot,off-on-delay-us = <20000>;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
+&pmic {
+ u-boot,dm-spl;
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+ assigned-clock-rates = <400000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+ assigned-clock-rates = <400000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mp.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Plus";
+ compatible = "toradex,verdin-imx8mp", "fsl,imx8mp";
+
+ aliases {
+ eeprom0 = &eeprom_module;
+ eeprom1 = &eeprom_carrier;
+ eeprom2 = &eeprom_mipi_dsi;
+ /* Ethernet aliases to ensure correct MAC addresses */
+ ethernet0 = &eqos;
+ ethernet1 = &fec;
+ };
+
+ chosen {
+ bootargs = "console=ttymxc2,115200 earlycon";
+ stdout-path = &uart3;
+ };
+
+ reg_usb1_host_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* USB_2_EN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus>;
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb1_host_vbus";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; /* SD_1_PWR_EN */
+ off-on-delay-us = <12000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "V3.3_SD";
+ startup-delay-us = <100>;
+ };
+};
+
+&eqos {
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&fec {
+ fsl,magic-packet;
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&gpio2 {
+ regulator-ethphy {
+ gpio-hog;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ line-name = "reg_ethphy";
+ output-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eth>;
+ };
+
+ ctrl_sleep_moci {
+ gpio-hog;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <29 GPIO_ACTIVE_HIGH>;
+ line-name = "CTRL_SLEEP_MOCI#";
+ output-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+ };
+};
+
+/* Verdin PMIC_I2C */
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pmic: pca9450@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+
+ regulators {
+ #address-cells = <1>;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ #size-cells = <0>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "buck1";
+ regulator-max-microvolt = <2187500>;
+ regulator-min-microvolt = <600000>;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2_reg: regulator@1 {
+ reg = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "buck2";
+ regulator-max-microvolt = <2187500>;
+ regulator-min-microvolt = <600000>;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4_reg: regulator@3 {
+ reg = <3>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "buck4";
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ };
+
+ buck5_reg: regulator@4 {
+ reg = <4>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "buck5";
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ };
+
+ buck6_reg: regulator@5 {
+ reg = <5>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "buck6";
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ };
+
+ ldo1_reg: regulator@6 {
+ reg = <6>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "ldo1";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1600000>;
+ };
+
+ ldo2_reg: regulator@7 {
+ reg = <7>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "ldo2";
+ regulator-max-microvolt = <1150000>;
+ regulator-min-microvolt = <800000>;
+ };
+
+ ldo3_reg: regulator@8 {
+ reg = <8>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "ldo3";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <800000>;
+ };
+
+ ldo4_reg: regulator@9 {
+ reg = <9>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-compatible = "ldo4";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <800000>;
+ };
+
+ ldo5_reg: regulator@10 { /* +V3.3_1.8_SD */
+ reg = <10>;
+ regulator-compatible = "ldo5";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ };
+ };
+ };
+
+ /* Epson RX8130 real time clock on carrier board */
+ rtc: rx8130@32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ eeprom_module: eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+};
+
+/* Verdin I2C2 DSI */
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* Verdin I2C4 CSI */
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x20>;
+ };
+};
+
+/* Verdin I2C1 */
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ /* EEPROM on MIPI-DSI to HDMI adapter */
+ eeprom_mipi_dsi: eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+
+ /* EEPROM on Verdin Development board */
+ eeprom_carrier: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
+ pagesize = <16>;
+ reg = <0x57>;
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* Verdin UART3 */
+&uart3 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ adp-disable;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* Verdin SDIO 1 */
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+/* On-module eMMC */
+&usdhc3 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ status = "okay";
+};
+
+&wdog1 {
+ fsl,ext-reset-output;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>,
+ <&pinctrl_gpio4>, <&pinctrl_gpio5>, <&pinctrl_gpio6>,
+ <&pinctrl_gpio7>, <&pinctrl_gpio8>;
+
+ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4 /* SODIMM 256 */
+ >;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ >;
+ };
+
+ /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184 /* SODIMM 206 */
+ >;
+ };
+
+ pinctrl_gpio2: gpio2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x184 /* SODIMM 208 */
+ >;
+ };
+
+ pinctrl_gpio3: gpio3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184 /* SODIMM 210 */
+ >;
+ };
+
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184 /* SODIMM 212 */
+ >;
+ };
+
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184 /* SODIMM 216 */
+ >;
+ };
+
+ pinctrl_gpio6: gpio6grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184 /* SODIMM 218 */
+ >;
+ };
+
+ pinctrl_gpio7: gpio7grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184 /* SODIMM 220 */
+ >;
+ };
+
+ pinctrl_gpio8: gpio8grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184 /* SODIMM 222 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
+ MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
+ >;
+ };
+
+ pinctrl_reg_eth: regethgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x41
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usb1_vbus: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&usdhc1 {
+ mmc-hs400-1_8v;
+};
+
+&usdhc2 {
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree File for the Kontron pitx-imx8m board.
+ *
+ * Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "Kontron pITX-imx8m";
+ compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ spi0 = &qspi0;
+ spi1 = &ecspi2;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ pcie0_refclk: pcie0-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pcie1_refclk: pcie1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2>;
+ regulator-name = "V_3V3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670";
+ reg = <0>;
+ spi-max-frequency = <43000000>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <280>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+ fsl,pfuze-support-disable-sw;
+ reg = <0x8>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-name = "V_0V9_GPU";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-name = "V_0V9_VPU";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-name = "V_1V1_NVCC_DRAM";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3ab {
+ regulator-name = "V_1V0_DRAM";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-name = "V_1V8_S0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-name = "NC";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-name = "V_0V9_SNVS";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-name = "V_0V55_VREF_DDR";
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-name = "V_1V5_CSI";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-name = "V_0V9_PHY";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <975000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-name = "V_1V8_PHY";
+ regulator-min-microvolt = <1675000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-name = "V_1V8_VDDA";
+ regulator-min-microvolt = <1625000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-name = "V_3V3_PHY";
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3625000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-name = "V_2V8_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ fan-controller@1b {
+ compatible = "maxim,max6650";
+ reg = <0x1b>;
+ maxim,fan-microvolt = <5000000>;
+ };
+
+ rtc@32 {
+ compatible = "microcrystal,rv8803";
+ reg = <0x32>;
+ };
+
+ sensor@4b {
+ compatible = "national,lm75b";
+ reg = <0x4b>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* M.2 B-key slot */
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ status = "okay";
+};
+
+/* Intel Ethernet Controller I210/I211 */
+&pcie1 {
+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&pcie1_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ fsl,max-link-speed = <1>;
+ status = "okay";
+};
+
+&pgc_gpu {
+ power-supply = <&sw1a_reg>;
+};
+
+&pgc_vpu {
+ power-supply = <&sw1c_reg>;
+};
+
+&qspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ maximum-speed = "high-speed";
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vqmmc-supply = <&sw4_reg>;
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
+ MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
+ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
+ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
+ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
+ MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
+ MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
+ >;
+ };
+
+ pinctrl_reg_usdhc2: regusdhc2gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
+ MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
+ MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
+ MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
+ MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
+ >;
+ };
+
+ pinctrl_ecspi2_cs: ecspi2csgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
+ MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
+ MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
+ MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usb0: usb0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
+ MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright 2019-2021 MNT Research GmbH
+ * Copyright 2021 Lucas Stach <dev@lynxeye.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mq-nitrogen-som.dtsi"
+
+/ {
+ model = "MNT Reform 2";
+ compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
+
+ pcie1_refclk: clock-pcie1-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ reg_main_5v: regulator-main-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_main_3v3: regulator-main-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_main_usb: regulator-main-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_main_5v>;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-wm8960";
+ audio-cpu = <&sai2>;
+ audio-codec = <&wm8960>;
+ audio-routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "Mic Jack", "MICB",
+ "LINPUT2", "Line In Jack",
+ "RINPUT2", "Line In Jack";
+ model = "wm8960-audio";
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ wm8960: codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ };
+
+ rtc@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie1>;
+ reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&pcie1_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ status = "okay";
+};
+
+®_1p8v {
+ vin-supply = <®_main_5v>;
+};
+
+®_snvs {
+ vin-supply = <®_main_5v>;
+};
+
+®_arm_dram {
+ vin-supply = <®_main_5v>;
+};
+
+®_dram_1p1v {
+ vin-supply = <®_main_5v>;
+};
+
+®_soc_gpu_vpu {
+ vin-supply = <®_main_5v>;
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ assigned-clock-rates = <25000000>;
+ fsl,sai-mclk-direction-output;
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
+&snvs_rtc {
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_main_usb>;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ vbus-supply = <®_main_usb>;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ vqmmc-supply = <®_main_3v3>;
+ vmmc-supply = <®_main_3v3>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Boundary Devices
+ * Copyright 2021 Lucas Stach <dev@lynxeye.de>
+ */
+
+#include "imx8mq.dtsi"
+
+/ {
+ model = "Boundary Devices i.MX8MQ Nitrogen8M";
+ compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ reg_1p8v: regulator-fixed-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_snvs: regulator-fixed-snvs {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SNVS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&{/opp-table/opp-800000000} {
+ opp-microvolt = <1000000>;
+};
+
+&{/opp-table/opp-1000000000} {
+ opp-microvolt = <1000000>;
+};
+
+&A53_0 {
+ cpu-supply = <®_arm_dram>;
+};
+
+&A53_1 {
+ cpu-supply = <®_arm_dram>;
+};
+
+&A53_2 {
+ cpu-supply = <®_arm_dram>;
+};
+
+&A53_3 {
+ cpu-supply = <®_arm_dram>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_pca9546>;
+ reg = <0x70>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c1a: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_arm_dram: regulator@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ regulator-name = "VDD_ARM_DRAM_1V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+ };
+
+ i2c1b: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_dram_1p1v: regulator@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ regulator-name = "NVCC_DRAM_1P1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+ };
+
+ i2c1c: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_soc_gpu_vpu: regulator@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ regulator-name = "VDD_SOC_GPU_VPU";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ };
+ };
+
+ i2c1d: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&pgc_gpu {
+ power-supply = <®_soc_gpu_vpu>;
+};
+
+&pgc_vpu {
+ power-supply = <®_soc_gpu_vpu>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vqmmc-supply = <®_1p8v>;
+ vmmc-supply = <®_snvs>;
+ bus-width = <8>;
+ non-removable;
+ no-mmc-hs400;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_pca9546: i2c1-pca9546grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
&binman {
u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
u-boot-spl {
align-end = <4>;
+ filename = "u-boot-spl.bin";
};
- blob_1: blob-ext@1 {
+ 1d-imem {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ 1d-dmem {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
- blob_3: blob-ext@3 {
+ 2d-imem {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_4: blob-ext@4 {
+ 2d-dmem {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
};
- signed_hdmi {
+ signed-hdmi {
filename = "signed_hdmi.bin";
- blob_5: blob-ext@5 {
+ signed-hdmi-imx8m {
filename = "signed_hdmi_imx8m.bin";
+ type = "blob-ext";
};
};
blob {
filename = "u-boot-spl-ddr.bin";
};
-
};
-
};
itb {
fit {
description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ #address-cells = <1>;
images {
uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
arch = "arm64";
compression = "none";
+ description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
+ type = "standalone";
- uboot_blob: blob-ext {
+ uboot-blob {
filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
};
};
atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
arch = "arm64";
compression = "none";
- load = <0x910000>;
+ description = "ARM Trusted Firmware";
entry = <0x910000>;
+ load = <0x910000>;
+ type = "firmware";
- atf_blob: blob-ext {
+ atf-blob {
filename = "bl31.bin";
+ type = "blob-ext";
};
};
fdt {
+ compression = "none";
description = "NAME";
type = "flat_dt";
- compression = "none";
- uboot_fdt_blob: blob-ext {
+ uboot-fdt-blob {
filename = "u-boot.dtb";
+ type = "blob-ext";
};
};
};
conf {
description = "NAME";
+ fdt = "fdt";
firmware = "uboot";
loadables = "atf";
- fdt = "fdt";
};
};
};
filename = "flash.bin";
pad-byte = <0x00>;
- spl: blob-ext@1 {
- offset = <0x0>;
+ spl {
filename = "spl.bin";
+ offset = <0x0>;
+ type = "blob-ext";
};
- uboot: blob-ext@2 {
- offset = <0x57c00>;
+ binman_uboot: uboot {
filename = "u-boot.itb";
+ offset = <0x57c00>;
+ type = "blob-ext";
};
};
};
#include "dt-bindings/input/input.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interconnect/imx8mq.h>
#include "imx8mq-pinfunc.h"
/ {
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
- usb0 = &usb_dwc3_0;
- usb1 = &usb_dwc3_1;
};
ckil: clock-ckil {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
};
psci {
};
soc@0 {
- compatible = "simple-bus";
+ compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
+ nvmem-cells = <&imx8mq_uid>;
+ nvmem-cell-names = "soc_unique_id";
bus@30000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ imx8mq_uid: soc-uid@410 {
+ reg = <0x4 0x8>;
+ };
+
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
+
+ fec_mac_address: mac-address@90 {
+ reg = <0x90 6>;
+ };
};
anatop: syscon@30360000 {
clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
<&clk IMX8MQ_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
<&clk IMX8MQ_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
<&clk IMX8MQ_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
reg = <0x30a00300 0x100>;
clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "phy_ref";
- assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
+ <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
+ <&clk IMX8MQ_VIDEO_PLL1>,
+ <&clk IMX8MQ_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
#phy-cells = <0>;
power-domains = <&pgc_mipi>;
status = "disabled";
status = "disabled";
};
+ mipi_csi1: csi@30a70000 {
+ compatible = "fsl,imx8mq-mipi-csi2";
+ reg = <0x30a70000 0x1000>;
+ clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
+ <&clk IMX8MQ_CLK_CSI1_ESC>,
+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
+ clock-names = "core", "esc", "ui";
+ assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MQ_CLK_CSI1_ESC>;
+ assigned-clock-rates = <266000000>, <333000000>, <66000000>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS2_PLL_1000M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>;
+ power-domains = <&pgc_mipi_csi1>;
+ resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
+ <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
+ <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
+ fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
+ interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
+ interconnect-names = "dram";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi1_mipi_ep: endpoint {
+ remote-endpoint = <&csi1_ep>;
+ };
+ };
+ };
+ };
+
+ csi1: csi@30a90000 {
+ compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
+ reg = <0x30a90000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
+ clock-names = "mclk";
+ status = "disabled";
+
+ port {
+ csi1_ep: endpoint {
+ remote-endpoint = <&csi1_mipi_ep>;
+ };
+ };
+ };
+
+ mipi_csi2: csi@30b60000 {
+ compatible = "fsl,imx8mq-mipi-csi2";
+ reg = <0x30b60000 0x1000>;
+ clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
+ <&clk IMX8MQ_CLK_CSI2_ESC>,
+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
+ clock-names = "core", "esc", "ui";
+ assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
+ <&clk IMX8MQ_CLK_CSI2_ESC>;
+ assigned-clock-rates = <266000000>, <333000000>, <66000000>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS2_PLL_1000M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>;
+ power-domains = <&pgc_mipi_csi2>;
+ resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
+ <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
+ <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
+ fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
+ interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
+ interconnect-names = "dram";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi2_mipi_ep: endpoint {
+ remote-endpoint = <&csi2_ep>;
+ };
+ };
+ };
+ };
+
+ csi2: csi@30b80000 {
+ compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
+ reg = <0x30b80000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
+ clock-names = "mclk";
+ status = "disabled";
+
+ port {
+ csi2_ep: endpoint {
+ remote-endpoint = <&csi2_mipi_ep>;
+ };
+ };
+ };
+
mu: mailbox@30aa0000 {
compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
reg = <0x30aa0000 0x10000>;
<&clk IMX8MQ_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
+ assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
+ <&clk IMX8MQ_CLK_ENET_TIMER>,
+ <&clk IMX8MQ_CLK_ENET_REF>,
+ <&clk IMX8MQ_CLK_ENET_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS2_PLL_125M>,
+ <&clk IMX8MQ_SYS2_PLL_50M>;
+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ nvmem-cells = <&fec_mac_address>;
+ nvmem-cell-names = "mac-address";
+ nvmem_macaddr_swap;
+ fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
status = "disabled";
};
};
+ noc: interconnect@32700000 {
+ compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
+ reg = <0x32700000 0x100000>;
+ clocks = <&clk IMX8MQ_CLK_NOC>;
+ fsl,ddrc = <&ddrc>;
+ #interconnect-cells = <1>;
+ operating-points-v2 = <&noc_opp_table>;
+
+ noc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-133M {
+ opp-hz = /bits/ 64 <133333333>;
+ };
+
+ opp-400M {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+
+ opp-800M {
+ opp-hz = /bits/ 64 <800000000>;
+ };
+ };
+ };
+
bus@32c00000 { /* AIPS4 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
- 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
+ <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
- num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
+ linux,pci-domain = <0>;
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
- 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
+ <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
- num-viewport = <4>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
+ linux,pci-domain = <1>;
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
/*
* Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated with the
- * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.06.00
- * Mon Apr 26 2021 20:47:47 GMT-0500 (Central Daylight Time)
+ * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00
+ * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz
* Density (per channel): 16Gb
#define DDRSS_CTL_251_DATA 0x00000000
#define DDRSS_CTL_252_DATA 0x00000000
#define DDRSS_CTL_253_DATA 0x00000000
-#define DDRSS_CTL_254_DATA 0x66006666
-#define DDRSS_CTL_255_DATA 0x00002766
+#define DDRSS_CTL_254_DATA 0x46004646
+#define DDRSS_CTL_255_DATA 0x00002746
#define DDRSS_CTL_256_DATA 0x00000027
#define DDRSS_CTL_257_DATA 0x00000027
#define DDRSS_CTL_258_DATA 0x00000027
#define DDRSS_PI_220_DATA 0x000000A7
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
-#define DDRSS_PI_223_DATA 0x06000301
+#define DDRSS_PI_223_DATA 0x06000101
#define DDRSS_PI_224_DATA 0x001D0204
#define DDRSS_PI_225_DATA 0x32120059
-#define DDRSS_PI_226_DATA 0x05000301
+#define DDRSS_PI_226_DATA 0x05000101
#define DDRSS_PI_227_DATA 0x001D0409
#define DDRSS_PI_228_DATA 0x32120059
-#define DDRSS_PI_229_DATA 0x05000301
+#define DDRSS_PI_229_DATA 0x05000101
#define DDRSS_PI_230_DATA 0x00000409
#define DDRSS_PI_231_DATA 0x05030900
#define DDRSS_PI_232_DATA 0x00040900
#define DDRSS_PI_308_DATA 0x00000031
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
-#define DDRSS_PI_311_DATA 0x66000000
+#define DDRSS_PI_311_DATA 0x46000000
#define DDRSS_PI_312_DATA 0x00150F27
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
#define DDRSS_PI_316_DATA 0x00000031
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
-#define DDRSS_PI_319_DATA 0x66000000
+#define DDRSS_PI_319_DATA 0x46000000
#define DDRSS_PI_320_DATA 0x00150F27
#define DDRSS_PI_321_DATA 0x00000000
#define DDRSS_PI_322_DATA 0x00000004
#define DDRSS_PI_332_DATA 0x00000031
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
-#define DDRSS_PI_335_DATA 0x66000000
+#define DDRSS_PI_335_DATA 0x46000000
#define DDRSS_PI_336_DATA 0x00150F27
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
#define DDRSS_PI_340_DATA 0x00000031
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
-#define DDRSS_PI_343_DATA 0x66000000
+#define DDRSS_PI_343_DATA 0x46000000
#define DDRSS_PI_344_DATA 0x00150F27
#define DDRSS_PHY_0_DATA 0x04F00000
#define DDRSS_PHY_1_DATA 0x00000000
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
#define DDRSS_PHY_90_DATA 0x07AB0340
-#define DDRSS_PHY_91_DATA 0x0100C0C0
+#define DDRSS_PHY_91_DATA 0x0000C0C0
#define DDRSS_PHY_92_DATA 0x03040000
#define DDRSS_PHY_93_DATA 0x00000403
#define DDRSS_PHY_94_DATA 0x42100010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
#define DDRSS_PHY_346_DATA 0x07AB0340
-#define DDRSS_PHY_347_DATA 0x0100C0C0
+#define DDRSS_PHY_347_DATA 0x0000C0C0
#define DDRSS_PHY_348_DATA 0x03040000
#define DDRSS_PHY_349_DATA 0x00000403
#define DDRSS_PHY_350_DATA 0x42100010
#define DDRSS_PHY_1372_DATA 0x00000002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142
-#define DDRSS_PHY_1375_DATA 0x030207AB
+#define DDRSS_PHY_1375_DATA 0x03020000
#define DDRSS_PHY_1376_DATA 0x00000080
#define DDRSS_PHY_1377_DATA 0x03900390
#define DDRSS_PHY_1378_DATA 0x03900390
&serdes0 {
u-boot,dm-spl;
};
+
+&main_r5fss0 {
+ ti,cluster-mode = <0>;
+};
&usb_serdes_mux {
u-boot,mux-autoprobe;
};
+
+&serdes0 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&serdes0_pcie_link {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+};
+
+&serdes0_qsgmii_link {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+};
};
&serdes_ln_ctrl {
- idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
};
&serdes0 {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz0_pll1_refclk>;
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 2>;
+ };
};
&serdes1 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.1
+ * This file was generated on 07/19/2021
+*/
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
+
+#define DDRSS_CTL_00_DATA 0x00000B00
+#define DDRSS_CTL_01_DATA 0x00000000
+#define DDRSS_CTL_02_DATA 0x00000000
+#define DDRSS_CTL_03_DATA 0x00000000
+#define DDRSS_CTL_04_DATA 0x00000000
+#define DDRSS_CTL_05_DATA 0x00000000
+#define DDRSS_CTL_06_DATA 0x00000000
+#define DDRSS_CTL_07_DATA 0x00002AF8
+#define DDRSS_CTL_08_DATA 0x0001ADAF
+#define DDRSS_CTL_09_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x0000006E
+#define DDRSS_CTL_11_DATA 0x000681C8
+#define DDRSS_CTL_12_DATA 0x004111C9
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x000010A9
+#define DDRSS_CTL_15_DATA 0x000681C8
+#define DDRSS_CTL_16_DATA 0x004111C9
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x000010A9
+#define DDRSS_CTL_19_DATA 0x01010000
+#define DDRSS_CTL_20_DATA 0x02011001
+#define DDRSS_CTL_21_DATA 0x02010000
+#define DDRSS_CTL_22_DATA 0x00020100
+#define DDRSS_CTL_23_DATA 0x0000000B
+#define DDRSS_CTL_24_DATA 0x0000001C
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x03020200
+#define DDRSS_CTL_28_DATA 0x00005656
+#define DDRSS_CTL_29_DATA 0x00100000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x040C0000
+#define DDRSS_CTL_35_DATA 0x12481248
+#define DDRSS_CTL_36_DATA 0x00050804
+#define DDRSS_CTL_37_DATA 0x09040008
+#define DDRSS_CTL_38_DATA 0x15000204
+#define DDRSS_CTL_39_DATA 0x1B60008B
+#define DDRSS_CTL_40_DATA 0x1500422B
+#define DDRSS_CTL_41_DATA 0x1B60008B
+#define DDRSS_CTL_42_DATA 0x2000422B
+#define DDRSS_CTL_43_DATA 0x000A0A09
+#define DDRSS_CTL_44_DATA 0x0400078A
+#define DDRSS_CTL_45_DATA 0x1E161104
+#define DDRSS_CTL_46_DATA 0x10012458
+#define DDRSS_CTL_47_DATA 0x1E161110
+#define DDRSS_CTL_48_DATA 0x10012458
+#define DDRSS_CTL_49_DATA 0x02030410
+#define DDRSS_CTL_50_DATA 0x2C040500
+#define DDRSS_CTL_51_DATA 0x082D2C2D
+#define DDRSS_CTL_52_DATA 0x14000E0A
+#define DDRSS_CTL_53_DATA 0x04010A0A
+#define DDRSS_CTL_54_DATA 0x01010004
+#define DDRSS_CTL_55_DATA 0x04585808
+#define DDRSS_CTL_56_DATA 0x04313104
+#define DDRSS_CTL_57_DATA 0x00003131
+#define DDRSS_CTL_58_DATA 0x00010100
+#define DDRSS_CTL_59_DATA 0x03010000
+#define DDRSS_CTL_60_DATA 0x00001008
+#define DDRSS_CTL_61_DATA 0x000000CE
+#define DDRSS_CTL_62_DATA 0x00000256
+#define DDRSS_CTL_63_DATA 0x00002073
+#define DDRSS_CTL_64_DATA 0x00000256
+#define DDRSS_CTL_65_DATA 0x00002073
+#define DDRSS_CTL_66_DATA 0x00000005
+#define DDRSS_CTL_67_DATA 0x00040000
+#define DDRSS_CTL_68_DATA 0x00950012
+#define DDRSS_CTL_69_DATA 0x00950408
+#define DDRSS_CTL_70_DATA 0x00400408
+#define DDRSS_CTL_71_DATA 0x00120103
+#define DDRSS_CTL_72_DATA 0x00100005
+#define DDRSS_CTL_73_DATA 0x2F080010
+#define DDRSS_CTL_74_DATA 0x0505012F
+#define DDRSS_CTL_75_DATA 0x0401030A
+#define DDRSS_CTL_76_DATA 0x041E100B
+#define DDRSS_CTL_77_DATA 0x100B0401
+#define DDRSS_CTL_78_DATA 0x0001041E
+#define DDRSS_CTL_79_DATA 0x00100010
+#define DDRSS_CTL_80_DATA 0x02660266
+#define DDRSS_CTL_81_DATA 0x02660266
+#define DDRSS_CTL_82_DATA 0x03050505
+#define DDRSS_CTL_83_DATA 0x03010303
+#define DDRSS_CTL_84_DATA 0x200B100B
+#define DDRSS_CTL_85_DATA 0x04041004
+#define DDRSS_CTL_86_DATA 0x200B100B
+#define DDRSS_CTL_87_DATA 0x04041004
+#define DDRSS_CTL_88_DATA 0x03010000
+#define DDRSS_CTL_89_DATA 0x00010000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x01000000
+#define DDRSS_CTL_93_DATA 0x80104002
+#define DDRSS_CTL_94_DATA 0x00000000
+#define DDRSS_CTL_95_DATA 0x00040005
+#define DDRSS_CTL_96_DATA 0x00000000
+#define DDRSS_CTL_97_DATA 0x00050000
+#define DDRSS_CTL_98_DATA 0x00000004
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x00040005
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00003380
+#define DDRSS_CTL_103_DATA 0x00003380
+#define DDRSS_CTL_104_DATA 0x00003380
+#define DDRSS_CTL_105_DATA 0x00003380
+#define DDRSS_CTL_106_DATA 0x00003380
+#define DDRSS_CTL_107_DATA 0x00000000
+#define DDRSS_CTL_108_DATA 0x000005A2
+#define DDRSS_CTL_109_DATA 0x00081CC0
+#define DDRSS_CTL_110_DATA 0x00081CC0
+#define DDRSS_CTL_111_DATA 0x00081CC0
+#define DDRSS_CTL_112_DATA 0x00081CC0
+#define DDRSS_CTL_113_DATA 0x00081CC0
+#define DDRSS_CTL_114_DATA 0x00000000
+#define DDRSS_CTL_115_DATA 0x0000E325
+#define DDRSS_CTL_116_DATA 0x00081CC0
+#define DDRSS_CTL_117_DATA 0x00081CC0
+#define DDRSS_CTL_118_DATA 0x00081CC0
+#define DDRSS_CTL_119_DATA 0x00081CC0
+#define DDRSS_CTL_120_DATA 0x00081CC0
+#define DDRSS_CTL_121_DATA 0x00000000
+#define DDRSS_CTL_122_DATA 0x0000E325
+#define DDRSS_CTL_123_DATA 0x00000000
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x00000000
+#define DDRSS_CTL_126_DATA 0x00000000
+#define DDRSS_CTL_127_DATA 0x00000000
+#define DDRSS_CTL_128_DATA 0x00000000
+#define DDRSS_CTL_129_DATA 0x00000000
+#define DDRSS_CTL_130_DATA 0x00000000
+#define DDRSS_CTL_131_DATA 0x0B030500
+#define DDRSS_CTL_132_DATA 0x00040B04
+#define DDRSS_CTL_133_DATA 0x0A090000
+#define DDRSS_CTL_134_DATA 0x0A090701
+#define DDRSS_CTL_135_DATA 0x0900000E
+#define DDRSS_CTL_136_DATA 0x0907010A
+#define DDRSS_CTL_137_DATA 0x00000E0A
+#define DDRSS_CTL_138_DATA 0x07010A09
+#define DDRSS_CTL_139_DATA 0x000E0A09
+#define DDRSS_CTL_140_DATA 0x07000401
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x08080000
+#define DDRSS_CTL_149_DATA 0x01000000
+#define DDRSS_CTL_150_DATA 0x800000C0
+#define DDRSS_CTL_151_DATA 0x800000C0
+#define DDRSS_CTL_152_DATA 0x800000C0
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00001500
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000001
+#define DDRSS_CTL_157_DATA 0x00000002
+#define DDRSS_CTL_158_DATA 0x0000100E
+#define DDRSS_CTL_159_DATA 0x00000000
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x00000000
+#define DDRSS_CTL_162_DATA 0x00000000
+#define DDRSS_CTL_163_DATA 0x00000000
+#define DDRSS_CTL_164_DATA 0x000B0000
+#define DDRSS_CTL_165_DATA 0x000E0006
+#define DDRSS_CTL_166_DATA 0x000E0404
+#define DDRSS_CTL_167_DATA 0x00D601AB
+#define DDRSS_CTL_168_DATA 0x10100216
+#define DDRSS_CTL_169_DATA 0x01AB0216
+#define DDRSS_CTL_170_DATA 0x021600D6
+#define DDRSS_CTL_171_DATA 0x02161010
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x3FF40084
+#define DDRSS_CTL_176_DATA 0x33003FF4
+#define DDRSS_CTL_177_DATA 0x00003333
+#define DDRSS_CTL_178_DATA 0x36000000
+#define DDRSS_CTL_179_DATA 0x27270036
+#define DDRSS_CTL_180_DATA 0x0F0F0000
+#define DDRSS_CTL_181_DATA 0x16000000
+#define DDRSS_CTL_182_DATA 0x00841616
+#define DDRSS_CTL_183_DATA 0x3FF43FF4
+#define DDRSS_CTL_184_DATA 0x33333300
+#define DDRSS_CTL_185_DATA 0x00000000
+#define DDRSS_CTL_186_DATA 0x00363600
+#define DDRSS_CTL_187_DATA 0x00002727
+#define DDRSS_CTL_188_DATA 0x00000F0F
+#define DDRSS_CTL_189_DATA 0x16161600
+#define DDRSS_CTL_190_DATA 0x00000020
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000001
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x01000000
+#define DDRSS_CTL_195_DATA 0x00000001
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x02000000
+#define DDRSS_CTL_207_DATA 0x01080101
+#define DDRSS_CTL_208_DATA 0x00000000
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000000
+#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000000
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000000
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000000
+#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_222_DATA 0x00001000
+#define DDRSS_CTL_223_DATA 0x006403E8
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x15110000
+#define DDRSS_CTL_228_DATA 0x00040C18
+#define DDRSS_CTL_229_DATA 0x00000000
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00030000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x01000200
+#define DDRSS_CTL_258_DATA 0x00370040
+#define DDRSS_CTL_259_DATA 0x00020008
+#define DDRSS_CTL_260_DATA 0x00400100
+#define DDRSS_CTL_261_DATA 0x00400855
+#define DDRSS_CTL_262_DATA 0x01000200
+#define DDRSS_CTL_263_DATA 0x08550040
+#define DDRSS_CTL_264_DATA 0x00000040
+#define DDRSS_CTL_265_DATA 0x006B0003
+#define DDRSS_CTL_266_DATA 0x0100006B
+#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_268_DATA 0x01010000
+#define DDRSS_CTL_269_DATA 0x00000202
+#define DDRSS_CTL_270_DATA 0x00000FFF
+#define DDRSS_CTL_271_DATA 0x1FFF1000
+#define DDRSS_CTL_272_DATA 0x01FF0000
+#define DDRSS_CTL_273_DATA 0x000101FF
+#define DDRSS_CTL_274_DATA 0x0FFF0B00
+#define DDRSS_CTL_275_DATA 0x01010001
+#define DDRSS_CTL_276_DATA 0x01010101
+#define DDRSS_CTL_277_DATA 0x01180101
+#define DDRSS_CTL_278_DATA 0x00030000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000000
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00040101
+#define DDRSS_CTL_287_DATA 0x04010100
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x03030300
+#define DDRSS_CTL_291_DATA 0x00000001
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00000000
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x01000000
+#define DDRSS_CTL_314_DATA 0x00020201
+#define DDRSS_CTL_315_DATA 0x01000101
+#define DDRSS_CTL_316_DATA 0x01010001
+#define DDRSS_CTL_317_DATA 0x00010101
+#define DDRSS_CTL_318_DATA 0x050A0A03
+#define DDRSS_CTL_319_DATA 0x10081F1F
+#define DDRSS_CTL_320_DATA 0x00090310
+#define DDRSS_CTL_321_DATA 0x0B0C030F
+#define DDRSS_CTL_322_DATA 0x0B0C0306
+#define DDRSS_CTL_323_DATA 0x0C090006
+#define DDRSS_CTL_324_DATA 0x0100000C
+#define DDRSS_CTL_325_DATA 0x08040801
+#define DDRSS_CTL_326_DATA 0x00000004
+#define DDRSS_CTL_327_DATA 0x00000000
+#define DDRSS_CTL_328_DATA 0x00010000
+#define DDRSS_CTL_329_DATA 0x00280D00
+#define DDRSS_CTL_330_DATA 0x00000001
+#define DDRSS_CTL_331_DATA 0x00030001
+#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x01000000
+#define DDRSS_CTL_341_DATA 0x00000001
+#define DDRSS_CTL_342_DATA 0x00010100
+#define DDRSS_CTL_343_DATA 0x03030000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x000556AA
+#define DDRSS_CTL_361_DATA 0x000AAAAA
+#define DDRSS_CTL_362_DATA 0x000AA955
+#define DDRSS_CTL_363_DATA 0x00055555
+#define DDRSS_CTL_364_DATA 0x000B3133
+#define DDRSS_CTL_365_DATA 0x0004CD33
+#define DDRSS_CTL_366_DATA 0x0004CECC
+#define DDRSS_CTL_367_DATA 0x000B32CC
+#define DDRSS_CTL_368_DATA 0x00010300
+#define DDRSS_CTL_369_DATA 0x03000100
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00010000
+#define DDRSS_CTL_378_DATA 0x00000404
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x00000000
+#define DDRSS_CTL_384_DATA 0x00000000
+#define DDRSS_CTL_385_DATA 0x00000000
+#define DDRSS_CTL_386_DATA 0x00000000
+#define DDRSS_CTL_387_DATA 0x3A3A1B00
+#define DDRSS_CTL_388_DATA 0x000A0000
+#define DDRSS_CTL_389_DATA 0x0000019C
+#define DDRSS_CTL_390_DATA 0x00000200
+#define DDRSS_CTL_391_DATA 0x00000200
+#define DDRSS_CTL_392_DATA 0x00000200
+#define DDRSS_CTL_393_DATA 0x00000200
+#define DDRSS_CTL_394_DATA 0x000004D4
+#define DDRSS_CTL_395_DATA 0x00001018
+#define DDRSS_CTL_396_DATA 0x00000204
+#define DDRSS_CTL_397_DATA 0x000040E6
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x0000C2B2
+#define DDRSS_CTL_403_DATA 0x000288FC
+#define DDRSS_CTL_404_DATA 0x00000E15
+#define DDRSS_CTL_405_DATA 0x000040E6
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x0000C2B2
+#define DDRSS_CTL_411_DATA 0x000288FC
+#define DDRSS_CTL_412_DATA 0x02020E15
+#define DDRSS_CTL_413_DATA 0x03030202
+#define DDRSS_CTL_414_DATA 0x00000022
+#define DDRSS_CTL_415_DATA 0x00000000
+#define DDRSS_CTL_416_DATA 0x00000000
+#define DDRSS_CTL_417_DATA 0x00001403
+#define DDRSS_CTL_418_DATA 0x000007D0
+#define DDRSS_CTL_419_DATA 0x00000000
+#define DDRSS_CTL_420_DATA 0x00000000
+#define DDRSS_CTL_421_DATA 0x00030000
+#define DDRSS_CTL_422_DATA 0x0007001F
+#define DDRSS_CTL_423_DATA 0x001B0033
+#define DDRSS_CTL_424_DATA 0x001B0033
+#define DDRSS_CTL_425_DATA 0x00000000
+#define DDRSS_CTL_426_DATA 0x00000000
+#define DDRSS_CTL_427_DATA 0x02000000
+#define DDRSS_CTL_428_DATA 0x01000404
+#define DDRSS_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS_CTL_430_DATA 0x00000105
+#define DDRSS_CTL_431_DATA 0x00010101
+#define DDRSS_CTL_432_DATA 0x00010101
+#define DDRSS_CTL_433_DATA 0x00010001
+#define DDRSS_CTL_434_DATA 0x00000101
+#define DDRSS_CTL_435_DATA 0x02000201
+#define DDRSS_CTL_436_DATA 0x02010000
+#define DDRSS_CTL_437_DATA 0x00000200
+#define DDRSS_CTL_438_DATA 0x28060000
+#define DDRSS_CTL_439_DATA 0x00000128
+#define DDRSS_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS_CTL_442_DATA 0x00000000
+#define DDRSS_CTL_443_DATA 0x00000000
+#define DDRSS_CTL_444_DATA 0x00000000
+#define DDRSS_CTL_445_DATA 0x00000000
+#define DDRSS_CTL_446_DATA 0x00000000
+#define DDRSS_CTL_447_DATA 0x00000000
+#define DDRSS_CTL_448_DATA 0x00000000
+#define DDRSS_CTL_449_DATA 0x00000000
+#define DDRSS_CTL_450_DATA 0x00000000
+#define DDRSS_CTL_451_DATA 0x00000000
+#define DDRSS_CTL_452_DATA 0x00000000
+#define DDRSS_CTL_453_DATA 0x00000000
+#define DDRSS_CTL_454_DATA 0x00000000
+#define DDRSS_CTL_455_DATA 0x00000000
+#define DDRSS_CTL_456_DATA 0x00000000
+#define DDRSS_CTL_457_DATA 0x00000000
+#define DDRSS_CTL_458_DATA 0x00000000
+
+#define DDRSS_PI_00_DATA 0x00000B00
+#define DDRSS_PI_01_DATA 0x00000000
+#define DDRSS_PI_02_DATA 0x00000000
+#define DDRSS_PI_03_DATA 0x00000000
+#define DDRSS_PI_04_DATA 0x00000000
+#define DDRSS_PI_05_DATA 0x00000101
+#define DDRSS_PI_06_DATA 0x00640000
+#define DDRSS_PI_07_DATA 0x00000001
+#define DDRSS_PI_08_DATA 0x00000000
+#define DDRSS_PI_09_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000007
+#define DDRSS_PI_13_DATA 0x00010002
+#define DDRSS_PI_14_DATA 0x0800000F
+#define DDRSS_PI_15_DATA 0x00000103
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010100
+#define DDRSS_PI_27_DATA 0x00280A00
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x0F000000
+#define DDRSS_PI_30_DATA 0x00003200
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x000F0F00
+#define DDRSS_PI_46_DATA 0x0000001B
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x00030000
+#define DDRSS_PI_55_DATA 0x0F000000
+#define DDRSS_PI_56_DATA 0x00000017
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x00020805
+#define DDRSS_PI_63_DATA 0x01000404
+#define DDRSS_PI_64_DATA 0x00000000
+#define DDRSS_PI_65_DATA 0x00000000
+#define DDRSS_PI_66_DATA 0x00000100
+#define DDRSS_PI_67_DATA 0x0001010F
+#define DDRSS_PI_68_DATA 0x00340000
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00080100
+#define DDRSS_PI_74_DATA 0x02000200
+#define DDRSS_PI_75_DATA 0x01000100
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x02000200
+#define DDRSS_PI_78_DATA 0x00000200
+#define DDRSS_PI_79_DATA 0x00000000
+#define DDRSS_PI_80_DATA 0x00000000
+#define DDRSS_PI_81_DATA 0x00000000
+#define DDRSS_PI_82_DATA 0x00000000
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x02010000
+#define DDRSS_PI_93_DATA 0x00080003
+#define DDRSS_PI_94_DATA 0x00080000
+#define DDRSS_PI_95_DATA 0x00000001
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x0000AA00
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x00000000
+#define DDRSS_PI_100_DATA 0x00010000
+#define DDRSS_PI_101_DATA 0x00000000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000008
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000002
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000000
+#define DDRSS_PI_137_DATA 0x0000000A
+#define DDRSS_PI_138_DATA 0x00000019
+#define DDRSS_PI_139_DATA 0x00000100
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00000401
+#define DDRSS_PI_160_DATA 0x00000000
+#define DDRSS_PI_161_DATA 0x00010000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x2B2B0200
+#define DDRSS_PI_164_DATA 0x00000034
+#define DDRSS_PI_165_DATA 0x00000064
+#define DDRSS_PI_166_DATA 0x00020064
+#define DDRSS_PI_167_DATA 0x02000200
+#define DDRSS_PI_168_DATA 0x48120C04
+#define DDRSS_PI_169_DATA 0x00104812
+#define DDRSS_PI_170_DATA 0x000000CE
+#define DDRSS_PI_171_DATA 0x00000256
+#define DDRSS_PI_172_DATA 0x00002073
+#define DDRSS_PI_173_DATA 0x00000256
+#define DDRSS_PI_174_DATA 0x04002073
+#define DDRSS_PI_175_DATA 0x01010404
+#define DDRSS_PI_176_DATA 0x00001501
+#define DDRSS_PI_177_DATA 0x00150015
+#define DDRSS_PI_178_DATA 0x01000100
+#define DDRSS_PI_179_DATA 0x00000100
+#define DDRSS_PI_180_DATA 0x00000000
+#define DDRSS_PI_181_DATA 0x01010101
+#define DDRSS_PI_182_DATA 0x00000101
+#define DDRSS_PI_183_DATA 0x00000000
+#define DDRSS_PI_184_DATA 0x00000000
+#define DDRSS_PI_185_DATA 0x15040000
+#define DDRSS_PI_186_DATA 0x0E0E0215
+#define DDRSS_PI_187_DATA 0x00040402
+#define DDRSS_PI_188_DATA 0x000D0035
+#define DDRSS_PI_189_DATA 0x00218049
+#define DDRSS_PI_190_DATA 0x00218049
+#define DDRSS_PI_191_DATA 0x01010101
+#define DDRSS_PI_192_DATA 0x0004000E
+#define DDRSS_PI_193_DATA 0x00040216
+#define DDRSS_PI_194_DATA 0x01000216
+#define DDRSS_PI_195_DATA 0x000F000F
+#define DDRSS_PI_196_DATA 0x02170100
+#define DDRSS_PI_197_DATA 0x01000217
+#define DDRSS_PI_198_DATA 0x02170217
+#define DDRSS_PI_199_DATA 0x32103200
+#define DDRSS_PI_200_DATA 0x01013210
+#define DDRSS_PI_201_DATA 0x0A070601
+#define DDRSS_PI_202_DATA 0x1F130A0D
+#define DDRSS_PI_203_DATA 0x1F130A14
+#define DDRSS_PI_204_DATA 0x0000C014
+#define DDRSS_PI_205_DATA 0x00C01000
+#define DDRSS_PI_206_DATA 0x00C01000
+#define DDRSS_PI_207_DATA 0x00021000
+#define DDRSS_PI_208_DATA 0x0024000E
+#define DDRSS_PI_209_DATA 0x00240216
+#define DDRSS_PI_210_DATA 0x00110216
+#define DDRSS_PI_211_DATA 0x32000056
+#define DDRSS_PI_212_DATA 0x00000301
+#define DDRSS_PI_213_DATA 0x005B003A
+#define DDRSS_PI_214_DATA 0x03013212
+#define DDRSS_PI_215_DATA 0x00003A00
+#define DDRSS_PI_216_DATA 0x3212005B
+#define DDRSS_PI_217_DATA 0x09000301
+#define DDRSS_PI_218_DATA 0x04010504
+#define DDRSS_PI_219_DATA 0x040006C9
+#define DDRSS_PI_220_DATA 0x0A032001
+#define DDRSS_PI_221_DATA 0x2C31110A
+#define DDRSS_PI_222_DATA 0x00002D1C
+#define DDRSS_PI_223_DATA 0x6001071C
+#define DDRSS_PI_224_DATA 0x1E202008
+#define DDRSS_PI_225_DATA 0x2C311116
+#define DDRSS_PI_226_DATA 0x00002D1C
+#define DDRSS_PI_227_DATA 0x6001071C
+#define DDRSS_PI_228_DATA 0x1E202008
+#define DDRSS_PI_229_DATA 0x00019C16
+#define DDRSS_PI_230_DATA 0x00001018
+#define DDRSS_PI_231_DATA 0x000040E6
+#define DDRSS_PI_232_DATA 0x000288FC
+#define DDRSS_PI_233_DATA 0x000040E6
+#define DDRSS_PI_234_DATA 0x000288FC
+#define DDRSS_PI_235_DATA 0x02660010
+#define DDRSS_PI_236_DATA 0x03030266
+#define DDRSS_PI_237_DATA 0x002AF803
+#define DDRSS_PI_238_DATA 0x0001ADAF
+#define DDRSS_PI_239_DATA 0x00000005
+#define DDRSS_PI_240_DATA 0x0000006E
+#define DDRSS_PI_241_DATA 0x00000010
+#define DDRSS_PI_242_DATA 0x000681C8
+#define DDRSS_PI_243_DATA 0x0001ADAF
+#define DDRSS_PI_244_DATA 0x00000005
+#define DDRSS_PI_245_DATA 0x000010A9
+#define DDRSS_PI_246_DATA 0x00000266
+#define DDRSS_PI_247_DATA 0x000681C8
+#define DDRSS_PI_248_DATA 0x0001ADAF
+#define DDRSS_PI_249_DATA 0x00000005
+#define DDRSS_PI_250_DATA 0x000010A9
+#define DDRSS_PI_251_DATA 0x01000266
+#define DDRSS_PI_252_DATA 0x00370040
+#define DDRSS_PI_253_DATA 0x00010008
+#define DDRSS_PI_254_DATA 0x08550040
+#define DDRSS_PI_255_DATA 0x00010040
+#define DDRSS_PI_256_DATA 0x08550040
+#define DDRSS_PI_257_DATA 0x00000340
+#define DDRSS_PI_258_DATA 0x006B006B
+#define DDRSS_PI_259_DATA 0x08040404
+#define DDRSS_PI_260_DATA 0x00000055
+#define DDRSS_PI_261_DATA 0x55083C5A
+#define DDRSS_PI_262_DATA 0x5A000000
+#define DDRSS_PI_263_DATA 0x0055083C
+#define DDRSS_PI_264_DATA 0x3C5A0000
+#define DDRSS_PI_265_DATA 0x00005508
+#define DDRSS_PI_266_DATA 0x0C3C5A00
+#define DDRSS_PI_267_DATA 0x080F0E0D
+#define DDRSS_PI_268_DATA 0x000B0A09
+#define DDRSS_PI_269_DATA 0x00030201
+#define DDRSS_PI_270_DATA 0x01000000
+#define DDRSS_PI_271_DATA 0x04020201
+#define DDRSS_PI_272_DATA 0x00080804
+#define DDRSS_PI_273_DATA 0x00000000
+#define DDRSS_PI_274_DATA 0x00000000
+#define DDRSS_PI_275_DATA 0x00330084
+#define DDRSS_PI_276_DATA 0x00160000
+#define DDRSS_PI_277_DATA 0x36333FF4
+#define DDRSS_PI_278_DATA 0x00160F27
+#define DDRSS_PI_279_DATA 0x36333FF4
+#define DDRSS_PI_280_DATA 0x00160F27
+#define DDRSS_PI_281_DATA 0x00330084
+#define DDRSS_PI_282_DATA 0x00160000
+#define DDRSS_PI_283_DATA 0x36333FF4
+#define DDRSS_PI_284_DATA 0x00160F27
+#define DDRSS_PI_285_DATA 0x36333FF4
+#define DDRSS_PI_286_DATA 0x00160F27
+#define DDRSS_PI_287_DATA 0x00330084
+#define DDRSS_PI_288_DATA 0x00160000
+#define DDRSS_PI_289_DATA 0x36333FF4
+#define DDRSS_PI_290_DATA 0x00160F27
+#define DDRSS_PI_291_DATA 0x36333FF4
+#define DDRSS_PI_292_DATA 0x00160F27
+#define DDRSS_PI_293_DATA 0x00330084
+#define DDRSS_PI_294_DATA 0x00160000
+#define DDRSS_PI_295_DATA 0x36333FF4
+#define DDRSS_PI_296_DATA 0x00160F27
+#define DDRSS_PI_297_DATA 0x36333FF4
+#define DDRSS_PI_298_DATA 0x00160F27
+#define DDRSS_PI_299_DATA 0x00000000
+
+#define DDRSS_PHY_00_DATA 0x000004F0
+#define DDRSS_PHY_01_DATA 0x00000000
+#define DDRSS_PHY_02_DATA 0x00030200
+#define DDRSS_PHY_03_DATA 0x00000000
+#define DDRSS_PHY_04_DATA 0x00000000
+#define DDRSS_PHY_05_DATA 0x01030000
+#define DDRSS_PHY_06_DATA 0x00010000
+#define DDRSS_PHY_07_DATA 0x01030004
+#define DDRSS_PHY_08_DATA 0x01000000
+#define DDRSS_PHY_09_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01000001
+#define DDRSS_PHY_12_DATA 0x00000100
+#define DDRSS_PHY_13_DATA 0x000800C0
+#define DDRSS_PHY_14_DATA 0x060100CC
+#define DDRSS_PHY_15_DATA 0x00030066
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000301
+#define DDRSS_PHY_18_DATA 0x0000AAAA
+#define DDRSS_PHY_19_DATA 0x00005555
+#define DDRSS_PHY_20_DATA 0x0000B5B5
+#define DDRSS_PHY_21_DATA 0x00004A4A
+#define DDRSS_PHY_22_DATA 0x00005656
+#define DDRSS_PHY_23_DATA 0x0000A9A9
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B5B5
+#define DDRSS_PHY_26_DATA 0x00000000
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x2A000000
+#define DDRSS_PHY_29_DATA 0x00000808
+#define DDRSS_PHY_30_DATA 0x0F000000
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x10200000
+#define DDRSS_PHY_33_DATA 0x0C002006
+#define DDRSS_PHY_34_DATA 0x00000000
+#define DDRSS_PHY_35_DATA 0x00000000
+#define DDRSS_PHY_36_DATA 0x55555555
+#define DDRSS_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x00005555
+#define DDRSS_PHY_41_DATA 0x01000100
+#define DDRSS_PHY_42_DATA 0x00800180
+#define DDRSS_PHY_43_DATA 0x00000001
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000104
+#define DDRSS_PHY_67_DATA 0x00000120
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x00000000
+#define DDRSS_PHY_75_DATA 0x00000001
+#define DDRSS_PHY_76_DATA 0x07FF0000
+#define DDRSS_PHY_77_DATA 0x0080081F
+#define DDRSS_PHY_78_DATA 0x00081020
+#define DDRSS_PHY_79_DATA 0x04010000
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00000000
+#define DDRSS_PHY_83_DATA 0x00000100
+#define DDRSS_PHY_84_DATA 0x01CC0C01
+#define DDRSS_PHY_85_DATA 0x1003CC0C
+#define DDRSS_PHY_86_DATA 0x20000140
+#define DDRSS_PHY_87_DATA 0x07FF0200
+#define DDRSS_PHY_88_DATA 0x0000DD01
+#define DDRSS_PHY_89_DATA 0x10100303
+#define DDRSS_PHY_90_DATA 0x10101010
+#define DDRSS_PHY_91_DATA 0x10101010
+#define DDRSS_PHY_92_DATA 0x00021010
+#define DDRSS_PHY_93_DATA 0x00100010
+#define DDRSS_PHY_94_DATA 0x00100010
+#define DDRSS_PHY_95_DATA 0x00100010
+#define DDRSS_PHY_96_DATA 0x00100010
+#define DDRSS_PHY_97_DATA 0x00050010
+#define DDRSS_PHY_98_DATA 0x51517041
+#define DDRSS_PHY_99_DATA 0x31C06001
+#define DDRSS_PHY_100_DATA 0x07AB0340
+#define DDRSS_PHY_101_DATA 0x00C0C001
+#define DDRSS_PHY_102_DATA 0x0E0D0001
+#define DDRSS_PHY_103_DATA 0x10001000
+#define DDRSS_PHY_104_DATA 0x0C083E42
+#define DDRSS_PHY_105_DATA 0x0F0C3701
+#define DDRSS_PHY_106_DATA 0x01000140
+#define DDRSS_PHY_107_DATA 0x0C000420
+#define DDRSS_PHY_108_DATA 0x00000198
+#define DDRSS_PHY_109_DATA 0x0A0000D0
+#define DDRSS_PHY_110_DATA 0x00030200
+#define DDRSS_PHY_111_DATA 0x02800000
+#define DDRSS_PHY_112_DATA 0x80800000
+#define DDRSS_PHY_113_DATA 0x000E2010
+#define DDRSS_PHY_114_DATA 0x76543210
+#define DDRSS_PHY_115_DATA 0x00000008
+#define DDRSS_PHY_116_DATA 0x02800280
+#define DDRSS_PHY_117_DATA 0x02800280
+#define DDRSS_PHY_118_DATA 0x02800280
+#define DDRSS_PHY_119_DATA 0x02800280
+#define DDRSS_PHY_120_DATA 0x00000280
+#define DDRSS_PHY_121_DATA 0x0000A000
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00A000A0
+#define DDRSS_PHY_128_DATA 0x00A000A0
+#define DDRSS_PHY_129_DATA 0x00A000A0
+#define DDRSS_PHY_130_DATA 0x01C200A0
+#define DDRSS_PHY_131_DATA 0x01A00005
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00080200
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x20202000
+#define DDRSS_PHY_137_DATA 0x20202020
+#define DDRSS_PHY_138_DATA 0xF0F02020
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x000004F0
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01000001
+#define DDRSS_PHY_268_DATA 0x00000100
+#define DDRSS_PHY_269_DATA 0x000800C0
+#define DDRSS_PHY_270_DATA 0x060100CC
+#define DDRSS_PHY_271_DATA 0x00030066
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000301
+#define DDRSS_PHY_274_DATA 0x0000AAAA
+#define DDRSS_PHY_275_DATA 0x00005555
+#define DDRSS_PHY_276_DATA 0x0000B5B5
+#define DDRSS_PHY_277_DATA 0x00004A4A
+#define DDRSS_PHY_278_DATA 0x00005656
+#define DDRSS_PHY_279_DATA 0x0000A9A9
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B5B5
+#define DDRSS_PHY_282_DATA 0x00000000
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x2A000000
+#define DDRSS_PHY_285_DATA 0x00000808
+#define DDRSS_PHY_286_DATA 0x0F000000
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x10200000
+#define DDRSS_PHY_289_DATA 0x0C002006
+#define DDRSS_PHY_290_DATA 0x00000000
+#define DDRSS_PHY_291_DATA 0x00000000
+#define DDRSS_PHY_292_DATA 0x55555555
+#define DDRSS_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x00005555
+#define DDRSS_PHY_297_DATA 0x01000100
+#define DDRSS_PHY_298_DATA 0x00800180
+#define DDRSS_PHY_299_DATA 0x00000000
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000104
+#define DDRSS_PHY_323_DATA 0x00000120
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x00000000
+#define DDRSS_PHY_331_DATA 0x00000001
+#define DDRSS_PHY_332_DATA 0x07FF0000
+#define DDRSS_PHY_333_DATA 0x0080081F
+#define DDRSS_PHY_334_DATA 0x00081020
+#define DDRSS_PHY_335_DATA 0x04010000
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00000000
+#define DDRSS_PHY_339_DATA 0x00000100
+#define DDRSS_PHY_340_DATA 0x01CC0C01
+#define DDRSS_PHY_341_DATA 0x1003CC0C
+#define DDRSS_PHY_342_DATA 0x20000140
+#define DDRSS_PHY_343_DATA 0x07FF0200
+#define DDRSS_PHY_344_DATA 0x0000DD01
+#define DDRSS_PHY_345_DATA 0x10100303
+#define DDRSS_PHY_346_DATA 0x10101010
+#define DDRSS_PHY_347_DATA 0x10101010
+#define DDRSS_PHY_348_DATA 0x00021010
+#define DDRSS_PHY_349_DATA 0x00100010
+#define DDRSS_PHY_350_DATA 0x00100010
+#define DDRSS_PHY_351_DATA 0x00100010
+#define DDRSS_PHY_352_DATA 0x00100010
+#define DDRSS_PHY_353_DATA 0x00050010
+#define DDRSS_PHY_354_DATA 0x51517041
+#define DDRSS_PHY_355_DATA 0x31C06001
+#define DDRSS_PHY_356_DATA 0x07AB0340
+#define DDRSS_PHY_357_DATA 0x00C0C001
+#define DDRSS_PHY_358_DATA 0x0E0D0001
+#define DDRSS_PHY_359_DATA 0x10001000
+#define DDRSS_PHY_360_DATA 0x0C083E42
+#define DDRSS_PHY_361_DATA 0x0F0C3701
+#define DDRSS_PHY_362_DATA 0x01000140
+#define DDRSS_PHY_363_DATA 0x0C000420
+#define DDRSS_PHY_364_DATA 0x00000198
+#define DDRSS_PHY_365_DATA 0x0A0000D0
+#define DDRSS_PHY_366_DATA 0x00030200
+#define DDRSS_PHY_367_DATA 0x02800000
+#define DDRSS_PHY_368_DATA 0x80800000
+#define DDRSS_PHY_369_DATA 0x000E2010
+#define DDRSS_PHY_370_DATA 0x76543210
+#define DDRSS_PHY_371_DATA 0x00000008
+#define DDRSS_PHY_372_DATA 0x02800280
+#define DDRSS_PHY_373_DATA 0x02800280
+#define DDRSS_PHY_374_DATA 0x02800280
+#define DDRSS_PHY_375_DATA 0x02800280
+#define DDRSS_PHY_376_DATA 0x00000280
+#define DDRSS_PHY_377_DATA 0x0000A000
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00A000A0
+#define DDRSS_PHY_384_DATA 0x00A000A0
+#define DDRSS_PHY_385_DATA 0x00A000A0
+#define DDRSS_PHY_386_DATA 0x01C200A0
+#define DDRSS_PHY_387_DATA 0x01A00005
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00080200
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x20202000
+#define DDRSS_PHY_393_DATA 0x20202020
+#define DDRSS_PHY_394_DATA 0xF0F02020
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x000004F0
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x01000001
+#define DDRSS_PHY_524_DATA 0x00000100
+#define DDRSS_PHY_525_DATA 0x000800C0
+#define DDRSS_PHY_526_DATA 0x060100CC
+#define DDRSS_PHY_527_DATA 0x00030066
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000301
+#define DDRSS_PHY_530_DATA 0x0000AAAA
+#define DDRSS_PHY_531_DATA 0x00005555
+#define DDRSS_PHY_532_DATA 0x0000B5B5
+#define DDRSS_PHY_533_DATA 0x00004A4A
+#define DDRSS_PHY_534_DATA 0x00005656
+#define DDRSS_PHY_535_DATA 0x0000A9A9
+#define DDRSS_PHY_536_DATA 0x0000A9A9
+#define DDRSS_PHY_537_DATA 0x0000B5B5
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x2A000000
+#define DDRSS_PHY_541_DATA 0x00000808
+#define DDRSS_PHY_542_DATA 0x0F000000
+#define DDRSS_PHY_543_DATA 0x00000F0F
+#define DDRSS_PHY_544_DATA 0x10200000
+#define DDRSS_PHY_545_DATA 0x0C002006
+#define DDRSS_PHY_546_DATA 0x00000000
+#define DDRSS_PHY_547_DATA 0x00000000
+#define DDRSS_PHY_548_DATA 0x55555555
+#define DDRSS_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x00005555
+#define DDRSS_PHY_553_DATA 0x01000100
+#define DDRSS_PHY_554_DATA 0x00800180
+#define DDRSS_PHY_555_DATA 0x00000001
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000104
+#define DDRSS_PHY_579_DATA 0x00000120
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000001
+#define DDRSS_PHY_588_DATA 0x07FF0000
+#define DDRSS_PHY_589_DATA 0x0080081F
+#define DDRSS_PHY_590_DATA 0x00081020
+#define DDRSS_PHY_591_DATA 0x04010000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000100
+#define DDRSS_PHY_596_DATA 0x01CC0C01
+#define DDRSS_PHY_597_DATA 0x1003CC0C
+#define DDRSS_PHY_598_DATA 0x20000140
+#define DDRSS_PHY_599_DATA 0x07FF0200
+#define DDRSS_PHY_600_DATA 0x0000DD01
+#define DDRSS_PHY_601_DATA 0x10100303
+#define DDRSS_PHY_602_DATA 0x10101010
+#define DDRSS_PHY_603_DATA 0x10101010
+#define DDRSS_PHY_604_DATA 0x00021010
+#define DDRSS_PHY_605_DATA 0x00100010
+#define DDRSS_PHY_606_DATA 0x00100010
+#define DDRSS_PHY_607_DATA 0x00100010
+#define DDRSS_PHY_608_DATA 0x00100010
+#define DDRSS_PHY_609_DATA 0x00050010
+#define DDRSS_PHY_610_DATA 0x51517041
+#define DDRSS_PHY_611_DATA 0x31C06001
+#define DDRSS_PHY_612_DATA 0x07AB0340
+#define DDRSS_PHY_613_DATA 0x00C0C001
+#define DDRSS_PHY_614_DATA 0x0E0D0001
+#define DDRSS_PHY_615_DATA 0x10001000
+#define DDRSS_PHY_616_DATA 0x0C083E42
+#define DDRSS_PHY_617_DATA 0x0F0C3701
+#define DDRSS_PHY_618_DATA 0x01000140
+#define DDRSS_PHY_619_DATA 0x0C000420
+#define DDRSS_PHY_620_DATA 0x00000198
+#define DDRSS_PHY_621_DATA 0x0A0000D0
+#define DDRSS_PHY_622_DATA 0x00030200
+#define DDRSS_PHY_623_DATA 0x02800000
+#define DDRSS_PHY_624_DATA 0x80800000
+#define DDRSS_PHY_625_DATA 0x000E2010
+#define DDRSS_PHY_626_DATA 0x76543210
+#define DDRSS_PHY_627_DATA 0x00000008
+#define DDRSS_PHY_628_DATA 0x02800280
+#define DDRSS_PHY_629_DATA 0x02800280
+#define DDRSS_PHY_630_DATA 0x02800280
+#define DDRSS_PHY_631_DATA 0x02800280
+#define DDRSS_PHY_632_DATA 0x00000280
+#define DDRSS_PHY_633_DATA 0x0000A000
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00A000A0
+#define DDRSS_PHY_640_DATA 0x00A000A0
+#define DDRSS_PHY_641_DATA 0x00A000A0
+#define DDRSS_PHY_642_DATA 0x01C200A0
+#define DDRSS_PHY_643_DATA 0x01A00005
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00080200
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x20202000
+#define DDRSS_PHY_649_DATA 0x20202020
+#define DDRSS_PHY_650_DATA 0xF0F02020
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x000004F0
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x01000001
+#define DDRSS_PHY_780_DATA 0x00000100
+#define DDRSS_PHY_781_DATA 0x000800C0
+#define DDRSS_PHY_782_DATA 0x060100CC
+#define DDRSS_PHY_783_DATA 0x00030066
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000301
+#define DDRSS_PHY_786_DATA 0x0000AAAA
+#define DDRSS_PHY_787_DATA 0x00005555
+#define DDRSS_PHY_788_DATA 0x0000B5B5
+#define DDRSS_PHY_789_DATA 0x00004A4A
+#define DDRSS_PHY_790_DATA 0x00005656
+#define DDRSS_PHY_791_DATA 0x0000A9A9
+#define DDRSS_PHY_792_DATA 0x0000A9A9
+#define DDRSS_PHY_793_DATA 0x0000B5B5
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x2A000000
+#define DDRSS_PHY_797_DATA 0x00000808
+#define DDRSS_PHY_798_DATA 0x0F000000
+#define DDRSS_PHY_799_DATA 0x00000F0F
+#define DDRSS_PHY_800_DATA 0x10200000
+#define DDRSS_PHY_801_DATA 0x0C002006
+#define DDRSS_PHY_802_DATA 0x00000000
+#define DDRSS_PHY_803_DATA 0x00000000
+#define DDRSS_PHY_804_DATA 0x55555555
+#define DDRSS_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x00005555
+#define DDRSS_PHY_809_DATA 0x01000100
+#define DDRSS_PHY_810_DATA 0x00800180
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000104
+#define DDRSS_PHY_835_DATA 0x00000120
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000001
+#define DDRSS_PHY_844_DATA 0x07FF0000
+#define DDRSS_PHY_845_DATA 0x0080081F
+#define DDRSS_PHY_846_DATA 0x00081020
+#define DDRSS_PHY_847_DATA 0x04010000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000100
+#define DDRSS_PHY_852_DATA 0x01CC0C01
+#define DDRSS_PHY_853_DATA 0x1003CC0C
+#define DDRSS_PHY_854_DATA 0x20000140
+#define DDRSS_PHY_855_DATA 0x07FF0200
+#define DDRSS_PHY_856_DATA 0x0000DD01
+#define DDRSS_PHY_857_DATA 0x10100303
+#define DDRSS_PHY_858_DATA 0x10101010
+#define DDRSS_PHY_859_DATA 0x10101010
+#define DDRSS_PHY_860_DATA 0x00021010
+#define DDRSS_PHY_861_DATA 0x00100010
+#define DDRSS_PHY_862_DATA 0x00100010
+#define DDRSS_PHY_863_DATA 0x00100010
+#define DDRSS_PHY_864_DATA 0x00100010
+#define DDRSS_PHY_865_DATA 0x00050010
+#define DDRSS_PHY_866_DATA 0x51517041
+#define DDRSS_PHY_867_DATA 0x31C06001
+#define DDRSS_PHY_868_DATA 0x07AB0340
+#define DDRSS_PHY_869_DATA 0x00C0C001
+#define DDRSS_PHY_870_DATA 0x0E0D0001
+#define DDRSS_PHY_871_DATA 0x10001000
+#define DDRSS_PHY_872_DATA 0x0C083E42
+#define DDRSS_PHY_873_DATA 0x0F0C3701
+#define DDRSS_PHY_874_DATA 0x01000140
+#define DDRSS_PHY_875_DATA 0x0C000420
+#define DDRSS_PHY_876_DATA 0x00000198
+#define DDRSS_PHY_877_DATA 0x0A0000D0
+#define DDRSS_PHY_878_DATA 0x00030200
+#define DDRSS_PHY_879_DATA 0x02800000
+#define DDRSS_PHY_880_DATA 0x80800000
+#define DDRSS_PHY_881_DATA 0x000E2010
+#define DDRSS_PHY_882_DATA 0x76543210
+#define DDRSS_PHY_883_DATA 0x00000008
+#define DDRSS_PHY_884_DATA 0x02800280
+#define DDRSS_PHY_885_DATA 0x02800280
+#define DDRSS_PHY_886_DATA 0x02800280
+#define DDRSS_PHY_887_DATA 0x02800280
+#define DDRSS_PHY_888_DATA 0x00000280
+#define DDRSS_PHY_889_DATA 0x0000A000
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00A000A0
+#define DDRSS_PHY_896_DATA 0x00A000A0
+#define DDRSS_PHY_897_DATA 0x00A000A0
+#define DDRSS_PHY_898_DATA 0x01C200A0
+#define DDRSS_PHY_899_DATA 0x01A00005
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00080200
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x20202000
+#define DDRSS_PHY_905_DATA 0x20202020
+#define DDRSS_PHY_906_DATA 0xF0F02020
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x00543210
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x00000000
+#define DDRSS_PHY_1062_DATA 0x00000000
+#define DDRSS_PHY_1063_DATA 0x00000000
+#define DDRSS_PHY_1064_DATA 0x000305CC
+#define DDRSS_PHY_1065_DATA 0x00030000
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x00000300
+#define DDRSS_PHY_1069_DATA 0x00000300
+#define DDRSS_PHY_1070_DATA 0x00000300
+#define DDRSS_PHY_1071_DATA 0x42080010
+#define DDRSS_PHY_1072_DATA 0x0000803E
+#define DDRSS_PHY_1073_DATA 0x00000001
+#define DDRSS_PHY_1074_DATA 0x01000102
+#define DDRSS_PHY_1075_DATA 0x00008000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00050000
+#define DDRSS_PHY_1285_DATA 0x04000000
+#define DDRSS_PHY_1286_DATA 0x00000055
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00002001
+#define DDRSS_PHY_1292_DATA 0x0000400F
+#define DDRSS_PHY_1293_DATA 0x50020028
+#define DDRSS_PHY_1294_DATA 0x01010000
+#define DDRSS_PHY_1295_DATA 0x80080001
+#define DDRSS_PHY_1296_DATA 0x10200000
+#define DDRSS_PHY_1297_DATA 0x00000008
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x01090E00
+#define DDRSS_PHY_1300_DATA 0x00040101
+#define DDRSS_PHY_1301_DATA 0x0000010F
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x0000FFFF
+#define DDRSS_PHY_1304_DATA 0x00000000
+#define DDRSS_PHY_1305_DATA 0x01010000
+#define DDRSS_PHY_1306_DATA 0x01080402
+#define DDRSS_PHY_1307_DATA 0x01200F02
+#define DDRSS_PHY_1308_DATA 0x00194280
+#define DDRSS_PHY_1309_DATA 0x00000004
+#define DDRSS_PHY_1310_DATA 0x00052000
+#define DDRSS_PHY_1311_DATA 0x00000000
+#define DDRSS_PHY_1312_DATA 0x00000000
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x01000000
+#define DDRSS_PHY_1318_DATA 0x00000705
+#define DDRSS_PHY_1319_DATA 0x00000054
+#define DDRSS_PHY_1320_DATA 0x00030820
+#define DDRSS_PHY_1321_DATA 0x00010820
+#define DDRSS_PHY_1322_DATA 0x00010820
+#define DDRSS_PHY_1323_DATA 0x00010820
+#define DDRSS_PHY_1324_DATA 0x00010820
+#define DDRSS_PHY_1325_DATA 0x00010820
+#define DDRSS_PHY_1326_DATA 0x00010820
+#define DDRSS_PHY_1327_DATA 0x00010820
+#define DDRSS_PHY_1328_DATA 0x00010820
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000074
+#define DDRSS_PHY_1331_DATA 0x00000400
+#define DDRSS_PHY_1332_DATA 0x00000108
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x03000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x04102006
+#define DDRSS_PHY_1343_DATA 0x00041020
+#define DDRSS_PHY_1344_DATA 0x01C98C98
+#define DDRSS_PHY_1345_DATA 0x3F400000
+#define DDRSS_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1347_DATA 0x0000001F
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00010000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x76543210
+#define DDRSS_PHY_1357_DATA 0x00010198
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00040700
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000002
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00080000
+#define DDRSS_PHY_1375_DATA 0x000007FF
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x000FFFFF
+#define DDRSS_PHY_1383_DATA 0x000FFFFF
+#define DDRSS_PHY_1384_DATA 0x0000FFFF
+#define DDRSS_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS_PHY_1386_DATA 0x030FFFFF
+#define DDRSS_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS_PHY_1388_DATA 0x0000FFFF
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x0001F7C0
+#define DDRSS_PHY_1394_DATA 0x00000003
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00001142
+#define DDRSS_PHY_1397_DATA 0x010207AB
+#define DDRSS_PHY_1398_DATA 0x01000080
+#define DDRSS_PHY_1399_DATA 0x03900390
+#define DDRSS_PHY_1400_DATA 0x03900390
+#define DDRSS_PHY_1401_DATA 0x00000390
+#define DDRSS_PHY_1402_DATA 0x00000390
+#define DDRSS_PHY_1403_DATA 0x00000390
+#define DDRSS_PHY_1404_DATA 0x00000390
+#define DDRSS_PHY_1405_DATA 0x00000005
+#define DDRSS_PHY_1406_DATA 0x01813FCC
+#define DDRSS_PHY_1407_DATA 0x000000CC
+#define DDRSS_PHY_1408_DATA 0x0C000DFF
+#define DDRSS_PHY_1409_DATA 0x30000DFF
+#define DDRSS_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS_PHY_1411_DATA 0x000100F0
+#define DDRSS_PHY_1412_DATA 0x780DFFCC
+#define DDRSS_PHY_1413_DATA 0x00007E31
+#define DDRSS_PHY_1414_DATA 0x000CBF11
+#define DDRSS_PHY_1415_DATA 0x01990010
+#define DDRSS_PHY_1416_DATA 0x000CBF11
+#define DDRSS_PHY_1417_DATA 0x01990010
+#define DDRSS_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS_PHY_1419_DATA 0x00EF00F0
+#define DDRSS_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS_PHY_1421_DATA 0x01FF00F0
+#define DDRSS_PHY_1422_DATA 0x20040006
#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
+#include <dt-bindings/phy/phy-cadence.h>
/ {
aliases {
regulators: regulators {
u-boot,dm-spl;
buck12_reg: buck12 {
- /*VDD_MPU*/
+ /*VDD_CPU*/
regulator-name = "buck12";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1250000>;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
u-boot,dm-spl;
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
+
+&wiz0_pll1_refclk {
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&serdes0 {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
+
+ serdes0_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 2>;
+ };
+};
+
+/* EEPROM might be read before SYSFW is available */
+&wkup_i2c0 {
+ /delete-property/ power-domains;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-j721e-sk-u-boot.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = &fs_loader0;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ remoteproc2 = &main_r5fss0_core0;
+ remoteproc3 = &main_r5fss0_core1;
+ };
+
+ fs_loader0: fs_loader@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ };
+};
+
+&tps659412 {
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ u-boot,dm-spl;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include "k3-j721e-ddr-sk-lp4-4266.dtsi"
+#include "k3-j721e-ddr.dtsi"
+
+/ {
+ model = "Texas Instruments J721E SK R5";
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_0_memory_region: c66-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_1_memory_region: c66-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@aa000000 {
+ reg = <0x00 0xaa000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+ assigned-clock-rates = <2000000000>, <200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ clk_200mhz: dummy_clock_200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+
+ clk_19_2mhz: dummy_clock_19_2mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu_wakeup {
+ mcu_secproxy: secproxy@28380000 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ };
+
+ sysctrler: sysctrler {
+ u-boot,dm-spl;
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx";
+ };
+
+ wkup_vtm0: wkup_vtm@42040000 {
+ compatible = "ti,am654-vtm", "ti,j721e-avs";
+ reg = <0x0 0x42040000 0x0 0x330>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_main {
+ main_esm: esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x700000 0x0 0x1000>;
+ ti,esm-pins = <344>, <345>;
+ u-boot,dm-spl;
+ };
+};
+
+&dmsc {
+ mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&wkup_pmx0 {
+ wkup_uart0_pins_default: wkup_uart0_pins_default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu_uart0_pins_default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
+ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
+ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
+ >;
+ };
+
+ mcu_i2c0_pins_default: mcu_i2c0_pins_default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
+ J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
+ >;
+ };
+};
+
+&main_pmx0 {
+ main_uart0_pins_default: main_uart0_pins_default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
+ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ main_usbss0_pins_default: main_usbss0_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+ >;
+ };
+
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c2_pins_default: main-i2c2-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x158, PIN_INPUT_PULLUP, 2) /* (U23) RGMII5_TX_CTL.I2C2_SCL */
+ J721E_IOPAD(0x15c, PIN_INPUT_PULLUP, 2) /* (U26) RGMII5_RX_CTL.I2C2_SDA */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_i2c5_pins_default: main-i2c5-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+};
+
+&mcu_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+ status = "okay";
+ clock-frequency = <48000000>;
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_sdhci0 {
+ status = "disabled";
+};
+
+&main_sdhci1 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
+ tps659412: tps659412@48 {
+ reg = <0x48>;
+ compatible = "ti,tps659412";
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ regulators: regulators {
+ u-boot,dm-spl;
+ /* 3 Phase Buck */
+ buck123_reg: buck123 {
+ /* VDD_CPU */
+ regulator-name = "buck123";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ u-boot,dm-spl;
+ };
+ };
+ };
+};
+
+&wkup_vtm0 {
+ vdd-supply-2 = <&buck123_reg>;
+ u-boot,dm-spl;
+};
+
+&usbss0 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clocks = <&clk_19_2mhz>;
+ clock-names = "usb2_refclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usbss1 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clocks = <&clk_19_2mhz>;
+ clock-names = "usb2_refclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>;
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ cdns,phy-mode;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&ospi1 {
+ status = "disabled";
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ interrupts = <428>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster3 {
+ interrupts = <424>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ interrupts = <420>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+ memory-region = <&c66_0_dma_memory_region>,
+ <&c66_0_memory_region>;
+};
+
+&c66_1 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+ memory-region = <&c66_1_dma_memory_region>,
+ <&c66_1_memory_region>;
+};
+
+&c71_0 {
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
+
+/* EEPROM might be read before SYSFW is available */
+&wkup_i2c0 {
+ /delete-property/ power-domains;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ spi0 = &ospi0;
+ remoteproc0 = &mcu_r5fss0_core0;
+ remoteproc1 = &mcu_r5fss0_core1;
+ remoteproc2 = &main_r5fss0_core0;
+ remoteproc3 = &main_r5fss0_core1;
+ remoteproc4 = &main_r5fss1_core0;
+ remoteproc5 = &main_r5fss1_core1;
+ remoteproc6 = &c66_0;
+ remoteproc7 = &c66_1;
+ remoteproc8 = &c71_0;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ mmc1 = &main_sdhci1; /* SD Card */
+ };
+};
+
+&cbass_main{
+ u-boot,dm-spl;
+
+ main_navss {
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu_wakeup {
+ u-boot,dm-spl;
+
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-spl;
+ };
+
+ mcu-navss {
+ u-boot,dm-spl;
+
+ ringacc@2b800000 {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+ };
+
+ dma-controller@285c0000 {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+ };
+ };
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_uart0 {
+ u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+ u-boot,dm-spl;
+};
+
+&main_sdhci0 {
+ status = "disabled";
+};
+
+&main_sdhci1 {
+ u-boot,dm-spl;
+};
+
+&wiz3_pll1_refclk {
+ assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+};
+
+&main_usbss0_pins_default {
+ u-boot,dm-spl;
+};
+
+&usbss0 {
+ u-boot,dm-spl;
+};
+
+&usb0 {
+ dr_mode = "host";
+ u-boot,dm-spl;
+};
+
+&wiz2_pll1_refclk {
+ assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
+};
+
+&main_usbss1_pins_default {
+ u-boot,dm-spl;
+};
+
+&usbss1 {
+ u-boot,dm-spl;
+};
+
+&usb1 {
+ dr_mode = "host";
+ u-boot,dm-spl;
+};
+
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x2>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
+};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_i2c0_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
+};
+
+&mcu_i2c0 {
+ u-boot,dm-spl;
+};
+
+&mcu_i2c1 {
+ status = "disabled";
+};
+
+&main_i2c0 {
+ status = "disabled";
+};
+
+&main_i2c1 {
+ status = "disabled";
+};
+
+&main_i2c2 {
+ status = "disabled";
+};
+
+&main_i2c3 {
+ status = "disabled";
+};
+
+&main_i2c4 {
+ status = "disabled";
+};
+
+&main_i2c5 {
+ status = "disabled";
+};
+
+&main_i2c6 {
+ status = "disabled";
+};
+
+&mcu_i2c0_pins_default {
+ u-boot,dm-spl;
+};
+
+&mcu_fss0_ospi0_pins_default {
+ u-boot,dm-spl;
+};
+
+&fss {
+ u-boot,dm-spl;
+};
+
+&ospi0 {
+ u-boot,dm-spl;
+
+ flash@0 {
+ u-boot,dm-spl;
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&serdes_ln_ctrl {
+ u-boot,mux-autoprobe;
+};
+
+&usb_serdes_mux {
+ u-boot,mux-autoprobe;
+};
+
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie1_rc {
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+};
+
+&pcie1_ep {
+ status = "disabled";
+};
+
+&dss {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ compatible = "ti,j721e-sk", "ti,j721e";
+ model = "Texas Instruments J721E SK A72";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_0_memory_region: c66-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_1_memory_region: c66-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@aa000000 {
+ reg = <0x00 0xaa000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ vusb_main: fixedregulator-vusb-main5v0 {
+ /* USB MAIN INPUT 5V DC */
+ compatible = "regulator-fixed";
+ regulator-name = "vusb-main5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of LM5141 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vusb_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_mmc1_en_pins_default>;
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: gpio-regulator-tps659411 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tps659411";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_3v3>;
+ gpios = <&wkup_gpio0 9 GPIO_ACTIVE_LOW>;
+ states = <3300000 0x0>,
+ <1800000 0x1>;
+ };
+};
+
+&main_pmx0 {
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
+ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
+ J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
+ >;
+ };
+
+ vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
+ >;
+ };
+
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "reserved";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart2 {
+ /* Brought out on RPi header */
+ status = "disabled";
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart5 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* Brought out on M.2 E Key */
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_sdhci1 {
+ /* SD Card */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ cdns,phy-mode;
+ cdns,phy-tx-start = <18>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&ospi1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c4 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c5 {
+ /* Brought out on RPi Header */
+ status = "disabled";
+};
+
+&main_i2c6 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcu_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+ serdes2_usb_link: link@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz2 2>;
+ };
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes2_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&tscadc1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
+ <&k3_clks 152 4>, /* VP 2 pixel clock */
+ <&k3_clks 152 9>, /* VP 3 pixel clock */
+ <&k3_clks 152 13>; /* VP 4 pixel clock */
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
+};
+
+&mcasp0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp3 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp4 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp5 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp6 {
+ /* Brought out on RPi header */
+ status = "disabled";
+};
+
+&mcasp7 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp8 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp9 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp10 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp11 {
+ /* Brought out on M.2 E Key */
+ status = "disabled";
+};
+
+&pcie2_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie2_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ interrupts = <428>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster3 {
+ interrupts = <424>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ interrupts = <420>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+ memory-region = <&c66_0_dma_memory_region>,
+ <&c66_0_memory_region>;
+};
+
+&c66_1 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+ memory-region = <&c66_1_dma_memory_region>,
+ <&c66_1_memory_region>;
+};
+
+&c71_0 {
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart8;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &mcu_i2c1;
+ i2c3 = &main_i2c0;
+ ethernet0 = &cpsw_port1;
+ };
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
+};
+
+&cbass_main {
+ u-boot,dm-spl;
+};
+
+&main_navss {
+ u-boot,dm-spl;
+};
+
+&cbass_mcu_wakeup {
+ u-boot,dm-spl;
+
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-spl;
+ };
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
+};
+
+&mcu_navss {
+ u-boot,dm-spl;
+};
+
+&mcu_ringacc {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&sms {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_uart8_pins_default {
+ u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&main_uart8 {
+ u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+ u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+};
+
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
+};
+
+&main_sdhci0 {
+ u-boot,dm-spl;
+};
+
+&main_sdhci1 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2-som-p0.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ compatible = "ti,j721s2-evm", "ti,j721s2";
+ model = "Texas Instruments J721S2 EVM";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000";
+ };
+
+ aliases {
+ serial2 = &main_uart8;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ can0 = &main_mcan16;
+ can1 = &mcu_mcan0;
+ can2 = &mcu_mcan1;
+ };
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixedregulator-sd {
+ /* Output of TPS22918 */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: gpio-regulator-TLV71033 {
+ /* Output of TLV71033 */
+ compatible = "regulator-gpio";
+ regulator-name = "tlv71033";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ transceiver1: can-phy1 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver2: can-phy2 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+};
+
+&main_pmx0 {
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
+ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
+ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
+ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */
+ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
+ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
+ J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+ J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
+ J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
+ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
+ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+ J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+ J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+ J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+ J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+ J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+ J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+ J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+ J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+ J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
+ J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
+ >;
+ };
+
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
+ J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
+ >;
+ };
+
+ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
+ >;
+ };
+};
+
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
+&wkup_uart0 {
+ status = "reserved";
+};
+
+&main_uart0 {
+ status = "disabled";
+};
+
+&main_uart1 {
+ status = "disabled";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&main_uart7 {
+ status = "disabled";
+};
+
+&main_uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart8_pins_default>;
+ /* Shared with TFA on this platform */
+ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+};
+
+&main_uart9 {
+ status = "disabled";
+};
+
+&main_i2c0 {
+ clock-frequency = <400000>;
+
+ exp1: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ",
+ "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ",
+ "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#",
+ "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1",
+ "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz";
+ };
+
+ exp2: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN",
+ "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#",
+ "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1",
+ "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL",
+ "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL",
+ "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2";
+ };
+};
+
+&main_i2c1 {
+ status = "disabled";
+};
+
+&main_i2c2 {
+ status = "disabled";
+};
+
+&main_i2c3 {
+ status = "disabled";
+};
+
+&main_i2c4 {
+ status = "disabled";
+};
+
+&main_i2c5 {
+ status = "disabled";
+};
+
+&main_i2c6 {
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD card */
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ disable-wp;
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&mcu_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
+};
+
+&mcu_mcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver2>;
+};
+
+&main_mcan0 {
+ status = "disabled";
+};
+
+&main_mcan1 {
+ status = "disabled";
+};
+
+&main_mcan2 {
+ status = "disabled";
+};
+
+&main_mcan3 {
+ status = "disabled";
+};
+
+&main_mcan4 {
+ status = "disabled";
+};
+
+&main_mcan5 {
+ status = "disabled";
+};
+
+&main_mcan6 {
+ status = "disabled";
+};
+
+&main_mcan7 {
+ status = "disabled";
+};
+
+&main_mcan8 {
+ status = "disabled";
+};
+
+&main_mcan9 {
+ status = "disabled";
+};
+
+&main_mcan10 {
+ status = "disabled";
+};
+
+&main_mcan11 {
+ status = "disabled";
+};
+
+&main_mcan12 {
+ status = "disabled";
+};
+
+&main_mcan13 {
+ status = "disabled";
+};
+
+&main_mcan14 {
+ status = "disabled";
+};
+
+&main_mcan15 {
+ status = "disabled";
+};
+
+&main_mcan17 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0
+ * This file was generated on 10/14/2021
+ */
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
+
+#define MULTI_DDR_CFG_INTRLV_GRAN 0
+#define MULTI_DDR_CFG_INTRLV_SIZE 11
+#define MULTI_DDR_CFG_ECC_ENABLE 0
+#define MULTI_DDR_CFG_HYBRID_SELECT 0
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 3
+
+#define DDRSS0_CTL_00_DATA 0x00000B00
+#define DDRSS0_CTL_01_DATA 0x00000000
+#define DDRSS0_CTL_02_DATA 0x00000000
+#define DDRSS0_CTL_03_DATA 0x00000000
+#define DDRSS0_CTL_04_DATA 0x00000000
+#define DDRSS0_CTL_05_DATA 0x00000000
+#define DDRSS0_CTL_06_DATA 0x00000000
+#define DDRSS0_CTL_07_DATA 0x00002AF8
+#define DDRSS0_CTL_08_DATA 0x0001ADAF
+#define DDRSS0_CTL_09_DATA 0x00000005
+#define DDRSS0_CTL_10_DATA 0x0000006E
+#define DDRSS0_CTL_11_DATA 0x000681C8
+#define DDRSS0_CTL_12_DATA 0x004111C9
+#define DDRSS0_CTL_13_DATA 0x00000005
+#define DDRSS0_CTL_14_DATA 0x000010A9
+#define DDRSS0_CTL_15_DATA 0x000681C8
+#define DDRSS0_CTL_16_DATA 0x004111C9
+#define DDRSS0_CTL_17_DATA 0x00000005
+#define DDRSS0_CTL_18_DATA 0x000010A9
+#define DDRSS0_CTL_19_DATA 0x01010000
+#define DDRSS0_CTL_20_DATA 0x02011001
+#define DDRSS0_CTL_21_DATA 0x02010000
+#define DDRSS0_CTL_22_DATA 0x00020100
+#define DDRSS0_CTL_23_DATA 0x0000000B
+#define DDRSS0_CTL_24_DATA 0x0000001C
+#define DDRSS0_CTL_25_DATA 0x00000000
+#define DDRSS0_CTL_26_DATA 0x00000000
+#define DDRSS0_CTL_27_DATA 0x03020200
+#define DDRSS0_CTL_28_DATA 0x00005656
+#define DDRSS0_CTL_29_DATA 0x00100000
+#define DDRSS0_CTL_30_DATA 0x00000000
+#define DDRSS0_CTL_31_DATA 0x00000000
+#define DDRSS0_CTL_32_DATA 0x00000000
+#define DDRSS0_CTL_33_DATA 0x00000000
+#define DDRSS0_CTL_34_DATA 0x040C0000
+#define DDRSS0_CTL_35_DATA 0x12481248
+#define DDRSS0_CTL_36_DATA 0x00050804
+#define DDRSS0_CTL_37_DATA 0x09040008
+#define DDRSS0_CTL_38_DATA 0x15000204
+#define DDRSS0_CTL_39_DATA 0x1760008B
+#define DDRSS0_CTL_40_DATA 0x1500422B
+#define DDRSS0_CTL_41_DATA 0x1760008B
+#define DDRSS0_CTL_42_DATA 0x2000422B
+#define DDRSS0_CTL_43_DATA 0x000A0A09
+#define DDRSS0_CTL_44_DATA 0x0400078A
+#define DDRSS0_CTL_45_DATA 0x1E161104
+#define DDRSS0_CTL_46_DATA 0x10012458
+#define DDRSS0_CTL_47_DATA 0x1E161110
+#define DDRSS0_CTL_48_DATA 0x10012458
+#define DDRSS0_CTL_49_DATA 0x02030410
+#define DDRSS0_CTL_50_DATA 0x2C040500
+#define DDRSS0_CTL_51_DATA 0x08292C29
+#define DDRSS0_CTL_52_DATA 0x14000E0A
+#define DDRSS0_CTL_53_DATA 0x04010A0A
+#define DDRSS0_CTL_54_DATA 0x01010004
+#define DDRSS0_CTL_55_DATA 0x04545408
+#define DDRSS0_CTL_56_DATA 0x04313104
+#define DDRSS0_CTL_57_DATA 0x00003131
+#define DDRSS0_CTL_58_DATA 0x00010100
+#define DDRSS0_CTL_59_DATA 0x03010000
+#define DDRSS0_CTL_60_DATA 0x00001508
+#define DDRSS0_CTL_61_DATA 0x000000CE
+#define DDRSS0_CTL_62_DATA 0x0000032B
+#define DDRSS0_CTL_63_DATA 0x00002073
+#define DDRSS0_CTL_64_DATA 0x0000032B
+#define DDRSS0_CTL_65_DATA 0x00002073
+#define DDRSS0_CTL_66_DATA 0x00000005
+#define DDRSS0_CTL_67_DATA 0x00050000
+#define DDRSS0_CTL_68_DATA 0x00CB0012
+#define DDRSS0_CTL_69_DATA 0x00CB0408
+#define DDRSS0_CTL_70_DATA 0x00400408
+#define DDRSS0_CTL_71_DATA 0x00120103
+#define DDRSS0_CTL_72_DATA 0x00100005
+#define DDRSS0_CTL_73_DATA 0x2F080010
+#define DDRSS0_CTL_74_DATA 0x0505012F
+#define DDRSS0_CTL_75_DATA 0x0401030A
+#define DDRSS0_CTL_76_DATA 0x041E100B
+#define DDRSS0_CTL_77_DATA 0x100B0401
+#define DDRSS0_CTL_78_DATA 0x0001041E
+#define DDRSS0_CTL_79_DATA 0x00160016
+#define DDRSS0_CTL_80_DATA 0x033B033B
+#define DDRSS0_CTL_81_DATA 0x033B033B
+#define DDRSS0_CTL_82_DATA 0x03050505
+#define DDRSS0_CTL_83_DATA 0x03010303
+#define DDRSS0_CTL_84_DATA 0x200B100B
+#define DDRSS0_CTL_85_DATA 0x04041004
+#define DDRSS0_CTL_86_DATA 0x200B100B
+#define DDRSS0_CTL_87_DATA 0x04041004
+#define DDRSS0_CTL_88_DATA 0x03010000
+#define DDRSS0_CTL_89_DATA 0x00010000
+#define DDRSS0_CTL_90_DATA 0x00000000
+#define DDRSS0_CTL_91_DATA 0x00000000
+#define DDRSS0_CTL_92_DATA 0x01000000
+#define DDRSS0_CTL_93_DATA 0x80104002
+#define DDRSS0_CTL_94_DATA 0x00000000
+#define DDRSS0_CTL_95_DATA 0x00040005
+#define DDRSS0_CTL_96_DATA 0x00000000
+#define DDRSS0_CTL_97_DATA 0x00050000
+#define DDRSS0_CTL_98_DATA 0x00000004
+#define DDRSS0_CTL_99_DATA 0x00000000
+#define DDRSS0_CTL_100_DATA 0x00040005
+#define DDRSS0_CTL_101_DATA 0x00000000
+#define DDRSS0_CTL_102_DATA 0x00003380
+#define DDRSS0_CTL_103_DATA 0x00003380
+#define DDRSS0_CTL_104_DATA 0x00003380
+#define DDRSS0_CTL_105_DATA 0x00003380
+#define DDRSS0_CTL_106_DATA 0x00003380
+#define DDRSS0_CTL_107_DATA 0x00000000
+#define DDRSS0_CTL_108_DATA 0x000005A2
+#define DDRSS0_CTL_109_DATA 0x00081CC0
+#define DDRSS0_CTL_110_DATA 0x00081CC0
+#define DDRSS0_CTL_111_DATA 0x00081CC0
+#define DDRSS0_CTL_112_DATA 0x00081CC0
+#define DDRSS0_CTL_113_DATA 0x00081CC0
+#define DDRSS0_CTL_114_DATA 0x00000000
+#define DDRSS0_CTL_115_DATA 0x0000E325
+#define DDRSS0_CTL_116_DATA 0x00081CC0
+#define DDRSS0_CTL_117_DATA 0x00081CC0
+#define DDRSS0_CTL_118_DATA 0x00081CC0
+#define DDRSS0_CTL_119_DATA 0x00081CC0
+#define DDRSS0_CTL_120_DATA 0x00081CC0
+#define DDRSS0_CTL_121_DATA 0x00000000
+#define DDRSS0_CTL_122_DATA 0x0000E325
+#define DDRSS0_CTL_123_DATA 0x00000000
+#define DDRSS0_CTL_124_DATA 0x00000000
+#define DDRSS0_CTL_125_DATA 0x00000000
+#define DDRSS0_CTL_126_DATA 0x00000000
+#define DDRSS0_CTL_127_DATA 0x00000000
+#define DDRSS0_CTL_128_DATA 0x00000000
+#define DDRSS0_CTL_129_DATA 0x00000000
+#define DDRSS0_CTL_130_DATA 0x00000000
+#define DDRSS0_CTL_131_DATA 0x0B030500
+#define DDRSS0_CTL_132_DATA 0x00040B04
+#define DDRSS0_CTL_133_DATA 0x0A090000
+#define DDRSS0_CTL_134_DATA 0x0A090701
+#define DDRSS0_CTL_135_DATA 0x0900000E
+#define DDRSS0_CTL_136_DATA 0x0907010A
+#define DDRSS0_CTL_137_DATA 0x00000E0A
+#define DDRSS0_CTL_138_DATA 0x07010A09
+#define DDRSS0_CTL_139_DATA 0x000E0A09
+#define DDRSS0_CTL_140_DATA 0x07000401
+#define DDRSS0_CTL_141_DATA 0x00000000
+#define DDRSS0_CTL_142_DATA 0x00000000
+#define DDRSS0_CTL_143_DATA 0x00000000
+#define DDRSS0_CTL_144_DATA 0x00000000
+#define DDRSS0_CTL_145_DATA 0x00000000
+#define DDRSS0_CTL_146_DATA 0x00000000
+#define DDRSS0_CTL_147_DATA 0x00000000
+#define DDRSS0_CTL_148_DATA 0x08080000
+#define DDRSS0_CTL_149_DATA 0x01000000
+#define DDRSS0_CTL_150_DATA 0x800000C0
+#define DDRSS0_CTL_151_DATA 0x800000C0
+#define DDRSS0_CTL_152_DATA 0x800000C0
+#define DDRSS0_CTL_153_DATA 0x00000000
+#define DDRSS0_CTL_154_DATA 0x00001500
+#define DDRSS0_CTL_155_DATA 0x00000000
+#define DDRSS0_CTL_156_DATA 0x00000001
+#define DDRSS0_CTL_157_DATA 0x00000002
+#define DDRSS0_CTL_158_DATA 0x0000100E
+#define DDRSS0_CTL_159_DATA 0x00000000
+#define DDRSS0_CTL_160_DATA 0x00000000
+#define DDRSS0_CTL_161_DATA 0x00000000
+#define DDRSS0_CTL_162_DATA 0x00000000
+#define DDRSS0_CTL_163_DATA 0x00000000
+#define DDRSS0_CTL_164_DATA 0x000B0000
+#define DDRSS0_CTL_165_DATA 0x000E0006
+#define DDRSS0_CTL_166_DATA 0x000E0404
+#define DDRSS0_CTL_167_DATA 0x00D601AB
+#define DDRSS0_CTL_168_DATA 0x10100216
+#define DDRSS0_CTL_169_DATA 0x01AB0216
+#define DDRSS0_CTL_170_DATA 0x021600D6
+#define DDRSS0_CTL_171_DATA 0x02161010
+#define DDRSS0_CTL_172_DATA 0x00000000
+#define DDRSS0_CTL_173_DATA 0x00000000
+#define DDRSS0_CTL_174_DATA 0x00000000
+#define DDRSS0_CTL_175_DATA 0x3FF40084
+#define DDRSS0_CTL_176_DATA 0x33003FF4
+#define DDRSS0_CTL_177_DATA 0x00003333
+#define DDRSS0_CTL_178_DATA 0x56000000
+#define DDRSS0_CTL_179_DATA 0x27270056
+#define DDRSS0_CTL_180_DATA 0x0F0F0000
+#define DDRSS0_CTL_181_DATA 0x16000000
+#define DDRSS0_CTL_182_DATA 0x00841616
+#define DDRSS0_CTL_183_DATA 0x3FF43FF4
+#define DDRSS0_CTL_184_DATA 0x33333300
+#define DDRSS0_CTL_185_DATA 0x00000000
+#define DDRSS0_CTL_186_DATA 0x00565600
+#define DDRSS0_CTL_187_DATA 0x00002727
+#define DDRSS0_CTL_188_DATA 0x00000F0F
+#define DDRSS0_CTL_189_DATA 0x16161600
+#define DDRSS0_CTL_190_DATA 0x00000020
+#define DDRSS0_CTL_191_DATA 0x00000000
+#define DDRSS0_CTL_192_DATA 0x00000001
+#define DDRSS0_CTL_193_DATA 0x00000000
+#define DDRSS0_CTL_194_DATA 0x01000000
+#define DDRSS0_CTL_195_DATA 0x00000001
+#define DDRSS0_CTL_196_DATA 0x00000000
+#define DDRSS0_CTL_197_DATA 0x00000000
+#define DDRSS0_CTL_198_DATA 0x00000000
+#define DDRSS0_CTL_199_DATA 0x00000000
+#define DDRSS0_CTL_200_DATA 0x00000000
+#define DDRSS0_CTL_201_DATA 0x00000000
+#define DDRSS0_CTL_202_DATA 0x00000000
+#define DDRSS0_CTL_203_DATA 0x00000000
+#define DDRSS0_CTL_204_DATA 0x00000000
+#define DDRSS0_CTL_205_DATA 0x00000000
+#define DDRSS0_CTL_206_DATA 0x02000000
+#define DDRSS0_CTL_207_DATA 0x01080101
+#define DDRSS0_CTL_208_DATA 0x00000000
+#define DDRSS0_CTL_209_DATA 0x00000000
+#define DDRSS0_CTL_210_DATA 0x00000000
+#define DDRSS0_CTL_211_DATA 0x00000000
+#define DDRSS0_CTL_212_DATA 0x00000000
+#define DDRSS0_CTL_213_DATA 0x00000000
+#define DDRSS0_CTL_214_DATA 0x00000000
+#define DDRSS0_CTL_215_DATA 0x00000000
+#define DDRSS0_CTL_216_DATA 0x00000000
+#define DDRSS0_CTL_217_DATA 0x00000000
+#define DDRSS0_CTL_218_DATA 0x00000000
+#define DDRSS0_CTL_219_DATA 0x00000000
+#define DDRSS0_CTL_220_DATA 0x00000000
+#define DDRSS0_CTL_221_DATA 0x00000000
+#define DDRSS0_CTL_222_DATA 0x00001000
+#define DDRSS0_CTL_223_DATA 0x006403E8
+#define DDRSS0_CTL_224_DATA 0x00000000
+#define DDRSS0_CTL_225_DATA 0x00000000
+#define DDRSS0_CTL_226_DATA 0x00000000
+#define DDRSS0_CTL_227_DATA 0x15110000
+#define DDRSS0_CTL_228_DATA 0x00040C18
+#define DDRSS0_CTL_229_DATA 0x00000000
+#define DDRSS0_CTL_230_DATA 0x00000000
+#define DDRSS0_CTL_231_DATA 0x00000000
+#define DDRSS0_CTL_232_DATA 0x00000000
+#define DDRSS0_CTL_233_DATA 0x00000000
+#define DDRSS0_CTL_234_DATA 0x00000000
+#define DDRSS0_CTL_235_DATA 0x00000000
+#define DDRSS0_CTL_236_DATA 0x00000000
+#define DDRSS0_CTL_237_DATA 0x00000000
+#define DDRSS0_CTL_238_DATA 0x00000000
+#define DDRSS0_CTL_239_DATA 0x00000000
+#define DDRSS0_CTL_240_DATA 0x00000000
+#define DDRSS0_CTL_241_DATA 0x00000000
+#define DDRSS0_CTL_242_DATA 0x00030000
+#define DDRSS0_CTL_243_DATA 0x00000000
+#define DDRSS0_CTL_244_DATA 0x00000000
+#define DDRSS0_CTL_245_DATA 0x00000000
+#define DDRSS0_CTL_246_DATA 0x00000000
+#define DDRSS0_CTL_247_DATA 0x00000000
+#define DDRSS0_CTL_248_DATA 0x00000000
+#define DDRSS0_CTL_249_DATA 0x00000000
+#define DDRSS0_CTL_250_DATA 0x00000000
+#define DDRSS0_CTL_251_DATA 0x00000000
+#define DDRSS0_CTL_252_DATA 0x00000000
+#define DDRSS0_CTL_253_DATA 0x00000000
+#define DDRSS0_CTL_254_DATA 0x00000000
+#define DDRSS0_CTL_255_DATA 0x00000000
+#define DDRSS0_CTL_256_DATA 0x00000000
+#define DDRSS0_CTL_257_DATA 0x01000200
+#define DDRSS0_CTL_258_DATA 0x00370040
+#define DDRSS0_CTL_259_DATA 0x00020008
+#define DDRSS0_CTL_260_DATA 0x00400100
+#define DDRSS0_CTL_261_DATA 0x00400855
+#define DDRSS0_CTL_262_DATA 0x01000200
+#define DDRSS0_CTL_263_DATA 0x08550040
+#define DDRSS0_CTL_264_DATA 0x00000040
+#define DDRSS0_CTL_265_DATA 0x006B0003
+#define DDRSS0_CTL_266_DATA 0x0100006B
+#define DDRSS0_CTL_267_DATA 0x00000000
+#define DDRSS0_CTL_268_DATA 0x00000000
+#define DDRSS0_CTL_269_DATA 0x00000202
+#define DDRSS0_CTL_270_DATA 0x00001FFF
+#define DDRSS0_CTL_271_DATA 0x3FFF2000
+#define DDRSS0_CTL_272_DATA 0x03FF0000
+#define DDRSS0_CTL_273_DATA 0x000103FF
+#define DDRSS0_CTL_274_DATA 0x0FFF0B00
+#define DDRSS0_CTL_275_DATA 0x01010001
+#define DDRSS0_CTL_276_DATA 0x01010101
+#define DDRSS0_CTL_277_DATA 0x01180101
+#define DDRSS0_CTL_278_DATA 0x00030000
+#define DDRSS0_CTL_279_DATA 0x00000000
+#define DDRSS0_CTL_280_DATA 0x00000000
+#define DDRSS0_CTL_281_DATA 0x00000000
+#define DDRSS0_CTL_282_DATA 0x00000000
+#define DDRSS0_CTL_283_DATA 0x00000000
+#define DDRSS0_CTL_284_DATA 0x00000000
+#define DDRSS0_CTL_285_DATA 0x00000000
+#define DDRSS0_CTL_286_DATA 0x00040101
+#define DDRSS0_CTL_287_DATA 0x04010100
+#define DDRSS0_CTL_288_DATA 0x00000000
+#define DDRSS0_CTL_289_DATA 0x00000000
+#define DDRSS0_CTL_290_DATA 0x03030300
+#define DDRSS0_CTL_291_DATA 0x00000001
+#define DDRSS0_CTL_292_DATA 0x00000000
+#define DDRSS0_CTL_293_DATA 0x00000000
+#define DDRSS0_CTL_294_DATA 0x00000000
+#define DDRSS0_CTL_295_DATA 0x00000000
+#define DDRSS0_CTL_296_DATA 0x00000000
+#define DDRSS0_CTL_297_DATA 0x00000000
+#define DDRSS0_CTL_298_DATA 0x00000000
+#define DDRSS0_CTL_299_DATA 0x00000000
+#define DDRSS0_CTL_300_DATA 0x00000000
+#define DDRSS0_CTL_301_DATA 0x00000000
+#define DDRSS0_CTL_302_DATA 0x00000000
+#define DDRSS0_CTL_303_DATA 0x00000000
+#define DDRSS0_CTL_304_DATA 0x00000000
+#define DDRSS0_CTL_305_DATA 0x00000000
+#define DDRSS0_CTL_306_DATA 0x00000000
+#define DDRSS0_CTL_307_DATA 0x00000000
+#define DDRSS0_CTL_308_DATA 0x00000000
+#define DDRSS0_CTL_309_DATA 0x00000000
+#define DDRSS0_CTL_310_DATA 0x00000000
+#define DDRSS0_CTL_311_DATA 0x00000000
+#define DDRSS0_CTL_312_DATA 0x00000000
+#define DDRSS0_CTL_313_DATA 0x01000000
+#define DDRSS0_CTL_314_DATA 0x00020201
+#define DDRSS0_CTL_315_DATA 0x01000101
+#define DDRSS0_CTL_316_DATA 0x01010001
+#define DDRSS0_CTL_317_DATA 0x00010101
+#define DDRSS0_CTL_318_DATA 0x050A0A03
+#define DDRSS0_CTL_319_DATA 0x10081F1F
+#define DDRSS0_CTL_320_DATA 0x00090310
+#define DDRSS0_CTL_321_DATA 0x0B0C030F
+#define DDRSS0_CTL_322_DATA 0x0B0C0306
+#define DDRSS0_CTL_323_DATA 0x0C090006
+#define DDRSS0_CTL_324_DATA 0x0100000C
+#define DDRSS0_CTL_325_DATA 0x08040801
+#define DDRSS0_CTL_326_DATA 0x00000004
+#define DDRSS0_CTL_327_DATA 0x00000000
+#define DDRSS0_CTL_328_DATA 0x00010000
+#define DDRSS0_CTL_329_DATA 0x00280D00
+#define DDRSS0_CTL_330_DATA 0x00000001
+#define DDRSS0_CTL_331_DATA 0x00030001
+#define DDRSS0_CTL_332_DATA 0x00000000
+#define DDRSS0_CTL_333_DATA 0x00000000
+#define DDRSS0_CTL_334_DATA 0x00000000
+#define DDRSS0_CTL_335_DATA 0x00000000
+#define DDRSS0_CTL_336_DATA 0x00000000
+#define DDRSS0_CTL_337_DATA 0x00000000
+#define DDRSS0_CTL_338_DATA 0x00000000
+#define DDRSS0_CTL_339_DATA 0x00000000
+#define DDRSS0_CTL_340_DATA 0x01000000
+#define DDRSS0_CTL_341_DATA 0x00000001
+#define DDRSS0_CTL_342_DATA 0x00010100
+#define DDRSS0_CTL_343_DATA 0x03030000
+#define DDRSS0_CTL_344_DATA 0x00000000
+#define DDRSS0_CTL_345_DATA 0x00000000
+#define DDRSS0_CTL_346_DATA 0x00000000
+#define DDRSS0_CTL_347_DATA 0x00000000
+#define DDRSS0_CTL_348_DATA 0x00000000
+#define DDRSS0_CTL_349_DATA 0x00000000
+#define DDRSS0_CTL_350_DATA 0x00000000
+#define DDRSS0_CTL_351_DATA 0x00000000
+#define DDRSS0_CTL_352_DATA 0x00000000
+#define DDRSS0_CTL_353_DATA 0x00000000
+#define DDRSS0_CTL_354_DATA 0x00000000
+#define DDRSS0_CTL_355_DATA 0x00000000
+#define DDRSS0_CTL_356_DATA 0x00000000
+#define DDRSS0_CTL_357_DATA 0x00000000
+#define DDRSS0_CTL_358_DATA 0x00000000
+#define DDRSS0_CTL_359_DATA 0x00000000
+#define DDRSS0_CTL_360_DATA 0x000556AA
+#define DDRSS0_CTL_361_DATA 0x000AAAAA
+#define DDRSS0_CTL_362_DATA 0x000AA955
+#define DDRSS0_CTL_363_DATA 0x00055555
+#define DDRSS0_CTL_364_DATA 0x000B3133
+#define DDRSS0_CTL_365_DATA 0x0004CD33
+#define DDRSS0_CTL_366_DATA 0x0004CECC
+#define DDRSS0_CTL_367_DATA 0x000B32CC
+#define DDRSS0_CTL_368_DATA 0x00010300
+#define DDRSS0_CTL_369_DATA 0x03000100
+#define DDRSS0_CTL_370_DATA 0x00000000
+#define DDRSS0_CTL_371_DATA 0x00000000
+#define DDRSS0_CTL_372_DATA 0x00000000
+#define DDRSS0_CTL_373_DATA 0x00000000
+#define DDRSS0_CTL_374_DATA 0x00000000
+#define DDRSS0_CTL_375_DATA 0x00000000
+#define DDRSS0_CTL_376_DATA 0x00000000
+#define DDRSS0_CTL_377_DATA 0x00010000
+#define DDRSS0_CTL_378_DATA 0x00000404
+#define DDRSS0_CTL_379_DATA 0x00000000
+#define DDRSS0_CTL_380_DATA 0x00000000
+#define DDRSS0_CTL_381_DATA 0x00000000
+#define DDRSS0_CTL_382_DATA 0x00000000
+#define DDRSS0_CTL_383_DATA 0x00000000
+#define DDRSS0_CTL_384_DATA 0x00000000
+#define DDRSS0_CTL_385_DATA 0x00000000
+#define DDRSS0_CTL_386_DATA 0x00000000
+#define DDRSS0_CTL_387_DATA 0x3A3A1B00
+#define DDRSS0_CTL_388_DATA 0x000A0000
+#define DDRSS0_CTL_389_DATA 0x0000019C
+#define DDRSS0_CTL_390_DATA 0x00000200
+#define DDRSS0_CTL_391_DATA 0x00000200
+#define DDRSS0_CTL_392_DATA 0x00000200
+#define DDRSS0_CTL_393_DATA 0x00000200
+#define DDRSS0_CTL_394_DATA 0x000004D4
+#define DDRSS0_CTL_395_DATA 0x00001018
+#define DDRSS0_CTL_396_DATA 0x00000204
+#define DDRSS0_CTL_397_DATA 0x000040E6
+#define DDRSS0_CTL_398_DATA 0x00000200
+#define DDRSS0_CTL_399_DATA 0x00000200
+#define DDRSS0_CTL_400_DATA 0x00000200
+#define DDRSS0_CTL_401_DATA 0x00000200
+#define DDRSS0_CTL_402_DATA 0x0000C2B2
+#define DDRSS0_CTL_403_DATA 0x000288FC
+#define DDRSS0_CTL_404_DATA 0x00000E15
+#define DDRSS0_CTL_405_DATA 0x000040E6
+#define DDRSS0_CTL_406_DATA 0x00000200
+#define DDRSS0_CTL_407_DATA 0x00000200
+#define DDRSS0_CTL_408_DATA 0x00000200
+#define DDRSS0_CTL_409_DATA 0x00000200
+#define DDRSS0_CTL_410_DATA 0x0000C2B2
+#define DDRSS0_CTL_411_DATA 0x000288FC
+#define DDRSS0_CTL_412_DATA 0x02020E15
+#define DDRSS0_CTL_413_DATA 0x03030202
+#define DDRSS0_CTL_414_DATA 0x00000022
+#define DDRSS0_CTL_415_DATA 0x00000000
+#define DDRSS0_CTL_416_DATA 0x00000000
+#define DDRSS0_CTL_417_DATA 0x00001403
+#define DDRSS0_CTL_418_DATA 0x000007D0
+#define DDRSS0_CTL_419_DATA 0x00000000
+#define DDRSS0_CTL_420_DATA 0x00000000
+#define DDRSS0_CTL_421_DATA 0x00030000
+#define DDRSS0_CTL_422_DATA 0x0007001F
+#define DDRSS0_CTL_423_DATA 0x001B0033
+#define DDRSS0_CTL_424_DATA 0x001B0033
+#define DDRSS0_CTL_425_DATA 0x00000000
+#define DDRSS0_CTL_426_DATA 0x00000000
+#define DDRSS0_CTL_427_DATA 0x02000000
+#define DDRSS0_CTL_428_DATA 0x01000404
+#define DDRSS0_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS0_CTL_430_DATA 0x00000105
+#define DDRSS0_CTL_431_DATA 0x00010101
+#define DDRSS0_CTL_432_DATA 0x00010101
+#define DDRSS0_CTL_433_DATA 0x00010001
+#define DDRSS0_CTL_434_DATA 0x00000101
+#define DDRSS0_CTL_435_DATA 0x02000201
+#define DDRSS0_CTL_436_DATA 0x02010000
+#define DDRSS0_CTL_437_DATA 0x00000200
+#define DDRSS0_CTL_438_DATA 0x28060000
+#define DDRSS0_CTL_439_DATA 0x00000128
+#define DDRSS0_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_442_DATA 0x00000000
+#define DDRSS0_CTL_443_DATA 0x00000000
+#define DDRSS0_CTL_444_DATA 0x00000000
+#define DDRSS0_CTL_445_DATA 0x00000000
+#define DDRSS0_CTL_446_DATA 0x00000000
+#define DDRSS0_CTL_447_DATA 0x00000000
+#define DDRSS0_CTL_448_DATA 0x00000000
+#define DDRSS0_CTL_449_DATA 0x00000000
+#define DDRSS0_CTL_450_DATA 0x00000000
+#define DDRSS0_CTL_451_DATA 0x00000000
+#define DDRSS0_CTL_452_DATA 0x00000000
+#define DDRSS0_CTL_453_DATA 0x00000000
+#define DDRSS0_CTL_454_DATA 0x00000000
+#define DDRSS0_CTL_455_DATA 0x00000000
+#define DDRSS0_CTL_456_DATA 0x00000000
+#define DDRSS0_CTL_457_DATA 0x00000000
+#define DDRSS0_CTL_458_DATA 0x00000000
+
+#define DDRSS0_PI_00_DATA 0x00000B00
+#define DDRSS0_PI_01_DATA 0x00000000
+#define DDRSS0_PI_02_DATA 0x00000000
+#define DDRSS0_PI_03_DATA 0x00000000
+#define DDRSS0_PI_04_DATA 0x00000000
+#define DDRSS0_PI_05_DATA 0x00000101
+#define DDRSS0_PI_06_DATA 0x00640000
+#define DDRSS0_PI_07_DATA 0x00000001
+#define DDRSS0_PI_08_DATA 0x00000000
+#define DDRSS0_PI_09_DATA 0x00000000
+#define DDRSS0_PI_10_DATA 0x00000000
+#define DDRSS0_PI_11_DATA 0x00000000
+#define DDRSS0_PI_12_DATA 0x00000007
+#define DDRSS0_PI_13_DATA 0x00010002
+#define DDRSS0_PI_14_DATA 0x0800000F
+#define DDRSS0_PI_15_DATA 0x00000103
+#define DDRSS0_PI_16_DATA 0x00000005
+#define DDRSS0_PI_17_DATA 0x00000000
+#define DDRSS0_PI_18_DATA 0x00000000
+#define DDRSS0_PI_19_DATA 0x00000000
+#define DDRSS0_PI_20_DATA 0x00000000
+#define DDRSS0_PI_21_DATA 0x00000000
+#define DDRSS0_PI_22_DATA 0x00000000
+#define DDRSS0_PI_23_DATA 0x00000000
+#define DDRSS0_PI_24_DATA 0x00000000
+#define DDRSS0_PI_25_DATA 0x00000000
+#define DDRSS0_PI_26_DATA 0x00010100
+#define DDRSS0_PI_27_DATA 0x00280A00
+#define DDRSS0_PI_28_DATA 0x00000000
+#define DDRSS0_PI_29_DATA 0x0F000000
+#define DDRSS0_PI_30_DATA 0x00003200
+#define DDRSS0_PI_31_DATA 0x00000000
+#define DDRSS0_PI_32_DATA 0x00000000
+#define DDRSS0_PI_33_DATA 0x01010102
+#define DDRSS0_PI_34_DATA 0x00000000
+#define DDRSS0_PI_35_DATA 0x000000AA
+#define DDRSS0_PI_36_DATA 0x00000055
+#define DDRSS0_PI_37_DATA 0x000000B5
+#define DDRSS0_PI_38_DATA 0x0000004A
+#define DDRSS0_PI_39_DATA 0x00000056
+#define DDRSS0_PI_40_DATA 0x000000A9
+#define DDRSS0_PI_41_DATA 0x000000A9
+#define DDRSS0_PI_42_DATA 0x000000B5
+#define DDRSS0_PI_43_DATA 0x00000000
+#define DDRSS0_PI_44_DATA 0x00000000
+#define DDRSS0_PI_45_DATA 0x000F0F00
+#define DDRSS0_PI_46_DATA 0x0000001B
+#define DDRSS0_PI_47_DATA 0x000007D0
+#define DDRSS0_PI_48_DATA 0x00000300
+#define DDRSS0_PI_49_DATA 0x00000000
+#define DDRSS0_PI_50_DATA 0x00000000
+#define DDRSS0_PI_51_DATA 0x01000000
+#define DDRSS0_PI_52_DATA 0x00010101
+#define DDRSS0_PI_53_DATA 0x00000000
+#define DDRSS0_PI_54_DATA 0x00030000
+#define DDRSS0_PI_55_DATA 0x0F000000
+#define DDRSS0_PI_56_DATA 0x00000017
+#define DDRSS0_PI_57_DATA 0x00000000
+#define DDRSS0_PI_58_DATA 0x00000000
+#define DDRSS0_PI_59_DATA 0x00000000
+#define DDRSS0_PI_60_DATA 0x0A0A140A
+#define DDRSS0_PI_61_DATA 0x10020101
+#define DDRSS0_PI_62_DATA 0x00020805
+#define DDRSS0_PI_63_DATA 0x01000404
+#define DDRSS0_PI_64_DATA 0x00000000
+#define DDRSS0_PI_65_DATA 0x00000000
+#define DDRSS0_PI_66_DATA 0x00000100
+#define DDRSS0_PI_67_DATA 0x0001010F
+#define DDRSS0_PI_68_DATA 0x00340000
+#define DDRSS0_PI_69_DATA 0x00000000
+#define DDRSS0_PI_70_DATA 0x00000000
+#define DDRSS0_PI_71_DATA 0x0000FFFF
+#define DDRSS0_PI_72_DATA 0x00000000
+#define DDRSS0_PI_73_DATA 0x00080000
+#define DDRSS0_PI_74_DATA 0x02000200
+#define DDRSS0_PI_75_DATA 0x01000100
+#define DDRSS0_PI_76_DATA 0x01000000
+#define DDRSS0_PI_77_DATA 0x02000200
+#define DDRSS0_PI_78_DATA 0x00000200
+#define DDRSS0_PI_79_DATA 0x00000000
+#define DDRSS0_PI_80_DATA 0x00000000
+#define DDRSS0_PI_81_DATA 0x00000000
+#define DDRSS0_PI_82_DATA 0x00000000
+#define DDRSS0_PI_83_DATA 0x00000000
+#define DDRSS0_PI_84_DATA 0x00000000
+#define DDRSS0_PI_85_DATA 0x00000000
+#define DDRSS0_PI_86_DATA 0x00000000
+#define DDRSS0_PI_87_DATA 0x00000000
+#define DDRSS0_PI_88_DATA 0x00000000
+#define DDRSS0_PI_89_DATA 0x00000000
+#define DDRSS0_PI_90_DATA 0x00000000
+#define DDRSS0_PI_91_DATA 0x00000400
+#define DDRSS0_PI_92_DATA 0x02010000
+#define DDRSS0_PI_93_DATA 0x00080003
+#define DDRSS0_PI_94_DATA 0x00080000
+#define DDRSS0_PI_95_DATA 0x00000001
+#define DDRSS0_PI_96_DATA 0x00000000
+#define DDRSS0_PI_97_DATA 0x0000AA00
+#define DDRSS0_PI_98_DATA 0x00000000
+#define DDRSS0_PI_99_DATA 0x00000000
+#define DDRSS0_PI_100_DATA 0x00010000
+#define DDRSS0_PI_101_DATA 0x00000000
+#define DDRSS0_PI_102_DATA 0x00000000
+#define DDRSS0_PI_103_DATA 0x00000000
+#define DDRSS0_PI_104_DATA 0x00000000
+#define DDRSS0_PI_105_DATA 0x00000000
+#define DDRSS0_PI_106_DATA 0x00000000
+#define DDRSS0_PI_107_DATA 0x00000000
+#define DDRSS0_PI_108_DATA 0x00000000
+#define DDRSS0_PI_109_DATA 0x00000000
+#define DDRSS0_PI_110_DATA 0x00000000
+#define DDRSS0_PI_111_DATA 0x00000000
+#define DDRSS0_PI_112_DATA 0x00000000
+#define DDRSS0_PI_113_DATA 0x00000000
+#define DDRSS0_PI_114_DATA 0x00000000
+#define DDRSS0_PI_115_DATA 0x00000000
+#define DDRSS0_PI_116_DATA 0x00000000
+#define DDRSS0_PI_117_DATA 0x00000000
+#define DDRSS0_PI_118_DATA 0x00000000
+#define DDRSS0_PI_119_DATA 0x00000000
+#define DDRSS0_PI_120_DATA 0x00000000
+#define DDRSS0_PI_121_DATA 0x00000000
+#define DDRSS0_PI_122_DATA 0x00000000
+#define DDRSS0_PI_123_DATA 0x00000000
+#define DDRSS0_PI_124_DATA 0x00000000
+#define DDRSS0_PI_125_DATA 0x00000008
+#define DDRSS0_PI_126_DATA 0x00000000
+#define DDRSS0_PI_127_DATA 0x00000000
+#define DDRSS0_PI_128_DATA 0x00000000
+#define DDRSS0_PI_129_DATA 0x00000000
+#define DDRSS0_PI_130_DATA 0x00000000
+#define DDRSS0_PI_131_DATA 0x00000000
+#define DDRSS0_PI_132_DATA 0x00000000
+#define DDRSS0_PI_133_DATA 0x00000000
+#define DDRSS0_PI_134_DATA 0x00000002
+#define DDRSS0_PI_135_DATA 0x00000000
+#define DDRSS0_PI_136_DATA 0x00000000
+#define DDRSS0_PI_137_DATA 0x0000000A
+#define DDRSS0_PI_138_DATA 0x00000019
+#define DDRSS0_PI_139_DATA 0x00000100
+#define DDRSS0_PI_140_DATA 0x00000000
+#define DDRSS0_PI_141_DATA 0x00000000
+#define DDRSS0_PI_142_DATA 0x00000000
+#define DDRSS0_PI_143_DATA 0x00000000
+#define DDRSS0_PI_144_DATA 0x01000000
+#define DDRSS0_PI_145_DATA 0x00010003
+#define DDRSS0_PI_146_DATA 0x02000101
+#define DDRSS0_PI_147_DATA 0x01030001
+#define DDRSS0_PI_148_DATA 0x00010400
+#define DDRSS0_PI_149_DATA 0x06000105
+#define DDRSS0_PI_150_DATA 0x01070001
+#define DDRSS0_PI_151_DATA 0x00000000
+#define DDRSS0_PI_152_DATA 0x00000000
+#define DDRSS0_PI_153_DATA 0x00000000
+#define DDRSS0_PI_154_DATA 0x00010001
+#define DDRSS0_PI_155_DATA 0x00000000
+#define DDRSS0_PI_156_DATA 0x00000000
+#define DDRSS0_PI_157_DATA 0x00000000
+#define DDRSS0_PI_158_DATA 0x00000000
+#define DDRSS0_PI_159_DATA 0x00000401
+#define DDRSS0_PI_160_DATA 0x00000000
+#define DDRSS0_PI_161_DATA 0x00010000
+#define DDRSS0_PI_162_DATA 0x00000000
+#define DDRSS0_PI_163_DATA 0x2B2B0200
+#define DDRSS0_PI_164_DATA 0x00000034
+#define DDRSS0_PI_165_DATA 0x00000064
+#define DDRSS0_PI_166_DATA 0x00020064
+#define DDRSS0_PI_167_DATA 0x02000200
+#define DDRSS0_PI_168_DATA 0x48120C04
+#define DDRSS0_PI_169_DATA 0x00154812
+#define DDRSS0_PI_170_DATA 0x000000CE
+#define DDRSS0_PI_171_DATA 0x0000032B
+#define DDRSS0_PI_172_DATA 0x00002073
+#define DDRSS0_PI_173_DATA 0x0000032B
+#define DDRSS0_PI_174_DATA 0x04002073
+#define DDRSS0_PI_175_DATA 0x01010404
+#define DDRSS0_PI_176_DATA 0x00001501
+#define DDRSS0_PI_177_DATA 0x00150015
+#define DDRSS0_PI_178_DATA 0x01000100
+#define DDRSS0_PI_179_DATA 0x00000100
+#define DDRSS0_PI_180_DATA 0x00000000
+#define DDRSS0_PI_181_DATA 0x01010101
+#define DDRSS0_PI_182_DATA 0x00000101
+#define DDRSS0_PI_183_DATA 0x00000000
+#define DDRSS0_PI_184_DATA 0x00000000
+#define DDRSS0_PI_185_DATA 0x15040000
+#define DDRSS0_PI_186_DATA 0x0E0E0215
+#define DDRSS0_PI_187_DATA 0x00040402
+#define DDRSS0_PI_188_DATA 0x000D0035
+#define DDRSS0_PI_189_DATA 0x00218049
+#define DDRSS0_PI_190_DATA 0x00218049
+#define DDRSS0_PI_191_DATA 0x01010101
+#define DDRSS0_PI_192_DATA 0x0004000E
+#define DDRSS0_PI_193_DATA 0x00040216
+#define DDRSS0_PI_194_DATA 0x01000216
+#define DDRSS0_PI_195_DATA 0x000F000F
+#define DDRSS0_PI_196_DATA 0x02170100
+#define DDRSS0_PI_197_DATA 0x01000217
+#define DDRSS0_PI_198_DATA 0x02170217
+#define DDRSS0_PI_199_DATA 0x32103200
+#define DDRSS0_PI_200_DATA 0x01013210
+#define DDRSS0_PI_201_DATA 0x0A070601
+#define DDRSS0_PI_202_DATA 0x1F130A0D
+#define DDRSS0_PI_203_DATA 0x1F130A14
+#define DDRSS0_PI_204_DATA 0x0000C014
+#define DDRSS0_PI_205_DATA 0x00C01000
+#define DDRSS0_PI_206_DATA 0x00C01000
+#define DDRSS0_PI_207_DATA 0x00021000
+#define DDRSS0_PI_208_DATA 0x0024000E
+#define DDRSS0_PI_209_DATA 0x00240216
+#define DDRSS0_PI_210_DATA 0x00110216
+#define DDRSS0_PI_211_DATA 0x32000056
+#define DDRSS0_PI_212_DATA 0x00000301
+#define DDRSS0_PI_213_DATA 0x005B0036
+#define DDRSS0_PI_214_DATA 0x03013212
+#define DDRSS0_PI_215_DATA 0x00003600
+#define DDRSS0_PI_216_DATA 0x3212005B
+#define DDRSS0_PI_217_DATA 0x09000301
+#define DDRSS0_PI_218_DATA 0x04010504
+#define DDRSS0_PI_219_DATA 0x040006C9
+#define DDRSS0_PI_220_DATA 0x0A032001
+#define DDRSS0_PI_221_DATA 0x2C31110A
+#define DDRSS0_PI_222_DATA 0x00002918
+#define DDRSS0_PI_223_DATA 0x6001071C
+#define DDRSS0_PI_224_DATA 0x1E202008
+#define DDRSS0_PI_225_DATA 0x2C311116
+#define DDRSS0_PI_226_DATA 0x00002918
+#define DDRSS0_PI_227_DATA 0x6001071C
+#define DDRSS0_PI_228_DATA 0x1E202008
+#define DDRSS0_PI_229_DATA 0x00019C16
+#define DDRSS0_PI_230_DATA 0x00001018
+#define DDRSS0_PI_231_DATA 0x000040E6
+#define DDRSS0_PI_232_DATA 0x000288FC
+#define DDRSS0_PI_233_DATA 0x000040E6
+#define DDRSS0_PI_234_DATA 0x000288FC
+#define DDRSS0_PI_235_DATA 0x033B0016
+#define DDRSS0_PI_236_DATA 0x0303033B
+#define DDRSS0_PI_237_DATA 0x002AF803
+#define DDRSS0_PI_238_DATA 0x0001ADAF
+#define DDRSS0_PI_239_DATA 0x00000005
+#define DDRSS0_PI_240_DATA 0x0000006E
+#define DDRSS0_PI_241_DATA 0x00000016
+#define DDRSS0_PI_242_DATA 0x000681C8
+#define DDRSS0_PI_243_DATA 0x0001ADAF
+#define DDRSS0_PI_244_DATA 0x00000005
+#define DDRSS0_PI_245_DATA 0x000010A9
+#define DDRSS0_PI_246_DATA 0x0000033B
+#define DDRSS0_PI_247_DATA 0x000681C8
+#define DDRSS0_PI_248_DATA 0x0001ADAF
+#define DDRSS0_PI_249_DATA 0x00000005
+#define DDRSS0_PI_250_DATA 0x000010A9
+#define DDRSS0_PI_251_DATA 0x0100033B
+#define DDRSS0_PI_252_DATA 0x00370040
+#define DDRSS0_PI_253_DATA 0x00010008
+#define DDRSS0_PI_254_DATA 0x08550040
+#define DDRSS0_PI_255_DATA 0x00010040
+#define DDRSS0_PI_256_DATA 0x08550040
+#define DDRSS0_PI_257_DATA 0x00000340
+#define DDRSS0_PI_258_DATA 0x006B006B
+#define DDRSS0_PI_259_DATA 0x08040404
+#define DDRSS0_PI_260_DATA 0x00000055
+#define DDRSS0_PI_261_DATA 0x55083C5A
+#define DDRSS0_PI_262_DATA 0x5A000000
+#define DDRSS0_PI_263_DATA 0x0055083C
+#define DDRSS0_PI_264_DATA 0x3C5A0000
+#define DDRSS0_PI_265_DATA 0x00005508
+#define DDRSS0_PI_266_DATA 0x0C3C5A00
+#define DDRSS0_PI_267_DATA 0x080F0E0D
+#define DDRSS0_PI_268_DATA 0x000B0A09
+#define DDRSS0_PI_269_DATA 0x00030201
+#define DDRSS0_PI_270_DATA 0x01000000
+#define DDRSS0_PI_271_DATA 0x04020201
+#define DDRSS0_PI_272_DATA 0x00080804
+#define DDRSS0_PI_273_DATA 0x00000000
+#define DDRSS0_PI_274_DATA 0x00000000
+#define DDRSS0_PI_275_DATA 0x00330084
+#define DDRSS0_PI_276_DATA 0x00160000
+#define DDRSS0_PI_277_DATA 0x56333FF4
+#define DDRSS0_PI_278_DATA 0x00160F27
+#define DDRSS0_PI_279_DATA 0x56333FF4
+#define DDRSS0_PI_280_DATA 0x00160F27
+#define DDRSS0_PI_281_DATA 0x00330084
+#define DDRSS0_PI_282_DATA 0x00160000
+#define DDRSS0_PI_283_DATA 0x56333FF4
+#define DDRSS0_PI_284_DATA 0x00160F27
+#define DDRSS0_PI_285_DATA 0x56333FF4
+#define DDRSS0_PI_286_DATA 0x00160F27
+#define DDRSS0_PI_287_DATA 0x00330084
+#define DDRSS0_PI_288_DATA 0x00160000
+#define DDRSS0_PI_289_DATA 0x56333FF4
+#define DDRSS0_PI_290_DATA 0x00160F27
+#define DDRSS0_PI_291_DATA 0x56333FF4
+#define DDRSS0_PI_292_DATA 0x00160F27
+#define DDRSS0_PI_293_DATA 0x00330084
+#define DDRSS0_PI_294_DATA 0x00160000
+#define DDRSS0_PI_295_DATA 0x56333FF4
+#define DDRSS0_PI_296_DATA 0x00160F27
+#define DDRSS0_PI_297_DATA 0x56333FF4
+#define DDRSS0_PI_298_DATA 0x00160F27
+#define DDRSS0_PI_299_DATA 0x00000000
+
+#define DDRSS0_PHY_00_DATA 0x000004F0
+#define DDRSS0_PHY_01_DATA 0x00000000
+#define DDRSS0_PHY_02_DATA 0x00030200
+#define DDRSS0_PHY_03_DATA 0x00000000
+#define DDRSS0_PHY_04_DATA 0x00000000
+#define DDRSS0_PHY_05_DATA 0x01030000
+#define DDRSS0_PHY_06_DATA 0x00010000
+#define DDRSS0_PHY_07_DATA 0x01030004
+#define DDRSS0_PHY_08_DATA 0x01000000
+#define DDRSS0_PHY_09_DATA 0x00000000
+#define DDRSS0_PHY_10_DATA 0x00000000
+#define DDRSS0_PHY_11_DATA 0x01000001
+#define DDRSS0_PHY_12_DATA 0x00000100
+#define DDRSS0_PHY_13_DATA 0x000800C0
+#define DDRSS0_PHY_14_DATA 0x060100CC
+#define DDRSS0_PHY_15_DATA 0x00030066
+#define DDRSS0_PHY_16_DATA 0x00000000
+#define DDRSS0_PHY_17_DATA 0x00000301
+#define DDRSS0_PHY_18_DATA 0x0000AAAA
+#define DDRSS0_PHY_19_DATA 0x00005555
+#define DDRSS0_PHY_20_DATA 0x0000B5B5
+#define DDRSS0_PHY_21_DATA 0x00004A4A
+#define DDRSS0_PHY_22_DATA 0x00005656
+#define DDRSS0_PHY_23_DATA 0x0000A9A9
+#define DDRSS0_PHY_24_DATA 0x0000A9A9
+#define DDRSS0_PHY_25_DATA 0x0000B5B5
+#define DDRSS0_PHY_26_DATA 0x00000000
+#define DDRSS0_PHY_27_DATA 0x00000000
+#define DDRSS0_PHY_28_DATA 0x2A000000
+#define DDRSS0_PHY_29_DATA 0x00000808
+#define DDRSS0_PHY_30_DATA 0x0F000000
+#define DDRSS0_PHY_31_DATA 0x00000F0F
+#define DDRSS0_PHY_32_DATA 0x10200000
+#define DDRSS0_PHY_33_DATA 0x0C002006
+#define DDRSS0_PHY_34_DATA 0x00000000
+#define DDRSS0_PHY_35_DATA 0x00000000
+#define DDRSS0_PHY_36_DATA 0x55555555
+#define DDRSS0_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_38_DATA 0x55555555
+#define DDRSS0_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_40_DATA 0x00005555
+#define DDRSS0_PHY_41_DATA 0x01000100
+#define DDRSS0_PHY_42_DATA 0x00800180
+#define DDRSS0_PHY_43_DATA 0x00000001
+#define DDRSS0_PHY_44_DATA 0x00000000
+#define DDRSS0_PHY_45_DATA 0x00000000
+#define DDRSS0_PHY_46_DATA 0x00000000
+#define DDRSS0_PHY_47_DATA 0x00000000
+#define DDRSS0_PHY_48_DATA 0x00000000
+#define DDRSS0_PHY_49_DATA 0x00000000
+#define DDRSS0_PHY_50_DATA 0x00000000
+#define DDRSS0_PHY_51_DATA 0x00000000
+#define DDRSS0_PHY_52_DATA 0x00000000
+#define DDRSS0_PHY_53_DATA 0x00000000
+#define DDRSS0_PHY_54_DATA 0x00000000
+#define DDRSS0_PHY_55_DATA 0x00000000
+#define DDRSS0_PHY_56_DATA 0x00000000
+#define DDRSS0_PHY_57_DATA 0x00000000
+#define DDRSS0_PHY_58_DATA 0x00000000
+#define DDRSS0_PHY_59_DATA 0x00000000
+#define DDRSS0_PHY_60_DATA 0x00000000
+#define DDRSS0_PHY_61_DATA 0x00000000
+#define DDRSS0_PHY_62_DATA 0x00000000
+#define DDRSS0_PHY_63_DATA 0x00000000
+#define DDRSS0_PHY_64_DATA 0x00000000
+#define DDRSS0_PHY_65_DATA 0x00000000
+#define DDRSS0_PHY_66_DATA 0x00000104
+#define DDRSS0_PHY_67_DATA 0x00000120
+#define DDRSS0_PHY_68_DATA 0x00000000
+#define DDRSS0_PHY_69_DATA 0x00000000
+#define DDRSS0_PHY_70_DATA 0x00000000
+#define DDRSS0_PHY_71_DATA 0x00000000
+#define DDRSS0_PHY_72_DATA 0x00000000
+#define DDRSS0_PHY_73_DATA 0x00000000
+#define DDRSS0_PHY_74_DATA 0x00000000
+#define DDRSS0_PHY_75_DATA 0x00000001
+#define DDRSS0_PHY_76_DATA 0x07FF0000
+#define DDRSS0_PHY_77_DATA 0x0080081F
+#define DDRSS0_PHY_78_DATA 0x00081020
+#define DDRSS0_PHY_79_DATA 0x04010000
+#define DDRSS0_PHY_80_DATA 0x00000000
+#define DDRSS0_PHY_81_DATA 0x00000000
+#define DDRSS0_PHY_82_DATA 0x00000000
+#define DDRSS0_PHY_83_DATA 0x00000100
+#define DDRSS0_PHY_84_DATA 0x01CC0C01
+#define DDRSS0_PHY_85_DATA 0x1003CC0C
+#define DDRSS0_PHY_86_DATA 0x20000140
+#define DDRSS0_PHY_87_DATA 0x07FF0200
+#define DDRSS0_PHY_88_DATA 0x0000DD01
+#define DDRSS0_PHY_89_DATA 0x10100303
+#define DDRSS0_PHY_90_DATA 0x10101010
+#define DDRSS0_PHY_91_DATA 0x10101010
+#define DDRSS0_PHY_92_DATA 0x00021010
+#define DDRSS0_PHY_93_DATA 0x00100010
+#define DDRSS0_PHY_94_DATA 0x00100010
+#define DDRSS0_PHY_95_DATA 0x00100010
+#define DDRSS0_PHY_96_DATA 0x00100010
+#define DDRSS0_PHY_97_DATA 0x00050010
+#define DDRSS0_PHY_98_DATA 0x51517041
+#define DDRSS0_PHY_99_DATA 0x31C06001
+#define DDRSS0_PHY_100_DATA 0x07AB0340
+#define DDRSS0_PHY_101_DATA 0x00C0C001
+#define DDRSS0_PHY_102_DATA 0x0E0D0001
+#define DDRSS0_PHY_103_DATA 0x10001000
+#define DDRSS0_PHY_104_DATA 0x0C083E42
+#define DDRSS0_PHY_105_DATA 0x0F0C3701
+#define DDRSS0_PHY_106_DATA 0x01000140
+#define DDRSS0_PHY_107_DATA 0x0C000420
+#define DDRSS0_PHY_108_DATA 0x00000198
+#define DDRSS0_PHY_109_DATA 0x0A0000D0
+#define DDRSS0_PHY_110_DATA 0x00030200
+#define DDRSS0_PHY_111_DATA 0x02800000
+#define DDRSS0_PHY_112_DATA 0x80800000
+#define DDRSS0_PHY_113_DATA 0x000E2010
+#define DDRSS0_PHY_114_DATA 0x76543210
+#define DDRSS0_PHY_115_DATA 0x00000008
+#define DDRSS0_PHY_116_DATA 0x02800280
+#define DDRSS0_PHY_117_DATA 0x02800280
+#define DDRSS0_PHY_118_DATA 0x02800280
+#define DDRSS0_PHY_119_DATA 0x02800280
+#define DDRSS0_PHY_120_DATA 0x00000280
+#define DDRSS0_PHY_121_DATA 0x0000A000
+#define DDRSS0_PHY_122_DATA 0x00A000A0
+#define DDRSS0_PHY_123_DATA 0x00A000A0
+#define DDRSS0_PHY_124_DATA 0x00A000A0
+#define DDRSS0_PHY_125_DATA 0x00A000A0
+#define DDRSS0_PHY_126_DATA 0x00A000A0
+#define DDRSS0_PHY_127_DATA 0x00A000A0
+#define DDRSS0_PHY_128_DATA 0x00A000A0
+#define DDRSS0_PHY_129_DATA 0x00A000A0
+#define DDRSS0_PHY_130_DATA 0x01C200A0
+#define DDRSS0_PHY_131_DATA 0x01A00005
+#define DDRSS0_PHY_132_DATA 0x00000000
+#define DDRSS0_PHY_133_DATA 0x00000000
+#define DDRSS0_PHY_134_DATA 0x00080200
+#define DDRSS0_PHY_135_DATA 0x00000000
+#define DDRSS0_PHY_136_DATA 0x20202000
+#define DDRSS0_PHY_137_DATA 0x20202020
+#define DDRSS0_PHY_138_DATA 0xF0F02020
+#define DDRSS0_PHY_139_DATA 0x00000000
+#define DDRSS0_PHY_140_DATA 0x00000000
+#define DDRSS0_PHY_141_DATA 0x00000000
+#define DDRSS0_PHY_142_DATA 0x00000000
+#define DDRSS0_PHY_143_DATA 0x00000000
+#define DDRSS0_PHY_144_DATA 0x00000000
+#define DDRSS0_PHY_145_DATA 0x00000000
+#define DDRSS0_PHY_146_DATA 0x00000000
+#define DDRSS0_PHY_147_DATA 0x00000000
+#define DDRSS0_PHY_148_DATA 0x00000000
+#define DDRSS0_PHY_149_DATA 0x00000000
+#define DDRSS0_PHY_150_DATA 0x00000000
+#define DDRSS0_PHY_151_DATA 0x00000000
+#define DDRSS0_PHY_152_DATA 0x00000000
+#define DDRSS0_PHY_153_DATA 0x00000000
+#define DDRSS0_PHY_154_DATA 0x00000000
+#define DDRSS0_PHY_155_DATA 0x00000000
+#define DDRSS0_PHY_156_DATA 0x00000000
+#define DDRSS0_PHY_157_DATA 0x00000000
+#define DDRSS0_PHY_158_DATA 0x00000000
+#define DDRSS0_PHY_159_DATA 0x00000000
+#define DDRSS0_PHY_160_DATA 0x00000000
+#define DDRSS0_PHY_161_DATA 0x00000000
+#define DDRSS0_PHY_162_DATA 0x00000000
+#define DDRSS0_PHY_163_DATA 0x00000000
+#define DDRSS0_PHY_164_DATA 0x00000000
+#define DDRSS0_PHY_165_DATA 0x00000000
+#define DDRSS0_PHY_166_DATA 0x00000000
+#define DDRSS0_PHY_167_DATA 0x00000000
+#define DDRSS0_PHY_168_DATA 0x00000000
+#define DDRSS0_PHY_169_DATA 0x00000000
+#define DDRSS0_PHY_170_DATA 0x00000000
+#define DDRSS0_PHY_171_DATA 0x00000000
+#define DDRSS0_PHY_172_DATA 0x00000000
+#define DDRSS0_PHY_173_DATA 0x00000000
+#define DDRSS0_PHY_174_DATA 0x00000000
+#define DDRSS0_PHY_175_DATA 0x00000000
+#define DDRSS0_PHY_176_DATA 0x00000000
+#define DDRSS0_PHY_177_DATA 0x00000000
+#define DDRSS0_PHY_178_DATA 0x00000000
+#define DDRSS0_PHY_179_DATA 0x00000000
+#define DDRSS0_PHY_180_DATA 0x00000000
+#define DDRSS0_PHY_181_DATA 0x00000000
+#define DDRSS0_PHY_182_DATA 0x00000000
+#define DDRSS0_PHY_183_DATA 0x00000000
+#define DDRSS0_PHY_184_DATA 0x00000000
+#define DDRSS0_PHY_185_DATA 0x00000000
+#define DDRSS0_PHY_186_DATA 0x00000000
+#define DDRSS0_PHY_187_DATA 0x00000000
+#define DDRSS0_PHY_188_DATA 0x00000000
+#define DDRSS0_PHY_189_DATA 0x00000000
+#define DDRSS0_PHY_190_DATA 0x00000000
+#define DDRSS0_PHY_191_DATA 0x00000000
+#define DDRSS0_PHY_192_DATA 0x00000000
+#define DDRSS0_PHY_193_DATA 0x00000000
+#define DDRSS0_PHY_194_DATA 0x00000000
+#define DDRSS0_PHY_195_DATA 0x00000000
+#define DDRSS0_PHY_196_DATA 0x00000000
+#define DDRSS0_PHY_197_DATA 0x00000000
+#define DDRSS0_PHY_198_DATA 0x00000000
+#define DDRSS0_PHY_199_DATA 0x00000000
+#define DDRSS0_PHY_200_DATA 0x00000000
+#define DDRSS0_PHY_201_DATA 0x00000000
+#define DDRSS0_PHY_202_DATA 0x00000000
+#define DDRSS0_PHY_203_DATA 0x00000000
+#define DDRSS0_PHY_204_DATA 0x00000000
+#define DDRSS0_PHY_205_DATA 0x00000000
+#define DDRSS0_PHY_206_DATA 0x00000000
+#define DDRSS0_PHY_207_DATA 0x00000000
+#define DDRSS0_PHY_208_DATA 0x00000000
+#define DDRSS0_PHY_209_DATA 0x00000000
+#define DDRSS0_PHY_210_DATA 0x00000000
+#define DDRSS0_PHY_211_DATA 0x00000000
+#define DDRSS0_PHY_212_DATA 0x00000000
+#define DDRSS0_PHY_213_DATA 0x00000000
+#define DDRSS0_PHY_214_DATA 0x00000000
+#define DDRSS0_PHY_215_DATA 0x00000000
+#define DDRSS0_PHY_216_DATA 0x00000000
+#define DDRSS0_PHY_217_DATA 0x00000000
+#define DDRSS0_PHY_218_DATA 0x00000000
+#define DDRSS0_PHY_219_DATA 0x00000000
+#define DDRSS0_PHY_220_DATA 0x00000000
+#define DDRSS0_PHY_221_DATA 0x00000000
+#define DDRSS0_PHY_222_DATA 0x00000000
+#define DDRSS0_PHY_223_DATA 0x00000000
+#define DDRSS0_PHY_224_DATA 0x00000000
+#define DDRSS0_PHY_225_DATA 0x00000000
+#define DDRSS0_PHY_226_DATA 0x00000000
+#define DDRSS0_PHY_227_DATA 0x00000000
+#define DDRSS0_PHY_228_DATA 0x00000000
+#define DDRSS0_PHY_229_DATA 0x00000000
+#define DDRSS0_PHY_230_DATA 0x00000000
+#define DDRSS0_PHY_231_DATA 0x00000000
+#define DDRSS0_PHY_232_DATA 0x00000000
+#define DDRSS0_PHY_233_DATA 0x00000000
+#define DDRSS0_PHY_234_DATA 0x00000000
+#define DDRSS0_PHY_235_DATA 0x00000000
+#define DDRSS0_PHY_236_DATA 0x00000000
+#define DDRSS0_PHY_237_DATA 0x00000000
+#define DDRSS0_PHY_238_DATA 0x00000000
+#define DDRSS0_PHY_239_DATA 0x00000000
+#define DDRSS0_PHY_240_DATA 0x00000000
+#define DDRSS0_PHY_241_DATA 0x00000000
+#define DDRSS0_PHY_242_DATA 0x00000000
+#define DDRSS0_PHY_243_DATA 0x00000000
+#define DDRSS0_PHY_244_DATA 0x00000000
+#define DDRSS0_PHY_245_DATA 0x00000000
+#define DDRSS0_PHY_246_DATA 0x00000000
+#define DDRSS0_PHY_247_DATA 0x00000000
+#define DDRSS0_PHY_248_DATA 0x00000000
+#define DDRSS0_PHY_249_DATA 0x00000000
+#define DDRSS0_PHY_250_DATA 0x00000000
+#define DDRSS0_PHY_251_DATA 0x00000000
+#define DDRSS0_PHY_252_DATA 0x00000000
+#define DDRSS0_PHY_253_DATA 0x00000000
+#define DDRSS0_PHY_254_DATA 0x00000000
+#define DDRSS0_PHY_255_DATA 0x00000000
+#define DDRSS0_PHY_256_DATA 0x000004F0
+#define DDRSS0_PHY_257_DATA 0x00000000
+#define DDRSS0_PHY_258_DATA 0x00030200
+#define DDRSS0_PHY_259_DATA 0x00000000
+#define DDRSS0_PHY_260_DATA 0x00000000
+#define DDRSS0_PHY_261_DATA 0x01030000
+#define DDRSS0_PHY_262_DATA 0x00010000
+#define DDRSS0_PHY_263_DATA 0x01030004
+#define DDRSS0_PHY_264_DATA 0x01000000
+#define DDRSS0_PHY_265_DATA 0x00000000
+#define DDRSS0_PHY_266_DATA 0x00000000
+#define DDRSS0_PHY_267_DATA 0x01000001
+#define DDRSS0_PHY_268_DATA 0x00000100
+#define DDRSS0_PHY_269_DATA 0x000800C0
+#define DDRSS0_PHY_270_DATA 0x060100CC
+#define DDRSS0_PHY_271_DATA 0x00030066
+#define DDRSS0_PHY_272_DATA 0x00000000
+#define DDRSS0_PHY_273_DATA 0x00000301
+#define DDRSS0_PHY_274_DATA 0x0000AAAA
+#define DDRSS0_PHY_275_DATA 0x00005555
+#define DDRSS0_PHY_276_DATA 0x0000B5B5
+#define DDRSS0_PHY_277_DATA 0x00004A4A
+#define DDRSS0_PHY_278_DATA 0x00005656
+#define DDRSS0_PHY_279_DATA 0x0000A9A9
+#define DDRSS0_PHY_280_DATA 0x0000A9A9
+#define DDRSS0_PHY_281_DATA 0x0000B5B5
+#define DDRSS0_PHY_282_DATA 0x00000000
+#define DDRSS0_PHY_283_DATA 0x00000000
+#define DDRSS0_PHY_284_DATA 0x2A000000
+#define DDRSS0_PHY_285_DATA 0x00000808
+#define DDRSS0_PHY_286_DATA 0x0F000000
+#define DDRSS0_PHY_287_DATA 0x00000F0F
+#define DDRSS0_PHY_288_DATA 0x10200000
+#define DDRSS0_PHY_289_DATA 0x0C002006
+#define DDRSS0_PHY_290_DATA 0x00000000
+#define DDRSS0_PHY_291_DATA 0x00000000
+#define DDRSS0_PHY_292_DATA 0x55555555
+#define DDRSS0_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_294_DATA 0x55555555
+#define DDRSS0_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_296_DATA 0x00005555
+#define DDRSS0_PHY_297_DATA 0x01000100
+#define DDRSS0_PHY_298_DATA 0x00800180
+#define DDRSS0_PHY_299_DATA 0x00000000
+#define DDRSS0_PHY_300_DATA 0x00000000
+#define DDRSS0_PHY_301_DATA 0x00000000
+#define DDRSS0_PHY_302_DATA 0x00000000
+#define DDRSS0_PHY_303_DATA 0x00000000
+#define DDRSS0_PHY_304_DATA 0x00000000
+#define DDRSS0_PHY_305_DATA 0x00000000
+#define DDRSS0_PHY_306_DATA 0x00000000
+#define DDRSS0_PHY_307_DATA 0x00000000
+#define DDRSS0_PHY_308_DATA 0x00000000
+#define DDRSS0_PHY_309_DATA 0x00000000
+#define DDRSS0_PHY_310_DATA 0x00000000
+#define DDRSS0_PHY_311_DATA 0x00000000
+#define DDRSS0_PHY_312_DATA 0x00000000
+#define DDRSS0_PHY_313_DATA 0x00000000
+#define DDRSS0_PHY_314_DATA 0x00000000
+#define DDRSS0_PHY_315_DATA 0x00000000
+#define DDRSS0_PHY_316_DATA 0x00000000
+#define DDRSS0_PHY_317_DATA 0x00000000
+#define DDRSS0_PHY_318_DATA 0x00000000
+#define DDRSS0_PHY_319_DATA 0x00000000
+#define DDRSS0_PHY_320_DATA 0x00000000
+#define DDRSS0_PHY_321_DATA 0x00000000
+#define DDRSS0_PHY_322_DATA 0x00000104
+#define DDRSS0_PHY_323_DATA 0x00000120
+#define DDRSS0_PHY_324_DATA 0x00000000
+#define DDRSS0_PHY_325_DATA 0x00000000
+#define DDRSS0_PHY_326_DATA 0x00000000
+#define DDRSS0_PHY_327_DATA 0x00000000
+#define DDRSS0_PHY_328_DATA 0x00000000
+#define DDRSS0_PHY_329_DATA 0x00000000
+#define DDRSS0_PHY_330_DATA 0x00000000
+#define DDRSS0_PHY_331_DATA 0x00000001
+#define DDRSS0_PHY_332_DATA 0x07FF0000
+#define DDRSS0_PHY_333_DATA 0x0080081F
+#define DDRSS0_PHY_334_DATA 0x00081020
+#define DDRSS0_PHY_335_DATA 0x04010000
+#define DDRSS0_PHY_336_DATA 0x00000000
+#define DDRSS0_PHY_337_DATA 0x00000000
+#define DDRSS0_PHY_338_DATA 0x00000000
+#define DDRSS0_PHY_339_DATA 0x00000100
+#define DDRSS0_PHY_340_DATA 0x01CC0C01
+#define DDRSS0_PHY_341_DATA 0x1003CC0C
+#define DDRSS0_PHY_342_DATA 0x20000140
+#define DDRSS0_PHY_343_DATA 0x07FF0200
+#define DDRSS0_PHY_344_DATA 0x0000DD01
+#define DDRSS0_PHY_345_DATA 0x10100303
+#define DDRSS0_PHY_346_DATA 0x10101010
+#define DDRSS0_PHY_347_DATA 0x10101010
+#define DDRSS0_PHY_348_DATA 0x00021010
+#define DDRSS0_PHY_349_DATA 0x00100010
+#define DDRSS0_PHY_350_DATA 0x00100010
+#define DDRSS0_PHY_351_DATA 0x00100010
+#define DDRSS0_PHY_352_DATA 0x00100010
+#define DDRSS0_PHY_353_DATA 0x00050010
+#define DDRSS0_PHY_354_DATA 0x51517041
+#define DDRSS0_PHY_355_DATA 0x31C06001
+#define DDRSS0_PHY_356_DATA 0x07AB0340
+#define DDRSS0_PHY_357_DATA 0x00C0C001
+#define DDRSS0_PHY_358_DATA 0x0E0D0001
+#define DDRSS0_PHY_359_DATA 0x10001000
+#define DDRSS0_PHY_360_DATA 0x0C083E42
+#define DDRSS0_PHY_361_DATA 0x0F0C3701
+#define DDRSS0_PHY_362_DATA 0x01000140
+#define DDRSS0_PHY_363_DATA 0x0C000420
+#define DDRSS0_PHY_364_DATA 0x00000198
+#define DDRSS0_PHY_365_DATA 0x0A0000D0
+#define DDRSS0_PHY_366_DATA 0x00030200
+#define DDRSS0_PHY_367_DATA 0x02800000
+#define DDRSS0_PHY_368_DATA 0x80800000
+#define DDRSS0_PHY_369_DATA 0x000E2010
+#define DDRSS0_PHY_370_DATA 0x76543210
+#define DDRSS0_PHY_371_DATA 0x00000008
+#define DDRSS0_PHY_372_DATA 0x02800280
+#define DDRSS0_PHY_373_DATA 0x02800280
+#define DDRSS0_PHY_374_DATA 0x02800280
+#define DDRSS0_PHY_375_DATA 0x02800280
+#define DDRSS0_PHY_376_DATA 0x00000280
+#define DDRSS0_PHY_377_DATA 0x0000A000
+#define DDRSS0_PHY_378_DATA 0x00A000A0
+#define DDRSS0_PHY_379_DATA 0x00A000A0
+#define DDRSS0_PHY_380_DATA 0x00A000A0
+#define DDRSS0_PHY_381_DATA 0x00A000A0
+#define DDRSS0_PHY_382_DATA 0x00A000A0
+#define DDRSS0_PHY_383_DATA 0x00A000A0
+#define DDRSS0_PHY_384_DATA 0x00A000A0
+#define DDRSS0_PHY_385_DATA 0x00A000A0
+#define DDRSS0_PHY_386_DATA 0x01C200A0
+#define DDRSS0_PHY_387_DATA 0x01A00005
+#define DDRSS0_PHY_388_DATA 0x00000000
+#define DDRSS0_PHY_389_DATA 0x00000000
+#define DDRSS0_PHY_390_DATA 0x00080200
+#define DDRSS0_PHY_391_DATA 0x00000000
+#define DDRSS0_PHY_392_DATA 0x20202000
+#define DDRSS0_PHY_393_DATA 0x20202020
+#define DDRSS0_PHY_394_DATA 0xF0F02020
+#define DDRSS0_PHY_395_DATA 0x00000000
+#define DDRSS0_PHY_396_DATA 0x00000000
+#define DDRSS0_PHY_397_DATA 0x00000000
+#define DDRSS0_PHY_398_DATA 0x00000000
+#define DDRSS0_PHY_399_DATA 0x00000000
+#define DDRSS0_PHY_400_DATA 0x00000000
+#define DDRSS0_PHY_401_DATA 0x00000000
+#define DDRSS0_PHY_402_DATA 0x00000000
+#define DDRSS0_PHY_403_DATA 0x00000000
+#define DDRSS0_PHY_404_DATA 0x00000000
+#define DDRSS0_PHY_405_DATA 0x00000000
+#define DDRSS0_PHY_406_DATA 0x00000000
+#define DDRSS0_PHY_407_DATA 0x00000000
+#define DDRSS0_PHY_408_DATA 0x00000000
+#define DDRSS0_PHY_409_DATA 0x00000000
+#define DDRSS0_PHY_410_DATA 0x00000000
+#define DDRSS0_PHY_411_DATA 0x00000000
+#define DDRSS0_PHY_412_DATA 0x00000000
+#define DDRSS0_PHY_413_DATA 0x00000000
+#define DDRSS0_PHY_414_DATA 0x00000000
+#define DDRSS0_PHY_415_DATA 0x00000000
+#define DDRSS0_PHY_416_DATA 0x00000000
+#define DDRSS0_PHY_417_DATA 0x00000000
+#define DDRSS0_PHY_418_DATA 0x00000000
+#define DDRSS0_PHY_419_DATA 0x00000000
+#define DDRSS0_PHY_420_DATA 0x00000000
+#define DDRSS0_PHY_421_DATA 0x00000000
+#define DDRSS0_PHY_422_DATA 0x00000000
+#define DDRSS0_PHY_423_DATA 0x00000000
+#define DDRSS0_PHY_424_DATA 0x00000000
+#define DDRSS0_PHY_425_DATA 0x00000000
+#define DDRSS0_PHY_426_DATA 0x00000000
+#define DDRSS0_PHY_427_DATA 0x00000000
+#define DDRSS0_PHY_428_DATA 0x00000000
+#define DDRSS0_PHY_429_DATA 0x00000000
+#define DDRSS0_PHY_430_DATA 0x00000000
+#define DDRSS0_PHY_431_DATA 0x00000000
+#define DDRSS0_PHY_432_DATA 0x00000000
+#define DDRSS0_PHY_433_DATA 0x00000000
+#define DDRSS0_PHY_434_DATA 0x00000000
+#define DDRSS0_PHY_435_DATA 0x00000000
+#define DDRSS0_PHY_436_DATA 0x00000000
+#define DDRSS0_PHY_437_DATA 0x00000000
+#define DDRSS0_PHY_438_DATA 0x00000000
+#define DDRSS0_PHY_439_DATA 0x00000000
+#define DDRSS0_PHY_440_DATA 0x00000000
+#define DDRSS0_PHY_441_DATA 0x00000000
+#define DDRSS0_PHY_442_DATA 0x00000000
+#define DDRSS0_PHY_443_DATA 0x00000000
+#define DDRSS0_PHY_444_DATA 0x00000000
+#define DDRSS0_PHY_445_DATA 0x00000000
+#define DDRSS0_PHY_446_DATA 0x00000000
+#define DDRSS0_PHY_447_DATA 0x00000000
+#define DDRSS0_PHY_448_DATA 0x00000000
+#define DDRSS0_PHY_449_DATA 0x00000000
+#define DDRSS0_PHY_450_DATA 0x00000000
+#define DDRSS0_PHY_451_DATA 0x00000000
+#define DDRSS0_PHY_452_DATA 0x00000000
+#define DDRSS0_PHY_453_DATA 0x00000000
+#define DDRSS0_PHY_454_DATA 0x00000000
+#define DDRSS0_PHY_455_DATA 0x00000000
+#define DDRSS0_PHY_456_DATA 0x00000000
+#define DDRSS0_PHY_457_DATA 0x00000000
+#define DDRSS0_PHY_458_DATA 0x00000000
+#define DDRSS0_PHY_459_DATA 0x00000000
+#define DDRSS0_PHY_460_DATA 0x00000000
+#define DDRSS0_PHY_461_DATA 0x00000000
+#define DDRSS0_PHY_462_DATA 0x00000000
+#define DDRSS0_PHY_463_DATA 0x00000000
+#define DDRSS0_PHY_464_DATA 0x00000000
+#define DDRSS0_PHY_465_DATA 0x00000000
+#define DDRSS0_PHY_466_DATA 0x00000000
+#define DDRSS0_PHY_467_DATA 0x00000000
+#define DDRSS0_PHY_468_DATA 0x00000000
+#define DDRSS0_PHY_469_DATA 0x00000000
+#define DDRSS0_PHY_470_DATA 0x00000000
+#define DDRSS0_PHY_471_DATA 0x00000000
+#define DDRSS0_PHY_472_DATA 0x00000000
+#define DDRSS0_PHY_473_DATA 0x00000000
+#define DDRSS0_PHY_474_DATA 0x00000000
+#define DDRSS0_PHY_475_DATA 0x00000000
+#define DDRSS0_PHY_476_DATA 0x00000000
+#define DDRSS0_PHY_477_DATA 0x00000000
+#define DDRSS0_PHY_478_DATA 0x00000000
+#define DDRSS0_PHY_479_DATA 0x00000000
+#define DDRSS0_PHY_480_DATA 0x00000000
+#define DDRSS0_PHY_481_DATA 0x00000000
+#define DDRSS0_PHY_482_DATA 0x00000000
+#define DDRSS0_PHY_483_DATA 0x00000000
+#define DDRSS0_PHY_484_DATA 0x00000000
+#define DDRSS0_PHY_485_DATA 0x00000000
+#define DDRSS0_PHY_486_DATA 0x00000000
+#define DDRSS0_PHY_487_DATA 0x00000000
+#define DDRSS0_PHY_488_DATA 0x00000000
+#define DDRSS0_PHY_489_DATA 0x00000000
+#define DDRSS0_PHY_490_DATA 0x00000000
+#define DDRSS0_PHY_491_DATA 0x00000000
+#define DDRSS0_PHY_492_DATA 0x00000000
+#define DDRSS0_PHY_493_DATA 0x00000000
+#define DDRSS0_PHY_494_DATA 0x00000000
+#define DDRSS0_PHY_495_DATA 0x00000000
+#define DDRSS0_PHY_496_DATA 0x00000000
+#define DDRSS0_PHY_497_DATA 0x00000000
+#define DDRSS0_PHY_498_DATA 0x00000000
+#define DDRSS0_PHY_499_DATA 0x00000000
+#define DDRSS0_PHY_500_DATA 0x00000000
+#define DDRSS0_PHY_501_DATA 0x00000000
+#define DDRSS0_PHY_502_DATA 0x00000000
+#define DDRSS0_PHY_503_DATA 0x00000000
+#define DDRSS0_PHY_504_DATA 0x00000000
+#define DDRSS0_PHY_505_DATA 0x00000000
+#define DDRSS0_PHY_506_DATA 0x00000000
+#define DDRSS0_PHY_507_DATA 0x00000000
+#define DDRSS0_PHY_508_DATA 0x00000000
+#define DDRSS0_PHY_509_DATA 0x00000000
+#define DDRSS0_PHY_510_DATA 0x00000000
+#define DDRSS0_PHY_511_DATA 0x00000000
+#define DDRSS0_PHY_512_DATA 0x000004F0
+#define DDRSS0_PHY_513_DATA 0x00000000
+#define DDRSS0_PHY_514_DATA 0x00030200
+#define DDRSS0_PHY_515_DATA 0x00000000
+#define DDRSS0_PHY_516_DATA 0x00000000
+#define DDRSS0_PHY_517_DATA 0x01030000
+#define DDRSS0_PHY_518_DATA 0x00010000
+#define DDRSS0_PHY_519_DATA 0x01030004
+#define DDRSS0_PHY_520_DATA 0x01000000
+#define DDRSS0_PHY_521_DATA 0x00000000
+#define DDRSS0_PHY_522_DATA 0x00000000
+#define DDRSS0_PHY_523_DATA 0x01000001
+#define DDRSS0_PHY_524_DATA 0x00000100
+#define DDRSS0_PHY_525_DATA 0x000800C0
+#define DDRSS0_PHY_526_DATA 0x060100CC
+#define DDRSS0_PHY_527_DATA 0x00030066
+#define DDRSS0_PHY_528_DATA 0x00000000
+#define DDRSS0_PHY_529_DATA 0x00000301
+#define DDRSS0_PHY_530_DATA 0x0000AAAA
+#define DDRSS0_PHY_531_DATA 0x00005555
+#define DDRSS0_PHY_532_DATA 0x0000B5B5
+#define DDRSS0_PHY_533_DATA 0x00004A4A
+#define DDRSS0_PHY_534_DATA 0x00005656
+#define DDRSS0_PHY_535_DATA 0x0000A9A9
+#define DDRSS0_PHY_536_DATA 0x0000A9A9
+#define DDRSS0_PHY_537_DATA 0x0000B5B5
+#define DDRSS0_PHY_538_DATA 0x00000000
+#define DDRSS0_PHY_539_DATA 0x00000000
+#define DDRSS0_PHY_540_DATA 0x2A000000
+#define DDRSS0_PHY_541_DATA 0x00000808
+#define DDRSS0_PHY_542_DATA 0x0F000000
+#define DDRSS0_PHY_543_DATA 0x00000F0F
+#define DDRSS0_PHY_544_DATA 0x10200000
+#define DDRSS0_PHY_545_DATA 0x0C002006
+#define DDRSS0_PHY_546_DATA 0x00000000
+#define DDRSS0_PHY_547_DATA 0x00000000
+#define DDRSS0_PHY_548_DATA 0x55555555
+#define DDRSS0_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_550_DATA 0x55555555
+#define DDRSS0_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_552_DATA 0x00005555
+#define DDRSS0_PHY_553_DATA 0x01000100
+#define DDRSS0_PHY_554_DATA 0x00800180
+#define DDRSS0_PHY_555_DATA 0x00000001
+#define DDRSS0_PHY_556_DATA 0x00000000
+#define DDRSS0_PHY_557_DATA 0x00000000
+#define DDRSS0_PHY_558_DATA 0x00000000
+#define DDRSS0_PHY_559_DATA 0x00000000
+#define DDRSS0_PHY_560_DATA 0x00000000
+#define DDRSS0_PHY_561_DATA 0x00000000
+#define DDRSS0_PHY_562_DATA 0x00000000
+#define DDRSS0_PHY_563_DATA 0x00000000
+#define DDRSS0_PHY_564_DATA 0x00000000
+#define DDRSS0_PHY_565_DATA 0x00000000
+#define DDRSS0_PHY_566_DATA 0x00000000
+#define DDRSS0_PHY_567_DATA 0x00000000
+#define DDRSS0_PHY_568_DATA 0x00000000
+#define DDRSS0_PHY_569_DATA 0x00000000
+#define DDRSS0_PHY_570_DATA 0x00000000
+#define DDRSS0_PHY_571_DATA 0x00000000
+#define DDRSS0_PHY_572_DATA 0x00000000
+#define DDRSS0_PHY_573_DATA 0x00000000
+#define DDRSS0_PHY_574_DATA 0x00000000
+#define DDRSS0_PHY_575_DATA 0x00000000
+#define DDRSS0_PHY_576_DATA 0x00000000
+#define DDRSS0_PHY_577_DATA 0x00000000
+#define DDRSS0_PHY_578_DATA 0x00000104
+#define DDRSS0_PHY_579_DATA 0x00000120
+#define DDRSS0_PHY_580_DATA 0x00000000
+#define DDRSS0_PHY_581_DATA 0x00000000
+#define DDRSS0_PHY_582_DATA 0x00000000
+#define DDRSS0_PHY_583_DATA 0x00000000
+#define DDRSS0_PHY_584_DATA 0x00000000
+#define DDRSS0_PHY_585_DATA 0x00000000
+#define DDRSS0_PHY_586_DATA 0x00000000
+#define DDRSS0_PHY_587_DATA 0x00000001
+#define DDRSS0_PHY_588_DATA 0x07FF0000
+#define DDRSS0_PHY_589_DATA 0x0080081F
+#define DDRSS0_PHY_590_DATA 0x00081020
+#define DDRSS0_PHY_591_DATA 0x04010000
+#define DDRSS0_PHY_592_DATA 0x00000000
+#define DDRSS0_PHY_593_DATA 0x00000000
+#define DDRSS0_PHY_594_DATA 0x00000000
+#define DDRSS0_PHY_595_DATA 0x00000100
+#define DDRSS0_PHY_596_DATA 0x01CC0C01
+#define DDRSS0_PHY_597_DATA 0x1003CC0C
+#define DDRSS0_PHY_598_DATA 0x20000140
+#define DDRSS0_PHY_599_DATA 0x07FF0200
+#define DDRSS0_PHY_600_DATA 0x0000DD01
+#define DDRSS0_PHY_601_DATA 0x10100303
+#define DDRSS0_PHY_602_DATA 0x10101010
+#define DDRSS0_PHY_603_DATA 0x10101010
+#define DDRSS0_PHY_604_DATA 0x00021010
+#define DDRSS0_PHY_605_DATA 0x00100010
+#define DDRSS0_PHY_606_DATA 0x00100010
+#define DDRSS0_PHY_607_DATA 0x00100010
+#define DDRSS0_PHY_608_DATA 0x00100010
+#define DDRSS0_PHY_609_DATA 0x00050010
+#define DDRSS0_PHY_610_DATA 0x51517041
+#define DDRSS0_PHY_611_DATA 0x31C06001
+#define DDRSS0_PHY_612_DATA 0x07AB0340
+#define DDRSS0_PHY_613_DATA 0x00C0C001
+#define DDRSS0_PHY_614_DATA 0x0E0D0001
+#define DDRSS0_PHY_615_DATA 0x10001000
+#define DDRSS0_PHY_616_DATA 0x0C083E42
+#define DDRSS0_PHY_617_DATA 0x0F0C3701
+#define DDRSS0_PHY_618_DATA 0x01000140
+#define DDRSS0_PHY_619_DATA 0x0C000420
+#define DDRSS0_PHY_620_DATA 0x00000198
+#define DDRSS0_PHY_621_DATA 0x0A0000D0
+#define DDRSS0_PHY_622_DATA 0x00030200
+#define DDRSS0_PHY_623_DATA 0x02800000
+#define DDRSS0_PHY_624_DATA 0x80800000
+#define DDRSS0_PHY_625_DATA 0x000E2010
+#define DDRSS0_PHY_626_DATA 0x76543210
+#define DDRSS0_PHY_627_DATA 0x00000008
+#define DDRSS0_PHY_628_DATA 0x02800280
+#define DDRSS0_PHY_629_DATA 0x02800280
+#define DDRSS0_PHY_630_DATA 0x02800280
+#define DDRSS0_PHY_631_DATA 0x02800280
+#define DDRSS0_PHY_632_DATA 0x00000280
+#define DDRSS0_PHY_633_DATA 0x0000A000
+#define DDRSS0_PHY_634_DATA 0x00A000A0
+#define DDRSS0_PHY_635_DATA 0x00A000A0
+#define DDRSS0_PHY_636_DATA 0x00A000A0
+#define DDRSS0_PHY_637_DATA 0x00A000A0
+#define DDRSS0_PHY_638_DATA 0x00A000A0
+#define DDRSS0_PHY_639_DATA 0x00A000A0
+#define DDRSS0_PHY_640_DATA 0x00A000A0
+#define DDRSS0_PHY_641_DATA 0x00A000A0
+#define DDRSS0_PHY_642_DATA 0x01C200A0
+#define DDRSS0_PHY_643_DATA 0x01A00005
+#define DDRSS0_PHY_644_DATA 0x00000000
+#define DDRSS0_PHY_645_DATA 0x00000000
+#define DDRSS0_PHY_646_DATA 0x00080200
+#define DDRSS0_PHY_647_DATA 0x00000000
+#define DDRSS0_PHY_648_DATA 0x20202000
+#define DDRSS0_PHY_649_DATA 0x20202020
+#define DDRSS0_PHY_650_DATA 0xF0F02020
+#define DDRSS0_PHY_651_DATA 0x00000000
+#define DDRSS0_PHY_652_DATA 0x00000000
+#define DDRSS0_PHY_653_DATA 0x00000000
+#define DDRSS0_PHY_654_DATA 0x00000000
+#define DDRSS0_PHY_655_DATA 0x00000000
+#define DDRSS0_PHY_656_DATA 0x00000000
+#define DDRSS0_PHY_657_DATA 0x00000000
+#define DDRSS0_PHY_658_DATA 0x00000000
+#define DDRSS0_PHY_659_DATA 0x00000000
+#define DDRSS0_PHY_660_DATA 0x00000000
+#define DDRSS0_PHY_661_DATA 0x00000000
+#define DDRSS0_PHY_662_DATA 0x00000000
+#define DDRSS0_PHY_663_DATA 0x00000000
+#define DDRSS0_PHY_664_DATA 0x00000000
+#define DDRSS0_PHY_665_DATA 0x00000000
+#define DDRSS0_PHY_666_DATA 0x00000000
+#define DDRSS0_PHY_667_DATA 0x00000000
+#define DDRSS0_PHY_668_DATA 0x00000000
+#define DDRSS0_PHY_669_DATA 0x00000000
+#define DDRSS0_PHY_670_DATA 0x00000000
+#define DDRSS0_PHY_671_DATA 0x00000000
+#define DDRSS0_PHY_672_DATA 0x00000000
+#define DDRSS0_PHY_673_DATA 0x00000000
+#define DDRSS0_PHY_674_DATA 0x00000000
+#define DDRSS0_PHY_675_DATA 0x00000000
+#define DDRSS0_PHY_676_DATA 0x00000000
+#define DDRSS0_PHY_677_DATA 0x00000000
+#define DDRSS0_PHY_678_DATA 0x00000000
+#define DDRSS0_PHY_679_DATA 0x00000000
+#define DDRSS0_PHY_680_DATA 0x00000000
+#define DDRSS0_PHY_681_DATA 0x00000000
+#define DDRSS0_PHY_682_DATA 0x00000000
+#define DDRSS0_PHY_683_DATA 0x00000000
+#define DDRSS0_PHY_684_DATA 0x00000000
+#define DDRSS0_PHY_685_DATA 0x00000000
+#define DDRSS0_PHY_686_DATA 0x00000000
+#define DDRSS0_PHY_687_DATA 0x00000000
+#define DDRSS0_PHY_688_DATA 0x00000000
+#define DDRSS0_PHY_689_DATA 0x00000000
+#define DDRSS0_PHY_690_DATA 0x00000000
+#define DDRSS0_PHY_691_DATA 0x00000000
+#define DDRSS0_PHY_692_DATA 0x00000000
+#define DDRSS0_PHY_693_DATA 0x00000000
+#define DDRSS0_PHY_694_DATA 0x00000000
+#define DDRSS0_PHY_695_DATA 0x00000000
+#define DDRSS0_PHY_696_DATA 0x00000000
+#define DDRSS0_PHY_697_DATA 0x00000000
+#define DDRSS0_PHY_698_DATA 0x00000000
+#define DDRSS0_PHY_699_DATA 0x00000000
+#define DDRSS0_PHY_700_DATA 0x00000000
+#define DDRSS0_PHY_701_DATA 0x00000000
+#define DDRSS0_PHY_702_DATA 0x00000000
+#define DDRSS0_PHY_703_DATA 0x00000000
+#define DDRSS0_PHY_704_DATA 0x00000000
+#define DDRSS0_PHY_705_DATA 0x00000000
+#define DDRSS0_PHY_706_DATA 0x00000000
+#define DDRSS0_PHY_707_DATA 0x00000000
+#define DDRSS0_PHY_708_DATA 0x00000000
+#define DDRSS0_PHY_709_DATA 0x00000000
+#define DDRSS0_PHY_710_DATA 0x00000000
+#define DDRSS0_PHY_711_DATA 0x00000000
+#define DDRSS0_PHY_712_DATA 0x00000000
+#define DDRSS0_PHY_713_DATA 0x00000000
+#define DDRSS0_PHY_714_DATA 0x00000000
+#define DDRSS0_PHY_715_DATA 0x00000000
+#define DDRSS0_PHY_716_DATA 0x00000000
+#define DDRSS0_PHY_717_DATA 0x00000000
+#define DDRSS0_PHY_718_DATA 0x00000000
+#define DDRSS0_PHY_719_DATA 0x00000000
+#define DDRSS0_PHY_720_DATA 0x00000000
+#define DDRSS0_PHY_721_DATA 0x00000000
+#define DDRSS0_PHY_722_DATA 0x00000000
+#define DDRSS0_PHY_723_DATA 0x00000000
+#define DDRSS0_PHY_724_DATA 0x00000000
+#define DDRSS0_PHY_725_DATA 0x00000000
+#define DDRSS0_PHY_726_DATA 0x00000000
+#define DDRSS0_PHY_727_DATA 0x00000000
+#define DDRSS0_PHY_728_DATA 0x00000000
+#define DDRSS0_PHY_729_DATA 0x00000000
+#define DDRSS0_PHY_730_DATA 0x00000000
+#define DDRSS0_PHY_731_DATA 0x00000000
+#define DDRSS0_PHY_732_DATA 0x00000000
+#define DDRSS0_PHY_733_DATA 0x00000000
+#define DDRSS0_PHY_734_DATA 0x00000000
+#define DDRSS0_PHY_735_DATA 0x00000000
+#define DDRSS0_PHY_736_DATA 0x00000000
+#define DDRSS0_PHY_737_DATA 0x00000000
+#define DDRSS0_PHY_738_DATA 0x00000000
+#define DDRSS0_PHY_739_DATA 0x00000000
+#define DDRSS0_PHY_740_DATA 0x00000000
+#define DDRSS0_PHY_741_DATA 0x00000000
+#define DDRSS0_PHY_742_DATA 0x00000000
+#define DDRSS0_PHY_743_DATA 0x00000000
+#define DDRSS0_PHY_744_DATA 0x00000000
+#define DDRSS0_PHY_745_DATA 0x00000000
+#define DDRSS0_PHY_746_DATA 0x00000000
+#define DDRSS0_PHY_747_DATA 0x00000000
+#define DDRSS0_PHY_748_DATA 0x00000000
+#define DDRSS0_PHY_749_DATA 0x00000000
+#define DDRSS0_PHY_750_DATA 0x00000000
+#define DDRSS0_PHY_751_DATA 0x00000000
+#define DDRSS0_PHY_752_DATA 0x00000000
+#define DDRSS0_PHY_753_DATA 0x00000000
+#define DDRSS0_PHY_754_DATA 0x00000000
+#define DDRSS0_PHY_755_DATA 0x00000000
+#define DDRSS0_PHY_756_DATA 0x00000000
+#define DDRSS0_PHY_757_DATA 0x00000000
+#define DDRSS0_PHY_758_DATA 0x00000000
+#define DDRSS0_PHY_759_DATA 0x00000000
+#define DDRSS0_PHY_760_DATA 0x00000000
+#define DDRSS0_PHY_761_DATA 0x00000000
+#define DDRSS0_PHY_762_DATA 0x00000000
+#define DDRSS0_PHY_763_DATA 0x00000000
+#define DDRSS0_PHY_764_DATA 0x00000000
+#define DDRSS0_PHY_765_DATA 0x00000000
+#define DDRSS0_PHY_766_DATA 0x00000000
+#define DDRSS0_PHY_767_DATA 0x00000000
+#define DDRSS0_PHY_768_DATA 0x000004F0
+#define DDRSS0_PHY_769_DATA 0x00000000
+#define DDRSS0_PHY_770_DATA 0x00030200
+#define DDRSS0_PHY_771_DATA 0x00000000
+#define DDRSS0_PHY_772_DATA 0x00000000
+#define DDRSS0_PHY_773_DATA 0x01030000
+#define DDRSS0_PHY_774_DATA 0x00010000
+#define DDRSS0_PHY_775_DATA 0x01030004
+#define DDRSS0_PHY_776_DATA 0x01000000
+#define DDRSS0_PHY_777_DATA 0x00000000
+#define DDRSS0_PHY_778_DATA 0x00000000
+#define DDRSS0_PHY_779_DATA 0x01000001
+#define DDRSS0_PHY_780_DATA 0x00000100
+#define DDRSS0_PHY_781_DATA 0x000800C0
+#define DDRSS0_PHY_782_DATA 0x060100CC
+#define DDRSS0_PHY_783_DATA 0x00030066
+#define DDRSS0_PHY_784_DATA 0x00000000
+#define DDRSS0_PHY_785_DATA 0x00000301
+#define DDRSS0_PHY_786_DATA 0x0000AAAA
+#define DDRSS0_PHY_787_DATA 0x00005555
+#define DDRSS0_PHY_788_DATA 0x0000B5B5
+#define DDRSS0_PHY_789_DATA 0x00004A4A
+#define DDRSS0_PHY_790_DATA 0x00005656
+#define DDRSS0_PHY_791_DATA 0x0000A9A9
+#define DDRSS0_PHY_792_DATA 0x0000A9A9
+#define DDRSS0_PHY_793_DATA 0x0000B5B5
+#define DDRSS0_PHY_794_DATA 0x00000000
+#define DDRSS0_PHY_795_DATA 0x00000000
+#define DDRSS0_PHY_796_DATA 0x2A000000
+#define DDRSS0_PHY_797_DATA 0x00000808
+#define DDRSS0_PHY_798_DATA 0x0F000000
+#define DDRSS0_PHY_799_DATA 0x00000F0F
+#define DDRSS0_PHY_800_DATA 0x10200000
+#define DDRSS0_PHY_801_DATA 0x0C002006
+#define DDRSS0_PHY_802_DATA 0x00000000
+#define DDRSS0_PHY_803_DATA 0x00000000
+#define DDRSS0_PHY_804_DATA 0x55555555
+#define DDRSS0_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_806_DATA 0x55555555
+#define DDRSS0_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_808_DATA 0x00005555
+#define DDRSS0_PHY_809_DATA 0x01000100
+#define DDRSS0_PHY_810_DATA 0x00800180
+#define DDRSS0_PHY_811_DATA 0x00000000
+#define DDRSS0_PHY_812_DATA 0x00000000
+#define DDRSS0_PHY_813_DATA 0x00000000
+#define DDRSS0_PHY_814_DATA 0x00000000
+#define DDRSS0_PHY_815_DATA 0x00000000
+#define DDRSS0_PHY_816_DATA 0x00000000
+#define DDRSS0_PHY_817_DATA 0x00000000
+#define DDRSS0_PHY_818_DATA 0x00000000
+#define DDRSS0_PHY_819_DATA 0x00000000
+#define DDRSS0_PHY_820_DATA 0x00000000
+#define DDRSS0_PHY_821_DATA 0x00000000
+#define DDRSS0_PHY_822_DATA 0x00000000
+#define DDRSS0_PHY_823_DATA 0x00000000
+#define DDRSS0_PHY_824_DATA 0x00000000
+#define DDRSS0_PHY_825_DATA 0x00000000
+#define DDRSS0_PHY_826_DATA 0x00000000
+#define DDRSS0_PHY_827_DATA 0x00000000
+#define DDRSS0_PHY_828_DATA 0x00000000
+#define DDRSS0_PHY_829_DATA 0x00000000
+#define DDRSS0_PHY_830_DATA 0x00000000
+#define DDRSS0_PHY_831_DATA 0x00000000
+#define DDRSS0_PHY_832_DATA 0x00000000
+#define DDRSS0_PHY_833_DATA 0x00000000
+#define DDRSS0_PHY_834_DATA 0x00000104
+#define DDRSS0_PHY_835_DATA 0x00000120
+#define DDRSS0_PHY_836_DATA 0x00000000
+#define DDRSS0_PHY_837_DATA 0x00000000
+#define DDRSS0_PHY_838_DATA 0x00000000
+#define DDRSS0_PHY_839_DATA 0x00000000
+#define DDRSS0_PHY_840_DATA 0x00000000
+#define DDRSS0_PHY_841_DATA 0x00000000
+#define DDRSS0_PHY_842_DATA 0x00000000
+#define DDRSS0_PHY_843_DATA 0x00000001
+#define DDRSS0_PHY_844_DATA 0x07FF0000
+#define DDRSS0_PHY_845_DATA 0x0080081F
+#define DDRSS0_PHY_846_DATA 0x00081020
+#define DDRSS0_PHY_847_DATA 0x04010000
+#define DDRSS0_PHY_848_DATA 0x00000000
+#define DDRSS0_PHY_849_DATA 0x00000000
+#define DDRSS0_PHY_850_DATA 0x00000000
+#define DDRSS0_PHY_851_DATA 0x00000100
+#define DDRSS0_PHY_852_DATA 0x01CC0C01
+#define DDRSS0_PHY_853_DATA 0x1003CC0C
+#define DDRSS0_PHY_854_DATA 0x20000140
+#define DDRSS0_PHY_855_DATA 0x07FF0200
+#define DDRSS0_PHY_856_DATA 0x0000DD01
+#define DDRSS0_PHY_857_DATA 0x10100303
+#define DDRSS0_PHY_858_DATA 0x10101010
+#define DDRSS0_PHY_859_DATA 0x10101010
+#define DDRSS0_PHY_860_DATA 0x00021010
+#define DDRSS0_PHY_861_DATA 0x00100010
+#define DDRSS0_PHY_862_DATA 0x00100010
+#define DDRSS0_PHY_863_DATA 0x00100010
+#define DDRSS0_PHY_864_DATA 0x00100010
+#define DDRSS0_PHY_865_DATA 0x00050010
+#define DDRSS0_PHY_866_DATA 0x51517041
+#define DDRSS0_PHY_867_DATA 0x31C06001
+#define DDRSS0_PHY_868_DATA 0x07AB0340
+#define DDRSS0_PHY_869_DATA 0x00C0C001
+#define DDRSS0_PHY_870_DATA 0x0E0D0001
+#define DDRSS0_PHY_871_DATA 0x10001000
+#define DDRSS0_PHY_872_DATA 0x0C083E42
+#define DDRSS0_PHY_873_DATA 0x0F0C3701
+#define DDRSS0_PHY_874_DATA 0x01000140
+#define DDRSS0_PHY_875_DATA 0x0C000420
+#define DDRSS0_PHY_876_DATA 0x00000198
+#define DDRSS0_PHY_877_DATA 0x0A0000D0
+#define DDRSS0_PHY_878_DATA 0x00030200
+#define DDRSS0_PHY_879_DATA 0x02800000
+#define DDRSS0_PHY_880_DATA 0x80800000
+#define DDRSS0_PHY_881_DATA 0x000E2010
+#define DDRSS0_PHY_882_DATA 0x76543210
+#define DDRSS0_PHY_883_DATA 0x00000008
+#define DDRSS0_PHY_884_DATA 0x02800280
+#define DDRSS0_PHY_885_DATA 0x02800280
+#define DDRSS0_PHY_886_DATA 0x02800280
+#define DDRSS0_PHY_887_DATA 0x02800280
+#define DDRSS0_PHY_888_DATA 0x00000280
+#define DDRSS0_PHY_889_DATA 0x0000A000
+#define DDRSS0_PHY_890_DATA 0x00A000A0
+#define DDRSS0_PHY_891_DATA 0x00A000A0
+#define DDRSS0_PHY_892_DATA 0x00A000A0
+#define DDRSS0_PHY_893_DATA 0x00A000A0
+#define DDRSS0_PHY_894_DATA 0x00A000A0
+#define DDRSS0_PHY_895_DATA 0x00A000A0
+#define DDRSS0_PHY_896_DATA 0x00A000A0
+#define DDRSS0_PHY_897_DATA 0x00A000A0
+#define DDRSS0_PHY_898_DATA 0x01C200A0
+#define DDRSS0_PHY_899_DATA 0x01A00005
+#define DDRSS0_PHY_900_DATA 0x00000000
+#define DDRSS0_PHY_901_DATA 0x00000000
+#define DDRSS0_PHY_902_DATA 0x00080200
+#define DDRSS0_PHY_903_DATA 0x00000000
+#define DDRSS0_PHY_904_DATA 0x20202000
+#define DDRSS0_PHY_905_DATA 0x20202020
+#define DDRSS0_PHY_906_DATA 0xF0F02020
+#define DDRSS0_PHY_907_DATA 0x00000000
+#define DDRSS0_PHY_908_DATA 0x00000000
+#define DDRSS0_PHY_909_DATA 0x00000000
+#define DDRSS0_PHY_910_DATA 0x00000000
+#define DDRSS0_PHY_911_DATA 0x00000000
+#define DDRSS0_PHY_912_DATA 0x00000000
+#define DDRSS0_PHY_913_DATA 0x00000000
+#define DDRSS0_PHY_914_DATA 0x00000000
+#define DDRSS0_PHY_915_DATA 0x00000000
+#define DDRSS0_PHY_916_DATA 0x00000000
+#define DDRSS0_PHY_917_DATA 0x00000000
+#define DDRSS0_PHY_918_DATA 0x00000000
+#define DDRSS0_PHY_919_DATA 0x00000000
+#define DDRSS0_PHY_920_DATA 0x00000000
+#define DDRSS0_PHY_921_DATA 0x00000000
+#define DDRSS0_PHY_922_DATA 0x00000000
+#define DDRSS0_PHY_923_DATA 0x00000000
+#define DDRSS0_PHY_924_DATA 0x00000000
+#define DDRSS0_PHY_925_DATA 0x00000000
+#define DDRSS0_PHY_926_DATA 0x00000000
+#define DDRSS0_PHY_927_DATA 0x00000000
+#define DDRSS0_PHY_928_DATA 0x00000000
+#define DDRSS0_PHY_929_DATA 0x00000000
+#define DDRSS0_PHY_930_DATA 0x00000000
+#define DDRSS0_PHY_931_DATA 0x00000000
+#define DDRSS0_PHY_932_DATA 0x00000000
+#define DDRSS0_PHY_933_DATA 0x00000000
+#define DDRSS0_PHY_934_DATA 0x00000000
+#define DDRSS0_PHY_935_DATA 0x00000000
+#define DDRSS0_PHY_936_DATA 0x00000000
+#define DDRSS0_PHY_937_DATA 0x00000000
+#define DDRSS0_PHY_938_DATA 0x00000000
+#define DDRSS0_PHY_939_DATA 0x00000000
+#define DDRSS0_PHY_940_DATA 0x00000000
+#define DDRSS0_PHY_941_DATA 0x00000000
+#define DDRSS0_PHY_942_DATA 0x00000000
+#define DDRSS0_PHY_943_DATA 0x00000000
+#define DDRSS0_PHY_944_DATA 0x00000000
+#define DDRSS0_PHY_945_DATA 0x00000000
+#define DDRSS0_PHY_946_DATA 0x00000000
+#define DDRSS0_PHY_947_DATA 0x00000000
+#define DDRSS0_PHY_948_DATA 0x00000000
+#define DDRSS0_PHY_949_DATA 0x00000000
+#define DDRSS0_PHY_950_DATA 0x00000000
+#define DDRSS0_PHY_951_DATA 0x00000000
+#define DDRSS0_PHY_952_DATA 0x00000000
+#define DDRSS0_PHY_953_DATA 0x00000000
+#define DDRSS0_PHY_954_DATA 0x00000000
+#define DDRSS0_PHY_955_DATA 0x00000000
+#define DDRSS0_PHY_956_DATA 0x00000000
+#define DDRSS0_PHY_957_DATA 0x00000000
+#define DDRSS0_PHY_958_DATA 0x00000000
+#define DDRSS0_PHY_959_DATA 0x00000000
+#define DDRSS0_PHY_960_DATA 0x00000000
+#define DDRSS0_PHY_961_DATA 0x00000000
+#define DDRSS0_PHY_962_DATA 0x00000000
+#define DDRSS0_PHY_963_DATA 0x00000000
+#define DDRSS0_PHY_964_DATA 0x00000000
+#define DDRSS0_PHY_965_DATA 0x00000000
+#define DDRSS0_PHY_966_DATA 0x00000000
+#define DDRSS0_PHY_967_DATA 0x00000000
+#define DDRSS0_PHY_968_DATA 0x00000000
+#define DDRSS0_PHY_969_DATA 0x00000000
+#define DDRSS0_PHY_970_DATA 0x00000000
+#define DDRSS0_PHY_971_DATA 0x00000000
+#define DDRSS0_PHY_972_DATA 0x00000000
+#define DDRSS0_PHY_973_DATA 0x00000000
+#define DDRSS0_PHY_974_DATA 0x00000000
+#define DDRSS0_PHY_975_DATA 0x00000000
+#define DDRSS0_PHY_976_DATA 0x00000000
+#define DDRSS0_PHY_977_DATA 0x00000000
+#define DDRSS0_PHY_978_DATA 0x00000000
+#define DDRSS0_PHY_979_DATA 0x00000000
+#define DDRSS0_PHY_980_DATA 0x00000000
+#define DDRSS0_PHY_981_DATA 0x00000000
+#define DDRSS0_PHY_982_DATA 0x00000000
+#define DDRSS0_PHY_983_DATA 0x00000000
+#define DDRSS0_PHY_984_DATA 0x00000000
+#define DDRSS0_PHY_985_DATA 0x00000000
+#define DDRSS0_PHY_986_DATA 0x00000000
+#define DDRSS0_PHY_987_DATA 0x00000000
+#define DDRSS0_PHY_988_DATA 0x00000000
+#define DDRSS0_PHY_989_DATA 0x00000000
+#define DDRSS0_PHY_990_DATA 0x00000000
+#define DDRSS0_PHY_991_DATA 0x00000000
+#define DDRSS0_PHY_992_DATA 0x00000000
+#define DDRSS0_PHY_993_DATA 0x00000000
+#define DDRSS0_PHY_994_DATA 0x00000000
+#define DDRSS0_PHY_995_DATA 0x00000000
+#define DDRSS0_PHY_996_DATA 0x00000000
+#define DDRSS0_PHY_997_DATA 0x00000000
+#define DDRSS0_PHY_998_DATA 0x00000000
+#define DDRSS0_PHY_999_DATA 0x00000000
+#define DDRSS0_PHY_1000_DATA 0x00000000
+#define DDRSS0_PHY_1001_DATA 0x00000000
+#define DDRSS0_PHY_1002_DATA 0x00000000
+#define DDRSS0_PHY_1003_DATA 0x00000000
+#define DDRSS0_PHY_1004_DATA 0x00000000
+#define DDRSS0_PHY_1005_DATA 0x00000000
+#define DDRSS0_PHY_1006_DATA 0x00000000
+#define DDRSS0_PHY_1007_DATA 0x00000000
+#define DDRSS0_PHY_1008_DATA 0x00000000
+#define DDRSS0_PHY_1009_DATA 0x00000000
+#define DDRSS0_PHY_1010_DATA 0x00000000
+#define DDRSS0_PHY_1011_DATA 0x00000000
+#define DDRSS0_PHY_1012_DATA 0x00000000
+#define DDRSS0_PHY_1013_DATA 0x00000000
+#define DDRSS0_PHY_1014_DATA 0x00000000
+#define DDRSS0_PHY_1015_DATA 0x00000000
+#define DDRSS0_PHY_1016_DATA 0x00000000
+#define DDRSS0_PHY_1017_DATA 0x00000000
+#define DDRSS0_PHY_1018_DATA 0x00000000
+#define DDRSS0_PHY_1019_DATA 0x00000000
+#define DDRSS0_PHY_1020_DATA 0x00000000
+#define DDRSS0_PHY_1021_DATA 0x00000000
+#define DDRSS0_PHY_1022_DATA 0x00000000
+#define DDRSS0_PHY_1023_DATA 0x00000000
+#define DDRSS0_PHY_1024_DATA 0x00000000
+#define DDRSS0_PHY_1025_DATA 0x00000000
+#define DDRSS0_PHY_1026_DATA 0x00000000
+#define DDRSS0_PHY_1027_DATA 0x00000000
+#define DDRSS0_PHY_1028_DATA 0x00000000
+#define DDRSS0_PHY_1029_DATA 0x00000100
+#define DDRSS0_PHY_1030_DATA 0x00000200
+#define DDRSS0_PHY_1031_DATA 0x00000000
+#define DDRSS0_PHY_1032_DATA 0x00000000
+#define DDRSS0_PHY_1033_DATA 0x00000000
+#define DDRSS0_PHY_1034_DATA 0x00000000
+#define DDRSS0_PHY_1035_DATA 0x00400000
+#define DDRSS0_PHY_1036_DATA 0x00000080
+#define DDRSS0_PHY_1037_DATA 0x00DCBA98
+#define DDRSS0_PHY_1038_DATA 0x03000000
+#define DDRSS0_PHY_1039_DATA 0x00200000
+#define DDRSS0_PHY_1040_DATA 0x00000000
+#define DDRSS0_PHY_1041_DATA 0x00000000
+#define DDRSS0_PHY_1042_DATA 0x00000000
+#define DDRSS0_PHY_1043_DATA 0x00000000
+#define DDRSS0_PHY_1044_DATA 0x00000000
+#define DDRSS0_PHY_1045_DATA 0x0000002A
+#define DDRSS0_PHY_1046_DATA 0x00000015
+#define DDRSS0_PHY_1047_DATA 0x00000015
+#define DDRSS0_PHY_1048_DATA 0x0000002A
+#define DDRSS0_PHY_1049_DATA 0x00000033
+#define DDRSS0_PHY_1050_DATA 0x0000000C
+#define DDRSS0_PHY_1051_DATA 0x0000000C
+#define DDRSS0_PHY_1052_DATA 0x00000033
+#define DDRSS0_PHY_1053_DATA 0x00543210
+#define DDRSS0_PHY_1054_DATA 0x003F0000
+#define DDRSS0_PHY_1055_DATA 0x000F013F
+#define DDRSS0_PHY_1056_DATA 0x20202003
+#define DDRSS0_PHY_1057_DATA 0x00202020
+#define DDRSS0_PHY_1058_DATA 0x20008008
+#define DDRSS0_PHY_1059_DATA 0x00000810
+#define DDRSS0_PHY_1060_DATA 0x00000F00
+#define DDRSS0_PHY_1061_DATA 0x00000000
+#define DDRSS0_PHY_1062_DATA 0x00000000
+#define DDRSS0_PHY_1063_DATA 0x00000000
+#define DDRSS0_PHY_1064_DATA 0x000305CC
+#define DDRSS0_PHY_1065_DATA 0x00030000
+#define DDRSS0_PHY_1066_DATA 0x00000300
+#define DDRSS0_PHY_1067_DATA 0x00000300
+#define DDRSS0_PHY_1068_DATA 0x00000300
+#define DDRSS0_PHY_1069_DATA 0x00000300
+#define DDRSS0_PHY_1070_DATA 0x00000300
+#define DDRSS0_PHY_1071_DATA 0x42080010
+#define DDRSS0_PHY_1072_DATA 0x0000803E
+#define DDRSS0_PHY_1073_DATA 0x00000001
+#define DDRSS0_PHY_1074_DATA 0x01000102
+#define DDRSS0_PHY_1075_DATA 0x00008000
+#define DDRSS0_PHY_1076_DATA 0x00000000
+#define DDRSS0_PHY_1077_DATA 0x00000000
+#define DDRSS0_PHY_1078_DATA 0x00000000
+#define DDRSS0_PHY_1079_DATA 0x00000000
+#define DDRSS0_PHY_1080_DATA 0x00000000
+#define DDRSS0_PHY_1081_DATA 0x00000000
+#define DDRSS0_PHY_1082_DATA 0x00000000
+#define DDRSS0_PHY_1083_DATA 0x00000000
+#define DDRSS0_PHY_1084_DATA 0x00000000
+#define DDRSS0_PHY_1085_DATA 0x00000000
+#define DDRSS0_PHY_1086_DATA 0x00000000
+#define DDRSS0_PHY_1087_DATA 0x00000000
+#define DDRSS0_PHY_1088_DATA 0x00000000
+#define DDRSS0_PHY_1089_DATA 0x00000000
+#define DDRSS0_PHY_1090_DATA 0x00000000
+#define DDRSS0_PHY_1091_DATA 0x00000000
+#define DDRSS0_PHY_1092_DATA 0x00000000
+#define DDRSS0_PHY_1093_DATA 0x00000000
+#define DDRSS0_PHY_1094_DATA 0x00000000
+#define DDRSS0_PHY_1095_DATA 0x00000000
+#define DDRSS0_PHY_1096_DATA 0x00000000
+#define DDRSS0_PHY_1097_DATA 0x00000000
+#define DDRSS0_PHY_1098_DATA 0x00000000
+#define DDRSS0_PHY_1099_DATA 0x00000000
+#define DDRSS0_PHY_1100_DATA 0x00000000
+#define DDRSS0_PHY_1101_DATA 0x00000000
+#define DDRSS0_PHY_1102_DATA 0x00000000
+#define DDRSS0_PHY_1103_DATA 0x00000000
+#define DDRSS0_PHY_1104_DATA 0x00000000
+#define DDRSS0_PHY_1105_DATA 0x00000000
+#define DDRSS0_PHY_1106_DATA 0x00000000
+#define DDRSS0_PHY_1107_DATA 0x00000000
+#define DDRSS0_PHY_1108_DATA 0x00000000
+#define DDRSS0_PHY_1109_DATA 0x00000000
+#define DDRSS0_PHY_1110_DATA 0x00000000
+#define DDRSS0_PHY_1111_DATA 0x00000000
+#define DDRSS0_PHY_1112_DATA 0x00000000
+#define DDRSS0_PHY_1113_DATA 0x00000000
+#define DDRSS0_PHY_1114_DATA 0x00000000
+#define DDRSS0_PHY_1115_DATA 0x00000000
+#define DDRSS0_PHY_1116_DATA 0x00000000
+#define DDRSS0_PHY_1117_DATA 0x00000000
+#define DDRSS0_PHY_1118_DATA 0x00000000
+#define DDRSS0_PHY_1119_DATA 0x00000000
+#define DDRSS0_PHY_1120_DATA 0x00000000
+#define DDRSS0_PHY_1121_DATA 0x00000000
+#define DDRSS0_PHY_1122_DATA 0x00000000
+#define DDRSS0_PHY_1123_DATA 0x00000000
+#define DDRSS0_PHY_1124_DATA 0x00000000
+#define DDRSS0_PHY_1125_DATA 0x00000000
+#define DDRSS0_PHY_1126_DATA 0x00000000
+#define DDRSS0_PHY_1127_DATA 0x00000000
+#define DDRSS0_PHY_1128_DATA 0x00000000
+#define DDRSS0_PHY_1129_DATA 0x00000000
+#define DDRSS0_PHY_1130_DATA 0x00000000
+#define DDRSS0_PHY_1131_DATA 0x00000000
+#define DDRSS0_PHY_1132_DATA 0x00000000
+#define DDRSS0_PHY_1133_DATA 0x00000000
+#define DDRSS0_PHY_1134_DATA 0x00000000
+#define DDRSS0_PHY_1135_DATA 0x00000000
+#define DDRSS0_PHY_1136_DATA 0x00000000
+#define DDRSS0_PHY_1137_DATA 0x00000000
+#define DDRSS0_PHY_1138_DATA 0x00000000
+#define DDRSS0_PHY_1139_DATA 0x00000000
+#define DDRSS0_PHY_1140_DATA 0x00000000
+#define DDRSS0_PHY_1141_DATA 0x00000000
+#define DDRSS0_PHY_1142_DATA 0x00000000
+#define DDRSS0_PHY_1143_DATA 0x00000000
+#define DDRSS0_PHY_1144_DATA 0x00000000
+#define DDRSS0_PHY_1145_DATA 0x00000000
+#define DDRSS0_PHY_1146_DATA 0x00000000
+#define DDRSS0_PHY_1147_DATA 0x00000000
+#define DDRSS0_PHY_1148_DATA 0x00000000
+#define DDRSS0_PHY_1149_DATA 0x00000000
+#define DDRSS0_PHY_1150_DATA 0x00000000
+#define DDRSS0_PHY_1151_DATA 0x00000000
+#define DDRSS0_PHY_1152_DATA 0x00000000
+#define DDRSS0_PHY_1153_DATA 0x00000000
+#define DDRSS0_PHY_1154_DATA 0x00000000
+#define DDRSS0_PHY_1155_DATA 0x00000000
+#define DDRSS0_PHY_1156_DATA 0x00000000
+#define DDRSS0_PHY_1157_DATA 0x00000000
+#define DDRSS0_PHY_1158_DATA 0x00000000
+#define DDRSS0_PHY_1159_DATA 0x00000000
+#define DDRSS0_PHY_1160_DATA 0x00000000
+#define DDRSS0_PHY_1161_DATA 0x00000000
+#define DDRSS0_PHY_1162_DATA 0x00000000
+#define DDRSS0_PHY_1163_DATA 0x00000000
+#define DDRSS0_PHY_1164_DATA 0x00000000
+#define DDRSS0_PHY_1165_DATA 0x00000000
+#define DDRSS0_PHY_1166_DATA 0x00000000
+#define DDRSS0_PHY_1167_DATA 0x00000000
+#define DDRSS0_PHY_1168_DATA 0x00000000
+#define DDRSS0_PHY_1169_DATA 0x00000000
+#define DDRSS0_PHY_1170_DATA 0x00000000
+#define DDRSS0_PHY_1171_DATA 0x00000000
+#define DDRSS0_PHY_1172_DATA 0x00000000
+#define DDRSS0_PHY_1173_DATA 0x00000000
+#define DDRSS0_PHY_1174_DATA 0x00000000
+#define DDRSS0_PHY_1175_DATA 0x00000000
+#define DDRSS0_PHY_1176_DATA 0x00000000
+#define DDRSS0_PHY_1177_DATA 0x00000000
+#define DDRSS0_PHY_1178_DATA 0x00000000
+#define DDRSS0_PHY_1179_DATA 0x00000000
+#define DDRSS0_PHY_1180_DATA 0x00000000
+#define DDRSS0_PHY_1181_DATA 0x00000000
+#define DDRSS0_PHY_1182_DATA 0x00000000
+#define DDRSS0_PHY_1183_DATA 0x00000000
+#define DDRSS0_PHY_1184_DATA 0x00000000
+#define DDRSS0_PHY_1185_DATA 0x00000000
+#define DDRSS0_PHY_1186_DATA 0x00000000
+#define DDRSS0_PHY_1187_DATA 0x00000000
+#define DDRSS0_PHY_1188_DATA 0x00000000
+#define DDRSS0_PHY_1189_DATA 0x00000000
+#define DDRSS0_PHY_1190_DATA 0x00000000
+#define DDRSS0_PHY_1191_DATA 0x00000000
+#define DDRSS0_PHY_1192_DATA 0x00000000
+#define DDRSS0_PHY_1193_DATA 0x00000000
+#define DDRSS0_PHY_1194_DATA 0x00000000
+#define DDRSS0_PHY_1195_DATA 0x00000000
+#define DDRSS0_PHY_1196_DATA 0x00000000
+#define DDRSS0_PHY_1197_DATA 0x00000000
+#define DDRSS0_PHY_1198_DATA 0x00000000
+#define DDRSS0_PHY_1199_DATA 0x00000000
+#define DDRSS0_PHY_1200_DATA 0x00000000
+#define DDRSS0_PHY_1201_DATA 0x00000000
+#define DDRSS0_PHY_1202_DATA 0x00000000
+#define DDRSS0_PHY_1203_DATA 0x00000000
+#define DDRSS0_PHY_1204_DATA 0x00000000
+#define DDRSS0_PHY_1205_DATA 0x00000000
+#define DDRSS0_PHY_1206_DATA 0x00000000
+#define DDRSS0_PHY_1207_DATA 0x00000000
+#define DDRSS0_PHY_1208_DATA 0x00000000
+#define DDRSS0_PHY_1209_DATA 0x00000000
+#define DDRSS0_PHY_1210_DATA 0x00000000
+#define DDRSS0_PHY_1211_DATA 0x00000000
+#define DDRSS0_PHY_1212_DATA 0x00000000
+#define DDRSS0_PHY_1213_DATA 0x00000000
+#define DDRSS0_PHY_1214_DATA 0x00000000
+#define DDRSS0_PHY_1215_DATA 0x00000000
+#define DDRSS0_PHY_1216_DATA 0x00000000
+#define DDRSS0_PHY_1217_DATA 0x00000000
+#define DDRSS0_PHY_1218_DATA 0x00000000
+#define DDRSS0_PHY_1219_DATA 0x00000000
+#define DDRSS0_PHY_1220_DATA 0x00000000
+#define DDRSS0_PHY_1221_DATA 0x00000000
+#define DDRSS0_PHY_1222_DATA 0x00000000
+#define DDRSS0_PHY_1223_DATA 0x00000000
+#define DDRSS0_PHY_1224_DATA 0x00000000
+#define DDRSS0_PHY_1225_DATA 0x00000000
+#define DDRSS0_PHY_1226_DATA 0x00000000
+#define DDRSS0_PHY_1227_DATA 0x00000000
+#define DDRSS0_PHY_1228_DATA 0x00000000
+#define DDRSS0_PHY_1229_DATA 0x00000000
+#define DDRSS0_PHY_1230_DATA 0x00000000
+#define DDRSS0_PHY_1231_DATA 0x00000000
+#define DDRSS0_PHY_1232_DATA 0x00000000
+#define DDRSS0_PHY_1233_DATA 0x00000000
+#define DDRSS0_PHY_1234_DATA 0x00000000
+#define DDRSS0_PHY_1235_DATA 0x00000000
+#define DDRSS0_PHY_1236_DATA 0x00000000
+#define DDRSS0_PHY_1237_DATA 0x00000000
+#define DDRSS0_PHY_1238_DATA 0x00000000
+#define DDRSS0_PHY_1239_DATA 0x00000000
+#define DDRSS0_PHY_1240_DATA 0x00000000
+#define DDRSS0_PHY_1241_DATA 0x00000000
+#define DDRSS0_PHY_1242_DATA 0x00000000
+#define DDRSS0_PHY_1243_DATA 0x00000000
+#define DDRSS0_PHY_1244_DATA 0x00000000
+#define DDRSS0_PHY_1245_DATA 0x00000000
+#define DDRSS0_PHY_1246_DATA 0x00000000
+#define DDRSS0_PHY_1247_DATA 0x00000000
+#define DDRSS0_PHY_1248_DATA 0x00000000
+#define DDRSS0_PHY_1249_DATA 0x00000000
+#define DDRSS0_PHY_1250_DATA 0x00000000
+#define DDRSS0_PHY_1251_DATA 0x00000000
+#define DDRSS0_PHY_1252_DATA 0x00000000
+#define DDRSS0_PHY_1253_DATA 0x00000000
+#define DDRSS0_PHY_1254_DATA 0x00000000
+#define DDRSS0_PHY_1255_DATA 0x00000000
+#define DDRSS0_PHY_1256_DATA 0x00000000
+#define DDRSS0_PHY_1257_DATA 0x00000000
+#define DDRSS0_PHY_1258_DATA 0x00000000
+#define DDRSS0_PHY_1259_DATA 0x00000000
+#define DDRSS0_PHY_1260_DATA 0x00000000
+#define DDRSS0_PHY_1261_DATA 0x00000000
+#define DDRSS0_PHY_1262_DATA 0x00000000
+#define DDRSS0_PHY_1263_DATA 0x00000000
+#define DDRSS0_PHY_1264_DATA 0x00000000
+#define DDRSS0_PHY_1265_DATA 0x00000000
+#define DDRSS0_PHY_1266_DATA 0x00000000
+#define DDRSS0_PHY_1267_DATA 0x00000000
+#define DDRSS0_PHY_1268_DATA 0x00000000
+#define DDRSS0_PHY_1269_DATA 0x00000000
+#define DDRSS0_PHY_1270_DATA 0x00000000
+#define DDRSS0_PHY_1271_DATA 0x00000000
+#define DDRSS0_PHY_1272_DATA 0x00000000
+#define DDRSS0_PHY_1273_DATA 0x00000000
+#define DDRSS0_PHY_1274_DATA 0x00000000
+#define DDRSS0_PHY_1275_DATA 0x00000000
+#define DDRSS0_PHY_1276_DATA 0x00000000
+#define DDRSS0_PHY_1277_DATA 0x00000000
+#define DDRSS0_PHY_1278_DATA 0x00000000
+#define DDRSS0_PHY_1279_DATA 0x00000000
+#define DDRSS0_PHY_1280_DATA 0x00000000
+#define DDRSS0_PHY_1281_DATA 0x00010100
+#define DDRSS0_PHY_1282_DATA 0x00000000
+#define DDRSS0_PHY_1283_DATA 0x00000000
+#define DDRSS0_PHY_1284_DATA 0x00050000
+#define DDRSS0_PHY_1285_DATA 0x04000000
+#define DDRSS0_PHY_1286_DATA 0x00000055
+#define DDRSS0_PHY_1287_DATA 0x00000000
+#define DDRSS0_PHY_1288_DATA 0x00000000
+#define DDRSS0_PHY_1289_DATA 0x00000000
+#define DDRSS0_PHY_1290_DATA 0x00000000
+#define DDRSS0_PHY_1291_DATA 0x00002001
+#define DDRSS0_PHY_1292_DATA 0x0000400F
+#define DDRSS0_PHY_1293_DATA 0x50020028
+#define DDRSS0_PHY_1294_DATA 0x01010000
+#define DDRSS0_PHY_1295_DATA 0x80080001
+#define DDRSS0_PHY_1296_DATA 0x10200000
+#define DDRSS0_PHY_1297_DATA 0x00000008
+#define DDRSS0_PHY_1298_DATA 0x00000000
+#define DDRSS0_PHY_1299_DATA 0x01090E00
+#define DDRSS0_PHY_1300_DATA 0x00040101
+#define DDRSS0_PHY_1301_DATA 0x0000010F
+#define DDRSS0_PHY_1302_DATA 0x00000000
+#define DDRSS0_PHY_1303_DATA 0x0000FFFF
+#define DDRSS0_PHY_1304_DATA 0x00000000
+#define DDRSS0_PHY_1305_DATA 0x01010000
+#define DDRSS0_PHY_1306_DATA 0x01080402
+#define DDRSS0_PHY_1307_DATA 0x01200F02
+#define DDRSS0_PHY_1308_DATA 0x00194280
+#define DDRSS0_PHY_1309_DATA 0x00000004
+#define DDRSS0_PHY_1310_DATA 0x00052000
+#define DDRSS0_PHY_1311_DATA 0x00000000
+#define DDRSS0_PHY_1312_DATA 0x00000000
+#define DDRSS0_PHY_1313_DATA 0x00000000
+#define DDRSS0_PHY_1314_DATA 0x00000000
+#define DDRSS0_PHY_1315_DATA 0x00000000
+#define DDRSS0_PHY_1316_DATA 0x00000000
+#define DDRSS0_PHY_1317_DATA 0x01000000
+#define DDRSS0_PHY_1318_DATA 0x00000705
+#define DDRSS0_PHY_1319_DATA 0x00000054
+#define DDRSS0_PHY_1320_DATA 0x00030820
+#define DDRSS0_PHY_1321_DATA 0x00010820
+#define DDRSS0_PHY_1322_DATA 0x00010820
+#define DDRSS0_PHY_1323_DATA 0x00010820
+#define DDRSS0_PHY_1324_DATA 0x00010820
+#define DDRSS0_PHY_1325_DATA 0x00010820
+#define DDRSS0_PHY_1326_DATA 0x00010820
+#define DDRSS0_PHY_1327_DATA 0x00010820
+#define DDRSS0_PHY_1328_DATA 0x00010820
+#define DDRSS0_PHY_1329_DATA 0x00000000
+#define DDRSS0_PHY_1330_DATA 0x00000074
+#define DDRSS0_PHY_1331_DATA 0x00000400
+#define DDRSS0_PHY_1332_DATA 0x00000108
+#define DDRSS0_PHY_1333_DATA 0x00000000
+#define DDRSS0_PHY_1334_DATA 0x00000000
+#define DDRSS0_PHY_1335_DATA 0x00000000
+#define DDRSS0_PHY_1336_DATA 0x00000000
+#define DDRSS0_PHY_1337_DATA 0x00000000
+#define DDRSS0_PHY_1338_DATA 0x03000000
+#define DDRSS0_PHY_1339_DATA 0x00000000
+#define DDRSS0_PHY_1340_DATA 0x00000000
+#define DDRSS0_PHY_1341_DATA 0x00000000
+#define DDRSS0_PHY_1342_DATA 0x04102006
+#define DDRSS0_PHY_1343_DATA 0x00041020
+#define DDRSS0_PHY_1344_DATA 0x01C98C98
+#define DDRSS0_PHY_1345_DATA 0x3F400000
+#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS0_PHY_1347_DATA 0x0000001F
+#define DDRSS0_PHY_1348_DATA 0x00000000
+#define DDRSS0_PHY_1349_DATA 0x00000000
+#define DDRSS0_PHY_1350_DATA 0x00000000
+#define DDRSS0_PHY_1351_DATA 0x00010000
+#define DDRSS0_PHY_1352_DATA 0x00000000
+#define DDRSS0_PHY_1353_DATA 0x00000000
+#define DDRSS0_PHY_1354_DATA 0x00000000
+#define DDRSS0_PHY_1355_DATA 0x00000000
+#define DDRSS0_PHY_1356_DATA 0x76543210
+#define DDRSS0_PHY_1357_DATA 0x00010198
+#define DDRSS0_PHY_1358_DATA 0x00000000
+#define DDRSS0_PHY_1359_DATA 0x00000000
+#define DDRSS0_PHY_1360_DATA 0x00000000
+#define DDRSS0_PHY_1361_DATA 0x00040700
+#define DDRSS0_PHY_1362_DATA 0x00000000
+#define DDRSS0_PHY_1363_DATA 0x00000000
+#define DDRSS0_PHY_1364_DATA 0x00000000
+#define DDRSS0_PHY_1365_DATA 0x00000000
+#define DDRSS0_PHY_1366_DATA 0x00000000
+#define DDRSS0_PHY_1367_DATA 0x00000002
+#define DDRSS0_PHY_1368_DATA 0x00000000
+#define DDRSS0_PHY_1369_DATA 0x00000000
+#define DDRSS0_PHY_1370_DATA 0x00000000
+#define DDRSS0_PHY_1371_DATA 0x00000000
+#define DDRSS0_PHY_1372_DATA 0x00000000
+#define DDRSS0_PHY_1373_DATA 0x00000000
+#define DDRSS0_PHY_1374_DATA 0x00080000
+#define DDRSS0_PHY_1375_DATA 0x000007FF
+#define DDRSS0_PHY_1376_DATA 0x00000000
+#define DDRSS0_PHY_1377_DATA 0x00000000
+#define DDRSS0_PHY_1378_DATA 0x00000000
+#define DDRSS0_PHY_1379_DATA 0x00000000
+#define DDRSS0_PHY_1380_DATA 0x00000000
+#define DDRSS0_PHY_1381_DATA 0x00000000
+#define DDRSS0_PHY_1382_DATA 0x000FFFFF
+#define DDRSS0_PHY_1383_DATA 0x000FFFFF
+#define DDRSS0_PHY_1384_DATA 0x0000FFFF
+#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS0_PHY_1386_DATA 0x030FFFFF
+#define DDRSS0_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS0_PHY_1388_DATA 0x0000FFFF
+#define DDRSS0_PHY_1389_DATA 0x00000000
+#define DDRSS0_PHY_1390_DATA 0x00000000
+#define DDRSS0_PHY_1391_DATA 0x00000000
+#define DDRSS0_PHY_1392_DATA 0x00000000
+#define DDRSS0_PHY_1393_DATA 0x0001F7C0
+#define DDRSS0_PHY_1394_DATA 0x00000003
+#define DDRSS0_PHY_1395_DATA 0x00000000
+#define DDRSS0_PHY_1396_DATA 0x00001142
+#define DDRSS0_PHY_1397_DATA 0x010207AB
+#define DDRSS0_PHY_1398_DATA 0x01000080
+#define DDRSS0_PHY_1399_DATA 0x03900390
+#define DDRSS0_PHY_1400_DATA 0x03900390
+#define DDRSS0_PHY_1401_DATA 0x00000390
+#define DDRSS0_PHY_1402_DATA 0x00000390
+#define DDRSS0_PHY_1403_DATA 0x00000390
+#define DDRSS0_PHY_1404_DATA 0x00000390
+#define DDRSS0_PHY_1405_DATA 0x00000005
+#define DDRSS0_PHY_1406_DATA 0x01813FCC
+#define DDRSS0_PHY_1407_DATA 0x000000CC
+#define DDRSS0_PHY_1408_DATA 0x0C000DFF
+#define DDRSS0_PHY_1409_DATA 0x30000DFF
+#define DDRSS0_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1411_DATA 0x000100F0
+#define DDRSS0_PHY_1412_DATA 0x780DFFCC
+#define DDRSS0_PHY_1413_DATA 0x00007E31
+#define DDRSS0_PHY_1414_DATA 0x000CBF11
+#define DDRSS0_PHY_1415_DATA 0x01990010
+#define DDRSS0_PHY_1416_DATA 0x000CBF11
+#define DDRSS0_PHY_1417_DATA 0x01990010
+#define DDRSS0_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1419_DATA 0x00EF00F0
+#define DDRSS0_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1421_DATA 0x01FF00F0
+#define DDRSS0_PHY_1422_DATA 0x20040006
+
+#define DDRSS1_CTL_00_DATA 0x00000B00
+#define DDRSS1_CTL_01_DATA 0x00000000
+#define DDRSS1_CTL_02_DATA 0x00000000
+#define DDRSS1_CTL_03_DATA 0x00000000
+#define DDRSS1_CTL_04_DATA 0x00000000
+#define DDRSS1_CTL_05_DATA 0x00000000
+#define DDRSS1_CTL_06_DATA 0x00000000
+#define DDRSS1_CTL_07_DATA 0x00002AF8
+#define DDRSS1_CTL_08_DATA 0x0001ADAF
+#define DDRSS1_CTL_09_DATA 0x00000005
+#define DDRSS1_CTL_10_DATA 0x0000006E
+#define DDRSS1_CTL_11_DATA 0x000681C8
+#define DDRSS1_CTL_12_DATA 0x004111C9
+#define DDRSS1_CTL_13_DATA 0x00000005
+#define DDRSS1_CTL_14_DATA 0x000010A9
+#define DDRSS1_CTL_15_DATA 0x000681C8
+#define DDRSS1_CTL_16_DATA 0x004111C9
+#define DDRSS1_CTL_17_DATA 0x00000005
+#define DDRSS1_CTL_18_DATA 0x000010A9
+#define DDRSS1_CTL_19_DATA 0x01010000
+#define DDRSS1_CTL_20_DATA 0x02011001
+#define DDRSS1_CTL_21_DATA 0x02010000
+#define DDRSS1_CTL_22_DATA 0x00020100
+#define DDRSS1_CTL_23_DATA 0x0000000B
+#define DDRSS1_CTL_24_DATA 0x0000001C
+#define DDRSS1_CTL_25_DATA 0x00000000
+#define DDRSS1_CTL_26_DATA 0x00000000
+#define DDRSS1_CTL_27_DATA 0x03020200
+#define DDRSS1_CTL_28_DATA 0x00005656
+#define DDRSS1_CTL_29_DATA 0x00100000
+#define DDRSS1_CTL_30_DATA 0x00000000
+#define DDRSS1_CTL_31_DATA 0x00000000
+#define DDRSS1_CTL_32_DATA 0x00000000
+#define DDRSS1_CTL_33_DATA 0x00000000
+#define DDRSS1_CTL_34_DATA 0x040C0000
+#define DDRSS1_CTL_35_DATA 0x12481248
+#define DDRSS1_CTL_36_DATA 0x00050804
+#define DDRSS1_CTL_37_DATA 0x09040008
+#define DDRSS1_CTL_38_DATA 0x15000204
+#define DDRSS1_CTL_39_DATA 0x1760008B
+#define DDRSS1_CTL_40_DATA 0x1500422B
+#define DDRSS1_CTL_41_DATA 0x1760008B
+#define DDRSS1_CTL_42_DATA 0x2000422B
+#define DDRSS1_CTL_43_DATA 0x000A0A09
+#define DDRSS1_CTL_44_DATA 0x0400078A
+#define DDRSS1_CTL_45_DATA 0x1E161104
+#define DDRSS1_CTL_46_DATA 0x10012458
+#define DDRSS1_CTL_47_DATA 0x1E161110
+#define DDRSS1_CTL_48_DATA 0x10012458
+#define DDRSS1_CTL_49_DATA 0x02030410
+#define DDRSS1_CTL_50_DATA 0x2C040500
+#define DDRSS1_CTL_51_DATA 0x08292C29
+#define DDRSS1_CTL_52_DATA 0x14000E0A
+#define DDRSS1_CTL_53_DATA 0x04010A0A
+#define DDRSS1_CTL_54_DATA 0x01010004
+#define DDRSS1_CTL_55_DATA 0x04545408
+#define DDRSS1_CTL_56_DATA 0x04313104
+#define DDRSS1_CTL_57_DATA 0x00003131
+#define DDRSS1_CTL_58_DATA 0x00010100
+#define DDRSS1_CTL_59_DATA 0x03010000
+#define DDRSS1_CTL_60_DATA 0x00001508
+#define DDRSS1_CTL_61_DATA 0x000000CE
+#define DDRSS1_CTL_62_DATA 0x0000032B
+#define DDRSS1_CTL_63_DATA 0x00002073
+#define DDRSS1_CTL_64_DATA 0x0000032B
+#define DDRSS1_CTL_65_DATA 0x00002073
+#define DDRSS1_CTL_66_DATA 0x00000005
+#define DDRSS1_CTL_67_DATA 0x00050000
+#define DDRSS1_CTL_68_DATA 0x00CB0012
+#define DDRSS1_CTL_69_DATA 0x00CB0408
+#define DDRSS1_CTL_70_DATA 0x00400408
+#define DDRSS1_CTL_71_DATA 0x00120103
+#define DDRSS1_CTL_72_DATA 0x00100005
+#define DDRSS1_CTL_73_DATA 0x2F080010
+#define DDRSS1_CTL_74_DATA 0x0505012F
+#define DDRSS1_CTL_75_DATA 0x0401030A
+#define DDRSS1_CTL_76_DATA 0x041E100B
+#define DDRSS1_CTL_77_DATA 0x100B0401
+#define DDRSS1_CTL_78_DATA 0x0001041E
+#define DDRSS1_CTL_79_DATA 0x00160016
+#define DDRSS1_CTL_80_DATA 0x033B033B
+#define DDRSS1_CTL_81_DATA 0x033B033B
+#define DDRSS1_CTL_82_DATA 0x03050505
+#define DDRSS1_CTL_83_DATA 0x03010303
+#define DDRSS1_CTL_84_DATA 0x200B100B
+#define DDRSS1_CTL_85_DATA 0x04041004
+#define DDRSS1_CTL_86_DATA 0x200B100B
+#define DDRSS1_CTL_87_DATA 0x04041004
+#define DDRSS1_CTL_88_DATA 0x03010000
+#define DDRSS1_CTL_89_DATA 0x00010000
+#define DDRSS1_CTL_90_DATA 0x00000000
+#define DDRSS1_CTL_91_DATA 0x00000000
+#define DDRSS1_CTL_92_DATA 0x01000000
+#define DDRSS1_CTL_93_DATA 0x80104002
+#define DDRSS1_CTL_94_DATA 0x00000000
+#define DDRSS1_CTL_95_DATA 0x00040005
+#define DDRSS1_CTL_96_DATA 0x00000000
+#define DDRSS1_CTL_97_DATA 0x00050000
+#define DDRSS1_CTL_98_DATA 0x00000004
+#define DDRSS1_CTL_99_DATA 0x00000000
+#define DDRSS1_CTL_100_DATA 0x00040005
+#define DDRSS1_CTL_101_DATA 0x00000000
+#define DDRSS1_CTL_102_DATA 0x00003380
+#define DDRSS1_CTL_103_DATA 0x00003380
+#define DDRSS1_CTL_104_DATA 0x00003380
+#define DDRSS1_CTL_105_DATA 0x00003380
+#define DDRSS1_CTL_106_DATA 0x00003380
+#define DDRSS1_CTL_107_DATA 0x00000000
+#define DDRSS1_CTL_108_DATA 0x000005A2
+#define DDRSS1_CTL_109_DATA 0x00081CC0
+#define DDRSS1_CTL_110_DATA 0x00081CC0
+#define DDRSS1_CTL_111_DATA 0x00081CC0
+#define DDRSS1_CTL_112_DATA 0x00081CC0
+#define DDRSS1_CTL_113_DATA 0x00081CC0
+#define DDRSS1_CTL_114_DATA 0x00000000
+#define DDRSS1_CTL_115_DATA 0x0000E325
+#define DDRSS1_CTL_116_DATA 0x00081CC0
+#define DDRSS1_CTL_117_DATA 0x00081CC0
+#define DDRSS1_CTL_118_DATA 0x00081CC0
+#define DDRSS1_CTL_119_DATA 0x00081CC0
+#define DDRSS1_CTL_120_DATA 0x00081CC0
+#define DDRSS1_CTL_121_DATA 0x00000000
+#define DDRSS1_CTL_122_DATA 0x0000E325
+#define DDRSS1_CTL_123_DATA 0x00000000
+#define DDRSS1_CTL_124_DATA 0x00000000
+#define DDRSS1_CTL_125_DATA 0x00000000
+#define DDRSS1_CTL_126_DATA 0x00000000
+#define DDRSS1_CTL_127_DATA 0x00000000
+#define DDRSS1_CTL_128_DATA 0x00000000
+#define DDRSS1_CTL_129_DATA 0x00000000
+#define DDRSS1_CTL_130_DATA 0x00000000
+#define DDRSS1_CTL_131_DATA 0x0B030500
+#define DDRSS1_CTL_132_DATA 0x00040B04
+#define DDRSS1_CTL_133_DATA 0x0A090000
+#define DDRSS1_CTL_134_DATA 0x0A090701
+#define DDRSS1_CTL_135_DATA 0x0900000E
+#define DDRSS1_CTL_136_DATA 0x0907010A
+#define DDRSS1_CTL_137_DATA 0x00000E0A
+#define DDRSS1_CTL_138_DATA 0x07010A09
+#define DDRSS1_CTL_139_DATA 0x000E0A09
+#define DDRSS1_CTL_140_DATA 0x07000401
+#define DDRSS1_CTL_141_DATA 0x00000000
+#define DDRSS1_CTL_142_DATA 0x00000000
+#define DDRSS1_CTL_143_DATA 0x00000000
+#define DDRSS1_CTL_144_DATA 0x00000000
+#define DDRSS1_CTL_145_DATA 0x00000000
+#define DDRSS1_CTL_146_DATA 0x00000000
+#define DDRSS1_CTL_147_DATA 0x00000000
+#define DDRSS1_CTL_148_DATA 0x08080000
+#define DDRSS1_CTL_149_DATA 0x01000000
+#define DDRSS1_CTL_150_DATA 0x800000C0
+#define DDRSS1_CTL_151_DATA 0x800000C0
+#define DDRSS1_CTL_152_DATA 0x800000C0
+#define DDRSS1_CTL_153_DATA 0x00000000
+#define DDRSS1_CTL_154_DATA 0x00001500
+#define DDRSS1_CTL_155_DATA 0x00000000
+#define DDRSS1_CTL_156_DATA 0x00000001
+#define DDRSS1_CTL_157_DATA 0x00000002
+#define DDRSS1_CTL_158_DATA 0x0000100E
+#define DDRSS1_CTL_159_DATA 0x00000000
+#define DDRSS1_CTL_160_DATA 0x00000000
+#define DDRSS1_CTL_161_DATA 0x00000000
+#define DDRSS1_CTL_162_DATA 0x00000000
+#define DDRSS1_CTL_163_DATA 0x00000000
+#define DDRSS1_CTL_164_DATA 0x000B0000
+#define DDRSS1_CTL_165_DATA 0x000E0006
+#define DDRSS1_CTL_166_DATA 0x000E0404
+#define DDRSS1_CTL_167_DATA 0x00D601AB
+#define DDRSS1_CTL_168_DATA 0x10100216
+#define DDRSS1_CTL_169_DATA 0x01AB0216
+#define DDRSS1_CTL_170_DATA 0x021600D6
+#define DDRSS1_CTL_171_DATA 0x02161010
+#define DDRSS1_CTL_172_DATA 0x00000000
+#define DDRSS1_CTL_173_DATA 0x00000000
+#define DDRSS1_CTL_174_DATA 0x00000000
+#define DDRSS1_CTL_175_DATA 0x3FF40084
+#define DDRSS1_CTL_176_DATA 0x33003FF4
+#define DDRSS1_CTL_177_DATA 0x00003333
+#define DDRSS1_CTL_178_DATA 0x56000000
+#define DDRSS1_CTL_179_DATA 0x27270056
+#define DDRSS1_CTL_180_DATA 0x0F0F0000
+#define DDRSS1_CTL_181_DATA 0x16000000
+#define DDRSS1_CTL_182_DATA 0x00841616
+#define DDRSS1_CTL_183_DATA 0x3FF43FF4
+#define DDRSS1_CTL_184_DATA 0x33333300
+#define DDRSS1_CTL_185_DATA 0x00000000
+#define DDRSS1_CTL_186_DATA 0x00565600
+#define DDRSS1_CTL_187_DATA 0x00002727
+#define DDRSS1_CTL_188_DATA 0x00000F0F
+#define DDRSS1_CTL_189_DATA 0x16161600
+#define DDRSS1_CTL_190_DATA 0x00000020
+#define DDRSS1_CTL_191_DATA 0x00000000
+#define DDRSS1_CTL_192_DATA 0x00000001
+#define DDRSS1_CTL_193_DATA 0x00000000
+#define DDRSS1_CTL_194_DATA 0x01000000
+#define DDRSS1_CTL_195_DATA 0x00000001
+#define DDRSS1_CTL_196_DATA 0x00000000
+#define DDRSS1_CTL_197_DATA 0x00000000
+#define DDRSS1_CTL_198_DATA 0x00000000
+#define DDRSS1_CTL_199_DATA 0x00000000
+#define DDRSS1_CTL_200_DATA 0x00000000
+#define DDRSS1_CTL_201_DATA 0x00000000
+#define DDRSS1_CTL_202_DATA 0x00000000
+#define DDRSS1_CTL_203_DATA 0x00000000
+#define DDRSS1_CTL_204_DATA 0x00000000
+#define DDRSS1_CTL_205_DATA 0x00000000
+#define DDRSS1_CTL_206_DATA 0x02000000
+#define DDRSS1_CTL_207_DATA 0x01080101
+#define DDRSS1_CTL_208_DATA 0x00000000
+#define DDRSS1_CTL_209_DATA 0x00000000
+#define DDRSS1_CTL_210_DATA 0x00000000
+#define DDRSS1_CTL_211_DATA 0x00000000
+#define DDRSS1_CTL_212_DATA 0x00000000
+#define DDRSS1_CTL_213_DATA 0x00000000
+#define DDRSS1_CTL_214_DATA 0x00000000
+#define DDRSS1_CTL_215_DATA 0x00000000
+#define DDRSS1_CTL_216_DATA 0x00000000
+#define DDRSS1_CTL_217_DATA 0x00000000
+#define DDRSS1_CTL_218_DATA 0x00000000
+#define DDRSS1_CTL_219_DATA 0x00000000
+#define DDRSS1_CTL_220_DATA 0x00000000
+#define DDRSS1_CTL_221_DATA 0x00000000
+#define DDRSS1_CTL_222_DATA 0x00001000
+#define DDRSS1_CTL_223_DATA 0x006403E8
+#define DDRSS1_CTL_224_DATA 0x00000000
+#define DDRSS1_CTL_225_DATA 0x00000000
+#define DDRSS1_CTL_226_DATA 0x00000000
+#define DDRSS1_CTL_227_DATA 0x15110000
+#define DDRSS1_CTL_228_DATA 0x00040C18
+#define DDRSS1_CTL_229_DATA 0x00000000
+#define DDRSS1_CTL_230_DATA 0x00000000
+#define DDRSS1_CTL_231_DATA 0x00000000
+#define DDRSS1_CTL_232_DATA 0x00000000
+#define DDRSS1_CTL_233_DATA 0x00000000
+#define DDRSS1_CTL_234_DATA 0x00000000
+#define DDRSS1_CTL_235_DATA 0x00000000
+#define DDRSS1_CTL_236_DATA 0x00000000
+#define DDRSS1_CTL_237_DATA 0x00000000
+#define DDRSS1_CTL_238_DATA 0x00000000
+#define DDRSS1_CTL_239_DATA 0x00000000
+#define DDRSS1_CTL_240_DATA 0x00000000
+#define DDRSS1_CTL_241_DATA 0x00000000
+#define DDRSS1_CTL_242_DATA 0x00030000
+#define DDRSS1_CTL_243_DATA 0x00000000
+#define DDRSS1_CTL_244_DATA 0x00000000
+#define DDRSS1_CTL_245_DATA 0x00000000
+#define DDRSS1_CTL_246_DATA 0x00000000
+#define DDRSS1_CTL_247_DATA 0x00000000
+#define DDRSS1_CTL_248_DATA 0x00000000
+#define DDRSS1_CTL_249_DATA 0x00000000
+#define DDRSS1_CTL_250_DATA 0x00000000
+#define DDRSS1_CTL_251_DATA 0x00000000
+#define DDRSS1_CTL_252_DATA 0x00000000
+#define DDRSS1_CTL_253_DATA 0x00000000
+#define DDRSS1_CTL_254_DATA 0x00000000
+#define DDRSS1_CTL_255_DATA 0x00000000
+#define DDRSS1_CTL_256_DATA 0x00000000
+#define DDRSS1_CTL_257_DATA 0x01000200
+#define DDRSS1_CTL_258_DATA 0x00370040
+#define DDRSS1_CTL_259_DATA 0x00020008
+#define DDRSS1_CTL_260_DATA 0x00400100
+#define DDRSS1_CTL_261_DATA 0x00400855
+#define DDRSS1_CTL_262_DATA 0x01000200
+#define DDRSS1_CTL_263_DATA 0x08550040
+#define DDRSS1_CTL_264_DATA 0x00000040
+#define DDRSS1_CTL_265_DATA 0x006B0003
+#define DDRSS1_CTL_266_DATA 0x0100006B
+#define DDRSS1_CTL_267_DATA 0x00000000
+#define DDRSS1_CTL_268_DATA 0x00000000
+#define DDRSS1_CTL_269_DATA 0x00000202
+#define DDRSS1_CTL_270_DATA 0x00001FFF
+#define DDRSS1_CTL_271_DATA 0x3FFF2000
+#define DDRSS1_CTL_272_DATA 0x03FF0000
+#define DDRSS1_CTL_273_DATA 0x000103FF
+#define DDRSS1_CTL_274_DATA 0x0FFF0B00
+#define DDRSS1_CTL_275_DATA 0x01010001
+#define DDRSS1_CTL_276_DATA 0x01010101
+#define DDRSS1_CTL_277_DATA 0x01180101
+#define DDRSS1_CTL_278_DATA 0x00030000
+#define DDRSS1_CTL_279_DATA 0x00000000
+#define DDRSS1_CTL_280_DATA 0x00000000
+#define DDRSS1_CTL_281_DATA 0x00000000
+#define DDRSS1_CTL_282_DATA 0x00000000
+#define DDRSS1_CTL_283_DATA 0x00000000
+#define DDRSS1_CTL_284_DATA 0x00000000
+#define DDRSS1_CTL_285_DATA 0x00000000
+#define DDRSS1_CTL_286_DATA 0x00040101
+#define DDRSS1_CTL_287_DATA 0x04010100
+#define DDRSS1_CTL_288_DATA 0x00000000
+#define DDRSS1_CTL_289_DATA 0x00000000
+#define DDRSS1_CTL_290_DATA 0x03030300
+#define DDRSS1_CTL_291_DATA 0x00000001
+#define DDRSS1_CTL_292_DATA 0x00000000
+#define DDRSS1_CTL_293_DATA 0x00000000
+#define DDRSS1_CTL_294_DATA 0x00000000
+#define DDRSS1_CTL_295_DATA 0x00000000
+#define DDRSS1_CTL_296_DATA 0x00000000
+#define DDRSS1_CTL_297_DATA 0x00000000
+#define DDRSS1_CTL_298_DATA 0x00000000
+#define DDRSS1_CTL_299_DATA 0x00000000
+#define DDRSS1_CTL_300_DATA 0x00000000
+#define DDRSS1_CTL_301_DATA 0x00000000
+#define DDRSS1_CTL_302_DATA 0x00000000
+#define DDRSS1_CTL_303_DATA 0x00000000
+#define DDRSS1_CTL_304_DATA 0x00000000
+#define DDRSS1_CTL_305_DATA 0x00000000
+#define DDRSS1_CTL_306_DATA 0x00000000
+#define DDRSS1_CTL_307_DATA 0x00000000
+#define DDRSS1_CTL_308_DATA 0x00000000
+#define DDRSS1_CTL_309_DATA 0x00000000
+#define DDRSS1_CTL_310_DATA 0x00000000
+#define DDRSS1_CTL_311_DATA 0x00000000
+#define DDRSS1_CTL_312_DATA 0x00000000
+#define DDRSS1_CTL_313_DATA 0x01000000
+#define DDRSS1_CTL_314_DATA 0x00020201
+#define DDRSS1_CTL_315_DATA 0x01000101
+#define DDRSS1_CTL_316_DATA 0x01010001
+#define DDRSS1_CTL_317_DATA 0x00010101
+#define DDRSS1_CTL_318_DATA 0x050A0A03
+#define DDRSS1_CTL_319_DATA 0x10081F1F
+#define DDRSS1_CTL_320_DATA 0x00090310
+#define DDRSS1_CTL_321_DATA 0x0B0C030F
+#define DDRSS1_CTL_322_DATA 0x0B0C0306
+#define DDRSS1_CTL_323_DATA 0x0C090006
+#define DDRSS1_CTL_324_DATA 0x0100000C
+#define DDRSS1_CTL_325_DATA 0x08040801
+#define DDRSS1_CTL_326_DATA 0x00000004
+#define DDRSS1_CTL_327_DATA 0x00000000
+#define DDRSS1_CTL_328_DATA 0x00010000
+#define DDRSS1_CTL_329_DATA 0x00280D00
+#define DDRSS1_CTL_330_DATA 0x00000001
+#define DDRSS1_CTL_331_DATA 0x00030001
+#define DDRSS1_CTL_332_DATA 0x00000000
+#define DDRSS1_CTL_333_DATA 0x00000000
+#define DDRSS1_CTL_334_DATA 0x00000000
+#define DDRSS1_CTL_335_DATA 0x00000000
+#define DDRSS1_CTL_336_DATA 0x00000000
+#define DDRSS1_CTL_337_DATA 0x00000000
+#define DDRSS1_CTL_338_DATA 0x00000000
+#define DDRSS1_CTL_339_DATA 0x00000000
+#define DDRSS1_CTL_340_DATA 0x01000000
+#define DDRSS1_CTL_341_DATA 0x00000001
+#define DDRSS1_CTL_342_DATA 0x00010100
+#define DDRSS1_CTL_343_DATA 0x03030000
+#define DDRSS1_CTL_344_DATA 0x00000000
+#define DDRSS1_CTL_345_DATA 0x00000000
+#define DDRSS1_CTL_346_DATA 0x00000000
+#define DDRSS1_CTL_347_DATA 0x00000000
+#define DDRSS1_CTL_348_DATA 0x00000000
+#define DDRSS1_CTL_349_DATA 0x00000000
+#define DDRSS1_CTL_350_DATA 0x00000000
+#define DDRSS1_CTL_351_DATA 0x00000000
+#define DDRSS1_CTL_352_DATA 0x00000000
+#define DDRSS1_CTL_353_DATA 0x00000000
+#define DDRSS1_CTL_354_DATA 0x00000000
+#define DDRSS1_CTL_355_DATA 0x00000000
+#define DDRSS1_CTL_356_DATA 0x00000000
+#define DDRSS1_CTL_357_DATA 0x00000000
+#define DDRSS1_CTL_358_DATA 0x00000000
+#define DDRSS1_CTL_359_DATA 0x00000000
+#define DDRSS1_CTL_360_DATA 0x000556AA
+#define DDRSS1_CTL_361_DATA 0x000AAAAA
+#define DDRSS1_CTL_362_DATA 0x000AA955
+#define DDRSS1_CTL_363_DATA 0x00055555
+#define DDRSS1_CTL_364_DATA 0x000B3133
+#define DDRSS1_CTL_365_DATA 0x0004CD33
+#define DDRSS1_CTL_366_DATA 0x0004CECC
+#define DDRSS1_CTL_367_DATA 0x000B32CC
+#define DDRSS1_CTL_368_DATA 0x00010300
+#define DDRSS1_CTL_369_DATA 0x03000100
+#define DDRSS1_CTL_370_DATA 0x00000000
+#define DDRSS1_CTL_371_DATA 0x00000000
+#define DDRSS1_CTL_372_DATA 0x00000000
+#define DDRSS1_CTL_373_DATA 0x00000000
+#define DDRSS1_CTL_374_DATA 0x00000000
+#define DDRSS1_CTL_375_DATA 0x00000000
+#define DDRSS1_CTL_376_DATA 0x00000000
+#define DDRSS1_CTL_377_DATA 0x00010000
+#define DDRSS1_CTL_378_DATA 0x00000404
+#define DDRSS1_CTL_379_DATA 0x00000000
+#define DDRSS1_CTL_380_DATA 0x00000000
+#define DDRSS1_CTL_381_DATA 0x00000000
+#define DDRSS1_CTL_382_DATA 0x00000000
+#define DDRSS1_CTL_383_DATA 0x00000000
+#define DDRSS1_CTL_384_DATA 0x00000000
+#define DDRSS1_CTL_385_DATA 0x00000000
+#define DDRSS1_CTL_386_DATA 0x00000000
+#define DDRSS1_CTL_387_DATA 0x3A3A1B00
+#define DDRSS1_CTL_388_DATA 0x000A0000
+#define DDRSS1_CTL_389_DATA 0x0000019C
+#define DDRSS1_CTL_390_DATA 0x00000200
+#define DDRSS1_CTL_391_DATA 0x00000200
+#define DDRSS1_CTL_392_DATA 0x00000200
+#define DDRSS1_CTL_393_DATA 0x00000200
+#define DDRSS1_CTL_394_DATA 0x000004D4
+#define DDRSS1_CTL_395_DATA 0x00001018
+#define DDRSS1_CTL_396_DATA 0x00000204
+#define DDRSS1_CTL_397_DATA 0x000040E6
+#define DDRSS1_CTL_398_DATA 0x00000200
+#define DDRSS1_CTL_399_DATA 0x00000200
+#define DDRSS1_CTL_400_DATA 0x00000200
+#define DDRSS1_CTL_401_DATA 0x00000200
+#define DDRSS1_CTL_402_DATA 0x0000C2B2
+#define DDRSS1_CTL_403_DATA 0x000288FC
+#define DDRSS1_CTL_404_DATA 0x00000E15
+#define DDRSS1_CTL_405_DATA 0x000040E6
+#define DDRSS1_CTL_406_DATA 0x00000200
+#define DDRSS1_CTL_407_DATA 0x00000200
+#define DDRSS1_CTL_408_DATA 0x00000200
+#define DDRSS1_CTL_409_DATA 0x00000200
+#define DDRSS1_CTL_410_DATA 0x0000C2B2
+#define DDRSS1_CTL_411_DATA 0x000288FC
+#define DDRSS1_CTL_412_DATA 0x02020E15
+#define DDRSS1_CTL_413_DATA 0x03030202
+#define DDRSS1_CTL_414_DATA 0x00000022
+#define DDRSS1_CTL_415_DATA 0x00000000
+#define DDRSS1_CTL_416_DATA 0x00000000
+#define DDRSS1_CTL_417_DATA 0x00001403
+#define DDRSS1_CTL_418_DATA 0x000007D0
+#define DDRSS1_CTL_419_DATA 0x00000000
+#define DDRSS1_CTL_420_DATA 0x00000000
+#define DDRSS1_CTL_421_DATA 0x00030000
+#define DDRSS1_CTL_422_DATA 0x0007001F
+#define DDRSS1_CTL_423_DATA 0x001B0033
+#define DDRSS1_CTL_424_DATA 0x001B0033
+#define DDRSS1_CTL_425_DATA 0x00000000
+#define DDRSS1_CTL_426_DATA 0x00000000
+#define DDRSS1_CTL_427_DATA 0x02000000
+#define DDRSS1_CTL_428_DATA 0x01000404
+#define DDRSS1_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS1_CTL_430_DATA 0x00000105
+#define DDRSS1_CTL_431_DATA 0x00010101
+#define DDRSS1_CTL_432_DATA 0x00010101
+#define DDRSS1_CTL_433_DATA 0x00010001
+#define DDRSS1_CTL_434_DATA 0x00000101
+#define DDRSS1_CTL_435_DATA 0x02000201
+#define DDRSS1_CTL_436_DATA 0x02010000
+#define DDRSS1_CTL_437_DATA 0x00000200
+#define DDRSS1_CTL_438_DATA 0x28060000
+#define DDRSS1_CTL_439_DATA 0x00000128
+#define DDRSS1_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_442_DATA 0x00000000
+#define DDRSS1_CTL_443_DATA 0x00000000
+#define DDRSS1_CTL_444_DATA 0x00000000
+#define DDRSS1_CTL_445_DATA 0x00000000
+#define DDRSS1_CTL_446_DATA 0x00000000
+#define DDRSS1_CTL_447_DATA 0x00000000
+#define DDRSS1_CTL_448_DATA 0x00000000
+#define DDRSS1_CTL_449_DATA 0x00000000
+#define DDRSS1_CTL_450_DATA 0x00000000
+#define DDRSS1_CTL_451_DATA 0x00000000
+#define DDRSS1_CTL_452_DATA 0x00000000
+#define DDRSS1_CTL_453_DATA 0x00000000
+#define DDRSS1_CTL_454_DATA 0x00000000
+#define DDRSS1_CTL_455_DATA 0x00000000
+#define DDRSS1_CTL_456_DATA 0x00000000
+#define DDRSS1_CTL_457_DATA 0x00000000
+#define DDRSS1_CTL_458_DATA 0x00000000
+
+#define DDRSS1_PI_00_DATA 0x00000B00
+#define DDRSS1_PI_01_DATA 0x00000000
+#define DDRSS1_PI_02_DATA 0x00000000
+#define DDRSS1_PI_03_DATA 0x00000000
+#define DDRSS1_PI_04_DATA 0x00000000
+#define DDRSS1_PI_05_DATA 0x00000101
+#define DDRSS1_PI_06_DATA 0x00640000
+#define DDRSS1_PI_07_DATA 0x00000001
+#define DDRSS1_PI_08_DATA 0x00000000
+#define DDRSS1_PI_09_DATA 0x00000000
+#define DDRSS1_PI_10_DATA 0x00000000
+#define DDRSS1_PI_11_DATA 0x00000000
+#define DDRSS1_PI_12_DATA 0x00000007
+#define DDRSS1_PI_13_DATA 0x00010002
+#define DDRSS1_PI_14_DATA 0x0800000F
+#define DDRSS1_PI_15_DATA 0x00000103
+#define DDRSS1_PI_16_DATA 0x00000005
+#define DDRSS1_PI_17_DATA 0x00000000
+#define DDRSS1_PI_18_DATA 0x00000000
+#define DDRSS1_PI_19_DATA 0x00000000
+#define DDRSS1_PI_20_DATA 0x00000000
+#define DDRSS1_PI_21_DATA 0x00000000
+#define DDRSS1_PI_22_DATA 0x00000000
+#define DDRSS1_PI_23_DATA 0x00000000
+#define DDRSS1_PI_24_DATA 0x00000000
+#define DDRSS1_PI_25_DATA 0x00000000
+#define DDRSS1_PI_26_DATA 0x00010100
+#define DDRSS1_PI_27_DATA 0x00280A00
+#define DDRSS1_PI_28_DATA 0x00000000
+#define DDRSS1_PI_29_DATA 0x0F000000
+#define DDRSS1_PI_30_DATA 0x00003200
+#define DDRSS1_PI_31_DATA 0x00000000
+#define DDRSS1_PI_32_DATA 0x00000000
+#define DDRSS1_PI_33_DATA 0x01010102
+#define DDRSS1_PI_34_DATA 0x00000000
+#define DDRSS1_PI_35_DATA 0x000000AA
+#define DDRSS1_PI_36_DATA 0x00000055
+#define DDRSS1_PI_37_DATA 0x000000B5
+#define DDRSS1_PI_38_DATA 0x0000004A
+#define DDRSS1_PI_39_DATA 0x00000056
+#define DDRSS1_PI_40_DATA 0x000000A9
+#define DDRSS1_PI_41_DATA 0x000000A9
+#define DDRSS1_PI_42_DATA 0x000000B5
+#define DDRSS1_PI_43_DATA 0x00000000
+#define DDRSS1_PI_44_DATA 0x00000000
+#define DDRSS1_PI_45_DATA 0x000F0F00
+#define DDRSS1_PI_46_DATA 0x0000001B
+#define DDRSS1_PI_47_DATA 0x000007D0
+#define DDRSS1_PI_48_DATA 0x00000300
+#define DDRSS1_PI_49_DATA 0x00000000
+#define DDRSS1_PI_50_DATA 0x00000000
+#define DDRSS1_PI_51_DATA 0x01000000
+#define DDRSS1_PI_52_DATA 0x00010101
+#define DDRSS1_PI_53_DATA 0x00000000
+#define DDRSS1_PI_54_DATA 0x00030000
+#define DDRSS1_PI_55_DATA 0x0F000000
+#define DDRSS1_PI_56_DATA 0x00000017
+#define DDRSS1_PI_57_DATA 0x00000000
+#define DDRSS1_PI_58_DATA 0x00000000
+#define DDRSS1_PI_59_DATA 0x00000000
+#define DDRSS1_PI_60_DATA 0x0A0A140A
+#define DDRSS1_PI_61_DATA 0x10020101
+#define DDRSS1_PI_62_DATA 0x00020805
+#define DDRSS1_PI_63_DATA 0x01000404
+#define DDRSS1_PI_64_DATA 0x00000000
+#define DDRSS1_PI_65_DATA 0x00000000
+#define DDRSS1_PI_66_DATA 0x00000100
+#define DDRSS1_PI_67_DATA 0x0001010F
+#define DDRSS1_PI_68_DATA 0x00340000
+#define DDRSS1_PI_69_DATA 0x00000000
+#define DDRSS1_PI_70_DATA 0x00000000
+#define DDRSS1_PI_71_DATA 0x0000FFFF
+#define DDRSS1_PI_72_DATA 0x00000000
+#define DDRSS1_PI_73_DATA 0x00080000
+#define DDRSS1_PI_74_DATA 0x02000200
+#define DDRSS1_PI_75_DATA 0x01000100
+#define DDRSS1_PI_76_DATA 0x01000000
+#define DDRSS1_PI_77_DATA 0x02000200
+#define DDRSS1_PI_78_DATA 0x00000200
+#define DDRSS1_PI_79_DATA 0x00000000
+#define DDRSS1_PI_80_DATA 0x00000000
+#define DDRSS1_PI_81_DATA 0x00000000
+#define DDRSS1_PI_82_DATA 0x00000000
+#define DDRSS1_PI_83_DATA 0x00000000
+#define DDRSS1_PI_84_DATA 0x00000000
+#define DDRSS1_PI_85_DATA 0x00000000
+#define DDRSS1_PI_86_DATA 0x00000000
+#define DDRSS1_PI_87_DATA 0x00000000
+#define DDRSS1_PI_88_DATA 0x00000000
+#define DDRSS1_PI_89_DATA 0x00000000
+#define DDRSS1_PI_90_DATA 0x00000000
+#define DDRSS1_PI_91_DATA 0x00000400
+#define DDRSS1_PI_92_DATA 0x02010000
+#define DDRSS1_PI_93_DATA 0x00080003
+#define DDRSS1_PI_94_DATA 0x00080000
+#define DDRSS1_PI_95_DATA 0x00000001
+#define DDRSS1_PI_96_DATA 0x00000000
+#define DDRSS1_PI_97_DATA 0x0000AA00
+#define DDRSS1_PI_98_DATA 0x00000000
+#define DDRSS1_PI_99_DATA 0x00000000
+#define DDRSS1_PI_100_DATA 0x00010000
+#define DDRSS1_PI_101_DATA 0x00000000
+#define DDRSS1_PI_102_DATA 0x00000000
+#define DDRSS1_PI_103_DATA 0x00000000
+#define DDRSS1_PI_104_DATA 0x00000000
+#define DDRSS1_PI_105_DATA 0x00000000
+#define DDRSS1_PI_106_DATA 0x00000000
+#define DDRSS1_PI_107_DATA 0x00000000
+#define DDRSS1_PI_108_DATA 0x00000000
+#define DDRSS1_PI_109_DATA 0x00000000
+#define DDRSS1_PI_110_DATA 0x00000000
+#define DDRSS1_PI_111_DATA 0x00000000
+#define DDRSS1_PI_112_DATA 0x00000000
+#define DDRSS1_PI_113_DATA 0x00000000
+#define DDRSS1_PI_114_DATA 0x00000000
+#define DDRSS1_PI_115_DATA 0x00000000
+#define DDRSS1_PI_116_DATA 0x00000000
+#define DDRSS1_PI_117_DATA 0x00000000
+#define DDRSS1_PI_118_DATA 0x00000000
+#define DDRSS1_PI_119_DATA 0x00000000
+#define DDRSS1_PI_120_DATA 0x00000000
+#define DDRSS1_PI_121_DATA 0x00000000
+#define DDRSS1_PI_122_DATA 0x00000000
+#define DDRSS1_PI_123_DATA 0x00000000
+#define DDRSS1_PI_124_DATA 0x00000000
+#define DDRSS1_PI_125_DATA 0x00000008
+#define DDRSS1_PI_126_DATA 0x00000000
+#define DDRSS1_PI_127_DATA 0x00000000
+#define DDRSS1_PI_128_DATA 0x00000000
+#define DDRSS1_PI_129_DATA 0x00000000
+#define DDRSS1_PI_130_DATA 0x00000000
+#define DDRSS1_PI_131_DATA 0x00000000
+#define DDRSS1_PI_132_DATA 0x00000000
+#define DDRSS1_PI_133_DATA 0x00000000
+#define DDRSS1_PI_134_DATA 0x00000002
+#define DDRSS1_PI_135_DATA 0x00000000
+#define DDRSS1_PI_136_DATA 0x00000000
+#define DDRSS1_PI_137_DATA 0x0000000A
+#define DDRSS1_PI_138_DATA 0x00000019
+#define DDRSS1_PI_139_DATA 0x00000100
+#define DDRSS1_PI_140_DATA 0x00000000
+#define DDRSS1_PI_141_DATA 0x00000000
+#define DDRSS1_PI_142_DATA 0x00000000
+#define DDRSS1_PI_143_DATA 0x00000000
+#define DDRSS1_PI_144_DATA 0x01000000
+#define DDRSS1_PI_145_DATA 0x00010003
+#define DDRSS1_PI_146_DATA 0x02000101
+#define DDRSS1_PI_147_DATA 0x01030001
+#define DDRSS1_PI_148_DATA 0x00010400
+#define DDRSS1_PI_149_DATA 0x06000105
+#define DDRSS1_PI_150_DATA 0x01070001
+#define DDRSS1_PI_151_DATA 0x00000000
+#define DDRSS1_PI_152_DATA 0x00000000
+#define DDRSS1_PI_153_DATA 0x00000000
+#define DDRSS1_PI_154_DATA 0x00010001
+#define DDRSS1_PI_155_DATA 0x00000000
+#define DDRSS1_PI_156_DATA 0x00000000
+#define DDRSS1_PI_157_DATA 0x00000000
+#define DDRSS1_PI_158_DATA 0x00000000
+#define DDRSS1_PI_159_DATA 0x00000401
+#define DDRSS1_PI_160_DATA 0x00000000
+#define DDRSS1_PI_161_DATA 0x00010000
+#define DDRSS1_PI_162_DATA 0x00000000
+#define DDRSS1_PI_163_DATA 0x2B2B0200
+#define DDRSS1_PI_164_DATA 0x00000034
+#define DDRSS1_PI_165_DATA 0x00000064
+#define DDRSS1_PI_166_DATA 0x00020064
+#define DDRSS1_PI_167_DATA 0x02000200
+#define DDRSS1_PI_168_DATA 0x48120C04
+#define DDRSS1_PI_169_DATA 0x00154812
+#define DDRSS1_PI_170_DATA 0x000000CE
+#define DDRSS1_PI_171_DATA 0x0000032B
+#define DDRSS1_PI_172_DATA 0x00002073
+#define DDRSS1_PI_173_DATA 0x0000032B
+#define DDRSS1_PI_174_DATA 0x04002073
+#define DDRSS1_PI_175_DATA 0x01010404
+#define DDRSS1_PI_176_DATA 0x00001501
+#define DDRSS1_PI_177_DATA 0x00150015
+#define DDRSS1_PI_178_DATA 0x01000100
+#define DDRSS1_PI_179_DATA 0x00000100
+#define DDRSS1_PI_180_DATA 0x00000000
+#define DDRSS1_PI_181_DATA 0x01010101
+#define DDRSS1_PI_182_DATA 0x00000101
+#define DDRSS1_PI_183_DATA 0x00000000
+#define DDRSS1_PI_184_DATA 0x00000000
+#define DDRSS1_PI_185_DATA 0x15040000
+#define DDRSS1_PI_186_DATA 0x0E0E0215
+#define DDRSS1_PI_187_DATA 0x00040402
+#define DDRSS1_PI_188_DATA 0x000D0035
+#define DDRSS1_PI_189_DATA 0x00218049
+#define DDRSS1_PI_190_DATA 0x00218049
+#define DDRSS1_PI_191_DATA 0x01010101
+#define DDRSS1_PI_192_DATA 0x0004000E
+#define DDRSS1_PI_193_DATA 0x00040216
+#define DDRSS1_PI_194_DATA 0x01000216
+#define DDRSS1_PI_195_DATA 0x000F000F
+#define DDRSS1_PI_196_DATA 0x02170100
+#define DDRSS1_PI_197_DATA 0x01000217
+#define DDRSS1_PI_198_DATA 0x02170217
+#define DDRSS1_PI_199_DATA 0x32103200
+#define DDRSS1_PI_200_DATA 0x01013210
+#define DDRSS1_PI_201_DATA 0x0A070601
+#define DDRSS1_PI_202_DATA 0x1F130A0D
+#define DDRSS1_PI_203_DATA 0x1F130A14
+#define DDRSS1_PI_204_DATA 0x0000C014
+#define DDRSS1_PI_205_DATA 0x00C01000
+#define DDRSS1_PI_206_DATA 0x00C01000
+#define DDRSS1_PI_207_DATA 0x00021000
+#define DDRSS1_PI_208_DATA 0x0024000E
+#define DDRSS1_PI_209_DATA 0x00240216
+#define DDRSS1_PI_210_DATA 0x00110216
+#define DDRSS1_PI_211_DATA 0x32000056
+#define DDRSS1_PI_212_DATA 0x00000301
+#define DDRSS1_PI_213_DATA 0x005B0036
+#define DDRSS1_PI_214_DATA 0x03013212
+#define DDRSS1_PI_215_DATA 0x00003600
+#define DDRSS1_PI_216_DATA 0x3212005B
+#define DDRSS1_PI_217_DATA 0x09000301
+#define DDRSS1_PI_218_DATA 0x04010504
+#define DDRSS1_PI_219_DATA 0x040006C9
+#define DDRSS1_PI_220_DATA 0x0A032001
+#define DDRSS1_PI_221_DATA 0x2C31110A
+#define DDRSS1_PI_222_DATA 0x00002918
+#define DDRSS1_PI_223_DATA 0x6001071C
+#define DDRSS1_PI_224_DATA 0x1E202008
+#define DDRSS1_PI_225_DATA 0x2C311116
+#define DDRSS1_PI_226_DATA 0x00002918
+#define DDRSS1_PI_227_DATA 0x6001071C
+#define DDRSS1_PI_228_DATA 0x1E202008
+#define DDRSS1_PI_229_DATA 0x00019C16
+#define DDRSS1_PI_230_DATA 0x00001018
+#define DDRSS1_PI_231_DATA 0x000040E6
+#define DDRSS1_PI_232_DATA 0x000288FC
+#define DDRSS1_PI_233_DATA 0x000040E6
+#define DDRSS1_PI_234_DATA 0x000288FC
+#define DDRSS1_PI_235_DATA 0x033B0016
+#define DDRSS1_PI_236_DATA 0x0303033B
+#define DDRSS1_PI_237_DATA 0x002AF803
+#define DDRSS1_PI_238_DATA 0x0001ADAF
+#define DDRSS1_PI_239_DATA 0x00000005
+#define DDRSS1_PI_240_DATA 0x0000006E
+#define DDRSS1_PI_241_DATA 0x00000016
+#define DDRSS1_PI_242_DATA 0x000681C8
+#define DDRSS1_PI_243_DATA 0x0001ADAF
+#define DDRSS1_PI_244_DATA 0x00000005
+#define DDRSS1_PI_245_DATA 0x000010A9
+#define DDRSS1_PI_246_DATA 0x0000033B
+#define DDRSS1_PI_247_DATA 0x000681C8
+#define DDRSS1_PI_248_DATA 0x0001ADAF
+#define DDRSS1_PI_249_DATA 0x00000005
+#define DDRSS1_PI_250_DATA 0x000010A9
+#define DDRSS1_PI_251_DATA 0x0100033B
+#define DDRSS1_PI_252_DATA 0x00370040
+#define DDRSS1_PI_253_DATA 0x00010008
+#define DDRSS1_PI_254_DATA 0x08550040
+#define DDRSS1_PI_255_DATA 0x00010040
+#define DDRSS1_PI_256_DATA 0x08550040
+#define DDRSS1_PI_257_DATA 0x00000340
+#define DDRSS1_PI_258_DATA 0x006B006B
+#define DDRSS1_PI_259_DATA 0x08040404
+#define DDRSS1_PI_260_DATA 0x00000055
+#define DDRSS1_PI_261_DATA 0x55083C5A
+#define DDRSS1_PI_262_DATA 0x5A000000
+#define DDRSS1_PI_263_DATA 0x0055083C
+#define DDRSS1_PI_264_DATA 0x3C5A0000
+#define DDRSS1_PI_265_DATA 0x00005508
+#define DDRSS1_PI_266_DATA 0x0C3C5A00
+#define DDRSS1_PI_267_DATA 0x080F0E0D
+#define DDRSS1_PI_268_DATA 0x000B0A09
+#define DDRSS1_PI_269_DATA 0x00030201
+#define DDRSS1_PI_270_DATA 0x01000000
+#define DDRSS1_PI_271_DATA 0x04020201
+#define DDRSS1_PI_272_DATA 0x00080804
+#define DDRSS1_PI_273_DATA 0x00000000
+#define DDRSS1_PI_274_DATA 0x00000000
+#define DDRSS1_PI_275_DATA 0x00330084
+#define DDRSS1_PI_276_DATA 0x00160000
+#define DDRSS1_PI_277_DATA 0x56333FF4
+#define DDRSS1_PI_278_DATA 0x00160F27
+#define DDRSS1_PI_279_DATA 0x56333FF4
+#define DDRSS1_PI_280_DATA 0x00160F27
+#define DDRSS1_PI_281_DATA 0x00330084
+#define DDRSS1_PI_282_DATA 0x00160000
+#define DDRSS1_PI_283_DATA 0x56333FF4
+#define DDRSS1_PI_284_DATA 0x00160F27
+#define DDRSS1_PI_285_DATA 0x56333FF4
+#define DDRSS1_PI_286_DATA 0x00160F27
+#define DDRSS1_PI_287_DATA 0x00330084
+#define DDRSS1_PI_288_DATA 0x00160000
+#define DDRSS1_PI_289_DATA 0x56333FF4
+#define DDRSS1_PI_290_DATA 0x00160F27
+#define DDRSS1_PI_291_DATA 0x56333FF4
+#define DDRSS1_PI_292_DATA 0x00160F27
+#define DDRSS1_PI_293_DATA 0x00330084
+#define DDRSS1_PI_294_DATA 0x00160000
+#define DDRSS1_PI_295_DATA 0x56333FF4
+#define DDRSS1_PI_296_DATA 0x00160F27
+#define DDRSS1_PI_297_DATA 0x56333FF4
+#define DDRSS1_PI_298_DATA 0x00160F27
+#define DDRSS1_PI_299_DATA 0x00000000
+
+#define DDRSS1_PHY_00_DATA 0x000004F0
+#define DDRSS1_PHY_01_DATA 0x00000000
+#define DDRSS1_PHY_02_DATA 0x00030200
+#define DDRSS1_PHY_03_DATA 0x00000000
+#define DDRSS1_PHY_04_DATA 0x00000000
+#define DDRSS1_PHY_05_DATA 0x01030000
+#define DDRSS1_PHY_06_DATA 0x00010000
+#define DDRSS1_PHY_07_DATA 0x01030004
+#define DDRSS1_PHY_08_DATA 0x01000000
+#define DDRSS1_PHY_09_DATA 0x00000000
+#define DDRSS1_PHY_10_DATA 0x00000000
+#define DDRSS1_PHY_11_DATA 0x01000001
+#define DDRSS1_PHY_12_DATA 0x00000100
+#define DDRSS1_PHY_13_DATA 0x000800C0
+#define DDRSS1_PHY_14_DATA 0x060100CC
+#define DDRSS1_PHY_15_DATA 0x00030066
+#define DDRSS1_PHY_16_DATA 0x00000000
+#define DDRSS1_PHY_17_DATA 0x00000301
+#define DDRSS1_PHY_18_DATA 0x0000AAAA
+#define DDRSS1_PHY_19_DATA 0x00005555
+#define DDRSS1_PHY_20_DATA 0x0000B5B5
+#define DDRSS1_PHY_21_DATA 0x00004A4A
+#define DDRSS1_PHY_22_DATA 0x00005656
+#define DDRSS1_PHY_23_DATA 0x0000A9A9
+#define DDRSS1_PHY_24_DATA 0x0000A9A9
+#define DDRSS1_PHY_25_DATA 0x0000B5B5
+#define DDRSS1_PHY_26_DATA 0x00000000
+#define DDRSS1_PHY_27_DATA 0x00000000
+#define DDRSS1_PHY_28_DATA 0x2A000000
+#define DDRSS1_PHY_29_DATA 0x00000808
+#define DDRSS1_PHY_30_DATA 0x0F000000
+#define DDRSS1_PHY_31_DATA 0x00000F0F
+#define DDRSS1_PHY_32_DATA 0x10200000
+#define DDRSS1_PHY_33_DATA 0x0C002006
+#define DDRSS1_PHY_34_DATA 0x00000000
+#define DDRSS1_PHY_35_DATA 0x00000000
+#define DDRSS1_PHY_36_DATA 0x55555555
+#define DDRSS1_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_38_DATA 0x55555555
+#define DDRSS1_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_40_DATA 0x00005555
+#define DDRSS1_PHY_41_DATA 0x01000100
+#define DDRSS1_PHY_42_DATA 0x00800180
+#define DDRSS1_PHY_43_DATA 0x00000001
+#define DDRSS1_PHY_44_DATA 0x00000000
+#define DDRSS1_PHY_45_DATA 0x00000000
+#define DDRSS1_PHY_46_DATA 0x00000000
+#define DDRSS1_PHY_47_DATA 0x00000000
+#define DDRSS1_PHY_48_DATA 0x00000000
+#define DDRSS1_PHY_49_DATA 0x00000000
+#define DDRSS1_PHY_50_DATA 0x00000000
+#define DDRSS1_PHY_51_DATA 0x00000000
+#define DDRSS1_PHY_52_DATA 0x00000000
+#define DDRSS1_PHY_53_DATA 0x00000000
+#define DDRSS1_PHY_54_DATA 0x00000000
+#define DDRSS1_PHY_55_DATA 0x00000000
+#define DDRSS1_PHY_56_DATA 0x00000000
+#define DDRSS1_PHY_57_DATA 0x00000000
+#define DDRSS1_PHY_58_DATA 0x00000000
+#define DDRSS1_PHY_59_DATA 0x00000000
+#define DDRSS1_PHY_60_DATA 0x00000000
+#define DDRSS1_PHY_61_DATA 0x00000000
+#define DDRSS1_PHY_62_DATA 0x00000000
+#define DDRSS1_PHY_63_DATA 0x00000000
+#define DDRSS1_PHY_64_DATA 0x00000000
+#define DDRSS1_PHY_65_DATA 0x00000000
+#define DDRSS1_PHY_66_DATA 0x00000104
+#define DDRSS1_PHY_67_DATA 0x00000120
+#define DDRSS1_PHY_68_DATA 0x00000000
+#define DDRSS1_PHY_69_DATA 0x00000000
+#define DDRSS1_PHY_70_DATA 0x00000000
+#define DDRSS1_PHY_71_DATA 0x00000000
+#define DDRSS1_PHY_72_DATA 0x00000000
+#define DDRSS1_PHY_73_DATA 0x00000000
+#define DDRSS1_PHY_74_DATA 0x00000000
+#define DDRSS1_PHY_75_DATA 0x00000001
+#define DDRSS1_PHY_76_DATA 0x07FF0000
+#define DDRSS1_PHY_77_DATA 0x0080081F
+#define DDRSS1_PHY_78_DATA 0x00081020
+#define DDRSS1_PHY_79_DATA 0x04010000
+#define DDRSS1_PHY_80_DATA 0x00000000
+#define DDRSS1_PHY_81_DATA 0x00000000
+#define DDRSS1_PHY_82_DATA 0x00000000
+#define DDRSS1_PHY_83_DATA 0x00000100
+#define DDRSS1_PHY_84_DATA 0x01CC0C01
+#define DDRSS1_PHY_85_DATA 0x1003CC0C
+#define DDRSS1_PHY_86_DATA 0x20000140
+#define DDRSS1_PHY_87_DATA 0x07FF0200
+#define DDRSS1_PHY_88_DATA 0x0000DD01
+#define DDRSS1_PHY_89_DATA 0x10100303
+#define DDRSS1_PHY_90_DATA 0x10101010
+#define DDRSS1_PHY_91_DATA 0x10101010
+#define DDRSS1_PHY_92_DATA 0x00021010
+#define DDRSS1_PHY_93_DATA 0x00100010
+#define DDRSS1_PHY_94_DATA 0x00100010
+#define DDRSS1_PHY_95_DATA 0x00100010
+#define DDRSS1_PHY_96_DATA 0x00100010
+#define DDRSS1_PHY_97_DATA 0x00050010
+#define DDRSS1_PHY_98_DATA 0x51517041
+#define DDRSS1_PHY_99_DATA 0x31C06001
+#define DDRSS1_PHY_100_DATA 0x07AB0340
+#define DDRSS1_PHY_101_DATA 0x00C0C001
+#define DDRSS1_PHY_102_DATA 0x0E0D0001
+#define DDRSS1_PHY_103_DATA 0x10001000
+#define DDRSS1_PHY_104_DATA 0x0C083E42
+#define DDRSS1_PHY_105_DATA 0x0F0C3701
+#define DDRSS1_PHY_106_DATA 0x01000140
+#define DDRSS1_PHY_107_DATA 0x0C000420
+#define DDRSS1_PHY_108_DATA 0x00000198
+#define DDRSS1_PHY_109_DATA 0x0A0000D0
+#define DDRSS1_PHY_110_DATA 0x00030200
+#define DDRSS1_PHY_111_DATA 0x02800000
+#define DDRSS1_PHY_112_DATA 0x80800000
+#define DDRSS1_PHY_113_DATA 0x000E2010
+#define DDRSS1_PHY_114_DATA 0x76543210
+#define DDRSS1_PHY_115_DATA 0x00000008
+#define DDRSS1_PHY_116_DATA 0x02800280
+#define DDRSS1_PHY_117_DATA 0x02800280
+#define DDRSS1_PHY_118_DATA 0x02800280
+#define DDRSS1_PHY_119_DATA 0x02800280
+#define DDRSS1_PHY_120_DATA 0x00000280
+#define DDRSS1_PHY_121_DATA 0x0000A000
+#define DDRSS1_PHY_122_DATA 0x00A000A0
+#define DDRSS1_PHY_123_DATA 0x00A000A0
+#define DDRSS1_PHY_124_DATA 0x00A000A0
+#define DDRSS1_PHY_125_DATA 0x00A000A0
+#define DDRSS1_PHY_126_DATA 0x00A000A0
+#define DDRSS1_PHY_127_DATA 0x00A000A0
+#define DDRSS1_PHY_128_DATA 0x00A000A0
+#define DDRSS1_PHY_129_DATA 0x00A000A0
+#define DDRSS1_PHY_130_DATA 0x01C200A0
+#define DDRSS1_PHY_131_DATA 0x01A00005
+#define DDRSS1_PHY_132_DATA 0x00000000
+#define DDRSS1_PHY_133_DATA 0x00000000
+#define DDRSS1_PHY_134_DATA 0x00080200
+#define DDRSS1_PHY_135_DATA 0x00000000
+#define DDRSS1_PHY_136_DATA 0x20202000
+#define DDRSS1_PHY_137_DATA 0x20202020
+#define DDRSS1_PHY_138_DATA 0xF0F02020
+#define DDRSS1_PHY_139_DATA 0x00000000
+#define DDRSS1_PHY_140_DATA 0x00000000
+#define DDRSS1_PHY_141_DATA 0x00000000
+#define DDRSS1_PHY_142_DATA 0x00000000
+#define DDRSS1_PHY_143_DATA 0x00000000
+#define DDRSS1_PHY_144_DATA 0x00000000
+#define DDRSS1_PHY_145_DATA 0x00000000
+#define DDRSS1_PHY_146_DATA 0x00000000
+#define DDRSS1_PHY_147_DATA 0x00000000
+#define DDRSS1_PHY_148_DATA 0x00000000
+#define DDRSS1_PHY_149_DATA 0x00000000
+#define DDRSS1_PHY_150_DATA 0x00000000
+#define DDRSS1_PHY_151_DATA 0x00000000
+#define DDRSS1_PHY_152_DATA 0x00000000
+#define DDRSS1_PHY_153_DATA 0x00000000
+#define DDRSS1_PHY_154_DATA 0x00000000
+#define DDRSS1_PHY_155_DATA 0x00000000
+#define DDRSS1_PHY_156_DATA 0x00000000
+#define DDRSS1_PHY_157_DATA 0x00000000
+#define DDRSS1_PHY_158_DATA 0x00000000
+#define DDRSS1_PHY_159_DATA 0x00000000
+#define DDRSS1_PHY_160_DATA 0x00000000
+#define DDRSS1_PHY_161_DATA 0x00000000
+#define DDRSS1_PHY_162_DATA 0x00000000
+#define DDRSS1_PHY_163_DATA 0x00000000
+#define DDRSS1_PHY_164_DATA 0x00000000
+#define DDRSS1_PHY_165_DATA 0x00000000
+#define DDRSS1_PHY_166_DATA 0x00000000
+#define DDRSS1_PHY_167_DATA 0x00000000
+#define DDRSS1_PHY_168_DATA 0x00000000
+#define DDRSS1_PHY_169_DATA 0x00000000
+#define DDRSS1_PHY_170_DATA 0x00000000
+#define DDRSS1_PHY_171_DATA 0x00000000
+#define DDRSS1_PHY_172_DATA 0x00000000
+#define DDRSS1_PHY_173_DATA 0x00000000
+#define DDRSS1_PHY_174_DATA 0x00000000
+#define DDRSS1_PHY_175_DATA 0x00000000
+#define DDRSS1_PHY_176_DATA 0x00000000
+#define DDRSS1_PHY_177_DATA 0x00000000
+#define DDRSS1_PHY_178_DATA 0x00000000
+#define DDRSS1_PHY_179_DATA 0x00000000
+#define DDRSS1_PHY_180_DATA 0x00000000
+#define DDRSS1_PHY_181_DATA 0x00000000
+#define DDRSS1_PHY_182_DATA 0x00000000
+#define DDRSS1_PHY_183_DATA 0x00000000
+#define DDRSS1_PHY_184_DATA 0x00000000
+#define DDRSS1_PHY_185_DATA 0x00000000
+#define DDRSS1_PHY_186_DATA 0x00000000
+#define DDRSS1_PHY_187_DATA 0x00000000
+#define DDRSS1_PHY_188_DATA 0x00000000
+#define DDRSS1_PHY_189_DATA 0x00000000
+#define DDRSS1_PHY_190_DATA 0x00000000
+#define DDRSS1_PHY_191_DATA 0x00000000
+#define DDRSS1_PHY_192_DATA 0x00000000
+#define DDRSS1_PHY_193_DATA 0x00000000
+#define DDRSS1_PHY_194_DATA 0x00000000
+#define DDRSS1_PHY_195_DATA 0x00000000
+#define DDRSS1_PHY_196_DATA 0x00000000
+#define DDRSS1_PHY_197_DATA 0x00000000
+#define DDRSS1_PHY_198_DATA 0x00000000
+#define DDRSS1_PHY_199_DATA 0x00000000
+#define DDRSS1_PHY_200_DATA 0x00000000
+#define DDRSS1_PHY_201_DATA 0x00000000
+#define DDRSS1_PHY_202_DATA 0x00000000
+#define DDRSS1_PHY_203_DATA 0x00000000
+#define DDRSS1_PHY_204_DATA 0x00000000
+#define DDRSS1_PHY_205_DATA 0x00000000
+#define DDRSS1_PHY_206_DATA 0x00000000
+#define DDRSS1_PHY_207_DATA 0x00000000
+#define DDRSS1_PHY_208_DATA 0x00000000
+#define DDRSS1_PHY_209_DATA 0x00000000
+#define DDRSS1_PHY_210_DATA 0x00000000
+#define DDRSS1_PHY_211_DATA 0x00000000
+#define DDRSS1_PHY_212_DATA 0x00000000
+#define DDRSS1_PHY_213_DATA 0x00000000
+#define DDRSS1_PHY_214_DATA 0x00000000
+#define DDRSS1_PHY_215_DATA 0x00000000
+#define DDRSS1_PHY_216_DATA 0x00000000
+#define DDRSS1_PHY_217_DATA 0x00000000
+#define DDRSS1_PHY_218_DATA 0x00000000
+#define DDRSS1_PHY_219_DATA 0x00000000
+#define DDRSS1_PHY_220_DATA 0x00000000
+#define DDRSS1_PHY_221_DATA 0x00000000
+#define DDRSS1_PHY_222_DATA 0x00000000
+#define DDRSS1_PHY_223_DATA 0x00000000
+#define DDRSS1_PHY_224_DATA 0x00000000
+#define DDRSS1_PHY_225_DATA 0x00000000
+#define DDRSS1_PHY_226_DATA 0x00000000
+#define DDRSS1_PHY_227_DATA 0x00000000
+#define DDRSS1_PHY_228_DATA 0x00000000
+#define DDRSS1_PHY_229_DATA 0x00000000
+#define DDRSS1_PHY_230_DATA 0x00000000
+#define DDRSS1_PHY_231_DATA 0x00000000
+#define DDRSS1_PHY_232_DATA 0x00000000
+#define DDRSS1_PHY_233_DATA 0x00000000
+#define DDRSS1_PHY_234_DATA 0x00000000
+#define DDRSS1_PHY_235_DATA 0x00000000
+#define DDRSS1_PHY_236_DATA 0x00000000
+#define DDRSS1_PHY_237_DATA 0x00000000
+#define DDRSS1_PHY_238_DATA 0x00000000
+#define DDRSS1_PHY_239_DATA 0x00000000
+#define DDRSS1_PHY_240_DATA 0x00000000
+#define DDRSS1_PHY_241_DATA 0x00000000
+#define DDRSS1_PHY_242_DATA 0x00000000
+#define DDRSS1_PHY_243_DATA 0x00000000
+#define DDRSS1_PHY_244_DATA 0x00000000
+#define DDRSS1_PHY_245_DATA 0x00000000
+#define DDRSS1_PHY_246_DATA 0x00000000
+#define DDRSS1_PHY_247_DATA 0x00000000
+#define DDRSS1_PHY_248_DATA 0x00000000
+#define DDRSS1_PHY_249_DATA 0x00000000
+#define DDRSS1_PHY_250_DATA 0x00000000
+#define DDRSS1_PHY_251_DATA 0x00000000
+#define DDRSS1_PHY_252_DATA 0x00000000
+#define DDRSS1_PHY_253_DATA 0x00000000
+#define DDRSS1_PHY_254_DATA 0x00000000
+#define DDRSS1_PHY_255_DATA 0x00000000
+#define DDRSS1_PHY_256_DATA 0x000004F0
+#define DDRSS1_PHY_257_DATA 0x00000000
+#define DDRSS1_PHY_258_DATA 0x00030200
+#define DDRSS1_PHY_259_DATA 0x00000000
+#define DDRSS1_PHY_260_DATA 0x00000000
+#define DDRSS1_PHY_261_DATA 0x01030000
+#define DDRSS1_PHY_262_DATA 0x00010000
+#define DDRSS1_PHY_263_DATA 0x01030004
+#define DDRSS1_PHY_264_DATA 0x01000000
+#define DDRSS1_PHY_265_DATA 0x00000000
+#define DDRSS1_PHY_266_DATA 0x00000000
+#define DDRSS1_PHY_267_DATA 0x01000001
+#define DDRSS1_PHY_268_DATA 0x00000100
+#define DDRSS1_PHY_269_DATA 0x000800C0
+#define DDRSS1_PHY_270_DATA 0x060100CC
+#define DDRSS1_PHY_271_DATA 0x00030066
+#define DDRSS1_PHY_272_DATA 0x00000000
+#define DDRSS1_PHY_273_DATA 0x00000301
+#define DDRSS1_PHY_274_DATA 0x0000AAAA
+#define DDRSS1_PHY_275_DATA 0x00005555
+#define DDRSS1_PHY_276_DATA 0x0000B5B5
+#define DDRSS1_PHY_277_DATA 0x00004A4A
+#define DDRSS1_PHY_278_DATA 0x00005656
+#define DDRSS1_PHY_279_DATA 0x0000A9A9
+#define DDRSS1_PHY_280_DATA 0x0000A9A9
+#define DDRSS1_PHY_281_DATA 0x0000B5B5
+#define DDRSS1_PHY_282_DATA 0x00000000
+#define DDRSS1_PHY_283_DATA 0x00000000
+#define DDRSS1_PHY_284_DATA 0x2A000000
+#define DDRSS1_PHY_285_DATA 0x00000808
+#define DDRSS1_PHY_286_DATA 0x0F000000
+#define DDRSS1_PHY_287_DATA 0x00000F0F
+#define DDRSS1_PHY_288_DATA 0x10200000
+#define DDRSS1_PHY_289_DATA 0x0C002006
+#define DDRSS1_PHY_290_DATA 0x00000000
+#define DDRSS1_PHY_291_DATA 0x00000000
+#define DDRSS1_PHY_292_DATA 0x55555555
+#define DDRSS1_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_294_DATA 0x55555555
+#define DDRSS1_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_296_DATA 0x00005555
+#define DDRSS1_PHY_297_DATA 0x01000100
+#define DDRSS1_PHY_298_DATA 0x00800180
+#define DDRSS1_PHY_299_DATA 0x00000000
+#define DDRSS1_PHY_300_DATA 0x00000000
+#define DDRSS1_PHY_301_DATA 0x00000000
+#define DDRSS1_PHY_302_DATA 0x00000000
+#define DDRSS1_PHY_303_DATA 0x00000000
+#define DDRSS1_PHY_304_DATA 0x00000000
+#define DDRSS1_PHY_305_DATA 0x00000000
+#define DDRSS1_PHY_306_DATA 0x00000000
+#define DDRSS1_PHY_307_DATA 0x00000000
+#define DDRSS1_PHY_308_DATA 0x00000000
+#define DDRSS1_PHY_309_DATA 0x00000000
+#define DDRSS1_PHY_310_DATA 0x00000000
+#define DDRSS1_PHY_311_DATA 0x00000000
+#define DDRSS1_PHY_312_DATA 0x00000000
+#define DDRSS1_PHY_313_DATA 0x00000000
+#define DDRSS1_PHY_314_DATA 0x00000000
+#define DDRSS1_PHY_315_DATA 0x00000000
+#define DDRSS1_PHY_316_DATA 0x00000000
+#define DDRSS1_PHY_317_DATA 0x00000000
+#define DDRSS1_PHY_318_DATA 0x00000000
+#define DDRSS1_PHY_319_DATA 0x00000000
+#define DDRSS1_PHY_320_DATA 0x00000000
+#define DDRSS1_PHY_321_DATA 0x00000000
+#define DDRSS1_PHY_322_DATA 0x00000104
+#define DDRSS1_PHY_323_DATA 0x00000120
+#define DDRSS1_PHY_324_DATA 0x00000000
+#define DDRSS1_PHY_325_DATA 0x00000000
+#define DDRSS1_PHY_326_DATA 0x00000000
+#define DDRSS1_PHY_327_DATA 0x00000000
+#define DDRSS1_PHY_328_DATA 0x00000000
+#define DDRSS1_PHY_329_DATA 0x00000000
+#define DDRSS1_PHY_330_DATA 0x00000000
+#define DDRSS1_PHY_331_DATA 0x00000001
+#define DDRSS1_PHY_332_DATA 0x07FF0000
+#define DDRSS1_PHY_333_DATA 0x0080081F
+#define DDRSS1_PHY_334_DATA 0x00081020
+#define DDRSS1_PHY_335_DATA 0x04010000
+#define DDRSS1_PHY_336_DATA 0x00000000
+#define DDRSS1_PHY_337_DATA 0x00000000
+#define DDRSS1_PHY_338_DATA 0x00000000
+#define DDRSS1_PHY_339_DATA 0x00000100
+#define DDRSS1_PHY_340_DATA 0x01CC0C01
+#define DDRSS1_PHY_341_DATA 0x1003CC0C
+#define DDRSS1_PHY_342_DATA 0x20000140
+#define DDRSS1_PHY_343_DATA 0x07FF0200
+#define DDRSS1_PHY_344_DATA 0x0000DD01
+#define DDRSS1_PHY_345_DATA 0x10100303
+#define DDRSS1_PHY_346_DATA 0x10101010
+#define DDRSS1_PHY_347_DATA 0x10101010
+#define DDRSS1_PHY_348_DATA 0x00021010
+#define DDRSS1_PHY_349_DATA 0x00100010
+#define DDRSS1_PHY_350_DATA 0x00100010
+#define DDRSS1_PHY_351_DATA 0x00100010
+#define DDRSS1_PHY_352_DATA 0x00100010
+#define DDRSS1_PHY_353_DATA 0x00050010
+#define DDRSS1_PHY_354_DATA 0x51517041
+#define DDRSS1_PHY_355_DATA 0x31C06001
+#define DDRSS1_PHY_356_DATA 0x07AB0340
+#define DDRSS1_PHY_357_DATA 0x00C0C001
+#define DDRSS1_PHY_358_DATA 0x0E0D0001
+#define DDRSS1_PHY_359_DATA 0x10001000
+#define DDRSS1_PHY_360_DATA 0x0C083E42
+#define DDRSS1_PHY_361_DATA 0x0F0C3701
+#define DDRSS1_PHY_362_DATA 0x01000140
+#define DDRSS1_PHY_363_DATA 0x0C000420
+#define DDRSS1_PHY_364_DATA 0x00000198
+#define DDRSS1_PHY_365_DATA 0x0A0000D0
+#define DDRSS1_PHY_366_DATA 0x00030200
+#define DDRSS1_PHY_367_DATA 0x02800000
+#define DDRSS1_PHY_368_DATA 0x80800000
+#define DDRSS1_PHY_369_DATA 0x000E2010
+#define DDRSS1_PHY_370_DATA 0x76543210
+#define DDRSS1_PHY_371_DATA 0x00000008
+#define DDRSS1_PHY_372_DATA 0x02800280
+#define DDRSS1_PHY_373_DATA 0x02800280
+#define DDRSS1_PHY_374_DATA 0x02800280
+#define DDRSS1_PHY_375_DATA 0x02800280
+#define DDRSS1_PHY_376_DATA 0x00000280
+#define DDRSS1_PHY_377_DATA 0x0000A000
+#define DDRSS1_PHY_378_DATA 0x00A000A0
+#define DDRSS1_PHY_379_DATA 0x00A000A0
+#define DDRSS1_PHY_380_DATA 0x00A000A0
+#define DDRSS1_PHY_381_DATA 0x00A000A0
+#define DDRSS1_PHY_382_DATA 0x00A000A0
+#define DDRSS1_PHY_383_DATA 0x00A000A0
+#define DDRSS1_PHY_384_DATA 0x00A000A0
+#define DDRSS1_PHY_385_DATA 0x00A000A0
+#define DDRSS1_PHY_386_DATA 0x01C200A0
+#define DDRSS1_PHY_387_DATA 0x01A00005
+#define DDRSS1_PHY_388_DATA 0x00000000
+#define DDRSS1_PHY_389_DATA 0x00000000
+#define DDRSS1_PHY_390_DATA 0x00080200
+#define DDRSS1_PHY_391_DATA 0x00000000
+#define DDRSS1_PHY_392_DATA 0x20202000
+#define DDRSS1_PHY_393_DATA 0x20202020
+#define DDRSS1_PHY_394_DATA 0xF0F02020
+#define DDRSS1_PHY_395_DATA 0x00000000
+#define DDRSS1_PHY_396_DATA 0x00000000
+#define DDRSS1_PHY_397_DATA 0x00000000
+#define DDRSS1_PHY_398_DATA 0x00000000
+#define DDRSS1_PHY_399_DATA 0x00000000
+#define DDRSS1_PHY_400_DATA 0x00000000
+#define DDRSS1_PHY_401_DATA 0x00000000
+#define DDRSS1_PHY_402_DATA 0x00000000
+#define DDRSS1_PHY_403_DATA 0x00000000
+#define DDRSS1_PHY_404_DATA 0x00000000
+#define DDRSS1_PHY_405_DATA 0x00000000
+#define DDRSS1_PHY_406_DATA 0x00000000
+#define DDRSS1_PHY_407_DATA 0x00000000
+#define DDRSS1_PHY_408_DATA 0x00000000
+#define DDRSS1_PHY_409_DATA 0x00000000
+#define DDRSS1_PHY_410_DATA 0x00000000
+#define DDRSS1_PHY_411_DATA 0x00000000
+#define DDRSS1_PHY_412_DATA 0x00000000
+#define DDRSS1_PHY_413_DATA 0x00000000
+#define DDRSS1_PHY_414_DATA 0x00000000
+#define DDRSS1_PHY_415_DATA 0x00000000
+#define DDRSS1_PHY_416_DATA 0x00000000
+#define DDRSS1_PHY_417_DATA 0x00000000
+#define DDRSS1_PHY_418_DATA 0x00000000
+#define DDRSS1_PHY_419_DATA 0x00000000
+#define DDRSS1_PHY_420_DATA 0x00000000
+#define DDRSS1_PHY_421_DATA 0x00000000
+#define DDRSS1_PHY_422_DATA 0x00000000
+#define DDRSS1_PHY_423_DATA 0x00000000
+#define DDRSS1_PHY_424_DATA 0x00000000
+#define DDRSS1_PHY_425_DATA 0x00000000
+#define DDRSS1_PHY_426_DATA 0x00000000
+#define DDRSS1_PHY_427_DATA 0x00000000
+#define DDRSS1_PHY_428_DATA 0x00000000
+#define DDRSS1_PHY_429_DATA 0x00000000
+#define DDRSS1_PHY_430_DATA 0x00000000
+#define DDRSS1_PHY_431_DATA 0x00000000
+#define DDRSS1_PHY_432_DATA 0x00000000
+#define DDRSS1_PHY_433_DATA 0x00000000
+#define DDRSS1_PHY_434_DATA 0x00000000
+#define DDRSS1_PHY_435_DATA 0x00000000
+#define DDRSS1_PHY_436_DATA 0x00000000
+#define DDRSS1_PHY_437_DATA 0x00000000
+#define DDRSS1_PHY_438_DATA 0x00000000
+#define DDRSS1_PHY_439_DATA 0x00000000
+#define DDRSS1_PHY_440_DATA 0x00000000
+#define DDRSS1_PHY_441_DATA 0x00000000
+#define DDRSS1_PHY_442_DATA 0x00000000
+#define DDRSS1_PHY_443_DATA 0x00000000
+#define DDRSS1_PHY_444_DATA 0x00000000
+#define DDRSS1_PHY_445_DATA 0x00000000
+#define DDRSS1_PHY_446_DATA 0x00000000
+#define DDRSS1_PHY_447_DATA 0x00000000
+#define DDRSS1_PHY_448_DATA 0x00000000
+#define DDRSS1_PHY_449_DATA 0x00000000
+#define DDRSS1_PHY_450_DATA 0x00000000
+#define DDRSS1_PHY_451_DATA 0x00000000
+#define DDRSS1_PHY_452_DATA 0x00000000
+#define DDRSS1_PHY_453_DATA 0x00000000
+#define DDRSS1_PHY_454_DATA 0x00000000
+#define DDRSS1_PHY_455_DATA 0x00000000
+#define DDRSS1_PHY_456_DATA 0x00000000
+#define DDRSS1_PHY_457_DATA 0x00000000
+#define DDRSS1_PHY_458_DATA 0x00000000
+#define DDRSS1_PHY_459_DATA 0x00000000
+#define DDRSS1_PHY_460_DATA 0x00000000
+#define DDRSS1_PHY_461_DATA 0x00000000
+#define DDRSS1_PHY_462_DATA 0x00000000
+#define DDRSS1_PHY_463_DATA 0x00000000
+#define DDRSS1_PHY_464_DATA 0x00000000
+#define DDRSS1_PHY_465_DATA 0x00000000
+#define DDRSS1_PHY_466_DATA 0x00000000
+#define DDRSS1_PHY_467_DATA 0x00000000
+#define DDRSS1_PHY_468_DATA 0x00000000
+#define DDRSS1_PHY_469_DATA 0x00000000
+#define DDRSS1_PHY_470_DATA 0x00000000
+#define DDRSS1_PHY_471_DATA 0x00000000
+#define DDRSS1_PHY_472_DATA 0x00000000
+#define DDRSS1_PHY_473_DATA 0x00000000
+#define DDRSS1_PHY_474_DATA 0x00000000
+#define DDRSS1_PHY_475_DATA 0x00000000
+#define DDRSS1_PHY_476_DATA 0x00000000
+#define DDRSS1_PHY_477_DATA 0x00000000
+#define DDRSS1_PHY_478_DATA 0x00000000
+#define DDRSS1_PHY_479_DATA 0x00000000
+#define DDRSS1_PHY_480_DATA 0x00000000
+#define DDRSS1_PHY_481_DATA 0x00000000
+#define DDRSS1_PHY_482_DATA 0x00000000
+#define DDRSS1_PHY_483_DATA 0x00000000
+#define DDRSS1_PHY_484_DATA 0x00000000
+#define DDRSS1_PHY_485_DATA 0x00000000
+#define DDRSS1_PHY_486_DATA 0x00000000
+#define DDRSS1_PHY_487_DATA 0x00000000
+#define DDRSS1_PHY_488_DATA 0x00000000
+#define DDRSS1_PHY_489_DATA 0x00000000
+#define DDRSS1_PHY_490_DATA 0x00000000
+#define DDRSS1_PHY_491_DATA 0x00000000
+#define DDRSS1_PHY_492_DATA 0x00000000
+#define DDRSS1_PHY_493_DATA 0x00000000
+#define DDRSS1_PHY_494_DATA 0x00000000
+#define DDRSS1_PHY_495_DATA 0x00000000
+#define DDRSS1_PHY_496_DATA 0x00000000
+#define DDRSS1_PHY_497_DATA 0x00000000
+#define DDRSS1_PHY_498_DATA 0x00000000
+#define DDRSS1_PHY_499_DATA 0x00000000
+#define DDRSS1_PHY_500_DATA 0x00000000
+#define DDRSS1_PHY_501_DATA 0x00000000
+#define DDRSS1_PHY_502_DATA 0x00000000
+#define DDRSS1_PHY_503_DATA 0x00000000
+#define DDRSS1_PHY_504_DATA 0x00000000
+#define DDRSS1_PHY_505_DATA 0x00000000
+#define DDRSS1_PHY_506_DATA 0x00000000
+#define DDRSS1_PHY_507_DATA 0x00000000
+#define DDRSS1_PHY_508_DATA 0x00000000
+#define DDRSS1_PHY_509_DATA 0x00000000
+#define DDRSS1_PHY_510_DATA 0x00000000
+#define DDRSS1_PHY_511_DATA 0x00000000
+#define DDRSS1_PHY_512_DATA 0x000004F0
+#define DDRSS1_PHY_513_DATA 0x00000000
+#define DDRSS1_PHY_514_DATA 0x00030200
+#define DDRSS1_PHY_515_DATA 0x00000000
+#define DDRSS1_PHY_516_DATA 0x00000000
+#define DDRSS1_PHY_517_DATA 0x01030000
+#define DDRSS1_PHY_518_DATA 0x00010000
+#define DDRSS1_PHY_519_DATA 0x01030004
+#define DDRSS1_PHY_520_DATA 0x01000000
+#define DDRSS1_PHY_521_DATA 0x00000000
+#define DDRSS1_PHY_522_DATA 0x00000000
+#define DDRSS1_PHY_523_DATA 0x01000001
+#define DDRSS1_PHY_524_DATA 0x00000100
+#define DDRSS1_PHY_525_DATA 0x000800C0
+#define DDRSS1_PHY_526_DATA 0x060100CC
+#define DDRSS1_PHY_527_DATA 0x00030066
+#define DDRSS1_PHY_528_DATA 0x00000000
+#define DDRSS1_PHY_529_DATA 0x00000301
+#define DDRSS1_PHY_530_DATA 0x0000AAAA
+#define DDRSS1_PHY_531_DATA 0x00005555
+#define DDRSS1_PHY_532_DATA 0x0000B5B5
+#define DDRSS1_PHY_533_DATA 0x00004A4A
+#define DDRSS1_PHY_534_DATA 0x00005656
+#define DDRSS1_PHY_535_DATA 0x0000A9A9
+#define DDRSS1_PHY_536_DATA 0x0000A9A9
+#define DDRSS1_PHY_537_DATA 0x0000B5B5
+#define DDRSS1_PHY_538_DATA 0x00000000
+#define DDRSS1_PHY_539_DATA 0x00000000
+#define DDRSS1_PHY_540_DATA 0x2A000000
+#define DDRSS1_PHY_541_DATA 0x00000808
+#define DDRSS1_PHY_542_DATA 0x0F000000
+#define DDRSS1_PHY_543_DATA 0x00000F0F
+#define DDRSS1_PHY_544_DATA 0x10200000
+#define DDRSS1_PHY_545_DATA 0x0C002006
+#define DDRSS1_PHY_546_DATA 0x00000000
+#define DDRSS1_PHY_547_DATA 0x00000000
+#define DDRSS1_PHY_548_DATA 0x55555555
+#define DDRSS1_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_550_DATA 0x55555555
+#define DDRSS1_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_552_DATA 0x00005555
+#define DDRSS1_PHY_553_DATA 0x01000100
+#define DDRSS1_PHY_554_DATA 0x00800180
+#define DDRSS1_PHY_555_DATA 0x00000001
+#define DDRSS1_PHY_556_DATA 0x00000000
+#define DDRSS1_PHY_557_DATA 0x00000000
+#define DDRSS1_PHY_558_DATA 0x00000000
+#define DDRSS1_PHY_559_DATA 0x00000000
+#define DDRSS1_PHY_560_DATA 0x00000000
+#define DDRSS1_PHY_561_DATA 0x00000000
+#define DDRSS1_PHY_562_DATA 0x00000000
+#define DDRSS1_PHY_563_DATA 0x00000000
+#define DDRSS1_PHY_564_DATA 0x00000000
+#define DDRSS1_PHY_565_DATA 0x00000000
+#define DDRSS1_PHY_566_DATA 0x00000000
+#define DDRSS1_PHY_567_DATA 0x00000000
+#define DDRSS1_PHY_568_DATA 0x00000000
+#define DDRSS1_PHY_569_DATA 0x00000000
+#define DDRSS1_PHY_570_DATA 0x00000000
+#define DDRSS1_PHY_571_DATA 0x00000000
+#define DDRSS1_PHY_572_DATA 0x00000000
+#define DDRSS1_PHY_573_DATA 0x00000000
+#define DDRSS1_PHY_574_DATA 0x00000000
+#define DDRSS1_PHY_575_DATA 0x00000000
+#define DDRSS1_PHY_576_DATA 0x00000000
+#define DDRSS1_PHY_577_DATA 0x00000000
+#define DDRSS1_PHY_578_DATA 0x00000104
+#define DDRSS1_PHY_579_DATA 0x00000120
+#define DDRSS1_PHY_580_DATA 0x00000000
+#define DDRSS1_PHY_581_DATA 0x00000000
+#define DDRSS1_PHY_582_DATA 0x00000000
+#define DDRSS1_PHY_583_DATA 0x00000000
+#define DDRSS1_PHY_584_DATA 0x00000000
+#define DDRSS1_PHY_585_DATA 0x00000000
+#define DDRSS1_PHY_586_DATA 0x00000000
+#define DDRSS1_PHY_587_DATA 0x00000001
+#define DDRSS1_PHY_588_DATA 0x07FF0000
+#define DDRSS1_PHY_589_DATA 0x0080081F
+#define DDRSS1_PHY_590_DATA 0x00081020
+#define DDRSS1_PHY_591_DATA 0x04010000
+#define DDRSS1_PHY_592_DATA 0x00000000
+#define DDRSS1_PHY_593_DATA 0x00000000
+#define DDRSS1_PHY_594_DATA 0x00000000
+#define DDRSS1_PHY_595_DATA 0x00000100
+#define DDRSS1_PHY_596_DATA 0x01CC0C01
+#define DDRSS1_PHY_597_DATA 0x1003CC0C
+#define DDRSS1_PHY_598_DATA 0x20000140
+#define DDRSS1_PHY_599_DATA 0x07FF0200
+#define DDRSS1_PHY_600_DATA 0x0000DD01
+#define DDRSS1_PHY_601_DATA 0x10100303
+#define DDRSS1_PHY_602_DATA 0x10101010
+#define DDRSS1_PHY_603_DATA 0x10101010
+#define DDRSS1_PHY_604_DATA 0x00021010
+#define DDRSS1_PHY_605_DATA 0x00100010
+#define DDRSS1_PHY_606_DATA 0x00100010
+#define DDRSS1_PHY_607_DATA 0x00100010
+#define DDRSS1_PHY_608_DATA 0x00100010
+#define DDRSS1_PHY_609_DATA 0x00050010
+#define DDRSS1_PHY_610_DATA 0x51517041
+#define DDRSS1_PHY_611_DATA 0x31C06001
+#define DDRSS1_PHY_612_DATA 0x07AB0340
+#define DDRSS1_PHY_613_DATA 0x00C0C001
+#define DDRSS1_PHY_614_DATA 0x0E0D0001
+#define DDRSS1_PHY_615_DATA 0x10001000
+#define DDRSS1_PHY_616_DATA 0x0C083E42
+#define DDRSS1_PHY_617_DATA 0x0F0C3701
+#define DDRSS1_PHY_618_DATA 0x01000140
+#define DDRSS1_PHY_619_DATA 0x0C000420
+#define DDRSS1_PHY_620_DATA 0x00000198
+#define DDRSS1_PHY_621_DATA 0x0A0000D0
+#define DDRSS1_PHY_622_DATA 0x00030200
+#define DDRSS1_PHY_623_DATA 0x02800000
+#define DDRSS1_PHY_624_DATA 0x80800000
+#define DDRSS1_PHY_625_DATA 0x000E2010
+#define DDRSS1_PHY_626_DATA 0x76543210
+#define DDRSS1_PHY_627_DATA 0x00000008
+#define DDRSS1_PHY_628_DATA 0x02800280
+#define DDRSS1_PHY_629_DATA 0x02800280
+#define DDRSS1_PHY_630_DATA 0x02800280
+#define DDRSS1_PHY_631_DATA 0x02800280
+#define DDRSS1_PHY_632_DATA 0x00000280
+#define DDRSS1_PHY_633_DATA 0x0000A000
+#define DDRSS1_PHY_634_DATA 0x00A000A0
+#define DDRSS1_PHY_635_DATA 0x00A000A0
+#define DDRSS1_PHY_636_DATA 0x00A000A0
+#define DDRSS1_PHY_637_DATA 0x00A000A0
+#define DDRSS1_PHY_638_DATA 0x00A000A0
+#define DDRSS1_PHY_639_DATA 0x00A000A0
+#define DDRSS1_PHY_640_DATA 0x00A000A0
+#define DDRSS1_PHY_641_DATA 0x00A000A0
+#define DDRSS1_PHY_642_DATA 0x01C200A0
+#define DDRSS1_PHY_643_DATA 0x01A00005
+#define DDRSS1_PHY_644_DATA 0x00000000
+#define DDRSS1_PHY_645_DATA 0x00000000
+#define DDRSS1_PHY_646_DATA 0x00080200
+#define DDRSS1_PHY_647_DATA 0x00000000
+#define DDRSS1_PHY_648_DATA 0x20202000
+#define DDRSS1_PHY_649_DATA 0x20202020
+#define DDRSS1_PHY_650_DATA 0xF0F02020
+#define DDRSS1_PHY_651_DATA 0x00000000
+#define DDRSS1_PHY_652_DATA 0x00000000
+#define DDRSS1_PHY_653_DATA 0x00000000
+#define DDRSS1_PHY_654_DATA 0x00000000
+#define DDRSS1_PHY_655_DATA 0x00000000
+#define DDRSS1_PHY_656_DATA 0x00000000
+#define DDRSS1_PHY_657_DATA 0x00000000
+#define DDRSS1_PHY_658_DATA 0x00000000
+#define DDRSS1_PHY_659_DATA 0x00000000
+#define DDRSS1_PHY_660_DATA 0x00000000
+#define DDRSS1_PHY_661_DATA 0x00000000
+#define DDRSS1_PHY_662_DATA 0x00000000
+#define DDRSS1_PHY_663_DATA 0x00000000
+#define DDRSS1_PHY_664_DATA 0x00000000
+#define DDRSS1_PHY_665_DATA 0x00000000
+#define DDRSS1_PHY_666_DATA 0x00000000
+#define DDRSS1_PHY_667_DATA 0x00000000
+#define DDRSS1_PHY_668_DATA 0x00000000
+#define DDRSS1_PHY_669_DATA 0x00000000
+#define DDRSS1_PHY_670_DATA 0x00000000
+#define DDRSS1_PHY_671_DATA 0x00000000
+#define DDRSS1_PHY_672_DATA 0x00000000
+#define DDRSS1_PHY_673_DATA 0x00000000
+#define DDRSS1_PHY_674_DATA 0x00000000
+#define DDRSS1_PHY_675_DATA 0x00000000
+#define DDRSS1_PHY_676_DATA 0x00000000
+#define DDRSS1_PHY_677_DATA 0x00000000
+#define DDRSS1_PHY_678_DATA 0x00000000
+#define DDRSS1_PHY_679_DATA 0x00000000
+#define DDRSS1_PHY_680_DATA 0x00000000
+#define DDRSS1_PHY_681_DATA 0x00000000
+#define DDRSS1_PHY_682_DATA 0x00000000
+#define DDRSS1_PHY_683_DATA 0x00000000
+#define DDRSS1_PHY_684_DATA 0x00000000
+#define DDRSS1_PHY_685_DATA 0x00000000
+#define DDRSS1_PHY_686_DATA 0x00000000
+#define DDRSS1_PHY_687_DATA 0x00000000
+#define DDRSS1_PHY_688_DATA 0x00000000
+#define DDRSS1_PHY_689_DATA 0x00000000
+#define DDRSS1_PHY_690_DATA 0x00000000
+#define DDRSS1_PHY_691_DATA 0x00000000
+#define DDRSS1_PHY_692_DATA 0x00000000
+#define DDRSS1_PHY_693_DATA 0x00000000
+#define DDRSS1_PHY_694_DATA 0x00000000
+#define DDRSS1_PHY_695_DATA 0x00000000
+#define DDRSS1_PHY_696_DATA 0x00000000
+#define DDRSS1_PHY_697_DATA 0x00000000
+#define DDRSS1_PHY_698_DATA 0x00000000
+#define DDRSS1_PHY_699_DATA 0x00000000
+#define DDRSS1_PHY_700_DATA 0x00000000
+#define DDRSS1_PHY_701_DATA 0x00000000
+#define DDRSS1_PHY_702_DATA 0x00000000
+#define DDRSS1_PHY_703_DATA 0x00000000
+#define DDRSS1_PHY_704_DATA 0x00000000
+#define DDRSS1_PHY_705_DATA 0x00000000
+#define DDRSS1_PHY_706_DATA 0x00000000
+#define DDRSS1_PHY_707_DATA 0x00000000
+#define DDRSS1_PHY_708_DATA 0x00000000
+#define DDRSS1_PHY_709_DATA 0x00000000
+#define DDRSS1_PHY_710_DATA 0x00000000
+#define DDRSS1_PHY_711_DATA 0x00000000
+#define DDRSS1_PHY_712_DATA 0x00000000
+#define DDRSS1_PHY_713_DATA 0x00000000
+#define DDRSS1_PHY_714_DATA 0x00000000
+#define DDRSS1_PHY_715_DATA 0x00000000
+#define DDRSS1_PHY_716_DATA 0x00000000
+#define DDRSS1_PHY_717_DATA 0x00000000
+#define DDRSS1_PHY_718_DATA 0x00000000
+#define DDRSS1_PHY_719_DATA 0x00000000
+#define DDRSS1_PHY_720_DATA 0x00000000
+#define DDRSS1_PHY_721_DATA 0x00000000
+#define DDRSS1_PHY_722_DATA 0x00000000
+#define DDRSS1_PHY_723_DATA 0x00000000
+#define DDRSS1_PHY_724_DATA 0x00000000
+#define DDRSS1_PHY_725_DATA 0x00000000
+#define DDRSS1_PHY_726_DATA 0x00000000
+#define DDRSS1_PHY_727_DATA 0x00000000
+#define DDRSS1_PHY_728_DATA 0x00000000
+#define DDRSS1_PHY_729_DATA 0x00000000
+#define DDRSS1_PHY_730_DATA 0x00000000
+#define DDRSS1_PHY_731_DATA 0x00000000
+#define DDRSS1_PHY_732_DATA 0x00000000
+#define DDRSS1_PHY_733_DATA 0x00000000
+#define DDRSS1_PHY_734_DATA 0x00000000
+#define DDRSS1_PHY_735_DATA 0x00000000
+#define DDRSS1_PHY_736_DATA 0x00000000
+#define DDRSS1_PHY_737_DATA 0x00000000
+#define DDRSS1_PHY_738_DATA 0x00000000
+#define DDRSS1_PHY_739_DATA 0x00000000
+#define DDRSS1_PHY_740_DATA 0x00000000
+#define DDRSS1_PHY_741_DATA 0x00000000
+#define DDRSS1_PHY_742_DATA 0x00000000
+#define DDRSS1_PHY_743_DATA 0x00000000
+#define DDRSS1_PHY_744_DATA 0x00000000
+#define DDRSS1_PHY_745_DATA 0x00000000
+#define DDRSS1_PHY_746_DATA 0x00000000
+#define DDRSS1_PHY_747_DATA 0x00000000
+#define DDRSS1_PHY_748_DATA 0x00000000
+#define DDRSS1_PHY_749_DATA 0x00000000
+#define DDRSS1_PHY_750_DATA 0x00000000
+#define DDRSS1_PHY_751_DATA 0x00000000
+#define DDRSS1_PHY_752_DATA 0x00000000
+#define DDRSS1_PHY_753_DATA 0x00000000
+#define DDRSS1_PHY_754_DATA 0x00000000
+#define DDRSS1_PHY_755_DATA 0x00000000
+#define DDRSS1_PHY_756_DATA 0x00000000
+#define DDRSS1_PHY_757_DATA 0x00000000
+#define DDRSS1_PHY_758_DATA 0x00000000
+#define DDRSS1_PHY_759_DATA 0x00000000
+#define DDRSS1_PHY_760_DATA 0x00000000
+#define DDRSS1_PHY_761_DATA 0x00000000
+#define DDRSS1_PHY_762_DATA 0x00000000
+#define DDRSS1_PHY_763_DATA 0x00000000
+#define DDRSS1_PHY_764_DATA 0x00000000
+#define DDRSS1_PHY_765_DATA 0x00000000
+#define DDRSS1_PHY_766_DATA 0x00000000
+#define DDRSS1_PHY_767_DATA 0x00000000
+#define DDRSS1_PHY_768_DATA 0x000004F0
+#define DDRSS1_PHY_769_DATA 0x00000000
+#define DDRSS1_PHY_770_DATA 0x00030200
+#define DDRSS1_PHY_771_DATA 0x00000000
+#define DDRSS1_PHY_772_DATA 0x00000000
+#define DDRSS1_PHY_773_DATA 0x01030000
+#define DDRSS1_PHY_774_DATA 0x00010000
+#define DDRSS1_PHY_775_DATA 0x01030004
+#define DDRSS1_PHY_776_DATA 0x01000000
+#define DDRSS1_PHY_777_DATA 0x00000000
+#define DDRSS1_PHY_778_DATA 0x00000000
+#define DDRSS1_PHY_779_DATA 0x01000001
+#define DDRSS1_PHY_780_DATA 0x00000100
+#define DDRSS1_PHY_781_DATA 0x000800C0
+#define DDRSS1_PHY_782_DATA 0x060100CC
+#define DDRSS1_PHY_783_DATA 0x00030066
+#define DDRSS1_PHY_784_DATA 0x00000000
+#define DDRSS1_PHY_785_DATA 0x00000301
+#define DDRSS1_PHY_786_DATA 0x0000AAAA
+#define DDRSS1_PHY_787_DATA 0x00005555
+#define DDRSS1_PHY_788_DATA 0x0000B5B5
+#define DDRSS1_PHY_789_DATA 0x00004A4A
+#define DDRSS1_PHY_790_DATA 0x00005656
+#define DDRSS1_PHY_791_DATA 0x0000A9A9
+#define DDRSS1_PHY_792_DATA 0x0000A9A9
+#define DDRSS1_PHY_793_DATA 0x0000B5B5
+#define DDRSS1_PHY_794_DATA 0x00000000
+#define DDRSS1_PHY_795_DATA 0x00000000
+#define DDRSS1_PHY_796_DATA 0x2A000000
+#define DDRSS1_PHY_797_DATA 0x00000808
+#define DDRSS1_PHY_798_DATA 0x0F000000
+#define DDRSS1_PHY_799_DATA 0x00000F0F
+#define DDRSS1_PHY_800_DATA 0x10200000
+#define DDRSS1_PHY_801_DATA 0x0C002006
+#define DDRSS1_PHY_802_DATA 0x00000000
+#define DDRSS1_PHY_803_DATA 0x00000000
+#define DDRSS1_PHY_804_DATA 0x55555555
+#define DDRSS1_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_806_DATA 0x55555555
+#define DDRSS1_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_808_DATA 0x00005555
+#define DDRSS1_PHY_809_DATA 0x01000100
+#define DDRSS1_PHY_810_DATA 0x00800180
+#define DDRSS1_PHY_811_DATA 0x00000000
+#define DDRSS1_PHY_812_DATA 0x00000000
+#define DDRSS1_PHY_813_DATA 0x00000000
+#define DDRSS1_PHY_814_DATA 0x00000000
+#define DDRSS1_PHY_815_DATA 0x00000000
+#define DDRSS1_PHY_816_DATA 0x00000000
+#define DDRSS1_PHY_817_DATA 0x00000000
+#define DDRSS1_PHY_818_DATA 0x00000000
+#define DDRSS1_PHY_819_DATA 0x00000000
+#define DDRSS1_PHY_820_DATA 0x00000000
+#define DDRSS1_PHY_821_DATA 0x00000000
+#define DDRSS1_PHY_822_DATA 0x00000000
+#define DDRSS1_PHY_823_DATA 0x00000000
+#define DDRSS1_PHY_824_DATA 0x00000000
+#define DDRSS1_PHY_825_DATA 0x00000000
+#define DDRSS1_PHY_826_DATA 0x00000000
+#define DDRSS1_PHY_827_DATA 0x00000000
+#define DDRSS1_PHY_828_DATA 0x00000000
+#define DDRSS1_PHY_829_DATA 0x00000000
+#define DDRSS1_PHY_830_DATA 0x00000000
+#define DDRSS1_PHY_831_DATA 0x00000000
+#define DDRSS1_PHY_832_DATA 0x00000000
+#define DDRSS1_PHY_833_DATA 0x00000000
+#define DDRSS1_PHY_834_DATA 0x00000104
+#define DDRSS1_PHY_835_DATA 0x00000120
+#define DDRSS1_PHY_836_DATA 0x00000000
+#define DDRSS1_PHY_837_DATA 0x00000000
+#define DDRSS1_PHY_838_DATA 0x00000000
+#define DDRSS1_PHY_839_DATA 0x00000000
+#define DDRSS1_PHY_840_DATA 0x00000000
+#define DDRSS1_PHY_841_DATA 0x00000000
+#define DDRSS1_PHY_842_DATA 0x00000000
+#define DDRSS1_PHY_843_DATA 0x00000001
+#define DDRSS1_PHY_844_DATA 0x07FF0000
+#define DDRSS1_PHY_845_DATA 0x0080081F
+#define DDRSS1_PHY_846_DATA 0x00081020
+#define DDRSS1_PHY_847_DATA 0x04010000
+#define DDRSS1_PHY_848_DATA 0x00000000
+#define DDRSS1_PHY_849_DATA 0x00000000
+#define DDRSS1_PHY_850_DATA 0x00000000
+#define DDRSS1_PHY_851_DATA 0x00000100
+#define DDRSS1_PHY_852_DATA 0x01CC0C01
+#define DDRSS1_PHY_853_DATA 0x1003CC0C
+#define DDRSS1_PHY_854_DATA 0x20000140
+#define DDRSS1_PHY_855_DATA 0x07FF0200
+#define DDRSS1_PHY_856_DATA 0x0000DD01
+#define DDRSS1_PHY_857_DATA 0x10100303
+#define DDRSS1_PHY_858_DATA 0x10101010
+#define DDRSS1_PHY_859_DATA 0x10101010
+#define DDRSS1_PHY_860_DATA 0x00021010
+#define DDRSS1_PHY_861_DATA 0x00100010
+#define DDRSS1_PHY_862_DATA 0x00100010
+#define DDRSS1_PHY_863_DATA 0x00100010
+#define DDRSS1_PHY_864_DATA 0x00100010
+#define DDRSS1_PHY_865_DATA 0x00050010
+#define DDRSS1_PHY_866_DATA 0x51517041
+#define DDRSS1_PHY_867_DATA 0x31C06001
+#define DDRSS1_PHY_868_DATA 0x07AB0340
+#define DDRSS1_PHY_869_DATA 0x00C0C001
+#define DDRSS1_PHY_870_DATA 0x0E0D0001
+#define DDRSS1_PHY_871_DATA 0x10001000
+#define DDRSS1_PHY_872_DATA 0x0C083E42
+#define DDRSS1_PHY_873_DATA 0x0F0C3701
+#define DDRSS1_PHY_874_DATA 0x01000140
+#define DDRSS1_PHY_875_DATA 0x0C000420
+#define DDRSS1_PHY_876_DATA 0x00000198
+#define DDRSS1_PHY_877_DATA 0x0A0000D0
+#define DDRSS1_PHY_878_DATA 0x00030200
+#define DDRSS1_PHY_879_DATA 0x02800000
+#define DDRSS1_PHY_880_DATA 0x80800000
+#define DDRSS1_PHY_881_DATA 0x000E2010
+#define DDRSS1_PHY_882_DATA 0x76543210
+#define DDRSS1_PHY_883_DATA 0x00000008
+#define DDRSS1_PHY_884_DATA 0x02800280
+#define DDRSS1_PHY_885_DATA 0x02800280
+#define DDRSS1_PHY_886_DATA 0x02800280
+#define DDRSS1_PHY_887_DATA 0x02800280
+#define DDRSS1_PHY_888_DATA 0x00000280
+#define DDRSS1_PHY_889_DATA 0x0000A000
+#define DDRSS1_PHY_890_DATA 0x00A000A0
+#define DDRSS1_PHY_891_DATA 0x00A000A0
+#define DDRSS1_PHY_892_DATA 0x00A000A0
+#define DDRSS1_PHY_893_DATA 0x00A000A0
+#define DDRSS1_PHY_894_DATA 0x00A000A0
+#define DDRSS1_PHY_895_DATA 0x00A000A0
+#define DDRSS1_PHY_896_DATA 0x00A000A0
+#define DDRSS1_PHY_897_DATA 0x00A000A0
+#define DDRSS1_PHY_898_DATA 0x01C200A0
+#define DDRSS1_PHY_899_DATA 0x01A00005
+#define DDRSS1_PHY_900_DATA 0x00000000
+#define DDRSS1_PHY_901_DATA 0x00000000
+#define DDRSS1_PHY_902_DATA 0x00080200
+#define DDRSS1_PHY_903_DATA 0x00000000
+#define DDRSS1_PHY_904_DATA 0x20202000
+#define DDRSS1_PHY_905_DATA 0x20202020
+#define DDRSS1_PHY_906_DATA 0xF0F02020
+#define DDRSS1_PHY_907_DATA 0x00000000
+#define DDRSS1_PHY_908_DATA 0x00000000
+#define DDRSS1_PHY_909_DATA 0x00000000
+#define DDRSS1_PHY_910_DATA 0x00000000
+#define DDRSS1_PHY_911_DATA 0x00000000
+#define DDRSS1_PHY_912_DATA 0x00000000
+#define DDRSS1_PHY_913_DATA 0x00000000
+#define DDRSS1_PHY_914_DATA 0x00000000
+#define DDRSS1_PHY_915_DATA 0x00000000
+#define DDRSS1_PHY_916_DATA 0x00000000
+#define DDRSS1_PHY_917_DATA 0x00000000
+#define DDRSS1_PHY_918_DATA 0x00000000
+#define DDRSS1_PHY_919_DATA 0x00000000
+#define DDRSS1_PHY_920_DATA 0x00000000
+#define DDRSS1_PHY_921_DATA 0x00000000
+#define DDRSS1_PHY_922_DATA 0x00000000
+#define DDRSS1_PHY_923_DATA 0x00000000
+#define DDRSS1_PHY_924_DATA 0x00000000
+#define DDRSS1_PHY_925_DATA 0x00000000
+#define DDRSS1_PHY_926_DATA 0x00000000
+#define DDRSS1_PHY_927_DATA 0x00000000
+#define DDRSS1_PHY_928_DATA 0x00000000
+#define DDRSS1_PHY_929_DATA 0x00000000
+#define DDRSS1_PHY_930_DATA 0x00000000
+#define DDRSS1_PHY_931_DATA 0x00000000
+#define DDRSS1_PHY_932_DATA 0x00000000
+#define DDRSS1_PHY_933_DATA 0x00000000
+#define DDRSS1_PHY_934_DATA 0x00000000
+#define DDRSS1_PHY_935_DATA 0x00000000
+#define DDRSS1_PHY_936_DATA 0x00000000
+#define DDRSS1_PHY_937_DATA 0x00000000
+#define DDRSS1_PHY_938_DATA 0x00000000
+#define DDRSS1_PHY_939_DATA 0x00000000
+#define DDRSS1_PHY_940_DATA 0x00000000
+#define DDRSS1_PHY_941_DATA 0x00000000
+#define DDRSS1_PHY_942_DATA 0x00000000
+#define DDRSS1_PHY_943_DATA 0x00000000
+#define DDRSS1_PHY_944_DATA 0x00000000
+#define DDRSS1_PHY_945_DATA 0x00000000
+#define DDRSS1_PHY_946_DATA 0x00000000
+#define DDRSS1_PHY_947_DATA 0x00000000
+#define DDRSS1_PHY_948_DATA 0x00000000
+#define DDRSS1_PHY_949_DATA 0x00000000
+#define DDRSS1_PHY_950_DATA 0x00000000
+#define DDRSS1_PHY_951_DATA 0x00000000
+#define DDRSS1_PHY_952_DATA 0x00000000
+#define DDRSS1_PHY_953_DATA 0x00000000
+#define DDRSS1_PHY_954_DATA 0x00000000
+#define DDRSS1_PHY_955_DATA 0x00000000
+#define DDRSS1_PHY_956_DATA 0x00000000
+#define DDRSS1_PHY_957_DATA 0x00000000
+#define DDRSS1_PHY_958_DATA 0x00000000
+#define DDRSS1_PHY_959_DATA 0x00000000
+#define DDRSS1_PHY_960_DATA 0x00000000
+#define DDRSS1_PHY_961_DATA 0x00000000
+#define DDRSS1_PHY_962_DATA 0x00000000
+#define DDRSS1_PHY_963_DATA 0x00000000
+#define DDRSS1_PHY_964_DATA 0x00000000
+#define DDRSS1_PHY_965_DATA 0x00000000
+#define DDRSS1_PHY_966_DATA 0x00000000
+#define DDRSS1_PHY_967_DATA 0x00000000
+#define DDRSS1_PHY_968_DATA 0x00000000
+#define DDRSS1_PHY_969_DATA 0x00000000
+#define DDRSS1_PHY_970_DATA 0x00000000
+#define DDRSS1_PHY_971_DATA 0x00000000
+#define DDRSS1_PHY_972_DATA 0x00000000
+#define DDRSS1_PHY_973_DATA 0x00000000
+#define DDRSS1_PHY_974_DATA 0x00000000
+#define DDRSS1_PHY_975_DATA 0x00000000
+#define DDRSS1_PHY_976_DATA 0x00000000
+#define DDRSS1_PHY_977_DATA 0x00000000
+#define DDRSS1_PHY_978_DATA 0x00000000
+#define DDRSS1_PHY_979_DATA 0x00000000
+#define DDRSS1_PHY_980_DATA 0x00000000
+#define DDRSS1_PHY_981_DATA 0x00000000
+#define DDRSS1_PHY_982_DATA 0x00000000
+#define DDRSS1_PHY_983_DATA 0x00000000
+#define DDRSS1_PHY_984_DATA 0x00000000
+#define DDRSS1_PHY_985_DATA 0x00000000
+#define DDRSS1_PHY_986_DATA 0x00000000
+#define DDRSS1_PHY_987_DATA 0x00000000
+#define DDRSS1_PHY_988_DATA 0x00000000
+#define DDRSS1_PHY_989_DATA 0x00000000
+#define DDRSS1_PHY_990_DATA 0x00000000
+#define DDRSS1_PHY_991_DATA 0x00000000
+#define DDRSS1_PHY_992_DATA 0x00000000
+#define DDRSS1_PHY_993_DATA 0x00000000
+#define DDRSS1_PHY_994_DATA 0x00000000
+#define DDRSS1_PHY_995_DATA 0x00000000
+#define DDRSS1_PHY_996_DATA 0x00000000
+#define DDRSS1_PHY_997_DATA 0x00000000
+#define DDRSS1_PHY_998_DATA 0x00000000
+#define DDRSS1_PHY_999_DATA 0x00000000
+#define DDRSS1_PHY_1000_DATA 0x00000000
+#define DDRSS1_PHY_1001_DATA 0x00000000
+#define DDRSS1_PHY_1002_DATA 0x00000000
+#define DDRSS1_PHY_1003_DATA 0x00000000
+#define DDRSS1_PHY_1004_DATA 0x00000000
+#define DDRSS1_PHY_1005_DATA 0x00000000
+#define DDRSS1_PHY_1006_DATA 0x00000000
+#define DDRSS1_PHY_1007_DATA 0x00000000
+#define DDRSS1_PHY_1008_DATA 0x00000000
+#define DDRSS1_PHY_1009_DATA 0x00000000
+#define DDRSS1_PHY_1010_DATA 0x00000000
+#define DDRSS1_PHY_1011_DATA 0x00000000
+#define DDRSS1_PHY_1012_DATA 0x00000000
+#define DDRSS1_PHY_1013_DATA 0x00000000
+#define DDRSS1_PHY_1014_DATA 0x00000000
+#define DDRSS1_PHY_1015_DATA 0x00000000
+#define DDRSS1_PHY_1016_DATA 0x00000000
+#define DDRSS1_PHY_1017_DATA 0x00000000
+#define DDRSS1_PHY_1018_DATA 0x00000000
+#define DDRSS1_PHY_1019_DATA 0x00000000
+#define DDRSS1_PHY_1020_DATA 0x00000000
+#define DDRSS1_PHY_1021_DATA 0x00000000
+#define DDRSS1_PHY_1022_DATA 0x00000000
+#define DDRSS1_PHY_1023_DATA 0x00000000
+#define DDRSS1_PHY_1024_DATA 0x00000000
+#define DDRSS1_PHY_1025_DATA 0x00000000
+#define DDRSS1_PHY_1026_DATA 0x00000000
+#define DDRSS1_PHY_1027_DATA 0x00000000
+#define DDRSS1_PHY_1028_DATA 0x00000000
+#define DDRSS1_PHY_1029_DATA 0x00000100
+#define DDRSS1_PHY_1030_DATA 0x00000200
+#define DDRSS1_PHY_1031_DATA 0x00000000
+#define DDRSS1_PHY_1032_DATA 0x00000000
+#define DDRSS1_PHY_1033_DATA 0x00000000
+#define DDRSS1_PHY_1034_DATA 0x00000000
+#define DDRSS1_PHY_1035_DATA 0x00400000
+#define DDRSS1_PHY_1036_DATA 0x00000080
+#define DDRSS1_PHY_1037_DATA 0x00DCBA98
+#define DDRSS1_PHY_1038_DATA 0x03000000
+#define DDRSS1_PHY_1039_DATA 0x00200000
+#define DDRSS1_PHY_1040_DATA 0x00000000
+#define DDRSS1_PHY_1041_DATA 0x00000000
+#define DDRSS1_PHY_1042_DATA 0x00000000
+#define DDRSS1_PHY_1043_DATA 0x00000000
+#define DDRSS1_PHY_1044_DATA 0x00000000
+#define DDRSS1_PHY_1045_DATA 0x0000002A
+#define DDRSS1_PHY_1046_DATA 0x00000015
+#define DDRSS1_PHY_1047_DATA 0x00000015
+#define DDRSS1_PHY_1048_DATA 0x0000002A
+#define DDRSS1_PHY_1049_DATA 0x00000033
+#define DDRSS1_PHY_1050_DATA 0x0000000C
+#define DDRSS1_PHY_1051_DATA 0x0000000C
+#define DDRSS1_PHY_1052_DATA 0x00000033
+#define DDRSS1_PHY_1053_DATA 0x00543210
+#define DDRSS1_PHY_1054_DATA 0x003F0000
+#define DDRSS1_PHY_1055_DATA 0x000F013F
+#define DDRSS1_PHY_1056_DATA 0x20202003
+#define DDRSS1_PHY_1057_DATA 0x00202020
+#define DDRSS1_PHY_1058_DATA 0x20008008
+#define DDRSS1_PHY_1059_DATA 0x00000810
+#define DDRSS1_PHY_1060_DATA 0x00000F00
+#define DDRSS1_PHY_1061_DATA 0x00000000
+#define DDRSS1_PHY_1062_DATA 0x00000000
+#define DDRSS1_PHY_1063_DATA 0x00000000
+#define DDRSS1_PHY_1064_DATA 0x000305CC
+#define DDRSS1_PHY_1065_DATA 0x00030000
+#define DDRSS1_PHY_1066_DATA 0x00000300
+#define DDRSS1_PHY_1067_DATA 0x00000300
+#define DDRSS1_PHY_1068_DATA 0x00000300
+#define DDRSS1_PHY_1069_DATA 0x00000300
+#define DDRSS1_PHY_1070_DATA 0x00000300
+#define DDRSS1_PHY_1071_DATA 0x42080010
+#define DDRSS1_PHY_1072_DATA 0x0000803E
+#define DDRSS1_PHY_1073_DATA 0x00000001
+#define DDRSS1_PHY_1074_DATA 0x01000102
+#define DDRSS1_PHY_1075_DATA 0x00008000
+#define DDRSS1_PHY_1076_DATA 0x00000000
+#define DDRSS1_PHY_1077_DATA 0x00000000
+#define DDRSS1_PHY_1078_DATA 0x00000000
+#define DDRSS1_PHY_1079_DATA 0x00000000
+#define DDRSS1_PHY_1080_DATA 0x00000000
+#define DDRSS1_PHY_1081_DATA 0x00000000
+#define DDRSS1_PHY_1082_DATA 0x00000000
+#define DDRSS1_PHY_1083_DATA 0x00000000
+#define DDRSS1_PHY_1084_DATA 0x00000000
+#define DDRSS1_PHY_1085_DATA 0x00000000
+#define DDRSS1_PHY_1086_DATA 0x00000000
+#define DDRSS1_PHY_1087_DATA 0x00000000
+#define DDRSS1_PHY_1088_DATA 0x00000000
+#define DDRSS1_PHY_1089_DATA 0x00000000
+#define DDRSS1_PHY_1090_DATA 0x00000000
+#define DDRSS1_PHY_1091_DATA 0x00000000
+#define DDRSS1_PHY_1092_DATA 0x00000000
+#define DDRSS1_PHY_1093_DATA 0x00000000
+#define DDRSS1_PHY_1094_DATA 0x00000000
+#define DDRSS1_PHY_1095_DATA 0x00000000
+#define DDRSS1_PHY_1096_DATA 0x00000000
+#define DDRSS1_PHY_1097_DATA 0x00000000
+#define DDRSS1_PHY_1098_DATA 0x00000000
+#define DDRSS1_PHY_1099_DATA 0x00000000
+#define DDRSS1_PHY_1100_DATA 0x00000000
+#define DDRSS1_PHY_1101_DATA 0x00000000
+#define DDRSS1_PHY_1102_DATA 0x00000000
+#define DDRSS1_PHY_1103_DATA 0x00000000
+#define DDRSS1_PHY_1104_DATA 0x00000000
+#define DDRSS1_PHY_1105_DATA 0x00000000
+#define DDRSS1_PHY_1106_DATA 0x00000000
+#define DDRSS1_PHY_1107_DATA 0x00000000
+#define DDRSS1_PHY_1108_DATA 0x00000000
+#define DDRSS1_PHY_1109_DATA 0x00000000
+#define DDRSS1_PHY_1110_DATA 0x00000000
+#define DDRSS1_PHY_1111_DATA 0x00000000
+#define DDRSS1_PHY_1112_DATA 0x00000000
+#define DDRSS1_PHY_1113_DATA 0x00000000
+#define DDRSS1_PHY_1114_DATA 0x00000000
+#define DDRSS1_PHY_1115_DATA 0x00000000
+#define DDRSS1_PHY_1116_DATA 0x00000000
+#define DDRSS1_PHY_1117_DATA 0x00000000
+#define DDRSS1_PHY_1118_DATA 0x00000000
+#define DDRSS1_PHY_1119_DATA 0x00000000
+#define DDRSS1_PHY_1120_DATA 0x00000000
+#define DDRSS1_PHY_1121_DATA 0x00000000
+#define DDRSS1_PHY_1122_DATA 0x00000000
+#define DDRSS1_PHY_1123_DATA 0x00000000
+#define DDRSS1_PHY_1124_DATA 0x00000000
+#define DDRSS1_PHY_1125_DATA 0x00000000
+#define DDRSS1_PHY_1126_DATA 0x00000000
+#define DDRSS1_PHY_1127_DATA 0x00000000
+#define DDRSS1_PHY_1128_DATA 0x00000000
+#define DDRSS1_PHY_1129_DATA 0x00000000
+#define DDRSS1_PHY_1130_DATA 0x00000000
+#define DDRSS1_PHY_1131_DATA 0x00000000
+#define DDRSS1_PHY_1132_DATA 0x00000000
+#define DDRSS1_PHY_1133_DATA 0x00000000
+#define DDRSS1_PHY_1134_DATA 0x00000000
+#define DDRSS1_PHY_1135_DATA 0x00000000
+#define DDRSS1_PHY_1136_DATA 0x00000000
+#define DDRSS1_PHY_1137_DATA 0x00000000
+#define DDRSS1_PHY_1138_DATA 0x00000000
+#define DDRSS1_PHY_1139_DATA 0x00000000
+#define DDRSS1_PHY_1140_DATA 0x00000000
+#define DDRSS1_PHY_1141_DATA 0x00000000
+#define DDRSS1_PHY_1142_DATA 0x00000000
+#define DDRSS1_PHY_1143_DATA 0x00000000
+#define DDRSS1_PHY_1144_DATA 0x00000000
+#define DDRSS1_PHY_1145_DATA 0x00000000
+#define DDRSS1_PHY_1146_DATA 0x00000000
+#define DDRSS1_PHY_1147_DATA 0x00000000
+#define DDRSS1_PHY_1148_DATA 0x00000000
+#define DDRSS1_PHY_1149_DATA 0x00000000
+#define DDRSS1_PHY_1150_DATA 0x00000000
+#define DDRSS1_PHY_1151_DATA 0x00000000
+#define DDRSS1_PHY_1152_DATA 0x00000000
+#define DDRSS1_PHY_1153_DATA 0x00000000
+#define DDRSS1_PHY_1154_DATA 0x00000000
+#define DDRSS1_PHY_1155_DATA 0x00000000
+#define DDRSS1_PHY_1156_DATA 0x00000000
+#define DDRSS1_PHY_1157_DATA 0x00000000
+#define DDRSS1_PHY_1158_DATA 0x00000000
+#define DDRSS1_PHY_1159_DATA 0x00000000
+#define DDRSS1_PHY_1160_DATA 0x00000000
+#define DDRSS1_PHY_1161_DATA 0x00000000
+#define DDRSS1_PHY_1162_DATA 0x00000000
+#define DDRSS1_PHY_1163_DATA 0x00000000
+#define DDRSS1_PHY_1164_DATA 0x00000000
+#define DDRSS1_PHY_1165_DATA 0x00000000
+#define DDRSS1_PHY_1166_DATA 0x00000000
+#define DDRSS1_PHY_1167_DATA 0x00000000
+#define DDRSS1_PHY_1168_DATA 0x00000000
+#define DDRSS1_PHY_1169_DATA 0x00000000
+#define DDRSS1_PHY_1170_DATA 0x00000000
+#define DDRSS1_PHY_1171_DATA 0x00000000
+#define DDRSS1_PHY_1172_DATA 0x00000000
+#define DDRSS1_PHY_1173_DATA 0x00000000
+#define DDRSS1_PHY_1174_DATA 0x00000000
+#define DDRSS1_PHY_1175_DATA 0x00000000
+#define DDRSS1_PHY_1176_DATA 0x00000000
+#define DDRSS1_PHY_1177_DATA 0x00000000
+#define DDRSS1_PHY_1178_DATA 0x00000000
+#define DDRSS1_PHY_1179_DATA 0x00000000
+#define DDRSS1_PHY_1180_DATA 0x00000000
+#define DDRSS1_PHY_1181_DATA 0x00000000
+#define DDRSS1_PHY_1182_DATA 0x00000000
+#define DDRSS1_PHY_1183_DATA 0x00000000
+#define DDRSS1_PHY_1184_DATA 0x00000000
+#define DDRSS1_PHY_1185_DATA 0x00000000
+#define DDRSS1_PHY_1186_DATA 0x00000000
+#define DDRSS1_PHY_1187_DATA 0x00000000
+#define DDRSS1_PHY_1188_DATA 0x00000000
+#define DDRSS1_PHY_1189_DATA 0x00000000
+#define DDRSS1_PHY_1190_DATA 0x00000000
+#define DDRSS1_PHY_1191_DATA 0x00000000
+#define DDRSS1_PHY_1192_DATA 0x00000000
+#define DDRSS1_PHY_1193_DATA 0x00000000
+#define DDRSS1_PHY_1194_DATA 0x00000000
+#define DDRSS1_PHY_1195_DATA 0x00000000
+#define DDRSS1_PHY_1196_DATA 0x00000000
+#define DDRSS1_PHY_1197_DATA 0x00000000
+#define DDRSS1_PHY_1198_DATA 0x00000000
+#define DDRSS1_PHY_1199_DATA 0x00000000
+#define DDRSS1_PHY_1200_DATA 0x00000000
+#define DDRSS1_PHY_1201_DATA 0x00000000
+#define DDRSS1_PHY_1202_DATA 0x00000000
+#define DDRSS1_PHY_1203_DATA 0x00000000
+#define DDRSS1_PHY_1204_DATA 0x00000000
+#define DDRSS1_PHY_1205_DATA 0x00000000
+#define DDRSS1_PHY_1206_DATA 0x00000000
+#define DDRSS1_PHY_1207_DATA 0x00000000
+#define DDRSS1_PHY_1208_DATA 0x00000000
+#define DDRSS1_PHY_1209_DATA 0x00000000
+#define DDRSS1_PHY_1210_DATA 0x00000000
+#define DDRSS1_PHY_1211_DATA 0x00000000
+#define DDRSS1_PHY_1212_DATA 0x00000000
+#define DDRSS1_PHY_1213_DATA 0x00000000
+#define DDRSS1_PHY_1214_DATA 0x00000000
+#define DDRSS1_PHY_1215_DATA 0x00000000
+#define DDRSS1_PHY_1216_DATA 0x00000000
+#define DDRSS1_PHY_1217_DATA 0x00000000
+#define DDRSS1_PHY_1218_DATA 0x00000000
+#define DDRSS1_PHY_1219_DATA 0x00000000
+#define DDRSS1_PHY_1220_DATA 0x00000000
+#define DDRSS1_PHY_1221_DATA 0x00000000
+#define DDRSS1_PHY_1222_DATA 0x00000000
+#define DDRSS1_PHY_1223_DATA 0x00000000
+#define DDRSS1_PHY_1224_DATA 0x00000000
+#define DDRSS1_PHY_1225_DATA 0x00000000
+#define DDRSS1_PHY_1226_DATA 0x00000000
+#define DDRSS1_PHY_1227_DATA 0x00000000
+#define DDRSS1_PHY_1228_DATA 0x00000000
+#define DDRSS1_PHY_1229_DATA 0x00000000
+#define DDRSS1_PHY_1230_DATA 0x00000000
+#define DDRSS1_PHY_1231_DATA 0x00000000
+#define DDRSS1_PHY_1232_DATA 0x00000000
+#define DDRSS1_PHY_1233_DATA 0x00000000
+#define DDRSS1_PHY_1234_DATA 0x00000000
+#define DDRSS1_PHY_1235_DATA 0x00000000
+#define DDRSS1_PHY_1236_DATA 0x00000000
+#define DDRSS1_PHY_1237_DATA 0x00000000
+#define DDRSS1_PHY_1238_DATA 0x00000000
+#define DDRSS1_PHY_1239_DATA 0x00000000
+#define DDRSS1_PHY_1240_DATA 0x00000000
+#define DDRSS1_PHY_1241_DATA 0x00000000
+#define DDRSS1_PHY_1242_DATA 0x00000000
+#define DDRSS1_PHY_1243_DATA 0x00000000
+#define DDRSS1_PHY_1244_DATA 0x00000000
+#define DDRSS1_PHY_1245_DATA 0x00000000
+#define DDRSS1_PHY_1246_DATA 0x00000000
+#define DDRSS1_PHY_1247_DATA 0x00000000
+#define DDRSS1_PHY_1248_DATA 0x00000000
+#define DDRSS1_PHY_1249_DATA 0x00000000
+#define DDRSS1_PHY_1250_DATA 0x00000000
+#define DDRSS1_PHY_1251_DATA 0x00000000
+#define DDRSS1_PHY_1252_DATA 0x00000000
+#define DDRSS1_PHY_1253_DATA 0x00000000
+#define DDRSS1_PHY_1254_DATA 0x00000000
+#define DDRSS1_PHY_1255_DATA 0x00000000
+#define DDRSS1_PHY_1256_DATA 0x00000000
+#define DDRSS1_PHY_1257_DATA 0x00000000
+#define DDRSS1_PHY_1258_DATA 0x00000000
+#define DDRSS1_PHY_1259_DATA 0x00000000
+#define DDRSS1_PHY_1260_DATA 0x00000000
+#define DDRSS1_PHY_1261_DATA 0x00000000
+#define DDRSS1_PHY_1262_DATA 0x00000000
+#define DDRSS1_PHY_1263_DATA 0x00000000
+#define DDRSS1_PHY_1264_DATA 0x00000000
+#define DDRSS1_PHY_1265_DATA 0x00000000
+#define DDRSS1_PHY_1266_DATA 0x00000000
+#define DDRSS1_PHY_1267_DATA 0x00000000
+#define DDRSS1_PHY_1268_DATA 0x00000000
+#define DDRSS1_PHY_1269_DATA 0x00000000
+#define DDRSS1_PHY_1270_DATA 0x00000000
+#define DDRSS1_PHY_1271_DATA 0x00000000
+#define DDRSS1_PHY_1272_DATA 0x00000000
+#define DDRSS1_PHY_1273_DATA 0x00000000
+#define DDRSS1_PHY_1274_DATA 0x00000000
+#define DDRSS1_PHY_1275_DATA 0x00000000
+#define DDRSS1_PHY_1276_DATA 0x00000000
+#define DDRSS1_PHY_1277_DATA 0x00000000
+#define DDRSS1_PHY_1278_DATA 0x00000000
+#define DDRSS1_PHY_1279_DATA 0x00000000
+#define DDRSS1_PHY_1280_DATA 0x00000000
+#define DDRSS1_PHY_1281_DATA 0x00010100
+#define DDRSS1_PHY_1282_DATA 0x00000000
+#define DDRSS1_PHY_1283_DATA 0x00000000
+#define DDRSS1_PHY_1284_DATA 0x00050000
+#define DDRSS1_PHY_1285_DATA 0x04000000
+#define DDRSS1_PHY_1286_DATA 0x00000055
+#define DDRSS1_PHY_1287_DATA 0x00000000
+#define DDRSS1_PHY_1288_DATA 0x00000000
+#define DDRSS1_PHY_1289_DATA 0x00000000
+#define DDRSS1_PHY_1290_DATA 0x00000000
+#define DDRSS1_PHY_1291_DATA 0x00002001
+#define DDRSS1_PHY_1292_DATA 0x0000400F
+#define DDRSS1_PHY_1293_DATA 0x50020028
+#define DDRSS1_PHY_1294_DATA 0x01010000
+#define DDRSS1_PHY_1295_DATA 0x80080001
+#define DDRSS1_PHY_1296_DATA 0x10200000
+#define DDRSS1_PHY_1297_DATA 0x00000008
+#define DDRSS1_PHY_1298_DATA 0x00000000
+#define DDRSS1_PHY_1299_DATA 0x01090E00
+#define DDRSS1_PHY_1300_DATA 0x00040101
+#define DDRSS1_PHY_1301_DATA 0x0000010F
+#define DDRSS1_PHY_1302_DATA 0x00000000
+#define DDRSS1_PHY_1303_DATA 0x0000FFFF
+#define DDRSS1_PHY_1304_DATA 0x00000000
+#define DDRSS1_PHY_1305_DATA 0x01010000
+#define DDRSS1_PHY_1306_DATA 0x01080402
+#define DDRSS1_PHY_1307_DATA 0x01200F02
+#define DDRSS1_PHY_1308_DATA 0x00194280
+#define DDRSS1_PHY_1309_DATA 0x00000004
+#define DDRSS1_PHY_1310_DATA 0x00052000
+#define DDRSS1_PHY_1311_DATA 0x00000000
+#define DDRSS1_PHY_1312_DATA 0x00000000
+#define DDRSS1_PHY_1313_DATA 0x00000000
+#define DDRSS1_PHY_1314_DATA 0x00000000
+#define DDRSS1_PHY_1315_DATA 0x00000000
+#define DDRSS1_PHY_1316_DATA 0x00000000
+#define DDRSS1_PHY_1317_DATA 0x01000000
+#define DDRSS1_PHY_1318_DATA 0x00000705
+#define DDRSS1_PHY_1319_DATA 0x00000054
+#define DDRSS1_PHY_1320_DATA 0x00030820
+#define DDRSS1_PHY_1321_DATA 0x00010820
+#define DDRSS1_PHY_1322_DATA 0x00010820
+#define DDRSS1_PHY_1323_DATA 0x00010820
+#define DDRSS1_PHY_1324_DATA 0x00010820
+#define DDRSS1_PHY_1325_DATA 0x00010820
+#define DDRSS1_PHY_1326_DATA 0x00010820
+#define DDRSS1_PHY_1327_DATA 0x00010820
+#define DDRSS1_PHY_1328_DATA 0x00010820
+#define DDRSS1_PHY_1329_DATA 0x00000000
+#define DDRSS1_PHY_1330_DATA 0x00000074
+#define DDRSS1_PHY_1331_DATA 0x00000400
+#define DDRSS1_PHY_1332_DATA 0x00000108
+#define DDRSS1_PHY_1333_DATA 0x00000000
+#define DDRSS1_PHY_1334_DATA 0x00000000
+#define DDRSS1_PHY_1335_DATA 0x00000000
+#define DDRSS1_PHY_1336_DATA 0x00000000
+#define DDRSS1_PHY_1337_DATA 0x00000000
+#define DDRSS1_PHY_1338_DATA 0x03000000
+#define DDRSS1_PHY_1339_DATA 0x00000000
+#define DDRSS1_PHY_1340_DATA 0x00000000
+#define DDRSS1_PHY_1341_DATA 0x00000000
+#define DDRSS1_PHY_1342_DATA 0x04102006
+#define DDRSS1_PHY_1343_DATA 0x00041020
+#define DDRSS1_PHY_1344_DATA 0x01C98C98
+#define DDRSS1_PHY_1345_DATA 0x3F400000
+#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS1_PHY_1347_DATA 0x0000001F
+#define DDRSS1_PHY_1348_DATA 0x00000000
+#define DDRSS1_PHY_1349_DATA 0x00000000
+#define DDRSS1_PHY_1350_DATA 0x00000000
+#define DDRSS1_PHY_1351_DATA 0x00010000
+#define DDRSS1_PHY_1352_DATA 0x00000000
+#define DDRSS1_PHY_1353_DATA 0x00000000
+#define DDRSS1_PHY_1354_DATA 0x00000000
+#define DDRSS1_PHY_1355_DATA 0x00000000
+#define DDRSS1_PHY_1356_DATA 0x76543210
+#define DDRSS1_PHY_1357_DATA 0x00010198
+#define DDRSS1_PHY_1358_DATA 0x00000000
+#define DDRSS1_PHY_1359_DATA 0x00000000
+#define DDRSS1_PHY_1360_DATA 0x00000000
+#define DDRSS1_PHY_1361_DATA 0x00040700
+#define DDRSS1_PHY_1362_DATA 0x00000000
+#define DDRSS1_PHY_1363_DATA 0x00000000
+#define DDRSS1_PHY_1364_DATA 0x00000000
+#define DDRSS1_PHY_1365_DATA 0x00000000
+#define DDRSS1_PHY_1366_DATA 0x00000000
+#define DDRSS1_PHY_1367_DATA 0x00000002
+#define DDRSS1_PHY_1368_DATA 0x00000000
+#define DDRSS1_PHY_1369_DATA 0x00000000
+#define DDRSS1_PHY_1370_DATA 0x00000000
+#define DDRSS1_PHY_1371_DATA 0x00000000
+#define DDRSS1_PHY_1372_DATA 0x00000000
+#define DDRSS1_PHY_1373_DATA 0x00000000
+#define DDRSS1_PHY_1374_DATA 0x00080000
+#define DDRSS1_PHY_1375_DATA 0x000007FF
+#define DDRSS1_PHY_1376_DATA 0x00000000
+#define DDRSS1_PHY_1377_DATA 0x00000000
+#define DDRSS1_PHY_1378_DATA 0x00000000
+#define DDRSS1_PHY_1379_DATA 0x00000000
+#define DDRSS1_PHY_1380_DATA 0x00000000
+#define DDRSS1_PHY_1381_DATA 0x00000000
+#define DDRSS1_PHY_1382_DATA 0x000FFFFF
+#define DDRSS1_PHY_1383_DATA 0x000FFFFF
+#define DDRSS1_PHY_1384_DATA 0x0000FFFF
+#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS1_PHY_1386_DATA 0x030FFFFF
+#define DDRSS1_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS1_PHY_1388_DATA 0x0000FFFF
+#define DDRSS1_PHY_1389_DATA 0x00000000
+#define DDRSS1_PHY_1390_DATA 0x00000000
+#define DDRSS1_PHY_1391_DATA 0x00000000
+#define DDRSS1_PHY_1392_DATA 0x00000000
+#define DDRSS1_PHY_1393_DATA 0x0001F7C0
+#define DDRSS1_PHY_1394_DATA 0x00000003
+#define DDRSS1_PHY_1395_DATA 0x00000000
+#define DDRSS1_PHY_1396_DATA 0x00001142
+#define DDRSS1_PHY_1397_DATA 0x010207AB
+#define DDRSS1_PHY_1398_DATA 0x01000080
+#define DDRSS1_PHY_1399_DATA 0x03900390
+#define DDRSS1_PHY_1400_DATA 0x03900390
+#define DDRSS1_PHY_1401_DATA 0x00000390
+#define DDRSS1_PHY_1402_DATA 0x00000390
+#define DDRSS1_PHY_1403_DATA 0x00000390
+#define DDRSS1_PHY_1404_DATA 0x00000390
+#define DDRSS1_PHY_1405_DATA 0x00000005
+#define DDRSS1_PHY_1406_DATA 0x01813FCC
+#define DDRSS1_PHY_1407_DATA 0x000000CC
+#define DDRSS1_PHY_1408_DATA 0x0C000DFF
+#define DDRSS1_PHY_1409_DATA 0x30000DFF
+#define DDRSS1_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1411_DATA 0x000100F0
+#define DDRSS1_PHY_1412_DATA 0x780DFFCC
+#define DDRSS1_PHY_1413_DATA 0x00007E31
+#define DDRSS1_PHY_1414_DATA 0x000CBF11
+#define DDRSS1_PHY_1415_DATA 0x01990010
+#define DDRSS1_PHY_1416_DATA 0x000CBF11
+#define DDRSS1_PHY_1417_DATA 0x01990010
+#define DDRSS1_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1419_DATA 0x00EF00F0
+#define DDRSS1_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1421_DATA 0x01FF00F0
+#define DDRSS1_PHY_1422_DATA 0x20040006
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&main_navss {
+ ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
+ <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
+ <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+
+ msmc0: msmc {
+ compatible = "ti,j721s2-msmc";
+ intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>;
+ intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>;
+ ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>;
+ emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>;
+ emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ u-boot,dm-spl;
+
+ memorycontroller0: memorycontroller@2990000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x02990000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>;
+ reg-names = "cfg", "ctrl_mmr_lp4";
+ power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+ <&k3_pds 96 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
+ ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+ ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+ ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+ ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+ instance = <0>;
+
+ u-boot,dm-spl;
+
+ ti,ctl-data = <
+ DDRSS0_CTL_00_DATA
+ DDRSS0_CTL_01_DATA
+ DDRSS0_CTL_02_DATA
+ DDRSS0_CTL_03_DATA
+ DDRSS0_CTL_04_DATA
+ DDRSS0_CTL_05_DATA
+ DDRSS0_CTL_06_DATA
+ DDRSS0_CTL_07_DATA
+ DDRSS0_CTL_08_DATA
+ DDRSS0_CTL_09_DATA
+ DDRSS0_CTL_10_DATA
+ DDRSS0_CTL_11_DATA
+ DDRSS0_CTL_12_DATA
+ DDRSS0_CTL_13_DATA
+ DDRSS0_CTL_14_DATA
+ DDRSS0_CTL_15_DATA
+ DDRSS0_CTL_16_DATA
+ DDRSS0_CTL_17_DATA
+ DDRSS0_CTL_18_DATA
+ DDRSS0_CTL_19_DATA
+ DDRSS0_CTL_20_DATA
+ DDRSS0_CTL_21_DATA
+ DDRSS0_CTL_22_DATA
+ DDRSS0_CTL_23_DATA
+ DDRSS0_CTL_24_DATA
+ DDRSS0_CTL_25_DATA
+ DDRSS0_CTL_26_DATA
+ DDRSS0_CTL_27_DATA
+ DDRSS0_CTL_28_DATA
+ DDRSS0_CTL_29_DATA
+ DDRSS0_CTL_30_DATA
+ DDRSS0_CTL_31_DATA
+ DDRSS0_CTL_32_DATA
+ DDRSS0_CTL_33_DATA
+ DDRSS0_CTL_34_DATA
+ DDRSS0_CTL_35_DATA
+ DDRSS0_CTL_36_DATA
+ DDRSS0_CTL_37_DATA
+ DDRSS0_CTL_38_DATA
+ DDRSS0_CTL_39_DATA
+ DDRSS0_CTL_40_DATA
+ DDRSS0_CTL_41_DATA
+ DDRSS0_CTL_42_DATA
+ DDRSS0_CTL_43_DATA
+ DDRSS0_CTL_44_DATA
+ DDRSS0_CTL_45_DATA
+ DDRSS0_CTL_46_DATA
+ DDRSS0_CTL_47_DATA
+ DDRSS0_CTL_48_DATA
+ DDRSS0_CTL_49_DATA
+ DDRSS0_CTL_50_DATA
+ DDRSS0_CTL_51_DATA
+ DDRSS0_CTL_52_DATA
+ DDRSS0_CTL_53_DATA
+ DDRSS0_CTL_54_DATA
+ DDRSS0_CTL_55_DATA
+ DDRSS0_CTL_56_DATA
+ DDRSS0_CTL_57_DATA
+ DDRSS0_CTL_58_DATA
+ DDRSS0_CTL_59_DATA
+ DDRSS0_CTL_60_DATA
+ DDRSS0_CTL_61_DATA
+ DDRSS0_CTL_62_DATA
+ DDRSS0_CTL_63_DATA
+ DDRSS0_CTL_64_DATA
+ DDRSS0_CTL_65_DATA
+ DDRSS0_CTL_66_DATA
+ DDRSS0_CTL_67_DATA
+ DDRSS0_CTL_68_DATA
+ DDRSS0_CTL_69_DATA
+ DDRSS0_CTL_70_DATA
+ DDRSS0_CTL_71_DATA
+ DDRSS0_CTL_72_DATA
+ DDRSS0_CTL_73_DATA
+ DDRSS0_CTL_74_DATA
+ DDRSS0_CTL_75_DATA
+ DDRSS0_CTL_76_DATA
+ DDRSS0_CTL_77_DATA
+ DDRSS0_CTL_78_DATA
+ DDRSS0_CTL_79_DATA
+ DDRSS0_CTL_80_DATA
+ DDRSS0_CTL_81_DATA
+ DDRSS0_CTL_82_DATA
+ DDRSS0_CTL_83_DATA
+ DDRSS0_CTL_84_DATA
+ DDRSS0_CTL_85_DATA
+ DDRSS0_CTL_86_DATA
+ DDRSS0_CTL_87_DATA
+ DDRSS0_CTL_88_DATA
+ DDRSS0_CTL_89_DATA
+ DDRSS0_CTL_90_DATA
+ DDRSS0_CTL_91_DATA
+ DDRSS0_CTL_92_DATA
+ DDRSS0_CTL_93_DATA
+ DDRSS0_CTL_94_DATA
+ DDRSS0_CTL_95_DATA
+ DDRSS0_CTL_96_DATA
+ DDRSS0_CTL_97_DATA
+ DDRSS0_CTL_98_DATA
+ DDRSS0_CTL_99_DATA
+ DDRSS0_CTL_100_DATA
+ DDRSS0_CTL_101_DATA
+ DDRSS0_CTL_102_DATA
+ DDRSS0_CTL_103_DATA
+ DDRSS0_CTL_104_DATA
+ DDRSS0_CTL_105_DATA
+ DDRSS0_CTL_106_DATA
+ DDRSS0_CTL_107_DATA
+ DDRSS0_CTL_108_DATA
+ DDRSS0_CTL_109_DATA
+ DDRSS0_CTL_110_DATA
+ DDRSS0_CTL_111_DATA
+ DDRSS0_CTL_112_DATA
+ DDRSS0_CTL_113_DATA
+ DDRSS0_CTL_114_DATA
+ DDRSS0_CTL_115_DATA
+ DDRSS0_CTL_116_DATA
+ DDRSS0_CTL_117_DATA
+ DDRSS0_CTL_118_DATA
+ DDRSS0_CTL_119_DATA
+ DDRSS0_CTL_120_DATA
+ DDRSS0_CTL_121_DATA
+ DDRSS0_CTL_122_DATA
+ DDRSS0_CTL_123_DATA
+ DDRSS0_CTL_124_DATA
+ DDRSS0_CTL_125_DATA
+ DDRSS0_CTL_126_DATA
+ DDRSS0_CTL_127_DATA
+ DDRSS0_CTL_128_DATA
+ DDRSS0_CTL_129_DATA
+ DDRSS0_CTL_130_DATA
+ DDRSS0_CTL_131_DATA
+ DDRSS0_CTL_132_DATA
+ DDRSS0_CTL_133_DATA
+ DDRSS0_CTL_134_DATA
+ DDRSS0_CTL_135_DATA
+ DDRSS0_CTL_136_DATA
+ DDRSS0_CTL_137_DATA
+ DDRSS0_CTL_138_DATA
+ DDRSS0_CTL_139_DATA
+ DDRSS0_CTL_140_DATA
+ DDRSS0_CTL_141_DATA
+ DDRSS0_CTL_142_DATA
+ DDRSS0_CTL_143_DATA
+ DDRSS0_CTL_144_DATA
+ DDRSS0_CTL_145_DATA
+ DDRSS0_CTL_146_DATA
+ DDRSS0_CTL_147_DATA
+ DDRSS0_CTL_148_DATA
+ DDRSS0_CTL_149_DATA
+ DDRSS0_CTL_150_DATA
+ DDRSS0_CTL_151_DATA
+ DDRSS0_CTL_152_DATA
+ DDRSS0_CTL_153_DATA
+ DDRSS0_CTL_154_DATA
+ DDRSS0_CTL_155_DATA
+ DDRSS0_CTL_156_DATA
+ DDRSS0_CTL_157_DATA
+ DDRSS0_CTL_158_DATA
+ DDRSS0_CTL_159_DATA
+ DDRSS0_CTL_160_DATA
+ DDRSS0_CTL_161_DATA
+ DDRSS0_CTL_162_DATA
+ DDRSS0_CTL_163_DATA
+ DDRSS0_CTL_164_DATA
+ DDRSS0_CTL_165_DATA
+ DDRSS0_CTL_166_DATA
+ DDRSS0_CTL_167_DATA
+ DDRSS0_CTL_168_DATA
+ DDRSS0_CTL_169_DATA
+ DDRSS0_CTL_170_DATA
+ DDRSS0_CTL_171_DATA
+ DDRSS0_CTL_172_DATA
+ DDRSS0_CTL_173_DATA
+ DDRSS0_CTL_174_DATA
+ DDRSS0_CTL_175_DATA
+ DDRSS0_CTL_176_DATA
+ DDRSS0_CTL_177_DATA
+ DDRSS0_CTL_178_DATA
+ DDRSS0_CTL_179_DATA
+ DDRSS0_CTL_180_DATA
+ DDRSS0_CTL_181_DATA
+ DDRSS0_CTL_182_DATA
+ DDRSS0_CTL_183_DATA
+ DDRSS0_CTL_184_DATA
+ DDRSS0_CTL_185_DATA
+ DDRSS0_CTL_186_DATA
+ DDRSS0_CTL_187_DATA
+ DDRSS0_CTL_188_DATA
+ DDRSS0_CTL_189_DATA
+ DDRSS0_CTL_190_DATA
+ DDRSS0_CTL_191_DATA
+ DDRSS0_CTL_192_DATA
+ DDRSS0_CTL_193_DATA
+ DDRSS0_CTL_194_DATA
+ DDRSS0_CTL_195_DATA
+ DDRSS0_CTL_196_DATA
+ DDRSS0_CTL_197_DATA
+ DDRSS0_CTL_198_DATA
+ DDRSS0_CTL_199_DATA
+ DDRSS0_CTL_200_DATA
+ DDRSS0_CTL_201_DATA
+ DDRSS0_CTL_202_DATA
+ DDRSS0_CTL_203_DATA
+ DDRSS0_CTL_204_DATA
+ DDRSS0_CTL_205_DATA
+ DDRSS0_CTL_206_DATA
+ DDRSS0_CTL_207_DATA
+ DDRSS0_CTL_208_DATA
+ DDRSS0_CTL_209_DATA
+ DDRSS0_CTL_210_DATA
+ DDRSS0_CTL_211_DATA
+ DDRSS0_CTL_212_DATA
+ DDRSS0_CTL_213_DATA
+ DDRSS0_CTL_214_DATA
+ DDRSS0_CTL_215_DATA
+ DDRSS0_CTL_216_DATA
+ DDRSS0_CTL_217_DATA
+ DDRSS0_CTL_218_DATA
+ DDRSS0_CTL_219_DATA
+ DDRSS0_CTL_220_DATA
+ DDRSS0_CTL_221_DATA
+ DDRSS0_CTL_222_DATA
+ DDRSS0_CTL_223_DATA
+ DDRSS0_CTL_224_DATA
+ DDRSS0_CTL_225_DATA
+ DDRSS0_CTL_226_DATA
+ DDRSS0_CTL_227_DATA
+ DDRSS0_CTL_228_DATA
+ DDRSS0_CTL_229_DATA
+ DDRSS0_CTL_230_DATA
+ DDRSS0_CTL_231_DATA
+ DDRSS0_CTL_232_DATA
+ DDRSS0_CTL_233_DATA
+ DDRSS0_CTL_234_DATA
+ DDRSS0_CTL_235_DATA
+ DDRSS0_CTL_236_DATA
+ DDRSS0_CTL_237_DATA
+ DDRSS0_CTL_238_DATA
+ DDRSS0_CTL_239_DATA
+ DDRSS0_CTL_240_DATA
+ DDRSS0_CTL_241_DATA
+ DDRSS0_CTL_242_DATA
+ DDRSS0_CTL_243_DATA
+ DDRSS0_CTL_244_DATA
+ DDRSS0_CTL_245_DATA
+ DDRSS0_CTL_246_DATA
+ DDRSS0_CTL_247_DATA
+ DDRSS0_CTL_248_DATA
+ DDRSS0_CTL_249_DATA
+ DDRSS0_CTL_250_DATA
+ DDRSS0_CTL_251_DATA
+ DDRSS0_CTL_252_DATA
+ DDRSS0_CTL_253_DATA
+ DDRSS0_CTL_254_DATA
+ DDRSS0_CTL_255_DATA
+ DDRSS0_CTL_256_DATA
+ DDRSS0_CTL_257_DATA
+ DDRSS0_CTL_258_DATA
+ DDRSS0_CTL_259_DATA
+ DDRSS0_CTL_260_DATA
+ DDRSS0_CTL_261_DATA
+ DDRSS0_CTL_262_DATA
+ DDRSS0_CTL_263_DATA
+ DDRSS0_CTL_264_DATA
+ DDRSS0_CTL_265_DATA
+ DDRSS0_CTL_266_DATA
+ DDRSS0_CTL_267_DATA
+ DDRSS0_CTL_268_DATA
+ DDRSS0_CTL_269_DATA
+ DDRSS0_CTL_270_DATA
+ DDRSS0_CTL_271_DATA
+ DDRSS0_CTL_272_DATA
+ DDRSS0_CTL_273_DATA
+ DDRSS0_CTL_274_DATA
+ DDRSS0_CTL_275_DATA
+ DDRSS0_CTL_276_DATA
+ DDRSS0_CTL_277_DATA
+ DDRSS0_CTL_278_DATA
+ DDRSS0_CTL_279_DATA
+ DDRSS0_CTL_280_DATA
+ DDRSS0_CTL_281_DATA
+ DDRSS0_CTL_282_DATA
+ DDRSS0_CTL_283_DATA
+ DDRSS0_CTL_284_DATA
+ DDRSS0_CTL_285_DATA
+ DDRSS0_CTL_286_DATA
+ DDRSS0_CTL_287_DATA
+ DDRSS0_CTL_288_DATA
+ DDRSS0_CTL_289_DATA
+ DDRSS0_CTL_290_DATA
+ DDRSS0_CTL_291_DATA
+ DDRSS0_CTL_292_DATA
+ DDRSS0_CTL_293_DATA
+ DDRSS0_CTL_294_DATA
+ DDRSS0_CTL_295_DATA
+ DDRSS0_CTL_296_DATA
+ DDRSS0_CTL_297_DATA
+ DDRSS0_CTL_298_DATA
+ DDRSS0_CTL_299_DATA
+ DDRSS0_CTL_300_DATA
+ DDRSS0_CTL_301_DATA
+ DDRSS0_CTL_302_DATA
+ DDRSS0_CTL_303_DATA
+ DDRSS0_CTL_304_DATA
+ DDRSS0_CTL_305_DATA
+ DDRSS0_CTL_306_DATA
+ DDRSS0_CTL_307_DATA
+ DDRSS0_CTL_308_DATA
+ DDRSS0_CTL_309_DATA
+ DDRSS0_CTL_310_DATA
+ DDRSS0_CTL_311_DATA
+ DDRSS0_CTL_312_DATA
+ DDRSS0_CTL_313_DATA
+ DDRSS0_CTL_314_DATA
+ DDRSS0_CTL_315_DATA
+ DDRSS0_CTL_316_DATA
+ DDRSS0_CTL_317_DATA
+ DDRSS0_CTL_318_DATA
+ DDRSS0_CTL_319_DATA
+ DDRSS0_CTL_320_DATA
+ DDRSS0_CTL_321_DATA
+ DDRSS0_CTL_322_DATA
+ DDRSS0_CTL_323_DATA
+ DDRSS0_CTL_324_DATA
+ DDRSS0_CTL_325_DATA
+ DDRSS0_CTL_326_DATA
+ DDRSS0_CTL_327_DATA
+ DDRSS0_CTL_328_DATA
+ DDRSS0_CTL_329_DATA
+ DDRSS0_CTL_330_DATA
+ DDRSS0_CTL_331_DATA
+ DDRSS0_CTL_332_DATA
+ DDRSS0_CTL_333_DATA
+ DDRSS0_CTL_334_DATA
+ DDRSS0_CTL_335_DATA
+ DDRSS0_CTL_336_DATA
+ DDRSS0_CTL_337_DATA
+ DDRSS0_CTL_338_DATA
+ DDRSS0_CTL_339_DATA
+ DDRSS0_CTL_340_DATA
+ DDRSS0_CTL_341_DATA
+ DDRSS0_CTL_342_DATA
+ DDRSS0_CTL_343_DATA
+ DDRSS0_CTL_344_DATA
+ DDRSS0_CTL_345_DATA
+ DDRSS0_CTL_346_DATA
+ DDRSS0_CTL_347_DATA
+ DDRSS0_CTL_348_DATA
+ DDRSS0_CTL_349_DATA
+ DDRSS0_CTL_350_DATA
+ DDRSS0_CTL_351_DATA
+ DDRSS0_CTL_352_DATA
+ DDRSS0_CTL_353_DATA
+ DDRSS0_CTL_354_DATA
+ DDRSS0_CTL_355_DATA
+ DDRSS0_CTL_356_DATA
+ DDRSS0_CTL_357_DATA
+ DDRSS0_CTL_358_DATA
+ DDRSS0_CTL_359_DATA
+ DDRSS0_CTL_360_DATA
+ DDRSS0_CTL_361_DATA
+ DDRSS0_CTL_362_DATA
+ DDRSS0_CTL_363_DATA
+ DDRSS0_CTL_364_DATA
+ DDRSS0_CTL_365_DATA
+ DDRSS0_CTL_366_DATA
+ DDRSS0_CTL_367_DATA
+ DDRSS0_CTL_368_DATA
+ DDRSS0_CTL_369_DATA
+ DDRSS0_CTL_370_DATA
+ DDRSS0_CTL_371_DATA
+ DDRSS0_CTL_372_DATA
+ DDRSS0_CTL_373_DATA
+ DDRSS0_CTL_374_DATA
+ DDRSS0_CTL_375_DATA
+ DDRSS0_CTL_376_DATA
+ DDRSS0_CTL_377_DATA
+ DDRSS0_CTL_378_DATA
+ DDRSS0_CTL_379_DATA
+ DDRSS0_CTL_380_DATA
+ DDRSS0_CTL_381_DATA
+ DDRSS0_CTL_382_DATA
+ DDRSS0_CTL_383_DATA
+ DDRSS0_CTL_384_DATA
+ DDRSS0_CTL_385_DATA
+ DDRSS0_CTL_386_DATA
+ DDRSS0_CTL_387_DATA
+ DDRSS0_CTL_388_DATA
+ DDRSS0_CTL_389_DATA
+ DDRSS0_CTL_390_DATA
+ DDRSS0_CTL_391_DATA
+ DDRSS0_CTL_392_DATA
+ DDRSS0_CTL_393_DATA
+ DDRSS0_CTL_394_DATA
+ DDRSS0_CTL_395_DATA
+ DDRSS0_CTL_396_DATA
+ DDRSS0_CTL_397_DATA
+ DDRSS0_CTL_398_DATA
+ DDRSS0_CTL_399_DATA
+ DDRSS0_CTL_400_DATA
+ DDRSS0_CTL_401_DATA
+ DDRSS0_CTL_402_DATA
+ DDRSS0_CTL_403_DATA
+ DDRSS0_CTL_404_DATA
+ DDRSS0_CTL_405_DATA
+ DDRSS0_CTL_406_DATA
+ DDRSS0_CTL_407_DATA
+ DDRSS0_CTL_408_DATA
+ DDRSS0_CTL_409_DATA
+ DDRSS0_CTL_410_DATA
+ DDRSS0_CTL_411_DATA
+ DDRSS0_CTL_412_DATA
+ DDRSS0_CTL_413_DATA
+ DDRSS0_CTL_414_DATA
+ DDRSS0_CTL_415_DATA
+ DDRSS0_CTL_416_DATA
+ DDRSS0_CTL_417_DATA
+ DDRSS0_CTL_418_DATA
+ DDRSS0_CTL_419_DATA
+ DDRSS0_CTL_420_DATA
+ DDRSS0_CTL_421_DATA
+ DDRSS0_CTL_422_DATA
+ DDRSS0_CTL_423_DATA
+ DDRSS0_CTL_424_DATA
+ DDRSS0_CTL_425_DATA
+ DDRSS0_CTL_426_DATA
+ DDRSS0_CTL_427_DATA
+ DDRSS0_CTL_428_DATA
+ DDRSS0_CTL_429_DATA
+ DDRSS0_CTL_430_DATA
+ DDRSS0_CTL_431_DATA
+ DDRSS0_CTL_432_DATA
+ DDRSS0_CTL_433_DATA
+ DDRSS0_CTL_434_DATA
+ DDRSS0_CTL_435_DATA
+ DDRSS0_CTL_436_DATA
+ DDRSS0_CTL_437_DATA
+ DDRSS0_CTL_438_DATA
+ DDRSS0_CTL_439_DATA
+ DDRSS0_CTL_440_DATA
+ DDRSS0_CTL_441_DATA
+ DDRSS0_CTL_442_DATA
+ DDRSS0_CTL_443_DATA
+ DDRSS0_CTL_444_DATA
+ DDRSS0_CTL_445_DATA
+ DDRSS0_CTL_446_DATA
+ DDRSS0_CTL_447_DATA
+ DDRSS0_CTL_448_DATA
+ DDRSS0_CTL_449_DATA
+ DDRSS0_CTL_450_DATA
+ DDRSS0_CTL_451_DATA
+ DDRSS0_CTL_452_DATA
+ DDRSS0_CTL_453_DATA
+ DDRSS0_CTL_454_DATA
+ DDRSS0_CTL_455_DATA
+ DDRSS0_CTL_456_DATA
+ DDRSS0_CTL_457_DATA
+ DDRSS0_CTL_458_DATA
+ >;
+
+ ti,pi-data = <
+ DDRSS0_PI_00_DATA
+ DDRSS0_PI_01_DATA
+ DDRSS0_PI_02_DATA
+ DDRSS0_PI_03_DATA
+ DDRSS0_PI_04_DATA
+ DDRSS0_PI_05_DATA
+ DDRSS0_PI_06_DATA
+ DDRSS0_PI_07_DATA
+ DDRSS0_PI_08_DATA
+ DDRSS0_PI_09_DATA
+ DDRSS0_PI_10_DATA
+ DDRSS0_PI_11_DATA
+ DDRSS0_PI_12_DATA
+ DDRSS0_PI_13_DATA
+ DDRSS0_PI_14_DATA
+ DDRSS0_PI_15_DATA
+ DDRSS0_PI_16_DATA
+ DDRSS0_PI_17_DATA
+ DDRSS0_PI_18_DATA
+ DDRSS0_PI_19_DATA
+ DDRSS0_PI_20_DATA
+ DDRSS0_PI_21_DATA
+ DDRSS0_PI_22_DATA
+ DDRSS0_PI_23_DATA
+ DDRSS0_PI_24_DATA
+ DDRSS0_PI_25_DATA
+ DDRSS0_PI_26_DATA
+ DDRSS0_PI_27_DATA
+ DDRSS0_PI_28_DATA
+ DDRSS0_PI_29_DATA
+ DDRSS0_PI_30_DATA
+ DDRSS0_PI_31_DATA
+ DDRSS0_PI_32_DATA
+ DDRSS0_PI_33_DATA
+ DDRSS0_PI_34_DATA
+ DDRSS0_PI_35_DATA
+ DDRSS0_PI_36_DATA
+ DDRSS0_PI_37_DATA
+ DDRSS0_PI_38_DATA
+ DDRSS0_PI_39_DATA
+ DDRSS0_PI_40_DATA
+ DDRSS0_PI_41_DATA
+ DDRSS0_PI_42_DATA
+ DDRSS0_PI_43_DATA
+ DDRSS0_PI_44_DATA
+ DDRSS0_PI_45_DATA
+ DDRSS0_PI_46_DATA
+ DDRSS0_PI_47_DATA
+ DDRSS0_PI_48_DATA
+ DDRSS0_PI_49_DATA
+ DDRSS0_PI_50_DATA
+ DDRSS0_PI_51_DATA
+ DDRSS0_PI_52_DATA
+ DDRSS0_PI_53_DATA
+ DDRSS0_PI_54_DATA
+ DDRSS0_PI_55_DATA
+ DDRSS0_PI_56_DATA
+ DDRSS0_PI_57_DATA
+ DDRSS0_PI_58_DATA
+ DDRSS0_PI_59_DATA
+ DDRSS0_PI_60_DATA
+ DDRSS0_PI_61_DATA
+ DDRSS0_PI_62_DATA
+ DDRSS0_PI_63_DATA
+ DDRSS0_PI_64_DATA
+ DDRSS0_PI_65_DATA
+ DDRSS0_PI_66_DATA
+ DDRSS0_PI_67_DATA
+ DDRSS0_PI_68_DATA
+ DDRSS0_PI_69_DATA
+ DDRSS0_PI_70_DATA
+ DDRSS0_PI_71_DATA
+ DDRSS0_PI_72_DATA
+ DDRSS0_PI_73_DATA
+ DDRSS0_PI_74_DATA
+ DDRSS0_PI_75_DATA
+ DDRSS0_PI_76_DATA
+ DDRSS0_PI_77_DATA
+ DDRSS0_PI_78_DATA
+ DDRSS0_PI_79_DATA
+ DDRSS0_PI_80_DATA
+ DDRSS0_PI_81_DATA
+ DDRSS0_PI_82_DATA
+ DDRSS0_PI_83_DATA
+ DDRSS0_PI_84_DATA
+ DDRSS0_PI_85_DATA
+ DDRSS0_PI_86_DATA
+ DDRSS0_PI_87_DATA
+ DDRSS0_PI_88_DATA
+ DDRSS0_PI_89_DATA
+ DDRSS0_PI_90_DATA
+ DDRSS0_PI_91_DATA
+ DDRSS0_PI_92_DATA
+ DDRSS0_PI_93_DATA
+ DDRSS0_PI_94_DATA
+ DDRSS0_PI_95_DATA
+ DDRSS0_PI_96_DATA
+ DDRSS0_PI_97_DATA
+ DDRSS0_PI_98_DATA
+ DDRSS0_PI_99_DATA
+ DDRSS0_PI_100_DATA
+ DDRSS0_PI_101_DATA
+ DDRSS0_PI_102_DATA
+ DDRSS0_PI_103_DATA
+ DDRSS0_PI_104_DATA
+ DDRSS0_PI_105_DATA
+ DDRSS0_PI_106_DATA
+ DDRSS0_PI_107_DATA
+ DDRSS0_PI_108_DATA
+ DDRSS0_PI_109_DATA
+ DDRSS0_PI_110_DATA
+ DDRSS0_PI_111_DATA
+ DDRSS0_PI_112_DATA
+ DDRSS0_PI_113_DATA
+ DDRSS0_PI_114_DATA
+ DDRSS0_PI_115_DATA
+ DDRSS0_PI_116_DATA
+ DDRSS0_PI_117_DATA
+ DDRSS0_PI_118_DATA
+ DDRSS0_PI_119_DATA
+ DDRSS0_PI_120_DATA
+ DDRSS0_PI_121_DATA
+ DDRSS0_PI_122_DATA
+ DDRSS0_PI_123_DATA
+ DDRSS0_PI_124_DATA
+ DDRSS0_PI_125_DATA
+ DDRSS0_PI_126_DATA
+ DDRSS0_PI_127_DATA
+ DDRSS0_PI_128_DATA
+ DDRSS0_PI_129_DATA
+ DDRSS0_PI_130_DATA
+ DDRSS0_PI_131_DATA
+ DDRSS0_PI_132_DATA
+ DDRSS0_PI_133_DATA
+ DDRSS0_PI_134_DATA
+ DDRSS0_PI_135_DATA
+ DDRSS0_PI_136_DATA
+ DDRSS0_PI_137_DATA
+ DDRSS0_PI_138_DATA
+ DDRSS0_PI_139_DATA
+ DDRSS0_PI_140_DATA
+ DDRSS0_PI_141_DATA
+ DDRSS0_PI_142_DATA
+ DDRSS0_PI_143_DATA
+ DDRSS0_PI_144_DATA
+ DDRSS0_PI_145_DATA
+ DDRSS0_PI_146_DATA
+ DDRSS0_PI_147_DATA
+ DDRSS0_PI_148_DATA
+ DDRSS0_PI_149_DATA
+ DDRSS0_PI_150_DATA
+ DDRSS0_PI_151_DATA
+ DDRSS0_PI_152_DATA
+ DDRSS0_PI_153_DATA
+ DDRSS0_PI_154_DATA
+ DDRSS0_PI_155_DATA
+ DDRSS0_PI_156_DATA
+ DDRSS0_PI_157_DATA
+ DDRSS0_PI_158_DATA
+ DDRSS0_PI_159_DATA
+ DDRSS0_PI_160_DATA
+ DDRSS0_PI_161_DATA
+ DDRSS0_PI_162_DATA
+ DDRSS0_PI_163_DATA
+ DDRSS0_PI_164_DATA
+ DDRSS0_PI_165_DATA
+ DDRSS0_PI_166_DATA
+ DDRSS0_PI_167_DATA
+ DDRSS0_PI_168_DATA
+ DDRSS0_PI_169_DATA
+ DDRSS0_PI_170_DATA
+ DDRSS0_PI_171_DATA
+ DDRSS0_PI_172_DATA
+ DDRSS0_PI_173_DATA
+ DDRSS0_PI_174_DATA
+ DDRSS0_PI_175_DATA
+ DDRSS0_PI_176_DATA
+ DDRSS0_PI_177_DATA
+ DDRSS0_PI_178_DATA
+ DDRSS0_PI_179_DATA
+ DDRSS0_PI_180_DATA
+ DDRSS0_PI_181_DATA
+ DDRSS0_PI_182_DATA
+ DDRSS0_PI_183_DATA
+ DDRSS0_PI_184_DATA
+ DDRSS0_PI_185_DATA
+ DDRSS0_PI_186_DATA
+ DDRSS0_PI_187_DATA
+ DDRSS0_PI_188_DATA
+ DDRSS0_PI_189_DATA
+ DDRSS0_PI_190_DATA
+ DDRSS0_PI_191_DATA
+ DDRSS0_PI_192_DATA
+ DDRSS0_PI_193_DATA
+ DDRSS0_PI_194_DATA
+ DDRSS0_PI_195_DATA
+ DDRSS0_PI_196_DATA
+ DDRSS0_PI_197_DATA
+ DDRSS0_PI_198_DATA
+ DDRSS0_PI_199_DATA
+ DDRSS0_PI_200_DATA
+ DDRSS0_PI_201_DATA
+ DDRSS0_PI_202_DATA
+ DDRSS0_PI_203_DATA
+ DDRSS0_PI_204_DATA
+ DDRSS0_PI_205_DATA
+ DDRSS0_PI_206_DATA
+ DDRSS0_PI_207_DATA
+ DDRSS0_PI_208_DATA
+ DDRSS0_PI_209_DATA
+ DDRSS0_PI_210_DATA
+ DDRSS0_PI_211_DATA
+ DDRSS0_PI_212_DATA
+ DDRSS0_PI_213_DATA
+ DDRSS0_PI_214_DATA
+ DDRSS0_PI_215_DATA
+ DDRSS0_PI_216_DATA
+ DDRSS0_PI_217_DATA
+ DDRSS0_PI_218_DATA
+ DDRSS0_PI_219_DATA
+ DDRSS0_PI_220_DATA
+ DDRSS0_PI_221_DATA
+ DDRSS0_PI_222_DATA
+ DDRSS0_PI_223_DATA
+ DDRSS0_PI_224_DATA
+ DDRSS0_PI_225_DATA
+ DDRSS0_PI_226_DATA
+ DDRSS0_PI_227_DATA
+ DDRSS0_PI_228_DATA
+ DDRSS0_PI_229_DATA
+ DDRSS0_PI_230_DATA
+ DDRSS0_PI_231_DATA
+ DDRSS0_PI_232_DATA
+ DDRSS0_PI_233_DATA
+ DDRSS0_PI_234_DATA
+ DDRSS0_PI_235_DATA
+ DDRSS0_PI_236_DATA
+ DDRSS0_PI_237_DATA
+ DDRSS0_PI_238_DATA
+ DDRSS0_PI_239_DATA
+ DDRSS0_PI_240_DATA
+ DDRSS0_PI_241_DATA
+ DDRSS0_PI_242_DATA
+ DDRSS0_PI_243_DATA
+ DDRSS0_PI_244_DATA
+ DDRSS0_PI_245_DATA
+ DDRSS0_PI_246_DATA
+ DDRSS0_PI_247_DATA
+ DDRSS0_PI_248_DATA
+ DDRSS0_PI_249_DATA
+ DDRSS0_PI_250_DATA
+ DDRSS0_PI_251_DATA
+ DDRSS0_PI_252_DATA
+ DDRSS0_PI_253_DATA
+ DDRSS0_PI_254_DATA
+ DDRSS0_PI_255_DATA
+ DDRSS0_PI_256_DATA
+ DDRSS0_PI_257_DATA
+ DDRSS0_PI_258_DATA
+ DDRSS0_PI_259_DATA
+ DDRSS0_PI_260_DATA
+ DDRSS0_PI_261_DATA
+ DDRSS0_PI_262_DATA
+ DDRSS0_PI_263_DATA
+ DDRSS0_PI_264_DATA
+ DDRSS0_PI_265_DATA
+ DDRSS0_PI_266_DATA
+ DDRSS0_PI_267_DATA
+ DDRSS0_PI_268_DATA
+ DDRSS0_PI_269_DATA
+ DDRSS0_PI_270_DATA
+ DDRSS0_PI_271_DATA
+ DDRSS0_PI_272_DATA
+ DDRSS0_PI_273_DATA
+ DDRSS0_PI_274_DATA
+ DDRSS0_PI_275_DATA
+ DDRSS0_PI_276_DATA
+ DDRSS0_PI_277_DATA
+ DDRSS0_PI_278_DATA
+ DDRSS0_PI_279_DATA
+ DDRSS0_PI_280_DATA
+ DDRSS0_PI_281_DATA
+ DDRSS0_PI_282_DATA
+ DDRSS0_PI_283_DATA
+ DDRSS0_PI_284_DATA
+ DDRSS0_PI_285_DATA
+ DDRSS0_PI_286_DATA
+ DDRSS0_PI_287_DATA
+ DDRSS0_PI_288_DATA
+ DDRSS0_PI_289_DATA
+ DDRSS0_PI_290_DATA
+ DDRSS0_PI_291_DATA
+ DDRSS0_PI_292_DATA
+ DDRSS0_PI_293_DATA
+ DDRSS0_PI_294_DATA
+ DDRSS0_PI_295_DATA
+ DDRSS0_PI_296_DATA
+ DDRSS0_PI_297_DATA
+ DDRSS0_PI_298_DATA
+ DDRSS0_PI_299_DATA
+ >;
+
+ ti,phy-data = <
+ DDRSS0_PHY_00_DATA
+ DDRSS0_PHY_01_DATA
+ DDRSS0_PHY_02_DATA
+ DDRSS0_PHY_03_DATA
+ DDRSS0_PHY_04_DATA
+ DDRSS0_PHY_05_DATA
+ DDRSS0_PHY_06_DATA
+ DDRSS0_PHY_07_DATA
+ DDRSS0_PHY_08_DATA
+ DDRSS0_PHY_09_DATA
+ DDRSS0_PHY_10_DATA
+ DDRSS0_PHY_11_DATA
+ DDRSS0_PHY_12_DATA
+ DDRSS0_PHY_13_DATA
+ DDRSS0_PHY_14_DATA
+ DDRSS0_PHY_15_DATA
+ DDRSS0_PHY_16_DATA
+ DDRSS0_PHY_17_DATA
+ DDRSS0_PHY_18_DATA
+ DDRSS0_PHY_19_DATA
+ DDRSS0_PHY_20_DATA
+ DDRSS0_PHY_21_DATA
+ DDRSS0_PHY_22_DATA
+ DDRSS0_PHY_23_DATA
+ DDRSS0_PHY_24_DATA
+ DDRSS0_PHY_25_DATA
+ DDRSS0_PHY_26_DATA
+ DDRSS0_PHY_27_DATA
+ DDRSS0_PHY_28_DATA
+ DDRSS0_PHY_29_DATA
+ DDRSS0_PHY_30_DATA
+ DDRSS0_PHY_31_DATA
+ DDRSS0_PHY_32_DATA
+ DDRSS0_PHY_33_DATA
+ DDRSS0_PHY_34_DATA
+ DDRSS0_PHY_35_DATA
+ DDRSS0_PHY_36_DATA
+ DDRSS0_PHY_37_DATA
+ DDRSS0_PHY_38_DATA
+ DDRSS0_PHY_39_DATA
+ DDRSS0_PHY_40_DATA
+ DDRSS0_PHY_41_DATA
+ DDRSS0_PHY_42_DATA
+ DDRSS0_PHY_43_DATA
+ DDRSS0_PHY_44_DATA
+ DDRSS0_PHY_45_DATA
+ DDRSS0_PHY_46_DATA
+ DDRSS0_PHY_47_DATA
+ DDRSS0_PHY_48_DATA
+ DDRSS0_PHY_49_DATA
+ DDRSS0_PHY_50_DATA
+ DDRSS0_PHY_51_DATA
+ DDRSS0_PHY_52_DATA
+ DDRSS0_PHY_53_DATA
+ DDRSS0_PHY_54_DATA
+ DDRSS0_PHY_55_DATA
+ DDRSS0_PHY_56_DATA
+ DDRSS0_PHY_57_DATA
+ DDRSS0_PHY_58_DATA
+ DDRSS0_PHY_59_DATA
+ DDRSS0_PHY_60_DATA
+ DDRSS0_PHY_61_DATA
+ DDRSS0_PHY_62_DATA
+ DDRSS0_PHY_63_DATA
+ DDRSS0_PHY_64_DATA
+ DDRSS0_PHY_65_DATA
+ DDRSS0_PHY_66_DATA
+ DDRSS0_PHY_67_DATA
+ DDRSS0_PHY_68_DATA
+ DDRSS0_PHY_69_DATA
+ DDRSS0_PHY_70_DATA
+ DDRSS0_PHY_71_DATA
+ DDRSS0_PHY_72_DATA
+ DDRSS0_PHY_73_DATA
+ DDRSS0_PHY_74_DATA
+ DDRSS0_PHY_75_DATA
+ DDRSS0_PHY_76_DATA
+ DDRSS0_PHY_77_DATA
+ DDRSS0_PHY_78_DATA
+ DDRSS0_PHY_79_DATA
+ DDRSS0_PHY_80_DATA
+ DDRSS0_PHY_81_DATA
+ DDRSS0_PHY_82_DATA
+ DDRSS0_PHY_83_DATA
+ DDRSS0_PHY_84_DATA
+ DDRSS0_PHY_85_DATA
+ DDRSS0_PHY_86_DATA
+ DDRSS0_PHY_87_DATA
+ DDRSS0_PHY_88_DATA
+ DDRSS0_PHY_89_DATA
+ DDRSS0_PHY_90_DATA
+ DDRSS0_PHY_91_DATA
+ DDRSS0_PHY_92_DATA
+ DDRSS0_PHY_93_DATA
+ DDRSS0_PHY_94_DATA
+ DDRSS0_PHY_95_DATA
+ DDRSS0_PHY_96_DATA
+ DDRSS0_PHY_97_DATA
+ DDRSS0_PHY_98_DATA
+ DDRSS0_PHY_99_DATA
+ DDRSS0_PHY_100_DATA
+ DDRSS0_PHY_101_DATA
+ DDRSS0_PHY_102_DATA
+ DDRSS0_PHY_103_DATA
+ DDRSS0_PHY_104_DATA
+ DDRSS0_PHY_105_DATA
+ DDRSS0_PHY_106_DATA
+ DDRSS0_PHY_107_DATA
+ DDRSS0_PHY_108_DATA
+ DDRSS0_PHY_109_DATA
+ DDRSS0_PHY_110_DATA
+ DDRSS0_PHY_111_DATA
+ DDRSS0_PHY_112_DATA
+ DDRSS0_PHY_113_DATA
+ DDRSS0_PHY_114_DATA
+ DDRSS0_PHY_115_DATA
+ DDRSS0_PHY_116_DATA
+ DDRSS0_PHY_117_DATA
+ DDRSS0_PHY_118_DATA
+ DDRSS0_PHY_119_DATA
+ DDRSS0_PHY_120_DATA
+ DDRSS0_PHY_121_DATA
+ DDRSS0_PHY_122_DATA
+ DDRSS0_PHY_123_DATA
+ DDRSS0_PHY_124_DATA
+ DDRSS0_PHY_125_DATA
+ DDRSS0_PHY_126_DATA
+ DDRSS0_PHY_127_DATA
+ DDRSS0_PHY_128_DATA
+ DDRSS0_PHY_129_DATA
+ DDRSS0_PHY_130_DATA
+ DDRSS0_PHY_131_DATA
+ DDRSS0_PHY_132_DATA
+ DDRSS0_PHY_133_DATA
+ DDRSS0_PHY_134_DATA
+ DDRSS0_PHY_135_DATA
+ DDRSS0_PHY_136_DATA
+ DDRSS0_PHY_137_DATA
+ DDRSS0_PHY_138_DATA
+ DDRSS0_PHY_139_DATA
+ DDRSS0_PHY_140_DATA
+ DDRSS0_PHY_141_DATA
+ DDRSS0_PHY_142_DATA
+ DDRSS0_PHY_143_DATA
+ DDRSS0_PHY_144_DATA
+ DDRSS0_PHY_145_DATA
+ DDRSS0_PHY_146_DATA
+ DDRSS0_PHY_147_DATA
+ DDRSS0_PHY_148_DATA
+ DDRSS0_PHY_149_DATA
+ DDRSS0_PHY_150_DATA
+ DDRSS0_PHY_151_DATA
+ DDRSS0_PHY_152_DATA
+ DDRSS0_PHY_153_DATA
+ DDRSS0_PHY_154_DATA
+ DDRSS0_PHY_155_DATA
+ DDRSS0_PHY_156_DATA
+ DDRSS0_PHY_157_DATA
+ DDRSS0_PHY_158_DATA
+ DDRSS0_PHY_159_DATA
+ DDRSS0_PHY_160_DATA
+ DDRSS0_PHY_161_DATA
+ DDRSS0_PHY_162_DATA
+ DDRSS0_PHY_163_DATA
+ DDRSS0_PHY_164_DATA
+ DDRSS0_PHY_165_DATA
+ DDRSS0_PHY_166_DATA
+ DDRSS0_PHY_167_DATA
+ DDRSS0_PHY_168_DATA
+ DDRSS0_PHY_169_DATA
+ DDRSS0_PHY_170_DATA
+ DDRSS0_PHY_171_DATA
+ DDRSS0_PHY_172_DATA
+ DDRSS0_PHY_173_DATA
+ DDRSS0_PHY_174_DATA
+ DDRSS0_PHY_175_DATA
+ DDRSS0_PHY_176_DATA
+ DDRSS0_PHY_177_DATA
+ DDRSS0_PHY_178_DATA
+ DDRSS0_PHY_179_DATA
+ DDRSS0_PHY_180_DATA
+ DDRSS0_PHY_181_DATA
+ DDRSS0_PHY_182_DATA
+ DDRSS0_PHY_183_DATA
+ DDRSS0_PHY_184_DATA
+ DDRSS0_PHY_185_DATA
+ DDRSS0_PHY_186_DATA
+ DDRSS0_PHY_187_DATA
+ DDRSS0_PHY_188_DATA
+ DDRSS0_PHY_189_DATA
+ DDRSS0_PHY_190_DATA
+ DDRSS0_PHY_191_DATA
+ DDRSS0_PHY_192_DATA
+ DDRSS0_PHY_193_DATA
+ DDRSS0_PHY_194_DATA
+ DDRSS0_PHY_195_DATA
+ DDRSS0_PHY_196_DATA
+ DDRSS0_PHY_197_DATA
+ DDRSS0_PHY_198_DATA
+ DDRSS0_PHY_199_DATA
+ DDRSS0_PHY_200_DATA
+ DDRSS0_PHY_201_DATA
+ DDRSS0_PHY_202_DATA
+ DDRSS0_PHY_203_DATA
+ DDRSS0_PHY_204_DATA
+ DDRSS0_PHY_205_DATA
+ DDRSS0_PHY_206_DATA
+ DDRSS0_PHY_207_DATA
+ DDRSS0_PHY_208_DATA
+ DDRSS0_PHY_209_DATA
+ DDRSS0_PHY_210_DATA
+ DDRSS0_PHY_211_DATA
+ DDRSS0_PHY_212_DATA
+ DDRSS0_PHY_213_DATA
+ DDRSS0_PHY_214_DATA
+ DDRSS0_PHY_215_DATA
+ DDRSS0_PHY_216_DATA
+ DDRSS0_PHY_217_DATA
+ DDRSS0_PHY_218_DATA
+ DDRSS0_PHY_219_DATA
+ DDRSS0_PHY_220_DATA
+ DDRSS0_PHY_221_DATA
+ DDRSS0_PHY_222_DATA
+ DDRSS0_PHY_223_DATA
+ DDRSS0_PHY_224_DATA
+ DDRSS0_PHY_225_DATA
+ DDRSS0_PHY_226_DATA
+ DDRSS0_PHY_227_DATA
+ DDRSS0_PHY_228_DATA
+ DDRSS0_PHY_229_DATA
+ DDRSS0_PHY_230_DATA
+ DDRSS0_PHY_231_DATA
+ DDRSS0_PHY_232_DATA
+ DDRSS0_PHY_233_DATA
+ DDRSS0_PHY_234_DATA
+ DDRSS0_PHY_235_DATA
+ DDRSS0_PHY_236_DATA
+ DDRSS0_PHY_237_DATA
+ DDRSS0_PHY_238_DATA
+ DDRSS0_PHY_239_DATA
+ DDRSS0_PHY_240_DATA
+ DDRSS0_PHY_241_DATA
+ DDRSS0_PHY_242_DATA
+ DDRSS0_PHY_243_DATA
+ DDRSS0_PHY_244_DATA
+ DDRSS0_PHY_245_DATA
+ DDRSS0_PHY_246_DATA
+ DDRSS0_PHY_247_DATA
+ DDRSS0_PHY_248_DATA
+ DDRSS0_PHY_249_DATA
+ DDRSS0_PHY_250_DATA
+ DDRSS0_PHY_251_DATA
+ DDRSS0_PHY_252_DATA
+ DDRSS0_PHY_253_DATA
+ DDRSS0_PHY_254_DATA
+ DDRSS0_PHY_255_DATA
+ DDRSS0_PHY_256_DATA
+ DDRSS0_PHY_257_DATA
+ DDRSS0_PHY_258_DATA
+ DDRSS0_PHY_259_DATA
+ DDRSS0_PHY_260_DATA
+ DDRSS0_PHY_261_DATA
+ DDRSS0_PHY_262_DATA
+ DDRSS0_PHY_263_DATA
+ DDRSS0_PHY_264_DATA
+ DDRSS0_PHY_265_DATA
+ DDRSS0_PHY_266_DATA
+ DDRSS0_PHY_267_DATA
+ DDRSS0_PHY_268_DATA
+ DDRSS0_PHY_269_DATA
+ DDRSS0_PHY_270_DATA
+ DDRSS0_PHY_271_DATA
+ DDRSS0_PHY_272_DATA
+ DDRSS0_PHY_273_DATA
+ DDRSS0_PHY_274_DATA
+ DDRSS0_PHY_275_DATA
+ DDRSS0_PHY_276_DATA
+ DDRSS0_PHY_277_DATA
+ DDRSS0_PHY_278_DATA
+ DDRSS0_PHY_279_DATA
+ DDRSS0_PHY_280_DATA
+ DDRSS0_PHY_281_DATA
+ DDRSS0_PHY_282_DATA
+ DDRSS0_PHY_283_DATA
+ DDRSS0_PHY_284_DATA
+ DDRSS0_PHY_285_DATA
+ DDRSS0_PHY_286_DATA
+ DDRSS0_PHY_287_DATA
+ DDRSS0_PHY_288_DATA
+ DDRSS0_PHY_289_DATA
+ DDRSS0_PHY_290_DATA
+ DDRSS0_PHY_291_DATA
+ DDRSS0_PHY_292_DATA
+ DDRSS0_PHY_293_DATA
+ DDRSS0_PHY_294_DATA
+ DDRSS0_PHY_295_DATA
+ DDRSS0_PHY_296_DATA
+ DDRSS0_PHY_297_DATA
+ DDRSS0_PHY_298_DATA
+ DDRSS0_PHY_299_DATA
+ DDRSS0_PHY_300_DATA
+ DDRSS0_PHY_301_DATA
+ DDRSS0_PHY_302_DATA
+ DDRSS0_PHY_303_DATA
+ DDRSS0_PHY_304_DATA
+ DDRSS0_PHY_305_DATA
+ DDRSS0_PHY_306_DATA
+ DDRSS0_PHY_307_DATA
+ DDRSS0_PHY_308_DATA
+ DDRSS0_PHY_309_DATA
+ DDRSS0_PHY_310_DATA
+ DDRSS0_PHY_311_DATA
+ DDRSS0_PHY_312_DATA
+ DDRSS0_PHY_313_DATA
+ DDRSS0_PHY_314_DATA
+ DDRSS0_PHY_315_DATA
+ DDRSS0_PHY_316_DATA
+ DDRSS0_PHY_317_DATA
+ DDRSS0_PHY_318_DATA
+ DDRSS0_PHY_319_DATA
+ DDRSS0_PHY_320_DATA
+ DDRSS0_PHY_321_DATA
+ DDRSS0_PHY_322_DATA
+ DDRSS0_PHY_323_DATA
+ DDRSS0_PHY_324_DATA
+ DDRSS0_PHY_325_DATA
+ DDRSS0_PHY_326_DATA
+ DDRSS0_PHY_327_DATA
+ DDRSS0_PHY_328_DATA
+ DDRSS0_PHY_329_DATA
+ DDRSS0_PHY_330_DATA
+ DDRSS0_PHY_331_DATA
+ DDRSS0_PHY_332_DATA
+ DDRSS0_PHY_333_DATA
+ DDRSS0_PHY_334_DATA
+ DDRSS0_PHY_335_DATA
+ DDRSS0_PHY_336_DATA
+ DDRSS0_PHY_337_DATA
+ DDRSS0_PHY_338_DATA
+ DDRSS0_PHY_339_DATA
+ DDRSS0_PHY_340_DATA
+ DDRSS0_PHY_341_DATA
+ DDRSS0_PHY_342_DATA
+ DDRSS0_PHY_343_DATA
+ DDRSS0_PHY_344_DATA
+ DDRSS0_PHY_345_DATA
+ DDRSS0_PHY_346_DATA
+ DDRSS0_PHY_347_DATA
+ DDRSS0_PHY_348_DATA
+ DDRSS0_PHY_349_DATA
+ DDRSS0_PHY_350_DATA
+ DDRSS0_PHY_351_DATA
+ DDRSS0_PHY_352_DATA
+ DDRSS0_PHY_353_DATA
+ DDRSS0_PHY_354_DATA
+ DDRSS0_PHY_355_DATA
+ DDRSS0_PHY_356_DATA
+ DDRSS0_PHY_357_DATA
+ DDRSS0_PHY_358_DATA
+ DDRSS0_PHY_359_DATA
+ DDRSS0_PHY_360_DATA
+ DDRSS0_PHY_361_DATA
+ DDRSS0_PHY_362_DATA
+ DDRSS0_PHY_363_DATA
+ DDRSS0_PHY_364_DATA
+ DDRSS0_PHY_365_DATA
+ DDRSS0_PHY_366_DATA
+ DDRSS0_PHY_367_DATA
+ DDRSS0_PHY_368_DATA
+ DDRSS0_PHY_369_DATA
+ DDRSS0_PHY_370_DATA
+ DDRSS0_PHY_371_DATA
+ DDRSS0_PHY_372_DATA
+ DDRSS0_PHY_373_DATA
+ DDRSS0_PHY_374_DATA
+ DDRSS0_PHY_375_DATA
+ DDRSS0_PHY_376_DATA
+ DDRSS0_PHY_377_DATA
+ DDRSS0_PHY_378_DATA
+ DDRSS0_PHY_379_DATA
+ DDRSS0_PHY_380_DATA
+ DDRSS0_PHY_381_DATA
+ DDRSS0_PHY_382_DATA
+ DDRSS0_PHY_383_DATA
+ DDRSS0_PHY_384_DATA
+ DDRSS0_PHY_385_DATA
+ DDRSS0_PHY_386_DATA
+ DDRSS0_PHY_387_DATA
+ DDRSS0_PHY_388_DATA
+ DDRSS0_PHY_389_DATA
+ DDRSS0_PHY_390_DATA
+ DDRSS0_PHY_391_DATA
+ DDRSS0_PHY_392_DATA
+ DDRSS0_PHY_393_DATA
+ DDRSS0_PHY_394_DATA
+ DDRSS0_PHY_395_DATA
+ DDRSS0_PHY_396_DATA
+ DDRSS0_PHY_397_DATA
+ DDRSS0_PHY_398_DATA
+ DDRSS0_PHY_399_DATA
+ DDRSS0_PHY_400_DATA
+ DDRSS0_PHY_401_DATA
+ DDRSS0_PHY_402_DATA
+ DDRSS0_PHY_403_DATA
+ DDRSS0_PHY_404_DATA
+ DDRSS0_PHY_405_DATA
+ DDRSS0_PHY_406_DATA
+ DDRSS0_PHY_407_DATA
+ DDRSS0_PHY_408_DATA
+ DDRSS0_PHY_409_DATA
+ DDRSS0_PHY_410_DATA
+ DDRSS0_PHY_411_DATA
+ DDRSS0_PHY_412_DATA
+ DDRSS0_PHY_413_DATA
+ DDRSS0_PHY_414_DATA
+ DDRSS0_PHY_415_DATA
+ DDRSS0_PHY_416_DATA
+ DDRSS0_PHY_417_DATA
+ DDRSS0_PHY_418_DATA
+ DDRSS0_PHY_419_DATA
+ DDRSS0_PHY_420_DATA
+ DDRSS0_PHY_421_DATA
+ DDRSS0_PHY_422_DATA
+ DDRSS0_PHY_423_DATA
+ DDRSS0_PHY_424_DATA
+ DDRSS0_PHY_425_DATA
+ DDRSS0_PHY_426_DATA
+ DDRSS0_PHY_427_DATA
+ DDRSS0_PHY_428_DATA
+ DDRSS0_PHY_429_DATA
+ DDRSS0_PHY_430_DATA
+ DDRSS0_PHY_431_DATA
+ DDRSS0_PHY_432_DATA
+ DDRSS0_PHY_433_DATA
+ DDRSS0_PHY_434_DATA
+ DDRSS0_PHY_435_DATA
+ DDRSS0_PHY_436_DATA
+ DDRSS0_PHY_437_DATA
+ DDRSS0_PHY_438_DATA
+ DDRSS0_PHY_439_DATA
+ DDRSS0_PHY_440_DATA
+ DDRSS0_PHY_441_DATA
+ DDRSS0_PHY_442_DATA
+ DDRSS0_PHY_443_DATA
+ DDRSS0_PHY_444_DATA
+ DDRSS0_PHY_445_DATA
+ DDRSS0_PHY_446_DATA
+ DDRSS0_PHY_447_DATA
+ DDRSS0_PHY_448_DATA
+ DDRSS0_PHY_449_DATA
+ DDRSS0_PHY_450_DATA
+ DDRSS0_PHY_451_DATA
+ DDRSS0_PHY_452_DATA
+ DDRSS0_PHY_453_DATA
+ DDRSS0_PHY_454_DATA
+ DDRSS0_PHY_455_DATA
+ DDRSS0_PHY_456_DATA
+ DDRSS0_PHY_457_DATA
+ DDRSS0_PHY_458_DATA
+ DDRSS0_PHY_459_DATA
+ DDRSS0_PHY_460_DATA
+ DDRSS0_PHY_461_DATA
+ DDRSS0_PHY_462_DATA
+ DDRSS0_PHY_463_DATA
+ DDRSS0_PHY_464_DATA
+ DDRSS0_PHY_465_DATA
+ DDRSS0_PHY_466_DATA
+ DDRSS0_PHY_467_DATA
+ DDRSS0_PHY_468_DATA
+ DDRSS0_PHY_469_DATA
+ DDRSS0_PHY_470_DATA
+ DDRSS0_PHY_471_DATA
+ DDRSS0_PHY_472_DATA
+ DDRSS0_PHY_473_DATA
+ DDRSS0_PHY_474_DATA
+ DDRSS0_PHY_475_DATA
+ DDRSS0_PHY_476_DATA
+ DDRSS0_PHY_477_DATA
+ DDRSS0_PHY_478_DATA
+ DDRSS0_PHY_479_DATA
+ DDRSS0_PHY_480_DATA
+ DDRSS0_PHY_481_DATA
+ DDRSS0_PHY_482_DATA
+ DDRSS0_PHY_483_DATA
+ DDRSS0_PHY_484_DATA
+ DDRSS0_PHY_485_DATA
+ DDRSS0_PHY_486_DATA
+ DDRSS0_PHY_487_DATA
+ DDRSS0_PHY_488_DATA
+ DDRSS0_PHY_489_DATA
+ DDRSS0_PHY_490_DATA
+ DDRSS0_PHY_491_DATA
+ DDRSS0_PHY_492_DATA
+ DDRSS0_PHY_493_DATA
+ DDRSS0_PHY_494_DATA
+ DDRSS0_PHY_495_DATA
+ DDRSS0_PHY_496_DATA
+ DDRSS0_PHY_497_DATA
+ DDRSS0_PHY_498_DATA
+ DDRSS0_PHY_499_DATA
+ DDRSS0_PHY_500_DATA
+ DDRSS0_PHY_501_DATA
+ DDRSS0_PHY_502_DATA
+ DDRSS0_PHY_503_DATA
+ DDRSS0_PHY_504_DATA
+ DDRSS0_PHY_505_DATA
+ DDRSS0_PHY_506_DATA
+ DDRSS0_PHY_507_DATA
+ DDRSS0_PHY_508_DATA
+ DDRSS0_PHY_509_DATA
+ DDRSS0_PHY_510_DATA
+ DDRSS0_PHY_511_DATA
+ DDRSS0_PHY_512_DATA
+ DDRSS0_PHY_513_DATA
+ DDRSS0_PHY_514_DATA
+ DDRSS0_PHY_515_DATA
+ DDRSS0_PHY_516_DATA
+ DDRSS0_PHY_517_DATA
+ DDRSS0_PHY_518_DATA
+ DDRSS0_PHY_519_DATA
+ DDRSS0_PHY_520_DATA
+ DDRSS0_PHY_521_DATA
+ DDRSS0_PHY_522_DATA
+ DDRSS0_PHY_523_DATA
+ DDRSS0_PHY_524_DATA
+ DDRSS0_PHY_525_DATA
+ DDRSS0_PHY_526_DATA
+ DDRSS0_PHY_527_DATA
+ DDRSS0_PHY_528_DATA
+ DDRSS0_PHY_529_DATA
+ DDRSS0_PHY_530_DATA
+ DDRSS0_PHY_531_DATA
+ DDRSS0_PHY_532_DATA
+ DDRSS0_PHY_533_DATA
+ DDRSS0_PHY_534_DATA
+ DDRSS0_PHY_535_DATA
+ DDRSS0_PHY_536_DATA
+ DDRSS0_PHY_537_DATA
+ DDRSS0_PHY_538_DATA
+ DDRSS0_PHY_539_DATA
+ DDRSS0_PHY_540_DATA
+ DDRSS0_PHY_541_DATA
+ DDRSS0_PHY_542_DATA
+ DDRSS0_PHY_543_DATA
+ DDRSS0_PHY_544_DATA
+ DDRSS0_PHY_545_DATA
+ DDRSS0_PHY_546_DATA
+ DDRSS0_PHY_547_DATA
+ DDRSS0_PHY_548_DATA
+ DDRSS0_PHY_549_DATA
+ DDRSS0_PHY_550_DATA
+ DDRSS0_PHY_551_DATA
+ DDRSS0_PHY_552_DATA
+ DDRSS0_PHY_553_DATA
+ DDRSS0_PHY_554_DATA
+ DDRSS0_PHY_555_DATA
+ DDRSS0_PHY_556_DATA
+ DDRSS0_PHY_557_DATA
+ DDRSS0_PHY_558_DATA
+ DDRSS0_PHY_559_DATA
+ DDRSS0_PHY_560_DATA
+ DDRSS0_PHY_561_DATA
+ DDRSS0_PHY_562_DATA
+ DDRSS0_PHY_563_DATA
+ DDRSS0_PHY_564_DATA
+ DDRSS0_PHY_565_DATA
+ DDRSS0_PHY_566_DATA
+ DDRSS0_PHY_567_DATA
+ DDRSS0_PHY_568_DATA
+ DDRSS0_PHY_569_DATA
+ DDRSS0_PHY_570_DATA
+ DDRSS0_PHY_571_DATA
+ DDRSS0_PHY_572_DATA
+ DDRSS0_PHY_573_DATA
+ DDRSS0_PHY_574_DATA
+ DDRSS0_PHY_575_DATA
+ DDRSS0_PHY_576_DATA
+ DDRSS0_PHY_577_DATA
+ DDRSS0_PHY_578_DATA
+ DDRSS0_PHY_579_DATA
+ DDRSS0_PHY_580_DATA
+ DDRSS0_PHY_581_DATA
+ DDRSS0_PHY_582_DATA
+ DDRSS0_PHY_583_DATA
+ DDRSS0_PHY_584_DATA
+ DDRSS0_PHY_585_DATA
+ DDRSS0_PHY_586_DATA
+ DDRSS0_PHY_587_DATA
+ DDRSS0_PHY_588_DATA
+ DDRSS0_PHY_589_DATA
+ DDRSS0_PHY_590_DATA
+ DDRSS0_PHY_591_DATA
+ DDRSS0_PHY_592_DATA
+ DDRSS0_PHY_593_DATA
+ DDRSS0_PHY_594_DATA
+ DDRSS0_PHY_595_DATA
+ DDRSS0_PHY_596_DATA
+ DDRSS0_PHY_597_DATA
+ DDRSS0_PHY_598_DATA
+ DDRSS0_PHY_599_DATA
+ DDRSS0_PHY_600_DATA
+ DDRSS0_PHY_601_DATA
+ DDRSS0_PHY_602_DATA
+ DDRSS0_PHY_603_DATA
+ DDRSS0_PHY_604_DATA
+ DDRSS0_PHY_605_DATA
+ DDRSS0_PHY_606_DATA
+ DDRSS0_PHY_607_DATA
+ DDRSS0_PHY_608_DATA
+ DDRSS0_PHY_609_DATA
+ DDRSS0_PHY_610_DATA
+ DDRSS0_PHY_611_DATA
+ DDRSS0_PHY_612_DATA
+ DDRSS0_PHY_613_DATA
+ DDRSS0_PHY_614_DATA
+ DDRSS0_PHY_615_DATA
+ DDRSS0_PHY_616_DATA
+ DDRSS0_PHY_617_DATA
+ DDRSS0_PHY_618_DATA
+ DDRSS0_PHY_619_DATA
+ DDRSS0_PHY_620_DATA
+ DDRSS0_PHY_621_DATA
+ DDRSS0_PHY_622_DATA
+ DDRSS0_PHY_623_DATA
+ DDRSS0_PHY_624_DATA
+ DDRSS0_PHY_625_DATA
+ DDRSS0_PHY_626_DATA
+ DDRSS0_PHY_627_DATA
+ DDRSS0_PHY_628_DATA
+ DDRSS0_PHY_629_DATA
+ DDRSS0_PHY_630_DATA
+ DDRSS0_PHY_631_DATA
+ DDRSS0_PHY_632_DATA
+ DDRSS0_PHY_633_DATA
+ DDRSS0_PHY_634_DATA
+ DDRSS0_PHY_635_DATA
+ DDRSS0_PHY_636_DATA
+ DDRSS0_PHY_637_DATA
+ DDRSS0_PHY_638_DATA
+ DDRSS0_PHY_639_DATA
+ DDRSS0_PHY_640_DATA
+ DDRSS0_PHY_641_DATA
+ DDRSS0_PHY_642_DATA
+ DDRSS0_PHY_643_DATA
+ DDRSS0_PHY_644_DATA
+ DDRSS0_PHY_645_DATA
+ DDRSS0_PHY_646_DATA
+ DDRSS0_PHY_647_DATA
+ DDRSS0_PHY_648_DATA
+ DDRSS0_PHY_649_DATA
+ DDRSS0_PHY_650_DATA
+ DDRSS0_PHY_651_DATA
+ DDRSS0_PHY_652_DATA
+ DDRSS0_PHY_653_DATA
+ DDRSS0_PHY_654_DATA
+ DDRSS0_PHY_655_DATA
+ DDRSS0_PHY_656_DATA
+ DDRSS0_PHY_657_DATA
+ DDRSS0_PHY_658_DATA
+ DDRSS0_PHY_659_DATA
+ DDRSS0_PHY_660_DATA
+ DDRSS0_PHY_661_DATA
+ DDRSS0_PHY_662_DATA
+ DDRSS0_PHY_663_DATA
+ DDRSS0_PHY_664_DATA
+ DDRSS0_PHY_665_DATA
+ DDRSS0_PHY_666_DATA
+ DDRSS0_PHY_667_DATA
+ DDRSS0_PHY_668_DATA
+ DDRSS0_PHY_669_DATA
+ DDRSS0_PHY_670_DATA
+ DDRSS0_PHY_671_DATA
+ DDRSS0_PHY_672_DATA
+ DDRSS0_PHY_673_DATA
+ DDRSS0_PHY_674_DATA
+ DDRSS0_PHY_675_DATA
+ DDRSS0_PHY_676_DATA
+ DDRSS0_PHY_677_DATA
+ DDRSS0_PHY_678_DATA
+ DDRSS0_PHY_679_DATA
+ DDRSS0_PHY_680_DATA
+ DDRSS0_PHY_681_DATA
+ DDRSS0_PHY_682_DATA
+ DDRSS0_PHY_683_DATA
+ DDRSS0_PHY_684_DATA
+ DDRSS0_PHY_685_DATA
+ DDRSS0_PHY_686_DATA
+ DDRSS0_PHY_687_DATA
+ DDRSS0_PHY_688_DATA
+ DDRSS0_PHY_689_DATA
+ DDRSS0_PHY_690_DATA
+ DDRSS0_PHY_691_DATA
+ DDRSS0_PHY_692_DATA
+ DDRSS0_PHY_693_DATA
+ DDRSS0_PHY_694_DATA
+ DDRSS0_PHY_695_DATA
+ DDRSS0_PHY_696_DATA
+ DDRSS0_PHY_697_DATA
+ DDRSS0_PHY_698_DATA
+ DDRSS0_PHY_699_DATA
+ DDRSS0_PHY_700_DATA
+ DDRSS0_PHY_701_DATA
+ DDRSS0_PHY_702_DATA
+ DDRSS0_PHY_703_DATA
+ DDRSS0_PHY_704_DATA
+ DDRSS0_PHY_705_DATA
+ DDRSS0_PHY_706_DATA
+ DDRSS0_PHY_707_DATA
+ DDRSS0_PHY_708_DATA
+ DDRSS0_PHY_709_DATA
+ DDRSS0_PHY_710_DATA
+ DDRSS0_PHY_711_DATA
+ DDRSS0_PHY_712_DATA
+ DDRSS0_PHY_713_DATA
+ DDRSS0_PHY_714_DATA
+ DDRSS0_PHY_715_DATA
+ DDRSS0_PHY_716_DATA
+ DDRSS0_PHY_717_DATA
+ DDRSS0_PHY_718_DATA
+ DDRSS0_PHY_719_DATA
+ DDRSS0_PHY_720_DATA
+ DDRSS0_PHY_721_DATA
+ DDRSS0_PHY_722_DATA
+ DDRSS0_PHY_723_DATA
+ DDRSS0_PHY_724_DATA
+ DDRSS0_PHY_725_DATA
+ DDRSS0_PHY_726_DATA
+ DDRSS0_PHY_727_DATA
+ DDRSS0_PHY_728_DATA
+ DDRSS0_PHY_729_DATA
+ DDRSS0_PHY_730_DATA
+ DDRSS0_PHY_731_DATA
+ DDRSS0_PHY_732_DATA
+ DDRSS0_PHY_733_DATA
+ DDRSS0_PHY_734_DATA
+ DDRSS0_PHY_735_DATA
+ DDRSS0_PHY_736_DATA
+ DDRSS0_PHY_737_DATA
+ DDRSS0_PHY_738_DATA
+ DDRSS0_PHY_739_DATA
+ DDRSS0_PHY_740_DATA
+ DDRSS0_PHY_741_DATA
+ DDRSS0_PHY_742_DATA
+ DDRSS0_PHY_743_DATA
+ DDRSS0_PHY_744_DATA
+ DDRSS0_PHY_745_DATA
+ DDRSS0_PHY_746_DATA
+ DDRSS0_PHY_747_DATA
+ DDRSS0_PHY_748_DATA
+ DDRSS0_PHY_749_DATA
+ DDRSS0_PHY_750_DATA
+ DDRSS0_PHY_751_DATA
+ DDRSS0_PHY_752_DATA
+ DDRSS0_PHY_753_DATA
+ DDRSS0_PHY_754_DATA
+ DDRSS0_PHY_755_DATA
+ DDRSS0_PHY_756_DATA
+ DDRSS0_PHY_757_DATA
+ DDRSS0_PHY_758_DATA
+ DDRSS0_PHY_759_DATA
+ DDRSS0_PHY_760_DATA
+ DDRSS0_PHY_761_DATA
+ DDRSS0_PHY_762_DATA
+ DDRSS0_PHY_763_DATA
+ DDRSS0_PHY_764_DATA
+ DDRSS0_PHY_765_DATA
+ DDRSS0_PHY_766_DATA
+ DDRSS0_PHY_767_DATA
+ DDRSS0_PHY_768_DATA
+ DDRSS0_PHY_769_DATA
+ DDRSS0_PHY_770_DATA
+ DDRSS0_PHY_771_DATA
+ DDRSS0_PHY_772_DATA
+ DDRSS0_PHY_773_DATA
+ DDRSS0_PHY_774_DATA
+ DDRSS0_PHY_775_DATA
+ DDRSS0_PHY_776_DATA
+ DDRSS0_PHY_777_DATA
+ DDRSS0_PHY_778_DATA
+ DDRSS0_PHY_779_DATA
+ DDRSS0_PHY_780_DATA
+ DDRSS0_PHY_781_DATA
+ DDRSS0_PHY_782_DATA
+ DDRSS0_PHY_783_DATA
+ DDRSS0_PHY_784_DATA
+ DDRSS0_PHY_785_DATA
+ DDRSS0_PHY_786_DATA
+ DDRSS0_PHY_787_DATA
+ DDRSS0_PHY_788_DATA
+ DDRSS0_PHY_789_DATA
+ DDRSS0_PHY_790_DATA
+ DDRSS0_PHY_791_DATA
+ DDRSS0_PHY_792_DATA
+ DDRSS0_PHY_793_DATA
+ DDRSS0_PHY_794_DATA
+ DDRSS0_PHY_795_DATA
+ DDRSS0_PHY_796_DATA
+ DDRSS0_PHY_797_DATA
+ DDRSS0_PHY_798_DATA
+ DDRSS0_PHY_799_DATA
+ DDRSS0_PHY_800_DATA
+ DDRSS0_PHY_801_DATA
+ DDRSS0_PHY_802_DATA
+ DDRSS0_PHY_803_DATA
+ DDRSS0_PHY_804_DATA
+ DDRSS0_PHY_805_DATA
+ DDRSS0_PHY_806_DATA
+ DDRSS0_PHY_807_DATA
+ DDRSS0_PHY_808_DATA
+ DDRSS0_PHY_809_DATA
+ DDRSS0_PHY_810_DATA
+ DDRSS0_PHY_811_DATA
+ DDRSS0_PHY_812_DATA
+ DDRSS0_PHY_813_DATA
+ DDRSS0_PHY_814_DATA
+ DDRSS0_PHY_815_DATA
+ DDRSS0_PHY_816_DATA
+ DDRSS0_PHY_817_DATA
+ DDRSS0_PHY_818_DATA
+ DDRSS0_PHY_819_DATA
+ DDRSS0_PHY_820_DATA
+ DDRSS0_PHY_821_DATA
+ DDRSS0_PHY_822_DATA
+ DDRSS0_PHY_823_DATA
+ DDRSS0_PHY_824_DATA
+ DDRSS0_PHY_825_DATA
+ DDRSS0_PHY_826_DATA
+ DDRSS0_PHY_827_DATA
+ DDRSS0_PHY_828_DATA
+ DDRSS0_PHY_829_DATA
+ DDRSS0_PHY_830_DATA
+ DDRSS0_PHY_831_DATA
+ DDRSS0_PHY_832_DATA
+ DDRSS0_PHY_833_DATA
+ DDRSS0_PHY_834_DATA
+ DDRSS0_PHY_835_DATA
+ DDRSS0_PHY_836_DATA
+ DDRSS0_PHY_837_DATA
+ DDRSS0_PHY_838_DATA
+ DDRSS0_PHY_839_DATA
+ DDRSS0_PHY_840_DATA
+ DDRSS0_PHY_841_DATA
+ DDRSS0_PHY_842_DATA
+ DDRSS0_PHY_843_DATA
+ DDRSS0_PHY_844_DATA
+ DDRSS0_PHY_845_DATA
+ DDRSS0_PHY_846_DATA
+ DDRSS0_PHY_847_DATA
+ DDRSS0_PHY_848_DATA
+ DDRSS0_PHY_849_DATA
+ DDRSS0_PHY_850_DATA
+ DDRSS0_PHY_851_DATA
+ DDRSS0_PHY_852_DATA
+ DDRSS0_PHY_853_DATA
+ DDRSS0_PHY_854_DATA
+ DDRSS0_PHY_855_DATA
+ DDRSS0_PHY_856_DATA
+ DDRSS0_PHY_857_DATA
+ DDRSS0_PHY_858_DATA
+ DDRSS0_PHY_859_DATA
+ DDRSS0_PHY_860_DATA
+ DDRSS0_PHY_861_DATA
+ DDRSS0_PHY_862_DATA
+ DDRSS0_PHY_863_DATA
+ DDRSS0_PHY_864_DATA
+ DDRSS0_PHY_865_DATA
+ DDRSS0_PHY_866_DATA
+ DDRSS0_PHY_867_DATA
+ DDRSS0_PHY_868_DATA
+ DDRSS0_PHY_869_DATA
+ DDRSS0_PHY_870_DATA
+ DDRSS0_PHY_871_DATA
+ DDRSS0_PHY_872_DATA
+ DDRSS0_PHY_873_DATA
+ DDRSS0_PHY_874_DATA
+ DDRSS0_PHY_875_DATA
+ DDRSS0_PHY_876_DATA
+ DDRSS0_PHY_877_DATA
+ DDRSS0_PHY_878_DATA
+ DDRSS0_PHY_879_DATA
+ DDRSS0_PHY_880_DATA
+ DDRSS0_PHY_881_DATA
+ DDRSS0_PHY_882_DATA
+ DDRSS0_PHY_883_DATA
+ DDRSS0_PHY_884_DATA
+ DDRSS0_PHY_885_DATA
+ DDRSS0_PHY_886_DATA
+ DDRSS0_PHY_887_DATA
+ DDRSS0_PHY_888_DATA
+ DDRSS0_PHY_889_DATA
+ DDRSS0_PHY_890_DATA
+ DDRSS0_PHY_891_DATA
+ DDRSS0_PHY_892_DATA
+ DDRSS0_PHY_893_DATA
+ DDRSS0_PHY_894_DATA
+ DDRSS0_PHY_895_DATA
+ DDRSS0_PHY_896_DATA
+ DDRSS0_PHY_897_DATA
+ DDRSS0_PHY_898_DATA
+ DDRSS0_PHY_899_DATA
+ DDRSS0_PHY_900_DATA
+ DDRSS0_PHY_901_DATA
+ DDRSS0_PHY_902_DATA
+ DDRSS0_PHY_903_DATA
+ DDRSS0_PHY_904_DATA
+ DDRSS0_PHY_905_DATA
+ DDRSS0_PHY_906_DATA
+ DDRSS0_PHY_907_DATA
+ DDRSS0_PHY_908_DATA
+ DDRSS0_PHY_909_DATA
+ DDRSS0_PHY_910_DATA
+ DDRSS0_PHY_911_DATA
+ DDRSS0_PHY_912_DATA
+ DDRSS0_PHY_913_DATA
+ DDRSS0_PHY_914_DATA
+ DDRSS0_PHY_915_DATA
+ DDRSS0_PHY_916_DATA
+ DDRSS0_PHY_917_DATA
+ DDRSS0_PHY_918_DATA
+ DDRSS0_PHY_919_DATA
+ DDRSS0_PHY_920_DATA
+ DDRSS0_PHY_921_DATA
+ DDRSS0_PHY_922_DATA
+ DDRSS0_PHY_923_DATA
+ DDRSS0_PHY_924_DATA
+ DDRSS0_PHY_925_DATA
+ DDRSS0_PHY_926_DATA
+ DDRSS0_PHY_927_DATA
+ DDRSS0_PHY_928_DATA
+ DDRSS0_PHY_929_DATA
+ DDRSS0_PHY_930_DATA
+ DDRSS0_PHY_931_DATA
+ DDRSS0_PHY_932_DATA
+ DDRSS0_PHY_933_DATA
+ DDRSS0_PHY_934_DATA
+ DDRSS0_PHY_935_DATA
+ DDRSS0_PHY_936_DATA
+ DDRSS0_PHY_937_DATA
+ DDRSS0_PHY_938_DATA
+ DDRSS0_PHY_939_DATA
+ DDRSS0_PHY_940_DATA
+ DDRSS0_PHY_941_DATA
+ DDRSS0_PHY_942_DATA
+ DDRSS0_PHY_943_DATA
+ DDRSS0_PHY_944_DATA
+ DDRSS0_PHY_945_DATA
+ DDRSS0_PHY_946_DATA
+ DDRSS0_PHY_947_DATA
+ DDRSS0_PHY_948_DATA
+ DDRSS0_PHY_949_DATA
+ DDRSS0_PHY_950_DATA
+ DDRSS0_PHY_951_DATA
+ DDRSS0_PHY_952_DATA
+ DDRSS0_PHY_953_DATA
+ DDRSS0_PHY_954_DATA
+ DDRSS0_PHY_955_DATA
+ DDRSS0_PHY_956_DATA
+ DDRSS0_PHY_957_DATA
+ DDRSS0_PHY_958_DATA
+ DDRSS0_PHY_959_DATA
+ DDRSS0_PHY_960_DATA
+ DDRSS0_PHY_961_DATA
+ DDRSS0_PHY_962_DATA
+ DDRSS0_PHY_963_DATA
+ DDRSS0_PHY_964_DATA
+ DDRSS0_PHY_965_DATA
+ DDRSS0_PHY_966_DATA
+ DDRSS0_PHY_967_DATA
+ DDRSS0_PHY_968_DATA
+ DDRSS0_PHY_969_DATA
+ DDRSS0_PHY_970_DATA
+ DDRSS0_PHY_971_DATA
+ DDRSS0_PHY_972_DATA
+ DDRSS0_PHY_973_DATA
+ DDRSS0_PHY_974_DATA
+ DDRSS0_PHY_975_DATA
+ DDRSS0_PHY_976_DATA
+ DDRSS0_PHY_977_DATA
+ DDRSS0_PHY_978_DATA
+ DDRSS0_PHY_979_DATA
+ DDRSS0_PHY_980_DATA
+ DDRSS0_PHY_981_DATA
+ DDRSS0_PHY_982_DATA
+ DDRSS0_PHY_983_DATA
+ DDRSS0_PHY_984_DATA
+ DDRSS0_PHY_985_DATA
+ DDRSS0_PHY_986_DATA
+ DDRSS0_PHY_987_DATA
+ DDRSS0_PHY_988_DATA
+ DDRSS0_PHY_989_DATA
+ DDRSS0_PHY_990_DATA
+ DDRSS0_PHY_991_DATA
+ DDRSS0_PHY_992_DATA
+ DDRSS0_PHY_993_DATA
+ DDRSS0_PHY_994_DATA
+ DDRSS0_PHY_995_DATA
+ DDRSS0_PHY_996_DATA
+ DDRSS0_PHY_997_DATA
+ DDRSS0_PHY_998_DATA
+ DDRSS0_PHY_999_DATA
+ DDRSS0_PHY_1000_DATA
+ DDRSS0_PHY_1001_DATA
+ DDRSS0_PHY_1002_DATA
+ DDRSS0_PHY_1003_DATA
+ DDRSS0_PHY_1004_DATA
+ DDRSS0_PHY_1005_DATA
+ DDRSS0_PHY_1006_DATA
+ DDRSS0_PHY_1007_DATA
+ DDRSS0_PHY_1008_DATA
+ DDRSS0_PHY_1009_DATA
+ DDRSS0_PHY_1010_DATA
+ DDRSS0_PHY_1011_DATA
+ DDRSS0_PHY_1012_DATA
+ DDRSS0_PHY_1013_DATA
+ DDRSS0_PHY_1014_DATA
+ DDRSS0_PHY_1015_DATA
+ DDRSS0_PHY_1016_DATA
+ DDRSS0_PHY_1017_DATA
+ DDRSS0_PHY_1018_DATA
+ DDRSS0_PHY_1019_DATA
+ DDRSS0_PHY_1020_DATA
+ DDRSS0_PHY_1021_DATA
+ DDRSS0_PHY_1022_DATA
+ DDRSS0_PHY_1023_DATA
+ DDRSS0_PHY_1024_DATA
+ DDRSS0_PHY_1025_DATA
+ DDRSS0_PHY_1026_DATA
+ DDRSS0_PHY_1027_DATA
+ DDRSS0_PHY_1028_DATA
+ DDRSS0_PHY_1029_DATA
+ DDRSS0_PHY_1030_DATA
+ DDRSS0_PHY_1031_DATA
+ DDRSS0_PHY_1032_DATA
+ DDRSS0_PHY_1033_DATA
+ DDRSS0_PHY_1034_DATA
+ DDRSS0_PHY_1035_DATA
+ DDRSS0_PHY_1036_DATA
+ DDRSS0_PHY_1037_DATA
+ DDRSS0_PHY_1038_DATA
+ DDRSS0_PHY_1039_DATA
+ DDRSS0_PHY_1040_DATA
+ DDRSS0_PHY_1041_DATA
+ DDRSS0_PHY_1042_DATA
+ DDRSS0_PHY_1043_DATA
+ DDRSS0_PHY_1044_DATA
+ DDRSS0_PHY_1045_DATA
+ DDRSS0_PHY_1046_DATA
+ DDRSS0_PHY_1047_DATA
+ DDRSS0_PHY_1048_DATA
+ DDRSS0_PHY_1049_DATA
+ DDRSS0_PHY_1050_DATA
+ DDRSS0_PHY_1051_DATA
+ DDRSS0_PHY_1052_DATA
+ DDRSS0_PHY_1053_DATA
+ DDRSS0_PHY_1054_DATA
+ DDRSS0_PHY_1055_DATA
+ DDRSS0_PHY_1056_DATA
+ DDRSS0_PHY_1057_DATA
+ DDRSS0_PHY_1058_DATA
+ DDRSS0_PHY_1059_DATA
+ DDRSS0_PHY_1060_DATA
+ DDRSS0_PHY_1061_DATA
+ DDRSS0_PHY_1062_DATA
+ DDRSS0_PHY_1063_DATA
+ DDRSS0_PHY_1064_DATA
+ DDRSS0_PHY_1065_DATA
+ DDRSS0_PHY_1066_DATA
+ DDRSS0_PHY_1067_DATA
+ DDRSS0_PHY_1068_DATA
+ DDRSS0_PHY_1069_DATA
+ DDRSS0_PHY_1070_DATA
+ DDRSS0_PHY_1071_DATA
+ DDRSS0_PHY_1072_DATA
+ DDRSS0_PHY_1073_DATA
+ DDRSS0_PHY_1074_DATA
+ DDRSS0_PHY_1075_DATA
+ DDRSS0_PHY_1076_DATA
+ DDRSS0_PHY_1077_DATA
+ DDRSS0_PHY_1078_DATA
+ DDRSS0_PHY_1079_DATA
+ DDRSS0_PHY_1080_DATA
+ DDRSS0_PHY_1081_DATA
+ DDRSS0_PHY_1082_DATA
+ DDRSS0_PHY_1083_DATA
+ DDRSS0_PHY_1084_DATA
+ DDRSS0_PHY_1085_DATA
+ DDRSS0_PHY_1086_DATA
+ DDRSS0_PHY_1087_DATA
+ DDRSS0_PHY_1088_DATA
+ DDRSS0_PHY_1089_DATA
+ DDRSS0_PHY_1090_DATA
+ DDRSS0_PHY_1091_DATA
+ DDRSS0_PHY_1092_DATA
+ DDRSS0_PHY_1093_DATA
+ DDRSS0_PHY_1094_DATA
+ DDRSS0_PHY_1095_DATA
+ DDRSS0_PHY_1096_DATA
+ DDRSS0_PHY_1097_DATA
+ DDRSS0_PHY_1098_DATA
+ DDRSS0_PHY_1099_DATA
+ DDRSS0_PHY_1100_DATA
+ DDRSS0_PHY_1101_DATA
+ DDRSS0_PHY_1102_DATA
+ DDRSS0_PHY_1103_DATA
+ DDRSS0_PHY_1104_DATA
+ DDRSS0_PHY_1105_DATA
+ DDRSS0_PHY_1106_DATA
+ DDRSS0_PHY_1107_DATA
+ DDRSS0_PHY_1108_DATA
+ DDRSS0_PHY_1109_DATA
+ DDRSS0_PHY_1110_DATA
+ DDRSS0_PHY_1111_DATA
+ DDRSS0_PHY_1112_DATA
+ DDRSS0_PHY_1113_DATA
+ DDRSS0_PHY_1114_DATA
+ DDRSS0_PHY_1115_DATA
+ DDRSS0_PHY_1116_DATA
+ DDRSS0_PHY_1117_DATA
+ DDRSS0_PHY_1118_DATA
+ DDRSS0_PHY_1119_DATA
+ DDRSS0_PHY_1120_DATA
+ DDRSS0_PHY_1121_DATA
+ DDRSS0_PHY_1122_DATA
+ DDRSS0_PHY_1123_DATA
+ DDRSS0_PHY_1124_DATA
+ DDRSS0_PHY_1125_DATA
+ DDRSS0_PHY_1126_DATA
+ DDRSS0_PHY_1127_DATA
+ DDRSS0_PHY_1128_DATA
+ DDRSS0_PHY_1129_DATA
+ DDRSS0_PHY_1130_DATA
+ DDRSS0_PHY_1131_DATA
+ DDRSS0_PHY_1132_DATA
+ DDRSS0_PHY_1133_DATA
+ DDRSS0_PHY_1134_DATA
+ DDRSS0_PHY_1135_DATA
+ DDRSS0_PHY_1136_DATA
+ DDRSS0_PHY_1137_DATA
+ DDRSS0_PHY_1138_DATA
+ DDRSS0_PHY_1139_DATA
+ DDRSS0_PHY_1140_DATA
+ DDRSS0_PHY_1141_DATA
+ DDRSS0_PHY_1142_DATA
+ DDRSS0_PHY_1143_DATA
+ DDRSS0_PHY_1144_DATA
+ DDRSS0_PHY_1145_DATA
+ DDRSS0_PHY_1146_DATA
+ DDRSS0_PHY_1147_DATA
+ DDRSS0_PHY_1148_DATA
+ DDRSS0_PHY_1149_DATA
+ DDRSS0_PHY_1150_DATA
+ DDRSS0_PHY_1151_DATA
+ DDRSS0_PHY_1152_DATA
+ DDRSS0_PHY_1153_DATA
+ DDRSS0_PHY_1154_DATA
+ DDRSS0_PHY_1155_DATA
+ DDRSS0_PHY_1156_DATA
+ DDRSS0_PHY_1157_DATA
+ DDRSS0_PHY_1158_DATA
+ DDRSS0_PHY_1159_DATA
+ DDRSS0_PHY_1160_DATA
+ DDRSS0_PHY_1161_DATA
+ DDRSS0_PHY_1162_DATA
+ DDRSS0_PHY_1163_DATA
+ DDRSS0_PHY_1164_DATA
+ DDRSS0_PHY_1165_DATA
+ DDRSS0_PHY_1166_DATA
+ DDRSS0_PHY_1167_DATA
+ DDRSS0_PHY_1168_DATA
+ DDRSS0_PHY_1169_DATA
+ DDRSS0_PHY_1170_DATA
+ DDRSS0_PHY_1171_DATA
+ DDRSS0_PHY_1172_DATA
+ DDRSS0_PHY_1173_DATA
+ DDRSS0_PHY_1174_DATA
+ DDRSS0_PHY_1175_DATA
+ DDRSS0_PHY_1176_DATA
+ DDRSS0_PHY_1177_DATA
+ DDRSS0_PHY_1178_DATA
+ DDRSS0_PHY_1179_DATA
+ DDRSS0_PHY_1180_DATA
+ DDRSS0_PHY_1181_DATA
+ DDRSS0_PHY_1182_DATA
+ DDRSS0_PHY_1183_DATA
+ DDRSS0_PHY_1184_DATA
+ DDRSS0_PHY_1185_DATA
+ DDRSS0_PHY_1186_DATA
+ DDRSS0_PHY_1187_DATA
+ DDRSS0_PHY_1188_DATA
+ DDRSS0_PHY_1189_DATA
+ DDRSS0_PHY_1190_DATA
+ DDRSS0_PHY_1191_DATA
+ DDRSS0_PHY_1192_DATA
+ DDRSS0_PHY_1193_DATA
+ DDRSS0_PHY_1194_DATA
+ DDRSS0_PHY_1195_DATA
+ DDRSS0_PHY_1196_DATA
+ DDRSS0_PHY_1197_DATA
+ DDRSS0_PHY_1198_DATA
+ DDRSS0_PHY_1199_DATA
+ DDRSS0_PHY_1200_DATA
+ DDRSS0_PHY_1201_DATA
+ DDRSS0_PHY_1202_DATA
+ DDRSS0_PHY_1203_DATA
+ DDRSS0_PHY_1204_DATA
+ DDRSS0_PHY_1205_DATA
+ DDRSS0_PHY_1206_DATA
+ DDRSS0_PHY_1207_DATA
+ DDRSS0_PHY_1208_DATA
+ DDRSS0_PHY_1209_DATA
+ DDRSS0_PHY_1210_DATA
+ DDRSS0_PHY_1211_DATA
+ DDRSS0_PHY_1212_DATA
+ DDRSS0_PHY_1213_DATA
+ DDRSS0_PHY_1214_DATA
+ DDRSS0_PHY_1215_DATA
+ DDRSS0_PHY_1216_DATA
+ DDRSS0_PHY_1217_DATA
+ DDRSS0_PHY_1218_DATA
+ DDRSS0_PHY_1219_DATA
+ DDRSS0_PHY_1220_DATA
+ DDRSS0_PHY_1221_DATA
+ DDRSS0_PHY_1222_DATA
+ DDRSS0_PHY_1223_DATA
+ DDRSS0_PHY_1224_DATA
+ DDRSS0_PHY_1225_DATA
+ DDRSS0_PHY_1226_DATA
+ DDRSS0_PHY_1227_DATA
+ DDRSS0_PHY_1228_DATA
+ DDRSS0_PHY_1229_DATA
+ DDRSS0_PHY_1230_DATA
+ DDRSS0_PHY_1231_DATA
+ DDRSS0_PHY_1232_DATA
+ DDRSS0_PHY_1233_DATA
+ DDRSS0_PHY_1234_DATA
+ DDRSS0_PHY_1235_DATA
+ DDRSS0_PHY_1236_DATA
+ DDRSS0_PHY_1237_DATA
+ DDRSS0_PHY_1238_DATA
+ DDRSS0_PHY_1239_DATA
+ DDRSS0_PHY_1240_DATA
+ DDRSS0_PHY_1241_DATA
+ DDRSS0_PHY_1242_DATA
+ DDRSS0_PHY_1243_DATA
+ DDRSS0_PHY_1244_DATA
+ DDRSS0_PHY_1245_DATA
+ DDRSS0_PHY_1246_DATA
+ DDRSS0_PHY_1247_DATA
+ DDRSS0_PHY_1248_DATA
+ DDRSS0_PHY_1249_DATA
+ DDRSS0_PHY_1250_DATA
+ DDRSS0_PHY_1251_DATA
+ DDRSS0_PHY_1252_DATA
+ DDRSS0_PHY_1253_DATA
+ DDRSS0_PHY_1254_DATA
+ DDRSS0_PHY_1255_DATA
+ DDRSS0_PHY_1256_DATA
+ DDRSS0_PHY_1257_DATA
+ DDRSS0_PHY_1258_DATA
+ DDRSS0_PHY_1259_DATA
+ DDRSS0_PHY_1260_DATA
+ DDRSS0_PHY_1261_DATA
+ DDRSS0_PHY_1262_DATA
+ DDRSS0_PHY_1263_DATA
+ DDRSS0_PHY_1264_DATA
+ DDRSS0_PHY_1265_DATA
+ DDRSS0_PHY_1266_DATA
+ DDRSS0_PHY_1267_DATA
+ DDRSS0_PHY_1268_DATA
+ DDRSS0_PHY_1269_DATA
+ DDRSS0_PHY_1270_DATA
+ DDRSS0_PHY_1271_DATA
+ DDRSS0_PHY_1272_DATA
+ DDRSS0_PHY_1273_DATA
+ DDRSS0_PHY_1274_DATA
+ DDRSS0_PHY_1275_DATA
+ DDRSS0_PHY_1276_DATA
+ DDRSS0_PHY_1277_DATA
+ DDRSS0_PHY_1278_DATA
+ DDRSS0_PHY_1279_DATA
+ DDRSS0_PHY_1280_DATA
+ DDRSS0_PHY_1281_DATA
+ DDRSS0_PHY_1282_DATA
+ DDRSS0_PHY_1283_DATA
+ DDRSS0_PHY_1284_DATA
+ DDRSS0_PHY_1285_DATA
+ DDRSS0_PHY_1286_DATA
+ DDRSS0_PHY_1287_DATA
+ DDRSS0_PHY_1288_DATA
+ DDRSS0_PHY_1289_DATA
+ DDRSS0_PHY_1290_DATA
+ DDRSS0_PHY_1291_DATA
+ DDRSS0_PHY_1292_DATA
+ DDRSS0_PHY_1293_DATA
+ DDRSS0_PHY_1294_DATA
+ DDRSS0_PHY_1295_DATA
+ DDRSS0_PHY_1296_DATA
+ DDRSS0_PHY_1297_DATA
+ DDRSS0_PHY_1298_DATA
+ DDRSS0_PHY_1299_DATA
+ DDRSS0_PHY_1300_DATA
+ DDRSS0_PHY_1301_DATA
+ DDRSS0_PHY_1302_DATA
+ DDRSS0_PHY_1303_DATA
+ DDRSS0_PHY_1304_DATA
+ DDRSS0_PHY_1305_DATA
+ DDRSS0_PHY_1306_DATA
+ DDRSS0_PHY_1307_DATA
+ DDRSS0_PHY_1308_DATA
+ DDRSS0_PHY_1309_DATA
+ DDRSS0_PHY_1310_DATA
+ DDRSS0_PHY_1311_DATA
+ DDRSS0_PHY_1312_DATA
+ DDRSS0_PHY_1313_DATA
+ DDRSS0_PHY_1314_DATA
+ DDRSS0_PHY_1315_DATA
+ DDRSS0_PHY_1316_DATA
+ DDRSS0_PHY_1317_DATA
+ DDRSS0_PHY_1318_DATA
+ DDRSS0_PHY_1319_DATA
+ DDRSS0_PHY_1320_DATA
+ DDRSS0_PHY_1321_DATA
+ DDRSS0_PHY_1322_DATA
+ DDRSS0_PHY_1323_DATA
+ DDRSS0_PHY_1324_DATA
+ DDRSS0_PHY_1325_DATA
+ DDRSS0_PHY_1326_DATA
+ DDRSS0_PHY_1327_DATA
+ DDRSS0_PHY_1328_DATA
+ DDRSS0_PHY_1329_DATA
+ DDRSS0_PHY_1330_DATA
+ DDRSS0_PHY_1331_DATA
+ DDRSS0_PHY_1332_DATA
+ DDRSS0_PHY_1333_DATA
+ DDRSS0_PHY_1334_DATA
+ DDRSS0_PHY_1335_DATA
+ DDRSS0_PHY_1336_DATA
+ DDRSS0_PHY_1337_DATA
+ DDRSS0_PHY_1338_DATA
+ DDRSS0_PHY_1339_DATA
+ DDRSS0_PHY_1340_DATA
+ DDRSS0_PHY_1341_DATA
+ DDRSS0_PHY_1342_DATA
+ DDRSS0_PHY_1343_DATA
+ DDRSS0_PHY_1344_DATA
+ DDRSS0_PHY_1345_DATA
+ DDRSS0_PHY_1346_DATA
+ DDRSS0_PHY_1347_DATA
+ DDRSS0_PHY_1348_DATA
+ DDRSS0_PHY_1349_DATA
+ DDRSS0_PHY_1350_DATA
+ DDRSS0_PHY_1351_DATA
+ DDRSS0_PHY_1352_DATA
+ DDRSS0_PHY_1353_DATA
+ DDRSS0_PHY_1354_DATA
+ DDRSS0_PHY_1355_DATA
+ DDRSS0_PHY_1356_DATA
+ DDRSS0_PHY_1357_DATA
+ DDRSS0_PHY_1358_DATA
+ DDRSS0_PHY_1359_DATA
+ DDRSS0_PHY_1360_DATA
+ DDRSS0_PHY_1361_DATA
+ DDRSS0_PHY_1362_DATA
+ DDRSS0_PHY_1363_DATA
+ DDRSS0_PHY_1364_DATA
+ DDRSS0_PHY_1365_DATA
+ DDRSS0_PHY_1366_DATA
+ DDRSS0_PHY_1367_DATA
+ DDRSS0_PHY_1368_DATA
+ DDRSS0_PHY_1369_DATA
+ DDRSS0_PHY_1370_DATA
+ DDRSS0_PHY_1371_DATA
+ DDRSS0_PHY_1372_DATA
+ DDRSS0_PHY_1373_DATA
+ DDRSS0_PHY_1374_DATA
+ DDRSS0_PHY_1375_DATA
+ DDRSS0_PHY_1376_DATA
+ DDRSS0_PHY_1377_DATA
+ DDRSS0_PHY_1378_DATA
+ DDRSS0_PHY_1379_DATA
+ DDRSS0_PHY_1380_DATA
+ DDRSS0_PHY_1381_DATA
+ DDRSS0_PHY_1382_DATA
+ DDRSS0_PHY_1383_DATA
+ DDRSS0_PHY_1384_DATA
+ DDRSS0_PHY_1385_DATA
+ DDRSS0_PHY_1386_DATA
+ DDRSS0_PHY_1387_DATA
+ DDRSS0_PHY_1388_DATA
+ DDRSS0_PHY_1389_DATA
+ DDRSS0_PHY_1390_DATA
+ DDRSS0_PHY_1391_DATA
+ DDRSS0_PHY_1392_DATA
+ DDRSS0_PHY_1393_DATA
+ DDRSS0_PHY_1394_DATA
+ DDRSS0_PHY_1395_DATA
+ DDRSS0_PHY_1396_DATA
+ DDRSS0_PHY_1397_DATA
+ DDRSS0_PHY_1398_DATA
+ DDRSS0_PHY_1399_DATA
+ DDRSS0_PHY_1400_DATA
+ DDRSS0_PHY_1401_DATA
+ DDRSS0_PHY_1402_DATA
+ DDRSS0_PHY_1403_DATA
+ DDRSS0_PHY_1404_DATA
+ DDRSS0_PHY_1405_DATA
+ DDRSS0_PHY_1406_DATA
+ DDRSS0_PHY_1407_DATA
+ DDRSS0_PHY_1408_DATA
+ DDRSS0_PHY_1409_DATA
+ DDRSS0_PHY_1410_DATA
+ DDRSS0_PHY_1411_DATA
+ DDRSS0_PHY_1412_DATA
+ DDRSS0_PHY_1413_DATA
+ DDRSS0_PHY_1414_DATA
+ DDRSS0_PHY_1415_DATA
+ DDRSS0_PHY_1416_DATA
+ DDRSS0_PHY_1417_DATA
+ DDRSS0_PHY_1418_DATA
+ DDRSS0_PHY_1419_DATA
+ DDRSS0_PHY_1420_DATA
+ DDRSS0_PHY_1421_DATA
+ DDRSS0_PHY_1422_DATA
+ >;
+ };
+
+ memorycontroller1: memorycontroller@29b0000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x029b0000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>;
+ reg-names = "cfg", "ctrl_mmr_lp4";
+ power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>,
+ <&k3_pds 97 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 139 0>, <&k3_clks 43 2>;
+ ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+ ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+ ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+ ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+ instance = <1>;
+
+ u-boot,dm-spl;
+
+ ti,ctl-data = <
+ DDRSS1_CTL_00_DATA
+ DDRSS1_CTL_01_DATA
+ DDRSS1_CTL_02_DATA
+ DDRSS1_CTL_03_DATA
+ DDRSS1_CTL_04_DATA
+ DDRSS1_CTL_05_DATA
+ DDRSS1_CTL_06_DATA
+ DDRSS1_CTL_07_DATA
+ DDRSS1_CTL_08_DATA
+ DDRSS1_CTL_09_DATA
+ DDRSS1_CTL_10_DATA
+ DDRSS1_CTL_11_DATA
+ DDRSS1_CTL_12_DATA
+ DDRSS1_CTL_13_DATA
+ DDRSS1_CTL_14_DATA
+ DDRSS1_CTL_15_DATA
+ DDRSS1_CTL_16_DATA
+ DDRSS1_CTL_17_DATA
+ DDRSS1_CTL_18_DATA
+ DDRSS1_CTL_19_DATA
+ DDRSS1_CTL_20_DATA
+ DDRSS1_CTL_21_DATA
+ DDRSS1_CTL_22_DATA
+ DDRSS1_CTL_23_DATA
+ DDRSS1_CTL_24_DATA
+ DDRSS1_CTL_25_DATA
+ DDRSS1_CTL_26_DATA
+ DDRSS1_CTL_27_DATA
+ DDRSS1_CTL_28_DATA
+ DDRSS1_CTL_29_DATA
+ DDRSS1_CTL_30_DATA
+ DDRSS1_CTL_31_DATA
+ DDRSS1_CTL_32_DATA
+ DDRSS1_CTL_33_DATA
+ DDRSS1_CTL_34_DATA
+ DDRSS1_CTL_35_DATA
+ DDRSS1_CTL_36_DATA
+ DDRSS1_CTL_37_DATA
+ DDRSS1_CTL_38_DATA
+ DDRSS1_CTL_39_DATA
+ DDRSS1_CTL_40_DATA
+ DDRSS1_CTL_41_DATA
+ DDRSS1_CTL_42_DATA
+ DDRSS1_CTL_43_DATA
+ DDRSS1_CTL_44_DATA
+ DDRSS1_CTL_45_DATA
+ DDRSS1_CTL_46_DATA
+ DDRSS1_CTL_47_DATA
+ DDRSS1_CTL_48_DATA
+ DDRSS1_CTL_49_DATA
+ DDRSS1_CTL_50_DATA
+ DDRSS1_CTL_51_DATA
+ DDRSS1_CTL_52_DATA
+ DDRSS1_CTL_53_DATA
+ DDRSS1_CTL_54_DATA
+ DDRSS1_CTL_55_DATA
+ DDRSS1_CTL_56_DATA
+ DDRSS1_CTL_57_DATA
+ DDRSS1_CTL_58_DATA
+ DDRSS1_CTL_59_DATA
+ DDRSS1_CTL_60_DATA
+ DDRSS1_CTL_61_DATA
+ DDRSS1_CTL_62_DATA
+ DDRSS1_CTL_63_DATA
+ DDRSS1_CTL_64_DATA
+ DDRSS1_CTL_65_DATA
+ DDRSS1_CTL_66_DATA
+ DDRSS1_CTL_67_DATA
+ DDRSS1_CTL_68_DATA
+ DDRSS1_CTL_69_DATA
+ DDRSS1_CTL_70_DATA
+ DDRSS1_CTL_71_DATA
+ DDRSS1_CTL_72_DATA
+ DDRSS1_CTL_73_DATA
+ DDRSS1_CTL_74_DATA
+ DDRSS1_CTL_75_DATA
+ DDRSS1_CTL_76_DATA
+ DDRSS1_CTL_77_DATA
+ DDRSS1_CTL_78_DATA
+ DDRSS1_CTL_79_DATA
+ DDRSS1_CTL_80_DATA
+ DDRSS1_CTL_81_DATA
+ DDRSS1_CTL_82_DATA
+ DDRSS1_CTL_83_DATA
+ DDRSS1_CTL_84_DATA
+ DDRSS1_CTL_85_DATA
+ DDRSS1_CTL_86_DATA
+ DDRSS1_CTL_87_DATA
+ DDRSS1_CTL_88_DATA
+ DDRSS1_CTL_89_DATA
+ DDRSS1_CTL_90_DATA
+ DDRSS1_CTL_91_DATA
+ DDRSS1_CTL_92_DATA
+ DDRSS1_CTL_93_DATA
+ DDRSS1_CTL_94_DATA
+ DDRSS1_CTL_95_DATA
+ DDRSS1_CTL_96_DATA
+ DDRSS1_CTL_97_DATA
+ DDRSS1_CTL_98_DATA
+ DDRSS1_CTL_99_DATA
+ DDRSS1_CTL_100_DATA
+ DDRSS1_CTL_101_DATA
+ DDRSS1_CTL_102_DATA
+ DDRSS1_CTL_103_DATA
+ DDRSS1_CTL_104_DATA
+ DDRSS1_CTL_105_DATA
+ DDRSS1_CTL_106_DATA
+ DDRSS1_CTL_107_DATA
+ DDRSS1_CTL_108_DATA
+ DDRSS1_CTL_109_DATA
+ DDRSS1_CTL_110_DATA
+ DDRSS1_CTL_111_DATA
+ DDRSS1_CTL_112_DATA
+ DDRSS1_CTL_113_DATA
+ DDRSS1_CTL_114_DATA
+ DDRSS1_CTL_115_DATA
+ DDRSS1_CTL_116_DATA
+ DDRSS1_CTL_117_DATA
+ DDRSS1_CTL_118_DATA
+ DDRSS1_CTL_119_DATA
+ DDRSS1_CTL_120_DATA
+ DDRSS1_CTL_121_DATA
+ DDRSS1_CTL_122_DATA
+ DDRSS1_CTL_123_DATA
+ DDRSS1_CTL_124_DATA
+ DDRSS1_CTL_125_DATA
+ DDRSS1_CTL_126_DATA
+ DDRSS1_CTL_127_DATA
+ DDRSS1_CTL_128_DATA
+ DDRSS1_CTL_129_DATA
+ DDRSS1_CTL_130_DATA
+ DDRSS1_CTL_131_DATA
+ DDRSS1_CTL_132_DATA
+ DDRSS1_CTL_133_DATA
+ DDRSS1_CTL_134_DATA
+ DDRSS1_CTL_135_DATA
+ DDRSS1_CTL_136_DATA
+ DDRSS1_CTL_137_DATA
+ DDRSS1_CTL_138_DATA
+ DDRSS1_CTL_139_DATA
+ DDRSS1_CTL_140_DATA
+ DDRSS1_CTL_141_DATA
+ DDRSS1_CTL_142_DATA
+ DDRSS1_CTL_143_DATA
+ DDRSS1_CTL_144_DATA
+ DDRSS1_CTL_145_DATA
+ DDRSS1_CTL_146_DATA
+ DDRSS1_CTL_147_DATA
+ DDRSS1_CTL_148_DATA
+ DDRSS1_CTL_149_DATA
+ DDRSS1_CTL_150_DATA
+ DDRSS1_CTL_151_DATA
+ DDRSS1_CTL_152_DATA
+ DDRSS1_CTL_153_DATA
+ DDRSS1_CTL_154_DATA
+ DDRSS1_CTL_155_DATA
+ DDRSS1_CTL_156_DATA
+ DDRSS1_CTL_157_DATA
+ DDRSS1_CTL_158_DATA
+ DDRSS1_CTL_159_DATA
+ DDRSS1_CTL_160_DATA
+ DDRSS1_CTL_161_DATA
+ DDRSS1_CTL_162_DATA
+ DDRSS1_CTL_163_DATA
+ DDRSS1_CTL_164_DATA
+ DDRSS1_CTL_165_DATA
+ DDRSS1_CTL_166_DATA
+ DDRSS1_CTL_167_DATA
+ DDRSS1_CTL_168_DATA
+ DDRSS1_CTL_169_DATA
+ DDRSS1_CTL_170_DATA
+ DDRSS1_CTL_171_DATA
+ DDRSS1_CTL_172_DATA
+ DDRSS1_CTL_173_DATA
+ DDRSS1_CTL_174_DATA
+ DDRSS1_CTL_175_DATA
+ DDRSS1_CTL_176_DATA
+ DDRSS1_CTL_177_DATA
+ DDRSS1_CTL_178_DATA
+ DDRSS1_CTL_179_DATA
+ DDRSS1_CTL_180_DATA
+ DDRSS1_CTL_181_DATA
+ DDRSS1_CTL_182_DATA
+ DDRSS1_CTL_183_DATA
+ DDRSS1_CTL_184_DATA
+ DDRSS1_CTL_185_DATA
+ DDRSS1_CTL_186_DATA
+ DDRSS1_CTL_187_DATA
+ DDRSS1_CTL_188_DATA
+ DDRSS1_CTL_189_DATA
+ DDRSS1_CTL_190_DATA
+ DDRSS1_CTL_191_DATA
+ DDRSS1_CTL_192_DATA
+ DDRSS1_CTL_193_DATA
+ DDRSS1_CTL_194_DATA
+ DDRSS1_CTL_195_DATA
+ DDRSS1_CTL_196_DATA
+ DDRSS1_CTL_197_DATA
+ DDRSS1_CTL_198_DATA
+ DDRSS1_CTL_199_DATA
+ DDRSS1_CTL_200_DATA
+ DDRSS1_CTL_201_DATA
+ DDRSS1_CTL_202_DATA
+ DDRSS1_CTL_203_DATA
+ DDRSS1_CTL_204_DATA
+ DDRSS1_CTL_205_DATA
+ DDRSS1_CTL_206_DATA
+ DDRSS1_CTL_207_DATA
+ DDRSS1_CTL_208_DATA
+ DDRSS1_CTL_209_DATA
+ DDRSS1_CTL_210_DATA
+ DDRSS1_CTL_211_DATA
+ DDRSS1_CTL_212_DATA
+ DDRSS1_CTL_213_DATA
+ DDRSS1_CTL_214_DATA
+ DDRSS1_CTL_215_DATA
+ DDRSS1_CTL_216_DATA
+ DDRSS1_CTL_217_DATA
+ DDRSS1_CTL_218_DATA
+ DDRSS1_CTL_219_DATA
+ DDRSS1_CTL_220_DATA
+ DDRSS1_CTL_221_DATA
+ DDRSS1_CTL_222_DATA
+ DDRSS1_CTL_223_DATA
+ DDRSS1_CTL_224_DATA
+ DDRSS1_CTL_225_DATA
+ DDRSS1_CTL_226_DATA
+ DDRSS1_CTL_227_DATA
+ DDRSS1_CTL_228_DATA
+ DDRSS1_CTL_229_DATA
+ DDRSS1_CTL_230_DATA
+ DDRSS1_CTL_231_DATA
+ DDRSS1_CTL_232_DATA
+ DDRSS1_CTL_233_DATA
+ DDRSS1_CTL_234_DATA
+ DDRSS1_CTL_235_DATA
+ DDRSS1_CTL_236_DATA
+ DDRSS1_CTL_237_DATA
+ DDRSS1_CTL_238_DATA
+ DDRSS1_CTL_239_DATA
+ DDRSS1_CTL_240_DATA
+ DDRSS1_CTL_241_DATA
+ DDRSS1_CTL_242_DATA
+ DDRSS1_CTL_243_DATA
+ DDRSS1_CTL_244_DATA
+ DDRSS1_CTL_245_DATA
+ DDRSS1_CTL_246_DATA
+ DDRSS1_CTL_247_DATA
+ DDRSS1_CTL_248_DATA
+ DDRSS1_CTL_249_DATA
+ DDRSS1_CTL_250_DATA
+ DDRSS1_CTL_251_DATA
+ DDRSS1_CTL_252_DATA
+ DDRSS1_CTL_253_DATA
+ DDRSS1_CTL_254_DATA
+ DDRSS1_CTL_255_DATA
+ DDRSS1_CTL_256_DATA
+ DDRSS1_CTL_257_DATA
+ DDRSS1_CTL_258_DATA
+ DDRSS1_CTL_259_DATA
+ DDRSS1_CTL_260_DATA
+ DDRSS1_CTL_261_DATA
+ DDRSS1_CTL_262_DATA
+ DDRSS1_CTL_263_DATA
+ DDRSS1_CTL_264_DATA
+ DDRSS1_CTL_265_DATA
+ DDRSS1_CTL_266_DATA
+ DDRSS1_CTL_267_DATA
+ DDRSS1_CTL_268_DATA
+ DDRSS1_CTL_269_DATA
+ DDRSS1_CTL_270_DATA
+ DDRSS1_CTL_271_DATA
+ DDRSS1_CTL_272_DATA
+ DDRSS1_CTL_273_DATA
+ DDRSS1_CTL_274_DATA
+ DDRSS1_CTL_275_DATA
+ DDRSS1_CTL_276_DATA
+ DDRSS1_CTL_277_DATA
+ DDRSS1_CTL_278_DATA
+ DDRSS1_CTL_279_DATA
+ DDRSS1_CTL_280_DATA
+ DDRSS1_CTL_281_DATA
+ DDRSS1_CTL_282_DATA
+ DDRSS1_CTL_283_DATA
+ DDRSS1_CTL_284_DATA
+ DDRSS1_CTL_285_DATA
+ DDRSS1_CTL_286_DATA
+ DDRSS1_CTL_287_DATA
+ DDRSS1_CTL_288_DATA
+ DDRSS1_CTL_289_DATA
+ DDRSS1_CTL_290_DATA
+ DDRSS1_CTL_291_DATA
+ DDRSS1_CTL_292_DATA
+ DDRSS1_CTL_293_DATA
+ DDRSS1_CTL_294_DATA
+ DDRSS1_CTL_295_DATA
+ DDRSS1_CTL_296_DATA
+ DDRSS1_CTL_297_DATA
+ DDRSS1_CTL_298_DATA
+ DDRSS1_CTL_299_DATA
+ DDRSS1_CTL_300_DATA
+ DDRSS1_CTL_301_DATA
+ DDRSS1_CTL_302_DATA
+ DDRSS1_CTL_303_DATA
+ DDRSS1_CTL_304_DATA
+ DDRSS1_CTL_305_DATA
+ DDRSS1_CTL_306_DATA
+ DDRSS1_CTL_307_DATA
+ DDRSS1_CTL_308_DATA
+ DDRSS1_CTL_309_DATA
+ DDRSS1_CTL_310_DATA
+ DDRSS1_CTL_311_DATA
+ DDRSS1_CTL_312_DATA
+ DDRSS1_CTL_313_DATA
+ DDRSS1_CTL_314_DATA
+ DDRSS1_CTL_315_DATA
+ DDRSS1_CTL_316_DATA
+ DDRSS1_CTL_317_DATA
+ DDRSS1_CTL_318_DATA
+ DDRSS1_CTL_319_DATA
+ DDRSS1_CTL_320_DATA
+ DDRSS1_CTL_321_DATA
+ DDRSS1_CTL_322_DATA
+ DDRSS1_CTL_323_DATA
+ DDRSS1_CTL_324_DATA
+ DDRSS1_CTL_325_DATA
+ DDRSS1_CTL_326_DATA
+ DDRSS1_CTL_327_DATA
+ DDRSS1_CTL_328_DATA
+ DDRSS1_CTL_329_DATA
+ DDRSS1_CTL_330_DATA
+ DDRSS1_CTL_331_DATA
+ DDRSS1_CTL_332_DATA
+ DDRSS1_CTL_333_DATA
+ DDRSS1_CTL_334_DATA
+ DDRSS1_CTL_335_DATA
+ DDRSS1_CTL_336_DATA
+ DDRSS1_CTL_337_DATA
+ DDRSS1_CTL_338_DATA
+ DDRSS1_CTL_339_DATA
+ DDRSS1_CTL_340_DATA
+ DDRSS1_CTL_341_DATA
+ DDRSS1_CTL_342_DATA
+ DDRSS1_CTL_343_DATA
+ DDRSS1_CTL_344_DATA
+ DDRSS1_CTL_345_DATA
+ DDRSS1_CTL_346_DATA
+ DDRSS1_CTL_347_DATA
+ DDRSS1_CTL_348_DATA
+ DDRSS1_CTL_349_DATA
+ DDRSS1_CTL_350_DATA
+ DDRSS1_CTL_351_DATA
+ DDRSS1_CTL_352_DATA
+ DDRSS1_CTL_353_DATA
+ DDRSS1_CTL_354_DATA
+ DDRSS1_CTL_355_DATA
+ DDRSS1_CTL_356_DATA
+ DDRSS1_CTL_357_DATA
+ DDRSS1_CTL_358_DATA
+ DDRSS1_CTL_359_DATA
+ DDRSS1_CTL_360_DATA
+ DDRSS1_CTL_361_DATA
+ DDRSS1_CTL_362_DATA
+ DDRSS1_CTL_363_DATA
+ DDRSS1_CTL_364_DATA
+ DDRSS1_CTL_365_DATA
+ DDRSS1_CTL_366_DATA
+ DDRSS1_CTL_367_DATA
+ DDRSS1_CTL_368_DATA
+ DDRSS1_CTL_369_DATA
+ DDRSS1_CTL_370_DATA
+ DDRSS1_CTL_371_DATA
+ DDRSS1_CTL_372_DATA
+ DDRSS1_CTL_373_DATA
+ DDRSS1_CTL_374_DATA
+ DDRSS1_CTL_375_DATA
+ DDRSS1_CTL_376_DATA
+ DDRSS1_CTL_377_DATA
+ DDRSS1_CTL_378_DATA
+ DDRSS1_CTL_379_DATA
+ DDRSS1_CTL_380_DATA
+ DDRSS1_CTL_381_DATA
+ DDRSS1_CTL_382_DATA
+ DDRSS1_CTL_383_DATA
+ DDRSS1_CTL_384_DATA
+ DDRSS1_CTL_385_DATA
+ DDRSS1_CTL_386_DATA
+ DDRSS1_CTL_387_DATA
+ DDRSS1_CTL_388_DATA
+ DDRSS1_CTL_389_DATA
+ DDRSS1_CTL_390_DATA
+ DDRSS1_CTL_391_DATA
+ DDRSS1_CTL_392_DATA
+ DDRSS1_CTL_393_DATA
+ DDRSS1_CTL_394_DATA
+ DDRSS1_CTL_395_DATA
+ DDRSS1_CTL_396_DATA
+ DDRSS1_CTL_397_DATA
+ DDRSS1_CTL_398_DATA
+ DDRSS1_CTL_399_DATA
+ DDRSS1_CTL_400_DATA
+ DDRSS1_CTL_401_DATA
+ DDRSS1_CTL_402_DATA
+ DDRSS1_CTL_403_DATA
+ DDRSS1_CTL_404_DATA
+ DDRSS1_CTL_405_DATA
+ DDRSS1_CTL_406_DATA
+ DDRSS1_CTL_407_DATA
+ DDRSS1_CTL_408_DATA
+ DDRSS1_CTL_409_DATA
+ DDRSS1_CTL_410_DATA
+ DDRSS1_CTL_411_DATA
+ DDRSS1_CTL_412_DATA
+ DDRSS1_CTL_413_DATA
+ DDRSS1_CTL_414_DATA
+ DDRSS1_CTL_415_DATA
+ DDRSS1_CTL_416_DATA
+ DDRSS1_CTL_417_DATA
+ DDRSS1_CTL_418_DATA
+ DDRSS1_CTL_419_DATA
+ DDRSS1_CTL_420_DATA
+ DDRSS1_CTL_421_DATA
+ DDRSS1_CTL_422_DATA
+ DDRSS1_CTL_423_DATA
+ DDRSS1_CTL_424_DATA
+ DDRSS1_CTL_425_DATA
+ DDRSS1_CTL_426_DATA
+ DDRSS1_CTL_427_DATA
+ DDRSS1_CTL_428_DATA
+ DDRSS1_CTL_429_DATA
+ DDRSS1_CTL_430_DATA
+ DDRSS1_CTL_431_DATA
+ DDRSS1_CTL_432_DATA
+ DDRSS1_CTL_433_DATA
+ DDRSS1_CTL_434_DATA
+ DDRSS1_CTL_435_DATA
+ DDRSS1_CTL_436_DATA
+ DDRSS1_CTL_437_DATA
+ DDRSS1_CTL_438_DATA
+ DDRSS1_CTL_439_DATA
+ DDRSS1_CTL_440_DATA
+ DDRSS1_CTL_441_DATA
+ DDRSS1_CTL_442_DATA
+ DDRSS1_CTL_443_DATA
+ DDRSS1_CTL_444_DATA
+ DDRSS1_CTL_445_DATA
+ DDRSS1_CTL_446_DATA
+ DDRSS1_CTL_447_DATA
+ DDRSS1_CTL_448_DATA
+ DDRSS1_CTL_449_DATA
+ DDRSS1_CTL_450_DATA
+ DDRSS1_CTL_451_DATA
+ DDRSS1_CTL_452_DATA
+ DDRSS1_CTL_453_DATA
+ DDRSS1_CTL_454_DATA
+ DDRSS1_CTL_455_DATA
+ DDRSS1_CTL_456_DATA
+ DDRSS1_CTL_457_DATA
+ DDRSS1_CTL_458_DATA
+ >;
+
+ ti,pi-data = <
+ DDRSS1_PI_00_DATA
+ DDRSS1_PI_01_DATA
+ DDRSS1_PI_02_DATA
+ DDRSS1_PI_03_DATA
+ DDRSS1_PI_04_DATA
+ DDRSS1_PI_05_DATA
+ DDRSS1_PI_06_DATA
+ DDRSS1_PI_07_DATA
+ DDRSS1_PI_08_DATA
+ DDRSS1_PI_09_DATA
+ DDRSS1_PI_10_DATA
+ DDRSS1_PI_11_DATA
+ DDRSS1_PI_12_DATA
+ DDRSS1_PI_13_DATA
+ DDRSS1_PI_14_DATA
+ DDRSS1_PI_15_DATA
+ DDRSS1_PI_16_DATA
+ DDRSS1_PI_17_DATA
+ DDRSS1_PI_18_DATA
+ DDRSS1_PI_19_DATA
+ DDRSS1_PI_20_DATA
+ DDRSS1_PI_21_DATA
+ DDRSS1_PI_22_DATA
+ DDRSS1_PI_23_DATA
+ DDRSS1_PI_24_DATA
+ DDRSS1_PI_25_DATA
+ DDRSS1_PI_26_DATA
+ DDRSS1_PI_27_DATA
+ DDRSS1_PI_28_DATA
+ DDRSS1_PI_29_DATA
+ DDRSS1_PI_30_DATA
+ DDRSS1_PI_31_DATA
+ DDRSS1_PI_32_DATA
+ DDRSS1_PI_33_DATA
+ DDRSS1_PI_34_DATA
+ DDRSS1_PI_35_DATA
+ DDRSS1_PI_36_DATA
+ DDRSS1_PI_37_DATA
+ DDRSS1_PI_38_DATA
+ DDRSS1_PI_39_DATA
+ DDRSS1_PI_40_DATA
+ DDRSS1_PI_41_DATA
+ DDRSS1_PI_42_DATA
+ DDRSS1_PI_43_DATA
+ DDRSS1_PI_44_DATA
+ DDRSS1_PI_45_DATA
+ DDRSS1_PI_46_DATA
+ DDRSS1_PI_47_DATA
+ DDRSS1_PI_48_DATA
+ DDRSS1_PI_49_DATA
+ DDRSS1_PI_50_DATA
+ DDRSS1_PI_51_DATA
+ DDRSS1_PI_52_DATA
+ DDRSS1_PI_53_DATA
+ DDRSS1_PI_54_DATA
+ DDRSS1_PI_55_DATA
+ DDRSS1_PI_56_DATA
+ DDRSS1_PI_57_DATA
+ DDRSS1_PI_58_DATA
+ DDRSS1_PI_59_DATA
+ DDRSS1_PI_60_DATA
+ DDRSS1_PI_61_DATA
+ DDRSS1_PI_62_DATA
+ DDRSS1_PI_63_DATA
+ DDRSS1_PI_64_DATA
+ DDRSS1_PI_65_DATA
+ DDRSS1_PI_66_DATA
+ DDRSS1_PI_67_DATA
+ DDRSS1_PI_68_DATA
+ DDRSS1_PI_69_DATA
+ DDRSS1_PI_70_DATA
+ DDRSS1_PI_71_DATA
+ DDRSS1_PI_72_DATA
+ DDRSS1_PI_73_DATA
+ DDRSS1_PI_74_DATA
+ DDRSS1_PI_75_DATA
+ DDRSS1_PI_76_DATA
+ DDRSS1_PI_77_DATA
+ DDRSS1_PI_78_DATA
+ DDRSS1_PI_79_DATA
+ DDRSS1_PI_80_DATA
+ DDRSS1_PI_81_DATA
+ DDRSS1_PI_82_DATA
+ DDRSS1_PI_83_DATA
+ DDRSS1_PI_84_DATA
+ DDRSS1_PI_85_DATA
+ DDRSS1_PI_86_DATA
+ DDRSS1_PI_87_DATA
+ DDRSS1_PI_88_DATA
+ DDRSS1_PI_89_DATA
+ DDRSS1_PI_90_DATA
+ DDRSS1_PI_91_DATA
+ DDRSS1_PI_92_DATA
+ DDRSS1_PI_93_DATA
+ DDRSS1_PI_94_DATA
+ DDRSS1_PI_95_DATA
+ DDRSS1_PI_96_DATA
+ DDRSS1_PI_97_DATA
+ DDRSS1_PI_98_DATA
+ DDRSS1_PI_99_DATA
+ DDRSS1_PI_100_DATA
+ DDRSS1_PI_101_DATA
+ DDRSS1_PI_102_DATA
+ DDRSS1_PI_103_DATA
+ DDRSS1_PI_104_DATA
+ DDRSS1_PI_105_DATA
+ DDRSS1_PI_106_DATA
+ DDRSS1_PI_107_DATA
+ DDRSS1_PI_108_DATA
+ DDRSS1_PI_109_DATA
+ DDRSS1_PI_110_DATA
+ DDRSS1_PI_111_DATA
+ DDRSS1_PI_112_DATA
+ DDRSS1_PI_113_DATA
+ DDRSS1_PI_114_DATA
+ DDRSS1_PI_115_DATA
+ DDRSS1_PI_116_DATA
+ DDRSS1_PI_117_DATA
+ DDRSS1_PI_118_DATA
+ DDRSS1_PI_119_DATA
+ DDRSS1_PI_120_DATA
+ DDRSS1_PI_121_DATA
+ DDRSS1_PI_122_DATA
+ DDRSS1_PI_123_DATA
+ DDRSS1_PI_124_DATA
+ DDRSS1_PI_125_DATA
+ DDRSS1_PI_126_DATA
+ DDRSS1_PI_127_DATA
+ DDRSS1_PI_128_DATA
+ DDRSS1_PI_129_DATA
+ DDRSS1_PI_130_DATA
+ DDRSS1_PI_131_DATA
+ DDRSS1_PI_132_DATA
+ DDRSS1_PI_133_DATA
+ DDRSS1_PI_134_DATA
+ DDRSS1_PI_135_DATA
+ DDRSS1_PI_136_DATA
+ DDRSS1_PI_137_DATA
+ DDRSS1_PI_138_DATA
+ DDRSS1_PI_139_DATA
+ DDRSS1_PI_140_DATA
+ DDRSS1_PI_141_DATA
+ DDRSS1_PI_142_DATA
+ DDRSS1_PI_143_DATA
+ DDRSS1_PI_144_DATA
+ DDRSS1_PI_145_DATA
+ DDRSS1_PI_146_DATA
+ DDRSS1_PI_147_DATA
+ DDRSS1_PI_148_DATA
+ DDRSS1_PI_149_DATA
+ DDRSS1_PI_150_DATA
+ DDRSS1_PI_151_DATA
+ DDRSS1_PI_152_DATA
+ DDRSS1_PI_153_DATA
+ DDRSS1_PI_154_DATA
+ DDRSS1_PI_155_DATA
+ DDRSS1_PI_156_DATA
+ DDRSS1_PI_157_DATA
+ DDRSS1_PI_158_DATA
+ DDRSS1_PI_159_DATA
+ DDRSS1_PI_160_DATA
+ DDRSS1_PI_161_DATA
+ DDRSS1_PI_162_DATA
+ DDRSS1_PI_163_DATA
+ DDRSS1_PI_164_DATA
+ DDRSS1_PI_165_DATA
+ DDRSS1_PI_166_DATA
+ DDRSS1_PI_167_DATA
+ DDRSS1_PI_168_DATA
+ DDRSS1_PI_169_DATA
+ DDRSS1_PI_170_DATA
+ DDRSS1_PI_171_DATA
+ DDRSS1_PI_172_DATA
+ DDRSS1_PI_173_DATA
+ DDRSS1_PI_174_DATA
+ DDRSS1_PI_175_DATA
+ DDRSS1_PI_176_DATA
+ DDRSS1_PI_177_DATA
+ DDRSS1_PI_178_DATA
+ DDRSS1_PI_179_DATA
+ DDRSS1_PI_180_DATA
+ DDRSS1_PI_181_DATA
+ DDRSS1_PI_182_DATA
+ DDRSS1_PI_183_DATA
+ DDRSS1_PI_184_DATA
+ DDRSS1_PI_185_DATA
+ DDRSS1_PI_186_DATA
+ DDRSS1_PI_187_DATA
+ DDRSS1_PI_188_DATA
+ DDRSS1_PI_189_DATA
+ DDRSS1_PI_190_DATA
+ DDRSS1_PI_191_DATA
+ DDRSS1_PI_192_DATA
+ DDRSS1_PI_193_DATA
+ DDRSS1_PI_194_DATA
+ DDRSS1_PI_195_DATA
+ DDRSS1_PI_196_DATA
+ DDRSS1_PI_197_DATA
+ DDRSS1_PI_198_DATA
+ DDRSS1_PI_199_DATA
+ DDRSS1_PI_200_DATA
+ DDRSS1_PI_201_DATA
+ DDRSS1_PI_202_DATA
+ DDRSS1_PI_203_DATA
+ DDRSS1_PI_204_DATA
+ DDRSS1_PI_205_DATA
+ DDRSS1_PI_206_DATA
+ DDRSS1_PI_207_DATA
+ DDRSS1_PI_208_DATA
+ DDRSS1_PI_209_DATA
+ DDRSS1_PI_210_DATA
+ DDRSS1_PI_211_DATA
+ DDRSS1_PI_212_DATA
+ DDRSS1_PI_213_DATA
+ DDRSS1_PI_214_DATA
+ DDRSS1_PI_215_DATA
+ DDRSS1_PI_216_DATA
+ DDRSS1_PI_217_DATA
+ DDRSS1_PI_218_DATA
+ DDRSS1_PI_219_DATA
+ DDRSS1_PI_220_DATA
+ DDRSS1_PI_221_DATA
+ DDRSS1_PI_222_DATA
+ DDRSS1_PI_223_DATA
+ DDRSS1_PI_224_DATA
+ DDRSS1_PI_225_DATA
+ DDRSS1_PI_226_DATA
+ DDRSS1_PI_227_DATA
+ DDRSS1_PI_228_DATA
+ DDRSS1_PI_229_DATA
+ DDRSS1_PI_230_DATA
+ DDRSS1_PI_231_DATA
+ DDRSS1_PI_232_DATA
+ DDRSS1_PI_233_DATA
+ DDRSS1_PI_234_DATA
+ DDRSS1_PI_235_DATA
+ DDRSS1_PI_236_DATA
+ DDRSS1_PI_237_DATA
+ DDRSS1_PI_238_DATA
+ DDRSS1_PI_239_DATA
+ DDRSS1_PI_240_DATA
+ DDRSS1_PI_241_DATA
+ DDRSS1_PI_242_DATA
+ DDRSS1_PI_243_DATA
+ DDRSS1_PI_244_DATA
+ DDRSS1_PI_245_DATA
+ DDRSS1_PI_246_DATA
+ DDRSS1_PI_247_DATA
+ DDRSS1_PI_248_DATA
+ DDRSS1_PI_249_DATA
+ DDRSS1_PI_250_DATA
+ DDRSS1_PI_251_DATA
+ DDRSS1_PI_252_DATA
+ DDRSS1_PI_253_DATA
+ DDRSS1_PI_254_DATA
+ DDRSS1_PI_255_DATA
+ DDRSS1_PI_256_DATA
+ DDRSS1_PI_257_DATA
+ DDRSS1_PI_258_DATA
+ DDRSS1_PI_259_DATA
+ DDRSS1_PI_260_DATA
+ DDRSS1_PI_261_DATA
+ DDRSS1_PI_262_DATA
+ DDRSS1_PI_263_DATA
+ DDRSS1_PI_264_DATA
+ DDRSS1_PI_265_DATA
+ DDRSS1_PI_266_DATA
+ DDRSS1_PI_267_DATA
+ DDRSS1_PI_268_DATA
+ DDRSS1_PI_269_DATA
+ DDRSS1_PI_270_DATA
+ DDRSS1_PI_271_DATA
+ DDRSS1_PI_272_DATA
+ DDRSS1_PI_273_DATA
+ DDRSS1_PI_274_DATA
+ DDRSS1_PI_275_DATA
+ DDRSS1_PI_276_DATA
+ DDRSS1_PI_277_DATA
+ DDRSS1_PI_278_DATA
+ DDRSS1_PI_279_DATA
+ DDRSS1_PI_280_DATA
+ DDRSS1_PI_281_DATA
+ DDRSS1_PI_282_DATA
+ DDRSS1_PI_283_DATA
+ DDRSS1_PI_284_DATA
+ DDRSS1_PI_285_DATA
+ DDRSS1_PI_286_DATA
+ DDRSS1_PI_287_DATA
+ DDRSS1_PI_288_DATA
+ DDRSS1_PI_289_DATA
+ DDRSS1_PI_290_DATA
+ DDRSS1_PI_291_DATA
+ DDRSS1_PI_292_DATA
+ DDRSS1_PI_293_DATA
+ DDRSS1_PI_294_DATA
+ DDRSS1_PI_295_DATA
+ DDRSS1_PI_296_DATA
+ DDRSS1_PI_297_DATA
+ DDRSS1_PI_298_DATA
+ DDRSS1_PI_299_DATA
+ >;
+
+ ti,phy-data = <
+ DDRSS1_PHY_00_DATA
+ DDRSS1_PHY_01_DATA
+ DDRSS1_PHY_02_DATA
+ DDRSS1_PHY_03_DATA
+ DDRSS1_PHY_04_DATA
+ DDRSS1_PHY_05_DATA
+ DDRSS1_PHY_06_DATA
+ DDRSS1_PHY_07_DATA
+ DDRSS1_PHY_08_DATA
+ DDRSS1_PHY_09_DATA
+ DDRSS1_PHY_10_DATA
+ DDRSS1_PHY_11_DATA
+ DDRSS1_PHY_12_DATA
+ DDRSS1_PHY_13_DATA
+ DDRSS1_PHY_14_DATA
+ DDRSS1_PHY_15_DATA
+ DDRSS1_PHY_16_DATA
+ DDRSS1_PHY_17_DATA
+ DDRSS1_PHY_18_DATA
+ DDRSS1_PHY_19_DATA
+ DDRSS1_PHY_20_DATA
+ DDRSS1_PHY_21_DATA
+ DDRSS1_PHY_22_DATA
+ DDRSS1_PHY_23_DATA
+ DDRSS1_PHY_24_DATA
+ DDRSS1_PHY_25_DATA
+ DDRSS1_PHY_26_DATA
+ DDRSS1_PHY_27_DATA
+ DDRSS1_PHY_28_DATA
+ DDRSS1_PHY_29_DATA
+ DDRSS1_PHY_30_DATA
+ DDRSS1_PHY_31_DATA
+ DDRSS1_PHY_32_DATA
+ DDRSS1_PHY_33_DATA
+ DDRSS1_PHY_34_DATA
+ DDRSS1_PHY_35_DATA
+ DDRSS1_PHY_36_DATA
+ DDRSS1_PHY_37_DATA
+ DDRSS1_PHY_38_DATA
+ DDRSS1_PHY_39_DATA
+ DDRSS1_PHY_40_DATA
+ DDRSS1_PHY_41_DATA
+ DDRSS1_PHY_42_DATA
+ DDRSS1_PHY_43_DATA
+ DDRSS1_PHY_44_DATA
+ DDRSS1_PHY_45_DATA
+ DDRSS1_PHY_46_DATA
+ DDRSS1_PHY_47_DATA
+ DDRSS1_PHY_48_DATA
+ DDRSS1_PHY_49_DATA
+ DDRSS1_PHY_50_DATA
+ DDRSS1_PHY_51_DATA
+ DDRSS1_PHY_52_DATA
+ DDRSS1_PHY_53_DATA
+ DDRSS1_PHY_54_DATA
+ DDRSS1_PHY_55_DATA
+ DDRSS1_PHY_56_DATA
+ DDRSS1_PHY_57_DATA
+ DDRSS1_PHY_58_DATA
+ DDRSS1_PHY_59_DATA
+ DDRSS1_PHY_60_DATA
+ DDRSS1_PHY_61_DATA
+ DDRSS1_PHY_62_DATA
+ DDRSS1_PHY_63_DATA
+ DDRSS1_PHY_64_DATA
+ DDRSS1_PHY_65_DATA
+ DDRSS1_PHY_66_DATA
+ DDRSS1_PHY_67_DATA
+ DDRSS1_PHY_68_DATA
+ DDRSS1_PHY_69_DATA
+ DDRSS1_PHY_70_DATA
+ DDRSS1_PHY_71_DATA
+ DDRSS1_PHY_72_DATA
+ DDRSS1_PHY_73_DATA
+ DDRSS1_PHY_74_DATA
+ DDRSS1_PHY_75_DATA
+ DDRSS1_PHY_76_DATA
+ DDRSS1_PHY_77_DATA
+ DDRSS1_PHY_78_DATA
+ DDRSS1_PHY_79_DATA
+ DDRSS1_PHY_80_DATA
+ DDRSS1_PHY_81_DATA
+ DDRSS1_PHY_82_DATA
+ DDRSS1_PHY_83_DATA
+ DDRSS1_PHY_84_DATA
+ DDRSS1_PHY_85_DATA
+ DDRSS1_PHY_86_DATA
+ DDRSS1_PHY_87_DATA
+ DDRSS1_PHY_88_DATA
+ DDRSS1_PHY_89_DATA
+ DDRSS1_PHY_90_DATA
+ DDRSS1_PHY_91_DATA
+ DDRSS1_PHY_92_DATA
+ DDRSS1_PHY_93_DATA
+ DDRSS1_PHY_94_DATA
+ DDRSS1_PHY_95_DATA
+ DDRSS1_PHY_96_DATA
+ DDRSS1_PHY_97_DATA
+ DDRSS1_PHY_98_DATA
+ DDRSS1_PHY_99_DATA
+ DDRSS1_PHY_100_DATA
+ DDRSS1_PHY_101_DATA
+ DDRSS1_PHY_102_DATA
+ DDRSS1_PHY_103_DATA
+ DDRSS1_PHY_104_DATA
+ DDRSS1_PHY_105_DATA
+ DDRSS1_PHY_106_DATA
+ DDRSS1_PHY_107_DATA
+ DDRSS1_PHY_108_DATA
+ DDRSS1_PHY_109_DATA
+ DDRSS1_PHY_110_DATA
+ DDRSS1_PHY_111_DATA
+ DDRSS1_PHY_112_DATA
+ DDRSS1_PHY_113_DATA
+ DDRSS1_PHY_114_DATA
+ DDRSS1_PHY_115_DATA
+ DDRSS1_PHY_116_DATA
+ DDRSS1_PHY_117_DATA
+ DDRSS1_PHY_118_DATA
+ DDRSS1_PHY_119_DATA
+ DDRSS1_PHY_120_DATA
+ DDRSS1_PHY_121_DATA
+ DDRSS1_PHY_122_DATA
+ DDRSS1_PHY_123_DATA
+ DDRSS1_PHY_124_DATA
+ DDRSS1_PHY_125_DATA
+ DDRSS1_PHY_126_DATA
+ DDRSS1_PHY_127_DATA
+ DDRSS1_PHY_128_DATA
+ DDRSS1_PHY_129_DATA
+ DDRSS1_PHY_130_DATA
+ DDRSS1_PHY_131_DATA
+ DDRSS1_PHY_132_DATA
+ DDRSS1_PHY_133_DATA
+ DDRSS1_PHY_134_DATA
+ DDRSS1_PHY_135_DATA
+ DDRSS1_PHY_136_DATA
+ DDRSS1_PHY_137_DATA
+ DDRSS1_PHY_138_DATA
+ DDRSS1_PHY_139_DATA
+ DDRSS1_PHY_140_DATA
+ DDRSS1_PHY_141_DATA
+ DDRSS1_PHY_142_DATA
+ DDRSS1_PHY_143_DATA
+ DDRSS1_PHY_144_DATA
+ DDRSS1_PHY_145_DATA
+ DDRSS1_PHY_146_DATA
+ DDRSS1_PHY_147_DATA
+ DDRSS1_PHY_148_DATA
+ DDRSS1_PHY_149_DATA
+ DDRSS1_PHY_150_DATA
+ DDRSS1_PHY_151_DATA
+ DDRSS1_PHY_152_DATA
+ DDRSS1_PHY_153_DATA
+ DDRSS1_PHY_154_DATA
+ DDRSS1_PHY_155_DATA
+ DDRSS1_PHY_156_DATA
+ DDRSS1_PHY_157_DATA
+ DDRSS1_PHY_158_DATA
+ DDRSS1_PHY_159_DATA
+ DDRSS1_PHY_160_DATA
+ DDRSS1_PHY_161_DATA
+ DDRSS1_PHY_162_DATA
+ DDRSS1_PHY_163_DATA
+ DDRSS1_PHY_164_DATA
+ DDRSS1_PHY_165_DATA
+ DDRSS1_PHY_166_DATA
+ DDRSS1_PHY_167_DATA
+ DDRSS1_PHY_168_DATA
+ DDRSS1_PHY_169_DATA
+ DDRSS1_PHY_170_DATA
+ DDRSS1_PHY_171_DATA
+ DDRSS1_PHY_172_DATA
+ DDRSS1_PHY_173_DATA
+ DDRSS1_PHY_174_DATA
+ DDRSS1_PHY_175_DATA
+ DDRSS1_PHY_176_DATA
+ DDRSS1_PHY_177_DATA
+ DDRSS1_PHY_178_DATA
+ DDRSS1_PHY_179_DATA
+ DDRSS1_PHY_180_DATA
+ DDRSS1_PHY_181_DATA
+ DDRSS1_PHY_182_DATA
+ DDRSS1_PHY_183_DATA
+ DDRSS1_PHY_184_DATA
+ DDRSS1_PHY_185_DATA
+ DDRSS1_PHY_186_DATA
+ DDRSS1_PHY_187_DATA
+ DDRSS1_PHY_188_DATA
+ DDRSS1_PHY_189_DATA
+ DDRSS1_PHY_190_DATA
+ DDRSS1_PHY_191_DATA
+ DDRSS1_PHY_192_DATA
+ DDRSS1_PHY_193_DATA
+ DDRSS1_PHY_194_DATA
+ DDRSS1_PHY_195_DATA
+ DDRSS1_PHY_196_DATA
+ DDRSS1_PHY_197_DATA
+ DDRSS1_PHY_198_DATA
+ DDRSS1_PHY_199_DATA
+ DDRSS1_PHY_200_DATA
+ DDRSS1_PHY_201_DATA
+ DDRSS1_PHY_202_DATA
+ DDRSS1_PHY_203_DATA
+ DDRSS1_PHY_204_DATA
+ DDRSS1_PHY_205_DATA
+ DDRSS1_PHY_206_DATA
+ DDRSS1_PHY_207_DATA
+ DDRSS1_PHY_208_DATA
+ DDRSS1_PHY_209_DATA
+ DDRSS1_PHY_210_DATA
+ DDRSS1_PHY_211_DATA
+ DDRSS1_PHY_212_DATA
+ DDRSS1_PHY_213_DATA
+ DDRSS1_PHY_214_DATA
+ DDRSS1_PHY_215_DATA
+ DDRSS1_PHY_216_DATA
+ DDRSS1_PHY_217_DATA
+ DDRSS1_PHY_218_DATA
+ DDRSS1_PHY_219_DATA
+ DDRSS1_PHY_220_DATA
+ DDRSS1_PHY_221_DATA
+ DDRSS1_PHY_222_DATA
+ DDRSS1_PHY_223_DATA
+ DDRSS1_PHY_224_DATA
+ DDRSS1_PHY_225_DATA
+ DDRSS1_PHY_226_DATA
+ DDRSS1_PHY_227_DATA
+ DDRSS1_PHY_228_DATA
+ DDRSS1_PHY_229_DATA
+ DDRSS1_PHY_230_DATA
+ DDRSS1_PHY_231_DATA
+ DDRSS1_PHY_232_DATA
+ DDRSS1_PHY_233_DATA
+ DDRSS1_PHY_234_DATA
+ DDRSS1_PHY_235_DATA
+ DDRSS1_PHY_236_DATA
+ DDRSS1_PHY_237_DATA
+ DDRSS1_PHY_238_DATA
+ DDRSS1_PHY_239_DATA
+ DDRSS1_PHY_240_DATA
+ DDRSS1_PHY_241_DATA
+ DDRSS1_PHY_242_DATA
+ DDRSS1_PHY_243_DATA
+ DDRSS1_PHY_244_DATA
+ DDRSS1_PHY_245_DATA
+ DDRSS1_PHY_246_DATA
+ DDRSS1_PHY_247_DATA
+ DDRSS1_PHY_248_DATA
+ DDRSS1_PHY_249_DATA
+ DDRSS1_PHY_250_DATA
+ DDRSS1_PHY_251_DATA
+ DDRSS1_PHY_252_DATA
+ DDRSS1_PHY_253_DATA
+ DDRSS1_PHY_254_DATA
+ DDRSS1_PHY_255_DATA
+ DDRSS1_PHY_256_DATA
+ DDRSS1_PHY_257_DATA
+ DDRSS1_PHY_258_DATA
+ DDRSS1_PHY_259_DATA
+ DDRSS1_PHY_260_DATA
+ DDRSS1_PHY_261_DATA
+ DDRSS1_PHY_262_DATA
+ DDRSS1_PHY_263_DATA
+ DDRSS1_PHY_264_DATA
+ DDRSS1_PHY_265_DATA
+ DDRSS1_PHY_266_DATA
+ DDRSS1_PHY_267_DATA
+ DDRSS1_PHY_268_DATA
+ DDRSS1_PHY_269_DATA
+ DDRSS1_PHY_270_DATA
+ DDRSS1_PHY_271_DATA
+ DDRSS1_PHY_272_DATA
+ DDRSS1_PHY_273_DATA
+ DDRSS1_PHY_274_DATA
+ DDRSS1_PHY_275_DATA
+ DDRSS1_PHY_276_DATA
+ DDRSS1_PHY_277_DATA
+ DDRSS1_PHY_278_DATA
+ DDRSS1_PHY_279_DATA
+ DDRSS1_PHY_280_DATA
+ DDRSS1_PHY_281_DATA
+ DDRSS1_PHY_282_DATA
+ DDRSS1_PHY_283_DATA
+ DDRSS1_PHY_284_DATA
+ DDRSS1_PHY_285_DATA
+ DDRSS1_PHY_286_DATA
+ DDRSS1_PHY_287_DATA
+ DDRSS1_PHY_288_DATA
+ DDRSS1_PHY_289_DATA
+ DDRSS1_PHY_290_DATA
+ DDRSS1_PHY_291_DATA
+ DDRSS1_PHY_292_DATA
+ DDRSS1_PHY_293_DATA
+ DDRSS1_PHY_294_DATA
+ DDRSS1_PHY_295_DATA
+ DDRSS1_PHY_296_DATA
+ DDRSS1_PHY_297_DATA
+ DDRSS1_PHY_298_DATA
+ DDRSS1_PHY_299_DATA
+ DDRSS1_PHY_300_DATA
+ DDRSS1_PHY_301_DATA
+ DDRSS1_PHY_302_DATA
+ DDRSS1_PHY_303_DATA
+ DDRSS1_PHY_304_DATA
+ DDRSS1_PHY_305_DATA
+ DDRSS1_PHY_306_DATA
+ DDRSS1_PHY_307_DATA
+ DDRSS1_PHY_308_DATA
+ DDRSS1_PHY_309_DATA
+ DDRSS1_PHY_310_DATA
+ DDRSS1_PHY_311_DATA
+ DDRSS1_PHY_312_DATA
+ DDRSS1_PHY_313_DATA
+ DDRSS1_PHY_314_DATA
+ DDRSS1_PHY_315_DATA
+ DDRSS1_PHY_316_DATA
+ DDRSS1_PHY_317_DATA
+ DDRSS1_PHY_318_DATA
+ DDRSS1_PHY_319_DATA
+ DDRSS1_PHY_320_DATA
+ DDRSS1_PHY_321_DATA
+ DDRSS1_PHY_322_DATA
+ DDRSS1_PHY_323_DATA
+ DDRSS1_PHY_324_DATA
+ DDRSS1_PHY_325_DATA
+ DDRSS1_PHY_326_DATA
+ DDRSS1_PHY_327_DATA
+ DDRSS1_PHY_328_DATA
+ DDRSS1_PHY_329_DATA
+ DDRSS1_PHY_330_DATA
+ DDRSS1_PHY_331_DATA
+ DDRSS1_PHY_332_DATA
+ DDRSS1_PHY_333_DATA
+ DDRSS1_PHY_334_DATA
+ DDRSS1_PHY_335_DATA
+ DDRSS1_PHY_336_DATA
+ DDRSS1_PHY_337_DATA
+ DDRSS1_PHY_338_DATA
+ DDRSS1_PHY_339_DATA
+ DDRSS1_PHY_340_DATA
+ DDRSS1_PHY_341_DATA
+ DDRSS1_PHY_342_DATA
+ DDRSS1_PHY_343_DATA
+ DDRSS1_PHY_344_DATA
+ DDRSS1_PHY_345_DATA
+ DDRSS1_PHY_346_DATA
+ DDRSS1_PHY_347_DATA
+ DDRSS1_PHY_348_DATA
+ DDRSS1_PHY_349_DATA
+ DDRSS1_PHY_350_DATA
+ DDRSS1_PHY_351_DATA
+ DDRSS1_PHY_352_DATA
+ DDRSS1_PHY_353_DATA
+ DDRSS1_PHY_354_DATA
+ DDRSS1_PHY_355_DATA
+ DDRSS1_PHY_356_DATA
+ DDRSS1_PHY_357_DATA
+ DDRSS1_PHY_358_DATA
+ DDRSS1_PHY_359_DATA
+ DDRSS1_PHY_360_DATA
+ DDRSS1_PHY_361_DATA
+ DDRSS1_PHY_362_DATA
+ DDRSS1_PHY_363_DATA
+ DDRSS1_PHY_364_DATA
+ DDRSS1_PHY_365_DATA
+ DDRSS1_PHY_366_DATA
+ DDRSS1_PHY_367_DATA
+ DDRSS1_PHY_368_DATA
+ DDRSS1_PHY_369_DATA
+ DDRSS1_PHY_370_DATA
+ DDRSS1_PHY_371_DATA
+ DDRSS1_PHY_372_DATA
+ DDRSS1_PHY_373_DATA
+ DDRSS1_PHY_374_DATA
+ DDRSS1_PHY_375_DATA
+ DDRSS1_PHY_376_DATA
+ DDRSS1_PHY_377_DATA
+ DDRSS1_PHY_378_DATA
+ DDRSS1_PHY_379_DATA
+ DDRSS1_PHY_380_DATA
+ DDRSS1_PHY_381_DATA
+ DDRSS1_PHY_382_DATA
+ DDRSS1_PHY_383_DATA
+ DDRSS1_PHY_384_DATA
+ DDRSS1_PHY_385_DATA
+ DDRSS1_PHY_386_DATA
+ DDRSS1_PHY_387_DATA
+ DDRSS1_PHY_388_DATA
+ DDRSS1_PHY_389_DATA
+ DDRSS1_PHY_390_DATA
+ DDRSS1_PHY_391_DATA
+ DDRSS1_PHY_392_DATA
+ DDRSS1_PHY_393_DATA
+ DDRSS1_PHY_394_DATA
+ DDRSS1_PHY_395_DATA
+ DDRSS1_PHY_396_DATA
+ DDRSS1_PHY_397_DATA
+ DDRSS1_PHY_398_DATA
+ DDRSS1_PHY_399_DATA
+ DDRSS1_PHY_400_DATA
+ DDRSS1_PHY_401_DATA
+ DDRSS1_PHY_402_DATA
+ DDRSS1_PHY_403_DATA
+ DDRSS1_PHY_404_DATA
+ DDRSS1_PHY_405_DATA
+ DDRSS1_PHY_406_DATA
+ DDRSS1_PHY_407_DATA
+ DDRSS1_PHY_408_DATA
+ DDRSS1_PHY_409_DATA
+ DDRSS1_PHY_410_DATA
+ DDRSS1_PHY_411_DATA
+ DDRSS1_PHY_412_DATA
+ DDRSS1_PHY_413_DATA
+ DDRSS1_PHY_414_DATA
+ DDRSS1_PHY_415_DATA
+ DDRSS1_PHY_416_DATA
+ DDRSS1_PHY_417_DATA
+ DDRSS1_PHY_418_DATA
+ DDRSS1_PHY_419_DATA
+ DDRSS1_PHY_420_DATA
+ DDRSS1_PHY_421_DATA
+ DDRSS1_PHY_422_DATA
+ DDRSS1_PHY_423_DATA
+ DDRSS1_PHY_424_DATA
+ DDRSS1_PHY_425_DATA
+ DDRSS1_PHY_426_DATA
+ DDRSS1_PHY_427_DATA
+ DDRSS1_PHY_428_DATA
+ DDRSS1_PHY_429_DATA
+ DDRSS1_PHY_430_DATA
+ DDRSS1_PHY_431_DATA
+ DDRSS1_PHY_432_DATA
+ DDRSS1_PHY_433_DATA
+ DDRSS1_PHY_434_DATA
+ DDRSS1_PHY_435_DATA
+ DDRSS1_PHY_436_DATA
+ DDRSS1_PHY_437_DATA
+ DDRSS1_PHY_438_DATA
+ DDRSS1_PHY_439_DATA
+ DDRSS1_PHY_440_DATA
+ DDRSS1_PHY_441_DATA
+ DDRSS1_PHY_442_DATA
+ DDRSS1_PHY_443_DATA
+ DDRSS1_PHY_444_DATA
+ DDRSS1_PHY_445_DATA
+ DDRSS1_PHY_446_DATA
+ DDRSS1_PHY_447_DATA
+ DDRSS1_PHY_448_DATA
+ DDRSS1_PHY_449_DATA
+ DDRSS1_PHY_450_DATA
+ DDRSS1_PHY_451_DATA
+ DDRSS1_PHY_452_DATA
+ DDRSS1_PHY_453_DATA
+ DDRSS1_PHY_454_DATA
+ DDRSS1_PHY_455_DATA
+ DDRSS1_PHY_456_DATA
+ DDRSS1_PHY_457_DATA
+ DDRSS1_PHY_458_DATA
+ DDRSS1_PHY_459_DATA
+ DDRSS1_PHY_460_DATA
+ DDRSS1_PHY_461_DATA
+ DDRSS1_PHY_462_DATA
+ DDRSS1_PHY_463_DATA
+ DDRSS1_PHY_464_DATA
+ DDRSS1_PHY_465_DATA
+ DDRSS1_PHY_466_DATA
+ DDRSS1_PHY_467_DATA
+ DDRSS1_PHY_468_DATA
+ DDRSS1_PHY_469_DATA
+ DDRSS1_PHY_470_DATA
+ DDRSS1_PHY_471_DATA
+ DDRSS1_PHY_472_DATA
+ DDRSS1_PHY_473_DATA
+ DDRSS1_PHY_474_DATA
+ DDRSS1_PHY_475_DATA
+ DDRSS1_PHY_476_DATA
+ DDRSS1_PHY_477_DATA
+ DDRSS1_PHY_478_DATA
+ DDRSS1_PHY_479_DATA
+ DDRSS1_PHY_480_DATA
+ DDRSS1_PHY_481_DATA
+ DDRSS1_PHY_482_DATA
+ DDRSS1_PHY_483_DATA
+ DDRSS1_PHY_484_DATA
+ DDRSS1_PHY_485_DATA
+ DDRSS1_PHY_486_DATA
+ DDRSS1_PHY_487_DATA
+ DDRSS1_PHY_488_DATA
+ DDRSS1_PHY_489_DATA
+ DDRSS1_PHY_490_DATA
+ DDRSS1_PHY_491_DATA
+ DDRSS1_PHY_492_DATA
+ DDRSS1_PHY_493_DATA
+ DDRSS1_PHY_494_DATA
+ DDRSS1_PHY_495_DATA
+ DDRSS1_PHY_496_DATA
+ DDRSS1_PHY_497_DATA
+ DDRSS1_PHY_498_DATA
+ DDRSS1_PHY_499_DATA
+ DDRSS1_PHY_500_DATA
+ DDRSS1_PHY_501_DATA
+ DDRSS1_PHY_502_DATA
+ DDRSS1_PHY_503_DATA
+ DDRSS1_PHY_504_DATA
+ DDRSS1_PHY_505_DATA
+ DDRSS1_PHY_506_DATA
+ DDRSS1_PHY_507_DATA
+ DDRSS1_PHY_508_DATA
+ DDRSS1_PHY_509_DATA
+ DDRSS1_PHY_510_DATA
+ DDRSS1_PHY_511_DATA
+ DDRSS1_PHY_512_DATA
+ DDRSS1_PHY_513_DATA
+ DDRSS1_PHY_514_DATA
+ DDRSS1_PHY_515_DATA
+ DDRSS1_PHY_516_DATA
+ DDRSS1_PHY_517_DATA
+ DDRSS1_PHY_518_DATA
+ DDRSS1_PHY_519_DATA
+ DDRSS1_PHY_520_DATA
+ DDRSS1_PHY_521_DATA
+ DDRSS1_PHY_522_DATA
+ DDRSS1_PHY_523_DATA
+ DDRSS1_PHY_524_DATA
+ DDRSS1_PHY_525_DATA
+ DDRSS1_PHY_526_DATA
+ DDRSS1_PHY_527_DATA
+ DDRSS1_PHY_528_DATA
+ DDRSS1_PHY_529_DATA
+ DDRSS1_PHY_530_DATA
+ DDRSS1_PHY_531_DATA
+ DDRSS1_PHY_532_DATA
+ DDRSS1_PHY_533_DATA
+ DDRSS1_PHY_534_DATA
+ DDRSS1_PHY_535_DATA
+ DDRSS1_PHY_536_DATA
+ DDRSS1_PHY_537_DATA
+ DDRSS1_PHY_538_DATA
+ DDRSS1_PHY_539_DATA
+ DDRSS1_PHY_540_DATA
+ DDRSS1_PHY_541_DATA
+ DDRSS1_PHY_542_DATA
+ DDRSS1_PHY_543_DATA
+ DDRSS1_PHY_544_DATA
+ DDRSS1_PHY_545_DATA
+ DDRSS1_PHY_546_DATA
+ DDRSS1_PHY_547_DATA
+ DDRSS1_PHY_548_DATA
+ DDRSS1_PHY_549_DATA
+ DDRSS1_PHY_550_DATA
+ DDRSS1_PHY_551_DATA
+ DDRSS1_PHY_552_DATA
+ DDRSS1_PHY_553_DATA
+ DDRSS1_PHY_554_DATA
+ DDRSS1_PHY_555_DATA
+ DDRSS1_PHY_556_DATA
+ DDRSS1_PHY_557_DATA
+ DDRSS1_PHY_558_DATA
+ DDRSS1_PHY_559_DATA
+ DDRSS1_PHY_560_DATA
+ DDRSS1_PHY_561_DATA
+ DDRSS1_PHY_562_DATA
+ DDRSS1_PHY_563_DATA
+ DDRSS1_PHY_564_DATA
+ DDRSS1_PHY_565_DATA
+ DDRSS1_PHY_566_DATA
+ DDRSS1_PHY_567_DATA
+ DDRSS1_PHY_568_DATA
+ DDRSS1_PHY_569_DATA
+ DDRSS1_PHY_570_DATA
+ DDRSS1_PHY_571_DATA
+ DDRSS1_PHY_572_DATA
+ DDRSS1_PHY_573_DATA
+ DDRSS1_PHY_574_DATA
+ DDRSS1_PHY_575_DATA
+ DDRSS1_PHY_576_DATA
+ DDRSS1_PHY_577_DATA
+ DDRSS1_PHY_578_DATA
+ DDRSS1_PHY_579_DATA
+ DDRSS1_PHY_580_DATA
+ DDRSS1_PHY_581_DATA
+ DDRSS1_PHY_582_DATA
+ DDRSS1_PHY_583_DATA
+ DDRSS1_PHY_584_DATA
+ DDRSS1_PHY_585_DATA
+ DDRSS1_PHY_586_DATA
+ DDRSS1_PHY_587_DATA
+ DDRSS1_PHY_588_DATA
+ DDRSS1_PHY_589_DATA
+ DDRSS1_PHY_590_DATA
+ DDRSS1_PHY_591_DATA
+ DDRSS1_PHY_592_DATA
+ DDRSS1_PHY_593_DATA
+ DDRSS1_PHY_594_DATA
+ DDRSS1_PHY_595_DATA
+ DDRSS1_PHY_596_DATA
+ DDRSS1_PHY_597_DATA
+ DDRSS1_PHY_598_DATA
+ DDRSS1_PHY_599_DATA
+ DDRSS1_PHY_600_DATA
+ DDRSS1_PHY_601_DATA
+ DDRSS1_PHY_602_DATA
+ DDRSS1_PHY_603_DATA
+ DDRSS1_PHY_604_DATA
+ DDRSS1_PHY_605_DATA
+ DDRSS1_PHY_606_DATA
+ DDRSS1_PHY_607_DATA
+ DDRSS1_PHY_608_DATA
+ DDRSS1_PHY_609_DATA
+ DDRSS1_PHY_610_DATA
+ DDRSS1_PHY_611_DATA
+ DDRSS1_PHY_612_DATA
+ DDRSS1_PHY_613_DATA
+ DDRSS1_PHY_614_DATA
+ DDRSS1_PHY_615_DATA
+ DDRSS1_PHY_616_DATA
+ DDRSS1_PHY_617_DATA
+ DDRSS1_PHY_618_DATA
+ DDRSS1_PHY_619_DATA
+ DDRSS1_PHY_620_DATA
+ DDRSS1_PHY_621_DATA
+ DDRSS1_PHY_622_DATA
+ DDRSS1_PHY_623_DATA
+ DDRSS1_PHY_624_DATA
+ DDRSS1_PHY_625_DATA
+ DDRSS1_PHY_626_DATA
+ DDRSS1_PHY_627_DATA
+ DDRSS1_PHY_628_DATA
+ DDRSS1_PHY_629_DATA
+ DDRSS1_PHY_630_DATA
+ DDRSS1_PHY_631_DATA
+ DDRSS1_PHY_632_DATA
+ DDRSS1_PHY_633_DATA
+ DDRSS1_PHY_634_DATA
+ DDRSS1_PHY_635_DATA
+ DDRSS1_PHY_636_DATA
+ DDRSS1_PHY_637_DATA
+ DDRSS1_PHY_638_DATA
+ DDRSS1_PHY_639_DATA
+ DDRSS1_PHY_640_DATA
+ DDRSS1_PHY_641_DATA
+ DDRSS1_PHY_642_DATA
+ DDRSS1_PHY_643_DATA
+ DDRSS1_PHY_644_DATA
+ DDRSS1_PHY_645_DATA
+ DDRSS1_PHY_646_DATA
+ DDRSS1_PHY_647_DATA
+ DDRSS1_PHY_648_DATA
+ DDRSS1_PHY_649_DATA
+ DDRSS1_PHY_650_DATA
+ DDRSS1_PHY_651_DATA
+ DDRSS1_PHY_652_DATA
+ DDRSS1_PHY_653_DATA
+ DDRSS1_PHY_654_DATA
+ DDRSS1_PHY_655_DATA
+ DDRSS1_PHY_656_DATA
+ DDRSS1_PHY_657_DATA
+ DDRSS1_PHY_658_DATA
+ DDRSS1_PHY_659_DATA
+ DDRSS1_PHY_660_DATA
+ DDRSS1_PHY_661_DATA
+ DDRSS1_PHY_662_DATA
+ DDRSS1_PHY_663_DATA
+ DDRSS1_PHY_664_DATA
+ DDRSS1_PHY_665_DATA
+ DDRSS1_PHY_666_DATA
+ DDRSS1_PHY_667_DATA
+ DDRSS1_PHY_668_DATA
+ DDRSS1_PHY_669_DATA
+ DDRSS1_PHY_670_DATA
+ DDRSS1_PHY_671_DATA
+ DDRSS1_PHY_672_DATA
+ DDRSS1_PHY_673_DATA
+ DDRSS1_PHY_674_DATA
+ DDRSS1_PHY_675_DATA
+ DDRSS1_PHY_676_DATA
+ DDRSS1_PHY_677_DATA
+ DDRSS1_PHY_678_DATA
+ DDRSS1_PHY_679_DATA
+ DDRSS1_PHY_680_DATA
+ DDRSS1_PHY_681_DATA
+ DDRSS1_PHY_682_DATA
+ DDRSS1_PHY_683_DATA
+ DDRSS1_PHY_684_DATA
+ DDRSS1_PHY_685_DATA
+ DDRSS1_PHY_686_DATA
+ DDRSS1_PHY_687_DATA
+ DDRSS1_PHY_688_DATA
+ DDRSS1_PHY_689_DATA
+ DDRSS1_PHY_690_DATA
+ DDRSS1_PHY_691_DATA
+ DDRSS1_PHY_692_DATA
+ DDRSS1_PHY_693_DATA
+ DDRSS1_PHY_694_DATA
+ DDRSS1_PHY_695_DATA
+ DDRSS1_PHY_696_DATA
+ DDRSS1_PHY_697_DATA
+ DDRSS1_PHY_698_DATA
+ DDRSS1_PHY_699_DATA
+ DDRSS1_PHY_700_DATA
+ DDRSS1_PHY_701_DATA
+ DDRSS1_PHY_702_DATA
+ DDRSS1_PHY_703_DATA
+ DDRSS1_PHY_704_DATA
+ DDRSS1_PHY_705_DATA
+ DDRSS1_PHY_706_DATA
+ DDRSS1_PHY_707_DATA
+ DDRSS1_PHY_708_DATA
+ DDRSS1_PHY_709_DATA
+ DDRSS1_PHY_710_DATA
+ DDRSS1_PHY_711_DATA
+ DDRSS1_PHY_712_DATA
+ DDRSS1_PHY_713_DATA
+ DDRSS1_PHY_714_DATA
+ DDRSS1_PHY_715_DATA
+ DDRSS1_PHY_716_DATA
+ DDRSS1_PHY_717_DATA
+ DDRSS1_PHY_718_DATA
+ DDRSS1_PHY_719_DATA
+ DDRSS1_PHY_720_DATA
+ DDRSS1_PHY_721_DATA
+ DDRSS1_PHY_722_DATA
+ DDRSS1_PHY_723_DATA
+ DDRSS1_PHY_724_DATA
+ DDRSS1_PHY_725_DATA
+ DDRSS1_PHY_726_DATA
+ DDRSS1_PHY_727_DATA
+ DDRSS1_PHY_728_DATA
+ DDRSS1_PHY_729_DATA
+ DDRSS1_PHY_730_DATA
+ DDRSS1_PHY_731_DATA
+ DDRSS1_PHY_732_DATA
+ DDRSS1_PHY_733_DATA
+ DDRSS1_PHY_734_DATA
+ DDRSS1_PHY_735_DATA
+ DDRSS1_PHY_736_DATA
+ DDRSS1_PHY_737_DATA
+ DDRSS1_PHY_738_DATA
+ DDRSS1_PHY_739_DATA
+ DDRSS1_PHY_740_DATA
+ DDRSS1_PHY_741_DATA
+ DDRSS1_PHY_742_DATA
+ DDRSS1_PHY_743_DATA
+ DDRSS1_PHY_744_DATA
+ DDRSS1_PHY_745_DATA
+ DDRSS1_PHY_746_DATA
+ DDRSS1_PHY_747_DATA
+ DDRSS1_PHY_748_DATA
+ DDRSS1_PHY_749_DATA
+ DDRSS1_PHY_750_DATA
+ DDRSS1_PHY_751_DATA
+ DDRSS1_PHY_752_DATA
+ DDRSS1_PHY_753_DATA
+ DDRSS1_PHY_754_DATA
+ DDRSS1_PHY_755_DATA
+ DDRSS1_PHY_756_DATA
+ DDRSS1_PHY_757_DATA
+ DDRSS1_PHY_758_DATA
+ DDRSS1_PHY_759_DATA
+ DDRSS1_PHY_760_DATA
+ DDRSS1_PHY_761_DATA
+ DDRSS1_PHY_762_DATA
+ DDRSS1_PHY_763_DATA
+ DDRSS1_PHY_764_DATA
+ DDRSS1_PHY_765_DATA
+ DDRSS1_PHY_766_DATA
+ DDRSS1_PHY_767_DATA
+ DDRSS1_PHY_768_DATA
+ DDRSS1_PHY_769_DATA
+ DDRSS1_PHY_770_DATA
+ DDRSS1_PHY_771_DATA
+ DDRSS1_PHY_772_DATA
+ DDRSS1_PHY_773_DATA
+ DDRSS1_PHY_774_DATA
+ DDRSS1_PHY_775_DATA
+ DDRSS1_PHY_776_DATA
+ DDRSS1_PHY_777_DATA
+ DDRSS1_PHY_778_DATA
+ DDRSS1_PHY_779_DATA
+ DDRSS1_PHY_780_DATA
+ DDRSS1_PHY_781_DATA
+ DDRSS1_PHY_782_DATA
+ DDRSS1_PHY_783_DATA
+ DDRSS1_PHY_784_DATA
+ DDRSS1_PHY_785_DATA
+ DDRSS1_PHY_786_DATA
+ DDRSS1_PHY_787_DATA
+ DDRSS1_PHY_788_DATA
+ DDRSS1_PHY_789_DATA
+ DDRSS1_PHY_790_DATA
+ DDRSS1_PHY_791_DATA
+ DDRSS1_PHY_792_DATA
+ DDRSS1_PHY_793_DATA
+ DDRSS1_PHY_794_DATA
+ DDRSS1_PHY_795_DATA
+ DDRSS1_PHY_796_DATA
+ DDRSS1_PHY_797_DATA
+ DDRSS1_PHY_798_DATA
+ DDRSS1_PHY_799_DATA
+ DDRSS1_PHY_800_DATA
+ DDRSS1_PHY_801_DATA
+ DDRSS1_PHY_802_DATA
+ DDRSS1_PHY_803_DATA
+ DDRSS1_PHY_804_DATA
+ DDRSS1_PHY_805_DATA
+ DDRSS1_PHY_806_DATA
+ DDRSS1_PHY_807_DATA
+ DDRSS1_PHY_808_DATA
+ DDRSS1_PHY_809_DATA
+ DDRSS1_PHY_810_DATA
+ DDRSS1_PHY_811_DATA
+ DDRSS1_PHY_812_DATA
+ DDRSS1_PHY_813_DATA
+ DDRSS1_PHY_814_DATA
+ DDRSS1_PHY_815_DATA
+ DDRSS1_PHY_816_DATA
+ DDRSS1_PHY_817_DATA
+ DDRSS1_PHY_818_DATA
+ DDRSS1_PHY_819_DATA
+ DDRSS1_PHY_820_DATA
+ DDRSS1_PHY_821_DATA
+ DDRSS1_PHY_822_DATA
+ DDRSS1_PHY_823_DATA
+ DDRSS1_PHY_824_DATA
+ DDRSS1_PHY_825_DATA
+ DDRSS1_PHY_826_DATA
+ DDRSS1_PHY_827_DATA
+ DDRSS1_PHY_828_DATA
+ DDRSS1_PHY_829_DATA
+ DDRSS1_PHY_830_DATA
+ DDRSS1_PHY_831_DATA
+ DDRSS1_PHY_832_DATA
+ DDRSS1_PHY_833_DATA
+ DDRSS1_PHY_834_DATA
+ DDRSS1_PHY_835_DATA
+ DDRSS1_PHY_836_DATA
+ DDRSS1_PHY_837_DATA
+ DDRSS1_PHY_838_DATA
+ DDRSS1_PHY_839_DATA
+ DDRSS1_PHY_840_DATA
+ DDRSS1_PHY_841_DATA
+ DDRSS1_PHY_842_DATA
+ DDRSS1_PHY_843_DATA
+ DDRSS1_PHY_844_DATA
+ DDRSS1_PHY_845_DATA
+ DDRSS1_PHY_846_DATA
+ DDRSS1_PHY_847_DATA
+ DDRSS1_PHY_848_DATA
+ DDRSS1_PHY_849_DATA
+ DDRSS1_PHY_850_DATA
+ DDRSS1_PHY_851_DATA
+ DDRSS1_PHY_852_DATA
+ DDRSS1_PHY_853_DATA
+ DDRSS1_PHY_854_DATA
+ DDRSS1_PHY_855_DATA
+ DDRSS1_PHY_856_DATA
+ DDRSS1_PHY_857_DATA
+ DDRSS1_PHY_858_DATA
+ DDRSS1_PHY_859_DATA
+ DDRSS1_PHY_860_DATA
+ DDRSS1_PHY_861_DATA
+ DDRSS1_PHY_862_DATA
+ DDRSS1_PHY_863_DATA
+ DDRSS1_PHY_864_DATA
+ DDRSS1_PHY_865_DATA
+ DDRSS1_PHY_866_DATA
+ DDRSS1_PHY_867_DATA
+ DDRSS1_PHY_868_DATA
+ DDRSS1_PHY_869_DATA
+ DDRSS1_PHY_870_DATA
+ DDRSS1_PHY_871_DATA
+ DDRSS1_PHY_872_DATA
+ DDRSS1_PHY_873_DATA
+ DDRSS1_PHY_874_DATA
+ DDRSS1_PHY_875_DATA
+ DDRSS1_PHY_876_DATA
+ DDRSS1_PHY_877_DATA
+ DDRSS1_PHY_878_DATA
+ DDRSS1_PHY_879_DATA
+ DDRSS1_PHY_880_DATA
+ DDRSS1_PHY_881_DATA
+ DDRSS1_PHY_882_DATA
+ DDRSS1_PHY_883_DATA
+ DDRSS1_PHY_884_DATA
+ DDRSS1_PHY_885_DATA
+ DDRSS1_PHY_886_DATA
+ DDRSS1_PHY_887_DATA
+ DDRSS1_PHY_888_DATA
+ DDRSS1_PHY_889_DATA
+ DDRSS1_PHY_890_DATA
+ DDRSS1_PHY_891_DATA
+ DDRSS1_PHY_892_DATA
+ DDRSS1_PHY_893_DATA
+ DDRSS1_PHY_894_DATA
+ DDRSS1_PHY_895_DATA
+ DDRSS1_PHY_896_DATA
+ DDRSS1_PHY_897_DATA
+ DDRSS1_PHY_898_DATA
+ DDRSS1_PHY_899_DATA
+ DDRSS1_PHY_900_DATA
+ DDRSS1_PHY_901_DATA
+ DDRSS1_PHY_902_DATA
+ DDRSS1_PHY_903_DATA
+ DDRSS1_PHY_904_DATA
+ DDRSS1_PHY_905_DATA
+ DDRSS1_PHY_906_DATA
+ DDRSS1_PHY_907_DATA
+ DDRSS1_PHY_908_DATA
+ DDRSS1_PHY_909_DATA
+ DDRSS1_PHY_910_DATA
+ DDRSS1_PHY_911_DATA
+ DDRSS1_PHY_912_DATA
+ DDRSS1_PHY_913_DATA
+ DDRSS1_PHY_914_DATA
+ DDRSS1_PHY_915_DATA
+ DDRSS1_PHY_916_DATA
+ DDRSS1_PHY_917_DATA
+ DDRSS1_PHY_918_DATA
+ DDRSS1_PHY_919_DATA
+ DDRSS1_PHY_920_DATA
+ DDRSS1_PHY_921_DATA
+ DDRSS1_PHY_922_DATA
+ DDRSS1_PHY_923_DATA
+ DDRSS1_PHY_924_DATA
+ DDRSS1_PHY_925_DATA
+ DDRSS1_PHY_926_DATA
+ DDRSS1_PHY_927_DATA
+ DDRSS1_PHY_928_DATA
+ DDRSS1_PHY_929_DATA
+ DDRSS1_PHY_930_DATA
+ DDRSS1_PHY_931_DATA
+ DDRSS1_PHY_932_DATA
+ DDRSS1_PHY_933_DATA
+ DDRSS1_PHY_934_DATA
+ DDRSS1_PHY_935_DATA
+ DDRSS1_PHY_936_DATA
+ DDRSS1_PHY_937_DATA
+ DDRSS1_PHY_938_DATA
+ DDRSS1_PHY_939_DATA
+ DDRSS1_PHY_940_DATA
+ DDRSS1_PHY_941_DATA
+ DDRSS1_PHY_942_DATA
+ DDRSS1_PHY_943_DATA
+ DDRSS1_PHY_944_DATA
+ DDRSS1_PHY_945_DATA
+ DDRSS1_PHY_946_DATA
+ DDRSS1_PHY_947_DATA
+ DDRSS1_PHY_948_DATA
+ DDRSS1_PHY_949_DATA
+ DDRSS1_PHY_950_DATA
+ DDRSS1_PHY_951_DATA
+ DDRSS1_PHY_952_DATA
+ DDRSS1_PHY_953_DATA
+ DDRSS1_PHY_954_DATA
+ DDRSS1_PHY_955_DATA
+ DDRSS1_PHY_956_DATA
+ DDRSS1_PHY_957_DATA
+ DDRSS1_PHY_958_DATA
+ DDRSS1_PHY_959_DATA
+ DDRSS1_PHY_960_DATA
+ DDRSS1_PHY_961_DATA
+ DDRSS1_PHY_962_DATA
+ DDRSS1_PHY_963_DATA
+ DDRSS1_PHY_964_DATA
+ DDRSS1_PHY_965_DATA
+ DDRSS1_PHY_966_DATA
+ DDRSS1_PHY_967_DATA
+ DDRSS1_PHY_968_DATA
+ DDRSS1_PHY_969_DATA
+ DDRSS1_PHY_970_DATA
+ DDRSS1_PHY_971_DATA
+ DDRSS1_PHY_972_DATA
+ DDRSS1_PHY_973_DATA
+ DDRSS1_PHY_974_DATA
+ DDRSS1_PHY_975_DATA
+ DDRSS1_PHY_976_DATA
+ DDRSS1_PHY_977_DATA
+ DDRSS1_PHY_978_DATA
+ DDRSS1_PHY_979_DATA
+ DDRSS1_PHY_980_DATA
+ DDRSS1_PHY_981_DATA
+ DDRSS1_PHY_982_DATA
+ DDRSS1_PHY_983_DATA
+ DDRSS1_PHY_984_DATA
+ DDRSS1_PHY_985_DATA
+ DDRSS1_PHY_986_DATA
+ DDRSS1_PHY_987_DATA
+ DDRSS1_PHY_988_DATA
+ DDRSS1_PHY_989_DATA
+ DDRSS1_PHY_990_DATA
+ DDRSS1_PHY_991_DATA
+ DDRSS1_PHY_992_DATA
+ DDRSS1_PHY_993_DATA
+ DDRSS1_PHY_994_DATA
+ DDRSS1_PHY_995_DATA
+ DDRSS1_PHY_996_DATA
+ DDRSS1_PHY_997_DATA
+ DDRSS1_PHY_998_DATA
+ DDRSS1_PHY_999_DATA
+ DDRSS1_PHY_1000_DATA
+ DDRSS1_PHY_1001_DATA
+ DDRSS1_PHY_1002_DATA
+ DDRSS1_PHY_1003_DATA
+ DDRSS1_PHY_1004_DATA
+ DDRSS1_PHY_1005_DATA
+ DDRSS1_PHY_1006_DATA
+ DDRSS1_PHY_1007_DATA
+ DDRSS1_PHY_1008_DATA
+ DDRSS1_PHY_1009_DATA
+ DDRSS1_PHY_1010_DATA
+ DDRSS1_PHY_1011_DATA
+ DDRSS1_PHY_1012_DATA
+ DDRSS1_PHY_1013_DATA
+ DDRSS1_PHY_1014_DATA
+ DDRSS1_PHY_1015_DATA
+ DDRSS1_PHY_1016_DATA
+ DDRSS1_PHY_1017_DATA
+ DDRSS1_PHY_1018_DATA
+ DDRSS1_PHY_1019_DATA
+ DDRSS1_PHY_1020_DATA
+ DDRSS1_PHY_1021_DATA
+ DDRSS1_PHY_1022_DATA
+ DDRSS1_PHY_1023_DATA
+ DDRSS1_PHY_1024_DATA
+ DDRSS1_PHY_1025_DATA
+ DDRSS1_PHY_1026_DATA
+ DDRSS1_PHY_1027_DATA
+ DDRSS1_PHY_1028_DATA
+ DDRSS1_PHY_1029_DATA
+ DDRSS1_PHY_1030_DATA
+ DDRSS1_PHY_1031_DATA
+ DDRSS1_PHY_1032_DATA
+ DDRSS1_PHY_1033_DATA
+ DDRSS1_PHY_1034_DATA
+ DDRSS1_PHY_1035_DATA
+ DDRSS1_PHY_1036_DATA
+ DDRSS1_PHY_1037_DATA
+ DDRSS1_PHY_1038_DATA
+ DDRSS1_PHY_1039_DATA
+ DDRSS1_PHY_1040_DATA
+ DDRSS1_PHY_1041_DATA
+ DDRSS1_PHY_1042_DATA
+ DDRSS1_PHY_1043_DATA
+ DDRSS1_PHY_1044_DATA
+ DDRSS1_PHY_1045_DATA
+ DDRSS1_PHY_1046_DATA
+ DDRSS1_PHY_1047_DATA
+ DDRSS1_PHY_1048_DATA
+ DDRSS1_PHY_1049_DATA
+ DDRSS1_PHY_1050_DATA
+ DDRSS1_PHY_1051_DATA
+ DDRSS1_PHY_1052_DATA
+ DDRSS1_PHY_1053_DATA
+ DDRSS1_PHY_1054_DATA
+ DDRSS1_PHY_1055_DATA
+ DDRSS1_PHY_1056_DATA
+ DDRSS1_PHY_1057_DATA
+ DDRSS1_PHY_1058_DATA
+ DDRSS1_PHY_1059_DATA
+ DDRSS1_PHY_1060_DATA
+ DDRSS1_PHY_1061_DATA
+ DDRSS1_PHY_1062_DATA
+ DDRSS1_PHY_1063_DATA
+ DDRSS1_PHY_1064_DATA
+ DDRSS1_PHY_1065_DATA
+ DDRSS1_PHY_1066_DATA
+ DDRSS1_PHY_1067_DATA
+ DDRSS1_PHY_1068_DATA
+ DDRSS1_PHY_1069_DATA
+ DDRSS1_PHY_1070_DATA
+ DDRSS1_PHY_1071_DATA
+ DDRSS1_PHY_1072_DATA
+ DDRSS1_PHY_1073_DATA
+ DDRSS1_PHY_1074_DATA
+ DDRSS1_PHY_1075_DATA
+ DDRSS1_PHY_1076_DATA
+ DDRSS1_PHY_1077_DATA
+ DDRSS1_PHY_1078_DATA
+ DDRSS1_PHY_1079_DATA
+ DDRSS1_PHY_1080_DATA
+ DDRSS1_PHY_1081_DATA
+ DDRSS1_PHY_1082_DATA
+ DDRSS1_PHY_1083_DATA
+ DDRSS1_PHY_1084_DATA
+ DDRSS1_PHY_1085_DATA
+ DDRSS1_PHY_1086_DATA
+ DDRSS1_PHY_1087_DATA
+ DDRSS1_PHY_1088_DATA
+ DDRSS1_PHY_1089_DATA
+ DDRSS1_PHY_1090_DATA
+ DDRSS1_PHY_1091_DATA
+ DDRSS1_PHY_1092_DATA
+ DDRSS1_PHY_1093_DATA
+ DDRSS1_PHY_1094_DATA
+ DDRSS1_PHY_1095_DATA
+ DDRSS1_PHY_1096_DATA
+ DDRSS1_PHY_1097_DATA
+ DDRSS1_PHY_1098_DATA
+ DDRSS1_PHY_1099_DATA
+ DDRSS1_PHY_1100_DATA
+ DDRSS1_PHY_1101_DATA
+ DDRSS1_PHY_1102_DATA
+ DDRSS1_PHY_1103_DATA
+ DDRSS1_PHY_1104_DATA
+ DDRSS1_PHY_1105_DATA
+ DDRSS1_PHY_1106_DATA
+ DDRSS1_PHY_1107_DATA
+ DDRSS1_PHY_1108_DATA
+ DDRSS1_PHY_1109_DATA
+ DDRSS1_PHY_1110_DATA
+ DDRSS1_PHY_1111_DATA
+ DDRSS1_PHY_1112_DATA
+ DDRSS1_PHY_1113_DATA
+ DDRSS1_PHY_1114_DATA
+ DDRSS1_PHY_1115_DATA
+ DDRSS1_PHY_1116_DATA
+ DDRSS1_PHY_1117_DATA
+ DDRSS1_PHY_1118_DATA
+ DDRSS1_PHY_1119_DATA
+ DDRSS1_PHY_1120_DATA
+ DDRSS1_PHY_1121_DATA
+ DDRSS1_PHY_1122_DATA
+ DDRSS1_PHY_1123_DATA
+ DDRSS1_PHY_1124_DATA
+ DDRSS1_PHY_1125_DATA
+ DDRSS1_PHY_1126_DATA
+ DDRSS1_PHY_1127_DATA
+ DDRSS1_PHY_1128_DATA
+ DDRSS1_PHY_1129_DATA
+ DDRSS1_PHY_1130_DATA
+ DDRSS1_PHY_1131_DATA
+ DDRSS1_PHY_1132_DATA
+ DDRSS1_PHY_1133_DATA
+ DDRSS1_PHY_1134_DATA
+ DDRSS1_PHY_1135_DATA
+ DDRSS1_PHY_1136_DATA
+ DDRSS1_PHY_1137_DATA
+ DDRSS1_PHY_1138_DATA
+ DDRSS1_PHY_1139_DATA
+ DDRSS1_PHY_1140_DATA
+ DDRSS1_PHY_1141_DATA
+ DDRSS1_PHY_1142_DATA
+ DDRSS1_PHY_1143_DATA
+ DDRSS1_PHY_1144_DATA
+ DDRSS1_PHY_1145_DATA
+ DDRSS1_PHY_1146_DATA
+ DDRSS1_PHY_1147_DATA
+ DDRSS1_PHY_1148_DATA
+ DDRSS1_PHY_1149_DATA
+ DDRSS1_PHY_1150_DATA
+ DDRSS1_PHY_1151_DATA
+ DDRSS1_PHY_1152_DATA
+ DDRSS1_PHY_1153_DATA
+ DDRSS1_PHY_1154_DATA
+ DDRSS1_PHY_1155_DATA
+ DDRSS1_PHY_1156_DATA
+ DDRSS1_PHY_1157_DATA
+ DDRSS1_PHY_1158_DATA
+ DDRSS1_PHY_1159_DATA
+ DDRSS1_PHY_1160_DATA
+ DDRSS1_PHY_1161_DATA
+ DDRSS1_PHY_1162_DATA
+ DDRSS1_PHY_1163_DATA
+ DDRSS1_PHY_1164_DATA
+ DDRSS1_PHY_1165_DATA
+ DDRSS1_PHY_1166_DATA
+ DDRSS1_PHY_1167_DATA
+ DDRSS1_PHY_1168_DATA
+ DDRSS1_PHY_1169_DATA
+ DDRSS1_PHY_1170_DATA
+ DDRSS1_PHY_1171_DATA
+ DDRSS1_PHY_1172_DATA
+ DDRSS1_PHY_1173_DATA
+ DDRSS1_PHY_1174_DATA
+ DDRSS1_PHY_1175_DATA
+ DDRSS1_PHY_1176_DATA
+ DDRSS1_PHY_1177_DATA
+ DDRSS1_PHY_1178_DATA
+ DDRSS1_PHY_1179_DATA
+ DDRSS1_PHY_1180_DATA
+ DDRSS1_PHY_1181_DATA
+ DDRSS1_PHY_1182_DATA
+ DDRSS1_PHY_1183_DATA
+ DDRSS1_PHY_1184_DATA
+ DDRSS1_PHY_1185_DATA
+ DDRSS1_PHY_1186_DATA
+ DDRSS1_PHY_1187_DATA
+ DDRSS1_PHY_1188_DATA
+ DDRSS1_PHY_1189_DATA
+ DDRSS1_PHY_1190_DATA
+ DDRSS1_PHY_1191_DATA
+ DDRSS1_PHY_1192_DATA
+ DDRSS1_PHY_1193_DATA
+ DDRSS1_PHY_1194_DATA
+ DDRSS1_PHY_1195_DATA
+ DDRSS1_PHY_1196_DATA
+ DDRSS1_PHY_1197_DATA
+ DDRSS1_PHY_1198_DATA
+ DDRSS1_PHY_1199_DATA
+ DDRSS1_PHY_1200_DATA
+ DDRSS1_PHY_1201_DATA
+ DDRSS1_PHY_1202_DATA
+ DDRSS1_PHY_1203_DATA
+ DDRSS1_PHY_1204_DATA
+ DDRSS1_PHY_1205_DATA
+ DDRSS1_PHY_1206_DATA
+ DDRSS1_PHY_1207_DATA
+ DDRSS1_PHY_1208_DATA
+ DDRSS1_PHY_1209_DATA
+ DDRSS1_PHY_1210_DATA
+ DDRSS1_PHY_1211_DATA
+ DDRSS1_PHY_1212_DATA
+ DDRSS1_PHY_1213_DATA
+ DDRSS1_PHY_1214_DATA
+ DDRSS1_PHY_1215_DATA
+ DDRSS1_PHY_1216_DATA
+ DDRSS1_PHY_1217_DATA
+ DDRSS1_PHY_1218_DATA
+ DDRSS1_PHY_1219_DATA
+ DDRSS1_PHY_1220_DATA
+ DDRSS1_PHY_1221_DATA
+ DDRSS1_PHY_1222_DATA
+ DDRSS1_PHY_1223_DATA
+ DDRSS1_PHY_1224_DATA
+ DDRSS1_PHY_1225_DATA
+ DDRSS1_PHY_1226_DATA
+ DDRSS1_PHY_1227_DATA
+ DDRSS1_PHY_1228_DATA
+ DDRSS1_PHY_1229_DATA
+ DDRSS1_PHY_1230_DATA
+ DDRSS1_PHY_1231_DATA
+ DDRSS1_PHY_1232_DATA
+ DDRSS1_PHY_1233_DATA
+ DDRSS1_PHY_1234_DATA
+ DDRSS1_PHY_1235_DATA
+ DDRSS1_PHY_1236_DATA
+ DDRSS1_PHY_1237_DATA
+ DDRSS1_PHY_1238_DATA
+ DDRSS1_PHY_1239_DATA
+ DDRSS1_PHY_1240_DATA
+ DDRSS1_PHY_1241_DATA
+ DDRSS1_PHY_1242_DATA
+ DDRSS1_PHY_1243_DATA
+ DDRSS1_PHY_1244_DATA
+ DDRSS1_PHY_1245_DATA
+ DDRSS1_PHY_1246_DATA
+ DDRSS1_PHY_1247_DATA
+ DDRSS1_PHY_1248_DATA
+ DDRSS1_PHY_1249_DATA
+ DDRSS1_PHY_1250_DATA
+ DDRSS1_PHY_1251_DATA
+ DDRSS1_PHY_1252_DATA
+ DDRSS1_PHY_1253_DATA
+ DDRSS1_PHY_1254_DATA
+ DDRSS1_PHY_1255_DATA
+ DDRSS1_PHY_1256_DATA
+ DDRSS1_PHY_1257_DATA
+ DDRSS1_PHY_1258_DATA
+ DDRSS1_PHY_1259_DATA
+ DDRSS1_PHY_1260_DATA
+ DDRSS1_PHY_1261_DATA
+ DDRSS1_PHY_1262_DATA
+ DDRSS1_PHY_1263_DATA
+ DDRSS1_PHY_1264_DATA
+ DDRSS1_PHY_1265_DATA
+ DDRSS1_PHY_1266_DATA
+ DDRSS1_PHY_1267_DATA
+ DDRSS1_PHY_1268_DATA
+ DDRSS1_PHY_1269_DATA
+ DDRSS1_PHY_1270_DATA
+ DDRSS1_PHY_1271_DATA
+ DDRSS1_PHY_1272_DATA
+ DDRSS1_PHY_1273_DATA
+ DDRSS1_PHY_1274_DATA
+ DDRSS1_PHY_1275_DATA
+ DDRSS1_PHY_1276_DATA
+ DDRSS1_PHY_1277_DATA
+ DDRSS1_PHY_1278_DATA
+ DDRSS1_PHY_1279_DATA
+ DDRSS1_PHY_1280_DATA
+ DDRSS1_PHY_1281_DATA
+ DDRSS1_PHY_1282_DATA
+ DDRSS1_PHY_1283_DATA
+ DDRSS1_PHY_1284_DATA
+ DDRSS1_PHY_1285_DATA
+ DDRSS1_PHY_1286_DATA
+ DDRSS1_PHY_1287_DATA
+ DDRSS1_PHY_1288_DATA
+ DDRSS1_PHY_1289_DATA
+ DDRSS1_PHY_1290_DATA
+ DDRSS1_PHY_1291_DATA
+ DDRSS1_PHY_1292_DATA
+ DDRSS1_PHY_1293_DATA
+ DDRSS1_PHY_1294_DATA
+ DDRSS1_PHY_1295_DATA
+ DDRSS1_PHY_1296_DATA
+ DDRSS1_PHY_1297_DATA
+ DDRSS1_PHY_1298_DATA
+ DDRSS1_PHY_1299_DATA
+ DDRSS1_PHY_1300_DATA
+ DDRSS1_PHY_1301_DATA
+ DDRSS1_PHY_1302_DATA
+ DDRSS1_PHY_1303_DATA
+ DDRSS1_PHY_1304_DATA
+ DDRSS1_PHY_1305_DATA
+ DDRSS1_PHY_1306_DATA
+ DDRSS1_PHY_1307_DATA
+ DDRSS1_PHY_1308_DATA
+ DDRSS1_PHY_1309_DATA
+ DDRSS1_PHY_1310_DATA
+ DDRSS1_PHY_1311_DATA
+ DDRSS1_PHY_1312_DATA
+ DDRSS1_PHY_1313_DATA
+ DDRSS1_PHY_1314_DATA
+ DDRSS1_PHY_1315_DATA
+ DDRSS1_PHY_1316_DATA
+ DDRSS1_PHY_1317_DATA
+ DDRSS1_PHY_1318_DATA
+ DDRSS1_PHY_1319_DATA
+ DDRSS1_PHY_1320_DATA
+ DDRSS1_PHY_1321_DATA
+ DDRSS1_PHY_1322_DATA
+ DDRSS1_PHY_1323_DATA
+ DDRSS1_PHY_1324_DATA
+ DDRSS1_PHY_1325_DATA
+ DDRSS1_PHY_1326_DATA
+ DDRSS1_PHY_1327_DATA
+ DDRSS1_PHY_1328_DATA
+ DDRSS1_PHY_1329_DATA
+ DDRSS1_PHY_1330_DATA
+ DDRSS1_PHY_1331_DATA
+ DDRSS1_PHY_1332_DATA
+ DDRSS1_PHY_1333_DATA
+ DDRSS1_PHY_1334_DATA
+ DDRSS1_PHY_1335_DATA
+ DDRSS1_PHY_1336_DATA
+ DDRSS1_PHY_1337_DATA
+ DDRSS1_PHY_1338_DATA
+ DDRSS1_PHY_1339_DATA
+ DDRSS1_PHY_1340_DATA
+ DDRSS1_PHY_1341_DATA
+ DDRSS1_PHY_1342_DATA
+ DDRSS1_PHY_1343_DATA
+ DDRSS1_PHY_1344_DATA
+ DDRSS1_PHY_1345_DATA
+ DDRSS1_PHY_1346_DATA
+ DDRSS1_PHY_1347_DATA
+ DDRSS1_PHY_1348_DATA
+ DDRSS1_PHY_1349_DATA
+ DDRSS1_PHY_1350_DATA
+ DDRSS1_PHY_1351_DATA
+ DDRSS1_PHY_1352_DATA
+ DDRSS1_PHY_1353_DATA
+ DDRSS1_PHY_1354_DATA
+ DDRSS1_PHY_1355_DATA
+ DDRSS1_PHY_1356_DATA
+ DDRSS1_PHY_1357_DATA
+ DDRSS1_PHY_1358_DATA
+ DDRSS1_PHY_1359_DATA
+ DDRSS1_PHY_1360_DATA
+ DDRSS1_PHY_1361_DATA
+ DDRSS1_PHY_1362_DATA
+ DDRSS1_PHY_1363_DATA
+ DDRSS1_PHY_1364_DATA
+ DDRSS1_PHY_1365_DATA
+ DDRSS1_PHY_1366_DATA
+ DDRSS1_PHY_1367_DATA
+ DDRSS1_PHY_1368_DATA
+ DDRSS1_PHY_1369_DATA
+ DDRSS1_PHY_1370_DATA
+ DDRSS1_PHY_1371_DATA
+ DDRSS1_PHY_1372_DATA
+ DDRSS1_PHY_1373_DATA
+ DDRSS1_PHY_1374_DATA
+ DDRSS1_PHY_1375_DATA
+ DDRSS1_PHY_1376_DATA
+ DDRSS1_PHY_1377_DATA
+ DDRSS1_PHY_1378_DATA
+ DDRSS1_PHY_1379_DATA
+ DDRSS1_PHY_1380_DATA
+ DDRSS1_PHY_1381_DATA
+ DDRSS1_PHY_1382_DATA
+ DDRSS1_PHY_1383_DATA
+ DDRSS1_PHY_1384_DATA
+ DDRSS1_PHY_1385_DATA
+ DDRSS1_PHY_1386_DATA
+ DDRSS1_PHY_1387_DATA
+ DDRSS1_PHY_1388_DATA
+ DDRSS1_PHY_1389_DATA
+ DDRSS1_PHY_1390_DATA
+ DDRSS1_PHY_1391_DATA
+ DDRSS1_PHY_1392_DATA
+ DDRSS1_PHY_1393_DATA
+ DDRSS1_PHY_1394_DATA
+ DDRSS1_PHY_1395_DATA
+ DDRSS1_PHY_1396_DATA
+ DDRSS1_PHY_1397_DATA
+ DDRSS1_PHY_1398_DATA
+ DDRSS1_PHY_1399_DATA
+ DDRSS1_PHY_1400_DATA
+ DDRSS1_PHY_1401_DATA
+ DDRSS1_PHY_1402_DATA
+ DDRSS1_PHY_1403_DATA
+ DDRSS1_PHY_1404_DATA
+ DDRSS1_PHY_1405_DATA
+ DDRSS1_PHY_1406_DATA
+ DDRSS1_PHY_1407_DATA
+ DDRSS1_PHY_1408_DATA
+ DDRSS1_PHY_1409_DATA
+ DDRSS1_PHY_1410_DATA
+ DDRSS1_PHY_1411_DATA
+ DDRSS1_PHY_1412_DATA
+ DDRSS1_PHY_1413_DATA
+ DDRSS1_PHY_1414_DATA
+ DDRSS1_PHY_1415_DATA
+ DDRSS1_PHY_1416_DATA
+ DDRSS1_PHY_1417_DATA
+ DDRSS1_PHY_1418_DATA
+ DDRSS1_PHY_1419_DATA
+ DDRSS1_PHY_1420_DATA
+ DDRSS1_PHY_1421_DATA
+ DDRSS1_PHY_1422_DATA
+ >;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721S2 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ msmc_ram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x70000000 0x0 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x70000000 0x400000>;
+
+ atf-sram@0 {
+ reg = <0x0 0x20000>;
+ };
+
+ tifs-sram@1f0000 {
+ reg = <0x1f0000 0x10000>;
+ };
+
+ l3cache-sram@200000 {
+ reg = <0x200000 0x200000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
+ <0x00 0x01900000 0x00 0x100000>; /* GICR */
+
+ /* vcpumntirq: virtual CPU interface maintenance interrupt */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_gpio_intr: interrupt-controller@a00000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x00a00000 0x00 0x800>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <148>;
+ ti,interrupt-ranges = <8 360 56>;
+ };
+
+ main_pmx0: pinctrl@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x0 0x11c000 0x0 0x120>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x200>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 146 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x200>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 350 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x200>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 351 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x200>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 352 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x200>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 353 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x200>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 354 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x200>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 355 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart7: serial@2870000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02870000 0x00 0x200>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 356 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart8: serial@2880000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02880000 0x00 0x200>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 357 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart9: serial@2890000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02890000 0x00 0x200>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 358 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_gpio0: gpio@600000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00600000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <145>, <146>, <147>, <148>, <149>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 111 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio2: gpio@610000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00610000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <154>, <155>, <156>, <157>, <158>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 112 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio4: gpio@620000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00620000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <163>, <164>, <165>, <166>, <167>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 113 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio6: gpio@630000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00630000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <172>, <173>, <174>, <175>, <176>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "gpio";
+ };
+
+ main_i2c0: i2c@2000000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02000000 0x00 0x100>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 214 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c1: i2c@2010000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02010000 0x00 0x100>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 215 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c2: i2c@2020000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02020000 0x00 0x100>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 216 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c3: i2c@2030000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02030000 0x00 0x100>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 217 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c4: i2c@2040000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02040000 0x00 0x100>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 218 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c5: i2c@2050000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02050000 0x00 0x100>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 219 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c6: i2c@2060000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02060000 0x00 0x100>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 220 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_sdhci0: mmc@4f80000 {
+ compatible = "ti,j721e-sdhci-8bit";
+ reg = <0x00 0x04f80000 0x00 0x1000>,
+ <0x00 0x04f88000 0x00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 98 1>;
+ assigned-clock-parents = <&k3_clks 98 2>;
+ bus-width = <8>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x5>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,strobe-sel = <0x77>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ dma-coherent;
+ };
+
+ main_sdhci1: mmc@4fb0000 {
+ compatible = "ti,j721e-sdhci-4bit";
+ reg = <0x00 0x04fb0000 0x00 0x1000>,
+ <0x00 0x04fb8000 0x00 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 99 1>;
+ assigned-clock-parents = <&k3_clks 99 2>;
+ bus-width = <4>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x5>;
+ ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ /* Masking support for SDR104 capability */
+ // sdhci-caps-mask = <0x00000003 0x00000000>;
+ };
+
+ main_navss: bus@30000000 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+ ti,sci-dev-id = <224>;
+ dma-coherent;
+ dma-ranges;
+
+ main_navss_intr: interrupt-controller@310e0000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x310e0000 0x00 0x4000>;
+ ti,intr-trigger-type = <4>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <227>;
+ ti,interrupt-ranges = <0 64 64>,
+ <64 448 64>,
+ <128 672 64>;
+ };
+
+ main_udmass_inta: msi-controller@33d00000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x33d00000 0x00 0x100000>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ interrupt-parent = <&main_navss_intr>;
+ msi-controller;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <265>;
+ ti,interrupt-ranges = <0 0 256>;
+ };
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ hwspinlock: spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f80000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster1: mailbox@31f81000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f81000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster2: mailbox@31f82000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f82000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster3: mailbox@31f83000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f83000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster4: mailbox@31f84000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f84000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster5: mailbox@31f85000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f85000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster6: mailbox@31f86000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f86000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster7: mailbox@31f87000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f87000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster8: mailbox@31f88000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f88000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster9: mailbox@31f89000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f89000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster10: mailbox@31f8a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster11: mailbox@31f8b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster0: mailbox@31f90000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f90000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster1: mailbox@31f91000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f91000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster2: mailbox@31f92000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f92000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster3: mailbox@31f93000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f93000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster4: mailbox@31f94000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f94000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster5: mailbox@31f95000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f95000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster6: mailbox@31f96000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f96000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster7: mailbox@31f97000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f97000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster8: mailbox@31f98000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f98000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster9: mailbox@31f99000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f99000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster10: mailbox@31f9a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f9a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox1_cluster11: mailbox@31f9b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f9b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ main_ringacc: ringacc@3c000000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <1024>;
+ ti,sci-rm-range-gp-rings = <0x1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <259>;
+ msi-parent = <&main_udmass_inta>;
+ };
+
+ main_udmap: dma-controller@31150000 {
+ compatible = "ti,j721e-navss-main-udmap";
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x80000>,
+ <0x0 0x35000000 0x0 0x200000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <1>;
+
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <263>;
+ ti,ringacc = <&main_ringacc>;
+
+ ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+ <0x0f>, /* TX_HCHAN */
+ <0x10>; /* TX_UHCHAN */
+ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+ <0x0b>, /* RX_HCHAN */
+ <0x0c>; /* RX_UHCHAN */
+ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ };
+
+ cpts@310d0000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x310d0000 0x0 0x400>;
+ reg-names = "cpts";
+ clocks = <&k3_clks 226 5>;
+ clock-names = "cpts";
+ interrupts-extended = <&main_navss_intr 391>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+ };
+ };
+
+ main_mcan0: can@2701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02701000 0x00 0x200>,
+ <0x00 0x02708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan1: can@2711000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02711000 0x00 0x200>,
+ <0x00 0x02718000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan2: can@2721000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02721000 0x00 0x200>,
+ <0x00 0x02728000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan3: can@2731000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02731000 0x00 0x200>,
+ <0x00 0x02738000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan4: can@2741000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02741000 0x00 0x200>,
+ <0x00 0x02748000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan5: can@2751000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02751000 0x00 0x200>,
+ <0x00 0x02758000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan6: can@2761000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02761000 0x00 0x200>,
+ <0x00 0x02768000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan7: can@2771000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02771000 0x00 0x200>,
+ <0x00 0x02778000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan8: can@2781000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02781000 0x00 0x200>,
+ <0x00 0x02788000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan9: can@2791000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02791000 0x00 0x200>,
+ <0x00 0x02798000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan10: can@27a1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027a1000 0x00 0x200>,
+ <0x00 0x027a8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan11: can@27b1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027b1000 0x00 0x200>,
+ <0x00 0x027b8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan12: can@27c1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027c1000 0x00 0x200>,
+ <0x00 0x027c8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan13: can@27d1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027d1000 0x00 0x200>,
+ <0x00 0x027d8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan14: can@2681000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02681000 0x00 0x200>,
+ <0x00 0x02688000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan15: can@2691000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02691000 0x00 0x200>,
+ <0x00 0x02698000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan16: can@26a1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x026a1000 0x00 0x200>,
+ <0x00 0x026a8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ main_mcan17: can@26b1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x026b1000 0x00 0x200>,
+ <0x00 0x026b8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu_wakeup {
+ sms: system-controller@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+
+ mbox-names = "rx", "tx";
+
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+
+ reg-names = "debug_messages";
+ reg = <0x00 0x44083000 0x00 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ chipid@43000014 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00 0x43000014 0x00 0x4>;
+ };
+
+ mcu_ram: sram@41c00000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x41c00000 0x00 0x100000>;
+ ranges = <0x00 0x00 0x41c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wkup_pmx0: pinctrl@4301c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c000 0x00 0x178>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_gpio_intr: interrupt-controller@42200000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x42200000 0x00 0x400>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <125>;
+ ti,interrupt-ranges = <16 928 16>;
+ };
+
+ mcu_conf: syscon@40f00000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x40f00000 0x0 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+ phy_gmii_sel: phy@4040 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4040 0x4>;
+ #phy-cells = <1>;
+ };
+
+ };
+
+ wkup_uart0: serial@42300000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x42300000 0x00 0x200>;
+ interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 359 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcu_uart0: serial@40a00000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x40a00000 0x00 0x200>;
+ interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 149 3>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ wkup_gpio0: gpio@42110000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x42110000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <89>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 115 0>;
+ clock-names = "gpio";
+ };
+
+ wkup_gpio1: gpio@42100000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x42100000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <89>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 116 0>;
+ clock-names = "gpio";
+ };
+
+ wkup_i2c0: i2c@42120000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x42120000 0x00 0x100>;
+ interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 223 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcu_i2c0: i2c@40b00000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x40b00000 0x00 0x100>;
+ interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 221 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcu_i2c1: i2c@40b10000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x40b10000 0x00 0x100>;
+ interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 222 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcu_mcan0: can@40528000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40528000 0x00 0x200>,
+ <0x00 0x40500000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ mcu_mcan1: can@40568000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40568000 0x00 0x200>,
+ <0x00 0x40540000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ };
+
+ mcu_navss: bus@28380000{
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
+ dma-coherent;
+ dma-ranges;
+
+ ti,sci-dev-id = <267>;
+
+ mcu_ringacc: ringacc@2b800000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <286>;
+ ti,sci-rm-range-gp-rings = <0x1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <272>;
+ msi-parent = <&main_udmass_inta>;
+ };
+
+ mcu_udmap: dma-controller@285c0000 {
+ compatible = "ti,j721e-navss-mcu-udmap";
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <1>;
+
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <273>;
+ ti,ringacc = <&mcu_ringacc>;
+ ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+ <0x0f>; /* TX_HCHAN */
+ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+ <0x0b>; /* RX_HCHAN */
+ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ };
+ };
+
+ mcu_cpsw: ethernet@46000000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
+ dma-coherent;
+ clocks = <&k3_clks 29 28>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&mcu_udmap 0xf000>,
+ <&mcu_udmap 0xf001>,
+ <&mcu_udmap 0xf002>,
+ <&mcu_udmap 0xf003>,
+ <&mcu_udmap 0xf004>,
+ <&mcu_udmap 0xf005>,
+ <&mcu_udmap 0xf006>,
+ <&mcu_udmap 0xf007>,
+ <&mcu_udmap 0x7000>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ ti,syscon-efuse = <&mcu_conf 0x200>;
+ phys = <&phy_gmii_sel 1>;
+ };
+ };
+
+ davinci_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 29 28>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 29 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2-som-p0.dtsi"
+#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
+#include "k3-j721s2-ddr.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = &fs_loader0;
+ stdout-path = &main_uart8;
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ compatible = "u-boot,fs-loader";
+ u-boot,dm-pre-reloc;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <2000000000>;
+ ti,sci = <&sms>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ clk_200mhz: dummy_clock_200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+
+ clk_19_2mhz: dummy_clock_19_2mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu_wakeup {
+ sa3_secproxy: secproxy@44880000 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x44880000 0x0 0x20000>,
+ <0x0 0x44860000 0x0 0x20000>,
+ <0x0 0x43600000 0x0 0x10000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ };
+
+ mcu_secproxy: secproxy@2a380000 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ u-boot,dm-spl;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
+ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
+ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
+ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
+ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
+ J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+ J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
+ J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
+ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
+ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ mcu_uart0_pins_default: mcu-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ wkup_uart0_pins_default: wkup-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
+ >;
+ };
+};
+
+&sms {
+ mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+ u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+};
+
+&main_uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart8_pins_default>;
+};
+
+&main_sdhci0 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+ non-removable;
+ bus-width = <8>;
+};
+
+&main_sdhci1 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+
+#include "k3-j721s2-common-proc-board-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 16 GB RAM */
+ reg = <0x00 0x80000000 0x00 0x80000000>,
+ <0x08 0x80000000 0x03 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ };
+
+ transceiver0: can-phy0 {
+ /* standby pin has been grounded by default */
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+};
+
+&main_pmx0 {
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
+ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
+ >;
+ };
+
+ main_mcan16_pins_default: main-mcan16-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
+ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
+ >;
+ };
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ exp_som: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+ "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+ "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
+ "GPIO_LIN_EN", "CAN_STB";
+ };
+};
+
+&main_mcan16 {
+ pinctrl-0 = <&main_mcan16_pins_default>;
+ pinctrl-names = "default";
+ phys = <&transceiver0>;
+};
+
+&mailbox0_cluster0 {
+ status = "disabled";
+};
+
+&mailbox0_cluster1 {
+ status = "disabled";
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mailbox1_cluster0 {
+ status = "disabled";
+};
+
+&mailbox1_cluster1 {
+ status = "disabled";
+};
+
+&mailbox1_cluster2 {
+ status = "disabled";
+};
+
+&mailbox1_cluster3 {
+ status = "disabled";
+};
+
+&mailbox1_cluster4 {
+ status = "disabled";
+};
+
+&mailbox1_cluster5 {
+ status = "disabled";
+};
+
+&mailbox1_cluster6 {
+ status = "disabled";
+};
+
+&mailbox1_cluster7 {
+ status = "disabled";
+};
+
+&mailbox1_cluster8 {
+ status = "disabled";
+};
+
+&mailbox1_cluster9 {
+ status = "disabled";
+};
+
+&mailbox1_cluster10 {
+ status = "disabled";
+};
+
+&mailbox1_cluster11 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721S2 SoC Family
+ *
+ * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+
+ model = "Texas Instruments K3 J721S2 SoC";
+ compatible = "ti,j721s2";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a72";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a72";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ msmc_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a72_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a72-pmu";
+ /* Recommendation from GIC500 TRM Table A.3 */
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
+ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
+ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
+ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
+ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
+ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
+
+ /* MCUSS_WKUP Range */
+ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ cbass_mcu_wakeup: bus@28380000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
+
+ };
+
+ };
+};
+
+/* Now include peripherals from each bus segment */
+#include "k3-j721s2-main.dtsi"
+#include "k3-j721s2-mcu-wakeup.dtsi"
label = "qe";
reg = <0x20000 0x20000>;
};
- /* ZL30343 init data to be added here */
partition@40000 {
label = "envred";
reg = <0x40000 0x20000>;
reg = <0x100000 0x100000>;
};
partition@200000 {
+ label = "redenvred";
+ reg = <0x200000 0x20000>;
+ };
+ partition@220000 {
+ label = "redenv";
+ reg = <0x220000 0x20000>;
+ };
+ partition@240000 {
+ label = "redu-boot";
+ reg = <0x240000 0x100000>;
+ };
+ partition@340000 {
label = "ubi0";
- reg = <0x200000 0x3E00000>;
+ reg = <0x340000 0x03C00000>;
};
};
};
&enet2 {
phy-handle = <&debug_phy>;
phy-connection-type = "rgmii-id";
+ max-speed = <100>;
status = "okay";
};
reg = <0x100000 0x100000>;
};
partition@200000 {
+ label = "redenvred";
+ reg = <0x200000 0x20000>;
+ };
+ partition@220000 {
+ label = "redenv";
+ reg = <0x220000 0x20000>;
+ };
+ partition@240000 {
+ label = "redu-boot";
+ reg = <0x240000 0x100000>;
+ };
+ partition@340000 {
label = "ubi0";
- reg = <0x200000 0x3E00000>;
+ reg = <0x340000 0x03C00000>;
};
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+/ {
+ model = "Lichee Pi Nano";
+ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pe_pins>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ clocks {
+ osc24M: clk-24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk-32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram-controller@1c00000 {
+ compatible = "allwinner,suniv-f1c100s-system-control",
+ "allwinner,sun4i-a10-system-control";
+ reg = <0x01c00000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_d: sram@10000 {
+ compatible = "mmio-sram";
+ reg = <0x00010000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00010000 0x1000>;
+
+ otg_sram: sram-section@0 {
+ compatible = "allwinner,suniv-f1c100s-sram-d",
+ "allwinner,sun4i-a10-sram-d";
+ reg = <0x0000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ccu: clock@1c20000 {
+ compatible = "allwinner,suniv-f1c100s-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ intc: interrupt-controller@1c20400 {
+ compatible = "allwinner,suniv-f1c100s-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,suniv-f1c100s-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <38>, <39>, <40>;
+ clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #gpio-cells = <3>;
+
+ uart0_pe_pins: uart0-pe-pins {
+ pins = "PE0", "PE1";
+ function = "uart0";
+ };
+ };
+
+ timer@1c20c00 {
+ compatible = "allwinner,suniv-f1c100s-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <13>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@1c20ca0 {
+ compatible = "allwinner,suniv-f1c100s-wdt",
+ "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20ca0 0x20>;
+ };
+
+ uart0: serial@1c25000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu 38>;
+ resets = <&ccu 24>;
+ status = "disabled";
+ };
+
+ uart1: serial@1c25400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu 39>;
+ resets = <&ccu 25>;
+ status = "disabled";
+ };
+
+ uart2: serial@1c25800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu 40>;
+ resets = <&ccu 26>;
+ status = "disabled";
+ };
+ };
+};
/ {
aliases {
+#ifndef CONFIG_MACH_SUNIV
mmc0 = &mmc0;
+#endif
#if CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
mmc1 = &mmc2;
#endif
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
-#include <include/dt-bindings/gpio/gpio.h>
/ {
model = "Smartlynq+ DLC21 RevA";
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP K26/KV260 SD wiring
- *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-/* SD0 only supports 3.3V, no level shifter */
-&sdhci1 { /* on CC - MIO 39 - 51 */
- status = "okay";
- no-1-8-v;
- disable-wp;
- broken-cd;
- xlnx,mio-bank = <1>;
- /* Do not run SD in HS mode from bootloader */
- sdhci-caps-mask = <0 0x200000>;
- sdhci-caps = <0 0>;
- max-frequency = <19000000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP Z2-VSOM
- *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-/* SD0 only supports 3.3V, no level shifter */
-&sdhci1 { /* FIXME - on CC - MIO 39 - 51 */
- status = "okay";
- no-1-8-v;
- disable-wp;
- broken-cd;
- xlnx,mio-bank = <1>;
- /* Do not run SD in HS mode from bootloader */
- sdhci-caps-mask = <0 0x200000>;
- sdhci-caps = <0 0>;
- max-frequency = <19000000>;
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#define APPLE_RTKIT_PWR_STATE_SLEEP 0x01
+#define APPLE_RTKIT_PWR_STATE_QUIESCED 0x10
+#define APPLE_RTKIT_PWR_STATE_ON 0x20
+
+int apple_rtkit_init(struct mbox_chan *);
+int apple_rtkit_shutdown(struct mbox_chan *, int);
#include <linux/bitops.h>
#include <stdbool.h>
-#define GPR_TZASC_EN BIT(0)
-#define GPR_TZASC_EN_LOCK BIT(16)
+#define GPR_TZASC_EN BIT(0)
+#define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
+#define GPR_TZASC_EN_LOCK BIT(16)
+#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
#define SRC_SCR_M4_ENABLE_OFFSET 3
#define SRC_SCR_M4_ENABLE_MASK BIT(3)
#ifndef _ASM_ARCH_CGC_H
#define _ASM_ARCH_CGC_H
-enum cgc1_clk {
+enum cgc_clk {
DUMMY0_CLK,
DUMMY1_CLK,
LPOSC,
+ NIC_APCLK,
+ NIC_PERCLK,
+ XBAR_APCLK,
XBAR_BUSCLK,
+ AD_SLOWCLK,
SOSC,
SOSC_DIV1,
SOSC_DIV2,
PLL3_PFD2_DIV2,
PLL3_PFD3_DIV1,
PLL3_PFD3_DIV2,
+ LVDS,
+ LPAV_AXICLK,
+ LPAV_AHBCLK,
+ LPAV_BUSCLK,
+ PLL4,
+ PLL4_VCODIV,
+ PLL4_PFD0,
+ PLL4_PFD1,
+ PLL4_PFD2,
+ PLL4_PFD3,
+ PLL4_PFD0_DIV1,
+ PLL4_PFD0_DIV2,
+ PLL4_PFD1_DIV1,
+ PLL4_PFD1_DIV2,
+ PLL4_PFD2_DIV1,
+ PLL4_PFD2_DIV2,
+ PLL4_PFD3_DIV1,
+ PLL4_PFD3_DIV2,
+ CM33_BUSCLK,
+ PLL1_VCO_DIV,
+ PLL0_PFD2_DIV,
+ PLL0_PFD1_DIV,
};
struct cgc1_regs {
u32 lvdscfg;
};
-u32 cgc1_clk_get_rate(enum cgc1_clk clk);
+u32 cgc_clk_get_rate(enum cgc_clk clk);
void cgc1_pll3_init(void);
void cgc1_pll2_init(void);
void cgc1_soscdiv_init(void);
void cgc1_init_core_clk(void);
void cgc2_pll4_init(void);
void cgc2_ddrclk_config(u32 src, u32 div);
-u32 cgc1_sosc_div(enum cgc1_clk clk);
+void cgc2_ddrclk_wait_unlock(void);
+u32 cgc1_sosc_div(enum cgc_clk clk);
+void cgc1_enet_stamp_sel(u32 clk_src);
+void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd);
+void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div);
+void cgc2_lpav_init(enum cgc_clk clk);
#endif
int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
void cgc1_enet_stamp_sel(u32 clk_src);
+void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
+void reset_lcdclk(void);
+void enable_mipi_dsi_clk(unsigned char enable);
+void enable_adc1_clk(bool enable);
#endif
#define PCC_XRDC_MGR_ADDR 0x292d00bc
+#define PCC1_RBASE 0x28091000
#define PCC3_RBASE 0x292d0000
#define PCC4_RBASE 0x29800000
#define PCC5_RBASE 0x2da70000
#include <asm/arch/iomux.h>
enum {
+ IMX8ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0x000c, 0x000c, IOMUX_CONFIG_MPORTS | 0x6, 0x0948, 0x1, 0),
+ IMX8ULP_PAD_PTA8__LPI2C0_SCL = IOMUX_PAD(0x0020, 0x0020, IOMUX_CONFIG_MPORTS | 0x5, 0x097c, 0x2, 0),
+ IMX8ULP_PAD_PTA9__LPI2C0_SDA = IOMUX_PAD(0x0024, 0x0024, IOMUX_CONFIG_MPORTS | 0x5, 0x0980, 0x2, 0),
+
IMX8ULP_PAD_PTB7__PMIC0_MODE2 = IOMUX_PAD(0x009C, 0x009C, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
IMX8ULP_PAD_PTB8__PMIC0_MODE1 = IOMUX_PAD(0x00A0, 0x00A0, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
IMX8ULP_PAD_PTB9__PMIC0_MODE0 = IOMUX_PAD(0x00A4, 0x00A4, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
#include <asm/arch/cgc.h>
+enum pcc1_entry {
+ ADC1_PCC1_SLOT = 34,
+};
+
enum pcc3_entry {
DMA1_MP_PCC3_SLOT = 1,
DMA1_CH0_PCC3_SLOT = 2,
RGPIOF_PCC4_SLOT = 31,
};
+enum pcc5_entry {
+ DMA2_MP_PCC5_SLOT = 0,
+ DMA2_CH0_PCC5_SLOT = 1,
+ DMA2_CH1_PCC5_SLOT = 2,
+ DMA2_CH2_PCC5_SLOT = 3,
+ DMA2_CH3_PCC5_SLOT = 4,
+ DMA2_CH4_PCC5_SLOT = 5,
+ DMA2_CH5_PCC5_SLOT = 6,
+ DMA2_CH6_PCC5_SLOT = 7,
+ DMA2_CH7_PCC5_SLOT = 8,
+ DMA2_CH8_PCC5_SLOT = 9,
+ DMA2_CH9_PCC5_SLOT = 10,
+ DMA2_CH10_PCC5_SLOT = 11,
+ DMA2_CH11_PCC5_SLOT = 12,
+ DMA2_CH12_PCC5_SLOT = 13,
+ DMA2_CH13_PCC5_SLOT = 14,
+ DMA2_CH14_PCC5_SLOT = 15,
+ DMA2_CH15_PCC5_SLOT = 16,
+ DMA2_CH16_PCC5_SLOT = 17,
+ DMA2_CH17_PCC5_SLOT = 18,
+ DMA2_CH18_PCC5_SLOT = 19,
+ DMA2_CH19_PCC5_SLOT = 20,
+ DMA2_CH20_PCC5_SLOT = 21,
+ DMA2_CH21_PCC5_SLOT = 22,
+ DMA2_CH22_PCC5_SLOT = 23,
+ DMA2_CH23_PCC5_SLOT = 24,
+ DMA2_CH24_PCC5_SLOT = 25,
+ DMA2_CH25_PCC5_SLOT = 26,
+ DMA2_CH26_PCC5_SLOT = 27,
+ DMA2_CH27_PCC5_SLOT = 28,
+ DMA2_CH28_PCC5_SLOT = 29,
+ DMA2_CH29_PCC5_SLOT = 30,
+ DMA2_CH30_PCC5_SLOT = 31,
+ DMA2_CH31_PCC5_SLOT = 32,
+ MU2_B_PCC5_SLOT = 33,
+ MU3_B_PCC5_SLOT = 34,
+ SEMA42_2_PCC5_SLOT = 35,
+ CMC2_PCC5_SLOT = 36,
+ AVD_SIM_PCC5_SLOT = 37,
+ LPAV_CGC_PCC5_SLOT = 38,
+ PCC5_PCC5_SLOT = 39,
+ TPM8_PCC5_SLOT = 40,
+ SAI6_PCC5_SLOT = 41,
+ SAI7_PCC5_SLOT = 42,
+ SPDIF_PCC5_SLOT = 43,
+ ISI_PCC5_SLOT = 44,
+ CSI_REGS_PCC5_SLOT = 45,
+ CSI_PCC5_SLOT = 47,
+ DSI_PCC5_SLOT = 48,
+ WDOG5_PCC5_SLOT = 50,
+ EPDC_PCC5_SLOT = 51,
+ PXP_PCC5_SLOT = 52,
+ SFA2_PCC5_SLOT = 53,
+ GPU2D_PCC5_SLOT = 60,
+ GPU3D_PCC5_SLOT = 61,
+ DCNANO_PCC5_SLOT = 62,
+ LPDDR4_PCC5_SLOT = 66,
+ CSI_CLK_UI_PCC5_SLOT = 67,
+ CSI_CLK_ESC_PCC5_SLOT = 68,
+ RGPIOD_PCC5_SLOT = 69,
+};
+
/* PCC registers */
#define PCC_PR_OFFSET 31
#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
};
int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable);
-int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src);
+int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src);
int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot);
-int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src);
+int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src);
int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot);
#endif
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
enum boot_device get_boot_device(void);
+void set_lpav_qos(void);
+void load_lposc_fuse(void);
#endif
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#ifdef CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
-#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
u32 is_mem_sdr(void);
u32 mem_ok(u32 cs);
-u32 get_sdr_cs_size(u32);
u32 get_sdr_cs_offset(u32);
#endif /* __ASSEMBLY__ */
void prcm_init(void);
void per_clocks_enable(void);
void ehci_clocks_enable(void);
-
void memif_init(void);
void sdrc_init(void);
-void do_sdrc_init(u32, u32);
-
void get_board_mem_timings(struct board_sdrc_timings *timings);
int identify_nand_chip(int *mfr, int *id);
void emif4_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
u32 base, u32 size);
void set_gpmc_cs0(int flash_type);
-
void watchdog_init(void);
void set_muxconf_regs(void);
-
u32 get_cpu_family(void);
u32 get_cpu_rev(void);
-u32 get_sku_id(void);
u32 is_gpmc_muxed(void);
u32 get_gpmc0_type(void);
-u32 get_gpmc0_width(void);
u32 is_running_in_sdram(void);
u32 is_running_in_sram(void);
u32 is_running_in_flash(void);
u32 wait_on_value(u32, u32, void *, u32);
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdelay(unsigned long);
-void make_cs1_contiguous(void);
int omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_set_aux_cr_secure(u32 acr);
u32 warm_reset(void);
-
void save_omap_boot_params(void);
#endif
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
+/* CM_IPU1_IPU1_CLKCTRL CLKSEL MASK */
+#define IPU1_CLKCTRL_CLKSEL_MASK BIT(24)
+
/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
#elif defined(CONFIG_SUN50I_GEN_H6)
#include <asm/arch/clock_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
- defined(CONFIG_MACH_SUN50I)
+ defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
#include <asm/arch/clock_sun6i.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/clock_sun9i.h>
#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
+#ifdef CONFIG_MACH_SUNIV
+/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
+#define PLL6_CFG_DEFAULT 0x90041801
+#else
#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
+#endif
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
#define AHB_RESET_OFFSET_EPHY 2
#define AHB_RESET_OFFSET_LVDS 0
+/* apb1 reset */
+#ifdef CONFIG_MACH_SUNIV
+#define APB1_GATE_UART_SHIFT (20)
+#define APB1_GATE_TWI_SHIFT (16)
+#define APB1_RESET_UART_SHIFT (20)
+#define APB1_RESET_TWI_SHIFT (16)
+#endif
+
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
+#ifdef CONFIG_MACH_SUNIV
+#define SUNXI_UART0_BASE 0x01c25000
+#define SUNXI_UART1_BASE 0x01c25400
+#define SUNXI_UART2_BASE 0x01c25800
+#else
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
+#endif
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400
void sunxi_reset(void);
int sunxi_get_ss_bonding_id(void);
int sunxi_get_sid(unsigned int *sid);
+unsigned int sunxi_get_sram_id(void);
#endif /* __ASSEMBLY__ */
#endif /* _SUNXI_CPU_SUN4I_H */
#include <asm/arch/dram_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN50I_H616)
#include <asm/arch/dram_sun50i_h616.h>
+#elif defined(CONFIG_MACH_SUNIV)
+#include <asm/arch/dram_suniv.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * suniv DRAM controller register definition
+ *
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is:
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ */
+
+#define PIO_SDRAM_DRV (0x2c0)
+#define PIO_SDRAM_PULL (0x2c4)
+
+#define DRAM_SCONR (0x00)
+#define DRAM_STMG0R (0x04)
+#define DRAM_STMG1R (0x08)
+#define DRAM_SCTLR (0x0c)
+#define DRAM_SREFR (0x10)
+#define DRAM_SEXTMR (0x14)
+#define DRAM_DDLYR (0x24)
+#define DRAM_DADRR (0x28)
+#define DRAM_DVALR (0x2c)
+#define DRAM_DRPTR0 (0x30)
+#define DRAM_DRPTR1 (0x34)
+#define DRAM_DRPTR2 (0x38)
+#define DRAM_DRPTR3 (0x3c)
+#define DRAM_SEFR (0x40)
+#define DRAM_MAE (0x44)
+#define DRAM_ASPR (0x48)
+#define DRAM_SDLY0 (0x4C)
+#define DRAM_SDLY1 (0x50)
+#define DRAM_SDLY2 (0x54)
+#define DRAM_MCR0 (0x100)
+#define DRAM_MCR1 (0x104)
+#define DRAM_MCR2 (0x108)
+#define DRAM_MCR3 (0x10c)
+#define DRAM_MCR4 (0x110)
+#define DRAM_MCR5 (0x114)
+#define DRAM_MCR6 (0x118)
+#define DRAM_MCR7 (0x11c)
+#define DRAM_MCR8 (0x120)
+#define DRAM_MCR9 (0x124)
+#define DRAM_MCR10 (0x128)
+#define DRAM_MCR11 (0x12c)
+#define DRAM_BWCR (0x140)
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
+#define SUNIV_GPE_UART0 5
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3
u32 insreg08; /* 0xb0 */
};
-#if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)
-/*
- * FIXME: forward declaration of this structs needed because omap got the
- * ehci implementation backwards. move out ehci_hcd_x from board files
- */
-struct ehci_hccr;
-struct ehci_hcor;
-
-int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor);
-int omap_ehci_hcd_stop(void);
-#endif
-
#endif /* _OMAP_COMMON_EHCI_H_ */
#endif
+#define IMX_PAD_SION 0x40000000
#define IOMUX_CONFIG_SION 0x10
#define GPIO_PIN_MASK 0x1f
#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define IMX6_BMODE_MASK GENMASK(7, 0)
-#define IMX6_BMODE_SHIFT 4
-#define IMX6_BMODE_EMI_MASK BIT(3)
-#define IMX6_BMODE_EMI_SHIFT 3
+#define IMX6_BMODE_SHIFT 4
+#define IMX6_BMODE_EIM_MASK BIT(3)
+#define IMX6_BMODE_EIM_SHIFT 3
#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
#define IMX6_BMODE_SERIAL_ROM_SHIFT 24
IMX6_BMODE_I2C3,
};
-enum imx6_bmode_emi {
+enum imx6_bmode_eim {
IMX6_BMODE_NOR,
IMX6_BMODE_ONENAND,
};
enum imx6_bmode {
- IMX6_BMODE_EMI,
+ IMX6_BMODE_EIM,
#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
IMX6_BMODE_QSPI,
IMX6_BMODE_RESERVED,
unsigned long reg3);
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
+void enable_ca7_smp(void);
+#endif
+
#endif
/* IPU */
u32 cm_ipu_clkstctrl;
u32 cm_ipu_i2c5_clkctrl;
+ u32 cm_ipu1_clkstctrl;
+ u32 cm_ipu1_ipu1_clkctrl;
+ u32 cm_ipu2_clkstctrl;
+ u32 cm_ipu2_ipu2_clkctrl;
/*l3main1 edma*/
u32 cm_l3main1_tptc1_clkctrl;
u8 wait_for_disable);
#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
+void do_enable_ipu_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+void enable_ipu1_clocks(void);
+void enable_ipu2_clocks(void);
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
u32 omap_ddr_clk(void);
default "apple"
config SYS_SOC
- default "m1"
+ default "apple"
config SYS_MALLOC_LEN
default 0x4000000
obj-y += board.o
obj-y += lowlevel_init.o
+obj-y += rtkit.o
DECLARE_GLOBAL_DATA_PTR;
-static struct mm_region apple_mem_map[] = {
+/* Apple M1 */
+
+static struct mm_region t8103_mem_map[] = {
{
/* I/O */
.virt = 0x200000000,
.phys = 0x200000000,
- .size = 8UL * SZ_1G,
+ .size = 2UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x380000000,
+ .phys = 0x380000000,
+ .size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
/* I/O */
.virt = 0x500000000,
.phys = 0x500000000,
- .size = 2UL * SZ_1G,
+ .size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
- /* Empty entry for framebuffer */
+ /* Framebuffer */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
0,
+ }
+};
+
+/* Apple M1 Pro/Max */
+
+static struct mm_region t6000_mem_map[] = {
+ {
+ /* I/O */
+ .virt = 0x280000000,
+ .phys = 0x280000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x380000000,
+ .phys = 0x380000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x580000000,
+ .phys = 0x580000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5a0000000,
+ .phys = 0x5a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5c0000000,
+ .phys = 0x5c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x700000000,
+ .phys = 0x700000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xb00000000,
+ .phys = 0xb00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xf00000000,
+ .phys = 0xf00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x1300000000,
+ .phys = 0x1300000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x10000000000,
+ .phys = 0x10000000000,
+ .size = 16UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Framebuffer */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
-struct mm_region *mem_map = apple_mem_map;
+struct mm_region *mem_map;
int board_init(void)
{
int dram_init(void)
{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+extern long fw_dtb_pointer;
+
+void *board_fdt_blob_setup(int *err)
+{
+ /* Return DTB pointer passed by m1n1 */
+ *err = 0;
+ return (void *)fw_dtb_pointer;
+}
+
+void build_mem_map(void)
+{
ofnode node;
- int index, ret;
fdt_addr_t base;
fdt_size_t size;
+ int i;
+
+ if (of_machine_is_compatible("apple,t8103"))
+ mem_map = t8103_mem_map;
+ else if (of_machine_is_compatible("apple,t6000"))
+ mem_map = t6000_mem_map;
+ else if (of_machine_is_compatible("apple,t6001"))
+ mem_map = t6000_mem_map;
+ else
+ panic("Unsupported SoC\n");
- ret = fdtdec_setup_mem_size_base();
- if (ret)
- return ret;
+ /* Find list terminator. */
+ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
+ ;
+
+ /* Align RAM mapping to page boundaries */
+ base = gd->bd->bi_dram[0].start;
+ size = gd->bd->bi_dram[0].size;
+ size += (base - ALIGN_DOWN(base, SZ_4K));
+ base = ALIGN_DOWN(base, SZ_4K);
+ size = ALIGN(size, SZ_4K);
/* Update RAM mapping */
- index = ARRAY_SIZE(apple_mem_map) - 3;
- apple_mem_map[index].virt = gd->ram_base;
- apple_mem_map[index].phys = gd->ram_base;
- apple_mem_map[index].size = gd->ram_size;
+ mem_map[i - 2].virt = base;
+ mem_map[i - 2].phys = base;
+ mem_map[i - 2].size = size;
node = ofnode_path("/chosen/framebuffer");
if (!ofnode_valid(node))
- return 0;
+ return;
base = ofnode_get_addr_size(node, "reg", &size);
if (base == FDT_ADDR_T_NONE)
- return 0;
+ return;
- /* Add framebuffer mapping */
- index = ARRAY_SIZE(apple_mem_map) - 2;
- apple_mem_map[index].virt = base;
- apple_mem_map[index].phys = base;
- apple_mem_map[index].size = size;
- apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
- PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ /* Align framebuffer mapping to page boundaries */
+ size += (base - ALIGN_DOWN(base, SZ_4K));
+ base = ALIGN_DOWN(base, SZ_4K);
+ size = ALIGN(size, SZ_4K);
- return 0;
+ /* Add framebuffer mapping */
+ mem_map[i - 1].virt = base;
+ mem_map[i - 1].phys = base;
+ mem_map[i - 1].size = size;
}
-int dram_init_banksize(void)
+void enable_caches(void)
{
- return fdtdec_setup_memory_banksize();
-}
+ build_mem_map();
-extern long fw_dtb_pointer;
+ icache_enable();
+ dcache_enable();
+}
-void *board_fdt_blob_setup(int *err)
+u64 get_page_table_size(void)
{
- /* Return DTB pointer passed by m1n1 */
- *err = 0;
- return (void *)fw_dtb_pointer;
+ return SZ_256K;
}
-ulong board_get_usable_ram_top(ulong total_size)
+int board_late_init(void)
{
- /*
- * Top part of RAM is used by firmware for things like the
- * framebuffer. This gives us plenty of room to play with.
+ unsigned long base;
+ unsigned long top;
+ u32 status = 0;
+
+ /* Reserve 4M each for scriptaddr and pxefile_addr_r at the top of RAM
+ * at least 1M below the stack.
*/
- return 0x980000000;
+ top = gd->start_addr_sp - CONFIG_STACK_SIZE - SZ_8M - SZ_1M;
+ top = ALIGN_DOWN(top, SZ_8M);
+
+ status |= env_set_hex("scriptaddr", top + SZ_4M);
+ status |= env_set_hex("pxefile_addr_r", top);
+
+ /* somewhat based on the Linux Kernel boot requirements:
+ * align by 2M and maximal FDT size 2M
+ */
+ base = ALIGN(gd->ram_base, SZ_2M);
+
+ status |= env_set_hex("fdt_addr_r", base);
+ status |= env_set_hex("kernel_addr_r", base + SZ_2M);
+ status |= env_set_hex("ramdisk_addr_r", base + SZ_128M);
+ status |= env_set_hex("loadaddr", base + SZ_2G);
+ status |= env_set_hex("kernel_comp_addr_r", base + SZ_2G - SZ_128M);
+ status |= env_set_hex("kernel_comp_size", SZ_128M);
+
+ if (status)
+ log_warning("late_init: Failed to set run time variables\n");
+
+ return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
+ * (C) Copyright 2021 Copyright The Asahi Linux Contributors
+ */
+
+#include <common.h>
+#include <mailbox.h>
+#include <malloc.h>
+
+#include <asm/arch/rtkit.h>
+#include <linux/apple-mailbox.h>
+#include <linux/bitfield.h>
+
+#define APPLE_RTKIT_EP_MGMT 0
+#define APPLE_RTKIT_EP_CRASHLOG 1
+#define APPLE_RTKIT_EP_SYSLOG 2
+#define APPLE_RTKIT_EP_DEBUG 3
+#define APPLE_RTKIT_EP_IOREPORT 4
+
+/* Messages for management endpoint. */
+#define APPLE_RTKIT_MGMT_TYPE GENMASK(59, 52)
+
+#define APPLE_RTKIT_MGMT_PWR_STATE GENMASK(15, 0)
+
+#define APPLE_RTKIT_MGMT_HELLO 1
+#define APPLE_RTKIT_MGMT_HELLO_REPLY 2
+#define APPLE_RTKIT_MGMT_HELLO_MINVER GENMASK(15, 0)
+#define APPLE_RTKIT_MGMT_HELLO_MAXVER GENMASK(31, 16)
+
+#define APPLE_RTKIT_MGMT_STARTEP 5
+#define APPLE_RTKIT_MGMT_STARTEP_EP GENMASK(39, 32)
+#define APPLE_RTKIT_MGMT_STARTEP_FLAG BIT(1)
+
+#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE 6
+#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK 7
+
+#define APPLE_RTKIT_MGMT_EPMAP 8
+#define APPLE_RTKIT_MGMT_EPMAP_LAST BIT(51)
+#define APPLE_RTKIT_MGMT_EPMAP_BASE GENMASK(34, 32)
+#define APPLE_RTKIT_MGMT_EPMAP_BITMAP GENMASK(31, 0)
+
+#define APPLE_RTKIT_MGMT_EPMAP_REPLY 8
+#define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT(0)
+
+#define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11
+#define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12
+
+/* Messages for internal endpoints. */
+#define APPLE_RTKIT_BUFFER_REQUEST 1
+#define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK(51, 44)
+#define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK(41, 0)
+
+int apple_rtkit_init(struct mbox_chan *chan)
+{
+ struct apple_mbox_msg msg;
+ int endpoints[256];
+ int nendpoints = 0;
+ int endpoint;
+ int min_ver, max_ver, want_ver;
+ int msgtype, pwrstate;
+ u64 reply;
+ u32 bitmap, base;
+ int i, ret;
+
+ /* Wakup the IOP. */
+ msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_ON);
+ msg.msg1 = APPLE_RTKIT_EP_MGMT;
+ ret = mbox_send(chan, &msg);
+ if (ret < 0)
+ return ret;
+
+ /* Wait for protocol version negotiation message. */
+ ret = mbox_recv(chan, &msg, 10000);
+ if (ret < 0)
+ return ret;
+
+ endpoint = msg.msg1;
+ msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
+ if (endpoint != APPLE_RTKIT_EP_MGMT) {
+ printf("%s: unexpected endpoint %d\n", __func__, endpoint);
+ return -EINVAL;
+ }
+ if (msgtype != APPLE_RTKIT_MGMT_HELLO) {
+ printf("%s: unexpected message type %d\n", __func__, msgtype);
+ return -EINVAL;
+ }
+
+ min_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MINVER, msg.msg0);
+ max_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MAXVER, msg.msg0);
+ want_ver = min(APPLE_RTKIT_MAX_SUPPORTED_VERSION, max_ver);
+
+ if (min_ver > APPLE_RTKIT_MAX_SUPPORTED_VERSION) {
+ printf("%s: firmware min version %d is too new\n",
+ __func__, min_ver);
+ return -ENOTSUPP;
+ }
+
+ if (max_ver < APPLE_RTKIT_MIN_SUPPORTED_VERSION) {
+ printf("%s: firmware max version %d is too old\n",
+ __func__, max_ver);
+ return -ENOTSUPP;
+ }
+
+ /* Ack version. */
+ msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_HELLO_REPLY) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MINVER, want_ver) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MAXVER, want_ver);
+ msg.msg1 = APPLE_RTKIT_EP_MGMT;
+ ret = mbox_send(chan, &msg);
+ if (ret < 0)
+ return ret;
+
+wait_epmap:
+ /* Wait for endpoint map message. */
+ ret = mbox_recv(chan, &msg, 10000);
+ if (ret < 0)
+ return ret;
+
+ endpoint = msg.msg1;
+ msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
+ if (endpoint != APPLE_RTKIT_EP_MGMT) {
+ printf("%s: unexpected endpoint %d\n", __func__, endpoint);
+ return -EINVAL;
+ }
+ if (msgtype != APPLE_RTKIT_MGMT_EPMAP) {
+ printf("%s: unexpected message type %d\n", __func__, msgtype);
+ return -EINVAL;
+ }
+
+ bitmap = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BITMAP, msg.msg0);
+ base = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BASE, msg.msg0);
+ for (i = 0; i < 32; i++) {
+ if (bitmap & (1U << i))
+ endpoints[nendpoints++] = base * 32 + i;
+ }
+
+ /* Ack endpoint map. */
+ reply = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_EPMAP_REPLY) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_EPMAP_BASE, base);
+ if (msg.msg0 & APPLE_RTKIT_MGMT_EPMAP_LAST)
+ reply |= APPLE_RTKIT_MGMT_EPMAP_LAST;
+ else
+ reply |= APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE;
+ msg.msg0 = reply;
+ msg.msg1 = APPLE_RTKIT_EP_MGMT;
+ ret = mbox_send(chan, &msg);
+ if (ret < 0)
+ return ret;
+
+ if (reply & APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE)
+ goto wait_epmap;
+
+ for (i = 0; i < nendpoints; i++) {
+ /* Don't start the syslog endpoint since we can't
+ easily handle its messages in U-Boot. */
+ if (endpoints[i] == APPLE_RTKIT_EP_SYSLOG)
+ continue;
+
+ /* Request endpoint. */
+ msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_STARTEP) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_STARTEP_EP, endpoints[i]) |
+ APPLE_RTKIT_MGMT_STARTEP_FLAG;
+ msg.msg1 = APPLE_RTKIT_EP_MGMT;
+ ret = mbox_send(chan, &msg);
+ if (ret < 0)
+ return ret;
+ }
+
+ pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP;
+ while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) {
+ ret = mbox_recv(chan, &msg, 100000);
+ if (ret < 0)
+ return ret;
+
+ endpoint = msg.msg1;
+ msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
+
+ if (endpoint == APPLE_RTKIT_EP_CRASHLOG ||
+ endpoint == APPLE_RTKIT_EP_SYSLOG ||
+ endpoint == APPLE_RTKIT_EP_IOREPORT) {
+ u64 addr = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg.msg0);
+ u64 size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg.msg0);
+
+ if (msgtype == APPLE_RTKIT_BUFFER_REQUEST && addr != 0)
+ continue;
+
+ msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) |
+ FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, size) |
+ FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, addr);
+ msg.msg1 = endpoint;
+ ret = mbox_send(chan, &msg);
+ if (ret < 0)
+ return ret;
+ continue;
+ }
+
+ if (endpoint != APPLE_RTKIT_EP_MGMT) {
+ printf("%s: unexpected endpoint %d\n", __func__, endpoint);
+ return -EINVAL;
+ }
+ if (msgtype != APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK) {
+ printf("%s: unexpected message type %d\n", __func__, msgtype);
+ return -EINVAL;
+ }
+
+ pwrstate = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
+ }
+
+ return 0;
+}
+
+int apple_rtkit_shutdown(struct mbox_chan *chan, int pwrstate)
+{
+ struct apple_mbox_msg msg;
+ int ret;
+
+ msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate);
+ msg.msg1 = APPLE_RTKIT_EP_MGMT;
+ ret = mbox_send(chan, &msg);
+ if (ret < 0)
+ return ret;
+
+ ret = mbox_recv(chan, &msg, 100000);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
endif
quiet_cmd_cpp_cfg = CFGS $@
- cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
+ cmd_cpp_cfg = $(CPP) $(cpp_flags) -D__ASSEMBLY__ -x c -o $@ $<
# mkimage source config file
IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
#include <asm/io.h>
#include <asm/mach-imx/sys_proto.h>
-static void enable_ca7_smp(void)
+void enable_ca7_smp(void)
{
u32 val;
/* boot search related variables and definitions */
static int g_boot_search_count = 4;
+static int g_boot_secondary_offset;
static int g_boot_search_stride;
static int g_pages_per_stride;
boot_stream2_address = ((maxsize - boot_stream1_address) / 2 +
boot_stream1_address);
- if (boot_cfg->secondary_boot_stream_off_in_MB)
+ if (g_boot_secondary_offset)
boot_stream2_address =
- (loff_t)boot_cfg->secondary_boot_stream_off_in_MB * 1024 * 1024;
+ (loff_t)g_boot_secondary_offset * 1024 * 1024;
max_boot_stream_size = boot_stream2_address - boot_stream1_address;
};
ret = mtd_write_oob(mtd, off, &ops);
- printf("NAND FCB write to 0x%llxx offset 0x%zx written: %s\n", off, ops.len, ret ? "ERROR" : "OK");
+ printf("NAND FCB write to 0x%llx offset 0x%zx written: %s\n", off, ops.len, ret ? "ERROR" : "OK");
}
if (ret)
return (*(int *)(data + off) == fingerprint);
}
+static int fuse_secondary_boot(u32 bank, u32 word, u32 mask, u32 off)
+{
+ int err;
+ u32 val;
+ int ret;
+
+ err = fuse_read(bank, word, &val);
+ if (err)
+ return 0;
+
+ val = (val & mask) >> off;
+
+ if (val > 10)
+ return 0;
+
+ switch (val) {
+ case 0:
+ ret = 4;
+ break;
+ case 1:
+ ret = 1;
+ break;
+ default:
+ ret = 2 << val;
+ break;
+ }
+
+ return ret;
+};
+
static int fuse_to_search_count(u32 bank, u32 word, u32 mask, u32 off)
{
int err;
g_boot_search_count);
}
+ if (plat_config.misc_flags & FIRMWARE_SECONDARY_FIXED_ADDR) {
+ if (is_imx8mn())
+ g_boot_secondary_offset = fuse_secondary_boot(2, 1, 0xff0000, 16);
+ }
+
cmd = argv[1];
--argc;
++argv;
select SUPPORT_SPL
select IMX8M_DDR4
+config TARGET_IMX8MN_VENICE
+ bool "Support Gateworks Venice iMX8M Nano module"
+ select BINMAN
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
+config TARGET_IMX8MN_VAR_SOM
+ bool "imx8mn_var_som"
+ select BINMAN
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_DDR4
+
+config TARGET_KONTRON_PITX_IMX8M
+ bool "Support Kontron pITX-imx8m"
+ select BINMAN
+ select IMX8MQ
+ select IMX8M_LPDDR4
+
config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"
select BINMAN
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_VERDIN_IMX8MP
+ bool "Support Toradex Verdin iMX8M Plus module"
+ select BINMAN
+ select IMX8MP
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select SUPPORT_EXTENSION_SCAN
config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
bool "CompuLab iot-gate-imx8 with optee support"
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select SUPPORT_EXTENSION_SCAN
+
+config TARGET_IMX8MP_RSB3720A1_4G
+ bool "Support i.MX8MP RSB3720A1 4G"
+ select BINMAN
+ select IMX8MP
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
+config TARGET_IMX8MP_RSB3720A1_6G
+ bool "Support i.MX8MP RSB3720A1 6G"
+ select BINMAN
+ select IMX8MP
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
endchoice
+source "board/advantech/imx8mp_rsb3720a1/Kconfig"
source "board/beacon/imx8mm/Kconfig"
source "board/beacon/imx8mn/Kconfig"
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
+source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
+source "board/variscite/imx8mn_var_som/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
+source "board/toradex/verdin-imx8mp/Kconfig"
endif
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
break;
case MHZ(1200):
- /* 24 * 0xc8 / 2 / 2 ^ 1 */
+ /* 24 * 0x12c / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1400):
+ /* 24 * 0x15e / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1500):
+ /* 24 * 0x177 / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1600):
+ /* 24 * 0xc8 / 3 / 2 ^ 0 */
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
- INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1);
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+ break;
+ case MHZ(1800):
+ /* 24 * 0xe1 / 3 / 2 ^ 0 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
break;
case MHZ(2000):
/* 24 * 0xfa / 3 / 2 ^ 0 */
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
return get_root_clk(AHB_CLK_ROOT) / (val + 1);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
case MXC_ESDHC_CLK:
return get_root_clk(USDHC1_CLK_ROOT);
case MXC_ESDHC2_CLK:
return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_QSPI_CLK:
+ return get_root_clk(QSPI_CLK_ROOT);
default:
return get_root_clk(clk);
}
* Copyright 2019 NXP
*/
-#define __ASSEMBLY__
FIT
BOOT_FROM sd
* Copyright 2019 NXP
*/
-#define __ASSEMBLY__
FIT
ROM_VERSION v2
* Copyright 2019 NXP
*/
-#define __ASSEMBLY__
FIT
ROM_VERSION v2
* Copyright 2019 NXP
*/
-#define __ASSEMBLY__
FIT
ROM_VERSION v2
* Copyright 2018-2021 NXP
*/
-#define __ASSEMBLY__
FIT
BOOT_FROM sd
/* Enable TZASC and lock setting */
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
+
+ /*
+ * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
+ * order to avoid AXI Bus errors when GPU is in use
+ */
if (is_imx8mm() || is_imx8mn() || is_imx8mp())
- setbits_le32(&gpr->gpr[10], BIT(1));
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
+
+ /*
+ * imx8mn and imx8mp implements the lock bit for
+ * TZASC_ID_SWAP_BYPASS, enable it to lock settings
+ */
+ if (is_imx8mn() || is_imx8mp())
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
+
/*
* set Region 0 attribute to allow secure and non-secure
* read/write permission. Found some masters like usb dwc3
enum env_location env_get_location(enum env_operation op, int prio)
{
enum boot_device dev = get_boot_device();
- enum env_location env_loc = ENVL_UNKNOWN;
if (prio)
- return env_loc;
+ return ENVL_UNKNOWN;
switch (dev) {
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
case QSPI_BOOT:
- env_loc = ENVL_SPI_FLASH;
- break;
-#endif
-#ifdef CONFIG_ENV_IS_IN_NAND
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ return ENVL_NOWHERE;
case NAND_BOOT:
- env_loc = ENVL_NAND;
- break;
-#endif
-#ifdef CONFIG_ENV_IS_IN_MMC
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+ return ENVL_NAND;
+ return ENVL_NOWHERE;
case SD1_BOOT:
case SD2_BOOT:
case SD3_BOOT:
case MMC1_BOOT:
case MMC2_BOOT:
case MMC3_BOOT:
- env_loc = ENVL_MMC;
- break;
-#endif
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+ return ENVL_EXT4;
+ else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ return ENVL_NOWHERE;
default:
-#if defined(CONFIG_ENV_IS_NOWHERE)
- env_loc = ENVL_NOWHERE;
-#endif
- break;
+ return ENVL_NOWHERE;
}
-
- return env_loc;
}
-#ifndef ENV_IS_EMBEDDED
-long long env_get_offset(long long defautl_offset)
-{
- enum boot_device dev = get_boot_device();
-
- switch (dev) {
- case NAND_BOOT:
- return (60 << 20); /* 60MB offset for NAND */
- default:
- break;
- }
-
- return defautl_offset;
-}
-#endif
#endif
;
/* Enable all 4 PFDs */
- setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 0); /* 316.8Mhz for NIC_LPAV */
- setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 8);
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0);
+ setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
}
+void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)
+{
+ void __iomem *reg = &cgc2_regs->pll4div_pfd0;
+ u32 halt_mask = BIT(7) | BIT(15);
+ u32 pfd_shift = (pllpfd - PLL4_PFD0) * 8;
+ u32 val;
+
+ if (pllpfd < PLL4_PFD0 || pllpfd > PLL4_PFD3)
+ return;
+
+ if ((pllpfd - PLL4_PFD0) >> 1)
+ reg = &cgc2_regs->pll4div_pfd1;
+
+ halt_mask = halt_mask << (((pllpfd - PLL4_PFD0) & 0x1) * 16);
+
+ /* halt pfd div */
+ setbits_le32(reg, halt_mask);
+
+ /* gate pfd */
+ setbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) << pfd_shift);
+
+ val = readl(&cgc2_regs->pll4pfdcfg);
+ val &= ~(0x3f << pfd_shift);
+ val |= (pfd << pfd_shift);
+ writel(val, &cgc2_regs->pll4pfdcfg);
+
+ /* ungate */
+ clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) << pfd_shift);
+
+ /* Wait stable */
+ while ((readl(&cgc2_regs->pll4pfdcfg) & (BIT(6) << pfd_shift))
+ != (BIT(6) << pfd_shift))
+ ;
+
+ /* enable pfd div */
+ clrbits_le32(reg, halt_mask);
+}
+
+void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div)
+{
+ void __iomem *reg = &cgc2_regs->pll4div_pfd0;
+ u32 shift = ((pllpfddiv - PLL4_PFD0_DIV1) & 0x3) * 8;
+
+ if (pllpfddiv < PLL4_PFD0_DIV1 || pllpfddiv > PLL4_PFD3_DIV2)
+ return;
+
+ if ((pllpfddiv - PLL4_PFD0_DIV1) >> 2)
+ reg = &cgc2_regs->pll4div_pfd1;
+
+ /* Halt pfd div */
+ setbits_le32(reg, BIT(7) << shift);
+
+ /* Clear div */
+ clrbits_le32(reg, 0x3f << shift);
+
+ /* Set div*/
+ setbits_le32(reg, div << shift);
+
+ /* Enable pfd div */
+ clrbits_le32(reg, BIT(7) << shift);
+}
+
void cgc2_ddrclk_config(u32 src, u32 div)
{
+ /* If reg lock is set, wait until unlock by HW */
+ /* This lock is triggered by div updating and ddrclk halt status change, */
+ while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
+ ;
+
writel((src << 28) | (div << 21), &cgc2_regs->ddrclk);
/* wait for DDRCLK switching done */
while (!(readl(&cgc2_regs->ddrclk) & BIT(27)))
;
}
-u32 decode_pll(enum cgc1_clk pll)
+void cgc2_ddrclk_wait_unlock(void)
+{
+ while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
+ ;
+}
+
+void cgc2_lpav_init(enum cgc_clk clk)
+{
+ u32 i, scs, reg;
+ const enum cgc_clk src[] = {FRO, PLL4_PFD1, SOSC, LVDS};
+
+ reg = readl(&cgc2_regs->niclpavclk);
+ scs = (reg >> 28) & 0x3;
+
+ for (i = 0; i < 4; i++) {
+ if (clk == src[i]) {
+ if (scs == i)
+ return;
+
+ reg &= ~(0x3 << 28);
+ reg |= (i << 28);
+
+ writel(reg, &cgc2_regs->niclpavclk);
+ break;
+ }
+ }
+
+ if (i == 4)
+ printf("Invalid clock source [%u] for LPAV\n", clk);
+}
+
+u32 cgc2_nic_get_rate(enum cgc_clk clk)
+{
+ u32 reg, rate;
+ u32 scs, lpav_axi_clk, lpav_ahb_clk, lpav_bus_clk;
+ const enum cgc_clk src[] = {FRO, PLL4_PFD1, SOSC, LVDS};
+
+ reg = readl(&cgc2_regs->niclpavclk);
+ scs = (reg >> 28) & 0x3;
+ lpav_axi_clk = ((reg >> 21) & 0x3f) + 1;
+ lpav_ahb_clk = ((reg >> 14) & 0x3f) + 1;
+ lpav_bus_clk = ((reg >> 7) & 0x3f) + 1;
+
+ rate = cgc_clk_get_rate(src[scs]);
+
+ switch (clk) {
+ case LPAV_AXICLK:
+ rate = rate / lpav_axi_clk;
+ break;
+ case LPAV_AHBCLK:
+ rate = rate / (lpav_axi_clk * lpav_ahb_clk);
+ break;
+ case LPAV_BUSCLK:
+ rate = rate / (lpav_axi_clk * lpav_bus_clk);
+ break;
+ default:
+ return 0;
+ }
+
+ return rate;
+}
+
+u32 decode_pll(enum cgc_clk pll)
{
u32 reg, infreq, mult;
u32 num, denom;
num = readl(&cgc1_regs->pll3num) & 0x3FFFFFFF;
return (u64)infreq * mult + (u64)infreq * num / denom;
+ case PLL4:
+ reg = readl(&cgc2_regs->pll4csr);
+ if (!(reg & BIT(24)))
+ return 0;
+
+ reg = readl(&cgc2_regs->pll4cfg);
+ mult = (reg >> 16) & 0x7F;
+ denom = readl(&cgc2_regs->pll4denom) & 0x3FFFFFFF;
+ num = readl(&cgc2_regs->pll4num) & 0x3FFFFFFF;
+
+ return (u64)infreq * mult + (u64)infreq * num / denom;
default:
printf("Unsupported pll clocks %d\n", pll);
break;
return 0;
}
-u32 cgc1_pll3_vcodiv_rate(void)
+u32 cgc_pll_vcodiv_rate(enum cgc_clk clk)
{
u32 reg, gate, div;
+ void __iomem *plldiv_vco;
+ enum cgc_clk pll;
+
+ if (clk == PLL3_VCODIV) {
+ plldiv_vco = &cgc1_regs->pll3div_vco;
+ pll = PLL3;
+ } else {
+ plldiv_vco = &cgc2_regs->pll4div_vco;
+ pll = PLL4;
+ }
- reg = readl(&cgc1_regs->pll3div_vco);
+ reg = readl(plldiv_vco);
gate = BIT(7) & reg;
div = reg & 0x3F;
- return gate ? 0 : decode_pll(PLL3) / (div + 1);
+ return gate ? 0 : decode_pll(pll) / (div + 1);
}
-u32 cgc1_pll3_pfd_rate(enum cgc1_clk clk)
+u32 cgc_pll_pfd_rate(enum cgc_clk clk)
{
u32 index, gate, vld, reg;
+ void __iomem *pllpfdcfg;
+ enum cgc_clk pll;
switch (clk) {
case PLL3_PFD0:
- index = 0;
- break;
case PLL3_PFD1:
- index = 1;
- break;
case PLL3_PFD2:
- index = 2;
- break;
case PLL3_PFD3:
- index = 3;
+ index = clk - PLL3_PFD0;
+ pllpfdcfg = &cgc1_regs->pll3pfdcfg;
+ pll = PLL3;
+ break;
+ case PLL4_PFD0:
+ case PLL4_PFD1:
+ case PLL4_PFD2:
+ case PLL4_PFD3:
+ index = clk - PLL4_PFD0;
+ pllpfdcfg = &cgc2_regs->pll4pfdcfg;
+ pll = PLL4;
break;
default:
return 0;
}
- reg = readl(&cgc1_regs->pll3pfdcfg);
+ reg = readl(pllpfdcfg);
gate = reg & (BIT(7) << (index * 8));
vld = reg & (BIT(6) << (index * 8));
if (gate || !vld)
return 0;
- return (u64)decode_pll(PLL3) * 18 / ((reg >> (index * 8)) & 0x3F);
+ return (u64)decode_pll(pll) * 18 / ((reg >> (index * 8)) & 0x3F);
}
-u32 cgc1_pll3_pfd_div(enum cgc1_clk clk)
+u32 cgc_pll_pfd_div(enum cgc_clk clk)
{
void __iomem *base;
u32 pfd, index, gate, reg;
switch (clk) {
case PLL3_PFD0_DIV1:
- base = &cgc1_regs->pll3div_pfd0;
- pfd = PLL3_PFD0;
- index = 0;
- break;
case PLL3_PFD0_DIV2:
base = &cgc1_regs->pll3div_pfd0;
pfd = PLL3_PFD0;
- index = 1;
+ index = clk - PLL3_PFD0_DIV1;
break;
case PLL3_PFD1_DIV1:
- base = &cgc1_regs->pll3div_pfd0;
- pfd = PLL3_PFD1;
- index = 2;
- break;
case PLL3_PFD1_DIV2:
base = &cgc1_regs->pll3div_pfd0;
pfd = PLL3_PFD1;
- index = 3;
+ index = clk - PLL3_PFD0_DIV1;
break;
case PLL3_PFD2_DIV1:
- base = &cgc1_regs->pll3div_pfd1;
- pfd = PLL3_PFD2;
- index = 0;
- break;
case PLL3_PFD2_DIV2:
base = &cgc1_regs->pll3div_pfd1;
pfd = PLL3_PFD2;
- index = 1;
+ index = clk - PLL3_PFD2_DIV1;
break;
case PLL3_PFD3_DIV1:
- base = &cgc1_regs->pll3div_pfd1;
- pfd = PLL3_PFD3;
- index = 2;
- break;
case PLL3_PFD3_DIV2:
base = &cgc1_regs->pll3div_pfd1;
pfd = PLL3_PFD3;
- index = 3;
+ index = clk - PLL3_PFD2_DIV1;
+ break;
+ case PLL4_PFD0_DIV1:
+ case PLL4_PFD0_DIV2:
+ base = &cgc2_regs->pll4div_pfd0;
+ pfd = PLL4_PFD0;
+ index = clk - PLL4_PFD0_DIV1;
+ break;
+ case PLL4_PFD1_DIV1:
+ case PLL4_PFD1_DIV2:
+ base = &cgc2_regs->pll4div_pfd0;
+ pfd = PLL4_PFD1;
+ index = clk - PLL4_PFD0_DIV1;
+ break;
+ case PLL4_PFD2_DIV1:
+ case PLL4_PFD2_DIV2:
+ base = &cgc2_regs->pll4div_pfd1;
+ pfd = PLL4_PFD2;
+ index = clk - PLL4_PFD2_DIV1;
+ break;
+ case PLL4_PFD3_DIV1:
+ case PLL4_PFD3_DIV2:
+ base = &cgc2_regs->pll4div_pfd1;
+ pfd = PLL4_PFD3;
+ index = clk - PLL4_PFD2_DIV1;
break;
default:
return 0;
if (gate)
return 0;
- return cgc1_pll3_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1);
+ return cgc_pll_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1);
+}
+
+u32 cgc1_nic_get_rate(enum cgc_clk clk)
+{
+ u32 reg, rate;
+ u32 scs, nic_ad_divplat, nic_per_divplat;
+ u32 xbar_ad_divplat, xbar_divbus, ad_slow;
+ const enum cgc_clk src[] = {FRO, PLL3_PFD0, SOSC, LVDS};
+
+ reg = readl(&cgc1_regs->nicclk);
+ scs = (reg >> 28) & 0x3;
+ nic_ad_divplat = ((reg >> 21) & 0x3f) + 1;
+ nic_per_divplat = ((reg >> 14) & 0x3f) + 1;
+
+ reg = readl(&cgc1_regs->xbarclk);
+ xbar_ad_divplat = ((reg >> 14) & 0x3f) + 1;
+ xbar_divbus = ((reg >> 7) & 0x3f) + 1;
+ ad_slow = (reg & 0x3f) + 1;
+
+ rate = cgc_clk_get_rate(src[scs]);
+
+ switch (clk) {
+ case NIC_APCLK:
+ rate = rate / nic_ad_divplat;
+ break;
+ case NIC_PERCLK:
+ rate = rate / (nic_ad_divplat * nic_per_divplat);
+ break;
+ case XBAR_APCLK:
+ rate = rate / (nic_ad_divplat * xbar_ad_divplat);
+ break;
+ case XBAR_BUSCLK:
+ rate = rate / (nic_ad_divplat * xbar_ad_divplat * xbar_divbus);
+ break;
+ case AD_SLOWCLK:
+ rate = rate / (nic_ad_divplat * xbar_ad_divplat * ad_slow);
+ break;
+ default:
+ return 0;
+ }
+
+ return rate;
}
-u32 cgc1_sosc_div(enum cgc1_clk clk)
+u32 cgc1_sosc_div(enum cgc_clk clk)
{
u32 reg, gate, index;
return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1);
}
-u32 cgc1_fro_div(enum cgc1_clk clk)
+u32 cgc1_fro_div(enum cgc_clk clk)
{
u32 reg, gate, vld, index;
return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1);
}
-u32 cgc1_clk_get_rate(enum cgc1_clk clk)
+u32 cgc_clk_get_rate(enum cgc_clk clk)
{
switch (clk) {
+ case LVDS:
+ return 0; /* No external LVDS clock used */
case SOSC:
case SOSC_DIV1:
case SOSC_DIV2:
case FRO_DIV3:
return cgc1_fro_div(clk);
case PLL2:
- return decode_pll(PLL2);
case PLL3:
- return decode_pll(PLL3);
+ case PLL4:
+ return decode_pll(clk);
case PLL3_VCODIV:
- return cgc1_pll3_vcodiv_rate();
+ case PLL4_VCODIV:
+ return cgc_pll_vcodiv_rate(clk);
case PLL3_PFD0:
case PLL3_PFD1:
case PLL3_PFD2:
case PLL3_PFD3:
- return cgc1_pll3_pfd_rate(clk);
+ case PLL4_PFD0:
+ case PLL4_PFD1:
+ case PLL4_PFD2:
+ case PLL4_PFD3:
+ return cgc_pll_pfd_rate(clk);
case PLL3_PFD0_DIV1:
case PLL3_PFD0_DIV2:
case PLL3_PFD1_DIV1:
case PLL3_PFD2_DIV2:
case PLL3_PFD3_DIV1:
case PLL3_PFD3_DIV2:
- return cgc1_pll3_pfd_div(clk);
+ case PLL4_PFD0_DIV1:
+ case PLL4_PFD0_DIV2:
+ case PLL4_PFD1_DIV1:
+ case PLL4_PFD1_DIV2:
+ case PLL4_PFD2_DIV1:
+ case PLL4_PFD2_DIV2:
+ case PLL4_PFD3_DIV1:
+ case PLL4_PFD3_DIV2:
+ return cgc_pll_pfd_div(clk);
+ case NIC_APCLK:
+ case NIC_PERCLK:
+ case XBAR_APCLK:
+ case XBAR_BUSCLK:
+ case AD_SLOWCLK:
+ return cgc1_nic_get_rate(clk);
+ case LPAV_AXICLK:
+ case LPAV_AHBCLK:
+ case LPAV_BUSCLK:
+ return cgc2_nic_get_rate(clk);
default:
- printf("Unsupported cgc1 clock: %d\n", clk);
+ printf("Unsupported cgc clock: %d\n", clk);
return 0;
}
}
#define PLL_USB_LOCK_MASK (0x01 << 31)
#define PCC5_LPDDR4_ADDR 0x2da70108
-static void lpuart_set_clk(u32 index, enum cgc1_clk clk)
+static void lpuart_set_clk(u32 index, enum cgc_clk clk)
{
const u32 lpuart_pcc_slots[] = {
LPUART4_PCC3_SLOT,
void init_clk_ddr(void)
{
+ /* disable the ddr pcc */
+ writel(0xc0000000, PCC5_LPDDR4_ADDR);
+
/* enable pll4 and ddrclk*/
cgc2_pll4_init();
cgc2_ddrclk_config(1, 1);
/* enable ddr pcc */
writel(0xd0000000, PCC5_LPDDR4_ADDR);
+ /* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
+ cgc2_ddrclk_wait_unlock();
+
/* for debug */
/* setclkout_ddr(); */
}
return -EINVAL;
}
+ /* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
+ cgc2_ddrclk_wait_unlock();
+
return 0;
}
LPI2C7_PCC4_SLOT << 8 | 4,
};
+ if (i2c_num == 0)
+ return 0;
+
if (i2c_num < 4 || i2c_num > 7)
return -EINVAL;
LPI2C7_PCC4_SLOT << 8 | 4,
};
+ if (i2c_num == 0)
+ return 24000000;
+
if (i2c_num < 4 || i2c_num > 7)
return 0;
return 0;
}
+void enable_mipi_dsi_clk(unsigned char enable)
+{
+ if (enable) {
+ pcc_clock_enable(5, DSI_PCC5_SLOT, false);
+ pcc_reset_peripheral(5, DSI_PCC5_SLOT, true);
+ pcc_clock_sel(5, DSI_PCC5_SLOT, PLL4_PFD3_DIV2);
+ pcc_clock_div_config(5, DSI_PCC5_SLOT, 0, 6);
+ pcc_clock_enable(5, DSI_PCC5_SLOT, true);
+ pcc_reset_peripheral(5, DSI_PCC5_SLOT, false);
+ } else {
+ pcc_clock_enable(5, DSI_PCC5_SLOT, false);
+ pcc_reset_peripheral(5, DSI_PCC5_SLOT, true);
+ }
+}
+
+void enable_adc1_clk(bool enable)
+{
+ if (enable) {
+ pcc_clock_enable(1, ADC1_PCC1_SLOT, false);
+ pcc_clock_sel(1, ADC1_PCC1_SLOT, CM33_BUSCLK);
+ pcc_clock_enable(1, ADC1_PCC1_SLOT, true);
+ pcc_reset_peripheral(1, ADC1_PCC1_SLOT, false);
+ } else {
+ pcc_clock_enable(1, ADC1_PCC1_SLOT, false);
+ }
+}
+
+void reset_lcdclk(void)
+{
+ /* Disable clock and reset dcnano*/
+ pcc_clock_enable(5, DCNANO_PCC5_SLOT, false);
+ pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true);
+}
+
+void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
+{
+ u8 pcd, best_pcd = 0;
+ u32 frac, rate, parent_rate, pfd, div;
+ u32 best_pfd = 0, best_frac = 0, best = 0, best_div = 0;
+ u32 pll4_rate;
+
+ pcc_clock_enable(5, DCNANO_PCC5_SLOT, false);
+
+ pll4_rate = cgc_clk_get_rate(PLL4);
+ pll4_rate = pll4_rate / 1000; /* Change to khz*/
+
+ debug("PLL4 rate %ukhz\n", pll4_rate);
+
+ for (pfd = 12; pfd <= 35; pfd++) {
+ parent_rate = pll4_rate;
+ parent_rate = parent_rate * 18 / pfd;
+
+ for (div = 1; div <= 64; div++) {
+ parent_rate = parent_rate / div;
+
+ for (pcd = 0; pcd < 8; pcd++) {
+ for (frac = 0; frac < 2; frac++) {
+ if (pcd == 0 && frac == 1)
+ continue;
+
+ rate = parent_rate * (frac + 1) / (pcd + 1);
+ if (rate > freq_in_khz)
+ continue;
+
+ if (best == 0 || rate > best) {
+ best = rate;
+ best_pfd = pfd;
+ best_frac = frac;
+ best_pcd = pcd;
+ best_div = div;
+ }
+ }
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz);
+ return;
+ }
+
+ debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_pfd %u, best_div %u\n",
+ freq_in_khz, best, best_frac, best_pcd, best_pfd, best_div);
+
+ cgc2_pll4_pfd_config(PLL4_PFD0, best_pfd);
+ cgc2_pll4_pfddiv_config(PLL4_PFD0_DIV1, best_div - 1);
+
+ pcc_clock_sel(5, DCNANO_PCC5_SLOT, PLL4_PFD0_DIV1);
+ pcc_clock_div_config(5, DCNANO_PCC5_SLOT, best_frac, best_pcd + 1);
+ pcc_clock_enable(5, DCNANO_PCC5_SLOT, true);
+ pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, false);
+}
+
u32 mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ESDHC3_CLK:
return pcc_clock_get_rate(4, SDHC2_PCC4_SLOT);
case MXC_ARM_CLK:
- return cgc1_clk_get_rate(PLL2);
+ return cgc_clk_get_rate(PLL2);
default:
return 0;
}
printf("SDHC1 %8d MHz\n", pcc_clock_get_rate(4, SDHC1_PCC4_SLOT) / 1000000);
printf("SDHC2 %8d MHz\n", pcc_clock_get_rate(4, SDHC2_PCC4_SLOT) / 1000000);
- printf("SOSC %8d MHz\n", cgc1_clk_get_rate(SOSC) / 1000000);
- printf("FRO %8d MHz\n", cgc1_clk_get_rate(FRO) / 1000000);
- printf("PLL2 %8d MHz\n", cgc1_clk_get_rate(PLL2) / 1000000);
- printf("PLL3 %8d MHz\n", cgc1_clk_get_rate(PLL3) / 1000000);
- printf("PLL3_VCODIV %8d MHz\n", cgc1_clk_get_rate(PLL3_VCODIV) / 1000000);
- printf("PLL3_PFD0 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD0) / 1000000);
- printf("PLL3_PFD1 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD1) / 1000000);
- printf("PLL3_PFD2 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD2) / 1000000);
- printf("PLL3_PFD3 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD3) / 1000000);
-
+ printf("SOSC %8d MHz\n", cgc_clk_get_rate(SOSC) / 1000000);
+ printf("FRO %8d MHz\n", cgc_clk_get_rate(FRO) / 1000000);
+ printf("PLL2 %8d MHz\n", cgc_clk_get_rate(PLL2) / 1000000);
+ printf("PLL3 %8d MHz\n", cgc_clk_get_rate(PLL3) / 1000000);
+ printf("PLL3_VCODIV %8d MHz\n", cgc_clk_get_rate(PLL3_VCODIV) / 1000000);
+ printf("PLL3_PFD0 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD0) / 1000000);
+ printf("PLL3_PFD1 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD1) / 1000000);
+ printf("PLL3_PFD2 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD2) / 1000000);
+ printf("PLL3_PFD3 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD3) / 1000000);
+
+ printf("PLL4_PFD0 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0) / 1000000);
+ printf("PLL4_PFD1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1) / 1000000);
+ printf("PLL4_PFD2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2) / 1000000);
+ printf("PLL4_PFD3 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3) / 1000000);
+
+ printf("PLL4_PFD0_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0_DIV1) / 1000000);
+ printf("PLL4_PFD0_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0_DIV2) / 1000000);
+ printf("PLL4_PFD1_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1_DIV1) / 1000000);
+ printf("PLL4_PFD1_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1_DIV2) / 1000000);
+
+ printf("PLL4_PFD2_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2_DIV1) / 1000000);
+ printf("PLL4_PFD2_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2_DIV2) / 1000000);
+ printf("PLL4_PFD3_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3_DIV1) / 1000000);
+ printf("PLL4_PFD3_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3_DIV2) / 1000000);
+
+ printf("LPAV_AXICLK %8d MHz\n", cgc_clk_get_rate(LPAV_AXICLK) / 1000000);
+ printf("LPAV_AHBCLK %8d MHz\n", cgc_clk_get_rate(LPAV_AHBCLK) / 1000000);
+ printf("LPAV_BUSCLK %8d MHz\n", cgc_clk_get_rate(LPAV_BUSCLK) / 1000000);
+ printf("NIC_APCLK %8d MHz\n", cgc_clk_get_rate(NIC_APCLK) / 1000000);
+
+ printf("NIC_PERCLK %8d MHz\n", cgc_clk_get_rate(NIC_PERCLK) / 1000000);
+ printf("XBAR_APCLK %8d MHz\n", cgc_clk_get_rate(XBAR_APCLK) / 1000000);
+ printf("XBAR_BUSCLK %8d MHz\n", cgc_clk_get_rate(XBAR_BUSCLK) / 1000000);
+ printf("AD_SLOWCLK %8d MHz\n", cgc_clk_get_rate(AD_SLOWCLK) / 1000000);
return 0;
}
#include <asm/arch/cgc.h>
#include <asm/arch/sys_proto.h>
-#define cgc1_clk_TYPES 2
-#define cgc1_clk_NUM 8
+#define cgc_clk_TYPES 2
+#define cgc_clk_NUM 8
-static enum cgc1_clk pcc3_clksrc[][8] = {
+static enum cgc_clk pcc1_clksrc[][8] = {
+ {
+ },
+ {
+ DUMMY0_CLK,
+ LPOSC,
+ SOSC_DIV2,
+ FRO_DIV2,
+ CM33_BUSCLK,
+ PLL1_VCO_DIV,
+ PLL0_PFD2_DIV,
+ PLL0_PFD1_DIV,
+ }
+};
+
+static enum cgc_clk pcc3_clksrc[][8] = {
{
},
{ DUMMY0_CLK,
}
};
-static enum cgc1_clk pcc4_clksrc[][8] = {
+static enum cgc_clk pcc4_clksrc[][8] = {
{
DUMMY0_CLK,
SOSC_DIV1,
}
};
+static enum cgc_clk pcc5_clksrc[][8] = {
+ {
+ DUMMY0_CLK,
+ PLL4_PFD3_DIV2,
+ PLL4_PFD2_DIV2,
+ PLL4_PFD2_DIV1,
+ PLL4_PFD1_DIV2,
+ PLL4_PFD1_DIV1,
+ PLL4_PFD0_DIV2,
+ PLL4_PFD0_DIV1
+ },
+ {
+ DUMMY0_CLK,
+ DUMMY1_CLK,
+ LPOSC,
+ SOSC_DIV2,
+ FRO_DIV2,
+ LPAV_BUSCLK,
+ PLL4_VCODIV,
+ PLL4_PFD3_DIV1
+ }
+};
+
+static struct pcc_entry pcc1_arrays[] = {
+ {PCC1_RBASE, ADC1_PCC1_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_HAS_RST_B},
+ {}
+};
+
static struct pcc_entry pcc3_arrays[] = {
{PCC3_RBASE, DMA1_MP_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, DMA1_CH0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{}
};
+static struct pcc_entry pcc5_arrays[] = {
+ {PCC5_RBASE, DMA2_MP_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH0_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH1_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH3_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH4_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH5_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH6_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH7_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH8_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH9_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH10_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH11_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH12_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH13_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH14_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH15_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH16_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH17_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH18_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH19_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH20_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH21_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH22_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH23_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH24_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH25_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH26_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH27_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH28_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH29_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH30_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, DMA2_CH31_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, MU2_B_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, MU3_B_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, SEMA42_2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, CMC2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, AVD_SIM_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, LPAV_CGC_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, PCC5_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, TPM8_PCC5_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, SAI6_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, SAI7_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, SPDIF_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, ISI_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, CSI_REGS_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, CSI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, DSI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, WDOG5_PCC5_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, EPDC_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, PXP_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, SFA2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, GPU2D_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, GPU3D_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, DCNANO_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, LPDDR4_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B },
+ {PCC5_RBASE, CSI_CLK_UI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, CSI_CLK_ESC_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_NO_RST_B },
+ {PCC5_RBASE, RGPIOD_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B },
+ {}
+};
+
static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry **out)
{
struct pcc_entry *pcc_array;
int index = 0;
switch (pcc_controller) {
+ case 1:
+ pcc_array = pcc1_arrays;
+ *out = &pcc1_arrays[0];
+ break;
case 3:
pcc_array = pcc3_arrays;
*out = &pcc3_arrays[0];
pcc_array = pcc4_arrays;
*out = &pcc4_arrays[0];
break;
+ case 5:
+ pcc_array = pcc5_arrays;
+ *out = &pcc5_arrays[0];
+ break;
default:
printf("Not supported pcc_controller: %d\n", pcc_controller);
return -EINVAL;
}
/* The clock source select needs clock is disabled */
-int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src)
+int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src)
{
u32 val, i, clksrc_type;
void __iomem *reg;
struct pcc_entry *pcc_array;
- enum cgc1_clk *cgc1_clk_array;
+ enum cgc_clk *cgc_clk_array;
int clk;
clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array);
return -EPERM;
}
- if (pcc_controller == 3)
- cgc1_clk_array = pcc3_clksrc[clksrc_type];
+ if (pcc_controller == 1)
+ cgc_clk_array = pcc1_clksrc[clksrc_type];
+ else if (pcc_controller == 3)
+ cgc_clk_array = pcc3_clksrc[clksrc_type];
+ else if (pcc_controller == 4)
+ cgc_clk_array = pcc4_clksrc[clksrc_type];
else
- cgc1_clk_array = pcc4_clksrc[clksrc_type];
+ cgc_clk_array = pcc5_clksrc[clksrc_type];
- for (i = 0; i < cgc1_clk_NUM; i++) {
- if (cgc1_clk_array[i] == src) {
+ for (i = 0; i < cgc_clk_NUM; i++) {
+ if (cgc_clk_array[i] == src) {
/* Find the clock src, then set it to PCS */
break;
}
}
- if (i == cgc1_clk_NUM) {
+ if (i == cgc_clk_NUM) {
printf("No parent in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
return -EINVAL;
}
return false;
}
-int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src)
+int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src)
{
u32 val, clksrc_type;
void __iomem *reg;
struct pcc_entry *pcc_array;
int clk;
- enum cgc1_clk *cgc1_clk_array;
+ enum cgc_clk *cgc_clk_array;
clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array);
if (clk < 0)
}
if (pcc_controller == 3)
- cgc1_clk_array = pcc3_clksrc[clksrc_type];
+ cgc_clk_array = pcc3_clksrc[clksrc_type];
+ else if (pcc_controller == 4)
+ cgc_clk_array = pcc4_clksrc[clksrc_type];
else
- cgc1_clk_array = pcc4_clksrc[clksrc_type];
+ cgc_clk_array = pcc5_clksrc[clksrc_type];
- *src = cgc1_clk_array[val];
+ *src = cgc_clk_array[val];
debug("%s: parent cgc1 clk %d\n", __func__, *src);
{
u32 val, rate, frac, div;
void __iomem *reg;
- enum cgc1_clk parent;
+ enum cgc_clk parent;
int ret;
int clk;
struct pcc_entry *pcc_array;
if (ret)
return 0;
- rate = cgc1_clk_get_rate(parent);
+ rate = cgc_clk_get_rate(parent);
debug("%s: parent rate %u\n", __func__, rate);
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
+#include <fuse.h>
+#include <thermal.h>
DECLARE_GLOBAL_DATA_PTR;
cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
+ printf("CPU: i.MX%s rev%d.%d at %d MHz\n",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
+#if defined(CONFIG_IMX_PMC_TEMPERATURE)
+ struct udevice *udev;
+ int ret, temp;
+
+ ret = uclass_get_device(UCLASS_THERMAL, 0, &udev);
+ if (!ret) {
+ ret = thermal_get_temp(udev, &temp);
+ if (!ret)
+ printf("CPU current temperature: %d\n", temp);
+ else
+ debug(" - failed to get CPU current temperature\n");
+ } else {
+ debug(" - failed to get CPU current temperature\n");
+ }
+#endif
+
printf("Reset cause: %s\n", get_reset_cause(cause));
printf("Boot mode: ");
/* Iomuxc0: : PBridge1 slot 33 */
trdc_mbc_set_access(2, 7, 1, 33, false);
+ /* flexspi0 */
+ trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false);
+
+ /* tpm0: PBridge1 slot 21 */
+ trdc_mbc_set_access(2, 7, 1, 21, false);
+ /* lpi2c0: PBridge1 slot 24 */
+ trdc_mbc_set_access(2, 7, 1, 24, false);
return 0;
}
+void lpav_configure(void)
+{
+ /* LPAV to APD */
+ setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7));
+
+ /* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */
+ setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F);
+
+ /* LPAV slave/dma2 ch allocation and request allocation to APD */
+ writel(0x1f, SIM_SEC_BASE_ADDR + 0x50);
+ writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54);
+ writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58);
+}
+
+void load_lposc_fuse(void)
+{
+ int ret;
+ u32 val = 0, val2 = 0, reg;
+
+ ret = fuse_read(25, 0, &val);
+ if (ret)
+ return; /* failed */
+
+ ret = fuse_read(25, 1, &val2);
+ if (ret)
+ return; /* failed */
+
+ /* LPOSCCTRL */
+ reg = readl(0x2802f304);
+ reg &= ~0xff;
+ reg |= (val & 0xff);
+ writel(reg, 0x2802f304);
+}
+
+void set_lpav_qos(void)
+{
+ /* Set read QoS of dcnano on LPAV NIC */
+ writel(0xf, 0x2e447100);
+}
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ u32 val = 0;
+ int ret;
+ bool rdc_en = true; /* Default assume DBD_EN is set */
+
/* Disable wdog */
init_wdog();
+ /* Read DBD_EN fuse */
+ ret = fuse_read(8, 1, &val);
+ if (!ret)
+ rdc_en = !!(val & 0x4000);
+
if (get_boot_mode() == SINGLE_BOOT) {
- release_rdc(RDC_TRDC);
+ if (rdc_en)
+ release_rdc(RDC_TRDC);
+
trdc_set_access();
- /* LPAV to APD */
- setbits_le32(0x2802B044, BIT(7));
- /* GPU 2D/3D to APD */
- setbits_le32(0x2802B04C, BIT(1) | BIT(2));
- /* DCNANO and MIPI_DSI to APD */
- setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4));
+
+ lpav_configure();
}
- /* release xrdc, then allow A35 to write SRAM2 */
- release_rdc(RDC_XRDC);
+ /* Release xrdc, then allow A35 to write SRAM2 */
+ if (rdc_en)
+ release_rdc(RDC_XRDC);
+
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
clock_init();
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
+ u32 val[2] = {};
+ int ret;
+
+ ret = fuse_read(5, 3, &val[0]);
+ if (ret)
+ goto err;
+
+ ret = fuse_read(5, 4, &val[1]);
+ if (ret)
+ goto err;
+
+ mac[0] = val[0];
+ mac[1] = val[0] >> 8;
+ mac[2] = val[0] >> 16;
+ mac[3] = val[0] >> 24;
+ mac[4] = val[1];
+ mac[5] = val[1] >> 8;
+
+ debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
+ __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ return;
+err:
memset(mac, 0, 6);
+ printf("%s: fuse read err: %d\n", __func__, ret);
}
int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
* 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
*/
if (is_mx6ull()) {
+ static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7};
+
val = readl(&fuse->mem0);
val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
val &= 0x7;
- writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+ writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
&anatop->ana_misc0_set);
}
}
if (is_mx6dqp())
noc_setup();
#endif
+
+ enable_ca7_smp();
+
return 0;
}
static int mmc_get_boot_dev(void)
{
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- u32 soc_sbmr = readl(&src_regs->sbmr1);
+ u32 soc_sbmr = imx6_src_get_boot_mode();
u32 bootsel;
int devno;
#include <asm/mach-imx/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>
#include <dm.h>
imx_gpcv2_init();
+ enable_ca7_smp();
+
return 0;
}
#else
Select this option to enable the PMC1 LDO.
config MX7ULP
+ select ARCH_SUPPORT_PSCI
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select HAS_CAAM
bool
bool "Support MX7ULP COM board"
select MX7ULP
select SYS_ARCH_TIMER
+ select SPL_DM if SPL
+ select SPL_GPIO_SUPPORT if SPL
+ select SPL_LIBCOMMON_SUPPORT if SPL
+ select SPL_LIBDISK_SUPPORT if SPL
+ select SPL_LIBGENERIC_SUPPORT if SPL
+ select SPL_MMC_SUPPORT if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_OF_LIBFDT if SPL
+ select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SPL_SERIAL_SUPPORT if SPL
+ select SUPPORT_SPL
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/sys_proto.h>
#include <asm/setup.h>
#include <linux/bitops.h>
int arch_cpu_init(void)
{
+ enable_ca7_smp();
return 0;
}
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
/* EIM: See 8.5.1, Table 8-9 */
- case IMX6_BMODE_EMI:
+ case IMX6_BMODE_EIM:
/* BOOT_CFG1[3]: NOR/OneNAND Selection */
- switch ((reg & IMX6_BMODE_EMI_MASK) >> IMX6_BMODE_EMI_SHIFT) {
+ switch ((reg & IMX6_BMODE_EIM_MASK) >> IMX6_BMODE_EIM_SHIFT) {
case IMX6_BMODE_ONENAND:
return BOOT_DEVICE_ONENAND;
case IMX6_BMODE_NOR:
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*/
-#define __ASSEMBLY__
#include <config.h>
IMAGE_VERSION 2
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*/
-#define __ASSEMBLY__
#include <config.h>
IMAGE_VERSION 2
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
+config SOC_K3_J721S2
+ bool "TI's K3 based J721S2 SoC Family Support"
+
config SOC_K3_AM642
bool "TI's K3 based AM642 SoC Family Support"
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x80000 if SOC_K3_AM6
- default 0x100000 if SOC_K3_J721E
+ default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x1c0000 if SOC_K3_AM642
help
Describes the total size of the MCU or OCMC MSRAM present on
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM6
- default 0xc0000 if SOC_K3_J721E
+ default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x180000 if SOC_K3_AM642
help
Describes the maximum size of the image that ROM can download
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x40280000 if SOC_K3_AM6
- default 0x40280000 if SOC_K3_J721E
+ default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM6
- default 0x200 if SOC_K3_J721E
+ default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the size of MCU Scratchpad RAM.
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41cffbfc if SOC_K3_J721E
+ default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
help
Address at which ROM stores the value which determines if SPL
config K3_DM_FW
bool "Separate DM firmware image"
- depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
+ depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
+source "board/ti/j721s2/Kconfig"
endif
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
#endif /* CONFIG_SOC_K3_J721E */
+#ifdef CONFIG_SOC_K3_J721S2
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x500000000UL,
+ .phys = 0x500000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = j721s2_mem_map;
+
+#endif /* CONFIG_SOC_K3_J721S2 */
+
#ifdef CONFIG_SOC_K3_AM642
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
#endif
}
-#ifdef CONFIG_FS_LOADER
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
{
struct udevice *fsdev;
char *name = NULL;
int size = 0;
+ if (!IS_ENABLED(CONFIG_FS_LOADER))
+ return 0;
+
*loadaddr = 0;
#ifdef CONFIG_SPL_ENV_SUPPORT
switch (spl_boot_device()) {
return size;
}
-#else
-int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
-{
- return 0;
-}
-#endif
__weak void release_resources_for_core_shutdown(void)
{
#include "j721e_hardware.h"
#endif
+#ifdef CONFIG_SOC_K3_J721S2
+#include "j721s2_hardware.h"
+#endif
+
#ifdef CONFIG_SOC_K3_AM642
#include "am64_hardware.h"
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J721S2 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_J721S2_HARDWARE_H
+#define __ASM_ARCH_J721S2_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define CTRL_MMR0_BASE 0x00100000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+
+#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
+#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
+
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define MCU_CTRL_MMR0_BASE 0x40f00000
+
+#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
+#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
+ * shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0 0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
+#define CTRLMMR_LOCK_KICK1 0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
+/* ROM HANDOFF Structure location */
+#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00
+
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
+#endif /* __ASM_ARCH_J721S2_HARDWARE_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * David Huang <d-huang@ti.com>
+ */
+#ifndef _ASM_ARCH_J721S2_SPL_H_
+#define _ASM_ARCH_J721S2_SPL_H_
+
+/* With BootMode B = 0 */
+#include <linux/bitops.h>
+#define BOOT_DEVICE_HYPERFLASH 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
+
+/* With BootMode B = 1 */
+#define BOOT_DEVICE_MMC2 0x10
+#define BOOT_DEVICE_MMC1 0x11
+#define BOOT_DEVICE_DFU 0x12
+#define BOOT_DEVICE_UFS 0x13
+#define BOOT_DEVIE_GPMC 0x14
+#define BOOT_DEVICE_PCIE 0x15
+#define BOOT_DEVICE_XSPI 0x16
+#define BOOT_DEVICE_RAM 0x17
+#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */
+
+/* Backup boot modes with MCU Only = 0 */
+#define BACKUP_BOOT_DEVICE_RAM 0x0
+#define BACKUP_BOOT_DEVICE_USB 0x1
+#define BACKUP_BOOT_DEVICE_UART 0x3
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x4
+#define BACKUP_BOOT_DEVICE_MMC2 0x5
+#define BACKUP_BOOT_DEVICE_SPI 0x6
+#define BACKUP_BOOT_DEVICE_I2C 0x7
+
+#define BOOT_MODE_B_SHIFT 4
+#define BOOT_MODE_B_MASK BIT(4)
+
+#define K3_PRIMARY_BOOTMODE 0x0
+#define K3_BACKUP_BOOTMODE 0x1
+
+#endif
#include "j721e_spl.h"
#endif
+#ifdef CONFIG_SOC_K3_J721S2
+#include "j721s2_spl.h"
+#endif
+
#ifdef CONFIG_SOC_K3_AM642
#include "am64_spl.h"
#endif
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <fdtdec.h>
#include <mmc.h>
#include <remoteproc.h>
sizeof(struct rom_extended_boot_data));
}
+#ifdef CONFIG_SPL_OF_LIST
+void do_dt_magic(void)
+{
+ int ret, rescan, mmc_dev = -1;
+ static struct mmc *mmc;
+
+ if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+ do_board_detect();
+
+ /*
+ * Board detection has been done.
+ * Let us see if another dtb wouldn't be a better match
+ * for our board
+ */
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ ret = fdtdec_resetup(&rescan);
+ if (!ret && rescan) {
+ dm_uninit();
+ dm_init_and_scan(true);
+ }
+ }
+
+ /*
+ * Because of multi DTB configuration, the MMC device has
+ * to be re-initialized after reconfiguring FDT inorder to
+ * boot from MMC. Do this when boot mode is MMC and ROM has
+ * not loaded SYSFW.
+ */
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+ mmc_dev = 0;
+ break;
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
+ mmc_dev = 1;
+ break;
+ }
+
+ if (mmc_dev > 0 && !is_rom_loaded_sysfw(&bootdata)) {
+ ret = mmc_init_device(mmc_dev);
+ if (!ret) {
+ mmc = find_mmc_device(mmc_dev);
+ if (mmc) {
+ ret = mmc_init(mmc);
+ if (ret) {
+ printf("mmc init failed with error: %d\n", ret);
+ }
+ }
+ }
+ }
+}
+#endif
+
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
k3_mmc_stop_clock, k3_mmc_restart_clock);
+#ifdef CONFIG_SPL_OF_LIST
+ do_dt_magic();
+#endif
+
/*
* Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721S2 specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Dave Gerlach <d-gerlach@ti.com>.
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ "osc_19_2_mhz",
+ "osc_20_mhz",
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi0_dqs_out",
+ "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi1_dqs_out",
+ "fss_mcu_0_ospi_1_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ NULL,
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+ "wkup_fref_clksel_out0",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcu_usart_clksel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out19_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const emmcsd1_lb_clksel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const mcu_clkout_mux_out0_parents[] = {
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+ "main_pll_hfosc_sel_out0",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const dpi0_ext_clksel_out0_parents[] = {
+ "hsdiv1_16fft_main_19_hsdivout0_clk",
+ "board_0_vout0_extpclkin_out",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout1_clk",
+ "postdiv3_16fft_main_0_hsdivout6_clk",
+ "board_0_mcu_cpts0_rft_clk_out",
+ "board_0_cpts0_rft_clk_out",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const struct clk_data clk_list[] = {
+ CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+ CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+ CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+ CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+ CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+ CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+ CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+ CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
+ CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
+ CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
+ CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
+ CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
+ CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
+ CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
+ CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+ CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+ CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+ CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
+ CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
+ CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ddr0_ckn_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ddr0_ckp_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ddr1_ckn_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ddr1_ckp_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
+ CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
+ CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
+ CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck", 0, 0),
+ CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
+ CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck", 0, 0),
+ CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n", 0, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+ CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
+ CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
+ CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
+ CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
+ CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+ CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
+ CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
+ CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+ CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+ CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
+ DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+ DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(43, 3, "board_0_hfosc1_clk_out"),
+ DEV_CLK(43, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(43, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(43, 7, "board_0_hfosc1_clk_out"),
+ DEV_CLK(43, 9, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(43, 10, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+ DEV_CLK(43, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(43, 12, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 1, "gtc_clk_mux_out0"),
+ DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+ DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
+ DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
+ DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
+ DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
+ DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+ DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(98, 1, "emmcsd_refclk_sel_out0"),
+ DEV_CLK(98, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(98, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(98, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(98, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(98, 6, "emmcsd1_lb_clksel_out0"),
+ DEV_CLK(98, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(99, 1, "emmcsd_refclk_sel_out1"),
+ DEV_CLK(99, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(99, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(99, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(99, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(99, 7, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(99, 8, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(108, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(108, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(108, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(108, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(108, 11, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(109, 0, "mcu_ospi0_iclk_sel_out0"),
+ DEV_CLK(109, 1, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(109, 2, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(109, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(109, 5, "mcu_ospi_ref_clk_sel_out0"),
+ DEV_CLK(109, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(109, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(109, 8, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(109, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(110, 0, "mcu_ospi1_iclk_sel_out0"),
+ DEV_CLK(110, 1, "board_0_mcu_ospi1_dqs_out"),
+ DEV_CLK(110, 2, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(110, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(110, 5, "mcu_ospi_ref_clk_sel_out1"),
+ DEV_CLK(110, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(110, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(110, 8, "board_0_mcu_ospi1_dqs_out"),
+ DEV_CLK(110, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(115, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(126, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(126, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(138, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(138, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(138, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(138, 3, "board_0_ddr0_ckn_out"),
+ DEV_CLK(138, 5, "board_0_ddr0_ckp_out"),
+ DEV_CLK(138, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(139, 0, "hsdiv0_16fft_main_26_hsdivout0_clk"),
+ DEV_CLK(139, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(139, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(139, 3, "board_0_ddr1_ckn_out"),
+ DEV_CLK(139, 5, "board_0_ddr1_ckp_out"),
+ DEV_CLK(139, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(143, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(143, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(146, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(146, 3, "usart_programmable_clock_divider_out0"),
+ DEV_CLK(149, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(149, 3, "mcu_usart_clksel_out0"),
+ DEV_CLK(149, 4, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+ DEV_CLK(149, 5, "postdiv3_16fft_main_1_hsdivout5_clk"),
+ DEV_CLK(157, 9, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 103, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 104, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck"),
+ DEV_CLK(157, 111, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 174, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck"),
+ DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 179, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 182, "mshsi2c_wkup_0_porscl"),
+ DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
+ DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
+ DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
+ DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
+ DEV_CLK(157, 222, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
+ DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+ DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
+ DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(223, 1, "wkup_i2c_mcupll_bypass_out0"),
+ DEV_CLK(223, 2, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+ DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
+ DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
+ DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(360, 13, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(360, 15, "postdiv3_16fft_main_1_hsdivout7_clk"),
+ DEV_CLK(360, 16, "usb0_refclk_sel_out0"),
+ DEV_CLK(360, 17, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(360, 18, "board_0_hfosc1_clk_out"),
+ DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+};
+
+const struct ti_k3_clk_platdata j721s2_clk_platdata = {
+ .clk_list = clk_list,
+ .clk_list_cnt = 104,
+ .soc_dev_clk_data = soc_dev_clk_data,
+ .soc_dev_clk_data_cnt = 122,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721S2 specific device platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Dave Gerlach <d-gerlach@ti.com>.
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+ [0] = PSC(0, 0x42000000),
+ [1] = PSC(1, 0x00400000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+ [0] = PSC_PD(0, &soc_psc_list[0], NULL),
+ [1] = PSC_PD(0, &soc_psc_list[1], NULL),
+ [2] = PSC_PD(1, &soc_psc_list[1], &soc_pd_list[1]),
+ [3] = PSC_PD(14, &soc_psc_list[1], NULL),
+ [4] = PSC_PD(15, &soc_psc_list[1], &soc_pd_list[3]),
+ [5] = PSC_PD(16, &soc_psc_list[1], &soc_pd_list[3]),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+ [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [5] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[1], NULL),
+ [6] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[2]),
+ [7] = PSC_LPSC(14, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
+ [8] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[1], NULL),
+ [9] = PSC_LPSC(16, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[10]),
+ [10] = PSC_LPSC(17, &soc_psc_list[1], &soc_pd_list[1], NULL),
+ [11] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
+ [12] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
+ [13] = PSC_LPSC(25, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
+ [14] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], NULL),
+ [15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[2], NULL),
+ [16] = PSC_LPSC(78, &soc_psc_list[1], &soc_pd_list[3], NULL),
+ [17] = PSC_LPSC(80, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[16]),
+ [18] = PSC_LPSC(81, &soc_psc_list[1], &soc_pd_list[5], &soc_lpsc_list[16]),
+};
+
+static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(108, &soc_lpsc_list[0]),
+ PSC_DEV(109, &soc_lpsc_list[0]),
+ PSC_DEV(110, &soc_lpsc_list[0]),
+ PSC_DEV(180, &soc_lpsc_list[0]),
+ PSC_DEV(149, &soc_lpsc_list[0]),
+ PSC_DEV(115, &soc_lpsc_list[1]),
+ PSC_DEV(223, &soc_lpsc_list[1]),
+ PSC_DEV(109, &soc_lpsc_list[2]),
+ PSC_DEV(110, &soc_lpsc_list[3]),
+ PSC_DEV(108, &soc_lpsc_list[4]),
+ PSC_DEV(43, &soc_lpsc_list[5]),
+ PSC_DEV(61, &soc_lpsc_list[6]),
+ PSC_DEV(96, &soc_lpsc_list[7]),
+ PSC_DEV(138, &soc_lpsc_list[8]),
+ PSC_DEV(97, &soc_lpsc_list[9]),
+ PSC_DEV(139, &soc_lpsc_list[10]),
+ PSC_DEV(360, &soc_lpsc_list[11]),
+ PSC_DEV(99, &soc_lpsc_list[12]),
+ PSC_DEV(98, &soc_lpsc_list[13]),
+ PSC_DEV(146, &soc_lpsc_list[14]),
+ PSC_DEV(357, &soc_lpsc_list[15]),
+ PSC_DEV(4, &soc_lpsc_list[16]),
+ PSC_DEV(202, &soc_lpsc_list[17]),
+ PSC_DEV(203, &soc_lpsc_list[18]),
+};
+
+const struct ti_k3_pd_platdata j721s2_pd_platdata = {
+ .psc = soc_psc_list,
+ .pd = soc_pd_list,
+ .lpsc = soc_lpsc_list,
+ .devs = soc_dev_list,
+ .num_psc = 2,
+ .num_pd = 6,
+ .num_lpsc = 19,
+ .num_devs = 24,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E: SoC specific initialization
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * David Huang <d-huang@ti.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <mmc.h>
+#include <remoteproc.h>
+
+#ifdef CONFIG_SPL_BUILD
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 3);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 7);
+}
+
+void k3_mmc_stop_clock(void)
+{
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc->saved_clock = mmc->clock;
+ mmc_set_clock(mmc, 0, true);
+ }
+ }
+}
+
+void k3_mmc_restart_clock(void)
+{
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc_set_clock(mmc, mmc->saved_clock, false);
+ }
+ }
+}
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __attribute__((section(".data")));
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+ /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+ */
+ store_boot_info_from_rom();
+
+ /* Make all control module registers accessible */
+ ctrl_mmr_unlock();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ disable_linefill_optimization();
+ setup_k3_mpu_regions();
+ }
+
+ /* Init DM early */
+ spl_early_init();
+
+ /* Prepare console output */
+ preloader_console_init();
+
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ /*
+ * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
+ * regardless of the result of pinctrl. Do this without probing the
+ * device, but instead by searching the device that would request the
+ * given sequence number if probed. The UART will be used by the system
+ * firmware (SYSFW) image for various purposes and SYSFW depends on us
+ * to initialize its pin settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ /*
+ * Load, start up, and configure system controller firmware. Provide
+ * the U-Boot console init function to the SYSFW post-PM configuration
+ * callback hook, effectively switching on (or over) the console
+ * output.
+ */
+ k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
+ k3_mmc_stop_clock, k3_mmc_restart_clock);
+
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ /*
+ * Force probe of clk_k3 driver here to ensure basic default clock
+ * configuration is always done for enabling PM services.
+ */
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ &dev);
+ if (ret)
+ panic("Failed to initialize clk-k3!\n");
+ }
+ }
+
+ /* Output System Firmware version info */
+ k3_sysfw_print_ver();
+
+ if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
+ ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
+ if (ret)
+ panic("Probe of msmc failed: %d\n", ret);
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("DRAM 0 init failed: %d\n", ret);
+
+ ret = uclass_next_device(&dev);
+ if (ret)
+ panic("DRAM 1 init failed: %d\n", ret);
+ }
+ spl_enable_dcache();
+}
+
+u32 spl_mmc_boot_mode(const u32 boot_device)
+{
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return MMCSD_MODE_EMMCBOOT;
+ case BOOT_DEVICE_MMC2:
+ return MMCSD_MODE_FS;
+ default:
+ return MMCSD_MODE_RAW;
+ }
+}
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+ u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
+
+ switch (bkup_boot) {
+ case BACKUP_BOOT_DEVICE_USB:
+ return BOOT_DEVICE_DFU;
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+ case BACKUP_BOOT_DEVICE_MMC2:
+ {
+ u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
+ if (port == 0x0)
+ return BOOT_DEVICE_MMC1;
+ return BOOT_DEVICE_MMC2;
+ }
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+ }
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
+{
+ u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+
+ bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
+ BOOT_MODE_B_SHIFT;
+
+ if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
+ bootmode == BOOT_DEVICE_XSPI)
+ bootmode = BOOT_DEVICE_SPI;
+
+ if (bootmode == BOOT_DEVICE_MMC2) {
+ u32 port = (main_devstat &
+ MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
+ if (port == 0x0)
+ bootmode = BOOT_DEVICE_MMC1;
+ }
+
+ return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
+ u32 main_devstat;
+
+ if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
+ printf("ERROR: MCU only boot is not yet supported\n");
+ return BOOT_DEVICE_RAM;
+ }
+
+ /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
+ main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+ if (bootindex == K3_PRIMARY_BOOTMODE)
+ return __get_primary_bootmedia(main_devstat, wkup_devstat);
+ else
+ return __get_backup_bootmedia(main_devstat);
+}
+#endif
+
+#define J721S2_DEV_MCU_RTI0 295
+#define J721S2_DEV_MCU_RTI1 296
+#define J721S2_DEV_MCU_ARMSS0_CPU0 284
+#define J721S2_DEV_MCU_ARMSS0_CPU1 285
+
+void release_resources_for_core_shutdown(void)
+{
+ if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
+ struct ti_sci_handle *ti_sci;
+ struct ti_sci_dev_ops *dev_ops;
+ struct ti_sci_proc_ops *proc_ops;
+ int ret;
+ u32 i;
+
+ const u32 put_device_ids[] = {
+ J721S2_DEV_MCU_RTI0,
+ J721S2_DEV_MCU_RTI1,
+ };
+
+ ti_sci = get_ti_sci_handle();
+ dev_ops = &ti_sci->ops.dev_ops;
+ proc_ops = &ti_sci->ops.proc_ops;
+
+ /* Iterate through list of devices to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+ u32 id = put_device_ids[i];
+
+ ret = dev_ops->put_device(ti_sci, id);
+ if (ret)
+ panic("Failed to put device %u (%d)\n", id, ret);
+ }
+
+ const u32 put_core_ids[] = {
+ J721S2_DEV_MCU_ARMSS0_CPU1,
+ J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
+ };
+
+ /* Iterate through list of cores to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+ u32 id = put_core_ids[i];
+
+ /*
+ * Queue up the core shutdown request. Note that this call
+ * needs to be followed up by an actual invocation of an WFE
+ * or WFI CPU instruction.
+ */
+ ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+ if (ret)
+ panic("Failed sending core %u shutdown message (%d)\n",
+ id, ret);
+ }
+ }
+}
#ifdef CONFIG_IDE
#define __io
/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* CONFIG_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 2
/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
#endif /* CONFIG_IDE */
/* Use common timer */
At level 3, rovides the windows margin of each DQ as a results of
DQS centeralization.
+config DDR_RESET_ON_TRAINING_FAILURE
+ bool "Reset the board on DDR training failure instead of hanging"
+ depends on ARMADA_38X || ARMADA_XP
+ help
+ If DDR training fails in SPL, reset the board instead of hanging.
+ Some boards are known to fail DDR training occasionally and an
+ immediate reset may be preferable to waiting until the board is
+ reset by watchdog (if there even is one).
+
+ Note that if booting via UART and the DDR training fails, the
+ device will still hang - it doesn't make sense to reset the board
+ in such a case.
+
config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG
default "helios4" if TARGET_HELIOS4
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
+#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
#define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
#define MVEBU_CPU_DEC_WIN_GRANULARITY 16
#define MVEBU_CPU_DEC_WINS 5
+#define MVEBU_CPU_DEC_CCI_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
+#define MVEBU_CPU_DEC_ROM_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xf4)
-#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2)
+#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 4)
#define A3700_PTE_BLOCK_NORMAL \
(PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
{
/*
* SRAM, MMIO regions
- * Don't remove this, a3700_build_mem_map needs it.
+ * Don't remove this, build_mem_map needs it.
*/
.phys = SOC_REGS_PHY_BASE,
.virt = SOC_REGS_PHY_BASE,
static void build_mem_map(void)
{
int win, region;
+ u32 reg;
region = 1;
+
+ /* CCI-400 */
+ reg = readl(MVEBU_CPU_DEC_CCI_BASE);
+ mvebu_mem_map[region].phys = reg << 20;
+ mvebu_mem_map[region].virt = reg << 20;
+ mvebu_mem_map[region].size = SZ_64K;
+ mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_DEVICE;
+ ++region;
+
+ /* AP BootROM */
+ reg = readl(MVEBU_CPU_DEC_ROM_BASE);
+ mvebu_mem_map[region].phys = reg << 20;
+ mvebu_mem_map[region].virt = reg << 20;
+ mvebu_mem_map[region].size = SZ_1M;
+ mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_NORMAL;
+ ++region;
+
for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
u32 base, tgt, size;
u64 attrs;
void enable_caches(void)
{
- build_mem_map();
-
icache_enable();
dcache_enable();
}
{
int win;
+ build_mem_map();
+
gd->ram_size = 0;
for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
u32 base, tgt, size;
*/
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
#include <fdtdec.h>
#include <hang.h>
ret = ddr3_init();
if (ret) {
printf("ddr3_init() failed: %d\n", ret);
- hang();
+ if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
+ get_boot_device() != BOOT_DEVICE_UART)
+ reset_cpu();
+ else
+ hang();
}
#endif
#include <common.h>
#include <ahci.h>
#include <log.h>
+#include <dm/uclass.h>
+#include <fs_loader.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/omap_common.h>
#include <watchdog.h>
#include <scsi.h>
#include <i2c.h>
+#include <remoteproc.h>
DECLARE_GLOBAL_DATA_PTR;
+#define IPU1_LOAD_ADDR (0xa17ff000)
+#define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
+#define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
+
__weak u32 omap_sys_boot_device(void)
{
return BOOT_DEVICE_NONE;
return gd->arch.omap_boot_mode;
}
+int load_firmware(char *name_fw, u32 *loadaddr)
+{
+ struct udevice *fsdev;
+ int size = 0;
+
+ if (!IS_ENABLED(CONFIG_FS_LOADER))
+ return 0;
+
+ if (!*loadaddr)
+ return 0;
+
+ if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
+ size = request_firmware_into_buf(fsdev, name_fw,
+ (void *)*loadaddr, 0, 0);
+ }
+
+ return size;
+}
+
+void spl_boot_ipu(void)
+{
+ int ret, size;
+ u32 loadaddr = IPU1_LOAD_ADDR;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) ||
+ !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+ return;
+
+ size = load_firmware("dra7-ipu1-fw.xem4", &loadaddr);
+ if (size <= 0) {
+ pr_err("Firmware loading failed\n");
+ goto skip_ipu1;
+ }
+
+ enable_ipu1_clocks();
+ ret = rproc_dev_init(0);
+ if (ret) {
+ debug("%s: IPU1 failed to initialize on rproc (%d)\n",
+ __func__, ret);
+ goto skip_ipu1;
+ }
+
+ ret = rproc_load(0, IPU1_LOAD_ADDR, 0x2000000);
+ if (ret) {
+ debug("%s: IPU1 failed to load on rproc (%d)\n", __func__,
+ ret);
+ goto skip_ipu1;
+ }
+
+ debug("Starting IPU1...\n");
+
+ ret = rproc_start(0);
+ if (ret)
+ debug("%s: IPU1 failed to start (%d)\n", __func__, ret);
+
+skip_ipu1:
+ loadaddr = IPU2_LOAD_ADDR;
+ size = load_firmware("dra7-ipu2-fw.xem4", &loadaddr);
+ if (size <= 0) {
+ pr_err("Firmware loading failed for ipu2\n");
+ return;
+ }
+
+ enable_ipu2_clocks();
+ ret = rproc_dev_init(1);
+ if (ret) {
+ debug("%s: IPU2 failed to initialize on rproc (%d)\n", __func__,
+ ret);
+ return;
+ }
+
+ ret = rproc_load(1, IPU2_LOAD_ADDR, 0x2000000);
+ if (ret) {
+ debug("%s: IPU2 failed to load on rproc (%d)\n", __func__,
+ ret);
+ return;
+ }
+
+ debug("Starting IPU2...\n");
+
+ ret = rproc_start(1);
+ if (ret)
+ debug("%s: IPU2 failed to start (%d)\n", __func__, ret);
+}
+
void spl_board_init(void)
{
/* Prepare console output */
#ifdef CONFIG_AM33XX
am33xx_spl_board_init();
#endif
+ if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+ IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+ spl_boot_ipu();
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
}
}
+void do_enable_ipu_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
+ u8 wait_for_enable)
+{
+ u32 i, max = 10;
+
+ if (!IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+ return;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in HW_AUTO */
+ for (i = 0; (i < max) && clk_modules_hw_auto &&
+ clk_modules_hw_auto[i]; i++) {
+ enable_clock_module(clk_modules_hw_auto[i],
+ MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+ wait_for_enable);
+ };
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i < max) && clk_modules_explicit_en &&
+ clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+}
+
void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable,
u8 wait_for_disable)
* get_sdr_cs_size -
* - Get size of chip select 0/1
*/
-u32 get_sdr_cs_size(u32 cs)
+static u32 get_sdr_cs_size(u32 cs)
{
u32 size = 0;
}
/*
+ * get_sdr_cs_size -
+ * - Get size of chip select 0/1
+ */
+static u32 get_sdr_cs_size(u32 cs)
+{
+ u32 size;
+
+ /* get ram size field */
+ size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+ size &= 0x3FF; /* remove unwanted bits */
+ size <<= 21; /* multiply by 2 MiB to find size in MB */
+ return size;
+}
+
+/*
* make_cs1_contiguous -
* - When we have CS1 populated we want to have it mapped after cs0 to allow
* command line mem=xyz use all memory with out discontinuous support
* compiled in. We could do it in the ATAG, but there really is two banks...
*/
-void make_cs1_contiguous(void)
+static void make_cs1_contiguous(void)
{
u32 size, a_add_low, a_add_high;
}
-
-/*
- * get_sdr_cs_size -
- * - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
- u32 size;
-
- /* get ram size field */
- size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
- size &= 0x3FF; /* remove unwanted bits */
- size <<= 21; /* multiply by 2 MiB to find size in MB */
- return size;
-}
-
/*
* get_sdr_cs_offset -
* - Get offset of cs from cs0 start
* true and a possible 2nd time depending on memory configuration from
* stack+global context.
*/
-void do_sdrc_init(u32 cs, u32 early)
+static void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
struct board_sdrc_timings timings;
/******************************************
* get_cpu_type(void) - extract cpu info
******************************************/
-u32 get_cpu_type(void)
+static u32 get_cpu_type(void)
{
return readl(&ctrl_base->ctrl_omap_stat);
}
* get_cpu_id(void) - extract cpu id
* returns 0 for ES1.0, cpuid otherwise
******************************************/
-u32 get_cpu_id(void)
+static u32 get_cpu_id(void)
{
struct ctrl_id *id_base;
u32 cpuid = 0;
/******************************************
* get_cpu_family(void) - extract cpu info
******************************************/
-u32 get_cpu_family(void)
+__used u32 get_cpu_family(void)
{
u16 hawkeye;
u32 cpu_family;
/******************************************
* get_cpu_rev(void) - extract version info
******************************************/
-u32 get_cpu_rev(void)
+__used u32 get_cpu_rev(void)
{
u32 cpuid = get_cpu_id();
/*****************************************************************
* get_sku_id(void) - read sku_id to get info on max clock rate
*****************************************************************/
-u32 get_sku_id(void)
+static u32 get_sku_id(void)
{
struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}
-/***************************************************************************
- * get_gpmc0_base() - Return current address hardware will be
- * fetching from. The below effectively gives what is correct, its a bit
- * mis-leading compared to the TRM. For the most general case the mask
- * needs to be also taken into account this does work in practice.
- * - for u-boot we currently map:
- * -- 0 to nothing,
- * -- 4 to flash
- * -- 8 to enent
- * -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
- u32 b;
-
- b = readl(&gpmc_cfg->cs[0].config7);
- b &= 0x1F; /* keep base [5:0] */
- b = b << 24; /* ret 0x0b000000 */
- return b;
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
- return WIDTH_16BIT;
-}
-
/*************************************************************************
* get_board_rev() - setup to pass kernel board revision information
* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
};
/*
+ * Enable IPU1 clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_ipu1_clocks(void)
+{
+ if (!IS_ENABLED(CONFIG_DRA7XX) ||
+ !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+ return;
+
+ u32 const clk_domains[] = {
+ (*prcm)->cm_ipu_clkstctrl,
+ (*prcm)->cm_ipu1_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_ipu1_ipu1_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_gptimer11_clkctrl,
+ (*prcm)->cm1_abe_timer7_clkctrl,
+ (*prcm)->cm1_abe_timer8_clkctrl,
+ 0
+ };
+ do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential, 0);
+
+ /* Enable optional additional functional clock for IPU1 */
+ setbits_le32((*prcm)->cm_ipu1_ipu1_clkctrl,
+ IPU1_CLKCTRL_CLKSEL_MASK);
+ /* Enable optional additional functional clock for IPU1 */
+ setbits_le32((*prcm)->cm1_abe_timer7_clkctrl,
+ IPU1_CLKCTRL_CLKSEL_MASK);
+ /* Enable optional additional functional clock for IPU1 */
+ setbits_le32((*prcm)->cm1_abe_timer8_clkctrl,
+ IPU1_CLKCTRL_CLKSEL_MASK);
+}
+
+/*
+ * Enable IPU2 clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_ipu2_clocks(void)
+{
+ if (!IS_ENABLED(CONFIG_DRA7XX) ||
+ !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+ return;
+
+ u32 const clk_domains[] = {
+ (*prcm)->cm_ipu_clkstctrl,
+ (*prcm)->cm_ipu2_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_ipu2_ipu2_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_gptimer3_clkctrl,
+ (*prcm)->cm_l4per_gptimer4_clkctrl,
+ (*prcm)->cm_l4per_gptimer9_clkctrl,
+ 0
+ };
+ do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential, 0);
+
+ /* Enable optional additional functional clock for IPU2 */
+ setbits_le32((*prcm)->cm_l4per_gptimer4_clkctrl,
+ IPU1_CLKCTRL_CLKSEL_MASK);
+ /* Enable optional additional functional clock for IPU2 */
+ setbits_le32((*prcm)->cm_l4per_gptimer9_clkctrl,
+ IPU1_CLKCTRL_CLKSEL_MASK);
+}
+
+/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_uboot_clocks(void)
{
- u32 const clk_domains_essential[] = {
-#if defined(CONFIG_DRA7XX)
- (*prcm)->cm_ipu_clkstctrl,
-#endif
- 0
- };
+ u32 cm_ipu_clkstctrl = 0;
+
+ if (IS_ENABLED(CONFIG_DRA7XX) &&
+ !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+ cm_ipu_clkstctrl = (*prcm)->cm_ipu_clkstctrl;
+
+ u32 const clk_domains_essential[] = {cm_ipu_clkstctrl, 0};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbtll_clkctrl,
/* cm IPU */
.cm_ipu_clkstctrl = 0x4a005540,
.cm_ipu_i2c5_clkctrl = 0x4a005578,
-
+ .cm_ipu1_clkstctrl = 0x4a005500,
+ .cm_ipu1_ipu1_clkctrl = 0x4a005520,
+ .cm_ipu2_clkstctrl = 0x4a008900,
+ .cm_ipu2_ipu2_clkctrl = 0x4a008920,
/* prm irqstatus regs */
.prm_irqstatus_mpu = 0x4ae06010,
.prm_irqstatus_mpu_2 = 0x4ae06014,
/*l3main1 edma*/
.cm_l3main1_tptc1_clkctrl = 0x4a008778,
.cm_l3main1_tptc2_clkctrl = 0x4a008780,
+
+ /* cm1.abe */
+ .cm1_abe_timer7_clkctrl = 0x4a005568,
+ .cm1_abe_timer8_clkctrl = 0x4a005570,
};
void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
if ARCH_SUNXI
config SPL_LDSCRIPT
+ default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
config IDENT_STRING
prompt "Sunxi SoC Variant"
optional
+config MACH_SUNIV
+ bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
+ select CPU_ARM926EJS
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7A
- select ARM_CORTEX_CPU_IS_UP
select PHY_SUN4I_USB
select DRAM_SUN4I
select SUNXI_GEN_SUN4I
config MACH_SUN5I
bool "sun5i (Allwinner A13)"
select CPU_V7A
- select ARM_CORTEX_CPU_IS_UP
select DRAM_SUN4I
select PHY_SUN4I_USB
select SUNXI_GEN_SUN4I
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select SPL_ARMV7_SET_CORTEX_SMPEN
select DRAM_SUN6I
select PHY_SUN4I_USB
select SPL_I2C
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select SPL_ARMV7_SET_CORTEX_SMPEN
select DRAM_SUN4I
select PHY_SUN4I_USB
select SUNXI_GEN_SUN4I
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7A
+ select SPL_ARMV7_SET_CORTEX_SMPEN
select DRAM_SUN9I
select SPL_I2C
select SUN6I_PRCM
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
+ select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64
select SUN6I_PRCM
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
endif
config SYS_CLK_FREQ
+ default 408000000 if MACH_SUNIV
default 1008000000 if MACH_SUN4I
default 1008000000 if MACH_SUN5I
default 1008000000 if MACH_SUN6I
default 1008000000 if MACH_SUN50I_H616
config SYS_CONFIG_NAME
+ default "suniv" if MACH_SUNIV
default "sun4i" if MACH_SUN4I
default "sun5i" if MACH_SUN5I
default "sun6i" if MACH_SUN6I
config VIDEO_HDMI
bool "HDMI output support"
- depends on VIDEO_SUNXI && !MACH_SUN8I
+ depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
default y
---help---
Say Y here to add support for outputting video over HDMI.
Set the GMAC Transmit Clock Delay Chain value.
config SPL_STACK_R_ADDR
+ default 0x81e00000 if MACH_SUNIV
default 0x4fe00000 if MACH_SUN4I
default 0x4fe00000 if MACH_SUN5I
default 0x4fe00000 if MACH_SUN6I
obj-y += pinmux.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
+obj-$(CONFIG_MACH_SUNIV) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
obj-$(CONFIG_SUN50I_GEN_H6) += clock_sun50i_h6.o
+ifndef CONFIG_ARM64
+obj-y += timer.o
+endif
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o
obj-$(CONFIG_DRAM_SUN8I_A23) += dram_sun8i_a23.o
}
#endif
+#ifdef CONFIG_SPL_BUILD
static int gpio_init(void)
{
__maybe_unused uint val;
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
+#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
+ defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40))
return 0;
}
-#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
static int spl_board_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
#endif
-void s_init(void)
-{
- /*
- * Undocumented magic taken from boot0, without this DRAM
- * access gets messed up (seems cache related).
- * The boot0 sources describe this as: "config ema for cache sram"
- */
-#if defined CONFIG_MACH_SUN6I
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-#elif defined CONFIG_MACH_SUN8I
- __maybe_unused uint version;
-
- /* Unlock sram version info reg, read it, relock */
- setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
- version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
- clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
-
- /*
- * Ideally this would be a switch case, but we do not know exactly
- * which versions there are and which version needs which settings,
- * so reproduce the per SoC code from the BSP.
- */
-#if defined CONFIG_MACH_SUN8I_A23
- if (version == 0x1650)
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
- else /* 0x1661 ? */
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-#elif defined CONFIG_MACH_SUN8I_A33
- if (version != 0x1667)
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-#endif
- /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
- /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
-#endif
-
-#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n"
- ::: "r0");
-#endif
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
- /* Enable non-secure access to some peripherals */
- tzpc_init();
-#endif
-
- clock_init();
- timer_init();
- gpio_init();
-#if !CONFIG_IS_ENABLED(DM_I2C)
- i2c_init_board();
-#endif
- eth_init_board();
-}
-
#define SUNXI_INVALID_BOOT_SOURCE -1
static int sunxi_get_boot_source(void)
return sector;
}
+#ifdef CONFIG_MACH_SUNIV
+/*
+ * The suniv BROM does not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ * TODO: This has the slight chance of being wrong (invalid SPL signature,
+ * but valid U-Boot legacy image on the SD card), but this should be rare.
+ * It looks like we can deduce from some BROM state upon entering the SPL
+ * (registers, SP, or stack itself) where the BROM was coming from and use
+ * that here.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+ * See the comments above in sunxi_get_boot_device() for information
+ * about FEL boot.
+ */
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+}
+#else
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#endif
+
+__weak void sunxi_sram_init(void)
+{
+}
void board_init_f(ulong dummy)
{
+ sunxi_sram_init();
+
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+ /* Enable non-secure access to some peripherals */
+ tzpc_init();
+#endif
+
+ clock_init();
+ timer_init();
+ gpio_init();
+ eth_init_board();
+
spl_init();
preloader_console_init();
#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
/* Needed early by sunxi_board_init if PMU is enabled */
+ i2c_init_board();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
}
/* These functions are shared between various SoCs so put them here. */
-#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
+ !defined CONFIG_MACH_SUNIV
int clock_twi_onoff(int port, int state)
{
struct sunxi_ccm_reg *const ccm =
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
+ !defined(CONFIG_MACH_SUNIV)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
- writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
- if (IS_ENABLED(CONFIG_MACH_SUN6I))
- writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+ if (!IS_ENABLED(CONFIG_MACH_SUNIV)) {
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
+ if (IS_ENABLED(CONFIG_MACH_SUN6I))
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+ }
#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- /* uart clock source is apb2 */
- writel(APB2_CLK_SRC_OSC24M|
- APB2_CLK_RATE_N_1|
- APB2_CLK_RATE_M(1),
- &ccm->apb2_div);
-
- /* open the clock for uart */
- setbits_le32(&ccm->apb2_gate,
- CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
-
- /* deassert uart reset */
- setbits_le32(&ccm->apb2_reset_cfg,
- 1 << (APB2_RESET_UART_SHIFT +
- CONFIG_CONS_INDEX - 1));
+#ifdef CONFIG_MACH_SUNIV
+ /* suniv doesn't have apb2, UART clock source is always apb1 */
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
#else
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_div);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+#endif /* !CONFIG_MACH_SUNIV */
+#else /* CONFIG_CONS_INDEX >= 5 */
/* enable R_PIO and R_UART clocks, and de-assert resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
#endif
}
/* Switch to 24MHz clock while changing PLL1 */
- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
- ATB_DIV_2 << ATB_DIV_SHIFT |
- CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_axi_cfg);
+ if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
+ writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+ } else {
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+ }
/*
* sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
sdelay(200);
/* Switch CPU to PLL1 */
- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
- ATB_DIV_2 << ATB_DIV_SHIFT |
- CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
- &ccm->cpu_axi_cfg);
+ if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
+ writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+ } else {
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+ }
}
#endif
uint32_t rval = readl(&ccm->pll6_cfg);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
- return 24000000 * n * k / 2;
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ return 24000000 * n * k;
+ else
+ return 24000000 * n * k / 2;
}
unsigned int clock_get_mipi_pll(void)
{
#ifdef CONFIG_MACH_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_MACH_SUNIV
+ puts("CPU: Allwinner F Series (SUNIV)\n");
#elif defined CONFIG_MACH_SUN5I
u32 val = readl(SUNXI_SID_BASE + 0x08);
switch ((val >> 12) & 0xf) {
/*
* Test if memory at offset offset matches memory at begin of DRAM
+ *
+ * Note: dsb() is not available on ARMv5 in Thumb mode
*/
+#ifndef CONFIG_MACH_SUNIV
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
return readl(CONFIG_SYS_SDRAM_BASE) ==
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
}
+#endif
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * suniv DRAM initialization
+ *
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is:
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/gpio.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <hang.h>
+
+#define SDR_T_CAS (0x2)
+#define SDR_T_RAS (0x8)
+#define SDR_T_RCD (0x3)
+#define SDR_T_RP (0x3)
+#define SDR_T_WR (0x3)
+#define SDR_T_RFC (0xd)
+#define SDR_T_XSR (0xf9)
+#define SDR_T_RC (0xb)
+#define SDR_T_INIT (0x8)
+#define SDR_T_INIT_REF (0x7)
+#define SDR_T_WTR (0x2)
+#define SDR_T_RRD (0x2)
+#define SDR_T_XP (0x0)
+
+enum dram_type {
+ DRAM_TYPE_SDR = 0,
+ DRAM_TYPE_DDR = 1,
+ /* Not supported yet. */
+ DRAM_TYPE_MDDR = 2,
+};
+
+struct dram_para {
+ u32 size; /* dram size (unit: MByte) */
+ u32 clk; /* dram work clock (unit: MHz) */
+ u32 access_mode; /* 0: interleave mode 1: sequence mode */
+ u32 cs_num; /* dram chip count 1: one chip 2: two chip */
+ u32 ddr8_remap; /* for 8bits data width DDR 0: normal 1: 8bits */
+ enum dram_type sdr_ddr;
+ u32 bwidth; /* dram bus width */
+ u32 col_width; /* column address width */
+ u32 row_width; /* row address width */
+ u32 bank_size; /* dram bank count */
+ u32 cas; /* dram cas */
+};
+
+struct dram_para suniv_dram_para = {
+ .size = 32,
+ .clk = 156,
+ .access_mode = 1,
+ .cs_num = 1,
+ .ddr8_remap = 0,
+ .sdr_ddr = DRAM_TYPE_DDR,
+ .bwidth = 16,
+ .col_width = 10,
+ .row_width = 13,
+ .bank_size = 4,
+ .cas = 0x3,
+};
+
+static int dram_initial(void)
+{
+ unsigned int time = 0xffffff;
+
+ setbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR, 0x1);
+ while ((readl(SUNXI_DRAMC_BASE + DRAM_SCTLR) & 0x1) && time--) {
+ if (time == 0)
+ return 0;
+ }
+ return 1;
+}
+
+static int dram_delay_scan(void)
+{
+ unsigned int time = 0xffffff;
+
+ setbits_le32(SUNXI_DRAMC_BASE + DRAM_DDLYR, 0x1);
+ while ((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) & 0x1) && time--) {
+ if (time == 0)
+ return 0;
+ }
+ return 1;
+}
+
+static void dram_set_autofresh_cycle(u32 clk)
+{
+ u32 val = 0;
+ u32 row = 0;
+ u32 temp = 0;
+
+ row = readl(SUNXI_DRAMC_BASE + DRAM_SCONR);
+ row &= 0x1e0;
+ row >>= 0x5;
+
+ if (row == 0xc) {
+ if (clk >= 1000000) {
+ temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
+ while (temp >= (10000000 >> 6)) {
+ temp -= (10000000 >> 6);
+ val++;
+ }
+ } else {
+ val = (clk * 499) >> 6;
+ }
+ } else if (row == 0xb) {
+ if (clk >= 1000000) {
+ temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
+ while (temp >= (10000000 >> 7)) {
+ temp -= (10000000 >> 7);
+ val++;
+ }
+ } else {
+ val = (clk * 499) >> 5;
+ }
+ }
+ writel(val, SUNXI_DRAMC_BASE + DRAM_SREFR);
+}
+
+static int dram_para_setup(struct dram_para *para)
+{
+ u32 val = 0;
+
+ val = (para->ddr8_remap) | (0x1 << 1) |
+ ((para->bank_size >> 2) << 3) |
+ ((para->cs_num >> 1) << 4) |
+ ((para->row_width - 1) << 5) |
+ ((para->col_width - 1) << 9) |
+ ((para->sdr_ddr ? (para->bwidth >> 4) : (para->bwidth >> 5)) << 13) |
+ (para->access_mode << 15) |
+ (para->sdr_ddr << 16);
+
+ writel(val, SUNXI_DRAMC_BASE + DRAM_SCONR);
+ setbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR, 0x1 << 19);
+ return dram_initial();
+}
+
+static u32 dram_check_delay(u32 bwidth)
+{
+ u32 dsize;
+ int i, j;
+ u32 num = 0;
+ u32 dflag = 0;
+
+ dsize = ((bwidth == 16) ? 4 : 2);
+ for (i = 0; i < dsize; i++) {
+ if (i == 0)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR0);
+ else if (i == 1)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR1);
+ else if (i == 2)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR2);
+ else if (i == 3)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR3);
+
+ for (j = 0; j < 32; j++) {
+ if (dflag & 0x1)
+ num++;
+ dflag >>= 1;
+ }
+ }
+ return num;
+}
+
+static int sdr_readpipe_scan(void)
+{
+ u32 k = 0;
+
+ for (k = 0; k < 32; k++)
+ writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k);
+ for (k = 0; k < 32; k++) {
+ if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k)
+ return 0;
+ }
+ return 1;
+}
+
+static u32 sdr_readpipe_select(void)
+{
+ u32 value = 0;
+ u32 i = 0;
+
+ for (i = 0; i < 8; i++) {
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, i << 6);
+ if (sdr_readpipe_scan()) {
+ value = i;
+ return value;
+ }
+ }
+ return value;
+}
+
+static u32 dram_check_type(struct dram_para *para)
+{
+ u32 times = 0;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, i << 6);
+ dram_delay_scan();
+ if (readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) & 0x30)
+ times++;
+ }
+
+ if (times == 8) {
+ para->sdr_ddr = DRAM_TYPE_SDR;
+ return 0;
+ }
+ para->sdr_ddr = DRAM_TYPE_DDR;
+ return 1;
+}
+
+static u32 dram_scan_readpipe(struct dram_para *para)
+{
+ u32 rp_best = 0, rp_val = 0;
+ u32 readpipe[8];
+ int i;
+
+ if (para->sdr_ddr == DRAM_TYPE_DDR) {
+ for (i = 0; i < 8; i++) {
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, i << 6);
+ dram_delay_scan();
+ readpipe[i] = 0;
+ if ((((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) >> 4) & 0x3) == 0x0) &&
+ (((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) >> 4) & 0x1) == 0x0))
+ readpipe[i] = dram_check_delay(para->bwidth);
+ if (rp_val < readpipe[i]) {
+ rp_val = readpipe[i];
+ rp_best = i;
+ }
+ }
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, rp_best << 6);
+ dram_delay_scan();
+ } else {
+ clrbits_le32(SUNXI_DRAMC_BASE + DRAM_SCONR,
+ (0x1 << 16) | (0x3 << 13));
+ rp_best = sdr_readpipe_select();
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, rp_best << 6);
+ }
+ return 0;
+}
+
+static u32 dram_get_dram_size(struct dram_para *para)
+{
+ u32 colflag = 10, rowflag = 13;
+ u32 val1 = 0;
+ u32 count = 0;
+ u32 addr1, addr2;
+ int i;
+
+ para->col_width = colflag;
+ para->row_width = rowflag;
+ dram_para_setup(para);
+ dram_scan_readpipe(para);
+ for (i = 0; i < 32; i++) {
+ *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
+ *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
+ }
+ for (i = 0; i < 32; i++) {
+ val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i));
+ if (val1 == 0x22)
+ count++;
+ }
+ if (count == 32)
+ colflag = 9;
+ else
+ colflag = 10;
+ count = 0;
+ para->col_width = colflag;
+ para->row_width = rowflag;
+ dram_para_setup(para);
+ if (colflag == 10) {
+ addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000;
+ addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000;
+ } else {
+ addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000;
+ addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000;
+ }
+ for (i = 0; i < 32; i++) {
+ *((u8 *)(addr1 + i)) = 0x33;
+ *((u8 *)(addr2 + i)) = 0x44;
+ }
+ for (i = 0; i < 32; i++) {
+ val1 = *((u8 *)(addr1 + i));
+ if (val1 == 0x44)
+ count++;
+ }
+ if (count == 32)
+ rowflag = 12;
+ else
+ rowflag = 13;
+ para->col_width = colflag;
+ para->row_width = rowflag;
+ if (para->row_width != 13)
+ para->size = 16;
+ else if (para->col_width == 10)
+ para->size = 64;
+ else
+ para->size = 32;
+ dram_set_autofresh_cycle(para->clk);
+ para->access_mode = 0;
+ dram_para_setup(para);
+
+ return 0;
+}
+
+static void simple_dram_check(void)
+{
+ volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE;
+ int i;
+
+ for (i = 0; i < 0x40; i++)
+ dram[i] = i;
+
+ for (i = 0; i < 0x40; i++) {
+ if (dram[i] != i) {
+ printf("DRAM initialization failed: dram[0x%x] != 0x%x.", i, dram[i]);
+ hang();
+ }
+ }
+
+ for (i = 0; i < 0x10000; i += 0x40)
+ dram[i] = i;
+
+ for (i = 0; i < 0x10000; i += 0x40) {
+ if (dram[i] != i) {
+ printf("DRAM initialization failed: dram[0x%x] != 0x%x.", i, dram[i]);
+ hang();
+ }
+ }
+}
+
+static void do_dram_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ u32 val;
+ u8 m; /* PLL_DDR clock factor */
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(3), 0x7);
+ mdelay(5);
+ /* TODO: dig out what's them... some analog register? */
+ if ((para->cas >> 3) & 0x1)
+ setbits_le32(SUNXI_PIO_BASE + 0x2c4, (0x1 << 23) | (0x20 << 17));
+
+ if (para->clk >= 144 && para->clk <= 180)
+ writel(0xaaa, SUNXI_PIO_BASE + 0x2c0);
+ if (para->clk >= 180)
+ writel(0xfff, SUNXI_PIO_BASE + 0x2c0);
+
+ if (para->cas & BIT(4))
+ writel(0xd1303333, &ccm->pll5_pattern_cfg);
+ else if (para->cas & BIT(5))
+ writel(0xcce06666, &ccm->pll5_pattern_cfg);
+ else if (para->cas & BIT(6))
+ writel(0xc8909999, &ccm->pll5_pattern_cfg);
+ else if (para->cas & BIT(7))
+ writel(0xc440cccc, &ccm->pll5_pattern_cfg);
+
+ if (para->clk <= 96)
+ m = 2;
+ else
+ m = 1;
+
+ val = CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+ CCM_PLL5_CTRL_N((para->clk * 2) / (24 / m)) |
+ CCM_PLL5_CTRL_K(1) | CCM_PLL5_CTRL_M(m);
+ if (para->cas & GENMASK(7, 4))
+ val |= CCM_PLL5_CTRL_SIGMA_DELTA_EN;
+ writel(val, &ccm->pll5_cfg);
+ setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_UPD);
+ mctl_await_completion(&ccm->pll5_cfg, BIT(28), BIT(28));
+ mdelay(5);
+
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_MCTL));
+ clrbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_RESET_OFFSET_MCTL));
+ udelay(50);
+ setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_RESET_OFFSET_MCTL));
+
+ clrsetbits_le32(SUNXI_PIO_BASE + 0x2c4, (1 << 16),
+ ((para->sdr_ddr == DRAM_TYPE_DDR) << 16));
+
+ val = (SDR_T_CAS << 0) | (SDR_T_RAS << 3) | (SDR_T_RCD << 7) |
+ (SDR_T_RP << 10) | (SDR_T_WR << 13) | (SDR_T_RFC << 15) |
+ (SDR_T_XSR << 19) | (SDR_T_RC << 28);
+ writel(val, SUNXI_DRAMC_BASE + DRAM_STMG0R);
+ val = (SDR_T_INIT << 0) | (SDR_T_INIT_REF << 16) | (SDR_T_WTR << 20) |
+ (SDR_T_RRD << 22) | (SDR_T_XP << 25);
+ writel(val, SUNXI_DRAMC_BASE + DRAM_STMG1R);
+ dram_para_setup(para);
+ dram_check_type(para);
+
+ clrsetbits_le32(SUNXI_PIO_BASE + 0x2c4, (1 << 16),
+ ((para->sdr_ddr == DRAM_TYPE_DDR) << 16));
+
+ dram_set_autofresh_cycle(para->clk);
+ dram_scan_readpipe(para);
+ dram_get_dram_size(para);
+ simple_dram_check();
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ do_dram_init(&suniv_dram_para);
+
+ return suniv_dram_para.size * 1024 * 1024;
+}
struct sunxi_timer_reg *timers =
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
+
writel(TIMER_LOAD_VAL, &timer->inter);
writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
&timer->ctl);
return 0;
}
-/* timer without interrupts */
static ulong get_timer_masked(void)
{
/* current tick value */
ulong now = TICKS_TO_HZ(read_timer());
- if (now >= gd->arch.lastinc) /* normal (non rollover) */
+ if (now >= gd->arch.lastinc) { /* normal (non rollover) */
gd->arch.tbl += (now - gd->arch.lastinc);
- else {
+ } else {
/* rollover */
gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
- gd->arch.lastinc) + now;
return gd->arch.tbl;
}
+/* timer without interrupts */
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 - 2018 Xilinx, Inc.
- */
-
-/* Empty file - for compilation */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2013 Xilinx, Inc.
- * Copyright (c) 2015 DAVE Embedded Systems
- */
-
-#ifndef _ZYNQ_GPIO_H
-#define _ZYNQ_GPIO_H
-
-#endif /* _ZYNQ_GPIO_H */
#include <asm/arch/sys_proto.h>
#include <asm/arch/ps7_init_gpl.h>
+#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
+void board_debug_uart_init(void)
+{
+ ps7_init();
+}
+#endif
+
void board_init_f(ulong dummy)
{
+#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
ps7_init();
+#endif
arch_cpu_init();
-
-#ifdef CONFIG_DEBUG_UART
- /* Uart debug for sure */
- debug_uart_init();
- puts("Debug uart enabled\n"); /* or printch() */
-#endif
}
#ifdef CONFIG_SPL_BOARD_INIT
config ZYNQMP_PSU_INIT_ENABLED
bool "Include psu_init"
+ select BOARD_EARLY_INIT_F
help
Include psu_init to full u-boot. SPL include psu_init by default.
obj-y += clk.o
obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
+obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Xilinx, Inc.
- */
-
-#ifndef __ARCH_ZYNQMP_GPIO_H
-#define __ARCH_ZYNQMP_GPIO_H
-
-/* Empty file - sdhci requires this. */
-
-#endif
#define CSU_JTAG_CHAIN_WR_SETUP GENMASK(1, 0)
#define CSU_PCAP_PROG_RELEASE_PL BIT(0)
+#define ZYNQMP_CSU_STATUS_AUTHENTICATED BIT(0)
+#define ZYNQMP_CSU_STATUS_ENCRYPTED BIT(1)
+
struct csu_regs {
- u32 reserved0[4];
+ u32 status;
+ u32 reserved0[3];
u32 multi_boot;
u32 reserved1[7];
u32 jtag_chain_status_wr;
int psu_init(void);
unsigned long psu_post_config_data(void);
+int psu_uboot_init(void);
#endif /* _PSU_INIT_GPL_H_ */
#include <asm/arch/psu_init_gpl.h>
#include <asm/arch/sys_proto.h>
+#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
+void board_debug_uart_init(void)
+{
+ psu_uboot_init();
+}
+#endif
+
void board_init_f(ulong dummy)
{
- board_early_init_f();
+#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
+ psu_uboot_init();
+#endif
+
board_early_init_r();
#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT
zynqmp_ecc_init();
dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
MFS(state, resr);
printf("Hardware exception at 0x%x address\n", address);
R17(address);
- printf("Return address from exception 0x%x\n", address);
+
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP) &&
+ (state & 0x1000)) {
+ /*
+ * For exceptions in delay slots, the return address is stored
+ * in the Branch Target Register (BTR), rather than R17.
+ */
+ MFS(address, rbtr);
+
+ puts("Exception in delay slot\n");
+ }
+
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
puts("Unaligned data access exception\n");
+
+ printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
+ printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
+ printf("Register R%x\n", (state & 0x3E0) >> 5);
break;
case 0x2:
puts("Illegal op-code exception\n");
case 0x5:
puts("Divide by zero exception\n");
break;
-#ifdef MICROBLAZE_V5
case 0x7:
puts("Priviledged or stack protection violation exception\n");
break;
- case 0x1000:
- puts("Exception in delay slot\n");
- break;
-#endif
default:
puts("Undefined cause\n");
break;
}
- printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
- printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
- printf("Register R%x\n", (state & 0x3E) >> 5);
+
+ printf("Return address from exception 0x%x\n", address);
hang();
}
dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
l2c = read_c0_config5() & MIPS_CONF5_L2C;
}
- if (l2c && config_enabled(CONFIG_MIPS_CM)) {
+ if (l2c && IS_ENABLED(CONFIG_MIPS_CM)) {
gd->arch.l2_line_size = mips_cm_l2_line_size();
} else if (l2c) {
/* We don't know how to retrieve L2 config on this system */
dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
/*
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
- */
-#ifdef CONFIG_SYS_RESET_ADDRESS
- addr = CONFIG_SYS_RESET_ADDRESS;
-#else
- /*
+ *
* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
* CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
- * Better pick an address known to be invalid on your system and assign
- * it to CONFIG_SYS_RESET_ADDRESS.
- * "(ulong)-1" used to be a good choice for many systems...
*/
addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
-#endif
+
((void (*)(void)) addr)();
return 1;
}
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
head-$(CONFIG_SANDBOX_SDL) += arch/sandbox/cpu/sdl.o
libs-y += arch/sandbox/cpu/
libs-y += arch/sandbox/lib/
+
+# sdl.c fails to compile with -fshort-wchar using musl.
+cmd_cc_sdl.o = $(CC) $(filter-out -nostdinc -fshort-wchar, \
+ $(patsubst -I%,-idirafter%,$(c_flags))) -fno-lto -c -o $@ $<
+
+$(obj)/sdl.o: $(src)/sdl.c FORCE
+ $(call if_changed_dep,cc_sdl.o)
obj-y := cache.o cpu.o state.o
extra-y := start.o os.o
-extra-$(CONFIG_SANDBOX_SDL) += sdl.o
+extra-$(CONFIG_SANDBOX_SDL) += sdl.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o
$(obj)/os.o: $(src)/os.c FORCE
$(call if_changed_dep,cc_os.o)
-$(obj)/sdl.o: $(src)/sdl.c FORCE
- $(call if_changed_dep,cc_os.o)
# eth-raw-os.c is built in the system env, so needs standard includes
# CFLAGS_REMOVE_eth-raw-os.o cannot be used to drop header include path
$(obj)/eth-raw-os.o: $(src)/eth-raw-os.c FORCE
$(call if_changed_dep,cc_eth-raw-os.o)
+
+# sdl.c fails to build with -fshort-wchar using musl
+cmd_cc_sdl.o = $(CC) $(filter-out -nostdinc -fshort-wchar, \
+ $(patsubst -I%,-idirafter%,$(c_flags))) -fno-lto -c -o $@ $<
+
+$(obj)/sdl.o: $(src)/sdl.c FORCE
+ $(call if_changed_dep,cc_sdl.o)
dtb-$(CONFIG_UT_DM) += test.dtb
dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
#ifndef __ASM_ACPI_TABLE_H__
#define __ASM_ACPI_TABLE_H__
-ulong write_acpi_tables(ulong start);
+/* Empty for now, this file is required by acpi/acpi_table.h */
#endif /* __ASM_ACPI_TABLE_H__ */
dtb-y += sh7751-r2dplus.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
#include <linux/err.h>
#include <power/acpi_pmc.h>
-u32 acpi_fill_mcfg(u32 current)
+int acpi_fill_mcfg(struct acpi_ctx *ctx)
{
+ size_t size;
+
/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
- current += acpi_create_mcfg_mmconfig((void *)current,
- CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
- (CONFIG_SA_PCIEX_LENGTH >> 20)
- - 1);
- return current;
+ size = acpi_create_mcfg_mmconfig((void *)ctx->current,
+ CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
+ (CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
+ acpi_inc(ctx, size);
+
+ return 0;
}
static int acpi_sci_irq(void)
return current;
}
-u32 acpi_fill_mcfg(u32 current)
+int acpi_fill_mcfg(struct acpi_ctx *ctx)
{
+ size_t size;
+
/* TODO: Derive parameters from SFI MCFG table */
- current += acpi_create_mcfg_mmconfig
- ((struct acpi_mcfg_mmconfig *)current,
+ size = acpi_create_mcfg_mmconfig
+ ((struct acpi_mcfg_mmconfig *)ctx->current,
MCFG_BASE_ADDRESS, 0x0, 0x0, 0x0);
+ acpi_inc(ctx, size);
- return current;
+ return 0;
}
static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp)
slimbootloader.dtb \
baytrail_som-db5800-som-6867.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p $(if $(CONFIG_EFI_APP),0x8000,0x1000)
u-boot-tpl-dtb {
};
#endif
- spl {
+ u-boot-spl {
type = "u-boot-spl";
offset = <CONFIG_X86_OFFSET_SPL>;
};
u32 acpi_fill_madt(u32 current);
int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
u16 seg_nr, u8 start, u8 end);
-u32 acpi_fill_mcfg(u32 current);
/**
* acpi_write_hpet() - Write out a HPET table
*/
int acpi_create_gnvs(struct acpi_global_nvs *gnvs);
-ulong write_acpi_tables(ulong start);
-
/**
* acpi_get_rsdp_addr() - get ACPI RSDP table address
*
}
ACPI_WRITER(5x86, NULL, acpi_write_madt, 0);
-int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
- u16 seg_nr, u8 start, u8 end)
-{
- memset(mmconfig, 0, sizeof(*mmconfig));
- mmconfig->base_address_l = base;
- mmconfig->base_address_h = 0;
- mmconfig->pci_segment_group_number = seg_nr;
- mmconfig->start_bus_number = start;
- mmconfig->end_bus_number = end;
-
- return sizeof(struct acpi_mcfg_mmconfig);
-}
-
-__weak u32 acpi_fill_mcfg(u32 current)
-{
- current += acpi_create_mcfg_mmconfig
- ((struct acpi_mcfg_mmconfig *)current,
- CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
-
- return current;
-}
-
/**
* acpi_create_tcpa() - Create a TCPA table
*
}
ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
-/* MCFG is defined in the PCI Firmware Specification 3.0 */
-int acpi_write_mcfg(struct acpi_ctx *ctx, const struct acpi_writer *entry)
-{
- struct acpi_table_header *header;
- struct acpi_mcfg *mcfg;
- u32 current;
-
- mcfg = ctx->current;
- header = &mcfg->header;
-
- current = (u32)mcfg + sizeof(struct acpi_mcfg);
-
- memset(mcfg, '\0', sizeof(struct acpi_mcfg));
-
- /* Fill out header fields */
- acpi_fill_header(header, "MCFG");
- header->length = sizeof(struct acpi_mcfg);
- header->revision = 1;
-
- /* (Re)calculate length and checksum */
- header->length = current - (u32)mcfg;
- header->checksum = table_compute_checksum(mcfg, header->length);
-
- acpi_inc(ctx, mcfg->header.length);
- acpi_add_table(ctx, mcfg);
-
- return 0;
-}
-ACPI_WRITER(5mcfg, "MCFG", acpi_write_mcfg, 0);
-
/**
* acpi_write_hpet() - Write out a HPET table
*
dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb
+include $(srctree)/scripts/Makefile.dts
+
targets += $(dtb-y)
DTC_FLAGS +=
{
struct phy_device *phydev;
struct mii_dev *bus;
+ const char *node_name;
+ int node;
+
+ node = fdt_path_offset(gd->fdt_blob, "ethernet0");
+ if (node < 0) {
+ printf("Cannot get eth0!\n");
+ return;
+ }
- bus = miiphy_get_dev_by_name("neta@30000");
+ node_name = fdt_get_name(gd->fdt_blob, node, NULL);
+ if (!node_name) {
+ printf("Cannot get eth0 node name!\n");
+ return;
+ }
+
+ bus = miiphy_get_dev_by_name(node_name);
if (!bus) {
printf("Cannot get MDIO bus device!\n");
return;
*/
if (peridot || topaz) {
struct mii_dev *bus;
+ const char *node_name;
+ int node;
- bus = miiphy_get_dev_by_name("neta@30000");
+ node = fdt_path_offset(gd->fdt_blob, "ethernet0");
+ node_name = (node >= 0) ? fdt_get_name(gd->fdt_blob, node, NULL) : NULL;
+ bus = node_name ? miiphy_get_dev_by_name(node_name) : NULL;
if (!bus) {
printf("Cannot get MDIO bus device!\n");
} else {
DREAMPLUG BOARD
+M: Tony Dinh <mibodhi@gmail.com>
M: Jason Cooper <u-boot@lakedaemon.net>
S: Maintained
F: board/Marvell/dreamplug/
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2021 Tony Dinh <mibodhi@gmail.com>
- * (C) Copyright 2011
- * Jason Cooper <u-boot@lakedaemon.net>
+ * Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2011 Jason Cooper <u-boot@lakedaemon.net>
*
* Based on work by:
* Marvell Semiconductor <www.marvell.com>
#include <common.h>
#include <init.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/global_data.h>
-#include "dreamplug.h"
DECLARE_GLOBAL_DATA_PTR;
+#define DREAMPLUG_OE_LOW (~(0))
+#define DREAMPLUG_OE_HIGH (~(0))
+#define DREAMPLUG_OE_VAL_LOW 0
+#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
+
int board_early_init_f(void)
{
/*
return 0;
}
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-static int fdt_get_phy_addr(const char *path)
-{
- const void *fdt = gd->fdt_blob;
- const u32 *reg;
- const u32 *val;
- int node, phandle, addr;
-
- /* Find the node by its full path */
- node = fdt_path_offset(fdt, path);
- if (node >= 0) {
- /* Look up phy-handle */
- val = fdt_getprop(fdt, node, "phy-handle", NULL);
- if (val) {
- phandle = fdt32_to_cpu(*val);
- if (!phandle)
- return -1;
- /* Follow it to its node */
- node = fdt_node_offset_by_phandle(fdt, phandle);
- if (node) {
- /* Look up reg */
- reg = fdt_getprop(fdt, node, "reg", NULL);
- if (reg) {
- addr = fdt32_to_cpu(*reg);
- return addr;
- }
- }
- }
- }
- return -1;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void mv_phy_88e1116_init(const char *name, const char *path)
+int board_eth_init(struct bd_info *bis)
{
- u16 reg;
- int phyaddr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- phyaddr = fdt_get_phy_addr(path);
- if (phyaddr < 0)
- return;
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL2_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL2_REG, reg);
- miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, phyaddr);
-
- printf("88E1116 Initialized on %s\n", name);
+ return cpu_eth_init(bis);
}
-void reset_phy(void)
+int board_init(void)
{
- char *eth0_name = "ethernet-controller@72000";
- char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
- char *eth1_name = "ethernet-controller@76000";
- char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0";
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
- /* configure and initialize both PHY's */
- mv_phy_88e1116_init(eth0_name, eth0_path);
- mv_phy_88e1116_init(eth1_name, eth1_path);
+ return 0;
}
-#endif /* CONFIG_RESET_PHY_R */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Jason Cooper <u-boot@lakedaemon.net>
- *
- * Based on work by:
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#ifndef __DREAMPLUG_H
-#define __DREAMPLUG_H
-
-#define DREAMPLUG_OE_LOW (~(0))
-#define DREAMPLUG_OE_HIGH (~(0))
-#define DREAMPLUG_OE_VAL_LOW 0
-#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
-
-/* PHY related */
-#define MV88E1116_MAC_CTRL2_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __DREAMPLUG_H */
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.c originally written by
#include <common.h>
#include <bootstage.h>
#include <init.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/arch/cpu.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
-#include "dockstar.h"
+#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
+#define DOCKSTAR_OE_LOW (~(0))
+#define DOCKSTAR_OE_HIGH (~(0))
+#define DOCKSTAR_OE_VAL_LOW BIT(29) /* USB_PWEN low */
+#define DOCKSTAR_OE_VAL_HIGH BIT(17) /* LED pin high */
+
int board_early_init_f(void)
{
/*
return 0;
}
+int board_eth_init(struct bd_info *bis)
+{
+ return cpu_eth_init(bis);
+}
+
int board_init(void)
{
/*
return 0;
}
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
-
#if CONFIG_IS_ENABLED(BOOTSTAGE)
-#define GREEN_LED (1 << 14)
-#define ORANGE_LED (1 << 15)
+#define GREEN_LED BIT(14)
+#define ORANGE_LED BIT(15)
#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
#define NEITHER_LED 0
static void set_leds(u32 leds, u32 blinking)
{
struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
- u32 oe = readl(&r->oe) | BOTH_LEDS;
+ u32 oe;
+ u32 bl;
+
+ oe = readl(&r->oe) | BOTH_LEDS;
writel(oe & ~leds, &r->oe); /* active low */
- u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
+ bl = readl(&r->blink_en) & ~BOTH_LEDS;
writel(bl | blinking, &r->blink_en);
}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
- *
- * Based on sheevaplug.h originally written by
- * Prafulla Wadaskar <prafulla@marvell.com>
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef __DOCKSTAR_H
-#define __DOCKSTAR_H
-
-#define DOCKSTAR_OE_LOW (~(0))
-#define DOCKSTAR_OE_HIGH (~(0))
-#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
-#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __DOCKSTAR_H */
--- /dev/null
+if TARGET_IMX8MP_RSB3720A1_4G || TARGET_IMX8MP_RSB3720A1_6G
+
+config SYS_BOARD
+ default "imx8mp_rsb3720a1"
+
+config SYS_VENDOR
+ default "advantech"
+
+config SYS_CONFIG_NAME
+ default "imx8mp_rsb3720"
+
+source "board/freescale/common/Kconfig"
+
+endif
--- /dev/null
+i.MX8MP RSB3720 BOARD
+M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+S: Maintained
+F: board/advantech/imx8mp_rsb3720a1/
+F: include/configs/imx8mp_rsb3720a1.h
+F: configs/imx8mp_rsb3720a1_4G_defconfig
+F: configs/imx8mp_rsb3720a1_6G_defconfig
--- /dev/null
+#
+# Copyright 2019 NXP
+# Copyright 2022 Linaro
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_6G
+obj-y += imx8mp_rsb3720a1.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_6G.o
+endif
+endif
+
+ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_4G
+obj-y += imx8mp_rsb3720a1.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_4G.o
+endif
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Linaro
+ */
+
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <spl.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/dma.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+ MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+ MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_NAND_MXS
+static void setup_gpmi_nand(void)
+{
+ init_nand_clk();
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(2);
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(4, 2)
+static const iomux_v3_cfg_t fec1_rst_pads[] = {
+ MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+ ARRAY_SIZE(fec1_rst_pads));
+
+ gpio_request(FEC_RST_PAD, "fec1_rst");
+ gpio_direction_output(FEC_RST_PAD, 0);
+ mdelay(15);
+ gpio_direction_output(FEC_RST_PAD, 1);
+ mdelay(100);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_fec();
+
+ /* Enable RGMII TX clk output */
+ setbits_le32(&gpr->gpr[1], BIT(22));
+
+ return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_DWC_ETH_QOS
+#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
+static const iomux_v3_cfg_t eqos_rst_pads[] = {
+ MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_eqos(void)
+{
+ imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
+ ARRAY_SIZE(eqos_rst_pads));
+
+ gpio_request(EQOS_RST_PAD, "eqos_rst");
+ gpio_direction_output(EQOS_RST_PAD, 0);
+ mdelay(15);
+ gpio_direction_output(EQOS_RST_PAD, 1);
+ mdelay(100);
+}
+
+static int setup_eqos(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_eqos();
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+ setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+#endif /* CONFIG_DWC_ETH_QOS */
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ }
+
+ return 0;
+}
+
+#define DISPMIX 13
+#define MIPI 15
+
+#define WDOG_TRIG IMX_GPIO_NR(4, 20)
+
+static iomux_v3_cfg_t wdt_trig[] = {
+ MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_wdt(void)
+{
+ imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig));
+ gpio_request(WDOG_TRIG, "wdt_trig");
+ gpio_direction_output(WDOG_TRIG, 1);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+#ifdef CONFIG_DWC_ETH_QOS
+ /* clock, pin, gpr */
+ setup_eqos();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+ setup_iomux_wdt();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ env_set("board_name", "RSB3720A1");
+ env_set("board_rev", "iMX8MP");
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+#define UBOOT_RAW_SECTOR_OFFSET 0x40
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
+{
+ u32 boot_dev = spl_boot_device();
+
+ switch (boot_dev) {
+ case BOOT_DEVICE_MMC2:
+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
+ default:
+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+ }
+}
+#endif /* CONFIG_SPL_MMC_SUPPORT */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 NXP
+ */
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x920000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x323 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x807bf },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x9121c1c },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400250, 0x1f05 },
+ { 0x3d400254, 0x1f },
+ { 0x3d400264, 0x90003ff },
+ { 0x3d40026c, 0x20003ff },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x1000e00 },
+ { 0x3d400498, 0x3ff0000 },
+ { 0x3d40049c, 0x1000e00 },
+ { 0x3d4004a0, 0x3ff0000 },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x18 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x3e8 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
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+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x448 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0xf },
+ { 0x9016b, 0x7c0 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x0 },
+ { 0x9016e, 0xe8 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x47 },
+ { 0x90171, 0x630 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x8 },
+ { 0x90174, 0x618 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0xe0 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x7c8 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x8 },
+ { 0x9017d, 0x8140 },
+ { 0x9017e, 0x10c },
+ { 0x9017f, 0x0 },
+ { 0x90180, 0x478 },
+ { 0x90181, 0x109 },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x7d },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+ { 0x3d400070, 0x01027f44 },
+#endif
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x460048 },
+ { 0x3d4000ec, 0x150048 },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x807bf },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x9121c1c },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+ { 0x3d400200, 0x13 },
+ { 0x3d40020c, 0x13131300 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x68040404 },
+#else
+ { 0x3d400200, 0x16 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x68070707 },
+#endif
+ { 0x3d40021c, 0xf08 },
+ { 0x3d400250, 0x00001705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0x30d400 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x18 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x3e8 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4846 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4846 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x4600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x4600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1500 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4846 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4846 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x4600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x4600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1500 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x448 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0xf },
+ { 0x9016b, 0x7c0 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x0 },
+ { 0x9016e, 0xe8 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x47 },
+ { 0x90171, 0x630 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x8 },
+ { 0x90174, 0x618 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0xe0 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x7c8 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x8 },
+ { 0x9017d, 0x8140 },
+ { 0x9017e, 0x10c },
+ { 0x9017f, 0x0 },
+ { 0x90180, 0x478 },
+ { 0x90181, 0x109 },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x7d },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+void board_dram_ecc_scrub(void)
+{
+ /* add inline scrb function MPlus spcific */
+ /* scrub 0-1.75G */
+ ddrc_inline_ecc_scrub(0x0, 0x1bffffff);
+ /* scrub 2-3.75G */
+ ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff);
+ /* scrub 4-5.75G */
+ ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff);
+ /* set scruber read range 0-6G */
+ ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
+}
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Copyright 2022 Linaro
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <errno.h>
+#include <fsl_esdhc_imx.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <mmc.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <dm/uclass.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
+ return BOOT_DEVICE_BOOTROM;
+#else
+ switch (boot_dev_spl) {
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+#endif
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_PE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS | \
+ PAD_CTL_DSE4)
+
+static const iomux_v3_cfg_t usdhc3_pads[] = {
+ MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t usdhc2_pads[] = {
+ MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+ MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
+};
+
+#ifndef USDHC3_BASE_ADDR
+#define USDHC3_BASE_ADDR 0x30B60000
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR, 0, 8},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ init_clk_usdhc(1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+ ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+ gpio_direction_input(USDHC2_CD_GPIO);
+ break;
+ case 1:
+ init_clk_usdhc(2);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+ ARRAY_SIZE(usdhc3_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers");
+ printf("(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ default:
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ return ret;
+ }
+
+ return 1;
+}
+
+int power_init_board(void)
+{
+ struct udevice *pdev;
+ int ret;
+
+ ret = pmic_get("pca9450@25", &pdev);
+ if (ret == -ENODEV) {
+ printf("No pmic\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(pdev, PCA9450_BUCK123_DVS, 0x29);
+
+ /*
+ * increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85v for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+ pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(pdev, PCA9450_BUCK1CTRL, 0x59);
+
+ /* Kernel uses OD/OD freq for SOC */
+ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
+ pmic_reg_write(pdev, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(pdev, PCA9450_RESET_CTRL, 0xA1);
+
+ /* Forced enable the I2C level translator*/
+ pmic_reg_write(pdev, PCA9450_CONFIG2, 0x03);
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ enable_tzc380();
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
* Copyright 2018 NXP
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
# Copyright (C) 2015, Google, Inc
obj-y += som-db5800-som-6867.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
*/
BOOT_FROM spi
-#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
Note: $(srctree) is U-Boot source directory
$ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ git checkout imx_5.4.70_2.3.0
+$ git lf-5.10.72-2.2.0
$ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu-
$ cp build/imx8mm/release/bl31.bin $(srctree)
Get the DDR firmware
====================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin
-$ chmod +x firmware-imx-8.5.bin
-$ ./firmware-imx-8.5
-$ cp firmware-imx-8.5/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Build U-Boot
============
$ make imx8mm_beacon_defconfig
-$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu-
+$ make CROSS_COMPILE=aarch64-linux-gnu-
Burn U-Boot to microSD Card
===========================
return 0;
}
-
-int board_mmc_get_env_dev(int devno)
-{
- return devno;
-}
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7E1000
Note: $(srctree) is U-Boot source directory
$ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ git checkout imx_5.4.47_2.2.0
+$ git lf-5.10.72-2.2.0
$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
-$ cp build/imx8mm/release/bl31.bin $(srctree)
+$ cp build/imx8mn/release/bl31.bin $(srctree)
Get the DDR firmware
====================
Build U-Boot
============
$ make imx8mn_beacon_defconfig
-$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x960000
+$ make CROSS_COMPILE=aarch64-linux-gnu-
Burn U-Boot to microSD Card
===========================
return 0;
}
-
-int board_mmc_get_env_dev(int devno)
-{
- return CONFIG_SYS_MMC_ENV_DEV;
-}
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
ROM_VERSION v2
BOOT_FROM sd
hang();
}
+ enable_tzc380();
+
/* DDR initialization */
spl_dram_init();
*/
BOOT_FROM spi
-#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
*/
BOOT_FROM spi
-#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
*/
BOOT_FROM spi
-#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
*/
BOOT_FROM spi
-#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
*/
BOOT_FROM spi
-#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
*/
BOOT_FROM spi
-#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2012
* David Purdy <david.c.purdy@gmail.com>
*
#include <common.h>
#include <init.h>
#include <log.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/global_data.h>
-#include "pogo_e02.h"
+#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
+/* GPIO configuration */
+#define POGO_E02_OE_LOW (~(0))
+#define POGO_E02_OE_HIGH (~(0))
+#define POGO_E02_OE_VAL_LOW BIT(29)
+#define POGO_E02_OE_VAL_HIGH 0
+
int board_early_init_f(void)
{
/*
return 0;
}
+int board_eth_init(struct bd_info *bis)
+{
+ return cpu_eth_init(bis);
+}
+
int board_init(void)
{
/* Boot parameters address */
return 0;
}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..(%s) could not read PHY dev address\n", __func__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- debug("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012
- * David Purdy <david.c.purdy@gmail.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __POGO_E02_H
-#define __POGO_E02_H
-
-/* GPIO configuration */
-#define POGO_E02_OE_LOW (~(0))
-#define POGO_E02_OE_HIGH (~(0))
-#define POGO_E02_OE_VAL_LOW (1 << 29)
-#define POGO_E02_OE_VAL_HIGH 0
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __POGO_E02_H */
#include <common.h>
#include <env.h>
+#include <extension_board.h>
#include <hang.h>
+#include <i2c.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
#include "ddr/ddr.h"
return 0;
}
+/* IOT_GATE-iMX8 extension boards ID */
+typedef enum {
+ IOT_GATE_EXT_EMPTY, /* No extension */
+ IOT_GATE_EXT_CAN, /* CAN bus */
+ IOT_GATE_EXT_IED, /* Bridge */
+ IOT_GATE_EXT_POE, /* POE */
+ IOT_GATE_EXT_POEV2, /* POEv2 */
+} iot_gate_imx8_ext;
+
+typedef enum {
+ IOT_GATE_IMX8_CARD_ID_EMPTY = 0, /* card id - uninhabited */
+ IOT_GATE_IMX8_CARD_ID_DI4O4 = 1, /* Card ID - IED-DI4O4 */
+ IOT_GATE_IMX8_CARD_ID_RS_485 = 2, /* Card ID - IED-RS485 */
+ IOT_GATE_IMX8_CARD_ID_TPM = 3, /* Card ID - IED-TPM */
+ IOT_GATE_IMX8_CARD_ID_CAN = 4, /* Card ID - IED-CAN */
+ IOT_GATE_IMX8_CARD_ID_CL420 = 5, /* Card ID - IED-CL420 */
+ IOT_GATE_IMX8_CARD_ID_RS_232 = 6, /* Card ID - IED-RS232 */
+} iot_gate_imx8_ied_ext;
+
static int setup_fec(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC)) {
return devno;
}
+#define IOT_GATE_IMX8_EXT_I2C 3 /* I2C ID of the extension board */
+#define IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM 0x54 /* I2C address of the EEPROM */
+
+/* I2C address of the EEPROM in the POE extension */
+#define IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POE 0x50
+#define IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POEV2 0x51
+#define IOT_GATE_IMX8_EXT_I2C_ADDR_GPIO 0x22 /* I2C address of the GPIO
+ extender */
+
+static int iot_gate_imx8_ext_id = IOT_GATE_EXT_EMPTY; /* Extension board ID */
+static int iot_gate_imx8_ext_ied_id [3] = {
+ IOT_GATE_IMX8_CARD_ID_EMPTY,
+ IOT_GATE_IMX8_CARD_ID_EMPTY,
+ IOT_GATE_IMX8_CARD_ID_EMPTY };
+
+/*
+ * iot_gate_imx8_detect_ext() - extended board detection
+ * The detection is done according to the detected I2C devices.
+ */
+static void iot_gate_imx8_detect_ext(void)
+{
+ int ret;
+ struct udevice *i2c_bus, *i2c_dev;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, IOT_GATE_IMX8_EXT_I2C,
+ &i2c_bus);
+ if (ret) {
+ printf("%s: Failed getting i2c device\n", __func__);
+ return;
+ }
+
+ ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POE, 0,
+ &i2c_dev);
+ if (!ret) {
+ iot_gate_imx8_ext_id = IOT_GATE_EXT_POE;
+ return;
+ }
+
+ ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM_POEV2, 0,
+ &i2c_dev);
+ if (!ret) {
+ iot_gate_imx8_ext_id = IOT_GATE_EXT_POEV2;
+ return;
+ }
+
+ ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_EEPROM, 0,
+ &i2c_dev);
+ if (ret){
+ iot_gate_imx8_ext_id = IOT_GATE_EXT_EMPTY;
+ return;
+ }
+ /* Only the bridge extension includes the GPIO extender */
+ ret = dm_i2c_probe(i2c_bus, IOT_GATE_IMX8_EXT_I2C_ADDR_GPIO, 0,
+ &i2c_dev);
+ if (ret) /* GPIO extender not detected */
+ iot_gate_imx8_ext_id = IOT_GATE_EXT_CAN;
+ else /* GPIO extender detected */
+ iot_gate_imx8_ext_id = IOT_GATE_EXT_IED;
+}
+
+static iomux_v3_cfg_t const iot_gate_imx8_ext_ied_pads[] = {
+ IMX8MM_PAD_NAND_ALE_GPIO3_IO0 | MUX_PAD_CTRL(PAD_CTL_PE),
+ IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 | MUX_PAD_CTRL(PAD_CTL_PE),
+ IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 | MUX_PAD_CTRL(PAD_CTL_PE),
+ IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(PAD_CTL_PE),
+ IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 | MUX_PAD_CTRL(PAD_CTL_PE),
+ IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 | MUX_PAD_CTRL(PAD_CTL_PE),
+};
+
+static iomux_v3_cfg_t const iot_gate_imx8_ext_poev2_pads[] = {
+ IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 | MUX_PAD_CTRL(PAD_CTL_PE |
+ PAD_CTL_PUE),
+};
+
+/* Extension board bridge GPIOs */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_I0 IMX_GPIO_NR(3, 0) /* IN 0 */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_I1 IMX_GPIO_NR(3, 1) /* IN 1 */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_I2 IMX_GPIO_NR(3, 6) /* IN 2 */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_I3 IMX_GPIO_NR(3, 7) /* IN 3 */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_O0 IMX_GPIO_NR(3, 8) /* OUT 0 */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_O1 IMX_GPIO_NR(3, 9) /* OUT 1 */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_O2 IMX_GPIO_NR(6, 9) /* OUT 2 */
+#define IOT_GATE_IMX8_GPIO_EXT_IED_O3 IMX_GPIO_NR(6, 10)/* OUT 3 */
+
+/* Extension board POE GPIOs */
+#define IOT_GATE_IMX8_GPIO_EXT_POE_MUX IMX_GPIO_NR(5, 1)/* USB_MUX */
+
+/*
+ * iot_gate_imx8_update_pinmux() - update the pinmux
+ * Update the pinmux according to the detected extended board.
+ */
+static void iot_gate_imx8_update_pinmux(void)
+{
+ if (iot_gate_imx8_ext_id == IOT_GATE_EXT_POEV2) {
+ imx_iomux_v3_setup_multiple_pads(iot_gate_imx8_ext_poev2_pads,
+ ARRAY_SIZE(iot_gate_imx8_ext_poev2_pads));
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_POE_MUX, "poev2_usb-mux");
+ /* Update USB MUX state */
+ gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_POE_MUX, 1);
+
+ return;
+ }
+ if (iot_gate_imx8_ext_id != IOT_GATE_EXT_IED)
+ return;
+
+ imx_iomux_v3_setup_multiple_pads(iot_gate_imx8_ext_ied_pads,
+ ARRAY_SIZE(iot_gate_imx8_ext_ied_pads));
+
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I0, "ied-di4o4_i0");
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I0);
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I1, "ied-di4o4_i1");
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I1);
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I2, "ied-di4o4_i2");
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I2);
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_I3, "ied-di4o4_i3");
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_EXT_IED_I3);
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O0, "ied-di4o4_o0");
+ gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O0, 0);
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O1, "ied-di4o4_o1");
+ gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O1, 0);
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O2, "ied-di4o4_o2");
+ gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O2, 0);
+ gpio_request(IOT_GATE_IMX8_GPIO_EXT_IED_O3, "ied-di4o4_o3");
+ gpio_direction_output(IOT_GATE_IMX8_GPIO_EXT_IED_O3, 0);
+}
+
+#define IOT_GATE_IMX8_GPIO_S0B0 IMX_GPIO_NR(6, 0) /* Slot ID slot 0 bit 0 */
+#define IOT_GATE_IMX8_GPIO_S0B1 IMX_GPIO_NR(6, 1) /* Slot ID slot 0 bit 1 */
+#define IOT_GATE_IMX8_GPIO_S0B2 IMX_GPIO_NR(6, 2) /* Slot ID slot 0 bit 2 */
+#define IOT_GATE_IMX8_GPIO_S1B0 IMX_GPIO_NR(6, 3) /* Slot ID slot 1 bit 0 */
+#define IOT_GATE_IMX8_GPIO_S1B1 IMX_GPIO_NR(6, 4) /* Slot ID slot 1 bit 1 */
+#define IOT_GATE_IMX8_GPIO_S1B2 IMX_GPIO_NR(6, 5) /* Slot ID slot 1 bit 2 */
+#define IOT_GATE_IMX8_GPIO_S2B0 IMX_GPIO_NR(6, 6) /* Slot ID slot 2 bit 0 */
+#define IOT_GATE_IMX8_GPIO_S2B1 IMX_GPIO_NR(6, 7) /* Slot ID slot 2 bit 1 */
+#define IOT_GATE_IMX8_GPIO_S2B2 IMX_GPIO_NR(6, 8) /* Slot ID slot 2 bit 2 */
+
+/*
+ * iot_gate_imx8_update_ext_ied()
+ * Update device tree of the extended board IED-BASE.
+ * The device tree is updated according to the detected sub modules.
+ *
+ * Return 0 for success, 1 for failure.
+ */
+static int iot_gate_imx8_update_ext_ied(void)
+{
+ int revision;
+
+ if (iot_gate_imx8_ext_id != IOT_GATE_EXT_IED)
+ return 0;
+
+ /* ID GPIO initializations */
+ if (gpio_request(IOT_GATE_IMX8_GPIO_S0B0, "id_s0b0") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S0B1, "id_s0b1") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S0B2, "id_s0b2") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S1B0, "id_s1b0") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S1B1, "id_s1b1") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S1B2, "id_s1b2") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S2B0, "id_s2b0") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S2B1, "id_s2b1") ||
+ gpio_request(IOT_GATE_IMX8_GPIO_S2B2, "id_s2b2")) {
+ printf("%s: ID GPIO request failure\n", __func__);
+ return 1;
+ }
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S0B0);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S0B1);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S0B2);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S1B0);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S1B1);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S1B2);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S2B0);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S2B1);
+ gpio_direction_input(IOT_GATE_IMX8_GPIO_S2B2);
+
+ /* Get slot 0 card ID */
+ revision = gpio_get_value(IOT_GATE_IMX8_GPIO_S0B0) |
+ gpio_get_value(IOT_GATE_IMX8_GPIO_S0B1) << 1 |
+ gpio_get_value(IOT_GATE_IMX8_GPIO_S0B2) << 2;
+ iot_gate_imx8_ext_ied_id[0] = revision;
+
+ /* Get slot 1 card ID */
+ revision = gpio_get_value(IOT_GATE_IMX8_GPIO_S1B0) |
+ gpio_get_value(IOT_GATE_IMX8_GPIO_S1B1) << 1 |
+ gpio_get_value(IOT_GATE_IMX8_GPIO_S1B2) << 2;
+ iot_gate_imx8_ext_ied_id[1] = revision;
+
+ /* Get slot 2 card ID */
+ revision = gpio_get_value(IOT_GATE_IMX8_GPIO_S2B0) |
+ gpio_get_value(IOT_GATE_IMX8_GPIO_S2B1) << 1 |
+ gpio_get_value(IOT_GATE_IMX8_GPIO_S2B2) << 2;
+ iot_gate_imx8_ext_ied_id[2] = revision;
+
+ return 0;
+}
+
+int board_fix_fdt(void *rw_fdt_blob)
+{
+ return 0;
+}
+
+int extension_board_scan(struct list_head *extension_list)
+{
+ struct extension *extension = NULL;
+ int i;
+ int ret = 0;
+
+ iot_gate_imx8_detect_ext(); /* Extended board detection */
+
+ switch(iot_gate_imx8_ext_id) {
+ case IOT_GATE_EXT_EMPTY:
+ break;
+ case IOT_GATE_EXT_CAN:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_EXT_CAN");
+ break;
+ case IOT_GATE_EXT_IED:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_EXT_IED");
+ snprintf(extension->overlay, sizeof(extension->overlay),
+ "imx8mm-cl-iot-gate-ied.dtbo");
+ break;
+ case IOT_GATE_EXT_POE:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_EXT_POE");
+ break;
+ case IOT_GATE_EXT_POEV2:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_EXT_POEV2");
+ break;
+ default:
+ printf("IOT_GATE-iMX8 extension board: unknown\n");
+ break;
+ }
+
+ if (extension) {
+ snprintf(extension->owner, sizeof(extension->owner),
+ "Compulab");
+ list_add_tail(&extension->list, extension_list);
+ ret = 1;
+ } else
+ return ret;
+
+ iot_gate_imx8_update_pinmux();
+
+ iot_gate_imx8_update_ext_ied();
+ for (i=0; i<ARRAY_SIZE(iot_gate_imx8_ext_ied_id); i++) {
+ extension = NULL;
+ switch (iot_gate_imx8_ext_ied_id[i]) {
+ case IOT_GATE_IMX8_CARD_ID_EMPTY:
+ break;
+ case IOT_GATE_IMX8_CARD_ID_RS_485:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_IMX8_CARD_ID_RS_485");
+ break;
+ case IOT_GATE_IMX8_CARD_ID_RS_232:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_IMX8_CARD_ID_RS_232");
+ break;
+ case IOT_GATE_IMX8_CARD_ID_CAN:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_IMX8_CARD_ID_CAN");
+ snprintf(extension->overlay, sizeof(extension->overlay),
+ "imx8mm-cl-iot-gate-ied-can%d.dtbo", i);
+ break;
+ case IOT_GATE_IMX8_CARD_ID_TPM:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_IMX8_CARD_ID_TPM");
+ snprintf(extension->overlay, sizeof(extension->overlay),
+ "imx8mm-cl-iot-gate-ied-tpm%d.dtbo", i);
+ break;
+ case IOT_GATE_IMX8_CARD_ID_CL420:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_IMX8_CARD_ID_CL420");
+ snprintf(extension->overlay, sizeof(extension->overlay),
+ "imx8mm-cl-iot-gate-ied-can%d.dtbo", i);
+ break;
+ case IOT_GATE_IMX8_CARD_ID_DI4O4:
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->name, sizeof(extension->name),
+ "IOT_GATE_IMX8_CARD_ID_DI4O4");
+ break;
+ default:
+ printf("%s: invalid slot %d card ID: %d\n",
+ __func__, i, iot_gate_imx8_ext_ied_id[i]);
+ break;
+ }
+ if (extension) {
+ snprintf(extension->owner, sizeof(extension->owner),
+ "Compulab");
+ snprintf(extension->other, sizeof(extension->other),
+ "On slot %d", i);
+ list_add_tail(&extension->list, extension_list);
+ ret = ret + 1;
+ }
+ }
+
+ return ret;
+}
+
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7e1000
* Copyright 2018 NXP
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
# Copyright (C) 2015, Google, Inc
obj-y += conga-qeval20-qa3.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
# Copyright (C) 2015, Google, Inc
obj-y += dfi-bt700.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "imx7ulp-com"))
+ return 0;
+
+ return -1;
+}
+#endif
+
+void spl_board_init(void)
+{
+ preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+ arch_cpu_init();
+
+ board_early_init_f();
+}
+#endif
PDU001 BOARD
M: Felix Brack <fb@ltec.ch>
S: Maintained
-F: board/eets/pdu001/
+F: board/eets/
F: include/configs/pdu001.h
F: configs/am335x_pdu001_defconfig
+F: arch/arm/dts/am335x-pdu001-u-boot.dtsi
+F: arch/arm/dts/am335x-pdu001.dts
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
+obj-y := board.o mux.o
return &dpll_ddr;
}
+void set_uart_mux_conf(void)
+{
+ switch (CONFIG_CONS_INDEX) {
+ case 1: {
+ enable_uart0_pin_mux();
+ break;
+ }
+ case 2: {
+ enable_uart1_pin_mux();
+ break;
+ }
+ case 3: {
+ enable_uart2_pin_mux();
+ break;
+ }
+ case 4: {
+ enable_uart3_pin_mux();
+ break;
+ }
+ case 5: {
+ enable_uart4_pin_mux();
+ break;
+ }
+ case 6: {
+ enable_uart5_pin_mux();
+ break;
+ }
+ }
+}
+
void set_mux_conf_regs(void)
{
/* done first by the ROM and afterwards by the pin controller driver */
#ifdef CONFIG_DEBUG_UART
void board_debug_uart_init(void)
{
+ setup_early_clocks();
+
/* done by pin controller driver if not debugging */
enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
}
imply DM_SCSI
imply SYS_NS16550
imply SIFIVE_SERIAL
+ imply HTIF_CONSOLE if 64BIT
imply SYSRESET
imply SYSRESET_CMD_POWEROFF
imply SYSRESET_SYSCON
#include <common.h>
#include <dm.h>
+#include <dm/ofnode.h>
#include <env.h>
#include <fdtdec.h>
#include <image.h>
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_MTD_NOR_FLASH)
+int is_flash_available(void)
+{
+ if (!ofnode_equal(ofnode_by_compatible(ofnode_null(), "cfi-flash"),
+ ofnode_null()))
+ return 1;
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/*
int board_late_init(void)
{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- env_set("board_name", "EVK");
- env_set("board_rev", "iMX8MM");
-#endif
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ env_set("board_name", "EVK");
+ env_set("board_rev", "iMX8MM");
+ }
+
return 0;
}
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7E1000
#include <env.h>
#include <init.h>
#include <asm/global_data.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_mmc_get_env_dev(int devno)
{
+ return devno;
+}
+
+static void setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
return 0;
}
-int board_mmc_get_env_dev(int devno)
+int board_init(void)
{
- return devno;
+ setup_fec();
+
+ return 0;
}
int board_late_init(void)
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
ROM_VERSION v2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x912000
+LOADER u-boot-spl-ddr.bin 0x912000
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
ROM_VERSION v2
BOOT_FROM sd
* Copyright 2018 NXP
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
* Copyright 2019 NXP
*/
-#define __ASSEMBLY__
/* This file is to create a container image could be loaded by SPL */
BOOT_FROM SD 0x400
* and create imx8image boot image
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
* Copyright 2019 NXP
*/
-#define __ASSEMBLY__
/* This file is to create a container image could be loaded by SPL */
BOOT_FROM SD 0x400
#include <asm/arch/sys_proto.h>
#include <miiphy.h>
#include <netdev.h>
+#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
+#define I2C_PAD_CTRL (PAD_CTL_ODE)
+static const iomux_cfg_t lpi2c0_pads[] = {
+ IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
+#define TPM_PAD_CTRL (PAD_CTL_DSE)
+static const iomux_cfg_t tpm0_pads[] = {
+ IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL),
+};
+
+void mipi_dsi_mux_panel(void)
+{
+ int ret;
+ struct gpio_desc desc;
+
+ /* It is temp solution to directly access i2c, need change to rpmsg later */
+
+ /* enable lpi2c0 clock and iomux */
+ imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads));
+ writel(0xD2000000, 0x28091060);
+
+ ret = dm_gpio_lookup_name("gpio@20_9", &desc);
+ if (ret) {
+ printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&desc, "dsi_mux");
+ if (ret) {
+ printf("%s request dsi_mux failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+void mipi_dsi_panel_backlight(void)
+{
+ /* It is temp solution to directly access pwm, need change to rpmsg later */
+ imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads));
+ writel(0xD4000001, 0x28091054);
+
+ /* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */
+ writel(1000, 0x28095018);
+ writel(1000, 0x28095034); /* MOD = CV, full duty */
+ writel(0x28, 0x28095010);
+ writel(0x20, 0x28095030);
+}
+
int board_init(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
+ if (IS_ENABLED(CONFIG_DM_VIDEO)) {
+ mipi_dsi_mux_panel();
+ mipi_dsi_panel_backlight();
+ }
+
return 0;
}
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
+ /* Load the lposc fuse for single boot to work around ROM issue,
+ * The fuse depends on S400 to read.
+ */
+ if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
+ load_lposc_fuse();
+
upower_init();
power_init_board();
/* Init XRDC MRC for VIDEO, DSP domains */
xrdc_init_mrc();
+
+ /* Call it after PS16 power up */
+ set_lpav_qos();
}
void board_init_f(ulong dummy)
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
ppa_init();
#endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
+
#ifdef CONFIG_U_QE
u_qe_init();
#endif
ppa_init();
#endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
+
/* invert AQR105 IRQ pins polarity */
out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2022 NXP
*/
#include <common.h>
#include <clock_legacy.h>
}
if (disable_ifc) {
- offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+ offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/ifc/nor");
+ offset = fdt_path_offset(fdt, "/memory-controller/nor");
} else {
offset = fdt_path_offset(fdt, "/soc/quadspi");
#else
#ifdef CONFIG_FSL_QSPI
- offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+ offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
if (offset < 0)
- offset = fdt_path_offset(fdt, "/ifc/nor");
+ offset = fdt_path_offset(fdt, "/memory-controller/nor");
#else
offset = fdt_path_offset(fdt, "/soc/quadspi");
*
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
config IMX_CONFIG
default "board/gateworks/venice/imximage-8mm-lpddr4.cfg"
endif
+
+if TARGET_IMX8MN_VENICE
+
+config SYS_BOARD
+ default "venice"
+
+config SYS_VENDOR
+ default "gateworks"
+
+config SYS_CONFIG_NAME
+ default "imx8mn_venice"
+
+config IMX_CONFIG
+ default "board/gateworks/venice/imximage-8mn-lpddr4.cfg"
+endif
i.MX8MM Venice
M: Tim Harvey <tharvey@gateworks.com>
S: Maintained
-F: arch/arm/dts/imx8mm-venice*
+F: arch/arm/dts/imx8m*-venice*
F: board/gateworks/venice/
-F: include/configs/venice.h
-F: configs/imx8mm_venice_defconfig
+F: include/configs/imx8m*_venice.h
+F: configs/imx8m*_venice_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += imx8mm_venice.o gsc.o
+obj-y += venice.o gsc.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+ifdef CONFIG_IMX8MM
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_imx8mm.o
+endif
+ifdef CONFIG_IMX8MN
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_imx8mn.o
+endif
endif
===========
=> tftpboot $loadaddr flash.bin
=> setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
-=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt
+=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt # for IMX8MM
+=> mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt # for IMX8MN
snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__)
const char *gsc_get_dtb_name(int level, char *buf, int sz)
{
+#ifdef CONFIG_IMX8MM
const char *pre = "imx8mm-venice-gw";
+#else
+ const char *pre = "imx8mn-venice-gw";
+#endif
int model, rev_pcb, rev_bom;
model = ((som_info.model[2] - '0') * 1000)
* board may be ready to probe the GSC before its firmware is
* running. We will wait here indefinately for the GSC/EEPROM.
*/
+#ifdef CONFIG_IMX8MN
+ // TODO:
+ // IMX8MN boots quicker than IMX8MM and exposes issue
+ // where because GSC I2C state machine isn't running and its
+ // SCL/SDA are driven low spams i2c errors
+ //
+ // Put a loop here that somehow waits for I2C CLK/DAT to be high
+ mdelay(40);
+#endif
while (1) {
/* probe device */
dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR);
* Copyright 2021 Gateworks Corporation
*/
-#define __ASSEMBLY__
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7E1000
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x912000
#ifndef __LPDDR4_TIMING_H__
#define __LPDDR4_TIMING_H__
+#ifdef CONFIG_IMX8MM
extern struct dram_timing_info dram_timing_1gb;
extern struct dram_timing_info dram_timing_2gb;
extern struct dram_timing_info dram_timing_4gb;
+#elif CONFIG_IMX8MN
+extern struct dram_timing_info dram_timing_1gb_single_die;
+extern struct dram_timing_info dram_timing_2gb_single_die;
+extern struct dram_timing_info dram_timing_2gb_dual_die;
+#endif
#endif /* __LPDDR4_TIMING_H__ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/*
+ * Generated code from MX8M_DDR_tool v3.20 using RPAv15
+ */
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x020072, 0x0},
+ {0x020073, 0x0},
+ {0x020074, 0x0},
+ {0x0100aa, 0x0},
+ {0x0110aa, 0x0},
+ {0x020010, 0x0},
+ {0x120010, 0x0},
+ {0x220010, 0x0},
+ {0x020011, 0x0},
+ {0x120011, 0x0},
+ {0x220011, 0x0},
+ {0x0100ae, 0x0},
+ {0x1100ae, 0x0},
+ {0x2100ae, 0x0},
+ {0x0100af, 0x0},
+ {0x1100af, 0x0},
+ {0x2100af, 0x0},
+ {0x0110ae, 0x0},
+ {0x1110ae, 0x0},
+ {0x2110ae, 0x0},
+ {0x0110af, 0x0},
+ {0x1110af, 0x0},
+ {0x2110af, 0x0},
+ {0x020020, 0x0},
+ {0x120020, 0x0},
+ {0x220020, 0x0},
+ {0x0100a0, 0x0},
+ {0x0100a1, 0x0},
+ {0x0100a2, 0x0},
+ {0x0100a3, 0x0},
+ {0x0100a4, 0x0},
+ {0x0100a5, 0x0},
+ {0x0100a6, 0x0},
+ {0x0100a7, 0x0},
+ {0x0110a0, 0x0},
+ {0x0110a1, 0x0},
+ {0x0110a2, 0x0},
+ {0x0110a3, 0x0},
+ {0x0110a4, 0x0},
+ {0x0110a5, 0x0},
+ {0x0110a6, 0x0},
+ {0x0110a7, 0x0},
+ {0x02007c, 0x0},
+ {0x12007c, 0x0},
+ {0x22007c, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x0400fd, 0x0},
+ {0x0400c0, 0x0},
+ {0x090201, 0x0},
+ {0x190201, 0x0},
+ {0x290201, 0x0},
+ {0x090202, 0x0},
+ {0x190202, 0x0},
+ {0x290202, 0x0},
+ {0x090203, 0x0},
+ {0x190203, 0x0},
+ {0x290203, 0x0},
+ {0x090204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x090205, 0x0},
+ {0x190205, 0x0},
+ {0x290205, 0x0},
+ {0x090206, 0x0},
+ {0x190206, 0x0},
+ {0x290206, 0x0},
+ {0x090207, 0x0},
+ {0x190207, 0x0},
+ {0x290207, 0x0},
+ {0x090208, 0x0},
+ {0x190208, 0x0},
+ {0x290208, 0x0},
+ {0x010062, 0x0},
+ {0x010162, 0x0},
+ {0x010262, 0x0},
+ {0x010362, 0x0},
+ {0x010462, 0x0},
+ {0x010562, 0x0},
+ {0x010662, 0x0},
+ {0x010762, 0x0},
+ {0x010862, 0x0},
+ {0x011062, 0x0},
+ {0x011162, 0x0},
+ {0x011262, 0x0},
+ {0x011362, 0x0},
+ {0x011462, 0x0},
+ {0x011562, 0x0},
+ {0x011662, 0x0},
+ {0x011762, 0x0},
+ {0x011862, 0x0},
+ {0x020077, 0x0},
+ {0x010001, 0x0},
+ {0x011001, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x448 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0xf },
+ { 0x9016b, 0x7c0 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x0 },
+ { 0x9016e, 0xe8 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x47 },
+ { 0x90171, 0x630 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x8 },
+ { 0x90174, 0x618 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0xe0 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x7c8 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x8 },
+ { 0x9017d, 0x8140 },
+ { 0x9017e, 0x10c },
+ { 0x9017f, 0x0 },
+ { 0x90180, 0x1 },
+ { 0x90181, 0x8 },
+ { 0x90182, 0x8 },
+ { 0x90183, 0x4 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x7c8 },
+ { 0x90187, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x64 },
+ { 0x2000c, 0xc8 },
+ { 0x2000d, 0x7d0 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+/*
+ * Generated code from MX8M_DDR_tool v3.20 using RPAv15
+ * - imx8mn-gw7902 1x Micron MT53D512M16D1 16bit single-die for total of 1GiB
+ */
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x213 },
+ { 0x3d400024, 0x3e800 },
+ { 0x3d400064, 0x6100e0 },
+ { 0x3d4000d0, 0xc003061c },
+ { 0x3d4000d4, 0x9e0000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x1a201b22 },
+ { 0x3d400104, 0x60633 },
+ { 0x3d40010c, 0xc0c000 },
+ { 0x3d400110, 0xf04080f },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xe6 },
+ { 0x3d400144, 0xa00050 },
+ { 0x3d400180, 0x3200018 },
+ { 0x3d400184, 0x28061a8 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x11 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x11 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x3 },
+ { 0x100a3, 0x4 },
+ { 0x100a4, 0x5 },
+ { 0x100a5, 0x2 },
+ { 0x100a6, 0x7 },
+ { 0x100a7, 0x6 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x2 },
+ { 0x110a3, 0x3 },
+ { 0x110a4, 0x4 },
+ { 0x110a5, 0x5 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+ { 0x2200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+static struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg_1gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg_1gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1gb_single_die),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg_1gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1gb_single_die = {
+ .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die),
+ .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_1gb_single_die),
+ .fsp_msg = ddr_dram_fsp_msg_1gb_single_die,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1gb_single_die),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
+
+/*
+ * Generated code from MX8M_DDR_tool v3.20 using RPAv15
+ * - imx8mn-gw7902 - 2x Micron MT53E1G16D1FW 16bit single-die for total of 2GiB
+ */
+static struct dram_cfg_param ddr_ddrc_cfg_2gb_single_die[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x203 },
+ { 0x3d400024, 0x3e800 },
+ { 0x3d400064, 0x610130 },
+ { 0x3d4000d0, 0xc003061c },
+ { 0x3d4000d4, 0x9e0000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x1a201b22 },
+ { 0x3d400104, 0x60633 },
+ { 0x3d40010c, 0xc0c000 },
+ { 0x3d400110, 0xf04080f },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x136 },
+ { 0x3d400144, 0xa00050 },
+ { 0x3d400180, 0x3200018 },
+ { 0x3d400184, 0x28061a8 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0x7 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc0026 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x27 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x3000a },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0xa },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg_2gb_single_die[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+ { 0x2200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg_2gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg_2gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg_2gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg_2gb_single_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_single_die[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg_2gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_2gb_single_die),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg_2gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_2gb_single_die),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg_2gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_2gb_single_die),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg_2gb_single_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_2gb_single_die),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_2gb_single_die = {
+ .ddrc_cfg = ddr_ddrc_cfg_2gb_single_die,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_single_die),
+ .ddrphy_cfg = ddr_ddrphy_cfg_2gb_single_die,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_2gb_single_die),
+ .fsp_msg = ddr_dram_fsp_msg_2gb_single_die,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_2gb_single_die),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
+
+/*
+ * Generated code from MX8M_DDR_tool v3.20 using RPAv15
+ * - imx8mn-gw7902 2x Kingston C1612PC2WDGTKR 16bit dual-die for total of 2GiB
+ */
+static struct dram_cfg_param ddr_ddrc_cfg_2gb_dual_die[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x203 },
+ { 0x3d400024, 0x3e800 },
+ { 0x3d400064, 0x6100e0 },
+ { 0x3d4000d0, 0xc003061c },
+ { 0x3d4000d4, 0x9e0000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x1a201b22 },
+ { 0x3d400104, 0x60633 },
+ { 0x3d40010c, 0xc0c000 },
+ { 0x3d400110, 0xf04080f },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xe6 },
+ { 0x3d400144, 0xa00050 },
+ { 0x3d400180, 0x3200018 },
+ { 0x3d400184, 0x28061a8 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg_2gb_dual_die[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+ { 0x2200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg_2gb_dual_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg_2gb_dual_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg_2gb_dual_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg_2gb_dual_die[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_dual_die[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg_2gb_dual_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_2gb_dual_die),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg_2gb_dual_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_2gb_dual_die),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg_2gb_dual_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_2gb_dual_die),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg_2gb_dual_die,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_2gb_dual_die),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_2gb_dual_die = {
+ .ddrc_cfg = ddr_ddrc_cfg_2gb_dual_die,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_dual_die),
+ .ddrphy_cfg = ddr_ddrphy_cfg_2gb_dual_die,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_2gb_dual_die),
+ .fsp_msg = ddr_dram_fsp_msg_2gb_dual_die,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_2gb_dual_die),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/imx8mn_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
struct dram_timing_info *dram_timing;
switch (size) {
+#ifdef CONFIG_IMX8MM
case 1:
dram_timing = &dram_timing_1gb;
break;
printf("Unknown DDR configuration: %d GiB\n", size);
dram_timing = &dram_timing_1gb;
size = 1;
+#endif
+#ifdef CONFIG_IMX8MN
+ case 1:
+ dram_timing = &dram_timing_1gb_single_die;
+ break;
+ case 2:
+ if (!strcmp(gsc_get_model(), "GW7902-SP466-A") ||
+ !strcmp(gsc_get_model(), "GW7902-SP466-B")) {
+ dram_timing = &dram_timing_2gb_dual_die;
+ } else {
+ dram_timing = &dram_timing_2gb_single_die;
+ }
+ break;
+ default:
+ printf("Unknown DDR configuration: %d GiB\n", size);
+ dram_timing = &dram_timing_2gb_dual_die;
+ size = 2;
+#endif
}
printf("DRAM : LPDDR4 %d GiB\n", size);
ddr_init(dram_timing);
- writel(size, M4_BOOTROM_BASE_ADDR);
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#ifdef CONFIG_IMX8MM
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
+#endif
+#ifdef CONFIG_IMX8MN
+static const iomux_v3_cfg_t uart_pads[] = {
+ IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+#endif
int board_early_init_f(void)
{
IMAGE_VERSION 2
BOOT_FROM sd
-#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
# Copyright 2019 Google LLC
obj-y += coral.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
obj-y += bayleybay.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
#
obj-y += edison.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
obj-y += galileo.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
# Copyright (C) 2015, Google, Inc
obj-y += minnowmax.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2009-2012
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
* Luka Perkov <luka@openwrt.org>
#include <common.h>
#include <init.h>
-#include <miiphy.h>
+#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/global_data.h>
-#include "iconnect.h"
+#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
+#define ICONNECT_OE_LOW (~BIT(7))
+#define ICONNECT_OE_HIGH (~BIT(10))
+#define ICONNECT_OE_VAL_LOW (0)
+#define ICONNECT_OE_VAL_HIGH BIT(10)
+
int board_early_init_f(void)
{
/*
return 0;
}
+int board_eth_init(struct bd_info *bis)
+{
+ return cpu_eth_init(bis);
+}
+
int board_init(void)
{
- /* adress of boot parameters */
+ /* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009-2012
- * Wojciech Dubowik <wojciech.dubowik@neratec.com>
- * Luka Perkov <luka@openwrt.org>
- */
-
-#ifndef __ICONNECT_H
-#define __ICONNECT_H
-
-#define ICONNECT_OE_LOW (~(1 << 7))
-#define ICONNECT_OE_HIGH (~(1 << 10))
-#define ICONNECT_OE_VAL_LOW (0)
-#define ICONNECT_OE_VAL_HIGH (1 << 10)
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __ICONNECT_H */
help
Page size of inventory in EEPROM.
+config PG_WCOM_UBOOT_UPDATE_SUPPORTED
+ bool "Enable U-boot Field Fail-Safe Update Functionality"
+ default n
+ help
+ Indicates that field fail-safe u-boot update is supported.
+ This functionality works only for designs that are booting
+ from parallel NOR flash.
+
+config PG_WCOM_UBOOT_BOOTPACKAGE
+ bool "U-boot Is Part Of Factory Boot-Package Image"
+ default n
+ help
+ Indicates that u-boot will be a part of the factory programmed
+ boot-package image.
+ Has to be set for original u-boot programmed at factory.
+
+config PG_WCOM_UBOOT_UPDATE_TEXT_BASE
+ hex "Text Base For U-boot Programmed Outside Factory"
+ default 0xFFFFFFFF
+ help
+ Text base of an updated u-boot that is not factory programmed but
+ later when the unit is rolled out on the field.
+ Has to be set for original u-boot programmed at factory.
+
+config PG_WCOM_UBOOT_UPDATE
+ bool "U-boot Is Part Of Factory Boot-Package Image"
+ default n
+ help
+ Indicates that u-boot will be a part of the embedded software and
+ programmed at field.
+ Has to be set for updated u-boot version programmed at field.
+
source "board/keymile/km83xx/Kconfig"
source "board/keymile/kmcent2/Kconfig"
source "board/keymile/km_arm/Kconfig"
--- /dev/null
+Field Fail-Save U-boot Update
+-----------------------------
+Field Fail-Save u-boot update is a feature that allows save u-boot update
+of FOX and XMC products that are rolled out in the field.
+
+The feature is initially implemented for designs based on LS102x SoC, but in
+theory can be used on all designs that are booting from parallel NOR flash.
+
+The implementation expects redundant (secondary) u-boot image on a predefined
+location in the NOR flash, u-boot execution will be transferred to the redundant
+(secondary) u-boot and redundant u-boot will be started if 'updateduboot' envvar
+is set to 'yes'.
+Update logic check_for_uboot_update() has to be invoked from the design early
+before relocation just after SoC initialization, e.g from board_early_init_f or
+misc_init_f functions.
+By design it is expected that primary u-boot image is burned in the factory and
+never updated, and in case u-boot update is required it can flashed and started
+from secondary u-boot location.
#include <asm/io.h>
#include <linux/ctype.h>
#include <linux/delay.h>
+#include <linux/bug.h>
+#include <bootcount.h>
#if defined(CONFIG_POST)
#include "post.h"
return 0;
}
+#if CONFIG_IS_ENABLED(PG_WCOM_UBOOT_UPDATE_SUPPORTED)
+#if ((!CONFIG_IS_ENABLED(PG_WCOM_UBOOT_BOOTPACKAGE) && \
+ !CONFIG_IS_ENABLED(PG_WCOM_UBOOT_UPDATE)) || \
+ (CONFIG_IS_ENABLED(PG_WCOM_UBOOT_BOOTPACKAGE) && \
+ CONFIG_IS_ENABLED(PG_WCOM_UBOOT_UPDATE)))
+#error "It has to be either bootpackage or update u-boot image!"
+#endif
+void check_for_uboot_update(void)
+{
+ void (*uboot_update_entry)(void) =
+ (void (*)(void)) CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE;
+ char *isupdated = env_get("updateduboot");
+ ulong bootcount = bootcount_load();
+ ulong ebootcount = 0;
+
+ if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_BOOTPACKAGE)) {
+ /*
+ * When running in factory burned u-boot move to the updated
+ * u-boot version only if updateduboot envvar is set to 'yes'
+ * and bootcount limit is not exceeded.
+ * Board must be able to start in factory bootloader mode!
+ */
+ if (isupdated && !strncmp(isupdated, "yes", 3) &&
+ bootcount <= CONFIG_BOOTCOUNT_BOOTLIMIT) {
+ printf("Check update: update detected, ");
+ printf("starting new image @%08x ...\n",
+ CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE);
+ ebootcount = early_bootcount_load();
+ if (ebootcount <= CONFIG_BOOTCOUNT_BOOTLIMIT) {
+ early_bootcount_store(++ebootcount);
+ uboot_update_entry();
+ } else {
+ printf("Check update: warning: ");
+ printf("early bootcount exceeded (%lu)\n",
+ ebootcount);
+ }
+ }
+ printf("Check update: starting factory image @%08x ...\n",
+ CONFIG_SYS_TEXT_BASE);
+ } else if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE)) {
+ /*
+ * When running in field updated u-boot, make sure that
+ * bootcount limit is never exceeded. Must never happen!
+ */
+ WARN_ON(bootcount > CONFIG_BOOTCOUNT_BOOTLIMIT);
+ printf("Check update: updated u-boot starting @%08x ...\n",
+ CONFIG_SYS_TEXT_BASE);
+ }
+}
+#endif
+
#if defined(CONFIG_SYS_I2C_INIT_BOARD)
static void i2c_write_start_seq(void)
{
int set_km_env(void);
+ulong early_bootcount_load(void);
+void early_bootcount_store(ulong ebootcount);
+void check_for_uboot_update(void);
+
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
(id_rev >> 8) & 0xff, id_rev & 0xff);
}
+#define SLFTEST_OFF 0x06
+
+bool qrio_get_selftest_pin(void)
+{
+ u8 slftest;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ slftest = in_8(qrio_base + SLFTEST_OFF);
+
+ return (slftest & 1) > 0;
+}
+
+#define BPRTH_OFF 0x04
+
+bool qrio_get_pgy_pres_pin(void)
+{
+ u8 pgy_pres;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ pgy_pres = in_8(qrio_base + BPRTH_OFF);
+
+ return (pgy_pres & 0x80) > 0;
+}
+
int qrio_get_gpio(u8 port_off, u8 gpio_nr)
{
u32 gprt;
out_8(qrio_base + RSTCFG_OFF, rstcfg);
}
+/* Early bootcount memory area is avilable starting from QRIO3 Rev.2 */
+#define QRIO3_ID 0x71
+#define QRIO3_REV 0x02
+#define EBOOTCNT_OFF 0x28
+
+ulong early_bootcount_load(void)
+{
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
+ u8 id = (id_rev >> 8) & 0xff;
+ u8 rev = id_rev & 0xff;
+ u32 ebootcount = 0;
+
+ if (id == QRIO3_ID && rev >= QRIO3_REV) {
+ ebootcount = in_be32(qrio_base + EBOOTCNT_OFF);
+ } else {
+ printf("QRIO: warning: early bootcount not supported, ");
+ printf("id = %u, rev = %u\n", id, rev);
+ }
+
+ return ebootcount;
+}
+
+void early_bootcount_store(ulong ebootcount)
+{
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
+ u8 id = (id_rev >> 8) & 0xff;
+ u8 rev = id_rev & 0xff;
+
+ if (id == QRIO3_ID && rev >= QRIO3_REV) {
+ out_be32(qrio_base + EBOOTCNT_OFF, ebootcount);
+ } else {
+ printf("QRIO: warning: early bootcount not supported, ");
+ printf("id = %u, rev = %u\n", id, rev);
+ }
+}
+
/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
* 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
* For I2C only the low state is activly driven and high state is pulled-up
#define QRIO_GPIO_B 0x60
void show_qrio(void);
+bool qrio_get_selftest_pin(void);
+bool qrio_get_pgy_pres_pin(void);
int qrio_get_gpio(u8 port_off, u8 gpio_nr);
void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
F: include/configs/pg-wcom-seli8.h
F: include/configs/pg-wcom-expu1.h
F: configs/pg_wcom_seli8_defconfig
+F: configs/pg_wcom_seli8_update_defconfig
F: configs/pg_wcom_expu1_defconfig
+F: configs/pg_wcom_expu1_update_defconfig
F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts
F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts
qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_CLIPS_RST, false, false);
#endif
+
+ /* deasset debug phy reset only if piggy is present */
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
- qrio_prst(KM_DBG_ETH_RST, false, false);
+ qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false);
i2c_deblock_gpio_cfg();
return 0;
}
+int misc_init_f(void)
+{
+ if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED))
+ check_for_uboot_update();
+ return 0;
+}
+
int board_init(void)
{
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
int misc_init_r(void)
{
- if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
- device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+ device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
#if defined(CONFIG_POST)
int post_hotkeys_pressed(void)
{
- /* DIC26_SELFTEST: GPRTA0, GPA0 */
- qrio_gpio_direction_input(QRIO_GPIO_A, 0);
- return qrio_get_gpio(QRIO_GPIO_A, 0);
+ /* DIC26_SELFTEST: QRIO, SLFTEST */
+ return qrio_get_selftest_pin();
}
+/* POST word is located in the unused SCRATCHRW4 register */
+#define CCSR_SCRATCHRW4_ADDR 0x1ee020c
+
ulong post_word_load(void)
{
- /* POST word is located at the beginning of reserved physical RAM */
- void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
- gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
+ void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
return in_le32(addr);
}
void post_word_store(ulong value)
{
- /* POST word is located at the beginning of reserved physical RAM */
- void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
- gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
+ void *addr = (void *)CCSR_SCRATCHRW4_ADDR;
out_le32(addr, value);
}
--- /dev/null
+if TARGET_KONTRON_PITX_IMX8M
+
+config SYS_BOARD
+ default "pitx_imx8m"
+
+config SYS_VENDOR
+ default "kontron"
+
+config SYS_CONFIG_NAME
+ default "kontron_pitx_imx8m"
+
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
--- /dev/null
+Kontron pITX-imx8m Board
+M: Heiko Thiery <heiko.thiery@gmail.com>
+S: Maintained
+F: arch/arm/dts/imx8mq-kontron-pitx-imx8m*
+F: board/kontron/pitx_imx8m/*
+F: include/configs/kontron_pitx_imx8m.h
+F: configs/kontron_pitx_imx8m_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += pitx_imx8m.o pitx_misc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o pitx_misc.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_2gb.o lpddr4_timing_4gb.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400028, 0x0 },
+ { 0x3d400020, 0x202 },
+ { 0x3d400024, 0x3e800 },
+ { 0x3d400064, 0x1800e0 },
+ { 0x3d4000d0, 0xc003061c },
+ { 0x3d4000d4, 0x9e0000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310008 },
+ { 0x3d4000e8, 0x66004a },
+ { 0x3d4000ec, 0x16004a },
+ { 0x3d400100, 0x1a200624 },
+ { 0x3d400104, 0x60636 },
+ { 0x3d40010c, 0xc0c000 },
+ { 0x3d400110, 0x10040a10 },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xe6 },
+ { 0x3d400144, 0xa00050 },
+ { 0x3d400180, 0xc3200018 },
+ { 0x3d400184, 0x28061a8 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0x639 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d402020, 0x0 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0x3001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004a },
+ { 0x3d4020ec, 0x16004a },
+ { 0x3d402100, 0xa040005 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0xc0640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d403020, 0x0 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004a },
+ { 0x3d4030ec, 0x16004a },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0xc0190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d400244, 0x0 },
+ { 0x3d400250, 0x29001505 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x5900575b },
+ { 0x3d400264, 0x90000096 },
+ { 0x3d40026c, 0x1000012c },
+ { 0x3d400300, 0x16 },
+ { 0x3d400304, 0x0 },
+ { 0x3d40030c, 0x0 },
+ { 0x3d400320, 0x1 },
+ { 0x3d40036c, 0x11 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x10f3 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400490, 0x1 },
+ { 0x3d400494, 0xe00 },
+ { 0x3d400498, 0x62ffff },
+ { 0x3d40049c, 0xe00 },
+ { 0x3d4004a0, 0xffff },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x2 },
+ { 0x100a1, 0x3 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x1 },
+ { 0x100a4, 0x5 },
+ { 0x100a5, 0x7 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x4 },
+ { 0x110a0, 0x2 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x6 },
+ { 0x110a5, 0x7 },
+ { 0x110a6, 0x4 },
+ { 0x110a7, 0x5 },
+ { 0x120a0, 0x4 },
+ { 0x120a1, 0x5 },
+ { 0x120a2, 0x7 },
+ { 0x120a3, 0x6 },
+ { 0x120a4, 0x1 },
+ { 0x120a5, 0x3 },
+ { 0x120a6, 0x2 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x4 },
+ { 0x130a1, 0x5 },
+ { 0x130a2, 0x7 },
+ { 0x130a3, 0x6 },
+ { 0x130a4, 0x2 },
+ { 0x130a5, 0x1 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x3 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x80 },
+ { 0x1200c7, 0x80 },
+ { 0x2200c7, 0x80 },
+ { 0x200ca, 0x106 },
+ { 0x1200ca, 0x106 },
+ { 0x2200ca, 0x106 },
+ { 0x20110, 0x2 },
+ { 0x20111, 0x3 },
+ { 0x20112, 0x4 },
+ { 0x20113, 0x5 },
+ { 0x20114, 0x0 },
+ { 0x20115, 0x1 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x64 },
+ { 0x2000c, 0xc8 },
+ { 0x2000d, 0x7d0 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_2gb = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400028, 0x0 },
+ { 0x3d400020, 0x202 },
+ { 0x3d400024, 0x3e800 },
+ { 0x3d400064, 0x1800e0 },
+ { 0x3d4000d0, 0xc003061c },
+ { 0x3d4000d4, 0x9e0000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310008 },
+ { 0x3d4000e8, 0x66004a },
+ { 0x3d4000ec, 0x16004a },
+ { 0x3d400100, 0x1a200624 },
+ { 0x3d400104, 0x60636 },
+ { 0x3d40010c, 0xc0c000 },
+ { 0x3d400110, 0x10040a10 },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xe6 },
+ { 0x3d400144, 0xa00050 },
+ { 0x3d400180, 0xc3200018 },
+ { 0x3d400184, 0x28061a8 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0x639 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d402020, 0x0 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0x3001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004a },
+ { 0x3d4020ec, 0x16004a },
+ { 0x3d402100, 0xa040005 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0xc0640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d403020, 0x0 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004a },
+ { 0x3d4030ec, 0x16004a },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0xc0190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d400244, 0x0 },
+ { 0x3d400250, 0x29001505 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x5900575b },
+ { 0x3d400264, 0x90000096 },
+ { 0x3d40026c, 0x1000012c },
+ { 0x3d400300, 0x16 },
+ { 0x3d400304, 0x0 },
+ { 0x3d40030c, 0x0 },
+ { 0x3d400320, 0x1 },
+ { 0x3d40036c, 0x11 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x10f3 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400490, 0x1 },
+ { 0x3d400494, 0xe00 },
+ { 0x3d400498, 0x62ffff },
+ { 0x3d40049c, 0xe00 },
+ { 0x3d4004a0, 0xffff },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x2 },
+ { 0x100a1, 0x3 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x1 },
+ { 0x100a4, 0x5 },
+ { 0x100a5, 0x7 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x4 },
+ { 0x110a0, 0x2 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x6 },
+ { 0x110a5, 0x7 },
+ { 0x110a6, 0x4 },
+ { 0x110a7, 0x5 },
+ { 0x120a0, 0x4 },
+ { 0x120a1, 0x5 },
+ { 0x120a2, 0x7 },
+ { 0x120a3, 0x6 },
+ { 0x120a4, 0x1 },
+ { 0x120a5, 0x3 },
+ { 0x120a6, 0x2 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x4 },
+ { 0x130a1, 0x5 },
+ { 0x130a2, 0x7 },
+ { 0x130a3, 0x6 },
+ { 0x130a4, 0x2 },
+ { 0x130a5, 0x1 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x3 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x80 },
+ { 0x1200c7, 0x80 },
+ { 0x2200c7, 0x80 },
+ { 0x200ca, 0x106 },
+ { 0x1200ca, 0x106 },
+ { 0x2200ca, 0x106 },
+ { 0x20110, 0x2 },
+ { 0x20111, 0x3 },
+ { 0x20112, 0x4 },
+ { 0x20113, 0x5 },
+ { 0x20114, 0x0 },
+ { 0x20115, 0x1 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x64 },
+ { 0x2000c, 0xc8 },
+ { 0x2000d, 0x7d0 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_4gb = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "pitx_misc.h"
+#include <common.h>
+#include <init.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <linux/delay.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *memsize)
+{
+ int variant = 0;
+
+ variant = get_pitx_board_variant();
+
+ switch(variant) {
+ case 2:
+ *memsize = 0x80000000;
+ break;
+ case 3:
+ *memsize = 0x100000000;
+ break;
+ default:
+ printf("Unknown DDR type!!!\n");
+ *memsize = 0x40000000;
+ break;
+ }
+
+ debug("Memsize: %d MiB\n", (int)(*memsize >> 20));
+
+ return 0;
+}
+
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 11)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+ ARRAY_SIZE(fec1_rst_pads));
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_fec();
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ unsigned int val;
+
+ /*
+ * Set LED configuration register 1:
+ * LED2_SEL: 0b1011 (link established, blink on activity)
+ */
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x18);
+ val &= 0xf0ff;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x18, val | (0xb << 8));
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+ init_usb_clk();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+#define TPM_RESET IMX_GPIO_NR(3, 2)
+#define USBHUB_RESET IMX_GPIO_NR(3, 4)
+
+static void reset_device_by_gpio(const char *label, int pin, int delay_ms)
+{
+ gpio_request(pin, label);
+ gpio_direction_output(pin, 0);
+ mdelay(delay_ms);
+ gpio_direction_output(pin, 1);
+}
+
+int misc_init_r(void)
+{
+ /*
+ * reset TPM chip (Infineon SLB9670) as required by datasheet
+ * (60ms minimum Reset Inactive Time, 70ms implemented)
+ */
+ reset_device_by_gpio("tpm_reset", TPM_RESET, 70);
+
+ /*
+ * reset USB hub as required by datasheet
+ * (3ms minimum reset duration, 10ms implemented)
+ */
+ reset_device_by_gpio("usbhub_reset", USBHUB_RESET, 10);
+
+ return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+uint mmc_get_env_part(struct mmc *mmc)
+{
+ /* part 1 for eMMC, part 1 for SD card */
+ return (mmc_get_env_dev() == 0) ? 1 : 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/imx8mq_pins.h>
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/gpio.h>
+
+/*
+ * BRD_REV1 BRD_REV0
+ * 0 0 n/a
+ * 0 1 n/a
+ * 1 0 2GB LPDDR4
+ * 1 1 4GB LPDDR4
+ */
+
+#define BRD_REV0 IMX_GPIO_NR(5, 0)
+#define BRD_REV1 IMX_GPIO_NR(5, 1)
+
+static iomux_v3_cfg_t const brdrev_pads[] = {
+ IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 | MUX_PAD_CTRL(PAD_CTL_PUE),
+ IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 | MUX_PAD_CTRL(PAD_CTL_PUE),
+ IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(PAD_CTL_PUE),
+};
+
+int get_pitx_board_variant(void)
+{
+ int variant = 0;
+
+ imx_iomux_v3_setup_multiple_pads(brdrev_pads, ARRAY_SIZE(brdrev_pads));
+
+ gpio_request(BRD_REV0, "BRD_REV0");
+ gpio_direction_input(BRD_REV0);
+ gpio_request(BRD_REV1, "BRD_REV1");
+ gpio_direction_input(BRD_REV1);
+
+ variant |= !!gpio_get_value(BRD_REV0) << 0;
+ variant |= !!gpio_get_value(BRD_REV1) << 1;
+
+ return variant;
+}
--- /dev/null
+#ifndef __PITX_MISC_H
+#define __PITX_MISC_H
+
+int get_pitx_board_variant(void);
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <errno.h>
+#include <fsl_esdhc_imx.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+#include "pitx_misc.h"
+
+extern struct dram_timing_info dram_timing_2gb;
+extern struct dram_timing_info dram_timing_4gb;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+static void spl_dram_init(void)
+{
+ struct dram_timing_info *dram_timing;
+ int variant = 0, size;
+
+ variant = get_pitx_board_variant();
+
+ switch(variant) {
+ case 2:
+ dram_timing = &dram_timing_2gb;
+ size = 2;
+ break;
+ case 3:
+ dram_timing = &dram_timing_4gb;
+ size = 4;
+ break;
+ default:
+ printf("Unknown DDR type (%d)\n", variant);
+ return;
+ };
+
+ /* ddr init */
+ ddr_init(dram_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#if CONFIG_IS_ENABLED(MMC)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ /* the eMMC does not have a CD pin */
+ return 1;
+ case USDHC2_BASE_ADDR:
+ return !gpio_get_value(USDHC2_CD_GPIO);
+ }
+
+ return 0;
+}
+
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+ IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 8},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ init_clk_usdhc(0);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+ ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ break;
+ case 1:
+ init_clk_usdhc(1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+ ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers "
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+const char *spl_board_loader_name(u32 boot_device)
+{
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return "eMMC";
+ case BOOT_DEVICE_MMC2:
+ return "SD card";
+ default:
+ return NULL;
+ }
+}
+#endif
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC 0
+
+static int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+ unsigned char offset, i, switch_num;
+ u32 id;
+ int ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+ id = id & 0xf;
+
+ if (id == 0) {
+ switch_num = 6;
+ offset = PFUZE100_SW1CMODE;
+ } else if (id == 1) {
+ switch_num = 4;
+ offset = PFUZE100_SW2MODE;
+ } else {
+ printf("Not supported, id=%d\n", id);
+ return -EINVAL;
+ }
+
+ ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+ if (ret < 0) {
+ printf("Set SW1AB mode error!\n");
+ return ret;
+ }
+
+ for (i = 0; i < switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+ if (ret < 0) {
+ printf("Set switch 0x%x mode error!\n",
+ offset + i * SWITCH_SIZE);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return -ENODEV;
+
+ p = pmic_get("PFUZE100");
+ ret = pmic_probe(p);
+ if (ret)
+ return -ENODEV;
+
+ pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
+ if ((reg & 0x3f) != 0x18) {
+ reg &= ~0x3f;
+ reg |= 0x18;
+ pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
+ }
+
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret < 0)
+ return ret;
+
+ /* set SW3A standby mode to off */
+ pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
+ reg &= ~0xf;
+ reg |= APS_OFF;
+ pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+
+ init_uart_clk(2);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ setup_i2c(0, 100000, 0x7f, &i2c_pad_info1);
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+ power_init_board();
+#endif
+
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
* Copyright (C) 2019 Kontron Electronics GmbH
*/
-#define __ASSEMBLY__
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7E1000
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <fsl_ddr.h>
#include <asm/arch/soc.h>
#include <fsl_immap.h>
#include <netdev.h>
+#include <wdt.h>
+#include <sl28cpld.h>
#include <fdtdec.h>
#include <miiphy.h>
return pci_eth_init(bis);
}
+static int __sl28cpld_read(uint reg)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_NOP,
+ DM_DRIVER_GET(sl28cpld), &dev);
+ if (ret)
+ return ret;
+
+ return sl28cpld_read(dev, reg);
+}
+
+static void print_cpld_version(void)
+{
+ int version = __sl28cpld_read(SL28CPLD_VERSION);
+
+ if (version < 0)
+ printf("CPLD: error reading version (%d)\n", version);
+ else
+ printf("CPLD: v%d\n", version);
+}
+
int checkboard(void)
{
printf("EL: %d\n", current_el());
+ if (CONFIG_IS_ENABLED(SL28CPLD))
+ print_cpld_version();
+
+ return 0;
+}
+
+static void stop_recovery_watchdog(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_WDT,
+ DM_DRIVER_GET(sl28cpld_wdt), &dev);
+ if (!ret)
+ wdt_stop(dev);
+}
+
+int fsl_board_late_init(void)
+{
+ /*
+ * Usually, the after a board reset, the watchdog is enabled by
+ * default. This is to supervise the bootloader boot-up. Therefore,
+ * to prevent a watchdog reset if we don't actively kick it, we have
+ * to disable it.
+ *
+ * If the watchdog isn't enabled at reset (which is a configuration
+ * option) disabling it doesn't hurt either.
+ */
+ if (!CONFIG_IS_ENABLED(WATCHDOG_AUTOSTART))
+ stop_recovery_watchdog();
+
return 0;
}
void detail_board_ddr_info(void)
{
- puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
}
F: board/liebherr/xea/
F: include/configs/xea.h
F: configs/imx28_xea_defconfig
+F: configs/imx28_xea_sb_defconfig
0x00000000, 0xffffffff
};
+#ifndef CONFIG_SPL_FRAMEWORK
+void board_init_ll(const u32 arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
+#else
void lowlevel_init(void)
{
struct mxs_pinctrl_regs *pinctrl_regs =
mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
}
+#endif
mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
}
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
void board_init_f(ulong arg)
{
init_clocks();
#include <twl4030.h>
#include <i2c.h>
#include <video_fb.h>
+#include <keyboard.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/setup.h>
static u8 keybuf_tail;
/*
- * Routine: rx51_kp_init
+ * Routine: rx51_kp_start
* Description: Initialize HW keyboard.
*/
-int rx51_kp_init(void)
+static int rx51_kp_start(struct udevice *dev)
{
int ret = 0;
u8 ctrl;
* Routine: rx51_kp_tstc
* Description: Test if key was pressed (from buffer).
*/
-int rx51_kp_tstc(struct stdio_dev *sdev)
+static int rx51_kp_tstc(struct udevice *dev)
{
u8 c, r, dk, i;
u8 intr;
* Routine: rx51_kp_getc
* Description: Get last pressed key (from buffer).
*/
-int rx51_kp_getc(struct stdio_dev *sdev)
+static int rx51_kp_getc(struct udevice *dev)
{
keybuf_head %= KEYBUF_SIZE;
- while (!rx51_kp_tstc(sdev))
+ while (!rx51_kp_tstc(dev))
WATCHDOG_RESET();
return keybuf[keybuf_head++];
}
+static int rx51_kp_probe(struct udevice *dev)
+{
+ struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct stdio_dev *sdev = &uc_priv->sdev;
+
+ strcpy(sdev->name, "keyboard");
+ return input_stdio_register(sdev);
+}
+
+static const struct keyboard_ops rx51_kp_ops = {
+ .start = rx51_kp_start,
+ .tstc = rx51_kp_tstc,
+ .getc = rx51_kp_getc,
+};
+
+U_BOOT_DRIVER(rx51_kp) = {
+ .name = "rx51_kp",
+ .id = UCLASS_KEYBOARD,
+ .probe = rx51_kp_probe,
+ .ops = &rx51_kp_ops,
+};
+
static const struct mmc_config rx51_mmc_cfg = {
.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
.f_min = 400000,
U_BOOT_DRVINFOS(rx51_watchdog) = {
{ "rx51_watchdog" },
};
+
+U_BOOT_DRVINFOS(rx51_kp) = {
+ { "rx51_kp" },
+};
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
// Copyright (C) 2016 Freescale Semiconductor, Inc.
// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
-#define __ASSEMBLY__
#include <config.h>
/* image version */
// Copyright (C) 2016 Freescale Semiconductor, Inc.
// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* Copyright 2021 Phytec Messtechnik GmbH
*/
-#define __ASSEMBLY__
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7E1000
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
ROM_VERSION v2
BOOT_FROM sd
* Copyright 2021 NXP
*/
-#define __ASSEMBLY__
BOOT_FROM sd
LOADER mkimage.flash.mkimage 0x7E1000
\ No newline at end of file
* and create imx8image boot image
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
* Copyright 2019 NXP
*/
-#define __ASSEMBLY__
/* This file is to create a container image could be loaded by SPL */
BOOT_FROM SD 0x400
* Copyright (C) 2017-2019 softing automotive electronics gmbH
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
*/
#include <common.h>
#include <env.h>
+#include <fdt_support.h>
#include <init.h>
#include <log.h>
#include <stdlib.h>
env_set("serial#", serial);
}
+#define SBL_BOARD "board_id="
+#define SBL_LCDTYPE "lcdtype="
+static ulong board_id = 0;
+static ulong lcdtype = 0;
+
+static void parse_cmdline(const struct tag_cmdline *cmdline)
+{
+ char *buf;
+
+ /* Export this to sbl_cmdline (secondary boot loader command line) */
+ env_set("sbl_cmdline", cmdline->cmdline);
+
+ buf = strstr(cmdline->cmdline, SBL_BOARD);
+ if (!buf)
+ return;
+ buf += strlen(SBL_BOARD);
+
+ board_id = simple_strtoul(buf, NULL, 10);
+
+ buf = strstr(cmdline->cmdline, SBL_LCDTYPE);
+ if (!buf)
+ return;
+ buf += strlen(SBL_LCDTYPE);
+
+ lcdtype = simple_strtoul(buf, NULL, 10);
+}
+
/*
* The downstream/vendor kernel (provided by Samsung) uses ATAGS for booting.
* It also requires an extremely long cmdline provided by the primary bootloader
if (t->hdr.tag == ATAG_SERIAL)
parse_serial(&t->u.serialnr);
+ if (t->hdr.tag == ATAG_CMDLINE)
+ parse_cmdline(&t->u.cmdline);
+
fw_atags_size += t->hdr.size * sizeof(u32);
}
memcpy(*in_params, fw_atags_copy, fw_atags_size);
*(u8 **)in_params += fw_atags_size;
}
+
+/* These numbers are unique per product but not across all products */
+#define SAMSUNG_CODINA_LCD_LMS380KF01 4
+#define SAMSUNG_CODINA_LCD_S6D27A1 13
+#define SAMSUNG_SKOMER_LCD_HVA40WV1 10
+#define SAMSUNG_SKOMER_LCD_NT35512 12
+
+static void codina_patch_display(void *fdt)
+{
+ int node;
+ int ret;
+
+ node = fdt_path_offset(fdt, "/spi-gpio-0/panel");
+ if (node < 0) {
+ printf("cannot find Codina panel node\n");
+ return;
+ }
+ if (lcdtype == SAMSUNG_CODINA_LCD_LMS380KF01) {
+ ret = fdt_setprop_string(fdt, node, "compatible", "samsung,lms380kf01");
+ if (ret < 0)
+ printf("could not set LCD compatible\n");
+ else
+ printf("updated LCD compatible to LMS380KF01\n");
+ } else if (lcdtype == SAMSUNG_CODINA_LCD_S6D27A1) {
+ ret = fdt_setprop_string(fdt, node, "compatible", "samsung,s6d27a1");
+ if (ret < 0)
+ printf("could not set LCD compatible\n");
+ else
+ printf("updated LCD compatible to S6D27A1\n");
+ } else {
+ printf("unknown LCD type\n");
+ }
+}
+
+static void skomer_kyle_patch_display(void *fdt)
+{
+ int node;
+ int ret;
+
+ node = fdt_path_offset(fdt, "/soc/mcde/dsi/panel");
+ if (node < 0) {
+ printf("cannot find Skomer/Kyle panel node\n");
+ return;
+ }
+ if (lcdtype == SAMSUNG_SKOMER_LCD_HVA40WV1) {
+ ret = fdt_setprop_string(fdt, node, "compatible", "hydis,hva40wv1");
+ if (ret < 0)
+ printf("could not set LCD compatible\n");
+ else
+ printf("updated LCD compatible to Hydis HVA40WV1\n");
+ } else if (lcdtype == SAMSUNG_SKOMER_LCD_NT35512) {
+ /*
+ * FIXME: This panel is actually a BOE product, but we don't know
+ * the exact product name, so the compatible for the NT35512
+ * is used for the time being. The vendor drivers also call it NT35512.
+ */
+ ret = fdt_setprop_string(fdt, node, "compatible", "novatek,nt35512");
+ if (ret < 0)
+ printf("could not set LCD compatible\n");
+ else
+ printf("updated LCD compatible to Novatek NT35512\n");
+ } else {
+ printf("unknown LCD type\n");
+ }
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+ const char *str;
+ int node;
+ int ret;
+
+ printf("stemmy patch: DTB at 0x%08lx\n", (ulong)fdt);
+
+ /* Inspect FDT to see what we've got here */
+ ret = fdt_check_header(fdt);
+ if (ret < 0) {
+ printf("invalid DTB\n");
+ return ret;
+ }
+ node = fdt_path_offset(fdt, "/");
+ if (node < 0) {
+ printf("cannot find root node\n");
+ return node;
+ }
+ str = fdt_stringlist_get(fdt, node, "compatible", 0, NULL);
+ if (!str) {
+ printf("could not find board compatible\n");
+ return -1;
+ }
+
+ if (!strcmp(str, "samsung,janice")) {
+ switch(board_id) {
+ case 7:
+ printf("Janice GT-I9070 Board Rev 0.0\n");
+ break;
+ case 8:
+ printf("Janice GT-I9070 Board Rev 0.1\n");
+ break;
+ case 9:
+ printf("Janice GT-I9070 Board Rev 0.2\n");
+ break;
+ case 10:
+ printf("Janice GT-I9070 Board Rev 0.3\n");
+ break;
+ case 11:
+ printf("Janice GT-I9070 Board Rev 0.4\n");
+ break;
+ case 12:
+ printf("Janice GT-I9070 Board Rev 0.5\n");
+ break;
+ case 13:
+ printf("Janice GT-I9070 Board Rev 0.6\n");
+ break;
+ default:
+ break;
+ }
+ } else if (!strcmp(str, "samsung,gavini")) {
+ switch(board_id) {
+ case 7:
+ printf("Gavini GT-I8530 Board Rev 0.0\n");
+ break;
+ case 8:
+ printf("Gavini GT-I8530 Board Rev 0.0A\n");
+ break;
+ case 9:
+ printf("Gavini GT-I8530 Board Rev 0.0B\n");
+ break;
+ case 10:
+ printf("Gavini GT-I8530 Board Rev 0.0A_EMUL\n");
+ break;
+ case 11:
+ printf("Gavini GT-I8530 Board Rev 0.0C\n");
+ break;
+ case 12:
+ printf("Gavini GT-I8530 Board Rev 0.0D\n");
+ break;
+ case 13:
+ printf("Gavini GT-I8530 Board Rev 0.1\n");
+ break;
+ case 14:
+ printf("Gavini GT-I8530 Board Rev 0.3\n");
+ break;
+ default:
+ break;
+ }
+ } else if (!strcmp(str, "samsung,codina")) {
+ switch(board_id) {
+ case 7:
+ printf("Codina GT-I8160 Board Rev 0.0\n");
+ break;
+ case 8:
+ printf("Codina GT-I8160 Board Rev 0.1\n");
+ break;
+ case 9:
+ printf("Codina GT-I8160 Board Rev 0.2\n");
+ break;
+ case 10:
+ printf("Codina GT-I8160 Board Rev 0.3\n");
+ break;
+ case 11:
+ printf("Codina GT-I8160 Board Rev 0.4\n");
+ break;
+ case 12:
+ printf("Codina GT-I8160 Board Rev 0.5\n");
+ break;
+ default:
+ break;
+ }
+ codina_patch_display(fdt);
+ } else if (!strcmp(str, "samsung,codina-tmo")) {
+ switch(board_id) {
+ case 0x101:
+ printf("Codina SGH-T599 Board pre-Rev 0.0\n");
+ break;
+ case 0x102:
+ printf("Codina SGH-T599 Board Rev 0.0\n");
+ break;
+ case 0x103:
+ printf("Codina SGH-T599 Board Rev 0.1\n");
+ break;
+ case 0x104:
+ printf("Codina SGH-T599 Board Rev 0.2\n");
+ break;
+ case 0x105:
+ printf("Codina SGH-T599 Board Rev 0.4\n");
+ break;
+ case 0x106:
+ printf("Codina SGH-T599 Board Rev 0.6\n");
+ break;
+ case 0x107:
+ printf("Codina SGH-T599 Board Rev 0.7\n");
+ break;
+ default:
+ break;
+ }
+ codina_patch_display(fdt);
+ } else if (!strcmp(str, "samsung,golden")) {
+ switch(board_id) {
+ case 0x102:
+ printf("Golden GT-I8190 Board SW bringup\n");
+ break;
+ case 0x103:
+ printf("Golden GT-I8190 Board Rev 0.2\n");
+ break;
+ case 0x104:
+ printf("Golden GT-I8190 Board Rev 0.3\n");
+ break;
+ case 0x105:
+ printf("Golden GT-I8190 Board Rev 0.4\n");
+ break;
+ case 0x106:
+ printf("Golden GT-I8190 Board Rev 0.5\n");
+ break;
+ case 0x107:
+ printf("Golden GT-I8190 Board Rev 0.6\n");
+ break;
+ default:
+ break;
+ }
+ } else if (!strcmp(str, "samsung,skomer")) {
+ switch(board_id) {
+ case 0x101:
+ printf("Skomer GT-S7710 Board Rev 0.0\n");
+ break;
+ case 0x102:
+ printf("Skomer GT-S7710 Board Rev 0.1\n");
+ break;
+ case 0x103:
+ printf("Skomer GT-S7710 Board Rev 0.2\n");
+ break;
+ case 0x104:
+ printf("Skomer GT-S7710 Board Rev 0.3\n");
+ break;
+ case 0x105:
+ printf("Skomer GT-S7710 Board Rev 0.4\n");
+ break;
+ case 0x106:
+ printf("Skomer GT-S7710 Board Rev 0.5\n");
+ break;
+ case 0x107:
+ printf("Skomer GT-S7710 Board Rev 0.6\n");
+ break;
+ case 0x108:
+ printf("Skomer GT-S7710 Board Rev 0.7\n");
+ break;
+ case 0x109:
+ printf("Skomer GT-S7710 Board Rev 0.8\n");
+ break;
+ default:
+ break;
+ }
+ skomer_kyle_patch_display(fdt);
+ } else if (!strcmp(str, "samsung,kyle")) {
+ switch(board_id) {
+ case 0x101:
+ printf("Kyle SGH-I407 Board Rev 0.0\n");
+ break;
+ case 0x102:
+ printf("Kyle SGH-I407 Board Rev 0.1\n");
+ break;
+ case 0x103:
+ printf("Kyle SGH-I407 Board Rev 0.2\n");
+ break;
+ case 0x104:
+ printf("Kyle SGH-I407 Board Rev 0.3\n");
+ break;
+ case 0x105:
+ printf("Kyle SGH-I407 Board Rev 0.4\n");
+ break;
+ case 0x106:
+ printf("Kyle SGH-I407 Board Rev 0.5\n");
+ break;
+ case 0x107:
+ printf("Kyle SGH-I407 Board Rev 0.6\n");
+ break;
+ default:
+ break;
+ }
+ skomer_kyle_patch_display(fdt);
+ }
+
+ return 0;
+}
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
IMAGE_VERSION 2
/* DDR initialization came from Phytec */
DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
DATA 4 0x30360388 0x40000000
DATA 4 0x30360384 0x40000000
+
+/* deassert presetn */
DATA 4 0x30391000 0x00000002
+
+/* DDR Controller Regs */
DATA 4 0x307a0000 0x01040001
-DATA 4 0x307a01a0 0x80400003
-DATA 4 0x307a01a4 0x00100020
-DATA 4 0x307a01a8 0x80100004
-DATA 4 0x307a0064 0x0040002b
+DATA 4 0x307a0064 0x00400046
DATA 4 0x307a0490 0x00000001
-DATA 4 0x307a00d0 0x00020083
DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00d0 0x00020083
DATA 4 0x307a00dc 0x09300004
-DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e0 0x04480000
DATA 4 0x307a00e4 0x00100004
DATA 4 0x307a00f4 0x0000033f
-DATA 4 0x307a0100 0x090b1109
-DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0100 0x090e110a
+DATA 4 0x307a0104 0x0007020e
DATA 4 0x307a0108 0x03040407
DATA 4 0x307a010c 0x00002006
-DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0110 0x04020304
DATA 4 0x307a0114 0x03030202
-DATA 4 0x307a0120 0x00000802
+DATA 4 0x307a0120 0x00000803
DATA 4 0x307a0180 0x00800020
-DATA 4 0x307a0184 0x02000100
DATA 4 0x307a0190 0x02098204
DATA 4 0x307a0194 0x00030303
-DATA 4 0x307a0200 0x00001f15
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0200 0x0000001f
DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a020c 0x00000000
DATA 4 0x307a0210 0x00000f0f
DATA 4 0x307a0214 0x07070707
-DATA 4 0x307a0218 0x0f0f0707
+DATA 4 0x307a0218 0x0f070707
DATA 4 0x307a0240 0x06000604
DATA 4 0x307a0244 0x00000001
+
+/* deassert presetn */
DATA 4 0x30391000 0x00000000
+
+/* PHY Controller Regs */
DATA 4 0x30790000 0x17420f40
DATA 4 0x30790004 0x10210100
DATA 4 0x30790010 0x00060807
DATA 4 0x307900b0 0x1010007e
DATA 4 0x3079009c 0x00000d6e
-DATA 4 0x30790020 0x0a0a0a0a
-DATA 4 0x30790030 0x06060606
+/* write leveling values for each byte lane */
+DATA 4 0x3079006c 0x06090108
+/* write leveling resync cycle */
+DATA 4 0x30790078 0x00000001
+DATA 4 0x30790078 0x00000000
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790020 0x08080808
DATA 4 0x30790050 0x01000010
DATA 4 0x30790050 0x00000010
+DATA 4 0x30790018 0x0000000f
+
+/* start manual ZQ */
DATA 4 0x307900c0 0x0e407304
DATA 4 0x307900c0 0x0e447304
DATA 4 0x307900c0 0x0e447306
-CHECK_BITS_SET 4 0x307900c4 0x1
DATA 4 0x307900c0 0x0e447304
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+/* end manual ZQ */
DATA 4 0x307900c0 0x0e407304
+
+/* final init sequence */
DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x30384130 0x00000002
DATA 4 0x30790018 0x0000000f
+
CHECK_BITS_SET 4 0x307a0004 0x1
S: Maintained
F: configs/LicheePi_Zero_defconfig
+LICHEEPI NANO BOARD
+M: Icenowy Zheng <icenowy@aosc.xyz>
+S: Maintained
+F: configs/licheepi_nano_defconfig
+
LINKSPRITE-PCDUINO BOARD
M: Zoltan Herpai <wigyori@uid0.hu>
S: Maintained
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
-#ifndef CONFIG_ARM64
+#if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
debug("id_pfr1: 0x%08x\n", id_pfr1);
/* Generic Timer Extension available? */
#endif
}
}
-#endif /* !CONFIG_ARM64 */
+#endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
ret = axp_gpio_init();
if (ret)
* Copyright (C) 2017 Soeren Moch <smoch@web.de>
*/
-#define __ASSEMBLY__
#include "asm/arch/crm_regs.h"
#include "asm/arch/iomux.h"
#include "asm/arch/mx6-ddr.h"
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \
board_ti_k3_is("J721EX-PM2-SOM"))
+#define board_is_j721e_sk() (board_ti_k3_is("J721EX-EAIK") || \
+ board_ti_k3_is("J721EX-SK"))
+
#define board_is_j7200_som() (board_ti_k3_is("J7200X-PM1-SOM") || \
board_ti_k3_is("J7200X-PM2-SOM"))
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- if (!strcmp(name, "k3-j721e-common-proc-board"))
- return 0;
+ bool eeprom_read = board_ti_was_eeprom_read();
+
+ if (!eeprom_read || board_is_j721e_som()) {
+ if (!strcmp(name, "k3-j721e-common-proc-board") ||
+ !strcmp(name, "k3-j721e-r5-common-proc-board"))
+ return 0;
+ } else if (board_is_j721e_sk()) {
+ if (!strcmp(name, "k3-j721e-sk") ||
+ !strcmp(name, "k3-j721e-r5-sk"))
+ return 0;
+ }
return -1;
}
{
int ret;
+ if (board_ti_was_eeprom_read())
+ return 0;
+
ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
- if (ret)
- pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
- CONFIG_EEPROM_CHIP_ADDRESS, ret);
+ if (ret) {
+ printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+ CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS + 1);
+ if (ret)
+ pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+ CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+ }
return ret;
}
return 0;
}
-static void setup_board_eeprom_env(void)
-{
- char *name = "j721e";
-
- if (do_board_detect())
- goto invalid_eeprom;
-
- if (board_is_j721e_som())
- name = "j721e";
- else if (board_is_j7200_som())
- name = "j7200";
- else
- printf("Unidentified board claims %s in eeprom header\n",
- board_ti_get_name());
-
-invalid_eeprom:
- set_board_info_env_am6(name);
-}
-
-static void setup_serial(void)
-{
- struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
- unsigned long board_serial;
- char *endp;
- char serial_string[17] = { 0 };
-
- if (env_get("serial#"))
- return;
-
- board_serial = hextoul(ep->serial, &endp);
- if (*endp != '\0') {
- pr_err("Error: Can't set serial# to %s\n", ep->serial);
- return;
- }
-
- snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
- env_set("serial#", serial_string);
-}
-
/*
* Declaration of daughtercards to probe. Note that when adding more
* cards they should be grouped by the 'i2c_addr' field to allow for a
printf("phy_power_on failed !!\n");
}
+void configure_serdes_sierra(void)
+{
+ struct udevice *dev, *lnk_dev;
+ struct phy serdes;
+ int ret, count, i;
+
+ if (!IS_ENABLED(CONFIG_PHY_CADENCE_SIERRA))
+ return;
+
+ ret = uclass_get_device_by_driver(UCLASS_PHY,
+ DM_DRIVER_GET(sierra_phy_provider),
+ &dev);
+ if (ret)
+ printf("Sierra init failed:%d\n", ret);
+
+ serdes.dev = dev;
+ serdes.id = 0;
+
+ count = device_get_child_count(dev);
+ for (i = 0; i < count; i++) {
+ ret = device_get_child(dev, i, &lnk_dev);
+ if (ret)
+ printf("probe of sierra child node %d failed\n", i);
+ }
+
+ ret = generic_phy_init(&serdes);
+ if (ret)
+ printf("phy_init failed!!\n");
+
+ ret = generic_phy_power_on(&serdes);
+ if (ret)
+ printf("phy_power_on failed !!\n");
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static void setup_board_eeprom_env(void)
+{
+ char *name = "j721e";
+
+ if (do_board_detect())
+ goto invalid_eeprom;
+
+ if (board_is_j721e_som())
+ name = "j721e";
+ else if (board_is_j721e_sk())
+ name = "j721e-sk";
+ else if (board_is_j7200_som())
+ name = "j7200";
+ else
+ printf("Unidentified board claims %s in eeprom header\n",
+ board_ti_get_name());
+
+invalid_eeprom:
+ set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+ unsigned long board_serial;
+ char *endp;
+ char serial_string[17] = { 0 };
+
+ if (env_get("serial#"))
+ return;
+
+ board_serial = hextoul(ep->serial, &endp);
+ if (*endp != '\0') {
+ pr_err("Error: Can't set serial# to %s\n", ep->serial);
+ return;
+ }
+
+ snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+ env_set("serial#", serial_string);
+}
+
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
setup_serial();
/* Check for and probe any plugged-in daughtercards */
- probe_daughtercards();
+ if (board_is_j721e_som() || board_is_j7200_som())
+ probe_daughtercards();
}
if (board_is_j7200_som())
configure_serdes_torrent();
+ if (board_is_j721e_som())
+ configure_serdes_sierra();
+
return 0;
}
+#endif
void spl_board_init(void)
{
if ((IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM) ||
IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM)) &&
- IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
- probe_daughtercards();
+ IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+ if (!board_is_j721e_sk())
+ probe_daughtercards();
+ }
#ifdef CONFIG_ESM_K3
if (board_ti_k3_is("J721EX-PM2-SOM")) {
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+# David Huang <d-huang@ti.com>
+
+choice
+ prompt "K3 J721S2 board"
+ optional
+
+config TARGET_J721S2_A72_EVM
+ bool "TI K3 based J721S2 EVM running on A72"
+ select ARM64
+ select SOC_K3_J721S2
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+
+config TARGET_J721S2_R5_EVM
+ bool "TI K3 based J721S2 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select SOC_K3_J721S2
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_J721S2_A72_EVM
+
+config SYS_BOARD
+ default "j721s2"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721s2_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J721S2_R5_EVM
+
+config SYS_BOARD
+ default "j721s2"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721s2_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
--- /dev/null
+J721S2 BOARD
+M: Aswath Govindraju <a-govindraju@ti.com>
+S: Maintained
+F: board/ti/j721s2
+F: include/configs/j721s2_evm.h
+F: configs/j721s2_evm_r5_defconfig
+F: configs/j721s2_evm_a72_defconfig
+F: arch/arm/dts/k3-j721s2.dtsi
+F: arch/arm/dts/k3-j721s2-main.dtsi
+F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+F: arch/arm/dts/k3-j721s2-som-p0.dtsi
+F: arch/arm/dts/k3-j721s2-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-ddr.dtsi
+F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
--- /dev/null
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+# David Huang <d-huang@ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J721S2 EVM
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * David Huang <d-huang@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <generic-phy.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/sys_proto.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+
+#include "../common/board_detect.h"
+
+#define board_is_j721s2_som() board_ti_k3_is("J721S2X-PM1-SOM")
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_PHYS_64BIT
+ gd->ram_size = 0x100000000;
+#else
+ gd->ram_size = 0x80000000;
+#endif
+
+ return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x100000000)
+ return 0x100000000;
+#endif
+
+ return gd->ram_top;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x7fffffff;
+ gd->ram_size = 0x80000000;
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].size = 0x37fffffff;
+ gd->ram_size = 0x400000000;
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "k3-j721s2-common-proc-board"))
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+
+ ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+ if (ret < 0)
+ ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+ "sram@70000000");
+ if (ret)
+ printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+ int ret;
+
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (ret)
+ pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+ CONFIG_EEPROM_CHIP_ADDRESS, ret);
+
+ return ret;
+}
+
+int checkboard(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (do_board_detect())
+ /* EEPROM not populated */
+ printf("Board: %s rev %s\n", "J721S2X-PM1-SOM", "E1");
+ else
+ printf("Board: %s rev %s\n", ep->name, ep->version);
+
+ return 0;
+}
+
+static void setup_board_eeprom_env(void)
+{
+ char *name = "j721s2";
+
+ if (do_board_detect())
+ goto invalid_eeprom;
+
+ if (board_is_j721s2_som())
+ name = "j721s2";
+ else
+ printf("Unidentified board claims %s in eeprom header\n",
+ board_ti_get_name());
+
+invalid_eeprom:
+ set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+ unsigned long board_serial;
+ char *endp;
+ char serial_string[17] = { 0 };
+
+ if (env_get("serial#"))
+ return;
+
+ board_serial = simple_strtoul(ep->serial, &endp, 16);
+ if (*endp != '\0') {
+ pr_err("Error: Can't set serial# to %s\n", ep->serial);
+ return;
+ }
+
+ snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+ env_set("serial#", serial_string);
+}
+#endif
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+ setup_board_eeprom_env();
+ setup_serial();
+ }
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+}
* and create imx8image boot image
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM EMMC_FASTBOOT 0x400
* and create imx8image boot image
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM EMMC_FASTBOOT 0x400
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* and create imx8image boot image
*/
-#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM EMMC_FASTBOOT 0x400
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* Copyright 2020-2021 Toradex
*/
-#define __ASSEMBLY__
BOOT_FROM emmc_fastboot
LOADER u-boot-spl-ddr.bin 0x7e1000
--- /dev/null
+if TARGET_VERDIN_IMX8MP
+
+config IMX_CONFIG
+ default "board/toradex/verdin-imx8mp/imximage.cfg"
+
+config SYS_BOARD
+ default "verdin-imx8mp"
+
+config SYS_CONFIG_NAME
+ default "verdin-imx8mp"
+
+config SYS_VENDOR
+ default "toradex"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "2"
+
+config TDX_CFG_BLOCK_EXTRA
+ default y
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+config TDX_HAVE_EEPROM_EXTRA
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+source "board/toradex/common/Kconfig"
+
+endif
--- /dev/null
+Verdin iMX8M Plus
+F: arch/arm/dts/imx8mp-verdin.dts
+F: arch/arm/dts/imx8mp-verdin-u-boot.dtsi
+F: board/toradex/verdin-imx8mp/
+F: configs/verdin-imx8mp_defconfig
+F: doc/board/toradex/verdin-imx8mp.rst
+F: include/configs/verdin-imx8mp.h
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S: Maintained
+W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright 2022 Toradex
+#
+
+obj-y += verdin-imx8mp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2022 Toradex
+ */
+
+ROM_VERSION v2
+BOOT_FROM emmc_fastboot
+LOADER u-boot-spl-ddr.bin 0x920000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Toradex
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+ { 0x3d400070, 0x61027f10 },
+ { 0x3d400074, 0x7b0 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x807bf },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x9121c1c },
+ { 0x3d400200, 0x18 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x1 },
+ { 0x100a1, 0x6 },
+ { 0x100a2, 0x4 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x2 },
+ { 0x100a5, 0x7 },
+ { 0x100a6, 0x5 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x4 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x2 },
+ { 0x130a5, 0x6 },
+ { 0x130a6, 0x5 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x18 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x3e8 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x7d },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+struct dram_cfg_param ddr_ddrc_cfg2[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+ { 0x3d400070, 0x61027f10 },
+ { 0x3d400074, 0x7b0 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x807bf },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x9121c1c },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg2[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg2[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg2[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg2[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg2,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg2,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg2,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg2,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2),
+ },
+};
+
+/* quad die, dual rank aka 8 GB DDR timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+/* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */
+struct dram_timing_info dram_timing2 = {
+ .ddrc_cfg = ddr_ddrc_cfg2,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg2,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 Toradex
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+extern struct dram_timing_info dram_timing2;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ /*
+ * try configuring for quad die, dual rank aka 8 GB falling back to
+ * dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails
+ */
+ if (ddr_init(&dram_timing)) {
+ printf("Quad die, dual rank failed, attempting dual die, single rank configuration.\n");
+ ddr_init(&dram_timing2);
+ }
+}
+
+void spl_board_init(void)
+{
+ /*
+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+ * not allow to change it. Should set the clock after PMIC
+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+ * set by ROM for ND VDD_SOC
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+
+ puts("Normal Boot\n");
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+
+ ret = power_pca9450_init(I2C_PMIC, 0x25);
+ if (ret)
+ printf("power init failed\n");
+ p = pmic_get("PCA9450");
+ pmic_probe(p);
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+
+ /*
+ * increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85v for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
+ /* set DVS0 to 0.85v for special case */
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+ else
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1c);
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+ /* Kernel uses OD/OD freq for SoC */
+ /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */
+ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+ /* set LDO4 and CONFIG2 to enable the I2C level translator */
+ pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59);
+ pmic_reg_write(p, PCA9450_CONFIG2, 0x1);
+
+ return 0;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+/* Do not use BSS area in this phase */
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ board_early_init_f();
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ enable_tzc380();
+
+ /* Adjust PMIC voltage to 1.0V for 800 MHz */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ /* PMIC initialization */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 Toradex
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm-generic/gpio.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <errno.h>
+#include <env.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+/* Verdin UART_3, Console/Debug UART */
+static const iomux_v3_cfg_t uart_pads[] = {
+ MX8MP_PAD_UART3_RXD__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX8MP_PAD_UART3_TXD__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+ MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(2);
+
+ return 0;
+}
+
+static void setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Enable RGMII TX clk output */
+ setbits_le32(&gpr->gpr[1], BIT(22));
+}
+
+static int setup_eqos(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+ setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
+#if IS_ENABLED(CONFIG_NET)
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ int ret = 0;
+
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
+ if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
+ ret = setup_eqos();
+
+ return ret;
+}
+
+static void select_dt_from_module_version(void)
+{
+ char variant[32];
+ char *env_variant = env_get("variant");
+ int is_wifi = 0;
+
+ if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+ /*
+ * If we have a valid config block and it says we are a module with
+ * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+ */
+ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) ||
+ (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) ||
+ (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT);
+ }
+
+ if (is_wifi)
+ strlcpy(&variant[0], "wifi", sizeof(variant));
+ else
+ strlcpy(&variant[0], "nonwifi", sizeof(variant));
+
+ if (strcmp(variant, env_variant)) {
+ printf("Setting variant to %s\n", variant);
+ env_set("variant", variant);
+
+ if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+ env_save();
+ }
+}
+
+int board_late_init(void)
+{
+ select_dt_from_module_version();
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+#endif
/* image version */
IMAGE_VERSION 2
-#define __ASSEMBLY__
#include <config.h>
/*
/* image version */
IMAGE_VERSION 2
-#define __ASSEMBLY__
#include <config.h>
/*
/* image version */
IMAGE_VERSION 2
-#define __ASSEMBLY__
#include <config.h>
/*
--- /dev/null
+config TEN64_CONTROLLER
+ bool "Enable Ten64 board controller driver"
+ depends on TARGET_TEN64
+ help
+ Support for the board microcontroller on the Traverse
+ Ten64 family of boards.
--- /dev/null
+obj-$(CONFIG_TEN64_CONTROLLER) += ten64_controller.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef TEN64_CNTRL_H
+#define TEN64_CNTRL_H
+
+/**
+ * struct t64uc_board_info - Board Information Structure
+ * @mac: Base MAC address
+ * @cpuId: Microcontroller unique serial number
+ * @fwversion_major: Microcontroller version number (Major)
+ * @fwversion_minor: Microcontroller version number (Minor)
+ * @fwversion_patch: Microcontroller version number (Patch)
+ */
+struct t64uc_board_info {
+ u8 mac[6];
+ u32 cpuId[4];
+ u8 fwversion_major;
+ u8 fwversion_minor;
+ u8 fwversion_patch;
+} __packed;
+
+enum {
+ TEN64_CNTRL_GET_BOARD_INFO,
+ TEN64_CNTRL_10G_OFF,
+ TEN64_CNTRL_10G_ON,
+ TEN64_CNTRL_SET_NEXT_BOOTSRC
+};
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/* Ten64 Board Microcontroller Driver
+ * Copyright 2021 Traverse Technologies Australia
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <i2c.h>
+#include <hexdump.h>
+#include <dm/device_compat.h>
+#include <inttypes.h>
+#include <linux/delay.h>
+
+#include "ten64-controller.h"
+
+/* Microcontroller command set and structure
+ * These should not be used outside this file
+ */
+
+#define T64_UC_DATA_MAX_SIZE 128U
+#define T64_UC_API_MSG_HEADER_SIZE 4U
+#define T64_UC_API_HEADER_PREAMB 0xcabe
+
+enum {
+ TEN64_UC_CMD_SET_BOARD_MAC = 0x10,
+ TEN64_UC_CMD_GET_BOARD_INFO = 0x11,
+ TEN64_UC_CMD_GET_STATE = 0x20,
+ TEN64_UC_CMD_SET_RESET_BTN_HOLD_TIME = 0x21,
+ TEN64_UC_CMD_ENABLE_RESET_BUTTON = 0x22,
+ TEN64_UC_CMD_SET_NEXT_BOOTSRC = 0x23,
+ TEN64_UC_CMD_ENABLE_10G = 0x24,
+ TEN64_UC_CMD_FWUP_GET_INFO = 0xA0,
+ TEN64_UC_CMD_FWUP_INIT = 0xA1,
+ TEN64_UC_CMD_FWUP_XFER = 0xA2,
+ TEN64_UC_CMD_FWUP_CHECK = 0xA3,
+ TEN64_UC_CMD_FWUPBOOT = 0x0A
+};
+
+/** struct t64uc_message - Wire Format for microcontroller messages
+ * @preamb: Message preamble (always 0xcabe)
+ * @cmd: Command to invoke
+ * @len: Length of data
+ * @data: Command data, up to 128 bytes
+ */
+struct t64uc_message {
+ u16 preamb;
+ u8 cmd;
+ u8 len;
+ u8 data[T64_UC_DATA_MAX_SIZE];
+} __packed;
+
+enum {
+ T64_CTRL_IO_SET = 1U,
+ T64_CTRL_IO_CLEAR = 2U,
+ T64_CTRL_IO_TOGGLE = 3U,
+ T64_CTRL_IO_RESET = 4U,
+ T64_CTRL_IO_UNKNOWN = 5U
+};
+
+/** struct t64uc_board_10g_enable - Wrapper for 10G enable command
+ * @control: state to set the 10G retimer - either
+ * T64_CTRL_IO_CLEAR (0x02) for off or
+ * T64_CTRL_IO_SET (0x01) for on.
+ *
+ * This struct exists to simplify the wrapping of the
+ * command value into a microcontroller message and passing into
+ * functions.
+ */
+struct t64uc_board_10g_enable {
+ u8 control;
+} __packed;
+
+/** ten64_controller_send_recv_command() - Wrapper function to
+ * send a command to the microcontroller.
+ * @uc_chip: the DM I2C chip handle for the microcontroller
+ * @uc_cmd: the microcontroller API command code
+ * @uc_cmd_data: pointer to the data struct for this command
+ * @uc_data_len: size of command data struct
+ * @return_data: place to store response from microcontroller, NULL if not expected
+ * @expected_return_len: expected size of microcontroller command response
+ * @return_message_wait: wait this long (in us) before reading the response
+ *
+ * Invoke a microcontroller command and receive a response.
+ * This function includes communicating with the microcontroller over
+ * I2C and encoding a message in the wire format.
+ *
+ * Return: 0 if successful, error code otherwise.
+ * Returns -EBADMSG if the microcontroller response could not be validated,
+ * other error codes may be passed from dm_i2c_xfer()
+ */
+static int ten64_controller_send_recv_command(struct udevice *ucdev, u8 uc_cmd,
+ void *uc_cmd_data, u8 cmd_data_len,
+ void *return_data, u8 expected_return_len,
+ u16 return_message_wait)
+{
+ int ret;
+ struct t64uc_message send, recv;
+ struct i2c_msg command_message, return_message;
+ struct dm_i2c_chip *chip = dev_get_parent_plat(ucdev);
+
+ dev_dbg(ucdev, "%s sending cmd %02X len %d\n", __func__, uc_cmd, cmd_data_len);
+
+ send.preamb = T64_UC_API_HEADER_PREAMB;
+ send.cmd = uc_cmd;
+ send.len = cmd_data_len;
+ if (uc_cmd_data && cmd_data_len > 0)
+ memcpy(send.data, uc_cmd_data, cmd_data_len);
+
+ command_message.addr = chip->chip_addr;
+ command_message.len = T64_UC_API_MSG_HEADER_SIZE + send.len;
+ command_message.buf = (void *)&send;
+ command_message.flags = I2C_M_STOP;
+
+ ret = dm_i2c_xfer(ucdev, &command_message, 1);
+ if (!return_data)
+ return ret;
+
+ udelay(return_message_wait);
+
+ return_message.addr = chip->chip_addr;
+ return_message.len = T64_UC_API_MSG_HEADER_SIZE + expected_return_len;
+ return_message.buf = (void *)&recv;
+ return_message.flags = I2C_M_RD;
+
+ ret = dm_i2c_xfer(ucdev, &return_message, 1);
+ if (ret)
+ return ret;
+
+ if (recv.preamb != T64_UC_API_HEADER_PREAMB) {
+ dev_err(ucdev, "%s: No preamble received in microcontroller response\n",
+ __func__);
+ return -EBADMSG;
+ }
+ if (recv.cmd != uc_cmd) {
+ dev_err(ucdev, "%s: command response mismatch, got %02X expecting %02X\n",
+ __func__, recv.cmd, uc_cmd);
+ return -EBADMSG;
+ }
+ if (recv.len != expected_return_len) {
+ dev_err(ucdev, "%s: received message has unexpected length, got %d expected %d\n",
+ __func__, recv.len, expected_return_len);
+ return -EBADMSG;
+ }
+ memcpy(return_data, recv.data, expected_return_len);
+ return ret;
+}
+
+/** ten64_controller_send_command() - Send command to microcontroller without
+ * expecting a response (for example, invoking a control command)
+ * @uc_chip: the DM I2C chip handle for the microcontroller
+ * @uc_cmd: the microcontroller API command code
+ * @uc_cmd_data: pointer to the data struct for this command
+ * @uc_data_len: size of command data struct
+ */
+static int ten64_controller_send_command(struct udevice *ucdev, u8 uc_cmd,
+ void *uc_cmd_data, u8 cmd_data_len)
+{
+ return ten64_controller_send_recv_command(ucdev, uc_cmd,
+ uc_cmd_data, cmd_data_len,
+ NULL, 0, 0);
+}
+
+/** ten64_controller_get_board_info() -Get board information from microcontroller
+ * @dev: The microcontroller device handle
+ * @out: Pointer to a t64uc_board_info struct that has been allocated by the caller
+ */
+static int ten64_controller_get_board_info(struct udevice *dev, struct t64uc_board_info *out)
+{
+ int ret;
+
+ ret = ten64_controller_send_recv_command(dev, TEN64_UC_CMD_GET_BOARD_INFO,
+ NULL, 0, out,
+ sizeof(struct t64uc_board_info),
+ 10000);
+ if (ret) {
+ dev_err(dev, "%s unable to send board info command: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * ten64_controller_10g_enable_command() - Sends a 10G (Retimer) enable command
+ * to the microcontroller.
+ * @ucdev: The microcontroller udevice
+ * @value: The value flag for the 10G state
+ */
+static int ten64_controller_10g_enable_command(struct udevice *ucdev, u8 value)
+{
+ int ret;
+ struct t64uc_board_10g_enable enable_msg;
+
+ enable_msg.control = value;
+
+ ret = ten64_controller_send_command(ucdev, TEN64_UC_CMD_ENABLE_10G,
+ &enable_msg, sizeof(enable_msg));
+ if (ret) {
+ dev_err(ucdev, "ERROR sending uC 10G Enable message: %d\n", ret);
+ return -1;
+ }
+
+ return 0;
+}
+
+int ten64_controller_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
+ void *rx_msg, int rx_size)
+{
+ switch (msgid) {
+ case TEN64_CNTRL_GET_BOARD_INFO:
+ return ten64_controller_get_board_info(dev, (struct t64uc_board_info *)rx_msg);
+ case TEN64_CNTRL_10G_OFF:
+ return ten64_controller_10g_enable_command(dev, T64_CTRL_IO_CLEAR);
+ case TEN64_CNTRL_10G_ON:
+ return ten64_controller_10g_enable_command(dev, T64_CTRL_IO_SET);
+ default:
+ dev_err(dev, "%s: Unknown operation %d\n", __func__, msgid);
+ }
+ return -EINVAL;
+}
+
+static struct misc_ops ten64_ctrl_ops = {
+ .call = ten64_controller_call
+};
+
+static const struct udevice_id ten64_controller_ids[] = {
+ {.compatible = "traverse,ten64-controller"},
+ {}
+};
+
+U_BOOT_DRIVER(ten64_controller) = {
+ .name = "ten64-controller-i2c",
+ .id = UCLASS_MISC,
+ .of_match = ten64_controller_ids,
+ .ops = &ten64_ctrl_ops
+};
--- /dev/null
+if TARGET_TEN64
+
+config SYS_BOARD
+ default "ten64"
+
+config SYS_VENDOR
+ default "traverse"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ten64"
+
+endif
+
+source "board/traverse/common/Kconfig"
--- /dev/null
+TEN64 BOARD
+M: Mathew McBride <matt@traverse.com.au>
+S: Maintained
+F: arch/arm/dts/fsl-ls1088a-ten64.dts
+F: board/traverse/ten64/
+F: board/traverse/common/
+F: include/configs/ten64.h
+F: configs/ten64_tfa_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += ten64.o
+obj-y += eth_ten64.o
+
+CFLAGS_ten64.o += -DDEBUG
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ * Copyright 2019-2021 Traverse Technologies Australia
+ */
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+void reset_phy(void)
+{
+ mc_env_boot();
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* These settings only apply to VSC8514 */
+ if (phydev->phy_id == 0x70670) {
+ /* First, ensure LEDs are driven to rails (not tristate)
+ * This is in the extended page 0x0010
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x0010);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0E, 0x2000);
+ /* Restore to page 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x0000);
+
+ /* Disable blink on the left LEDs, and make the activity LEDs blink faster */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0xC03);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x3421);
+ }
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Traverse Ten64 Family board
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2021 Traverse Technologies
+ */
+#include <common.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <log.h>
+#include <malloc.h>
+#include <errno.h>
+#include <misc.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch/ppa.h>
+#include <hwconfig.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+
+#include <fsl_immap.h>
+
+#include "../common/ten64-controller.h"
+
+#define I2C_RETIMER_ADDR 0x27
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int ten64_read_board_info(struct t64uc_board_info *);
+static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *);
+static void ten64_board_retimer_ds110df410_init(void);
+
+enum {
+ TEN64_BOARD_REV_A = 0xFF,
+ TEN64_BOARD_REV_B = 0xFE,
+ TEN64_BOARD_REV_C = 0xFD
+};
+
+#define RESV_MEM_IN_BANK(b) (gd->arch.resv_ram >= base[b] && \
+ gd->arch.resv_ram < base[b] + size[b])
+
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+static u32 ten64_get_board_rev(void)
+{
+ struct ccsr_gur *dcfg = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 board_rev_in = in_le32(&dcfg->gpporcr1);
+ return board_rev_in;
+}
+
+int checkboard(void)
+{
+ enum boot_src src = get_boot_src();
+ char boardmodel[32];
+ struct t64uc_board_info boardinfo;
+ u32 board_rev = ten64_get_board_rev();
+
+ switch (board_rev) {
+ case TEN64_BOARD_REV_A:
+ snprintf(boardmodel, 32, "1064-0201A (Alpha)");
+ break;
+ case TEN64_BOARD_REV_B:
+ snprintf(boardmodel, 32, "1064-0201B (Beta)");
+ break;
+ case TEN64_BOARD_REV_C:
+ snprintf(boardmodel, 32, "1064-0201C");
+ break;
+ default:
+ snprintf(boardmodel, 32, "1064 Revision %X", (0xFF - board_rev));
+ break;
+ }
+
+ printf("Board: %s, boot from ", boardmodel);
+ if (src == BOOT_SOURCE_SD_MMC)
+ puts("SD card\n");
+ else if (src == BOOT_SOURCE_QSPI_NOR)
+ puts("QSPI\n");
+ else
+ printf("Unknown boot source %d\n", src);
+
+ puts("Controller: ");
+ if (CONFIG_IS_ENABLED(TEN64_CONTROLLER)) {
+ /* Driver not compatible with alpha/beta board MCU firmware */
+ if (board_rev <= TEN64_BOARD_REV_C) {
+ if (ten64_read_board_info(&boardinfo)) {
+ puts("ERROR: unable to communicate\n");
+ } else {
+ printf("firmware %d.%d.%d\n",
+ boardinfo.fwversion_major,
+ boardinfo.fwversion_minor,
+ boardinfo.fwversion_patch);
+ ten64_set_macaddrs_from_board_info(&boardinfo);
+ }
+ } else {
+ puts("not supported on this board revision\n");
+ }
+ } else {
+ puts("driver not enabled (no MAC addresses or other information will be read)\n");
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ init_final_memctl_regs();
+
+ if (CONFIG_IS_ENABLED(FSL_CAAM))
+ sec_init();
+
+ return 0;
+}
+
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+}
+
+void board_quiesce_devices(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_MC_ENET))
+ fsl_mc_ldpaa_exit(gd->bd);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+ if (offset < 0) {
+ printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
+ fdt_status_okay(fdt, offset);
+ else
+ fdt_status_fail(fdt, offset);
+}
+
+/* Called after SoC board_late_init in fsl-layerscape/soc.c */
+int fsl_board_late_init(void)
+{
+ ten64_board_retimer_ds110df410_init();
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int i;
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
+
+ debug("%s blob=0x%p\n", __func__, blob);
+
+ ft_cpu_setup(blob, bd);
+
+ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank++;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
+ /* fixup DT for the two GPP DDR banks */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ /* reduce size if reserved memory is within this bank */
+ if (CONFIG_IS_ENABLED(RESV_RAM) && RESV_MEM_IN_BANK(i))
+ size[i] = gd->arch.resv_ram - base[i];
+ }
+
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
+
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
+ if (CONFIG_IS_ENABLED(FSL_MC_ENET))
+ fdt_fixup_board_enet(blob);
+
+ fdt_fixup_icid(blob);
+
+ return 0;
+}
+
+#define MACADDRBITS(a, b) (u8)(((a) >> (b)) & 0xFF)
+
+/** Probe and return a udevice for the Ten64 board microcontroller.
+ * Optionally, return the I2C bus the microcontroller resides on
+ * @i2c_bus_out: return I2C bus device handle in this pointer
+ */
+static int ten64_get_micro_udevice(struct udevice **ucdev, struct udevice **i2c_bus_out)
+{
+ int ret;
+ struct udevice *i2cbus;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
+ if (ret) {
+ printf("%s: Could not get I2C UCLASS", __func__);
+ return ret;
+ }
+ if (i2c_bus_out)
+ *i2c_bus_out = i2cbus;
+
+ ret = dm_i2c_probe(i2cbus, 0x7E, DM_I2C_CHIP_RD_ADDRESS, ucdev);
+ if (ret) {
+ printf("%s: Could not get microcontroller device\n", __func__);
+ return ret;
+ }
+ return ret;
+}
+
+static int ten64_read_board_info(struct t64uc_board_info *boardinfo)
+{
+ struct udevice *ucdev;
+ int ret;
+
+ ret = ten64_get_micro_udevice(&ucdev, NULL);
+ if (ret)
+ return ret;
+
+ ret = misc_call(ucdev, TEN64_CNTRL_GET_BOARD_INFO, NULL, 0, (void *)boardinfo, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *boardinfo)
+{
+ char ethaddr[18];
+ char enetvar[10];
+ u8 intfidx, this_dpmac_num;
+ u64 macaddr = 0;
+ /* We will copy the MAC address returned from the
+ * uC (48 bits) into the u64 macaddr
+ */
+ u8 *macaddr_bytes = (u8 *)&macaddr + 2;
+
+ /** MAC addresses are allocated in order of the physical port numbers,
+ * DPMAC7->10 is "eth0" through "eth3"
+ * DPMAC3->6 is "eth4" through "eth7"
+ * DPMAC2 and 1 are "eth8" and "eth9" respectively
+ */
+ int allocation_order[10] = {7, 8, 9, 10, 3, 4, 5, 6, 2, 1};
+
+ memcpy(macaddr_bytes, boardinfo->mac, 6);
+ /* MAC address bytes from uC are in big endian,
+ * convert to CPU
+ */
+ macaddr = __be64_to_cpu(macaddr);
+
+ for (intfidx = 0; intfidx < 10; intfidx++) {
+ snprintf(ethaddr, 18, "%02X:%02X:%02X:%02X:%02X:%02X",
+ MACADDRBITS(macaddr, 40),
+ MACADDRBITS(macaddr, 32),
+ MACADDRBITS(macaddr, 24),
+ MACADDRBITS(macaddr, 16),
+ MACADDRBITS(macaddr, 8),
+ MACADDRBITS(macaddr, 0));
+
+ this_dpmac_num = allocation_order[intfidx];
+ printf("DPMAC%d: %s\n", this_dpmac_num, ethaddr);
+ snprintf(enetvar, 10,
+ (this_dpmac_num != 1) ? "eth%daddr" : "ethaddr",
+ this_dpmac_num - 1);
+ macaddr++;
+
+ if (!env_get(enetvar))
+ env_set(enetvar, ethaddr);
+ }
+}
+
+/* The retimer (DS110DF410) is one of the devices without
+ * a RESET line, but a power switch is on the board
+ * allowing it to be reset via uC command
+ */
+static int board_cycle_retimer(struct udevice **retim_dev)
+{
+ int ret;
+ u8 loop;
+ struct udevice *uc_dev;
+ struct udevice *i2cbus;
+
+ ret = ten64_get_micro_udevice(&uc_dev, &i2cbus);
+ if (ret)
+ return ret;
+
+ ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
+ if (ret == 0) {
+ puts("(retimer on, resetting...) ");
+
+ ret = misc_call(uc_dev, TEN64_CNTRL_10G_OFF, NULL, 0, NULL, 0);
+ mdelay(1000);
+ }
+
+ ret = misc_call(uc_dev, TEN64_CNTRL_10G_ON, NULL, 0, NULL, 0);
+
+ // Wait for retimer to come back
+ for (loop = 0; loop < 5; loop++) {
+ ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
+ if (ret == 0)
+ return 0;
+ mdelay(500);
+ }
+
+ return -ENOSYS;
+}
+
+/* ten64_board_retimer_ds110df410_init() - Configure the 10G retimer
+ * Adopted from the t102xqds board file
+ */
+static void ten64_board_retimer_ds110df410_init(void)
+{
+ u8 reg;
+ int ret;
+ struct udevice *retim_dev;
+ u32 board_rev = ten64_get_board_rev();
+
+ puts("Retimer: ");
+ /* Retimer power cycle not implemented on early board
+ * revisions/controller firmwares
+ */
+ if (CONFIG_IS_ENABLED(TEN64_CONTROLLER) &&
+ board_rev >= TEN64_BOARD_REV_C) {
+ ret = board_cycle_retimer(&retim_dev);
+ if (ret) {
+ puts("Retimer power on failed\n");
+ return;
+ }
+ }
+
+ /* Access to Control/Shared register */
+ reg = 0x0;
+
+ ret = dm_i2c_write(retim_dev, 0xff, ®, 1);
+ if (ret) {
+ printf("Error writing to retimer register (error %d)\n", ret);
+ return;
+ }
+
+ /* Read device revision and ID */
+ dm_i2c_read(retim_dev, 1, ®, 1);
+ if (reg == 0xF0)
+ puts("DS110DF410 found\n");
+ else
+ printf("Unknown retimer 0x%xn\n", reg);
+
+ /* Enable Broadcast */
+ reg = 0x0c;
+ dm_i2c_write(retim_dev, 0xff, ®, 1);
+
+ /* Perform a full reset (state, channel and clock)
+ * for all channels
+ * as the DS110DF410 does not have a RESET line
+ */
+ dm_i2c_read(retim_dev, 0, ®, 1);
+ reg |= 0x7;
+ dm_i2c_write(retim_dev, 0, ®, 1);
+
+ /* Set rate/subrate = 0 */
+ reg = 0x6;
+ dm_i2c_write(retim_dev, 0x2F, ®, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x0;
+ dm_i2c_write(retim_dev, 0x60, ®, 1);
+ reg = 0xb2;
+ dm_i2c_write(retim_dev, 0x61, ®, 1);
+ reg = 0x90;
+ dm_i2c_write(retim_dev, 0x62, ®, 1);
+ reg = 0xb3;
+ dm_i2c_write(retim_dev, 0x63, ®, 1);
+ reg = 0xff;
+ dm_i2c_write(retim_dev, 0x64, ®, 1);
+
+ /* Invert channel 2 (Lower SFP TX to CPU) due to the SFP being inverted */
+ reg = 0x05;
+ dm_i2c_write(retim_dev, 0xFF, ®, 1);
+ dm_i2c_read(retim_dev, 0x1F, ®, 1);
+ reg |= 0x80;
+ dm_i2c_write(retim_dev, 0x1F, ®, 1);
+
+ puts("OK\n");
+}
--- /dev/null
+if TARGET_IMX8MN_VAR_SOM
+
+config SYS_BOARD
+ default "imx8mn_var_som"
+
+config SYS_VENDOR
+ default "variscite"
+
+config SYS_CONFIG_NAME
+ default "imx8mn_var_som"
+
+config IMX_CONFIG
+ default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg"
+
+source "board/freescale/common/Kconfig"
+
+endif
--- /dev/null
+ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE
+M: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
+S: Maintained
+F: arch/arm/dts/imx8mn-var-som*
+F: board/variscite/imx8mn_var_som/
+F: configs/imx8mn_var_som_defconfig
+F: include/configs/imx8mn_var_som.h
--- /dev/null
+#
+# Copyright 2021 Collabora Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mn_var_som.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr4_timing.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400000, 0x81040010 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400034, 0x221306 },
+ { 0x3d400050, 0x210070 },
+ { 0x3d400054, 0x10008 },
+ { 0x3d400060, 0x0 },
+ { 0x3d400064, 0x9200d2 },
+ { 0x3d4000c0, 0x0 },
+ { 0x3d4000c4, 0x1000 },
+ { 0x3d4000d0, 0xc0030126 },
+ { 0x3d4000d4, 0x770000 },
+ { 0x3d4000dc, 0x8340105 },
+ { 0x3d4000e0, 0x180200 },
+ { 0x3d4000e4, 0x110000 },
+ { 0x3d4000e8, 0x2000600 },
+ { 0x3d4000ec, 0x810 },
+ { 0x3d4000f0, 0x20 },
+ { 0x3d4000f4, 0xec7 },
+ { 0x3d400100, 0x11122914 },
+ { 0x3d400104, 0x4051c },
+ { 0x3d400108, 0x608050d },
+ { 0x3d40010c, 0x400c },
+ { 0x3d400110, 0x8030409 },
+ { 0x3d400114, 0x6060403 },
+ { 0x3d40011c, 0x606 },
+ { 0x3d400120, 0x5050d08 },
+ { 0x3d400124, 0x2040a },
+ { 0x3d40012c, 0x1409010e },
+ { 0x3d400130, 0x8 },
+ { 0x3d40013c, 0x0 },
+ { 0x3d400180, 0x1000040 },
+ { 0x3d400184, 0x493e },
+ { 0x3d400190, 0x38b8207 },
+ { 0x3d400194, 0x2020303 },
+ { 0x3d400198, 0x7f04011 },
+ { 0x3d40019c, 0xb0 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0x48005a },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x1 },
+ { 0x3d4001b4, 0xb07 },
+ { 0x3d4001b8, 0x4 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x3f1f },
+ { 0x3d400204, 0x3f0909 },
+ { 0x3d400208, 0x700 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400220, 0x3f01 },
+ { 0x3d400240, 0x6000610 },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
+ { 0x3d400250, 0x317d1a07 },
+ { 0x3d400254, 0xf },
+ { 0x3d40025c, 0x2a001b76 },
+ { 0x3d400264, 0x7300b473 },
+ { 0x3d40026c, 0x30000e06 },
+ { 0x3d400300, 0x14 },
+ { 0x3d40036c, 0x10 },
+ { 0x3d400404, 0x13193 },
+ { 0x3d400408, 0x6096 },
+ { 0x3d400490, 0x1 },
+ { 0x3d400494, 0x2000c00 },
+ { 0x3d400498, 0x3c00db },
+ { 0x3d40049c, 0x100009 },
+ { 0x3d4004a0, 0x2 },
+ { 0x3d402050, 0x210070 },
+ { 0x3d402064, 0x40005e },
+ { 0x3d4020dc, 0x40105 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d4020e8, 0x2000600 },
+ { 0x3d4020ec, 0x10 },
+ { 0x3d402100, 0xb081209 },
+ { 0x3d402104, 0x2020d },
+ { 0x3d402108, 0x5050309 },
+ { 0x3d40210c, 0x400c },
+ { 0x3d402110, 0x5030206 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d40211c, 0x303 },
+ { 0x3d402120, 0x3030d04 },
+ { 0x3d402124, 0x20208 },
+ { 0x3d40212c, 0x1005010e },
+ { 0x3d402130, 0x8 },
+ { 0x3d40213c, 0x0 },
+ { 0x3d402180, 0x1000040 },
+ { 0x3d402190, 0x3858204 },
+ { 0x3d402194, 0x2020303 },
+ { 0x3d4021b4, 0x504 },
+ { 0x3d4021b8, 0x4 },
+ { 0x3d402240, 0x6000604 },
+ { 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x2fd },
+ { 0x1015f, 0x2fd },
+ { 0x1105f, 0x2fd },
+ { 0x1115f, 0x2fd },
+ { 0x11005f, 0x2fd },
+ { 0x11015f, 0x2fd },
+ { 0x11105f, 0x2fd },
+ { 0x11115f, 0x2fd },
+ { 0x55, 0x355 },
+ { 0x1055, 0x355 },
+ { 0x2055, 0x355 },
+ { 0x3055, 0x355 },
+ { 0x4055, 0x55 },
+ { 0x5055, 0x55 },
+ { 0x6055, 0x355 },
+ { 0x7055, 0x355 },
+ { 0x8055, 0x355 },
+ { 0x9055, 0x355 },
+ { 0x200c5, 0xa },
+ { 0x1200c5, 0x6 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x6 },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x1a },
+ { 0x1014d, 0x1a },
+ { 0x1104d, 0x1a },
+ { 0x1114d, 0x1a },
+ { 0x11004d, 0x1a },
+ { 0x11014d, 0x1a },
+ { 0x11104d, 0x1a },
+ { 0x11114d, 0x1a },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x2 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x258 },
+ { 0x120008, 0x10a },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x268 },
+ { 0x10043, 0x5b1 },
+ { 0x10143, 0x5b1 },
+ { 0x11043, 0x5b1 },
+ { 0x11143, 0x5b1 },
+ { 0x1200b2, 0x268 },
+ { 0x110043, 0x5b1 },
+ { 0x110143, 0x5b1 },
+ { 0x111043, 0x5b1 },
+ { 0x111143, 0x5b1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x810 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x42a },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x4 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x10 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x61 },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x1f7f },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x810 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x4b },
+ { 0x2000c, 0x96 },
+ { 0x2000d, 0x5dc },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x21 },
+ { 0x12000c, 0x42 },
+ { 0x12000d, 0x29a },
+ { 0x12000e, 0x21 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1066mts 1D */
+ .drate = 1066,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 1066, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+#include <common.h>
+#include <env.h>
+#include <asm/io.h>
+
+static void setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+}
+
+int board_init(void)
+{
+ if (CONFIG_IS_ENABLED(FEC_MXC))
+ setup_fec();
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x912000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ *
+ */
+
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ debug("Normal Boot\n");
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0)
+ puts("Failed to find clock node. Check device tree\n");
+}
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+ IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+ init_uart_clk(3);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
*
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
/* image version */
* The syntax is taken as close as possible with the kwbimage
*/
-#define __ASSEMBLY__
#include <config.h>
IMAGE_VERSION 2
return 0;
}
-#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
+#if defined(CONFIG_OF_BOARD)
void *board_fdt_blob_setup(int *err)
{
void *fdt_blob;
debug("DTB is also not passed via %p\n", fdt_blob);
+ *err = -EINVAL;
return NULL;
}
#endif
u32 ret = 0;
int i, id, macid = 0;
struct xilinx_board_description *desc;
- phys_size_t bootm_size = gd->ram_size;
+ phys_size_t bootm_size = gd->ram_top - gd->ram_base;
if (!CONFIG_IS_ENABLED(MICROBLAZE)) {
ulong scriptaddr;
the exception vector table. The user exception vector is located at
C_BASE_VECTORS + 0x8 address.
+config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
+ bool "MicroBlaze delay slot exception support"
+ default y
+ help
+ Enable this option if the MicroBlaze processor supports exceptions
+ caused by delay slot instructions (processor version >= v5.00). When
+ enabled, the hw exception handler will print a message indicating
+ whether the exception was triggered by a delay slot instruction.
+
config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
hex "Location of MicroBlaze vectors"
default 0x0
DECLARE_GLOBAL_DATA_PTR;
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
+void board_debug_uart_init(void)
+{
+ /* Add initialization sequence if UART is not configured */
+}
+#endif
+
int board_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD))
if (argc != cmdtp->maxargs)
return CMD_RET_USAGE;
+ if (!strncmp(argv[2], "node", 4)) {
+ u32 id;
+
+ if (!strncmp(argv[3], "close", 5))
+ return zynqmp_pmufw_config_close();
+
+ id = dectoul(argv[3], NULL);
+
+ printf("Enable permission for node ID %d\n", id);
+
+ return zynqmp_pmufw_node(id);
+ }
+
addr = hextoul(argv[2], NULL);
size = hextoul(argv[3], NULL);
" lock(0)/split(1)\n"
#endif
"zynqmp pmufw address size - load PMU FW configuration object\n"
+ "zynqmp pmufw node <id> - load PMU FW configuration object\n"
+ "zynqmp pmufw node close - disable config object loading\n"
+ " node: keyword, id: NODE_ID in decimal format\n"
"zynqmp rsa srcaddr srclen mod exp rsaop -\n"
" Performs RSA encryption and RSA decryption on blob of data\n"
" at srcaddr and puts it back in srcaddr using modulus and\n"
}
#endif
-int board_early_init_f(void)
+int __maybe_unused psu_uboot_init(void)
{
-#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
int ret;
ret = psu_init();
/* Delay is required for clocks to be propagated */
udelay(1000000);
-#endif
+
+ return 0;
+}
-#ifdef CONFIG_DEBUG_UART
- /* Uart debug for sure */
- debug_uart_init();
- puts("Debug uart enabled\n"); /* or printch() */
-#endif
+#if !defined(CONFIG_SPL_BUILD)
+# if defined(CONFIG_DEBUG_UART_BOARD_INIT)
+void board_debug_uart_init(void)
+{
+# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
+ psu_uboot_init();
+# endif
+}
+# endif
- return 0;
+# if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ int ret = 0;
+# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) && !defined(CONFIG_DEBUG_UART_BOARD_INIT)
+ ret = psu_uboot_init();
+# endif
+ return ret;
}
+# endif
+#endif
static int multi_boot(void)
{
}
#endif
+static void print_secure_boot(void)
+{
+ u32 status = 0;
+
+ if (zynqmp_mmio_read((ulong)&csu_base->status, &status))
+ return;
+
+ printf("Secure Boot:\t%sauthenticated, %sencrypted\n",
+ status & ZYNQMP_CSU_STATUS_AUTHENTICATED ? "" : "not ",
+ status & ZYNQMP_CSU_STATUS_ENCRYPTED ? "" : "not ");
+}
+
#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
fpga_add(fpga_xilinx, &zynqmppl);
#endif
+ /* display secure boot information */
+ print_secure_boot();
if (current_el() == 3)
printf("Multiboot:\t%d\n", multi_boot());
depends on HAVE_SYS_TEXT_BASE
default 0x0 if POSITION_INDEPENDENT
default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
- default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
- default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
- default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
+ default 0x81700000 if MACH_SUNIV
+ default 0x2a000000 if MACH_SUN9I
+ default 0x42e00000 if MACH_SUN8I_V3S
+ default 0x4a000000 if ARCH_SUNXI
hex "Text Base"
help
The address in memory that U-Boot will be running from, initially.
#include <errno.h>
#include <linux/list.h>
+#ifdef CONFIG_DM_RNG
+#include <dm.h>
+#include <rng.h>
+#endif
+
#include <splash.h>
#include <asm/io.h>
return run_command_list(localcmd, strlen(localcmd), 0);
}
+/*
+ * label_boot_kaslrseed generate kaslrseed from hw rng
+ */
+
+static void label_boot_kaslrseed(void)
+{
+#ifdef CONFIG_DM_RNG
+ ulong fdt_addr;
+ struct fdt_header *working_fdt;
+ size_t n = 0x8;
+ struct udevice *dev;
+ u64 *buf;
+ int nodeoffset;
+ int err;
+
+ /* Get the main fdt and map it */
+ fdt_addr = hextoul(env_get("fdt_addr_r"), NULL);
+ working_fdt = map_sysmem(fdt_addr, 0);
+ err = fdt_check_header(working_fdt);
+ if (err)
+ return;
+
+ /* add extra size for holding kaslr-seed */
+ /* err is new fdt size, 0 or negtive */
+ err = fdt_shrink_to_minimum(working_fdt, 512);
+ if (err <= 0)
+ return;
+
+ if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+ printf("No RNG device\n");
+ return;
+ }
+
+ nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
+ if (nodeoffset < 0) {
+ printf("Reading chosen node failed\n");
+ return;
+ }
+
+ buf = malloc(n);
+ if (!buf) {
+ printf("Out of memory\n");
+ return;
+ }
+
+ if (dm_rng_read(dev, buf, n)) {
+ printf("Reading RNG failed\n");
+ goto err;
+ }
+
+ err = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
+ if (err < 0) {
+ printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(err));
+ goto err;
+ }
+err:
+ free(buf);
+#endif
+ return;
+}
+
/**
* label_boot_fdtoverlay() - Loads fdt overlays specified in 'fdtoverlays'
*
}
}
+ if (label->kaslrseed)
+ label_boot_kaslrseed();
+
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (label->fdtoverlays)
label_boot_fdtoverlay(ctx, label);
T_ONTIMEOUT,
T_IPAPPEND,
T_BACKGROUND,
+ T_KASLRSEED,
T_INVALID
};
{"ontimeout", T_ONTIMEOUT,},
{"ipappend", T_IPAPPEND,},
{"background", T_BACKGROUND,},
+ {"kaslrseed", T_KASLRSEED,},
{NULL, T_INVALID}
};
err = parse_integer(c, &label->ipappend);
break;
+ case T_KASLRSEED:
+ label->kaslrseed = 1;
+ break;
+
case T_EOL:
break;
#include <log.h>
#include <part.h>
#include <malloc.h>
+#include <memalign.h>
enum bcb_cmd {
BCB_CMD_LOAD,
static int bcb_dev = -1;
static int bcb_part = -1;
-static struct bootloader_message bcb = { { 0 } };
+static struct bootloader_message bcb __aligned(ARCH_DMA_MINALIGN) = { { 0 } };
static int bcb_cmd_get(char *cmd)
{
struct efi_device_path *device, *image;
efi_status_t ret;
+ log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev,
+ devnr, path, buffer, buffer_size);
+
/* Forget overwritten image */
if (buffer + buffer_size >= image_addr &&
image_addr + image_size >= buffer)
/* Remember only PE-COFF and FIT images */
if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) {
-#ifdef CONFIG_FIT
- if (fit_check_format(buffer, IMAGE_SIZE_INVAL))
+ if (IS_ENABLED(CONFIG_FIT) &&
+ !fit_check_format(buffer, IMAGE_SIZE_INVAL)) {
+ /*
+ * FIT images of type EFI_OS are started via command
+ * bootm. We should not use their boot device with the
+ * bootefi command.
+ */
+ buffer = 0;
+ buffer_size = 0;
+ } else {
+ log_debug("- not remembering image\n");
return;
- /*
- * FIT images of type EFI_OS are started via command bootm.
- * We should not use their boot device with the bootefi command.
- */
- buffer = 0;
- buffer_size = 0;
-#else
- return;
-#endif
+ }
}
/* efi_set_bootdev() is typically called repeatedly, recover memory */
efi_free_pool(image_tmp);
}
bootefi_image_path = image;
+ log_debug("- recorded device %ls\n", efi_dp_str(device));
+ if (image)
+ log_debug("- and image %ls\n", efi_dp_str(image));
} else {
+ log_debug("- efi_dp_from_name() failed, err=%lx\n", ret);
efi_clear_bootdev();
}
}
/* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
switch_to_non_secure_mode();
+ /*
+ * The UEFI standard requires that the watchdog timer is set to five
+ * minutes when invoking an EFI boot option.
+ *
+ * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A
+ * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer
+ */
+ ret = efi_set_watchdog(300);
+ if (ret != EFI_SUCCESS) {
+ log_err("ERROR: Failed to set watchdog timer\n");
+ goto out;
+ }
+
/* Call our payload! */
ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data));
if (ret != EFI_SUCCESS) {
efi_restore_gd();
+out:
free(load_options);
if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD))
efi_initrd_deregister();
+ /* Control is returned to U-Boot, disable EFI watchdog */
+ efi_set_watchdog(0);
+
return ret;
}
u16 *load_options;
if (!bootefi_device_path || !bootefi_image_path) {
+ log_debug("Not loaded from disk\n");
/*
* Special case for efi payload not loaded from disk,
* such as 'bootefi hello' or for example payload
file_path = efi_dp_append(bootefi_device_path,
bootefi_image_path);
msg_path = bootefi_image_path;
+ log_debug("Loaded from disk\n");
}
log_info("Booting %pD\n", msg_path);
}
#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK)
-struct udevice *clk_lookup(const char *name)
-{
- int i = 0;
- struct udevice *dev;
-
- do {
- uclass_get_device(UCLASS_CLK, i++, &dev);
- if (!strcmp(name, dev->name))
- return dev;
- } while (dev);
-
- return NULL;
-}
-
static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
s32 freq;
struct udevice *dev;
- freq = dectoul(argv[2], NULL);
+ if (argc != 3)
+ return CMD_RET_USAGE;
- dev = clk_lookup(argv[1]);
+ freq = dectoul(argv[2], NULL);
- if (dev)
+ if (!uclass_get_device_by_name(UCLASS_CLK, argv[1], &dev))
clk = dev_get_clk_ptr(dev);
if (!clk) {
printf("clock '%s' not found.\n", argv[1]);
- return -EINVAL;
+ return CMD_RET_FAILURE;
}
freq = clk_set_rate(clk, freq);
#ifdef CONFIG_SYS_LONGHELP
static char clk_help_text[] =
"dump - Print clock frequencies\n"
- "setfreq [clk] [freq] - Set clock frequency";
+ "clk setfreq [clk] [freq] - Set clock frequency";
#endif
U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
#ifdef CONFIG_DFU_OVER_USB
char *usb_controller = argv[1];
#endif
-#if defined(CONFIG_DFU_OVER_USB) || defined(CONFIG_DFU_OVER_TFTP)
char *interface = NULL;
char *devstring = NULL;
#if defined(CONFIG_DFU_TIMEOUT) || defined(CONFIG_DFU_OVER_TFTP)
if (argc == 5 || argc == 3)
value = simple_strtoul(argv[argc - 1], NULL, 0);
#endif
-#endif
int ret = 0;
#ifdef CONFIG_DFU_OVER_TFTP
if (!strcmp(argv[1], "tftp"))
return update_tftp(value, interface, devstring);
#endif
-#ifdef CONFIG_DFU_OVER_USB
ret = dfu_init_env_entities(interface, devstring);
if (ret)
goto done;
goto done;
}
+#ifdef CONFIG_DFU_OVER_USB
int controller_index = simple_strtoul(usb_controller, NULL, 0);
bool retry = false;
do {
}
} while (retry);
+#endif
done:
dfu_free_entities();
-#endif
return ret;
}
#ifdef CONFIG_DFU_TIMEOUT
" [<timeout>] - specify inactivity timeout in seconds\n"
#endif
- " [list] - list available alt settings\n"
#endif
+ " [list] - list available alt settings\n"
#ifdef CONFIG_DFU_OVER_TFTP
#ifdef CONFIG_DFU_OVER_USB
"dfu "
guid = efi_guid_capsule_report;
if (argc == 1) {
size = sizeof(var_name16);
- ret = efi_get_variable_int(L"CapsuleLast", &guid, NULL,
+ ret = efi_get_variable_int(u"CapsuleLast", &guid, NULL,
&size, var_name16, NULL);
if (ret != EFI_SUCCESS) {
return CMD_RET_FAILURE;
}
- if (memcmp(var_name16, L"Boot", 8))
+ if (memcmp(var_name16, u"Boot", 8))
continue;
for (id = 0, i = 0; i < 4; i++) {
efi_status_t ret;
size = 0;
- ret = EFI_CALL(efi_get_variable(L"BootOrder", &efi_global_variable_guid,
+ ret = EFI_CALL(efi_get_variable(u"BootOrder", &efi_global_variable_guid,
NULL, &size, NULL));
if (ret != EFI_BUFFER_TOO_SMALL) {
if (ret == EFI_NOT_FOUND) {
printf("ERROR: Out of memory\n");
return CMD_RET_FAILURE;
}
- ret = EFI_CALL(efi_get_variable(L"BootOrder", &efi_global_variable_guid,
+ ret = EFI_CALL(efi_get_variable(u"BootOrder", &efi_global_variable_guid,
NULL, &size, bootorder));
if (ret != EFI_SUCCESS) {
ret = CMD_RET_FAILURE;
guid = efi_global_variable_guid;
size = sizeof(u16);
- ret = efi_set_variable_int(L"BootNext", &guid,
- EFI_VARIABLE_NON_VOLATILE |
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
- size, &bootnext, false);
+ ret = efi_set_variable_int(u"BootNext", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, &bootnext, false);
if (ret != EFI_SUCCESS) {
printf("Cannot set BootNext\n");
r = CMD_RET_FAILURE;
}
guid = efi_global_variable_guid;
- ret = efi_set_variable_int(L"BootOrder", &guid,
- EFI_VARIABLE_NON_VOLATILE |
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
- size, bootorder, true);
+ ret = efi_set_variable_int(u"BootOrder", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, bootorder, true);
if (ret != EFI_SUCCESS) {
printf("Cannot set BootOrder\n");
r = CMD_RET_FAILURE;
#include <command.h>
#include <console.h>
#include <fuse.h>
+#include <mapmem.h>
#include <linux/errno.h>
static int strtou32(const char *str, unsigned int base, u32 *result)
{
const char *op = argc >= 2 ? argv[1] : NULL;
int confirmed = argc >= 3 && !strcmp(argv[2], "-y");
- u32 bank, word, cnt, val;
+ u32 bank, word, cnt, val, cmp;
+ ulong addr;
+ void *buf, *start;
int ret, i;
argc -= 2 + confirmed;
printf(" %.8x", val);
}
putc('\n');
+ } else if (!strcmp(op, "readm")) {
+ if (argc == 3)
+ cnt = 1;
+ else if (argc != 4 || strtou32(argv[3], 0, &cnt))
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ start = map_sysmem(addr, 4);
+ buf = start;
+
+ printf("Reading bank %u len %u to 0x%lx\n", bank, cnt, addr);
+ for (i = 0; i < cnt; i++, word++) {
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ goto err;
+
+ *((u32 *)buf) = val;
+ buf += 4;
+ }
+
+ unmap_sysmem(start);
+ } else if (!strcmp(op, "cmp")) {
+ if (argc != 3 || strtou32(argv[2], 0, &cmp))
+ return CMD_RET_USAGE;
+
+ printf("Comparing bank %u:\n", bank);
+ printf("\nWord 0x%.8x:", word);
+ printf("\nValue 0x%.8x:", cmp);
+
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ goto err;
+
+ printf("0x%.8x\n", val);
+ if (val != cmp) {
+ printf("failed\n");
+ return CMD_RET_FAILURE;
+ }
+ printf("passed\n");
} else if (!strcmp(op, "sense")) {
if (argc == 2)
cnt = 1;
"Fuse sub-system",
"read <bank> <word> [<cnt>] - read 1 or 'cnt' fuse words,\n"
" starting at 'word'\n"
+ "fuse cmp <bank> <word> <hexval> - compare 'hexval' to fuse\n"
+ " at 'word'\n"
+ "fuse readm <bank> <word> <addr> [<cnt>] - read 1 or 'cnt' fuse words,\n"
+ " starting at 'word' into memory at 'addr'\n"
"fuse sense <bank> <word> [<cnt>] - sense 1 or 'cnt' fuse words,\n"
" starting at 'word'\n"
"fuse prog [-y] <bank> <word> <hexval> [<hexval>...] - program 1 or\n"
struct mmc_hwpart_conf *pconf,
char *argv)
{
- int ret;
+ int i, ret;
pconf->user.enh_size = 0;
ret = mmc_send_ext_csd(mmc, ext_csd);
if (ret)
return;
- /* This value is in 512B block units */
+ /* The enh_size value is in 512B block units */
pconf->user.enh_size =
((ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16) +
(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) +
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
pconf->user.enh_size -= pconf->user.enh_start;
+ for (i = 0; i < ARRAY_SIZE(mmc->capacity_gp); i++) {
+ /*
+ * If the eMMC already has GP partitions set,
+ * subtract their size from the maximum USER
+ * partition size.
+ *
+ * Else, if the command was used to configure new
+ * GP partitions, subtract their size from maximum
+ * USER partition size.
+ */
+ if (mmc->capacity_gp[i]) {
+ /* The capacity_gp is in 1B units */
+ pconf->user.enh_size -= mmc->capacity_gp[i] >> 9;
+ } else if (pconf->gp_part[i].size) {
+ /* The gp_part[].size is in 512B units */
+ pconf->user.enh_size -= pconf->gp_part[i].size;
+ }
+ }
} else {
pconf->user.enh_size = dectoul(argv, NULL);
}
#include <mapmem.h>
#include <memalign.h>
#include <part.h>
+#include <fdt_support.h>
struct persistent_ram_buffer {
u32 sig;
{
char node[32];
int nodeoffset; /* node offset from libfdt */
+ u32 addr_cells;
+ u32 size_cells;
nodeoffset = fdt_path_offset(blob, "/");
if (nodeoffset < 0) {
return;
}
- nodeoffset = fdt_add_subnode(blob, nodeoffset, "reserved-memory");
+ nodeoffset = fdt_find_or_add_subnode(blob, nodeoffset, "reserved-memory");
if (nodeoffset < 0) {
log_err("Add 'reserved-memory' node failed: %s\n",
fdt_strerror(nodeoffset));
return;
}
- fdt_setprop_u32(blob, nodeoffset, "#address-cells", 2);
- fdt_setprop_u32(blob, nodeoffset, "#size-cells", 2);
+
+ addr_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#address-cells", 2);
+ size_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#size-cells", 2);
+ fdt_setprop_u32(blob, nodeoffset, "#address-cells", addr_cells);
+ fdt_setprop_u32(blob, nodeoffset, "#size-cells", size_cells);
+
fdt_setprop_empty(blob, nodeoffset, "ranges");
sprintf(node, "ramoops@%llx", (unsigned long long)pstore_addr);
log_err("Add '%s' node failed: %s\n", node, fdt_strerror(nodeoffset));
return;
}
+
fdt_setprop_string(blob, nodeoffset, "compatible", "ramoops");
- fdt_setprop_u64(blob, nodeoffset, "reg", pstore_addr);
- fdt_appendprop_u64(blob, nodeoffset, "reg", pstore_length);
+
+ if (addr_cells == 1) {
+ fdt_setprop_u32(blob, nodeoffset, "reg", pstore_addr);
+ } else if (addr_cells == 2) {
+ fdt_setprop_u64(blob, nodeoffset, "reg", pstore_addr);
+ } else {
+ log_err("Unsupported #address-cells: %u\n", addr_cells);
+ goto clean_ramoops;
+ }
+
+ if (size_cells == 1) {
+ // Let's consider that the pstore_length fits in a 32 bits value
+ fdt_appendprop_u32(blob, nodeoffset, "reg", pstore_length);
+ } else if (size_cells == 2) {
+ fdt_appendprop_u64(blob, nodeoffset, "reg", pstore_length);
+ } else {
+ log_err("Unsupported #size-cells: %u\n", addr_cells);
+ goto clean_ramoops;
+ }
+
fdt_setprop_u32(blob, nodeoffset, "record-size", pstore_record_size);
fdt_setprop_u32(blob, nodeoffset, "console-size", pstore_console_size);
fdt_setprop_u32(blob, nodeoffset, "ftrace-size", pstore_ftrace_size);
fdt_setprop_u32(blob, nodeoffset, "pmsg-size", pstore_pmsg_size);
fdt_setprop_u32(blob, nodeoffset, "ecc-size", pstore_ecc_size);
+
+clean_ramoops:
+ fdt_del_node_and_alias(blob, node);
}
U_BOOT_CMD(pstore, 10, 0, do_pstore,
memset(a, 0xa5, 512);
- printf("We have smashed our stack as this should not exceed 128: sizeof(a) = %ld\n", strlen(a));
+ printf("We have smashed our stack as this should not exceed 128: sizeof(a) = %zd\n",
+ strlen(a));
return 0;
}
int bloblist_init(void)
{
+ bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
int ret = -ENOENT;
ulong addr, size;
bool expected;
/**
- * Wed expect to find an existing bloblist in the first phase of U-Boot
- * that runs
+ * We don't expect to find an existing bloblist in the first phase of
+ * U-Boot that runs. Also we have no way to receive the address of an
+ * allocated bloblist from a previous stage, so it must be at a fixed
+ * address.
*/
- expected = !u_boot_first_phase();
+ expected = fixed && !u_boot_first_phase();
if (spl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
expected = false;
- addr = bloblist_addr();
+ if (fixed)
+ addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
+ CONFIG_BLOBLIST_ADDR);
size = CONFIG_BLOBLIST_SIZE;
if (expected) {
ret = bloblist_check(addr, size);
if (!ptr)
return log_msg_ret("alloc", -ENOMEM);
addr = map_to_sysmem(ptr);
+ } else if (!fixed) {
+ return log_msg_ret("!fixed", ret);
}
log_debug("Creating new bloblist size %lx at %lx\n", size,
addr);
{
struct mtd_device *dev;
int i, idx;
- int noff;
+ int noff, parts;
bool inited = false;
for (i = 0; i < node_info_size; i++) {
dev = device_find(node_info[i].type, idx++);
if (dev) {
- if (fdt_node_set_part_info(blob, noff, dev))
+ parts = fdt_subnode_offset(blob, noff,
+ "partitions");
+ if (parts < 0)
+ parts = noff;
+
+ if (fdt_node_set_part_info(blob, parts, dev))
return; /* return on error */
}
}
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
new_ptr = addr + bytes - gd->malloc_base;
- log_debug("size=%zx, ptr=%lx, limit=%lx: ", bytes, new_ptr,
+ log_debug("size=%lx, ptr=%lx, limit=%lx: ", (ulong)bytes, new_ptr,
gd->malloc_limit);
if (new_ptr > gd->malloc_limit) {
log_err("alloc space exhausted\n");
This adds a small amount to SPL code size, perhaps 100 bytes.
+config SPL_BINMAN_SYMBOLS
+ bool "Declare binman symbols in SPL"
+ depends on SPL_FRAMEWORK && BINMAN
+ default y
+ help
+ This enables use of symbols in SPL which refer to U-Boot, enabling SPL
+ to obtain the location of U-Boot simply by calling spl_get_image_pos()
+ and spl_get_image_size().
+
+ For this to work, you must have a U-Boot image in the binman image, so
+ binman can update SPL with the location of it.
+
menu "PowerPC and LayerScape SPL Boot options"
config SPL_NAND_BOOT
Specifies the maximum length of the U-Boot TPL image.
If this value is zero, it is ignored.
+config TPL_BINMAN_SYMBOLS
+ bool "Declare binman symbols in SPL"
+ depends on SPL_FRAMEWORK && BINMAN
+ default y
+ help
+ This enables use of symbols in TPL which refer to U-Boot, enabling SPL
+ to obtain the location of U-Boot simply by calling spl_get_image_pos()
+ and spl_get_image_size().
+
+ For this to work, you must have a U-Boot image in the binman image, so
+ binman can update SPL with the location of it.
+
config TPL_FRAMEWORK
bool "Support TPL based upon the common SPL framework"
default y if SPL_FRAMEWORK
u32 *boot_params_ptr = NULL;
+#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS)
/* See spl.h for information about this */
binman_sym_declare(ulong, u_boot_any, image_pos);
binman_sym_declare(ulong, u_boot_any, size);
+#endif
#ifdef CONFIG_TPL
-binman_sym_declare(ulong, spl, image_pos);
-binman_sym_declare(ulong, spl, size);
+binman_sym_declare(ulong, u_boot_spl, image_pos);
+binman_sym_declare(ulong, u_boot_spl, size);
#endif
/* Define board data structure */
#endif
}
+#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS)
ulong spl_get_image_pos(void)
{
return spl_phase() == PHASE_TPL ?
- binman_sym(ulong, spl, image_pos) :
+ binman_sym(ulong, u_boot_spl, image_pos) :
binman_sym(ulong, u_boot_any, image_pos);
}
ulong spl_get_image_size(void)
{
return spl_phase() == PHASE_TPL ?
- binman_sym(ulong, spl, size) :
+ binman_sym(ulong, u_boot_spl, size) :
binman_sym(ulong, u_boot_any, size);
}
+#endif /* BINMAN_SYMBOLS */
ulong spl_get_image_text_base(void)
{
int res, err, buf_offset;
struct ymodem_fit_info *info = load->priv;
char *buf = info->buf;
+ ulong copy_size = size;
while (info->image_read < offset) {
res = xyzModem_stream_read(buf, BUF_SIZE, &err);
buf_offset = (info->image_read % BUF_SIZE);
else
buf_offset = BUF_SIZE;
+
+ if (res > copy_size) {
+ memcpy(addr, &buf[buf_offset - res], copy_size);
+ goto done;
+ }
memcpy(addr, &buf[buf_offset - res], res);
addr = addr + res;
+ copy_size -= res;
}
while (info->image_read < offset + size) {
if (res <= 0)
break;
- memcpy(addr, buf, res);
info->image_read += res;
+ if (res > copy_size) {
+ memcpy(addr, buf, copy_size);
+ goto done;
+ }
+ memcpy(addr, buf, res);
addr += res;
+ copy_size -= res;
}
+done:
return size;
}
#include <stdio_dev.h>
#include <watchdog.h>
#include <asm/byteorder.h>
+#ifdef CONFIG_SANDBOX
+#include <asm/state.h>
+#endif
#include <usb.h>
extern int __maybe_unused net_busy_flag;
/* The period of time between two calls of usb_kbd_testc(). */
-static unsigned long __maybe_unused kbd_testc_tms;
+static unsigned long kbd_testc_tms;
/* Puts character in the queue and sets up the in and out pointer. */
static void usb_kbd_put_queue(struct usb_kbd_pdata *data, u8 c)
struct usb_device *usb_kbd_dev;
struct usb_kbd_pdata *data;
+ /*
+ * Polling the keyboard for an event can take dozens of milliseconds.
+ * Add a delay between polls to avoid blocking activity which polls
+ * rapidly, like the UEFI console timer.
+ */
+ unsigned long poll_delay = CONFIG_SYS_HZ / 50;
+
#ifdef CONFIG_CMD_NET
/*
* If net_busy_flag is 1, NET transfer is running,
* then we check key-pressed every second (first check may be
* less than 1 second) to improve TFTP booting performance.
*/
- if (net_busy_flag && (get_timer(kbd_testc_tms) < CONFIG_SYS_HZ))
- return 0;
- kbd_testc_tms = get_timer(0);
+ if (net_busy_flag)
+ poll_delay = CONFIG_SYS_HZ;
+#endif
+
+#ifdef CONFIG_SANDBOX
+ /*
+ * Skip delaying polls if a test requests it.
+ */
+ if (state_get_skip_delays())
+ poll_delay = 0;
#endif
+
dev = stdio_get_by_name(sdev->name);
usb_kbd_dev = (struct usb_device *)dev->priv;
data = usb_kbd_dev->privptr;
- usb_kbd_poll_for_event(usb_kbd_dev);
+ if (get_timer(kbd_testc_tms) >= poll_delay) {
+ usb_kbd_poll_for_event(usb_kbd_dev);
+ kbd_testc_tms = get_timer(0);
+ }
return !(data->usb_in_pointer == data->usb_out_pointer);
}
CONFIG_MAC_PARTITION=y
CONFIG_ENV_ADDR=0xFF804000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0xA0
+CONFIG_SYS_ATA_REG_OFFSET=0xA0
+CONFIG_SYS_ATA_ALT_OFFSET=0xC0
+CONFIG_SYS_ATA_IDE0_OFFSET=0
+CONFIG_ATAPI=y
+CONFIG_IDE_RESET=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x280
CONFIG_ENV_ADDR=0xFE080000
CONFIG_DM=y
CONFIG_FSL_SATA=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFE001001
CONFIG_SYS_OR0_PRELIM=0xFF800193
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFA00C21
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x180000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FW_ADDR=0x200000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_U_QE=y
+CONFIG_SYS_QE_FW_ADDR=0x124000
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_MALLOC_F_LEN=0x1200
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
# CONFIG_NET is not set
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DM_I2C=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_SDHCI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=57
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_BCH=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_TARGET_APALIS_IMX8=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis"
CONFIG_TARGET_APALIS_IMX8X=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x89000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_APPLE=y
CONFIG_DEFAULT_DEVICE_TREE="t8103-j274"
CONFIG_DEBUG_UART_BASE=0x235200000
-CONFIG_DEBUG_UART_CLOCK=240000
-CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x880000000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_NET is not set
+CONFIG_APPLE_SPI_KEYB=y
# CONFIG_MMC is not set
+CONFIG_NVME_APPLE=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING="bpi-m5"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" beelink"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
CONFIG_TARGET_COLIBRI_IMX8X=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_LOG=y
CONFIG_TFTP_TSIZE=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
+CONFIG_FXL6408_GPIO=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
-# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_MVEBU=y
CONFIG_SCSI=y
+CONFIG_SCSI_AHCI_PLAT=y
+CONFIG_SYS_SCSI_MAX_SCSI_ID=2
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_IDENT_STRING=" ##v01.06"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_SYS_KWD_CONFIG="board/Seagate/dockstar/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; ubifsload 0x1100000 ${initrd}; bootm 0x800000 0x1100000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000
+CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80080000
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_ENV_ADDR=0x3D0000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFF84000
CONFIG_NETCONSOLE=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_IDE_MAXDEVICE=1
+CONFIG_SYS_ATA_BASE_ADDR=0xf1080000
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x4000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
# CONFIG_PCI_PNP is not set
# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
+CONFIG_USB_GADGET_VENDOR_NUM=0x3016
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_AXI=y
CONFIG_IHS_AXI=y
CONFIG_CLK=y
-CONFIG_ICS8N3QV01=y
+CONFIG_CLK_ICS8N3QV01=y
CONFIG_CPU=y
CONFIG_CPU_MPC83XX=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_IDENT_STRING=" ##v01.07"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_MMC is not set
CONFIG_CALXEDA_XGMAC=y
CONFIG_SCSI=y
+CONFIG_SCSI_AHCI_PLAT=y
+CONFIG_SYS_SCSI_MAX_SCSI_ID=5
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_HIHOPE_RZG2=y
# CONFIG_SPL is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
CONFIG_IDENT_STRING="hikey"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80000
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SYS_PROMPT="iconnect => "
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="iConnect> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=spi3.0"
-CONFIG_MTDPARTS_DEFAULT="spi3.0:64k(SPL),448k(uboot),128k(envs),384k(unused1),4096k(kernel),8192k(swupdate),-(unused2)"
CONFIG_DOS_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_MXS=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=1
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MX28=y
+CONFIG_SYS_TEXT_BASE=0x40002000
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
+CONFIG_SPL_TEXT_BASE=0x1000
+CONFIG_TARGET_XEA=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x90000
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_SYS_LOAD_ADDR=0x42000000
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200n8"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run prebootcmd"
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
+CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent interrupts"
+CONFIG_SPL_OF_PLATDATA=y
+# CONFIG_SPL_OF_PLATDATA_PARENT is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_DEVRES=y
+# CONFIG_SPL_BLK is not set
+CONFIG_MXS_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_MXS=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=3
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=1
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MXS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXS_SPI=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_FS_FAT=y
+# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate-optee"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_MXC_GPIO=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_DM_PMIC=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som-symphony"
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_VAR_SOM=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="> "
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x40480000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0xff0000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-venice"
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_VENICE=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0xff8000
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_LTO=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="gsc wd-disable"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx8mn-venice imx8mn-venice-gw7902"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_KSZ9477=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_PMIC_MP5416=y
+CONFIG_SPL_DM_PMIC_MP5416=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_HEXDUMP=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_RSB3720A1_4G=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_IMX_CONFIG="board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_S35392A=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_SDP_LOADADDR=0x40480000
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SHA512_ALGO=y
+CONFIG_SHA512=y
+CONFIG_SHA384=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_SPL_DM_I2C=y
+CONFIG_SPL_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_I2C=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SYSRESET=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_RSB3720A1_6G=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_IMX_CONFIG="board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_S35392A=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_SDP_LOADADDR=0x40480000
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SHA512_ALGO=y
+CONFIG_SHA512=y
+CONFIG_SHA384=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_SPL_DM_I2C=y
+CONFIG_SPL_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_I2C=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SYSRESET=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80480000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMXRT1020=y
CONFIG_CLK_IMXRT1020=y
# CONFIG_SPL_DM_GPIO is not set
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMXRT1050=y
CONFIG_CLK_IMXRT1050=y
# CONFIG_SPL_DM_GPIO is not set
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
CONFIG_K3_AVS0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
+CONFIG_ENV_OFFSET_REDUND=0x7C0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57344k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk"
+CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
CONFIG_ESM_PMIC=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
CONFIG_K3_AVS0=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ENV_OFFSET_REDUND=0x6A0000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HS512T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PHY_CADENCE_TORRENT=y
+CONFIG_PHY_J721E_WIZ=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_UFS=y
+CONFIG_CADENCE_UFS=y
+CONFIG_TI_J721E_UFS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J721S2=y
+CONFIG_K3_EARLY_CONS=y
+CONFIG_TARGET_J721S2_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board"
+CONFIG_SPL_TEXT_BASE=0x41c00000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x80000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_USE_BOOTCOMMAND=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HS512T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_PANIC_HANG=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" jethubj100"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" jethubj80"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim2"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_KONTRON_MX8MM=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x300000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-kontron-pitx-imx8m"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_KONTRON_PITX_IMX8M=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_MMC=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RNG=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST=""
+CONFIG_OF_LIST="fsl-ls1028a-kontron-sl28 fsl-ls1028a-kontron-sl28-var1 fsl-ls1028a-kontron-sl28-var2 fsl-ls1028a-kontron-sl28-var3 fsl-ls1028a-kontron-sl28-var4"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
+CONFIG_SL28CPLD_GPIO=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
+CONFIG_SL28CPLD=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_RTC_RV8803=y
CONFIG_USB_DWC3_LAYERSCAPE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_WDT=y
+CONFIG_WDT_SL28CPLD=y
+CONFIG_WDT_SP805=y
CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_SET_TIME=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-ac"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-cc"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-cc-v2"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-s905d-pc"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-s912-pc"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
+CONFIG_SPL=y
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
+# CONFIG_VIDEO_SUNXI is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_MII=y
CONFIG_SJA1105=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MII=y
CONFIG_SJA1105=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x940000
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x60900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x40900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_I2C=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x80300000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x20300000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x20300000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x80300000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_AHCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_CORTINA_FW_ADDR=0x580980000
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x80300000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_CORTINA_FW_ADDR=0x580980000
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_E1000=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x580500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xBE3E0000
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVNETA=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_AARDVARK=y
CONFIG_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" nanopi-k2"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_BLK=y
CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_DM_SEQ_ALIAS is not set
# CONFIG_BLOCK_CACHE is not set
CONFIG_DM_I2C=y
+CONFIG_DM_KEYBOARD=y
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_USB_OMAP3=y
CONFIG_CFB_CONSOLE=y
CONFIG_CFB_CONSOLE_ANSI=y
-# CONFIG_VGA_AS_SINGLE_DEVICE is not set
CONFIG_SPLASH_SCREEN=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=31000
CONFIG_WDT=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
+CONFIG_USB_GADGET_VENDOR_NUM=0x3016
CONFIG_CMD_E1000=y
CONFIG_NET_OCTEONTX2=y
CONFIG_OCTEONTX_SMI=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SRIOV=y
CONFIG_CMD_E1000=y
CONFIG_NET_OCTEONTX=y
CONFIG_OCTEONTX_SMI=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SRIOV=y
CONFIG_CMD_E1000=y
CONFIG_NET_OCTEONTX=y
CONFIG_OCTEONTX_SMI=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SRIOV=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-c2"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-c4/hc4"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_IDENT_STRING=" odroid-hc4"
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-n2/n2-plus"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
-CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
-CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=147
CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
-CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=1
-CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=62
CONFIG_USB_OMAP3=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_SCSI=y
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=80
-CONFIG_HAS_OMAP_EHCI_PHY3_RESET_GPIO=y
-CONFIG_OMAP_EHCI_PHY3_RESET_GPIO=79
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0x100
+CONFIG_SYS_ATA_REG_OFFSET=0x100
+CONFIG_SYS_ATA_ALT_OFFSET=0x100
+CONFIG_SYS_ATA_IDE0_OFFSET=0x2000
+CONFIG_SYS_ATA_IDE1_OFFSET=0x4000
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p200"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p201"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p212"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_RTL8169=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
+CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
+CONFIG_PG_WCOM_UBOOT_BOOTPACKAGE=y
+CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE=0x60240000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x4000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
+CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DDR_CLK_FREQ=50000000
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_QE_FW_ADDR=0x60020000
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_TARGET_PG_WCOM_EXPU1=y
+CONFIG_SYS_TEXT_BASE=0x60240000
+CONFIG_SYS_MALLOC_LEN=0x1004000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_KM_DEF_NETDEV="eth2"
+CONFIG_KM_COMMON_ETH_INIT=y
+CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
+CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
+CONFIG_PG_WCOM_UBOOT_UPDATE=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_CRAMFS=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_ADDR=0x60220000
+CONFIG_ENV_ADDR_REDUND=0x60200000
+CONFIG_VERSION_VARIABLE=y
+CONFIG_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DDR_CLK_FREQ=50000000
+CONFIG_SYS_FSL_DDR3=y
+CONFIG_SYS_I2C_LEGACY=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FW_ADDR=0x60020000
+CONFIG_SCSI_AHCI_PLAT=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
+CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
+CONFIG_PG_WCOM_UBOOT_BOOTPACKAGE=y
+CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE=0x60240000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x4000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
+CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DDR_CLK_FREQ=50000000
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_QE_FW_ADDR=0x60020000
+CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_TARGET_PG_WCOM_SELI8=y
+CONFIG_SYS_TEXT_BASE=0x60240000
+CONFIG_SYS_MALLOC_LEN=0x1004000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_KM_DEF_NETDEV="eth2"
+CONFIG_KM_COMMON_ETH_INIT=y
+CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
+CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y
+CONFIG_PG_WCOM_UBOOT_UPDATE=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_CRAMFS=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_ADDR=0x60220000
+CONFIG_ENV_ADDR_REDUND=0x60200000
+CONFIG_VERSION_VARIABLE=y
+CONFIG_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DDR_CLK_FREQ=50000000
+CONFIG_SYS_FSL_DDR3=y
+CONFIG_SYS_I2C_LEGACY=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FW_ADDR=0x60020000
+CONFIG_SCSI_AHCI_PLAT=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_e02/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_POGO_E02=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_OFFSET=0xC0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02"
CONFIG_IDENT_STRING="\nPogo E02"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MVEBU_MMC=y
CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
CONFIG_CPU=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_SPL_DM_RTC=y
CONFIG_SPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
CONFIG_CPU=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_SPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_SCSI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_SCSI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xA0040000
CONFIG_DM=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_IDE_MAXDEVICE=1
+CONFIG_SYS_ATA_BASE_ADDR=0xb4000000
+CONFIG_SYS_ATA_STRIDE=2
+CONFIG_SYS_ATA_DATA_OFFSET=0x1000
+CONFIG_SYS_ATA_REG_OFFSET=0x1000
+CONFIG_SYS_ATA_ALT_OFFSET=0x800
+CONFIG_IDE_RESET=y
CONFIG_CLK=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EAGLE=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_CONDOR=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EBISU=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_DRAAK=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_CLK_FREQ=16666666
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" radxa-zero"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_RCAR_GEN3=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_TARGET_BEACON_RZG2M=y
# CONFIG_SPL is not set
CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
-CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" s400"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_DEVRES=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_RTC=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_DM_ETH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SANDBOX=y
CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
+CONFIG_SCSI=y
+CONFIG_SCSI_AHCI_PLAT=y
+CONFIG_SYS_SCSI_MAX_SCSI_ID=8
+CONFIG_SYS_SCSI_MAX_LUN=4
CONFIG_SANDBOX_SERIAL=y
CONFIG_SMEM=y
CONFIG_SANDBOX_SMEM=y
CONFIG_DEBUG_DEVRES=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
CONFIG_CLK=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SANDBOX=y
# CONFIG_SPL_SIMPLE_BUS is not set
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CPU=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
# CONFIG_SPL_SIMPLE_BUS is not set
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
+CONFIG_SYS_IDE_MAXBUS=1
+CONFIG_SYS_ATA_BASE_ADDR=0x100
+CONFIG_SYS_ATA_STRIDE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=1
+CONFIG_SYS_ATA_ALT_OFFSET=2
+CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CPU=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
CONFIG_IDENT_STRING=" sei510"
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_IDENT_STRING=" sei610"
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_MVEBU_MMC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x54
CONFIG_SPI_FLASH_ISSI=y
CONFIG_E1000=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_SIFIVE=y
CONFIG_DM_RESET=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SILINUX_EK874=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y
CONFIG_IDENT_STRING="socfpga_n5x"
CONFIG_SPL_FS_FAT=y
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_IDENT_STRING="socfpga_n5x"
CONFIG_SPL_FS_FAT=y
# CONFIG_PSCI_RESET is not set
+CONFIG_REMAKE_ELF=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200"
CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y
CONFIG_IDENT_STRING="socfpga_n5x"
CONFIG_SPL_FS_FAT=y
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
# CONFIG_PSCI_RESET is not set
CONFIG_OPTIMIZE_INLINING=y
CONFIG_SPL_OPTIMIZE_INLINING=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_MCDE_SIMPLE=y
# CONFIG_EFI_LOADER is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_LIBFDT=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_SNI_NETSEC=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
CONFIG_SCSI=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_TEN64=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x80000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x80000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-ten64"
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_TEN64_CONTROLLER=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_MP=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_LOGLEVEL=7
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_ID_EEPROM is not set
+CONFIG_PCI_INIT_R=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TPM=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:8m(reserved),32m(recovery),108m(ubia),108m(ubib);nor1:1m(bl2),2m(bl3),2m(mcfirmware),512k(ubootenv),256k(dpl),256k(dpc),256k(devicetree)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_PCA953X=y
+CONFIG_MPC8XXX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RX8025=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_TPM_ATMEL_TWI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_TPM=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SATA_MV=y
+CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_FPGA_ALTERA=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x500000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
# CONFIG_ACPIGEN is not set
+CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
CONFIG_SANDBOX_GPIO=y
# CONFIG_VIRTIO_SANDBOX is not set
# CONFIG_GENERATE_ACPI_TABLE is not set
# CONFIG_EFI_LOADER is not set
+CONFIG_TOOLS_MKEFICAPSULE=y
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_ENV_SIZE=0x2a00000
CONFIG_DEFAULT_DEVICE_TREE="total_compute"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_AARDVARK=y
CONFIG_PHY=y
CONFIG_SYS_MEMTEST_START=0x00800000
CONFIG_SYS_MEMTEST_END=0x00ffffff
CONFIG_TARGET_TURRIS_OMNIA=y
+CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xF0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_MII=y
-CONFIG_NVME=y
+CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" u200"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-verdin"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_VERDIN_IMX8MP=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x43500000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdtfile imx8mp-verdin-${variant}-${fdt_board}.dtb"
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="Verdin iMX8MP # "
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_I2C is not set
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DEFAULT_DEVICE_TREE="juno-r2"
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_BOOTDELAY=1
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" wetek-core2"
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_COUNTER_FREQUENCY=100000000
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DEFINE_TCM_OCM_MMAP=y
CONFIG_COUNTER_FREQUENCY=100000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_FRU=y
CONFIG_CMD_ZYNQ_AES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_CMD_MTDPARTS_SPREAD=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_UBI=y
+CONFIG_OF_BOARD=y
CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_SPL=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_MP is not set
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_MP is not set
CONFIG_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_MP is not set
CONFIG_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_MP is not set
CONFIG_FIT=y
# CONFIG_CMD_ZYNQMP is not set
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_CMD_FRU=y
CONFIG_ZYNQMP_USB=y
-CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run scsi_init;usb start"
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_FPGA=y
CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_BOARD=y
CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_BUTTON=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_ZYNQ_DDRC_INIT is not set
# CONFIG_CMD_ZYNQ is not set
CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_SYS_LOAD_ADDR=0x0
and then applied in the load order to the fdt blob stored at the
address indicated in the fdt_addr_r environment variable.
+kaslrseed - set this label to request random number from hwrng as kaslr seed.
+
append <string> - use <string> as the kernel command line when booting this
label.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Clock API
+=========
+
+.. kernel-doc:: include/clk.h
+ :doc: Overview
+
+Client API
+----------
+
+.. kernel-doc:: include/clk.h
+ :internal:
+
+Driver API
+----------
+
+.. kernel-doc:: include/clk-uclass.h
+ :internal:
.. toctree::
:maxdepth: 2
+ clk
dfu
dm
efi
To generate SMBIOS tables in U-Boot, for use by the OS, enable the
CONFIG_GENERATE_SMBIOS_TABLE option. The easiest way to provide the values to
use is via the device tree. For details see
-device-tree-bindings/sysinfo/smbios.txt
+:download:`smbios.txt <../device-tree-bindings/sysinfo/smbios.txt>`.
TODO List
---------
developed by the Asahi Linux project. At this point the machines with
the following SoCs work:
- - Apple M1 SoC
+ - Apple M1 SoC (t8103)
+ - Apple M1 Pro SoC (t6000)
+ - Apple M1 Max SoC (t6001)
On these SoCs the following hardware is supported:
- S5L serial port
+ - SPI keyboard (on laptops)
- Framebuffer
+ - NVMe storage
- USB 3.1 Type-C ports
-Device trees are currently provided for the M1 Mac mini (2020, J274)
-and M1 MacBook Pro 13" (2020, J293). The M1 MacBook Air (2020) is
-expected to work with the J293 device tree. The M1 iMac (2021) may
-work with the J274 device tree.
+Device trees are currently provided for the M1 Mac mini (2020, J274),
+M1 MacBook Pro 13" (2020, J293), M1 MacBook Air (2020, J313) and M1
+iMac (2021, J456/J457).
Building U-Boot
---------------
https://github.com/AsahiLinux/docs/wiki/Developer-Quickstart
Just replace ``m1n1.macho`` with ``u-boot.macho`` in the instructions.
+
+Debug UART
+----------
+
+Since the base address of the UART is SoC-dependent, the debug UART is
+not enabled by default. To enable the debug UART the base address
+needs to be adjusted and the CONFIG_DEBUG_UART option needs to be
+enabled. The table below gives the correct base address for the
+supported SoCs.
+
+.. list-table::
+ :widths: 32 16
+ :header-rows: 1
+
+ * - SoC
+ - Base Address
+ * - M1 (t8103)
+ - 0x235200000
+ * - M1 Pro/Max (t6000/t6001)
+ - 0x39b200000
QEMU RISC-V
===========
-QEMU for RISC-V supports a special 'virt' machine designed for emulation and
-virtualization purposes. This document describes how to run U-Boot under it.
-Both 32-bit and 64-bit targets are supported, running in either machine or
-supervisor mode.
+QEMU for RISC-V supports a special 'virt' machine and 'spike' machine designed
+for emulation and virtualization purposes. This document describes how to run
+U-Boot under it. Both 32-bit and 64-bit targets are supported, running in
+either machine or supervisor mode.
The QEMU virt machine models a generic RISC-V virtual machine with support for
the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
16550A UART devices in addition to VirtIO and it also uses device-tree to pass
-configuration information to guest software. It implements RISC-V privileged
+configuration information to guest software. It implements the latest RISC-V
+privileged architecture.
See :doc:`../../develop/devicetree/dt_qemu` for information on how to see
the devicetree actually generated by QEMU.
-architecture spec v1.10.
+
+The QEMU spike machine models a minimalistic RISC-V virtual machine with
+only CLINT and HTIF devices. It also uses device-tree to pass configuration
+information to guest software and implements the latest RISC-V privileged
+architecture.
Building U-Boot
---------------
--------------
The minimal QEMU command line to get U-Boot up and running is:
-- For 32-bit RISC-V::
+- For 32-bit RISC-V virt machine::
- qemu-system-riscv32 -nographic -machine virt -bios u-boot
+ qemu-system-riscv32 -nographic -machine virt -bios u-boot.bin
-- For 64-bit RISC-V::
+- For 64-bit RISC-V virt machine::
+
+ qemu-system-riscv64 -nographic -machine virt -bios u-boot.bin
+
+- For 64-bit RISC-V spike machine::
- qemu-system-riscv64 -nographic -machine virt -bios u-boot
+ qemu-system-riscv64 -nographic -machine spike -bios u-boot.bin
The commands above create targets with 128MiB memory by default.
A freely configurable amount of RAM can be created via the '-m'
For instructions on how to run U-Boot in supervisor mode on QEMU
with OpenSBI, see the documentation available with OpenSBI:
https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+https://github.com/riscv/opensbi/blob/master/docs/platform/spike.md
These have been tested in QEMU 5.0.0.
See the OpenSBI documentation for full details:
https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+https://github.com/riscv/opensbi/blob/master/docs/platform/spike.md
-To make the FW_DYNAMIC binary (build/platform/qemu/virt/firmware/fw_dynamic.bin)
+To make the FW_DYNAMIC binary (build/platform/generic/firmware/fw_dynamic.bin)
available to U-Boot, either copy it into the U-Boot root directory or specify
its location with the OPENSBI environment variable. Afterwards, compile U-Boot
with the following commands.
The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
configurations are:
-- For 32-bit RISC-V::
+- For 32-bit RISC-V virt machine::
- qemu-system-riscv32 -nographic -machine virt -bios spl/u-boot-spl \
+ qemu-system-riscv32 -nographic -machine virt -bios spl/u-boot-spl.bin \
-device loader,file=u-boot.itb,addr=0x80200000
-- For 64-bit RISC-V::
+- For 64-bit RISC-V virt machine::
+
+ qemu-system-riscv64 -nographic -machine virt -bios spl/u-boot-spl.bin \
+ -device loader,file=u-boot.itb,addr=0x80200000
+
+- For 64-bit RISC-V spike machine::
- qemu-system-riscv64 -nographic -machine virt -bios spl/u-boot-spl \
+ qemu-system-riscv64 -nographic -machine spike -bios spl/u-boot-spl.bin \
-device loader,file=u-boot.itb,addr=0x80200000
-An attached disk can be emulated by adding::
+An attached disk can be emulated in RISC-V virt machine by adding::
-device ich9-ahci,id=ahci \
-drive if=none,file=riscv64.img,format=raw,id=mydisk \
tbs/index
ti/index
toradex/index
+ variscite/index
xen/index
xilinx/index
.. toctree::
:maxdepth: 2
+ pitx-imx8m
sl28
sl-mx6ul
sl-mx8mm
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron pitx-imx8m
+==================
+
+The Kontron pitx-imx8m is an embedded board with an i.MX8MQ in the pITX
+form factor.
+
+The board has two Ethernet ports, USB, HDMI/LVDS, m.2 slot, SD card, CAN,
+RS232 and much more.
+
+Quick Start
+-----------
+
+- Get and build the ARM Trusted firmware binary
+- Get DDR and HDMI firmware
+- Build U-Boot
+- Install on SD card
+- Boot
+
+Get and build the ARM Trusted firmware binary
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+
+.. code-block:: bash
+
+ $ git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ $ git checkout v2.5
+ $ make PLAT=imx8mq ARCH=aarch64 CROSS_COMPILE=aarch64-linux-gnu- bl31
+ $ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get DDR and HDMI firmware
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.11.bin
+ $ chmod +x firmware-imx-8.11.bin
+ $ ./firmware-imx-8.11
+ $ cp firmware-imx-8.11/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+ $ cp firmware-imx-8.11/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make kontron_pitx_imx8m_defconfig
+ $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+Install on SD card
+^^^^^^^^^^^^^^^^^^
+
+
+Burn the flash.bin to SD card at an offset of 33 KiB:
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+^^^^
+
+Set the boot source selection to SD card boot and power on the board.
.. code-block:: bash
$ make kontron-sl-mx8mm_defconfig
- $ export ATF_LOAD_ADDR=0x920000
$ make
Burn the flash.bin to SD card at an offset of 33 KiB:
Install the bootloader on the board
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-Please note, this bootloader doesn't support the builtin watchdog (yet),
-therefore you have to disable it, see below. Otherwise you'll end up in
-the failsafe bootloader on every reset::
+To install the bootloader binary use the following command::
> tftp path/to/u-boot.rom
> sf probe 0
> sf update $fileaddr 0x210000 $filesize
-The board is fully failsafe, you can't break anything. But because you've
-disabled the builtin watchdog you might have to manually enter failsafe
-mode by asserting the ``FORCE_RECOV#`` line during board reset.
-
-Disable the builtin watchdog
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-- boot into the failsafe bootloader, either by asserting the
- ``FORCE_RECOV#`` line or if you still have the original bootloader
- installed you can use the command::
-
- > wdt dev cpld_watchdog@4a; wdt expire 1
-
-- in the failsafe bootloader use the "sl28 nvm" command to disable
- the automatic start of the builtin watchdog::
-
- > sl28 nvm 0008
-
-- power-cycle the board
-
+The board is fully failsafe, you can't break anything. If builtin watchdog
+is enabled, you'll automatically end up in the failsafe bootloader if
+something goes wrong. If the watchdog is disabled, you have to manually
+enter failsafe mode by asserting the ``FORCE_RECOV#`` line during board
+reset.
Update image
------------
folder. On the next EFI boot this will automatically update your
bootloader.
-Useful I2C tricks
------------------
+Builtin watchdog
+----------------
+
+The builtin watchdog will supervise the bootloader startup. If anything
+goes wrong it will reset the board and boot into the failsafe bootloader.
+
+Once the bootloader is started successfully, it will disable the watchdog
+timer.
-The board has a board management controller which is not supported in
-u-boot (yet). But you can use the i2c command to access it.
+wdt command flags
+^^^^^^^^^^^^^^^^^
-- reset into failsafe bootloader::
+The `wdt start` as well as the `wdt expire` command take a flags argument.
+The supported bitmask is as follows.
- > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
+| Bit | Description |
+| --- | ----------------------------- |
+| 0 | Enable failsafe mode |
+| 1 | Lock the control register |
+| 2 | Disable board reset |
+| 3 | Enable WDT_TIME_OUT# line |
-- read board management controller version::
+For example, you can use `wdt expire 1` to issue a reset and boot into the
+failsafe bootloader.
+
+Disable the builtin watchdog
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- > i2c md 4a 3.1 1
+If for some reason, this isn't a desired behavior, the watchdog can also
+be configured to not be enabled on board reset. It's configuration is saved
+in the non-volatile board configuration bits. To change these you can use
+the `sl28 nvm` command.
+For more information on the non-volatile board configuration bits, see the
+following section.
Non-volatile Board Configuration Bits
-------------------------------------
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx8mm_evk_defconfig
- $ export ATF_LOAD_ADDR=0x920000
$ make
Burn the flash.bin to MicroSD card offset 33KB:
.. code-block:: bash
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
- $sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=notrunc
Boot
----
colibri_imx7
colibri-imx8x
verdin-imx8mm
+ verdin-imx8mp
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-linux-gnu-
- $ export ATF_LOAD_ADDR=0x920000
$ make verdin-imx8mm_defconfig
$ make
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Verdin iMX8M Plus Module
+========================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get the DDR firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: bash
+
+ $ echo "Downloading and building TF-A..."
+ $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make PLAT=imx8mp IMX_BOOT_UART_BASE=0x30880000 bl31
+ $ cp build/imx8mp/release/bl31.bin ../
+
+Get the DDR Firmware
+--------------------
+
+.. code-block:: bash
+
+ $ cd ..
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.1.bin
+ $ chmod +x firmware-imx-8.10.1.bin
+ $ ./firmware-imx-8.10.1.bin
+ $ cp firmware-imx-8.10.1/firmware/ddr/synopsys/lpddr4*_202006.bin ./
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make verdin-imx8mp_defconfig
+ $ make
+
+Flash to eMMC
+-------------
+
+.. code-block:: bash
+
+ > tftpboot ${loadaddr} flash.bin
+ > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+ > mmc dev 2 1 && mmc write ${loadaddr} 0x0 ${blkcnt}
+
+As a convenience, instead of the last two commands one may also use the update
+U-Boot wrapper:
+
+.. code-block:: bash
+
+ > run update_uboot
+
+Boot
+----
+
+ATF, U-Boot proper and u-boot.dtb images are packed into FIT image,
+which is loaded and parsed by SPL.
+
+Boot sequence is:
+
+* SPL ---> ATF (TF-A) ---> U-Boot proper
+
+Output:
+
+.. code-block:: bash
+
+U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
+Quad die, dual rank failed, attempting dual die, single rank configuration.
+Normal Boot
+WDT: Started watchdog@30280000 with servicing (60s timeout)
+Trying to boot from BOOTROM
+Find img info 0x&48025a00, size 872
+Need continue download 1024
+Download 779264, Total size 780424
+NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
+NOTICE: BL31: Built : 16:52:37, Aug 26 2021
+
+
+U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
+
+CPU: Freescale i.MX8MP[8] rev1.1 at 1200 MHz
+Reset cause: POR
+DRAM: 8 GiB
+Core: 78 devices, 18 uclasses, devicetree: separate
+WDT: Started watchdog@30280000 with servicing (60s timeout)
+MMC: FSL_SDHC: 1, FSL_SDHC: 2
+Loading Environment from MMC... OK
+In: serial
+Out: serial
+Err: serial
+Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
+Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
+Setting variant to wifi
+Net: Hard-coding pdata->enetaddr
+eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
+Hit any key to stop autoboot: 0
+Verdin iMX8MP #
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mn_var_som
+==============
+
+U-Boot for the Variscite VAR-SOM-MX8MN Symphony evaluation board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/ARM-software/arm-trusted-firmware
+tag: v2.5
+
+.. code-block:: bash
+
+ $ make PLAT=imx8mn IMX_BOOT_UART_BASE=0x30a60000 bl31
+ $ cp build/imx8mn/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+ $ chmod +x firmware-imx-8.9.bin
+ $ ./firmware-imx-8.9
+ $ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr4*.bin $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make imx8mn_var_som_defconfig
+ $ make
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Variscite
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ imx8mn_var_som
The first argument for kcalloc or kmalloc_array should be the
number of elements. sizeof() as the first argument is generally
wrong.
+
See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html
**ALLOC_SIZEOF_STRUCT**
**ALLOC_WITH_MULTIPLY**
Prefer kmalloc_array/kcalloc over kmalloc/kzalloc with a
sizeof multiply.
+
See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html
BUG() or BUG_ON() should be avoided totally.
Use WARN() and WARN_ON() instead, and handle the "impossible"
error condition as gracefully as possible.
+
See: https://www.kernel.org/doc/html/latest/process/deprecated.html#bug-and-bug-on
**CONSIDER_KSTRTO**
may lead to unexpected results in callers. The respective kstrtol(),
kstrtoll(), kstrtoul(), and kstrtoull() functions tend to be the
correct replacements.
+
See: https://www.kernel.org/doc/html/latest/process/deprecated.html#simple-strtol-simple-strtoll-simple-strtoul-simple-strtoull
+ **CONSTANT_CONVERSION**
+ Use of __constant_<foo> form is discouraged for the following functions::
+
+ __constant_cpu_to_be[x]
+ __constant_cpu_to_le[x]
+ __constant_be[x]_to_cpu
+ __constant_le[x]_to_cpu
+ __constant_htons
+ __constant_ntohs
+
+ Using any of these outside of include/uapi/ is not preferred as using the
+ function without __constant_ is identical when the argument is a
+ constant.
+
+ In big endian systems, the macros like __constant_cpu_to_be32(x) and
+ cpu_to_be32(x) expand to the same expression::
+
+ #define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x))
+ #define __cpu_to_be32(x) ((__force __be32)(__u32)(x))
+
+ In little endian systems, the macros __constant_cpu_to_be32(x) and
+ cpu_to_be32(x) expand to __constant_swab32 and __swab32. __swab32
+ has a __builtin_constant_p check::
+
+ #define __swab32(x) \
+ (__builtin_constant_p((__u32)(x)) ? \
+ ___constant_swab32(x) : \
+ __fswab32(x))
+
+ So ultimately they have a special case for constants.
+ Similar is the case with all of the macros in the list. Thus
+ using the __constant_... forms are unnecessarily verbose and
+ not preferred outside of include/uapi.
+
+ See: https://lore.kernel.org/lkml/1400106425.12666.6.camel@joe-AO725/
+
+ **DEPRECATED_API**
+ Usage of a deprecated RCU API is detected. It is recommended to replace
+ old flavourful RCU APIs by their new vanilla-RCU counterparts.
+
+ The full list of available RCU APIs can be viewed from the kernel docs.
+
+ See: https://www.kernel.org/doc/html/latest/RCU/whatisRCU.html#full-list-of-rcu-apis
+
+ **DEPRECATED_VARIABLE**
+ EXTRA_{A,C,CPP,LD}FLAGS are deprecated and should be replaced by the new
+ flags added via commit f77bf01425b1 ("kbuild: introduce ccflags-y,
+ asflags-y and ldflags-y").
+
+ The following conversion scheme maybe used::
+
+ EXTRA_AFLAGS -> asflags-y
+ EXTRA_CFLAGS -> ccflags-y
+ EXTRA_CPPFLAGS -> cppflags-y
+ EXTRA_LDFLAGS -> ldflags-y
+
+ See:
+
+ 1. https://lore.kernel.org/lkml/20070930191054.GA15876@uranus.ravnborg.org/
+ 2. https://lore.kernel.org/lkml/1313384834-24433-12-git-send-email-lacombar@gmail.com/
+ 3. https://www.kernel.org/doc/html/latest/kbuild/makefiles.html#compilation-flags
+
+ **DEVICE_ATTR_FUNCTIONS**
+ The function names used in DEVICE_ATTR is unusual.
+ Typically, the store and show functions are used with <attr>_store and
+ <attr>_show, where <attr> is a named attribute variable of the device.
+
+ Consider the following examples::
+
+ static DEVICE_ATTR(type, 0444, type_show, NULL);
+ static DEVICE_ATTR(power, 0644, power_show, power_store);
+
+ The function names should preferably follow the above pattern.
+
+ See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes
+
+ **DEVICE_ATTR_RO**
+ The DEVICE_ATTR_RO(name) helper macro can be used instead of
+ DEVICE_ATTR(name, 0444, name_show, NULL);
+
+ Note that the macro automatically appends _show to the named
+ attribute variable of the device for the show method.
+
+ See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes
+
+ **DEVICE_ATTR_RW**
+ The DEVICE_ATTR_RW(name) helper macro can be used instead of
+ DEVICE_ATTR(name, 0644, name_show, name_store);
+
+ Note that the macro automatically appends _show and _store to the
+ named attribute variable of the device for the show and store methods.
+
+ See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes
+
+ **DEVICE_ATTR_WO**
+ The DEVICE_AATR_WO(name) helper macro can be used instead of
+ DEVICE_ATTR(name, 0200, NULL, name_store);
+
+ Note that the macro automatically appends _store to the
+ named attribute variable of the device for the store method.
+
+ See: https://www.kernel.org/doc/html/latest/driver-api/driver-model/device.html#attributes
+
+ **DUPLICATED_SYSCTL_CONST**
+ Commit d91bff3011cf ("proc/sysctl: add shared variables for range
+ check") added some shared const variables to be used instead of a local
+ copy in each source file.
+
+ Consider replacing the sysctl range checking value with the shared
+ one in include/linux/sysctl.h. The following conversion scheme may
+ be used::
+
+ &zero -> SYSCTL_ZERO
+ &one -> SYSCTL_ONE
+ &int_max -> SYSCTL_INT_MAX
+
+ See:
+
+ 1. https://lore.kernel.org/lkml/20190430180111.10688-1-mcroce@redhat.com/
+ 2. https://lore.kernel.org/lkml/20190531131422.14970-1-mcroce@redhat.com/
+
+ **ENOSYS**
+ ENOSYS means that a nonexistent system call was called.
+ Earlier, it was wrongly used for things like invalid operations on
+ otherwise valid syscalls. This should be avoided in new code.
+
+ See: https://lore.kernel.org/lkml/5eb299021dec23c1a48fa7d9f2c8b794e967766d.1408730669.git.luto@amacapital.net/
+
+ **ENOTSUPP**
+ ENOTSUPP is not a standard error code and should be avoided in new patches.
+ EOPNOTSUPP should be used instead.
+
+ See: https://lore.kernel.org/netdev/20200510182252.GA411829@lunn.ch/
+
+ **EXPORT_SYMBOL**
+ EXPORT_SYMBOL should immediately follow the symbol to be exported.
+
+ **IN_ATOMIC**
+ in_atomic() is not for driver use so any such use is reported as an ERROR.
+ Also in_atomic() is often used to determine if sleeping is permitted,
+ but it is not reliable in this use model. Therefore its use is
+ strongly discouraged.
+
+ However, in_atomic() is ok for core kernel use.
+
+ See: https://lore.kernel.org/lkml/20080320201723.b87b3732.akpm@linux-foundation.org/
+
**LOCKDEP**
The lockdep_no_validate class was added as a temporary measure to
prevent warnings on conversion of device->sem to device->mutex.
It should not be used for any other purpose.
+
See: https://lore.kernel.org/lkml/1268959062.9440.467.camel@laptop/
**MALFORMED_INCLUDE**
**USE_LOCKDEP**
lockdep_assert_held() annotations should be preferred over
assertions based on spin_is_locked()
+
See: https://www.kernel.org/doc/html/latest/locking/lockdep-design.html#annotations
**UAPI_INCLUDE**
No #include statements in include/uapi should use a uapi/ path.
+ **USLEEP_RANGE**
+ usleep_range() should be preferred over udelay(). The proper way of
+ using usleep_range() is mentioned in the kernel docs.
+
+ See: https://www.kernel.org/doc/html/latest/timers/timers-howto.html#delays-information-on-the-various-kernel-delay-sleep-mechanisms
-Comment style
--------------
+
+Comments
+--------
**BLOCK_COMMENT_STYLE**
The comment style is incorrect. The preferred style for multi-
**C99_COMMENTS**
C99 style single line comments (//) should not be used.
Prefer the block comment style instead.
+
See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting
+ **DATA_RACE**
+ Applications of data_race() should have a comment so as to document the
+ reasoning behind why it was deemed safe.
+
+ See: https://lore.kernel.org/lkml/20200401101714.44781-1-elver@google.com/
+
+ **FSF_MAILING_ADDRESS**
+ Kernel maintainers reject new instances of the GPL boilerplate paragraph
+ directing people to write to the FSF for a copy of the GPL, since the
+ FSF has moved in the past and may do so again.
+ So do not write paragraphs about writing to the Free Software Foundation's
+ mailing address.
+
+ See: https://lore.kernel.org/lkml/20131006222342.GT19510@leaf/
+
Commit message
--------------
**BAD_SIGN_OFF**
The signed-off-by line does not fall in line with the standards
specified by the community.
+
See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1
**BAD_STABLE_ADDRESS_STYLE**
**COMMIT_MESSAGE**
The patch is missing a commit description. A brief
description of the changes made by the patch should be added.
+
+ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes
+
+ **EMAIL_SUBJECT**
+ Naming the tool that found the issue is not very useful in the
+ subject line. A good subject line summarizes the change that
+ the patch brings.
+
See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes
+ **FROM_SIGN_OFF_MISMATCH**
+ The author's email does not match with that in the Signed-off-by:
+ line(s). This can be sometimes caused due to an improperly configured
+ email client.
+
+ This message is emitted due to any of the following reasons::
+
+ - The email names do not match.
+ - The email addresses do not match.
+ - The email subaddresses do not match.
+ - The email comments do not match.
+
**MISSING_SIGN_OFF**
The patch is missing a Signed-off-by line. A signed-off-by
line should be added according to Developer's certificate of
Origin.
+
See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin
**NO_AUTHOR_SIGN_OFF**
end of explanation of the patch to denote that the author has
written it or otherwise has the rights to pass it on as an open
source patch.
+
See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin
**DIFF_IN_COMMIT_MSG**
This causes problems when one tries to apply a file containing both
the changelog and the diff because patch(1) tries to apply the diff
which it found in the changelog.
+
See: https://lore.kernel.org/lkml/20150611134006.9df79a893e3636019ad2759e@linux-foundation.org/
**GERRIT_CHANGE_ID**
**BOOL_COMPARISON**
Comparisons of A to true and false are better written
as A and !A.
+
See: https://lore.kernel.org/lkml/1365563834.27174.12.camel@joe-AO722/
**COMPARISON_TO_NULL**
side of the test should be avoided.
+Indentation and Line Breaks
+---------------------------
+
+ **CODE_INDENT**
+ Code indent should use tabs instead of spaces.
+ Outside of comments, documentation and Kconfig,
+ spaces are never used for indentation.
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation
+
+ **DEEP_INDENTATION**
+ Indentation with 6 or more tabs usually indicate overly indented
+ code.
+
+ It is suggested to refactor excessive indentation of
+ if/else/for/do/while/switch statements.
+
+ See: https://lore.kernel.org/lkml/1328311239.21255.24.camel@joe2Laptop/
+
+ **SWITCH_CASE_INDENT_LEVEL**
+ switch should be at the same indent as case.
+ Example::
+
+ switch (suffix) {
+ case 'G':
+ case 'g':
+ mem <<= 30;
+ break;
+ case 'M':
+ case 'm':
+ mem <<= 20;
+ break;
+ case 'K':
+ case 'k':
+ mem <<= 10;
+ fallthrough;
+ default:
+ break;
+ }
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation
+
+ **LONG_LINE**
+ The line has exceeded the specified maximum length.
+ To use a different maximum line length, the --max-line-length=n option
+ may be added while invoking checkpatch.
+
+ Earlier, the default line length was 80 columns. Commit bdc48fa11e46
+ ("checkpatch/coding-style: deprecate 80-column warning") increased the
+ limit to 100 columns. This is not a hard limit either and it's
+ preferable to stay within 80 columns whenever possible.
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
+
+ **LONG_LINE_STRING**
+ A string starts before but extends beyond the maximum line length.
+ To use a different maximum line length, the --max-line-length=n option
+ may be added while invoking checkpatch.
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
+
+ **LONG_LINE_COMMENT**
+ A comment starts before but extends beyond the maximum line length.
+ To use a different maximum line length, the --max-line-length=n option
+ may be added while invoking checkpatch.
+
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
+
+ **SPLIT_STRING**
+ Quoted strings that appear as messages in userspace and can be
+ grepped, should not be split across multiple lines.
+
+ See: https://lore.kernel.org/lkml/20120203052727.GA15035@leaf/
+
+ **MULTILINE_DEREFERENCE**
+ A single dereferencing identifier spanned on multiple lines like::
+
+ struct_identifier->member[index].
+ member = <foo>;
+
+ is generally hard to follow. It can easily lead to typos and so makes
+ the code vulnerable to bugs.
+
+ If fixing the multiple line dereferencing leads to an 80 column
+ violation, then either rewrite the code in a more simple way or if the
+ starting part of the dereferencing identifier is the same and used at
+ multiple places then store it in a temporary variable, and use that
+ temporary variable only at all the places. For example, if there are
+ two dereferencing identifiers::
+
+ member1->member2->member3.foo1;
+ member1->member2->member3.foo2;
+
+ then store the member1->member2->member3 part in a temporary variable.
+ It not only helps to avoid the 80 column violation but also reduces
+ the program size by removing the unnecessary dereferences.
+
+ But if none of the above methods work then ignore the 80 column
+ violation because it is much easier to read a dereferencing identifier
+ on a single line.
+
+ **TRAILING_STATEMENTS**
+ Trailing statements (for example after any conditional) should be
+ on the next line.
+ Statements, such as::
+
+ if (x == y) break;
+
+ should be::
+
+ if (x == y)
+ break;
+
+
Macros, Attributes and Symbols
------------------------------
**BIT_MACRO**
Defines like: 1 << <digit> could be BIT(digit).
- The BIT() macro is defined in include/linux/bitops.h::
+ The BIT() macro is defined via include/linux/bits.h::
#define BIT(nr) (1UL << (nr))
The kernel does *not* use the ``__DATE__`` and ``__TIME__`` macros,
and enables warnings if they are used as they can lead to
non-deterministic builds.
+
See: https://www.kernel.org/doc/html/latest/kbuild/reproducible-builds.html#timestamps
**DEFINE_ARCH_HAS**
want architectures able to override them with optimized ones, we
should either use weak functions (appropriate for some cases), or
the symbol that protects them should be the same symbol we use.
+
See: https://lore.kernel.org/lkml/CA+55aFycQ9XJvEOsiM3txHL5bjUc8CeKWJNR_H+MiicaddB42Q@mail.gmail.com/
+ **DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON**
+ do {} while(0) macros should not have a trailing semicolon.
+
**INIT_ATTRIBUTE**
Const init definitions should use __initconst instead of
__initdata.
...
}
+ **MISPLACED_INIT**
+ It is possible to use section markers on variables in a way
+ which gcc doesn't understand (or at least not the way the
+ developer intended)::
+
+ static struct __initdata samsung_pll_clock exynos4_plls[nr_plls] = {
+
+ does not put exynos4_plls in the .initdata section. The __initdata
+ marker can be virtually anywhere on the line, except right after
+ "struct". The preferred location is before the "=" sign if there is
+ one, or before the trailing ";" otherwise.
+
+ See: https://lore.kernel.org/lkml/1377655732.3619.19.camel@joe-AO722/
+
**MULTISTATEMENT_MACRO_USE_DO_WHILE**
Macros with multiple statements should be enclosed in a
do - while block. Same should also be the case for macros
See: https://www.kernel.org/doc/html/latest/process/coding-style.html#macros-enums-and-rtl
+ **PREFER_FALLTHROUGH**
+ Use the `fallthrough;` pseudo keyword instead of
+ `/* fallthrough */` like comments.
+
+ **TRAILING_SEMICOLON**
+ Macro definition should not end with a semicolon. The macro
+ invocation style should be consistent with function calls.
+ This can prevent any unexpected code paths::
+
+ #define MAC do_something;
+
+ If this macro is used within a if else statement, like::
+
+ if (some_condition)
+ MAC;
+
+ else
+ do_something;
+
+ Then there would be a compilation error, because when the macro is
+ expanded there are two trailing semicolons, so the else branch gets
+ orphaned.
+
+ See: https://lore.kernel.org/lkml/1399671106.2912.21.camel@joe-AO725/
+
+ **SINGLE_STATEMENT_DO_WHILE_MACRO**
+ For the multi-statement macros, it is necessary to use the do-while
+ loop to avoid unpredictable code paths. The do-while loop helps to
+ group the multiple statements into a single one so that a
+ function-like macro can be used as a function only.
+
+ But for the single statement macros, it is unnecessary to use the
+ do-while loop. Although the code is syntactically correct but using
+ the do-while loop is redundant. So remove the do-while loop for single
+ statement macros.
+
**WEAK_DECLARATION**
Using weak declarations like __attribute__((weak)) or __weak
can have unintended link defects. Avoid using them.
**CAMELCASE**
Avoid CamelCase Identifiers.
+
See: https://www.kernel.org/doc/html/latest/process/coding-style.html#naming
+ **CONST_CONST**
+ Using `const <type> const *` is generally meant to be
+ written `const <type> * const`.
+
+ **CONST_STRUCT**
+ Using const is generally a good idea. Checkpatch reads
+ a list of frequently used structs that are always or
+ almost always constant.
+
+ The existing structs list can be viewed from
+ `scripts/const_structs.checkpatch`.
+
+ See: https://lore.kernel.org/lkml/alpine.DEB.2.10.1608281509480.3321@hadrien/
+
+ **EMBEDDED_FUNCTION_NAME**
+ Embedded function names are less appropriate to use as
+ refactoring can cause function renaming. Prefer the use of
+ "%s", __func__ to embedded function names.
+
+ Note that this does not work with -f (--file) checkpatch option
+ as it depends on patch context providing the function name.
+
+ **FUNCTION_ARGUMENTS**
+ This warning is emitted due to any of the following reasons:
+
+ 1. Arguments for the function declaration do not follow
+ the identifier name. Example::
+
+ void foo
+ (int bar, int baz)
+
+ This should be corrected to::
+
+ void foo(int bar, int baz)
+
+ 2. Some arguments for the function definition do not
+ have an identifier name. Example::
+
+ void foo(int)
+
+ All arguments should have identifier names.
+
**FUNCTION_WITHOUT_ARGS**
Function declarations without arguments like::
Your compiler (or rather your loader) automatically does
it for you.
+ **MULTIPLE_ASSIGNMENTS**
+ Multiple assignments on a single line makes the code unnecessarily
+ complicated. So on a single line assign value to a single variable
+ only, this makes the code more readable and helps avoid typos.
+
**RETURN_PARENTHESES**
return is not a function and as such doesn't need parentheses::
return bar;
+Permissions
+-----------
+
+ **DEVICE_ATTR_PERMS**
+ The permissions used in DEVICE_ATTR are unusual.
+ Typically only three permissions are used - 0644 (RW), 0444 (RO)
+ and 0200 (WO).
+
+ See: https://www.kernel.org/doc/html/latest/filesystems/sysfs.html#attributes
+
+ **EXECUTE_PERMISSIONS**
+ There is no reason for source files to be executable. The executable
+ bit can be removed safely.
+
+ **EXPORTED_WORLD_WRITABLE**
+ Exporting world writable sysfs/debugfs files is usually a bad thing.
+ When done arbitrarily they can introduce serious security bugs.
+ In the past, some of the debugfs vulnerabilities would seemingly allow
+ any local user to write arbitrary values into device registers - a
+ situation from which little good can be expected to emerge.
+
+ See: https://lore.kernel.org/linux-arm-kernel/cover.1296818921.git.segoon@openwall.com/
+
+ **NON_OCTAL_PERMISSIONS**
+ Permission bits should use 4 digit octal permissions (like 0700 or 0444).
+ Avoid using any other base like decimal.
+
+ **SYMBOLIC_PERMS**
+ Permission bits in the octal form are more readable and easier to
+ understand than their symbolic counterparts because many command-line
+ tools use this notation. Experienced kernel developers have been using
+ these traditional Unix permission bits for decades and so they find it
+ easier to understand the octal notation than the symbolic macros.
+ For example, it is harder to read S_IWUSR|S_IRUGO than 0644, which
+ obscures the developer's intent rather than clarifying it.
+
+ See: https://lore.kernel.org/lkml/CA+55aFw5v23T-zvDZp-MmD_EYxF8WbafwwB59934FV7g21uMGQ@mail.gmail.com/
+
+
Spacing and Brackets
--------------------
1. With a type on the left::
- ;int [] a;
+ int [] a;
2. At the beginning of a line for slice initialisers::
= { [0...10] = 5 }
- **CODE_INDENT**
- Code indent should use tabs instead of spaces.
- Outside of comments, documentation and Kconfig,
- spaces are never used for indentation.
- See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation
-
**CONCATENATED_STRING**
Concatenated elements should have a space in between.
Example::
**ELSE_AFTER_BRACE**
`else {` should follow the closing block `}` on the same line.
+
See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces
**LINE_SPACING**
Vertical space is wasted given the limited number of lines an
editor window can display when multiple blank lines are used.
+
See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
**OPEN_BRACE**
The opening brace should be following the function definitions on the
next line. For any non-functional block it should be on the same line
as the last construct.
+
See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces
**POINTER_LOCATION**
**SPACING**
Whitespace style used in the kernel sources is described in kernel docs.
- See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
-
- **SWITCH_CASE_INDENT_LEVEL**
- switch should be at the same indent as case.
- Example::
- switch (suffix) {
- case 'G':
- case 'g':
- mem <<= 30;
- break;
- case 'M':
- case 'm':
- mem <<= 20;
- break;
- case 'K':
- case 'k':
- mem <<= 10;
- /* fall through */
- default:
- break;
- }
-
- See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation
+ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
**TRAILING_WHITESPACE**
Trailing whitespace should always be removed.
Some editors highlight the trailing whitespace and cause visual
distractions when editing files.
+
See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces
+ **UNNECESSARY_PARENTHESES**
+ Parentheses are not required in the following cases:
+
+ 1. Function pointer uses::
+
+ (foo->bar)();
+
+ could be::
+
+ foo->bar();
+
+ 2. Comparisons in if::
+
+ if ((foo->bar) && (foo->baz))
+ if ((foo == bar))
+
+ could be::
+
+ if (foo->bar && foo->baz)
+ if (foo == bar)
+
+ 3. addressof/dereference single Lvalues::
+
+ &(foo->bar)
+ *(foo->bar)
+
+ could be::
+
+ &foo->bar
+ *foo->bar
+
**WHILE_AFTER_BRACE**
while should follow the closing bracket on the same line::
The patch seems to be corrupted or lines are wrapped.
Please regenerate the patch file before sending it to the maintainer.
+ **CVS_KEYWORD**
+ Since linux moved to git, the CVS markers are no longer used.
+ So, CVS style keywords ($Id$, $Revision$, $Log$) should not be
+ added.
+
+ **DEFAULT_NO_BREAK**
+ switch default case is sometimes written as "default:;". This can
+ cause new cases added below default to be defective.
+
+ A "break;" should be added after empty default statement to avoid
+ unwanted fallthrough.
+
**DOS_LINE_ENDINGS**
For DOS-formatted patches, there are extra ^M symbols at the end of
the line. These should be removed.
- **EXECUTE_PERMISSIONS**
- There is no reason for source files to be executable. The executable
- bit can be removed safely.
+ **DT_SCHEMA_BINDING_PATCH**
+ DT bindings moved to a json-schema based format instead of
+ freeform text.
- **NON_OCTAL_PERMISSIONS**
- Permission bits should use 4 digit octal permissions (like 0700 or 0444).
- Avoid using any other base like decimal.
+ See: https://www.kernel.org/doc/html/latest/devicetree/bindings/writing-schema.html
+
+ **DT_SPLIT_BINDING_PATCH**
+ Devicetree bindings should be their own patch. This is because
+ bindings are logically independent from a driver implementation,
+ they have a different maintainer (even though they often
+ are applied via the same tree), and it makes for a cleaner history in the
+ DT only tree created with git-filter-branch.
+
+ See: https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
+
+ **EMBEDDED_FILENAME**
+ Embedding the complete filename path inside the file isn't particularly
+ useful as often the path is moved around and becomes incorrect.
+
+ **FILE_PATH_CHANGES**
+ Whenever files are added, moved, or deleted, the MAINTAINERS file
+ patterns can be out of sync or outdated.
+
+ So MAINTAINERS might need updating in these cases.
+
+ **MEMSET**
+ The memset use appears to be incorrect. This may be caused due to
+ badly ordered parameters. Please recheck the usage.
**NOT_UNIFIED_DIFF**
The patch file does not appear to be in unified-diff format. Please
**PRINTF_0XDECIMAL**
Prefixing 0x with decimal output is defective and should be corrected.
- **TRAILING_STATEMENTS**
- Trailing statements (for example after any conditional) should be
- on the next line.
- Like::
+ **SPDX_LICENSE_TAG**
+ The source file is missing or has an improper SPDX identifier tag.
+ The Linux kernel requires the precise SPDX identifier in all source files,
+ and it is thoroughly documented in the kernel docs.
- if (x == y) break;
+ See: https://www.kernel.org/doc/html/latest/process/license-rules.html
- should be::
-
- if (x == y)
- break;
+ **TYPO_SPELLING**
+ Some words may have been misspelled. Consider reviewing them.
Config options
--------------
CONFIG_NVME Enable NVMe device support
+CONFIG_NVME_PCI Enable PCIe NVMe device support
CONFIG_CMD_NVME Enable basic NVMe commands
Usage in U-Boot
makefiles
menus
printf
+ smbios
uefi/index
version
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+SMBIOS tables
+=============
+
+The System Management BIOS (SMBIOS) table is used to deliver management
+information from the firmware to the operating system. The content is
+standardized in [1]_.
+
+In Linux you can use the dmidecode command to view the contents of the SMBIOS
+table.
+
+When booting via UEFI the SMBIOS table is transferred as an UEFI configuration
+table to the operating system.
+
+To generate SMBIOS tables in U-Boot, the CONFIG_GENERATE_SMBIOS_TABLE option
+must be enabled. The easiest way to provide the values to use is via the device
+tree. For details see
+:download:`smbios.txt <../device-tree-bindings/sysinfo/smbios.txt>`.
+
+.. [1] `System Management BIOS (SMBIOS) Reference, version 3.5
+ <https://www.dmtf.org/content/dmtf-releases-smbios-35>`_
enables updating the U-Boot image using the UEFI firmware management
protocol (FMP). The capsules are not passed to the firmware through
the UpdateCapsule runtime service. Instead, capsule-on-disk
-functionality is used for fetching the capsule from the EFI System
-Partition (ESP) by placing the capsule file under the
-\EFI\UpdateCapsule directory.
-
-The directory \EFI\UpdateCapsule is checked for capsules only within the
-EFI system partition on the device specified in the active boot option
-determined by reference to BootNext variable or BootOrder variable processing.
-The active Boot Variable is the variable with highest priority BootNext or
-within BootOrder that refers to a device found to be present. Boot variables
-in BootOrder but referring to devices not present are ignored when determining
-active boot variable.
-Before starting a capsule update make sure your capsules are installed in the
-correct ESP partition or set BootNext.
+functionality is used for fetching capsules from the EFI System
+Partition (ESP) by placing capsule files under the directory::
+
+ \EFI\UpdateCapsule
+
+The directory is checked for capsules only within the
+EFI system partition on the device specified in the active boot option,
+which is determined by BootXXXX variable in BootNext, or if not, the highest
+priority one within BootOrder. Any BootXXXX variables referring to devices
+not present are ignored when determining the active boot option.
+
+Please note that capsules will be applied in the alphabetic order of
+capsule file names.
+
+Creating a capsule file
+***********************
+
+A capsule file can be created by using tools/mkeficapsule.
+To build this tool, enable::
+
+ CONFIG_TOOLS_MKEFICAPSULE=y
+ CONFIG_TOOLS_LIBCRYPTO=y
+
+Run the following command
+
+.. code-block:: console
+
+ $ mkeficapsule \
+ --index 1 --instance 0 \
+ [--fit <FIT image> | --raw <raw image>] \
+ <capsule_file_name>
Performing the update
*********************
-Since U-boot doesn't currently support SetVariable at runtime there's a Kconfig
-option (CONFIG_EFI_IGNORE_OSINDICATIONS) to disable the OsIndications variable
-check. If that option is enabled just copy your capsule to \EFI\UpdateCapsule.
+Put capsule files under the directory mentioned above.
+Then, following the UEFI specification, you'll need to set
+the EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED
+bit in OsIndications variable with
-If that option is disabled, you'll need to set the OsIndications variable with::
+.. code-block:: console
=> setenv -e -nv -bs -rt -v OsIndications =0x04
-Finally, the capsule update can be initiated either by rebooting the board,
-which is the preferred method, or by issuing the following command::
-
- => efidebug capsule disk-update
+Since U-boot doesn't currently support SetVariable at runtime, its value
+won't be taken over across the reboot. If this is the case, you can skip
+this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS)
+set.
-**The efidebug command is should only be used during debugging/development.**
+Finally, the capsule update can be initiated by rebooting the board.
Enabling Capsule Authentication
*******************************
is computed and prepended to the capsule payload at the time of
capsule generation. This signature is then verified by using the
public key stored as part of the X509 certificate. This certificate is
-in the form of an efi signature list (esl) file, which is embedded as
-part of U-Boot.
+in the form of an efi signature list (esl) file, which is embedded in
+a device tree.
The capsule authentication feature can be enabled through the
following config, in addition to the configs listed above for capsule
update::
CONFIG_EFI_CAPSULE_AUTHENTICATE=y
- CONFIG_EFI_CAPSULE_KEY_PATH=<path to .esl cert>
The public and private keys used for the signing process are generated
-and used by the steps highlighted below::
+and used by the steps highlighted below.
- 1. Install utility commands on your host
- * OPENSSL
+1. Install utility commands on your host
+ * openssl
* efitools
- 2. Create signing keys and certificate files on your host
+2. Create signing keys and certificate files on your host
- $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ \
- -keyout CRT.key -out CRT.crt -nodes -days 365
- $ cert-to-efi-sig-list CRT.crt CRT.esl
+.. code-block:: console
- $ openssl x509 -in CRT.crt -out CRT.cer -outform DER
- $ openssl x509 -inform DER -in CRT.cer -outform PEM -out CRT.pub.pem
+ $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ \
+ -keyout CRT.key -out CRT.crt -nodes -days 365
+ $ cert-to-efi-sig-list CRT.crt CRT.esl
- $ openssl pkcs12 -export -out CRT.pfx -inkey CRT.key -in CRT.crt
- $ openssl pkcs12 -in CRT.pfx -nodes -out CRT.pem
+3. Run the following command to create and sign the capsule file
-The capsule file can be generated by using the GenerateCapsule.py
-script in EDKII::
+.. code-block:: console
- $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
- <capsule_file_name> --monotonic-count <val> --fw-version \
- <val> --lsv <val> --guid \
- e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose \
- --update-image-index <val> --signer-private-cert \
- /path/to/CRT.pem --trusted-public-cert \
- /path/to/CRT.pub.pem --other-public-cert /path/to/CRT.pub.pem \
- <u-boot.bin>
+ $ mkeficapsule --monotonic-count 1 \
+ --private-key CRT.key \
+ --certificate CRT.crt \
+ --index 1 --instance 0 \
+ [--fit | --raw | --guid <guid-string] \
+ <image_blob> <capsule_file_name>
-Place the capsule generated in the above step on the EFI System
-Partition under the EFI/UpdateCapsule directory
+4. Insert the signature list into a device tree in the following format::
-Testing on QEMU
-***************
+ {
+ signature {
+ capsule-key = [ <binary of signature list> ];
+ }
+ ...
+ }
-Currently, support has been added on the QEMU ARM64 virt platform for
-updating the U-Boot binary as a raw image when the platform is booted
-in non-secure mode, i.e. with CONFIG_TFABOOT disabled. For this
-configuration, the QEMU platform needs to be booted with
-'secure=off'. The U-Boot binary placed on the first bank of the NOR
-flash at offset 0x0. The U-Boot environment is placed on the second
-NOR flash bank at offset 0x4000000.
+You can do step-4 manually with
-The capsule update feature is enabled with the following configuration
-settings::
+.. code-block:: console
- CONFIG_MTD=y
- CONFIG_FLASH_CFI_MTD=y
- CONFIG_CMD_MTDPARTS=y
- CONFIG_CMD_DFU=y
- CONFIG_DFU_MTD=y
- CONFIG_PCI_INIT_R=y
- CONFIG_EFI_CAPSULE_ON_DISK=y
- CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
- CONFIG_EFI_CAPSULE_FIRMWARE=y
- CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+ $ dtc -@ -I dts -O dtb -o signature.dtbo signature.dts
+ $ fdtoverlay -i orig.dtb -o new.dtb -v signature.dtbo
-In addition, the following config needs to be disabled(QEMU ARM specific)::
+where signature.dts looks like::
- CONFIG_TFABOOT
-
-The capsule file can be generated by using the tools/mkeficapsule::
-
- $ mkeficapsule --raw <u-boot.bin> --index 1 <capsule_file_name>
+ &{/} {
+ signature {
+ capsule-key = /incbin/("CRT.esl");
+ };
+ };
Executing the boot manager
~~~~~~~~~~~~~~~~~~~~~~~~~~
"rx" for Receive channel
- mboxes: Corresponding phandles to mailbox channels.
+Optional properties:
+--------------------
+- mbox-names: "boot_notify" for Optional alternate boot notification channel.
Example:
--------
--- /dev/null
+.\" SPDX-License-Identifier: GPL-2.0+
+.\" Copyright (c) 2021, Linaro Limited
+.\" written by AKASHI Takahiro <takahiro.akashi@linaro.org>
+.TH MAEFICAPSULE 1 "May 2021"
+
+.SH NAME
+mkeficapsule \- Generate EFI capsule file for U-Boot
+
+.SH SYNOPSIS
+.B mkeficapsule
+.RI [ options "] " image-blob " " capsule-file
+
+.SH "DESCRIPTION"
+.B mkeficapsule
+command is used to create an EFI capsule file for use with the U-Boot
+EFI capsule update.
+A capsule file may contain various type of firmware blobs which
+are to be applied to the system and must be placed in the specific
+directory on the UEFI system partition.
+An update will be automatically executed at next reboot.
+
+Optionally, a capsule file can be signed with a given private key.
+In this case, the update will be authenticated by verifying the signature
+before applying.
+
+.B mkeficapsule
+takes any type of image files, including:
+.TP
+.I raw image
+format is a single binary blob of any type of firmware.
+
+.TP
+.I FIT (Flattened Image Tree) image
+format is the same as used in the new uImage format and allows for
+multiple binary blobs in a single capsule file.
+This type of image file can be generated by
+.BR mkimage .
+
+.PP
+If you want to use other types than above two, you should explicitly
+specify a guid for the FMP driver.
+
+.SH "OPTIONS"
+One of
+.BR --fit ", " --raw " or " --guid
+option must be specified.
+
+.TP
+.BR -f ", " --fit
+Indicate that the blob is a FIT image file
+
+.TP
+.BR -r ", " --raw
+Indicate that the blob is a raw image file
+
+.TP
+.BI "-g\fR,\fB --guid " guid-string
+Specify guid for image blob type. The format is:
+ xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+
+The first three elements are in little endian, while the rest
+is in big endian.
+
+.TP
+.BI "-i\fR,\fB --index " index
+Specify an image index
+
+.TP
+.BI "-I\fR,\fB --instance " instance
+Specify a hardware instance
+
+.TP
+.BR -h ", " --help
+Print a help message
+
+.PP
+With signing,
+.BR --private-key ", " --certificate " and " --monotonic-count
+are all mandatory.
+
+.TP
+.BI "-p\fR,\fB --private-key " private-key-file
+Specify signer's private key file in PEM
+
+.TP
+.BI "-c\fR,\fB --certificate " certificate-file
+Specify signer's certificate file in EFI certificate list format
+
+.TP
+.BI "-m\fR,\fB --monotonic-count " count
+Specify a monotonic count which is set to be monotonically incremented
+at every firmware update.
+
+.TP
+.B "-d\fR,\fB --dump_sig"
+Dump signature data into *.p7 file
+
+.PP
+.SH FILES
+.TP
+.I /EFI/UpdateCapsule
+The directory in which all capsule files be placed
+
+.SH SEE ALSO
+.BR mkimage (1)
+
+.SH AUTHORS
+Written by AKASHI Takahiro <takahiro.akashi@linaro.org>
+
+.SH HOMEPAGE
+http://www.denx.de/wiki/U-Boot/WebHome
-.TH MKIMAGE 1 "2010-05-16"
+.TH MKIMAGE 1 "2022-02-07"
.SH NAME
mkimage \- Generate image for U-Boot
.SH SYNOPSIS
.B mkimage
-.RB "\-l [" "uimage file name" "]"
+.RB [ \-T " \fItype\fP] " \-l " [\fIuimage file name\fP]"
.B mkimage
.RB [\fIoptions\fP] " \-f [" "image tree source file" "]" " [" "uimage file name" "]"
.BI "\-l [" "uimage file name" "]"
mkimage lists the information contained in the header of an existing U-Boot image.
+.TP
+.BI "\-T [" "image type" "]"
+Parse image file as type.
+Pass \-h as the image to see the list of supported image type.
+Without this option image type is autodetected.
+
.P
.B Create old legacy image:
.TP
.BI "\-o [" "signing algorithm" "]"
Specifies the algorithm to be used for signing a FIT image. The default is
-taken from the target signature nodes 'algo' properties.
+taken from the signature node's 'algo' property.
.TP
.BI "\-p [" "external position" "]"
each element in *dfu_alt_info* being
* <name> raw <offset> <size> [mmcpart <num>] raw access to mmc device
- * <name> part <dev> <part_id> [mmcpart <num>] raw access to partition
- * <name> fat <dev> <part_id> [mmcpart <num>] file in FAT partition
- * <name> ext4 <dev> <part_id> [mmcpart <num>] file in EXT4 partition
+ * <name> part <dev> <part_id> [offset <byte>] raw access to partition
+ * <name> fat <dev> <part_id> file in FAT partition
+ * <name> ext4 <dev> <part_id> file in EXT4 partition
* <name> skip 0 0 ignore flashed data
* <name> script 0 0 execute commands in shell
each element in *dfu_alt_info* being either of
- * <name> raw <offset> <size> raw access to mmc device
- * <name> part <dev> <part_id> raw acces to partition
- * <name> partubi <dev> <part_id> raw acces to ubi partition
+ * <name> raw <offset> <size> raw access to nand device
+ * <name> part <dev_id> <part_id> raw access to partition
+ * <name> partubi <dev_id> <part_id> raw access to ubi partition
with
- partid
- is the MTD partition index
+ offset
+ is the offset in the nand device (hexadecimal without "0x")
+ size
+ is the size of the access area (hexadecimal without "0x")
+ dev_id
+ is the NAND device index (decimal only)
+ part_id
+ is the NAND partition index (decimal only)
ram
raw access to ram::
<name> ram <offset> <size> raw access to ram
+ with
+
+ offset
+ is the offset in the ram device (hexadecimal without "0x")
+ size
+ is the size of the access area (hexadecimal without "0x")
+
sf
serial flash : NOR::
each element in *dfu_alt_info* being either of:
* <name> raw <offset> <size> raw access to sf device
- * <name> part <dev> <part_id> raw acces to partition
- * <name> partubi <dev> <part_id> raw acces to ubi partition
+ * <name> part <dev
_id> <part_id> raw acces to partition
+ * <name> partubi <dev
_id> <part_id> raw acces to ubi partition
with
- partid
- is the MTD partition index
+ offset
+ is the offset in the sf device (hexadecimal without "0x")
+ size
+ is the size of the access area (hexadecimal without "0x")
+ dev_id
+ is the sf device index (the device is "nor<dev_id>") (deximal only)
+ part_id
+ is the MTD partition index (decimal only)
mtd
all MTD device: NAND, SPI-NOR, SPI-NAND,...::
each element in *dfu_alt_info* being either of:
- * <name> raw <offset> <size> forraw access to mtd device
- * <name> part <dev> <part_id> for raw acces to partition
- * <name> partubi <dev> <part_id> for raw acces to ubi partition
+ * <name> raw <offset> <size> for raw access to mtd device
+ * <name> part <part_id> for raw access to partition
+ * <name> partubi <part_id> for raw access to ubi partition
with
- partid
- is the MTD partition index
+ offset
+ is the offset in the mtd device (hexadecimal without "0x")
+ size
+ is the size of the access area (hexadecimal without "0x")
+ part_id
+ is the MTD partition index (decimal only)
virt
virtual flash back end for DFU
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+:
+
+fatload command
+===============
+
+Synopsis
+--------
+
+::
+
+ fatload <interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]]
+
+Description
+-----------
+
+The fatload command is used to read a file from a FAT filesystem into memory.
+You can always use the :doc:`load command <load>` instead.
+
+The number of transferred bytes is saved in the environment variable filesize.
+The load address is saved in the environment variable fileaddr.
+
+interface
+ interface for accessing the block device (mmc, sata, scsi, usb, ....)
+
+dev
+ device number
+
+part
+ partition number, defaults to 0 (whole device)
+
+addr
+ load address, defaults to environment variable loadaddr or if loadaddr is
+ not set to configuration variable CONFIG_SYS_LOAD_ADDR
+
+filename
+ path to file, defaults to environment variable bootfile
+
+bytes
+ maximum number of bytes to load
+
+pos
+ number of bytes to skip
+
+addr, bytes, pos are hexadecimal numbers.
+
+If either 'pos' or 'bytes' are not aligned according to the minimum alignment
+requirement for DMA transfer (ARCH_DMA_MINALIGN) additional buffering will be
+used, a misaligned buffer warning will be printed, and performance will suffer
+for the load.
+
+Example
+-------
+
+::
+
+ => fatload mmc 0:1 ${kernel_addr_r} snp.efi
+ 149280 bytes read in 11 ms (12.9 MiB/s)
+ =>
+ => fatload mmc 0:1 ${kernel_addr_r} snp.efi 1000000
+ 149280 bytes read in 9 ms (15.8 MiB/s)
+ =>
+ => fatload mmc 0:1 ${kernel_addr_r} snp.efi 1000000 100
+ 149024 bytes read in 10 ms (14.2 MiB/s)
+ =>
+ => fatload mmc 0:1 ${kernel_addr_r} snp.efi 10
+ 16 bytes read in 1 ms (15.6 KiB/s)
+ =>
+
+Configuration
+-------------
+
+The fatload command is only available if CONFIG_CMD_FAT=y.
+
+Return value
+------------
+
+The return value $? is set to 0 (true) if the file was successfully loaded
+even if the number of bytes is less then the specified length.
+
+If an error occurs, the return value $? is set to 1 (false).
exit
false
fatinfo
+ fatload
for
load
loady
config SATA
bool "Support SATA controllers"
+ depends on BLK
select HAVE_BLOCK_DEVICE
help
This enables support for SATA (Serial Advanced Technology
help
Enables support for the PCI-based AHCI controller.
+if AHCI
+
config SPL_AHCI_PCI
bool "Support for PCI-based AHCI controller for SPL"
depends on SPL
depends on SPL_PCI
depends on SPL_SATA_SUPPORT && DM_SCSI
-config SATA_CEVA
- bool "Ceva Sata controller"
- depends on AHCI
- depends on DM_SCSI
- help
- This option enables Ceva Sata controller hard IP available on Xilinx
- ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and
- AHCI 1.3 specifications with hot-plug detect feature.
-
-
config DWC_AHCI
bool "Enable Synopsys DWC AHCI driver support"
select SCSI_AHCI
config DWC_AHSATA_AHCI
bool "Enable DWC AHSATA AHCI driver support"
depends on DWC_AHSATA
- depends on AHCI
default y
help
Enable this option unless you need your private ahci implementation
+config MTK_AHCI
+ bool "Enable Mediatek AHCI driver support"
+ help
+ Enable this driver to support Sata devices through
+ Mediatek AHCI controller (e.g. MT7622).
+
+config AHCI_MVEBU
+ bool "Marvell EBU AHCI SATA support"
+ depends on ARCH_MVEBU || ARCH_OCTEON
+ select SCSI_AHCI
+ select DM_SCSI
+ help
+ This option enables support for the Marvell EBU SoC's
+ onboard AHCI SATA.
+
+ If unsure, say N.
+
+config SUNXI_AHCI
+ bool "Enable Allwinner SATA driver support"
+ default y if ARCH_SUNXI
+ help
+ Enable this driver to support the SATA controllers found in the
+ Allwinner A10, A20 and R40 SoCs.
+
+endif # AHCI
+
+if SATA
+
+config SATA_CEVA
+ bool "Ceva Sata controller"
+ depends on AHCI
+ depends on DM_SCSI
+ help
+ This option enables Ceva Sata controller hard IP available on Xilinx
+ ZynqMP. Support up to 2 external devices. Compliant with SATA 3.1 and
+ AHCI 1.3 specifications with hot-plug detect feature.
+
config FSL_SATA
bool "Enable Freescale SATA controller driver support"
select AHCI
select LIBATA
- depends on BLK
help
Enable this driver to support the SATA controller found in
some Freescale PowerPC SoCs.
bool "Enable Marvell SATA controller driver support"
select AHCI
select LIBATA
- depends on BLK
help
Enable this driver to support the SATA controller found in
some Marvell SoCs.
bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver support"
select AHCI
select LIBATA
- depends on BLK
help
Enable this driver to support the SIL3131, SIL3132 and SIL3124
SATA controllers.
-config SATA_SIL3114
- bool "Enable Silicon Image SIL3114 SATA driver support"
- select LIBATA
+config SYS_SATA_MAX_DEVICE
+ int "Maximum number of SATA devices"
+ depends on !AHCI || FSL_SATA || SATA_MV
help
- Enable this driver to support the SIL3114 SATA controllers.
+ Sets the maximum number of SATA devices which can be supported
+ by U-Boot.
-config SUNXI_AHCI
- bool "Enable Allwinner SATA driver support"
- depends on AHCI
- default y if ARCH_SUNXI
- help
- Enable this driver to support the SATA controllers found in the
- Allwinner A10, A20 and R40 SoCs.
+ This is only partially converted to driver model. See sata_bread()
+ for example, which shows where the conversion needs to be completed.
-config AHCI_MVEBU
- bool "Marvell EBU AHCI SATA support"
- depends on ARCH_MVEBU || ARCH_OCTEON
- depends on AHCI
- select SCSI_AHCI
- select DM_SCSI
- help
- This option enables support for the Marvell EBU SoC's
- onboard AHCI SATA.
-
- If unsure, say N.
-
-config MTK_AHCI
- bool "Enable Mediatek AHCI driver support"
- depends on AHCI
- help
- Enable this driver to support Sata devices through
- Mediatek AHCI controller (e.g. MT7622).
+endif # SATA
endmenu
obj-$(CONFIG_SATA) += sata.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
-obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_SANDBOX) += sata_sandbox.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
#endif
#endif
-#ifdef CONFIG_BLK
static unsigned long sata_bread(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt, void *dst)
{
{
return -ENOSYS;
}
-#else
-static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt, void *dst)
-{
- return sata_read(block_dev->devnum, start, blkcnt, dst);
-}
-
-static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt, const void *buffer)
-{
- return sata_write(block_dev->devnum, start, blkcnt, buffer);
-}
-#endif
#ifndef CONFIG_AHCI
int __sata_initialize(void)
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].blksz = 512;
sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
-#ifndef CONFIG_BLK
- sata_dev_desc[i].block_read = sata_bread;
- sata_dev_desc[i].block_write = sata_bwrite;
-#endif
rc = init_sata(i);
if (!rc) {
rc = scan_sata(i);
int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
#endif
-#ifdef CONFIG_BLK
static const struct blk_ops sata_blk_ops = {
.read = sata_bread,
.write = sata_bwrite,
.id = UCLASS_BLK,
.ops = &sata_blk_ops,
};
-#else
-U_BOOT_LEGACY_BLK(sata) = {
- .if_typename = "sata",
- .if_type = IF_TYPE_SATA,
- .max_devs = CONFIG_SYS_SATA_MAX_DEVICE,
- .desc = sata_dev_desc,
-};
-#endif
#include <common.h>
#include <dm.h>
#include <ahci.h>
+#include <generic-phy.h>
#include <log.h>
+#include <reset.h>
#include <scsi.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include <linux/ioport.h>
/* Vendor Specific Register Offsets */
static int sata_ceva_probe(struct udevice *dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
+ struct phy phy;
+ int ret;
+ struct reset_ctl_bulk resets;
+
+ ret = generic_phy_get_by_index(dev, 0, &phy);
+ if (!ret) {
+ dev_dbg(dev, "Perform PHY initialization\n");
+ ret = generic_phy_init(&phy);
+ if (ret)
+ return ret;
+ } else if (ret != -ENOENT) {
+ dev_dbg(dev, "could not get phy (err %d)\n", ret);
+ return ret;
+ }
+
+ /* reset is optional */
+ ret = reset_get_bulk(dev, &resets);
+ if (ret && ret != -ENOTSUPP && ret != -ENOENT) {
+ dev_dbg(dev, "Getting reset fails (err %d)\n", ret);
+ return ret;
+ }
+
+ /* Just trigger reset when reset is specified */
+ if (!ret) {
+ dev_dbg(dev, "Perform IP reset\n");
+ ret = reset_deassert_bulk(&resets);
+ if (ret) {
+ dev_dbg(dev, "Reset fails (err %d)\n", ret);
+ reset_release_bulk(&resets);
+ return ret;
+ }
+ }
+
+ if (phy.dev) {
+ dev_dbg(dev, "Perform PHY power on\n");
+ ret = generic_phy_power_on(&phy);
+ if (ret) {
+ dev_dbg(dev, "PHY power on failed (err %d)\n", ret);
+ return ret;
+ }
+ }
ceva_init_sata(priv);
*/
#include <common.h>
+#include <blk.h>
#include <cpu_func.h>
+#include <dm.h>
#include <log.h>
#include <pci.h>
#include <command.h>
#include <sata.h>
#include <libata.h>
#include <sata.h>
-#include <linux/delay.h>
-
-#if CONFIG_IS_ENABLED(BLK)
-#include <dm.h>
-#include <blk.h>
#include <dm/device-internal.h>
-#endif
+#include <linux/delay.h>
#include "sata_sil.h"
/*
* SATA interface between low level driver and command layer
*/
-#if !CONFIG_IS_ENABLED(BLK)
-ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
- struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
-#else
static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
{
struct sil_sata_priv *priv = dev_get_plat(dev);
int port_number = priv->port_num;
struct sil_sata *sata = priv->sil_sata_desc[port_number];
-#endif
ulong rc;
if (sata->lba48)
/*
* SATA interface between low level driver and command layer
*/
-#if !CONFIG_IS_ENABLED(BLK)
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
-{
- struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
-#else
ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer)
{
struct sil_sata_priv *priv = dev_get_plat(dev);
int port_number = priv->port_num;
struct sil_sata *sata = priv->sil_sata_desc[port_number];
-#endif
ulong rc;
if (sata->lba48) {
return rc;
}
-#if !CONFIG_IS_ENABLED(BLK)
-static int sil_init_sata(int dev)
-{
-#else
static int sil_init_sata(struct udevice *uc_dev, int dev)
{
struct sil_sata_priv *priv = dev_get_plat(uc_dev);
-#endif
struct sil_sata *sata;
void *port;
u32 tmp;
memset((void *)sata, 0, sizeof(struct sil_sata));
/* Save the private struct to block device struct */
-#if !CONFIG_IS_ENABLED(BLK)
- sata_dev_desc[dev].priv = (void *)sata;
- sata->devno = sata_info.devno;
-#else
priv->sil_sata_desc[dev] = sata;
priv->port_num = dev;
sata->devno = uc_dev->parent;
-#endif
sata->id = dev;
sata->port = port;
sprintf(sata->name, "SATA#%d", dev);
return 0;
}
-#if !CONFIG_IS_ENABLED(BLK)
-/*
- * SATA interface between low level driver and command layer
- */
-int init_sata(int dev)
-{
- static int init_done, idx;
- pci_dev_t devno;
- u16 word;
-
- if (init_done == 1 && dev < sata_info.maxport)
- goto init_start;
-
- init_done = 1;
-
- /* Find PCI device(s) */
- devno = pci_find_devices(supported, idx++);
- if (devno == -1)
- return 1;
-
- pci_read_config_word(devno, PCI_DEVICE_ID, &word);
-
- /* get the port count */
- word &= 0xf;
-
- sata_info.portbase = 0;
- sata_info.maxport = sata_info.portbase + word;
- sata_info.devno = devno;
-
- /* Read out all BARs */
- sata_info.iobase[0] = (ulong)pci_map_bar(devno,
- PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- sata_info.iobase[1] = (ulong)pci_map_bar(devno,
- PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
-
- /* mask out the unused bits */
- sata_info.iobase[0] &= 0xffffff80;
- sata_info.iobase[1] &= 0xfffffc00;
-
- /* Enable Bus Mastering and memory region */
- pci_write_config_word(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Check if mem accesses and Bus Mastering are enabled. */
- pci_read_config_word(devno, PCI_COMMAND, &word);
- if (!(word & PCI_COMMAND_MEMORY) ||
- (!(word & PCI_COMMAND_MASTER))) {
- printf("Error: Can not enable MEM access or Bus Mastering.\n");
- debug("PCI command: %04x\n", word);
- return 1;
- }
-
- /* GPIO off */
- writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
- /* clear global reset & mask interrupts during initialization */
- writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
-
-init_start:
- return sil_init_sata(dev);
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-/*
- * SATA interface between low level driver and command layer
- */
-int scan_sata(int dev)
-{
- struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
-#else
static int scan_sata(struct udevice *blk_dev, int dev)
{
struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
struct sil_sata_priv *priv = dev_get_plat(blk_dev);
struct sil_sata *sata = priv->sil_sata_desc[dev];
-#endif
unsigned char serial[ATA_ID_SERNO_LEN + 1];
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
unsigned char product[ATA_ID_PROD_LEN + 1];
/* Product model */
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
-#if !CONFIG_IS_ENABLED(BLK)
- memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
- memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
- memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
- /* Totoal sectors */
- sata_dev_desc[dev].lba = ata_id_n_sectors(id);
-#ifdef CONFIG_LBA48
- sata_dev_desc[dev].lba48 = sata->lba48;
-#endif
-#else
memcpy(desc->product, serial, sizeof(serial));
memcpy(desc->revision, firmware, sizeof(firmware));
memcpy(desc->vendor, product, sizeof(product));
#ifdef CONFIG_LBA48
desc->lba48 = sata->lba48;
#endif
-#endif
#ifdef DEBUG
ata_dump_id(id);
return 0;
}
-#if CONFIG_IS_ENABLED(BLK)
static const struct blk_ops sata_sil_blk_ops = {
.read = sata_read,
.write = sata_write,
};
U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
- * Author: Tor Krill <tor@excito.com>
- *
- * This is a driver for Silicon Image sil3114 sata chip modelled on
- * the ata_piix driver
- */
-
-#include <common.h>
-#include <blk.h>
-#include <log.h>
-#include <part.h>
-#include <pci.h>
-#include <command.h>
-#include <config.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <ide.h>
-#include <sata.h>
-#include <libata.h>
-#include <linux/delay.h>
-#include "sata_sil3114.h"
-
-/* Convert sectorsize to wordsize */
-#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
-
-/* Forwards */
-u8 sil3114_spin_up (int num);
-u8 sil3114_spin_down (int num);
-static int sata_bus_softreset (int num);
-static void sata_identify (int num, int dev);
-static u8 check_power_mode (int num);
-static void sata_port (struct sata_ioports *ioport);
-static void set_Feature_cmd (int num, int dev);
-static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
- unsigned int max, u8 usealtstatus);
-static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
-static void msleep (int count);
-
-static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
-
-static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
-
-static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
-{
- while (words--) {
- __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
- }
-}
-
-static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
-{
- while (words--) {
- *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
- }
- return 0;
-}
-
-static int sata_bus_softreset (int num)
-{
- u8 status = 0;
-
- port[num].dev_mask = 1;
-
- port[num].ctl_reg = 0x08; /*Default value of control reg */
- writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- udelay(10);
- writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
- udelay(10);
- writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
-
- /* spec mandates ">= 2ms" before checking status.
- * We wait 150ms, because that was the magic delay used for
- * ATAPI devices in Hale Landis's ATADRVR, for the period of time
- * between when the ATA command register is written, and then
- * status is checked. Because waiting for "a while" before
- * checking status is fine, post SRST, we perform this magic
- * delay here as well.
- */
- msleep (150);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
- while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
- }
-
- if (status & ATA_BUSY) {
- printf ("ata%u is slow to respond,plz be patient\n", num);
- }
-
- while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_chk_status (&port[num].ioaddr, 0);
- }
-
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond : ", num);
- printf ("bus reset failed\n");
- port[num].dev_mask = 0;
- return 1;
- }
- return 0;
-}
-
-static void sata_identify (int num, int dev)
-{
- u8 cmd = 0, status = 0, devno = num;
- u16 iobuf[ATA_SECTOR_WORDS];
- u64 n_sectors = 0;
-
- memset (iobuf, 0, sizeof (iobuf));
-
- if (!(port[num].dev_mask & 0x01)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
- return;
- }
-
- debug ("port=%d dev=%d\n", num, dev);
-
- status = 0;
- cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
- writeb (cmd, port[num].ioaddr.command_addr);
- readb (port[num].ioaddr.altstatus_addr);
- udelay(10);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
- if (status & ATA_ERR) {
- printf ("\ndevice not responding\n");
- port[num].dev_mask &= ~0x01;
- return;
- }
-
- input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
-
- ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
-
- debug ("Specific config: %x\n", iobuf[2]);
-
- /* we require LBA and DMA support (bits 8 & 9 of word 49) */
- if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
- debug ("ata%u: no dma/lba\n", num);
- }
-#ifdef DEBUG
- ata_dump_id (iobuf);
-#endif
- n_sectors = ata_id_n_sectors (iobuf);
-
- if (n_sectors == 0) {
- port[num].dev_mask &= ~0x01;
- return;
- }
- ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
- ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
- ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
- ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
- ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
- ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
-
- /* TODO - atm we asume harddisk ie not removable */
- sata_dev_desc[devno].removable = 0;
-
- sata_dev_desc[devno].lba = (u32) n_sectors;
- debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
-
-#ifdef CONFIG_LBA48
- if (iobuf[83] & (1 << 10)) {
- sata_dev_desc[devno].lba48 = 1;
- } else {
- sata_dev_desc[devno].lba48 = 0;
- }
-#endif
-
- /* assuming HD */
- sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
- sata_dev_desc[devno].lun = 0; /* just to fill something in... */
-}
-
-static void set_Feature_cmd (int num, int dev)
-{
- u8 status = 0;
-
- if (!(port[num].dev_mask & 0x01)) {
- debug ("dev%d is not present on port#%d\n", dev, num);
- return;
- }
-
- writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
- writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
- writeb (0, port[num].ioaddr.lbal_addr);
- writeb (0, port[num].ioaddr.lbam_addr);
- writeb (0, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
-
- udelay(50);
- msleep (150);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf ("Error : status 0x%02x\n", status);
- port[num].dev_mask &= ~0x01;
- }
-}
-
-u8 sil3114_spin_down (int num)
-{
- u8 status = 0;
-
- debug ("Spin down disk\n");
-
- if (!(port[num].dev_mask & 0x01)) {
- debug ("Device ata%d is not present\n", num);
- return 1;
- }
-
- if ((status = check_power_mode (num)) == 0x00) {
- debug ("Already in standby\n");
- return 0;
- }
-
- if (status == 0x01) {
- printf ("Failed to check power mode on ata%d\n", num);
- return 1;
- }
-
- if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", num);
- return 1;
- }
-
- writeb (0x00, port[num].ioaddr.feature_addr);
-
- writeb (0x00, port[num].ioaddr.nsect_addr);
- writeb (0x00, port[num].ioaddr.lbal_addr);
- writeb (0x00, port[num].ioaddr.lbam_addr);
- writeb (0x00, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf ("Error waiting for disk spin down: status 0x%02x\n",
- status);
- port[num].dev_mask &= ~0x01;
- return 1;
- }
- return 0;
-}
-
-u8 sil3114_spin_up (int num)
-{
- u8 status = 0;
-
- debug ("Spin up disk\n");
-
- if (!(port[num].dev_mask & 0x01)) {
- debug ("Device ata%d is not present\n", num);
- return 1;
- }
-
- if ((status = check_power_mode (num)) != 0x00) {
- if (status == 0x01) {
- printf ("Failed to check power mode on ata%d\n", num);
- return 1;
- } else {
- /* should be up and running already */
- return 0;
- }
- }
-
- if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", num);
- return 1;
- }
-
- debug ("Stautus of device check: %d\n", status);
-
- writeb (0x00, port[num].ioaddr.feature_addr);
-
- writeb (0x00, port[num].ioaddr.nsect_addr);
- writeb (0x00, port[num].ioaddr.lbal_addr);
- writeb (0x00, port[num].ioaddr.lbam_addr);
- writeb (0x00, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf ("Error waiting for disk spin up: status 0x%02x\n",
- status);
- port[num].dev_mask &= ~0x01;
- return 1;
- }
-
- /* Wait for disk to enter Active state */
- do {
- msleep (10);
- status = check_power_mode (num);
- } while ((status == 0x00) || (status == 0x80));
-
- if (status == 0x01) {
- printf ("Falied waiting for disk to spin up\n");
- return 1;
- }
-
- return 0;
-}
-
-/* Return value is not the usual here
- * 0x00 - Device stand by
- * 0x01 - Operation failed
- * 0x80 - Device idle
- * 0xff - Device active
-*/
-static u8 check_power_mode (int num)
-{
- u8 status = 0;
- u8 res = 0;
- if (!(port[num].dev_mask & 0x01)) {
- debug ("Device ata%d is not present\n", num);
- return 1;
- }
-
- if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", num);
- return 1;
- }
-
- writeb (0, port[num].ioaddr.feature_addr);
- writeb (0, port[num].ioaddr.nsect_addr);
- writeb (0, port[num].ioaddr.lbal_addr);
- writeb (0, port[num].ioaddr.lbam_addr);
- writeb (0, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf
- ("Error waiting for check power mode complete : status 0x%02x\n",
- status);
- port[num].dev_mask &= ~0x01;
- return 1;
- }
- res = readb (port[num].ioaddr.nsect_addr);
- debug ("Check powermode: %d\n", res);
- return res;
-
-}
-
-static void sata_port (struct sata_ioports *ioport)
-{
- ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
- ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
- ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
- ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
- ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
- ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
- ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
- ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
- ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
- ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
-}
-
-static u8 wait_for_irq (int num, unsigned int max)
-{
-
- u32 port = iobase[5];
- switch (num) {
- case 0:
- port += VND_TF_CNST_CH0;
- break;
- case 1:
- port += VND_TF_CNST_CH1;
- break;
- case 2:
- port += VND_TF_CNST_CH2;
- break;
- case 3:
- port += VND_TF_CNST_CH3;
- break;
- default:
- return 1;
- }
-
- do {
- if (readl (port) & VND_TF_CNST_INTST) {
- break;
- }
- udelay(1000);
- max--;
- } while ((max > 0));
-
- return (max == 0);
-}
-
-static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
- unsigned int max, u8 usealtstatus)
-{
- u8 status;
-
- do {
- if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
- break;
- }
- udelay(1000);
- max--;
- } while ((status & bits) && (max > 0));
-
- return status;
-}
-
-static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
-{
- if (!usealtstatus) {
- return readb (ioaddr->status_addr);
- } else {
- return readb (ioaddr->altstatus_addr);
- }
-}
-
-static void msleep (int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- udelay(1000);
-}
-
-/* Read up to 255 sectors
- *
- * Returns sectors read
-*/
-static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
- uchar lba48)
-{
-
- u8 sr = 0;
- u8 status;
- u64 blknr = (u64) block;
-
- if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", device);
- return 0;
- }
-
- /* Set up transfer */
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- writeb (0, port[device].ioaddr.nsect_addr);
- writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
- writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
- writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
- }
-#endif
- writeb (blkcnt, port[device].ioaddr.nsect_addr);
- writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
- writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
- writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- writeb (ATA_LBA, port[device].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
- } else
-#endif
- {
- writeb (ATA_LBA | ((blknr >> 24) & 0xF),
- port[device].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
- }
-
- status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
-
- if (status & ATA_BUSY) {
- u8 err = 0;
-
- printf ("Device %d not responding status %d\n", device, status);
- err = readb (port[device].ioaddr.error_addr);
- printf ("Error reg = 0x%x\n", err);
-
- return (sr);
- }
- while (blkcnt--) {
-
- if (wait_for_irq (device, 500)) {
- printf ("ata%u irq failed\n", device);
- return sr;
- }
-
- status = sata_chk_status (&port[device].ioaddr, 0);
- if (status & ATA_ERR) {
- printf ("ata%u error %d\n", device,
- readb (port[device].ioaddr.error_addr));
- return sr;
- }
- /* Read one sector */
- input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
- buff += ATA_SECTOR_WORDS;
- sr++;
-
- }
- return sr;
-}
-
-ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
-{
- ulong n = 0, sread;
- u16 *buffer = (u16 *) buff;
- u8 status = 0;
- u64 blknr = (u64) block;
- unsigned char lba48 = 0;
-
-#ifdef CONFIG_LBA48
- if (blknr > 0xfffffff) {
- if (!sata_dev_desc[device].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
-
- while (blkcnt > 0) {
-
- if (blkcnt > 255) {
- sread = 255;
- } else {
- sread = blkcnt;
- }
-
- status = do_one_read (device, blknr, sread, buffer, lba48);
- if (status != sread) {
- printf ("Read failed\n");
- return n;
- }
-
- blkcnt -= sread;
- blknr += sread;
- n += sread;
- buffer += sread * ATA_SECTOR_WORDS;
- }
- return n;
-}
-
-ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
-{
- ulong n = 0;
- u16 *buffer = (u16 *) buff;
- unsigned char status = 0, num = 0;
- u64 blknr = (u64) block;
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr > 0xfffffff) {
- if (!sata_dev_desc[device].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
- /*Port Number */
- num = device;
-
- while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
- return n;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- writeb (0, port[num].ioaddr.nsect_addr);
- writeb ((blknr >> 24) & 0xFF,
- port[num].ioaddr.lbal_addr);
- writeb ((blknr >> 32) & 0xFF,
- port[num].ioaddr.lbam_addr);
- writeb ((blknr >> 40) & 0xFF,
- port[num].ioaddr.lbah_addr);
- }
-#endif
- writeb (1, port[num].ioaddr.nsect_addr);
- writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
- writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
-#ifdef CONFIG_LBA48
- if (lba48) {
- writeb (ATA_LBA, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
- } else
-#endif
- {
- writeb (ATA_LBA | ((blknr >> 24) & 0xF),
- port[num].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
- }
-
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
- if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
- device, (ulong) blknr, status);
- return (n);
- }
-
- output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
- readb (port[num].ioaddr.altstatus_addr);
- udelay(50);
-
- ++n;
- ++blknr;
- buffer += ATA_SECTOR_WORDS;
- }
- return n;
-}
-
-/* Driver implementation */
-static u8 sil_get_device_cache_line (pci_dev_t pdev)
-{
- u8 cache_line = 0;
- pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
- return cache_line;
-}
-
-int init_sata (int dev)
-{
- static u8 init_done = 0;
- static int res = 1;
- pci_dev_t devno;
- u8 cls = 0;
- u16 cmd = 0;
- u32 sconf = 0;
-
- if (init_done) {
- return res;
- }
-
- init_done = 1;
-
- if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
- res = 1;
- return res;
- }
-
- /* Read out all BARs, even though we only use MMIO from BAR5 */
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
-
- if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
- (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
- (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
- printf ("Error no base addr for SATA controller\n");
- res = 1;
- return res;
- }
-
- /* mask off unused bits */
- iobase[0] &= 0xfffffffc;
- iobase[1] &= 0xfffffff8;
- iobase[2] &= 0xfffffffc;
- iobase[3] &= 0xfffffff8;
- iobase[4] &= 0xfffffff0;
- iobase[5] &= 0xfffffc00;
-
- /* from sata_sil in Linux kernel */
- cls = sil_get_device_cache_line (devno);
- if (cls) {
- cls >>= 3;
- cls++; /* cls = (line_size/8)+1 */
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
- } else {
- printf ("Cache line not set. Driver may not function\n");
- }
-
- /* Enable operation */
- pci_read_config_word (devno, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
- pci_write_config_word (devno, PCI_COMMAND, cmd);
-
- /* Disable interrupt usage */
- pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
- sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
- pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
-
- res = 0;
- return res;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-/* Check if device is connected to port */
-int sata_bus_probe (int portno)
-{
- u32 port = iobase[5];
- u32 val;
- switch (portno) {
- case 0:
- port += VND_SSTATUS_CH0;
- break;
- case 1:
- port += VND_SSTATUS_CH1;
- break;
- case 2:
- port += VND_SSTATUS_CH2;
- break;
- case 3:
- port += VND_SSTATUS_CH3;
- break;
- default:
- return 0;
- }
- val = readl (port);
- if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
- return 1;
- } else {
- return 0;
- }
-}
-
-int sata_phy_reset (int portno)
-{
- u32 port = iobase[5];
- u32 val;
- switch (portno) {
- case 0:
- port += VND_SCONTROL_CH0;
- break;
- case 1:
- port += VND_SCONTROL_CH1;
- break;
- case 2:
- port += VND_SCONTROL_CH2;
- break;
- case 3:
- port += VND_SCONTROL_CH3;
- break;
- default:
- return 0;
- }
- val = readl (port);
- writel (val | SATA_SC_DET_RST, port);
- msleep (150);
- writel (val & ~SATA_SC_DET_RST, port);
- return 0;
-}
-
-int scan_sata (int dev)
-{
- /* A bit brain dead, but the code has a legacy */
- switch (dev) {
- case 0:
- port[0].port_no = 0;
- port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
- port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
- port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
- break;
-#if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
- case 1:
- port[1].port_no = 0;
- port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
- port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
- port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
- break;
-#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
- case 2:
- port[2].port_no = 0;
- port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
- port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
- port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
- break;
-#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
- case 3:
- port[3].port_no = 0;
- port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
- port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
- port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
- break;
-#endif
- default:
- printf ("Tried to scan unknown port: ata%d\n", dev);
- return 1;
- }
-
- /* Initialize other registers */
- sata_port (&port[dev].ioaddr);
-
- /* Check for attached device */
- if (!sata_bus_probe (dev)) {
- port[dev].port_state = 0;
- debug ("SATA#%d port is not present\n", dev);
- } else {
- debug ("SATA#%d port is present\n", dev);
- if (sata_bus_softreset (dev)) {
- /* soft reset failed, try a hard one */
- sata_phy_reset (dev);
- if (sata_bus_softreset (dev)) {
- port[dev].port_state = 0;
- } else {
- port[dev].port_state = 1;
- }
- } else {
- port[dev].port_state = 1;
- }
- }
- if (port[dev].port_state == 1) {
- /* Probe device and set xfer mode */
- sata_identify (dev, 0);
- set_Feature_cmd (dev, 0);
- }
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
- * Author: Tor Krill <tor@excito.com>
- */
-
-#ifndef SATA_SIL3114_H
-#define SATA_SIL3114_H
-
-struct sata_ioports {
- unsigned long cmd_addr;
- unsigned long data_addr;
- unsigned long error_addr;
- unsigned long feature_addr;
- unsigned long nsect_addr;
- unsigned long lbal_addr;
- unsigned long lbam_addr;
- unsigned long lbah_addr;
- unsigned long device_addr;
- unsigned long status_addr;
- unsigned long command_addr;
- unsigned long altstatus_addr;
- unsigned long ctl_addr;
- unsigned long bmdma_addr;
- unsigned long scr_addr;
-};
-
-struct sata_port {
- unsigned char port_no; /* primary=0, secondary=1 */
- struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
- unsigned char ctl_reg;
- unsigned char last_ctl;
- unsigned char port_state; /* 1-port is available and */
- /* 0-port is not available */
- unsigned char dev_mask;
-};
-
-/* Missing ata defines */
-#define ATA_CMD_STANDBY 0xE2
-#define ATA_CMD_STANDBYNOW1 0xE0
-#define ATA_CMD_IDLE 0xE3
-#define ATA_CMD_IDLEIMMEDIATE 0xE1
-
-/* Defines for SIL3114 chip */
-
-/* PCI defines */
-#define SIL_VEND_ID 0x1095
-#define SIL3114_DEVICE_ID 0x3114
-
-/* some vendor specific registers */
-#define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */
-#define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22)
-#define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23)
-#define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24)
-#define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25)
-
-/* internal registers mapped by BAR5 */
-/* SATA Control*/
-#define VND_SCONTROL_CH0 0x100
-#define VND_SCONTROL_CH1 0x180
-#define VND_SCONTROL_CH2 0x300
-#define VND_SCONTROL_CH3 0x380
-
-#define SATA_SC_IPM_T2P (1<<16)
-#define SATA_SC_IPM_T2S (2<<16)
-#define SATA_SC_SPD_1_5 (1<<4)
-#define SATA_SC_SPD_3_0 (2<<4)
-#define SATA_SC_DET_RST (1) /* ATA Reset sequence */
-#define SATA_SC_DET_PDIS (4) /* PHY Disable */
-
-/* SATA Status */
-#define VND_SSTATUS_CH0 0x104
-#define VND_SSTATUS_CH1 0x184
-#define VND_SSTATUS_CH2 0x304
-#define VND_SSTATUS_CH3 0x384
-
-#define SATA_SS_IPM_ACTIVE (1<<8)
-#define SATA_SS_IPM_PARTIAL (2<<8)
-#define SATA_SS_IPM_SLUMBER (6<<8)
-#define SATA_SS_SPD_1_5 (1<<4)
-#define SATA_SS_SPD_3_0 (2<<4)
-#define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */
-#define SATA_DET_PRES (3) /* Device presence and active PHY */
-#define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */
-
-/* Task file registers in BAR5 mapping */
-#define VND_TF0_CH0 0x80
-#define VND_TF0_CH1 0xc0
-#define VND_TF0_CH2 0x280
-#define VND_TF0_CH3 0x2c0
-#define VND_TF1_CH0 0x88
-#define VND_TF1_CH1 0xc8
-#define VND_TF1_CH2 0x288
-#define VND_TF1_CH3 0x2c8
-#define VND_TF2_CH0 0x88
-#define VND_TF2_CH1 0xc8
-#define VND_TF2_CH2 0x288
-#define VND_TF2_CH3 0x2c8
-
-#define VND_BMDMA_CH0 0x00
-#define VND_BMDMA_CH1 0x08
-#define VND_BMDMA_CH2 0x200
-#define VND_BMDMA_CH3 0x208
-#define VND_BMDMA2_CH0 0x10
-#define VND_BMDMA2_CH1 0x18
-#define VND_BMDMA2_CH2 0x210
-#define VND_BMDMA2_CH3 0x218
-
-/* FIFO control */
-#define VND_FIFOCFG_CH0 0x40
-#define VND_FIFOCFG_CH1 0x44
-#define VND_FIFOCFG_CH2 0x240
-#define VND_FIFOCFG_CH3 0x244
-
-/* Task File configuration and status */
-#define VND_TF_CNST_CH0 0xa0
-#define VND_TF_CNST_CH1 0xe0
-#define VND_TF_CNST_CH2 0x2a0
-#define VND_TF_CNST_CH3 0x2e0
-
-#define VND_TF_CNST_BFCMD (1<<1)
-#define VND_TF_CNST_CHNRST (1<<2)
-#define VND_TF_CNST_VDMA (1<<10)
-#define VND_TF_CNST_INTST (1<<11)
-#define VND_TF_CNST_WDTO (1<<12)
-#define VND_TF_CNST_WDEN (1<<13)
-#define VND_TF_CNST_WDIEN (1<<14)
-
-/* for testing */
-#define VND_SSDR 0x04c /* System Software Data Register */
-#define VND_FMACS 0x050 /* Flash Memory Address control and status */
-
-#endif
This allows access to raw blocks and filesystems on an IDE drive
from U-Boot. See also CMD_IDE which provides an 'ide' command for
performing various IDE operations.
+
+if IDE
+
+config SYS_IDE_MAXBUS
+ hex "Maximumm number of IDE buses"
+ default 2
+ help
+ This is the number of IDE buses provided by the board. Each one
+ can have one or two devices. One is designated the master and the
+ other one the slave. It is not required to have one or both on any
+ controller.
+
+config SYS_IDE_MAXDEVICE
+ hex "Maximum number of IDE devices"
+ default 2
+ help
+ This is the number of IDE devices which can be connected to the
+ board. Normally this is 2 * CONFIG_SYS_IDE_MAXBUS since up to two
+ devices can be connected to each bus. The number of devices actually
+ connected is determined by probing.
+
+config SYS_ATA_BASE_ADDR
+ hex "Base address of IDE controller"
+ default 0
+ help
+ This is the address of the IDE controller, from which other addresses
+ are calculated. Each bus is at a fixed offset from this address,
+ so it assumed that they are in the same area of the I/O space or
+ memory.
+
+config SYS_ATA_STRIDE
+ hex "IDE port stride"
+ default 0x1
+ help
+ This is the distance between each IDE register, in bytes. For an
+ 8-bit controller this is typically 1, meaning that the registers
+ appear at consecutive bytes. If the value 2 two, that might indicate
+ a 16-bit register space.
+
+config SYS_ATA_DATA_OFFSET
+ hex "Offset of the data register"
+ default 0x0
+ help
+ This is the offset of the controller's data register from the base
+ address of the controller. This is typically 0, but may be something
+ else if there are some other registers at the start of the
+ controller space.
+
+config SYS_ATA_REG_OFFSET
+ hex "Offset of the register space"
+ default 0x0
+ help
+ This is the offset of the controller's 'register' space from the base
+ address of the controller. The data register (which is typically at
+ offset 0) has its own CONFIG, to deal with controllers where it is
+ somewhere else. Register 1 will be at this offset + 1, register 2 at
+ CONFIG_SYS_ATA_REG_OFFSET + 2, etc.
+
+config SYS_ATA_ALT_OFFSET
+ hex "Offset of the alternative registers"
+ default 0x0
+ help
+ This is the offset of the controller's 'alternative' space from the
+ base address of the controller. This allows these registers to be
+ located separately from the data and register space.
+
+config SYS_ATA_IDE0_OFFSET
+ hex "Offset of bus 0"
+ default 0x1f0
+ help
+ This is the start offset of bus 0 from the start of the
+ controller registers. All the other registers are calculated from
+ this address. using the above options. For x86 hardware this is often
+ 0x1f0.
+
+config SYS_ATA_IDE1_OFFSET
+ hex "Offset of bus 1"
+ default 0x170
+ help
+ This is the start offset of bus 1 from the start of the
+ controller registers. All the other registers are calculated from
+ this address. using the above options. For x86 hardware this is often
+ 0x170.
+
+config ATAPI
+ bool "Enable ATAPI support"
+ help
+ This enabled Advanced Technology Attachment Packet Interface (ATAPI),
+ a protocol that allows a greater variety of devices to be connected
+ to the IDE port than with plain ATA. It allows SCSI commands to be
+ sent across the bus, e.g. to support optical drives.
+
+config IDE_RESET
+ bool "Support board-specific reset"
+ help
+ If this is defined, IDE Reset will be performed by calling the
+ function:
+
+ ide_set_reset(int reset)
+
+ where reset is 1 to assert reset and 0 to de-assert it. This function
+ must be defined in a board-specific file.
+
+endif # IDE
debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
dev, port, val, ATA_CURR_BASE(dev) + port);
-#if defined(CONFIG_IDE_AHB)
- if (port) {
- /* write command */
- ide_write_register(dev, port, val);
- } else {
- /* write data */
- outb(val, (ATA_CURR_BASE(dev)));
- }
-#else
outb(val, ATA_CURR_BASE(dev) + port);
-#endif
}
__weak unsigned char ide_inb(int dev, int port)
{
uchar val;
-#if defined(CONFIG_IDE_AHB)
- val = ide_read_register(dev, port);
-#else
val = inb(ATA_CURR_BASE(dev) + port);
-#endif
debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
dev, port, ATA_CURR_BASE(dev) + port, val);
__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
{
-#if defined(CONFIG_IDE_AHB)
- ide_write_data(dev, sect_buf, words);
-#else
uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf;
EIEIO;
outw(cpu_to_le16(*dbuf++), paddr);
}
-#endif /* CONFIG_IDE_AHB */
}
__weak void ide_input_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_IDE_AHB)
- ide_read_data(dev, sect_buf, words);
-#else
uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf;
EIEIO;
*dbuf++ = le16_to_cpu(inw(paddr));
}
-#endif /* CONFIG_IDE_AHB */
}
#ifdef CONFIG_BLK
struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct button_adc_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
- u32 threshold, up_threshold, t;
+ u32 down_threshold = 0, up_threshold, voltage, t;
ofnode node;
int ret;
return ret;
ret = ofnode_read_u32(dev_ofnode(dev), "press-threshold-microvolt",
- &threshold);
+ &voltage);
if (ret)
return ret;
if (ret)
return ret;
- if (t > threshold)
+ if (t > voltage && t < up_threshold)
up_threshold = t;
+ else if (t < voltage && t > down_threshold)
+ down_threshold = t;
}
priv->channel = args.args[0];
- priv->min = threshold;
- priv->max = up_threshold;
+
+ /*
+ * Define the voltage range such that the button is only pressed
+ * when the voltage is closest to its own press-threshold-microvolt
+ */
+ if (down_threshold == 0)
+ priv->min = 0;
+ else
+ priv->min = down_threshold + (voltage - down_threshold) / 2;
+
+ priv->max = voltage + (up_threshold - voltage) / 2;
return ret;
}
setting up clocks within TPL, and allows the same drivers to be
used as U-Boot proper.
-config CLK_BCM6345
- bool "Clock controller driver for BCM6345"
- depends on CLK && ARCH_BMIPS
- default y
- help
- This clock driver adds support for enabling and disabling peripheral
- clocks on BCM6345 SoCs. HW has no rate changing capabilities.
-
-config CLK_BOSTON
- def_bool y if TARGET_BOSTON
- depends on CLK
- select REGMAP
- select SYSCON
- help
- Enable this to support the clocks
-
config SPL_CLK_CCF
bool "SPL Common Clock Framework [CCF] support "
depends on SPL
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] composite code in U-Boot's clock driver.
+config CLK_BCM6345
+ bool "Clock controller driver for BCM6345"
+ depends on CLK && ARCH_BMIPS
+ default y
+ help
+ This clock driver adds support for enabling and disabling peripheral
+ clocks on BCM6345 SoCs. HW has no rate changing capabilities.
+
+config CLK_BOSTON
+ def_bool y if TARGET_BOSTON
+ depends on CLK
+ select REGMAP
+ select SYSCON
+ help
+ Enable this to support the clocks
+
+config CLK_CDCE9XX
+ bool "Enable CDCD9XX clock driver"
+ depends on CLK
+ help
+ Enable the clock synthesizer driver for CDCE913/925/937/949
+ series of chips.
+
+config CLK_ICS8N3QV01
+ bool "Enable ICS8N3QV01 VCXO driver"
+ depends on CLK
+ help
+ Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
+ Crystal Oscillator). The output frequency can be programmed via an
+ I2C interface.
+
config CLK_INTEL
bool "Enable clock driver for Intel x86"
depends on CLK && X86
set up by U-Boot itself but only statically. Thus the driver does not
support changing clock rates, only querying them.
+config CLK_K210
+ bool "Clock support for Kendryte K210"
+ depends on CLK
+ help
+ This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+ bool "Enable setting the Kendryte K210 PLL rate"
+ depends on CLK_K210
+ help
+ Add functionality to calculate new rates for K210 PLLs. Enabling this
+ feature adds around 1K to U-Boot's final size.
+
+config CLK_MPC83XX
+ bool "Enable MPC83xx clock driver"
+ depends on CLK
+ help
+ Support for the clock driver of the MPC83xx series of SoCs.
+
config CLK_OCTEON
bool "Clock controller driver for Marvell MIPS Octeon"
depends on CLK && ARCH_OCTEON
help
Enable this to support the clocks on Octeon MIPS platforms.
+config SANDBOX_CLK_CCF
+ bool "Sandbox Common Clock Framework [CCF] support "
+ depends on SANDBOX
+ select CLK_CCF
+ help
+ Enable this option if you want to test the Linux kernel's Common
+ Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
+
+config CLK_SCMI
+ bool "Enable SCMI clock driver"
+ depends on SCMI_FIRMWARE
+ help
+ Enable this option if you want to support clock devices exposed
+ by a SCMI agent based on SCMI clock protocol communication
+ with a SCMI server.
+
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
+config CLK_STM32MP1
+ bool "Enable RCC clock driver for STM32MP1"
+ depends on ARCH_STM32MP && CLK
+ default y
+ help
+ Enable the STM32 clock (RCC) driver. Enable support for
+ manipulating STM32MP1's on-SoC clocks.
+
config CLK_HSDK
bool "Enable cgu clock driver for HSDK boards"
depends on CLK && TARGET_HSDK
Enable this to support the cgu clocks on Synopsys ARC HSDK and
Synopsys ARC HSDK-4xD boards
+config CLK_VERSACLOCK
+ tristate "Enable VersaClock 5/6 devices"
+ depends on CLK
+ depends on CLK_CCF
+ depends on OF_CONTROL
+ help
+ This driver supports the IDT VersaClock 5 and VersaClock 6
+ programmable clock generators.
+
config CLK_VERSAL
bool "Enable clock driver support for Versal"
depends on ARCH_VERSAL
This clock driver adds support for clock generators present on
Arm Versatile Express platforms.
-config CLK_ZYNQ
- bool "Enable clock driver support for Zynq"
- depends on CLK && ARCH_ZYNQ
- default y
- help
- This clock driver adds support for clock related settings for
- Zynq platform.
-
config CLK_XLNX_CLKWZRD
bool "Xilinx Clocking Wizard"
depends on CLK
set_duty_cycle API, this driver only supports set_rate to modify
the frequency.
+config CLK_ZYNQ
+ bool "Enable clock driver support for Zynq"
+ depends on CLK && ARCH_ZYNQ
+ default y
+ help
+ This clock driver adds support for clock related settings for
+ Zynq platform.
+
config CLK_ZYNQMP
bool "Enable clock driver support for ZynqMP"
depends on ARCH_ZYNQMP
This clock driver adds support for clock realted settings for
ZynqMP platform.
-config CLK_STM32MP1
- bool "Enable RCC clock driver for STM32MP1"
- depends on ARCH_STM32MP && CLK
- default y
- help
- Enable the STM32 clock (RCC) driver. Enable support for
- manipulating STM32MP1's on-SoC clocks.
-
-config CLK_CDCE9XX
- bool "Enable CDCD9XX clock driver"
- depends on CLK
- help
- Enable the clock synthesizer driver for CDCE913/925/937/949
- series of chips.
-
-config CLK_SCMI
- bool "Enable SCMI clock driver"
- depends on SCMI_FIRMWARE
- help
- Enable this option if you want to support clock devices exposed
- by a SCMI agent based on SCMI clock protocol communication
- with a SCMI server.
-
-config CLK_K210
- bool "Clock support for Kendryte K210"
- depends on CLK
- help
- This enables support clock driver for Kendryte K210 platforms.
-
-config CLK_K210_SET_RATE
- bool "Enable setting the Kendryte K210 PLL rate"
- depends on CLK_K210
- help
- Add functionality to calculate new rates for K210 PLLs. Enabling this
- feature adds around 1K to U-Boot's final size.
-
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"
-config ICS8N3QV01
- bool "Enable ICS8N3QV01 VCXO driver"
- depends on CLK
- help
- Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
- Crystal Oscillator). The output frequency can be programmed via an
- I2C interface.
-
-config CLK_MPC83XX
- bool "Enable MPC83xx clock driver"
- depends on CLK
- help
- Support for the clock driver of the MPC83xx series of SoCs.
-
-config SANDBOX_CLK_CCF
- bool "Sandbox Common Clock Framework [CCF] support "
- depends on SANDBOX
- select CLK_CCF
- help
- Enable this option if you want to test the Linux kernel's Common
- Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
-
-config CLK_VERSACLOCK
- tristate "Enable VersaClock 5/6 devices"
- depends on CLK
- depends on CLK_CCF
- depends on OF_CONTROL
- help
- This driver supports the IDT VersaClock 5 and VersaClock 6
- programmable clock generators.
-
endmenu
obj-y += imx/
obj-y += tegra/
obj-y += ti/
+obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
-obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_MESON) += meson/
+obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_AT91) += at91/
-obj-$(CONFIG_CLK_MVEBU) += mvebu/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
+obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
-obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += clk_kendryte.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_MPFS) += microchip/
+obj-$(CONFIG_CLK_MVEBU) += mvebu/
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
+obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
+obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
-obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
-obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
+obj-$(CONFIG_CLK_ICS8N3QV01) += ics8n3qv01.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
-obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
-obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
-obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
return ret;
}
-static int cdce9xx_clk_of_xlate(struct clk *clk,
- struct ofnode_phandle_args *args)
+static int cdce9xx_clk_request(struct clk *clk)
{
struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
- if (args->args_count != 1)
+ if (clk->id > data->chip->num_outputs)
return -EINVAL;
- if (args->args[0] > data->chip->num_outputs)
- return -EINVAL;
-
- clk->id = args->args[0];
-
return 0;
}
};
static const struct clk_ops cdce9xx_clk_ops = {
- .of_xlate = cdce9xx_clk_of_xlate,
+ .request = cdce9xx_clk_request,
.get_rate = cdce9xx_clk_get_rate,
.set_rate = cdce9xx_clk_set_rate,
};
return clk_get_by_index_nodev(node, index, clk);
}
-int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
-{
- int ret;
-
- ret = clk_get_by_name_nodev(node, name, clk);
- if (ret == -ENODATA)
- return 0;
-
- return ret;
-}
-
int clk_release_all(struct clk *clk, int count)
{
int i, ret;
return 0;
}
if (clkp->dev->parent &&
- device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
+ device_get_uclass_id(clkp->dev->parent) == UCLASS_CLK) {
ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
if (ret) {
printf("Enable %s failed\n",
}
if (clkp && clkp->dev->parent &&
- device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
+ device_get_uclass_id(clkp->dev->parent) == UCLASS_CLK) {
ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
if (ret) {
printf("Disable %s failed\n",
return clk;
}
-struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
-{
- struct clk *clk = devm_clk_get(dev, id);
-
- if (PTR_ERR(clk) == -ENODATA)
- return NULL;
-
- return clk;
-}
-
void devm_clk_put(struct udevice *dev, struct clk *clk)
{
int rc;
return vc5_update_bits(vc->i2c, VC5_OUT_DIV_CONTROL(num), mask, src);
}
-/*
- * The device references to the Versaclock point to the head, so xlate needs to
- * redirect it to clk_out[idx]
- */
-static int vc5_clk_out_xlate(struct clk *hw, struct ofnode_phandle_args *args)
-{
- unsigned int idx = args->args[0];
-
- if (args->args_count != 1) {
- debug("Invalid args_count: %d\n", args->args_count);
- return -EINVAL;
- }
-
- hw->id = idx;
-
- return 0;
-}
-
static unsigned long vc5_clk_out_set_rate(struct clk *hw, unsigned long rate)
{
struct udevice *dev;
static const struct clk_ops vc5_clk_ops = {
.enable = vc5_clk_out_prepare,
.disable = vc5_clk_out_unprepare,
- .of_xlate = vc5_clk_out_xlate,
.set_rate = vc5_clk_out_set_rate,
.get_rate = vc5_clk_out_get_rate,
};
for (i = 0; i < 2; i++) {
sprintf(name, "gem%d_emio_clk", i);
- ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]);
- if (ret < 0 && ret != -ENODATA) {
+ ret = clk_get_by_name_optional(dev, name,
+ &priv->gem_emio_clk[i]);
+ if (ret) {
dev_err(dev, "failed to get %s clock\n", name);
return ret;
}
return 0;
}
-static int ics8n3qv01_request(struct clk *clock)
-{
- return 0;
-}
-
static ulong ics8n3qv01_get_rate(struct clk *clk)
{
struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev);
}
static const struct clk_ops ics8n3qv01_ops = {
- .request = ics8n3qv01_request,
.get_rate = ics8n3qv01_get_rate,
.set_rate = ics8n3qv01_set_rate,
.enable = ics8n3qv01_enable,
depends on ARCH_IMX8M && SPL
select SPL_CLK
select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
help
This enables SPL DM/DTS support for clock driver in i.MX8MN
depends on ARCH_IMX8M
select CLK
select CLK_CCF
+ select CLK_COMPOSITE_CCF
help
This enables support clock driver for i.MX8MN platforms.
depends on ARCH_IMXRT && SPL
select SPL_CLK
select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
help
This enables SPL DM/DTS support for clock driver in i.MXRT1020
depends on ARCH_IMXRT
select CLK
select CLK_CCF
+ select CLK_COMPOSITE_CCF
help
This enables support clock driver for i.MXRT1020 platforms.
depends on ARCH_IMXRT && SPL
select SPL_CLK
select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
help
This enables SPL DM/DTS support for clock driver in i.MXRT1050
depends on ARCH_IMXRT
select CLK
select CLK_CCF
+ select CLK_COMPOSITE_CCF
help
This enables support clock driver for i.MXRT1050 platforms.
return 0;
}
-static int tegra_car_clk_free(struct clk *clk)
-{
- debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
- clk->id);
-
- return 0;
-}
-
static ulong tegra_car_clk_get_rate(struct clk *clk)
{
enum clock_id parent;
static struct clk_ops tegra_car_clk_ops = {
.request = tegra_car_clk_request,
- .rfree = tegra_car_clk_free,
.get_rate = tegra_car_clk_get_rate,
.set_rate = tegra_car_clk_set_rate,
.enable = tegra_car_clk_enable,
.family = "J7200",
.data = &j7200_clk_platdata,
},
+#elif CONFIG_SOC_K3_J721S2
+ {
+ .family = "J721S2",
+ .data = &j721s2_clk_platdata,
+ },
#endif
{ /* sentinel */ }
};
return 0;
}
-static int ti_sci_clk_request(struct clk *clk)
-{
- debug("%s(clk=%p)\n", __func__, clk);
- return 0;
-}
-
-static int ti_sci_clk_free(struct clk *clk)
-{
- debug("%s(clk=%p)\n", __func__, clk);
- return 0;
-}
-
static ulong ti_sci_clk_get_rate(struct clk *clk)
{
struct ti_sci_clk_data *data = dev_get_priv(clk->dev);
static struct clk_ops ti_sci_clk_ops = {
.of_xlate = ti_sci_clk_of_xlate,
- .request = ti_sci_clk_request,
- .rfree = ti_sci_clk_free,
.get_rate = ti_sci_clk_get_rate,
.set_rate = ti_sci_clk_set_rate,
.set_parent = ti_sci_clk_set_parent,
while (1) {
reg = readl(acry->base + ACRY_RSA_INT_STS);
if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_CMPLT)) {
- writel(reg, ACRY_RSA_INT_STS);
+ writel(reg, acry->base + ACRY_RSA_INT_STS);
break;
}
udelay(20);
bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
depends on IMX8ULP_DRAM
+config SAVED_DRAM_TIMING_BASE
+ hex "Define the base address for saved dram timing"
+ help
+ The DRAM config timing data need to be saved into sram
+ for low power use.
+ default 0x2006c000
+
endmenu
* Polling SIM LPDDR_CTRL2 Bit phy_freq_chg_req until be 1'b1
*/
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
- phy_freq_req = (reg_val >> 7) & 0x1;
-
+ /* DFS interrupt is set */
+ phy_freq_req = ((reg_val >> 7) & 0x1) && ((reg_val >> 15) & 0x1);
if (phy_freq_req) {
phy_freq_type = reg_val & 0x1F;
if (phy_freq_type == 0x00) {
if (freq_chg_pt == 2)
freq_chg_cnt--;
}
- reg_val = readl(AVD_SIM_LPDDR_CTRL2);
+
+ /* Hardware clear the ack on falling edge of LPDDR_CTRL2:phy_freq_chg_reg */
+ /* Ensure the ack is clear before starting to poll request again */
+ while ((readl(AVD_SIM_LPDDR_CTRL2) & BIT(6)))
+ ;
}
} while (1);
return 0;
}
+static void save_dram_config(struct dram_timing_info2 *timing_info, unsigned long saved_timing_base)
+{
+ int i = 0;
+ struct dram_timing_info2 *saved_timing = (struct dram_timing_info2 *)saved_timing_base;
+ struct dram_cfg_param *cfg;
+
+ saved_timing->ctl_cfg_num = timing_info->ctl_cfg_num;
+ saved_timing->phy_f1_cfg_num = timing_info->phy_f1_cfg_num;
+ saved_timing->phy_f2_cfg_num = timing_info->phy_f2_cfg_num;
+
+ /* save the fsp table */
+ for (i = 0; i < 3; i++)
+ saved_timing->fsp_table[i] = timing_info->fsp_table[i];
+
+ cfg = (struct dram_cfg_param *)(saved_timing_base +
+ sizeof(*timing_info));
+
+ /* save ctl config */
+ saved_timing->ctl_cfg = cfg;
+ for (i = 0; i < timing_info->ctl_cfg_num; i++) {
+ cfg->reg = timing_info->ctl_cfg[i].reg;
+ cfg->val = timing_info->ctl_cfg[i].val;
+ cfg++;
+ }
+
+ /* save phy f1 config */
+ saved_timing->phy_f1_cfg = cfg;
+ for (i = 0; i < timing_info->phy_f1_cfg_num; i++) {
+ cfg->reg = timing_info->phy_f1_cfg[i].reg;
+ cfg->val = timing_info->phy_f1_cfg[i].val;
+ cfg++;
+ }
+
+ /* save phy f2 config */
+ saved_timing->phy_f2_cfg = cfg;
+ for (i = 0; i < timing_info->phy_f2_cfg_num; i++) {
+ cfg->reg = timing_info->phy_f2_cfg[i].reg;
+ cfg->val = timing_info->phy_f2_cfg[i].val;
+ cfg++;
+ }
+}
+
int ddr_init(struct dram_timing_info2 *dram_timing)
{
int i;
clrbits_le32(AVD_SIM_BASE_ADDR, 0x1); /* SIM_DDR_CTRL_DIV2_EN */
}
+ /* save the dram config into sram for low power mode */
+ save_dram_config(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+
/* Initialize CTL registers */
for (i = 0; i < dram_timing->ctl_cfg_num; i++)
writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);
[bit_id],
EDGE_1);
if (current_byte_status &
- BYTE_SPLIT_OUT_MIX) {
+ (BYTE_SPLIT_OUT_MIX |
+ BYTE_HOMOGENEOUS_SPLIT_OUT)) {
if (cur_start_win[bit_id] >= 64)
cur_start_win[bit_id] -= 64;
else
EDGE_1);
if (cur_end_win[bit_id] >= 64 &&
(current_byte_status &
- BYTE_SPLIT_OUT_MIX)) {
+ (BYTE_SPLIT_OUT_MIX |
+ BYTE_HOMOGENEOUS_SPLIT_OUT))) {
cur_end_win[bit_id] -= 64;
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,
s = env;
while (s) {
ret = -EINVAL;
- i = strsep(&s, " ");
+ i = strsep(&s, " \t");
if (!i)
break;
+ s = skip_spaces(s);
d = strsep(&s, "=");
if (!d)
break;
static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt,
char *interface, char *devstr)
{
+ char *argv[DFU_MAX_ENTITY_ARGS];
+ int argc;
char *st;
debug("%s: %s interface: %s dev: %s\n", __func__, s, interface, devstr);
- st = strsep(&s, " ");
- strcpy(dfu->name, st);
+ st = strsep(&s, " \t");
+ strlcpy(dfu->name, st, DFU_NAME_SIZE);
+
+ /* Parse arguments */
+ for (argc = 0; s && argc < DFU_MAX_ENTITY_ARGS; argc++) {
+ s = skip_spaces(s);
+ if (!*s)
+ break;
+ argv[argc] = strsep(&s, " \t");
+ }
+
+ if (argc == DFU_MAX_ENTITY_ARGS && s) {
+ s = skip_spaces(s);
+ if (*s) {
+ log_err("Too many arguments for %s\n", dfu->name);
+ return -EINVAL;
+ }
+ }
dfu->alt = alt;
dfu->max_buf_size = 0;
/* Specific for mmc device */
if (strcmp(interface, "mmc") == 0) {
- if (dfu_fill_entity_mmc(dfu, devstr, s))
+ if (dfu_fill_entity_mmc(dfu, devstr, argv, argc))
return -1;
} else if (strcmp(interface, "mtd") == 0) {
- if (dfu_fill_entity_mtd(dfu, devstr, s))
+ if (dfu_fill_entity_mtd(dfu, devstr, argv, argc))
return -1;
} else if (strcmp(interface, "nand") == 0) {
- if (dfu_fill_entity_nand(dfu, devstr, s))
+ if (dfu_fill_entity_nand(dfu, devstr, argv, argc))
return -1;
} else if (strcmp(interface, "ram") == 0) {
- if (dfu_fill_entity_ram(dfu, devstr, s))
+ if (dfu_fill_entity_ram(dfu, devstr, argv, argc))
return -1;
} else if (strcmp(interface, "sf") == 0) {
- if (dfu_fill_entity_sf(dfu, devstr, s))
+ if (dfu_fill_entity_sf(dfu, devstr, argv, argc))
return -1;
} else if (strcmp(interface, "virt") == 0) {
- if (dfu_fill_entity_virt(dfu, devstr, s))
+ if (dfu_fill_entity_virt(dfu, devstr, argv, argc))
return -1;
} else {
printf("%s: Device %s not (yet) supported!\n",
* 4th (optional):
* mmcpart <num> (access to HW eMMC partitions)
*/
-int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s)
+int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
{
const char *entity_type;
ssize_t second_arg;
size_t third_arg;
-
struct mmc *mmc;
+ char *s;
- const char *argv[3];
- const char **parg = argv;
-
- dfu->data.mmc.dev_num = dectoul(devstr, NULL);
-
- for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) {
- *parg = strsep(&s, " ");
- if (*parg == NULL) {
- pr_err("Invalid number of arguments.\n");
- return -ENODEV;
- }
+ if (argc < 3) {
+ pr_err("The number of parameters are not enough.\n");
+ return -EINVAL;
}
+ dfu->data.mmc.dev_num = dectoul(devstr, &s);
+ if (*s)
+ return -EINVAL;
+
entity_type = argv[0];
/*
* Base 0 means we'll accept (prefixed with 0x or 0) base 16, 8,
* with default 10.
*/
- second_arg = simple_strtol(argv[1], NULL, 0);
- third_arg = simple_strtoul(argv[2], NULL, 0);
+ second_arg = simple_strtol(argv[1], &s, 0);
+ if (*s)
+ return -EINVAL;
+ third_arg = simple_strtoul(argv[2], &s, 0);
+ if (*s)
+ return -EINVAL;
mmc = find_mmc_device(dfu->data.mmc.dev_num);
if (mmc == NULL) {
* Check for an extra entry at dfu_alt_info env variable
* specifying the mmc HW defined partition number
*/
- if (s)
- if (!strcmp(strsep(&s, " "), "mmcpart"))
- dfu->data.mmc.hw_partition =
- simple_strtoul(s, NULL, 0);
+ if (argc > 3) {
+ if (argc != 5 || strcmp(argv[3], "mmcpart")) {
+ pr_err("DFU mmc raw accept 'mmcpart <partnum>' option.\n");
+ return -EINVAL;
+ }
+ dfu->data.mmc.hw_partition =
+ simple_strtoul(argv[4], NULL, 0);
+ }
} else if (!strcmp(entity_type, "part")) {
struct disk_partition partinfo;
* Check for an extra entry at dfu_alt_info env variable
* specifying the mmc HW defined partition number
*/
- if (s)
- if (!strcmp(strsep(&s, " "), "offset"))
- offset = simple_strtoul(s, NULL, 0);
+ if (argc > 3) {
+ if (argc != 5 || strcmp(argv[3], "offset")) {
+ pr_err("DFU mmc raw accept 'mmcpart <partnum>' option.\n");
+ return -EINVAL;
+ }
+ dfu->data.mmc.hw_partition =
+ simple_strtoul(argv[4], NULL, 0);
+ }
dfu->layout = DFU_RAW_ADDR;
dfu->data.mmc.lba_start = partinfo.start + offset;
- dfu->data.mmc.lba_size = partinfo.size-offset;
+ dfu->data.mmc.lba_size = partinfo.size - offset;
dfu->data.mmc.lba_blk_size = partinfo.blksz;
} else if (!strcmp(entity_type, "fat")) {
dfu->layout = DFU_FS_FAT;
#include <mtd.h>
#include <jffs2/load_kernel.h>
#include <linux/err.h>
+#include <linux/ctype.h>
static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size)
{
return DFU_DEFAULT_POLL_TIMEOUT;
}
-int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s)
+int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
{
- char *st;
+ char *s;
struct mtd_info *mtd;
int ret, part;
dfu->dev_type = DFU_DEV_MTD;
dfu->data.mtd.info = mtd;
dfu->max_buf_size = mtd->erasesize;
+ if (argc < 1)
+ return -EINVAL;
- st = strsep(&s, " ");
- if (!strcmp(st, "raw")) {
+ if (!strcmp(argv[0], "raw")) {
+ if (argc != 3)
+ return -EINVAL;
dfu->layout = DFU_RAW_ADDR;
- dfu->data.mtd.start = hextoul(s, &s);
- s++;
- dfu->data.mtd.size = hextoul(s, &s);
- } else if ((!strcmp(st, "part")) || (!strcmp(st, "partubi"))) {
+ dfu->data.mtd.start = hextoul(argv[1], &s);
+ if (*s)
+ return -EINVAL;
+ dfu->data.mtd.size = hextoul(argv[2], &s);
+ if (*s)
+ return -EINVAL;
+ } else if ((!strcmp(argv[0], "part")) || (!strcmp(argv[0], "partubi"))) {
char mtd_id[32];
struct mtd_device *mtd_dev;
u8 part_num;
struct part_info *pi;
+ if (argc != 2)
+ return -EINVAL;
+
dfu->layout = DFU_RAW_ADDR;
- part = dectoul(s, &s);
+ part = dectoul(argv[1], &s);
+ if (*s)
+ return -EINVAL;
sprintf(mtd_id, "%s,%d", devstr, part - 1);
printf("using id '%s'\n", mtd_id);
dfu->data.mtd.start = pi->offset;
dfu->data.mtd.size = pi->size;
- if (!strcmp(st, "partubi"))
+ if (!strcmp(argv[0], "partubi"))
dfu->data.mtd.ubi = 1;
} else {
- printf("%s: Memory layout (%s) not supported!\n", __func__, st);
+ printf("%s: Memory layout (%s) not supported!\n", __func__, argv[0]);
return -1;
}
return DFU_DEFAULT_POLL_TIMEOUT;
}
-int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s)
+int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
{
- char *st;
+ char *s;
int ret, dev, part;
dfu->data.nand.ubi = 0;
dfu->dev_type = DFU_DEV_NAND;
- st = strsep(&s, " ");
- if (!strcmp(st, "raw")) {
+ if (argc != 3)
+ return -EINVAL;
+
+ if (!strcmp(argv[0], "raw")) {
dfu->layout = DFU_RAW_ADDR;
- dfu->data.nand.start = hextoul(s, &s);
- s++;
- dfu->data.nand.size = hextoul(s, &s);
- } else if ((!strcmp(st, "part")) || (!strcmp(st, "partubi"))) {
+ dfu->data.nand.start = hextoul(argv[1], &s);
+ if (*s)
+ return -EINVAL;
+ dfu->data.nand.size = hextoul(argv[2], &s);
+ if (*s)
+ return -EINVAL;
+ } else if ((!strcmp(argv[0], "part")) || (!strcmp(argv[0], "partubi"))) {
char mtd_id[32];
struct mtd_device *mtd_dev;
u8 part_num;
dfu->layout = DFU_RAW_ADDR;
- dev = dectoul(s, &s);
- s++;
- part = dectoul(s, &s);
+ dev = dectoul(argv[1], &s);
+ if (*s)
+ return -EINVAL;
+ part = dectoul(argv[2], &s);
+ if (*s)
+ return -EINVAL;
sprintf(mtd_id, "%s%d,%d", "nand", dev, part - 1);
debug("using id '%s'\n", mtd_id);
dfu->data.nand.start = pi->offset;
dfu->data.nand.size = pi->size;
- if (!strcmp(st, "partubi"))
+ if (!strcmp(argv[0], "partubi"))
dfu->data.nand.ubi = 1;
} else {
- printf("%s: Memory layout (%s) not supported!\n", __func__, st);
+ printf("%s: Memory layout (%s) not supported!\n", __func__, argv[0]);
return -1;
}
return dfu_transfer_medium_ram(DFU_OP_READ, dfu, offset, buf, len);
}
-int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s)
+int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
{
- const char *argv[3];
- const char **parg = argv;
-
- for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) {
- *parg = strsep(&s, " ");
- if (*parg == NULL) {
- pr_err("Invalid number of arguments.\n");
- return -ENODEV;
- }
+ char *s;
+
+ if (argc != 3) {
+ pr_err("Invalid number of arguments.\n");
+ return -EINVAL;
}
dfu->dev_type = DFU_DEV_RAM;
}
dfu->layout = DFU_RAM_ADDR;
- dfu->data.ram.start = hextoul(argv[1], NULL);
- dfu->data.ram.size = hextoul(argv[2], NULL);
+ dfu->data.ram.start = hextoul(argv[1], &s);
+ if (*s)
+ return -EINVAL;
+ dfu->data.ram.size = hextoul(argv[2], &s);
+ if (*s)
+ return -EINVAL;
dfu->write_medium = dfu_write_medium_ram;
dfu->get_medium_size = dfu_get_medium_size_ram;
#include <spi_flash.h>
#include <jffs2/load_kernel.h>
#include <linux/mtd/mtd.h>
+#include <linux/ctype.h>
static int dfu_get_medium_size_sf(struct dfu_entity *dfu, u64 *size)
{
return dev;
}
-int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s)
+int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
{
- char *st;
+ char *s;
char *devstr_bkup = strdup(devstr);
dfu->data.sf.dev = parse_dev(devstr_bkup);
dfu->dev_type = DFU_DEV_SF;
dfu->max_buf_size = dfu->data.sf.dev->sector_size;
- st = strsep(&s, " ");
- if (!strcmp(st, "raw")) {
+ if (argc != 3)
+ return -EINVAL;
+ if (!strcmp(argv[0], "raw")) {
dfu->layout = DFU_RAW_ADDR;
- dfu->data.sf.start = hextoul(s, &s);
- s++;
- dfu->data.sf.size = hextoul(s, &s);
+ dfu->data.sf.start = hextoul(argv[1], &s);
+ if (*s)
+ return -EINVAL;
+ dfu->data.sf.size = hextoul(argv[2], &s);
+ if (*s)
+ return -EINVAL;
} else if (CONFIG_IS_ENABLED(DFU_SF_PART) &&
- (!strcmp(st, "part") || !strcmp(st, "partubi"))) {
+ (!strcmp(argv[0], "part") || !strcmp(argv[0], "partubi"))) {
char mtd_id[32];
struct mtd_device *mtd_dev;
u8 part_num;
dfu->layout = DFU_RAW_ADDR;
- dev = dectoul(s, &s);
- s++;
- part = dectoul(s, &s);
+ dev = dectoul(argv[1], &s);
+ if (*s)
+ return -EINVAL;
+ part = dectoul(argv[2], &s);
+ if (*s)
+ return -EINVAL;
sprintf(mtd_id, "%s%d,%d", "nor", dev, part - 1);
printf("using id '%s'\n", mtd_id);
}
dfu->data.sf.start = pi->offset;
dfu->data.sf.size = pi->size;
- if (!strcmp(st, "partubi"))
+ if (!strcmp(argv[0], "partubi"))
dfu->data.sf.ubi = 1;
} else {
- printf("%s: Memory layout (%s) not supported!\n", __func__, st);
+ printf("%s: Memory layout (%s) not supported!\n", __func__, argv[0]);
spi_flash_free(dfu->data.sf.dev);
return -1;
}
return 0;
}
-int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, char *s)
+int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
{
debug("%s: devstr = %s\n", __func__, devstr);
+ if (argc != 0)
+ return -EINVAL;
+
dfu->dev_type = DFU_DEV_VIRT;
dfu->layout = DFU_RAW_ADDR;
dfu->data.virt.dev_num = dectoul(devstr, NULL);
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1, \
+ .pdma_burst = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ }, \
+ }
+
+#define PSIL_SA2UL(x, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 64, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep j721s2_src_ep_map[] = {
+ /* PDMA_MCASP - McASP0-4 */
+ PSIL_PDMA_MCASP(0x4400),
+ PSIL_PDMA_MCASP(0x4401),
+ PSIL_PDMA_MCASP(0x4402),
+ PSIL_PDMA_MCASP(0x4403),
+ PSIL_PDMA_MCASP(0x4404),
+ /* PDMA_SPI_G0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4600),
+ PSIL_PDMA_XY_PKT(0x4601),
+ PSIL_PDMA_XY_PKT(0x4602),
+ PSIL_PDMA_XY_PKT(0x4603),
+ PSIL_PDMA_XY_PKT(0x4604),
+ PSIL_PDMA_XY_PKT(0x4605),
+ PSIL_PDMA_XY_PKT(0x4606),
+ PSIL_PDMA_XY_PKT(0x4607),
+ PSIL_PDMA_XY_PKT(0x4608),
+ PSIL_PDMA_XY_PKT(0x4609),
+ PSIL_PDMA_XY_PKT(0x460a),
+ PSIL_PDMA_XY_PKT(0x460b),
+ PSIL_PDMA_XY_PKT(0x460c),
+ PSIL_PDMA_XY_PKT(0x460d),
+ PSIL_PDMA_XY_PKT(0x460e),
+ PSIL_PDMA_XY_PKT(0x460f),
+ /* PDMA_SPI_G1 - SPI4-7 */
+ PSIL_PDMA_XY_PKT(0x4610),
+ PSIL_PDMA_XY_PKT(0x4611),
+ PSIL_PDMA_XY_PKT(0x4612),
+ PSIL_PDMA_XY_PKT(0x4613),
+ PSIL_PDMA_XY_PKT(0x4614),
+ PSIL_PDMA_XY_PKT(0x4615),
+ PSIL_PDMA_XY_PKT(0x4616),
+ PSIL_PDMA_XY_PKT(0x4617),
+ PSIL_PDMA_XY_PKT(0x4618),
+ PSIL_PDMA_XY_PKT(0x4619),
+ PSIL_PDMA_XY_PKT(0x461a),
+ PSIL_PDMA_XY_PKT(0x461b),
+ PSIL_PDMA_XY_PKT(0x461c),
+ PSIL_PDMA_XY_PKT(0x461d),
+ PSIL_PDMA_XY_PKT(0x461e),
+ PSIL_PDMA_XY_PKT(0x461f),
+ /* PDMA_USART_G0 - UART0-1 */
+ PSIL_PDMA_XY_PKT(0x4700),
+ PSIL_PDMA_XY_PKT(0x4701),
+ /* PDMA_USART_G1 - UART2-3 */
+ PSIL_PDMA_XY_PKT(0x4702),
+ PSIL_PDMA_XY_PKT(0x4703),
+ /* PDMA_USART_G2 - UART4-9 */
+ PSIL_PDMA_XY_PKT(0x4704),
+ PSIL_PDMA_XY_PKT(0x4705),
+ PSIL_PDMA_XY_PKT(0x4706),
+ PSIL_PDMA_XY_PKT(0x4707),
+ PSIL_PDMA_XY_PKT(0x4708),
+ PSIL_PDMA_XY_PKT(0x4709),
+ /* CPSW0 */
+ PSIL_ETHERNET(0x7000),
+ /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
+ PSIL_PDMA_XY_PKT(0x7100),
+ PSIL_PDMA_XY_PKT(0x7101),
+ PSIL_PDMA_XY_PKT(0x7102),
+ PSIL_PDMA_XY_PKT(0x7103),
+ /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
+ PSIL_PDMA_XY_PKT(0x7200),
+ PSIL_PDMA_XY_PKT(0x7201),
+ PSIL_PDMA_XY_PKT(0x7202),
+ PSIL_PDMA_XY_PKT(0x7203),
+ PSIL_PDMA_XY_PKT(0x7204),
+ PSIL_PDMA_XY_PKT(0x7205),
+ PSIL_PDMA_XY_PKT(0x7206),
+ PSIL_PDMA_XY_PKT(0x7207),
+ /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
+ PSIL_PDMA_XY_PKT(0x7300),
+ /* MCU_PDMA_ADC - ADC0-1 */
+ PSIL_PDMA_XY_TR(0x7400),
+ PSIL_PDMA_XY_TR(0x7401),
+ PSIL_PDMA_XY_TR(0x7402),
+ PSIL_PDMA_XY_TR(0x7403),
+ /* SA2UL */
+ PSIL_SA2UL(0x7500, 0),
+ PSIL_SA2UL(0x7501, 0),
+ PSIL_SA2UL(0x7502, 0),
+ PSIL_SA2UL(0x7503, 0),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep j721s2_dst_ep_map[] = {
+ /* CPSW0 */
+ PSIL_ETHERNET(0xf000),
+ PSIL_ETHERNET(0xf001),
+ PSIL_ETHERNET(0xf002),
+ PSIL_ETHERNET(0xf003),
+ PSIL_ETHERNET(0xf004),
+ PSIL_ETHERNET(0xf005),
+ PSIL_ETHERNET(0xf006),
+ PSIL_ETHERNET(0xf007),
+ /* SA2UL */
+ PSIL_SA2UL(0xf500, 1),
+ PSIL_SA2UL(0xf501, 1),
+};
+
+struct psil_ep_map j721s2_ep_map = {
+ .name = "j721s2",
+ .src = j721s2_src_ep_map,
+ .src_count = ARRAY_SIZE(j721s2_src_ep_map),
+ .dst = j721s2_dst_ep_map,
+ .dst_count = ARRAY_SIZE(j721s2_dst_ep_map),
+};
/* SoC PSI-L endpoint maps */
extern struct psil_ep_map am654_ep_map;
extern struct psil_ep_map j721e_ep_map;
+extern struct psil_ep_map j721s2_ep_map;
extern struct psil_ep_map am64_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
soc_ep_map = &am654_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
soc_ep_map = &j721e_ep_map;
+ else if (IS_ENABLED(CONFIG_SOC_K3_J721S2))
+ soc_ep_map = &j721s2_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
soc_ep_map = &am64_ep_map;
}
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
+#include <dm/lists.h>
#include <log.h>
#include <zynqmp_firmware.h>
#include <asm/cache.h>
struct mbox_chan rx_chan;
} zynqmp_power;
+#define NODE_ID_LOCATION 5
+
+static unsigned int xpm_configobject[] = {
+ /**********************************************************************/
+ /* HEADER */
+ 2, /* Number of remaining words in the header */
+ 1, /* Number of sections included in config object */
+ PM_CONFIG_OBJECT_TYPE_OVERLAY, /* Type of Config object as overlay */
+ /**********************************************************************/
+ /* SLAVE SECTION */
+
+ PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
+ 1, /* Number of slaves */
+
+ 0, /* Node ID which will be changed below */
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK |
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK |
+ PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+};
+
+static unsigned int xpm_configobject_close[] = {
+ /**********************************************************************/
+ /* HEADER */
+ 2, /* Number of remaining words in the header */
+ 1, /* Number of sections included in config object */
+ PM_CONFIG_OBJECT_TYPE_OVERLAY, /* Type of Config object as overlay */
+ /**********************************************************************/
+ /* SET CONFIG SECTION */
+ PM_CONFIG_SET_CONFIG_SECTION_ID,
+ 0U, /* Loading permission to Overlay config object */
+};
+
+int zynqmp_pmufw_config_close(void)
+{
+ zynqmp_pmufw_load_config_object(xpm_configobject_close,
+ sizeof(xpm_configobject_close));
+ return 0;
+}
+
+int zynqmp_pmufw_node(u32 id)
+{
+ /* Record power domain id */
+ xpm_configobject[NODE_ID_LOCATION] = id;
+
+ zynqmp_pmufw_load_config_object(xpm_configobject,
+ sizeof(xpm_configobject));
+
+ return 0;
+}
+
static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
{
struct zynqmp_ipi_msg msg;
{ }
};
+static int zynqmp_firmware_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *child;
+
+ if (IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) {
+ ret = device_bind_driver_to_node(dev, "zynqmp_power_domain",
+ "zynqmp_power_domain",
+ dev_ofnode(dev), &child);
+ if (ret) {
+ printf("zynqmp power domain driver is not bound: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return dm_scan_fdt_dev(dev);
+}
+
U_BOOT_DRIVER(zynqmp_firmware) = {
.id = UCLASS_FIRMWARE,
.name = "zynqmp_firmware",
.of_match = zynqmp_firmware_ids,
+ .bind = zynqmp_firmware_bind,
};
{
.dev_id = 235,
.subtype = 1,
- .range_start = 144,
+ .range_start = 124,
.range_num = 32,
},
/* TX channels */
{
.dev_id = 236,
.subtype = 13,
- .range_start = 7,
+ .range_start = 6,
.range_num = 2,
},
/* RX channels */
{
.dev_id = 236,
.subtype = 10,
- .range_start = 7,
+ .range_start = 6,
.range_num = 2,
},
/* RX Free flows */
};
#endif /* CONFIG_TARGET_J7200_R5_EVM */
+#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+ /* Free rings */
+ {
+ .dev_id = 272,
+ .subtype = 1,
+ .range_start = 180,
+ .range_num = 32,
+ },
+ /* TX channels */
+ {
+ .dev_id = 273,
+ .subtype = 13,
+ .range_start = 12,
+ .range_num = 2,
+ },
+ /* RX channels */
+ {
+ .dev_id = 273,
+ .subtype = 10,
+ .range_start = 12,
+ .range_num = 2,
+ },
+ /* RX Free flows */
+ {
+ .dev_id = 273,
+ .subtype = 0,
+ .range_start = 80,
+ .range_num = 8,
+ },
+ { },
+};
+#endif /* CONFIG_TARGET_J721S2_R5_EVM */
+
#else
static struct ti_sci_resource_static_data rm_static_data[] = {
{ },
help
This driver supports the DA8xx GPIO controller
+config FXL6408_GPIO
+ bool "FXL6408 I2C GPIO expander driver"
+ depends on DM_GPIO && DM_I2C
+ help
+ This driver supports the Fairchild FXL6408 device. FXL6408 is a
+ fully configurable 8-bit I2C-controlled GPIO expander.
+
config INTEL_BROADWELL_GPIO
bool "Intel Broadwell GPIO driver"
depends on DM
are accessed using xilinx firmware. In modepin register, [3:0] bits
set direction, [7:4] bits read IO, [11:8] bits set/clear IO.
+config SL28CPLD_GPIO
+ bool "Kontron sl28cpld GPIO driver"
+ depends on DM_GPIO && SL28CPLD
+ help
+ Support GPIO access on Kontron sl28cpld board management controllers.
+
endif
obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o
obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o
+obj-$(CONFIG_FXL6408_GPIO) += gpio-fxl6408.o
obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
+obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Toradex
+ * Copyright (C) 2016 Broadcom
+ */
+
+/**
+ * DOC: FXL6408 I2C to GPIO expander.
+ *
+ * This chip has 8 GPIO lines out of it, and is controlled by an I2C
+ * bus (a pair of lines), providing 4x expansion of GPIO lines. It
+ * also provides an interrupt line out for notifying of state changes.
+ *
+ * Any preconfigured state will be left in place until the GPIO lines
+ * get activated. At power on, everything is treated as an input,
+ * default input is HIGH and pulled-up, all interrupts are masked.
+ *
+ * Documentation can be found at:
+ * ------------------------------
+ *
+ * https://www.fairchildsemi.com/datasheets/FX/FXL6408.pdf
+ *
+ * This driver bases on:
+ * ---------------------
+ *
+ * - the original driver by Eric Anholt <eric@anholt.net>:
+ * https://patchwork.kernel.org/patch/9148419/
+ * - the Toradex version by Max Krummenacher <max.krummenacher@toradex.com>:
+ * http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx
+ * - the U-boot PCA953x driver by Peng Fan <van.freenix@gmail.com>:
+ * drivers/gpio/pca953x_gpio.c
+ *
+ * TODO:
+ * - Add interrupts support
+ * - Replace deprecated callbacks direction_input/output() with set_flags()
+ */
+
+#include <asm-generic/gpio.h>
+#include <asm/global_data.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <i2c.h>
+#include <linux/bitops.h>
+#include <log.h>
+
+#define REG_DEVID_CTRL 0x1
+# define SW_RST BIT(0)
+# define RST_INT BIT(1)
+/** 0b101 is the Manufacturer's ID assigned to Fairchild by Nokia */
+# define MF_ID_FAIRCHILD 5
+
+/** Bits set here indicate that the GPIO is an output */
+#define REG_IO_DIR 0x3
+
+/**
+ * REG_OUT_STATE - a high-output state register address
+ *
+ * Bits set here, when the corresponding bit of REG_IO_DIR is set,
+ * drive the output high instead of low.
+ */
+#define REG_OUT_STATE 0x5
+
+/** Bits here make the output High-Z, instead of the OUTPUT value */
+#define REG_OUT_HIGH_Z 0x7
+
+/**
+ * REG_IN_DEFAULT_STATE - an interrupt state register address
+ *
+ * Bits here define the expected input state of the GPIO.
+ * INTERRUPT_STATUS bits will be set when the INPUT transitions away
+ * from this value.
+ */
+#define REG_IN_DEFAULT_STATE 0x9
+
+/**
+ * REG_PULL_ENABLE - a pull-up/down enable state register address
+ *
+ * Bits here enable either pull up or pull down according to
+ * REG_PULL_MODE.
+ */
+#define REG_PULL_ENABLE 0xb
+
+/**
+ * REG_PULL_MODE - a pull-up/pull-down mode state register address
+ *
+ * Bits set here selects a pull-up/pull-down state of pin, which
+ * is configured as Input and the corresponding REG_PULL_ENABLE bit is
+ * set.
+ */
+#define REG_PULL_MODE 0xd
+
+/** Returns the current status (1 = HIGH) of the input pins */
+#define REG_IN_STATUS 0xf
+
+/** Mask of pins which can generate interrupts */
+#define REG_INT_MASK 0x11
+
+/** Mask of pins which have generated an interrupt. Cleared on read */
+#define REG_INT_STATUS 0x13
+
+/* Manufacturer's ID getting from Device ID & Ctrl register */
+enum {
+ MF_ID_MASK = GENMASK(7, 5),
+ MF_ID_SHIFT = 5,
+};
+
+/* Firmware revision getting from Device ID & Ctrl register */
+enum {
+ FW_REV_MASK = GENMASK(4, 2),
+ FW_REV_SHIFT = 2,
+};
+
+enum io_direction {
+ DIR_IN = 0,
+ DIR_OUT = 1,
+};
+
+/**
+ * struct fxl6408_info - Data for fxl6408
+ *
+ * @dev: udevice structure for the device
+ * @addr: i2c slave address
+ * @device_id: hold the value of device id register
+ * @reg_io_dir: hold the value of direction register
+ * @reg_output: hold the value of output register
+ */
+struct fxl6408_info {
+ struct udevice *dev;
+ int addr;
+ u8 device_id;
+ u8 reg_io_dir;
+ u8 reg_output;
+};
+
+static inline int fxl6408_write(struct udevice *dev, int reg, u8 val)
+{
+ return dm_i2c_write(dev, reg, &val, 1);
+}
+
+static int fxl6408_read(struct udevice *dev, int reg)
+{
+ int ret;
+ u8 tmp;
+
+ ret = dm_i2c_read(dev, reg, &tmp, 1);
+ if (!ret)
+ ret = tmp;
+
+ return ret;
+}
+
+/**
+ * fxl6408_is_output() - check whether the gpio configures as either
+ * output or input.
+ *
+ * @dev: an instance of a driver
+ * @offset: a gpio offset
+ *
+ * Return: false - input, true - output.
+ */
+static bool fxl6408_is_output(struct udevice *dev, int offset)
+{
+ struct fxl6408_info *info = dev_get_plat(dev);
+
+ return info->reg_io_dir & BIT(offset);
+}
+
+static int fxl6408_get_value(struct udevice *dev, uint offset)
+{
+ int ret, reg = fxl6408_is_output(dev, offset) ? REG_OUT_STATE : REG_IN_STATUS;
+
+ ret = fxl6408_read(dev, reg);
+ if (ret < 0)
+ return ret;
+
+ return !!(ret & BIT(offset));
+}
+
+static int fxl6408_set_value(struct udevice *dev, uint offset, int value)
+{
+ struct fxl6408_info *info = dev_get_plat(dev);
+ u8 val;
+ int ret;
+
+ if (value)
+ val = info->reg_output | BIT(offset);
+ else
+ val = info->reg_output & ~BIT(offset);
+
+ ret = fxl6408_write(dev, REG_OUT_STATE, val);
+ if (ret < 0)
+ return ret;
+
+ info->reg_output = val;
+
+ return 0;
+}
+
+static int fxl6408_set_direction(struct udevice *dev, uint offset,
+ enum io_direction dir)
+{
+ struct fxl6408_info *info = dev_get_plat(dev);
+ u8 val;
+ int ret;
+
+ if (dir == DIR_IN)
+ val = info->reg_io_dir & ~BIT(offset);
+ else
+ val = info->reg_io_dir | BIT(offset);
+
+ ret = fxl6408_write(dev, REG_IO_DIR, val);
+ if (ret < 0)
+ return ret;
+
+ info->reg_io_dir = val;
+
+ return 0;
+}
+
+static int fxl6408_direction_input(struct udevice *dev, uint offset)
+{
+ return fxl6408_set_direction(dev, offset, DIR_IN);
+}
+
+static int fxl6408_direction_output(struct udevice *dev, uint offset, int value)
+{
+ int ret;
+
+ /* Configure output value */
+ ret = fxl6408_set_value(dev, offset, value);
+ if (ret < 0)
+ return ret;
+
+ /* Configure direction as output */
+ fxl6408_set_direction(dev, offset, DIR_OUT);
+
+ return 0;
+}
+
+static int fxl6408_get_function(struct udevice *dev, uint offset)
+{
+ if (fxl6408_is_output(dev, offset))
+ return GPIOF_OUTPUT;
+
+ return GPIOF_INPUT;
+}
+
+static int fxl6408_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ desc->offset = args->args[0];
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops fxl6408_ops = {
+ .direction_input = fxl6408_direction_input,
+ .direction_output = fxl6408_direction_output,
+ .get_value = fxl6408_get_value,
+ .set_value = fxl6408_set_value,
+ .get_function = fxl6408_get_function,
+ .xlate = fxl6408_xlate,
+};
+
+static int fxl6408_probe(struct udevice *dev)
+{
+ struct fxl6408_info *info = dev_get_plat(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ char bank_name[32], *tmp_str;
+ int addr, ret, size;
+ u32 val32;
+
+ addr = dev_read_addr(dev);
+ if (addr == 0)
+ return -EINVAL;
+
+ info->addr = addr;
+
+ /*
+ * Check the device ID register to see if it's responding.
+ * This also clears RST_INT as a side effect, so we won't get
+ * the "we've been power cycled" interrupt once interrupts
+ * being enabled.
+ */
+ ret = fxl6408_read(dev, REG_DEVID_CTRL);
+ if (ret < 0) {
+ dev_err(dev, "FXL6408 probe returned %d\n", ret);
+ return ret;
+ }
+
+ if ((ret & MF_ID_MASK) >> MF_ID_SHIFT != MF_ID_FAIRCHILD) {
+ dev_err(dev, "FXL6408 probe: wrong Manufacturer's ID: 0x%02x\n", ret);
+ return -ENXIO;
+ }
+ info->device_id = ret;
+
+ /*
+ * Disable High-Z of outputs, so that the OUTPUT updates
+ * actually take effect.
+ */
+ ret = fxl6408_write(dev, REG_OUT_HIGH_Z, (u8)0);
+ if (ret < 0) {
+ dev_err(dev, "Error writing High-Z register\n");
+ return ret;
+ }
+
+ /*
+ * If configured, set initial output state and direction,
+ * otherwise read them from the chip.
+ */
+ if (dev_read_u32(dev, "initial_io_dir", &val32)) {
+ ret = fxl6408_read(dev, REG_IO_DIR);
+ if (ret < 0) {
+ dev_err(dev, "Error reading direction register\n");
+ return ret;
+ }
+ info->reg_io_dir = ret;
+ } else {
+ info->reg_io_dir = val32 & 0xFF;
+ ret = fxl6408_write(dev, REG_IO_DIR, info->reg_io_dir);
+ if (ret < 0) {
+ dev_err(dev, "Error setting direction register\n");
+ return ret;
+ }
+ }
+
+ if (dev_read_u32(dev, "initial_output", &val32)) {
+ ret = fxl6408_read(dev, REG_OUT_STATE);
+ if (ret < 0) {
+ dev_err(dev, "Error reading output register\n");
+ return ret;
+ }
+ info->reg_output = ret;
+ } else {
+ info->reg_output = val32 & 0xFF;
+ ret = fxl6408_write(dev, REG_OUT_STATE, info->reg_output);
+ if (ret < 0) {
+ dev_err(dev, "Error setting output register\n");
+ return ret;
+ }
+ }
+
+ tmp_str = (char *)dev_read_prop(dev, "bank-name", &size);
+ if (tmp_str) {
+ snprintf(bank_name, sizeof(bank_name), "%s@%x_", tmp_str,
+ info->addr);
+ } else {
+ snprintf(bank_name, sizeof(bank_name), "gpio@%x_", info->addr);
+ }
+
+ tmp_str = strdup(bank_name);
+ if (!tmp_str)
+ return -ENOMEM;
+
+ uc_priv->bank_name = tmp_str;
+ uc_priv->gpio_count = dev_get_driver_data(dev);
+ uc_priv->gpio_base = -1;
+
+ dev_dbg(dev, "%s (FW rev. %d) is ready\n", bank_name,
+ (info->device_id & FW_REV_MASK) >> FW_REV_SHIFT);
+
+ return 0;
+}
+
+static const struct udevice_id fxl6408_ids[] = {
+ { .compatible = "fcs,fxl6408", .data = 8 },
+ { }
+};
+
+U_BOOT_DRIVER(fxl6408_gpio) = {
+ .name = "fxl6408_gpio",
+ .id = UCLASS_GPIO,
+ .ops = &fxl6408_ops,
+ .probe = fxl6408_probe,
+ .of_match = fxl6408_ids,
+ .plat_auto = sizeof(struct fxl6408_info),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GPIO driver for the sl28cpld
+ *
+ * Copyright (c) 2021 Michael Walle <michael@walle.cc>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <sl28cpld.h>
+
+/* GPIO flavor */
+#define SL28CPLD_GPIO_DIR 0x00
+#define SL28CPLD_GPIO_OUT 0x01
+#define SL28CPLD_GPIO_IN 0x02
+
+/* input-only flavor */
+#define SL28CPLD_GPI_IN 0x00
+
+/* output-only flavor */
+#define SL28CPLD_GPO_OUT 0x00
+
+enum {
+ SL28CPLD_GPIO,
+ SL28CPLD_GPI,
+ SL28CPLD_GPO,
+};
+
+static int sl28cpld_gpio_get_value(struct udevice *dev, unsigned int gpio)
+{
+ ulong type = dev_get_driver_data(dev);
+ int val, reg;
+
+ switch (type) {
+ case SL28CPLD_GPIO:
+ reg = SL28CPLD_GPIO_IN;
+ break;
+ case SL28CPLD_GPI:
+ reg = SL28CPLD_GPI_IN;
+ break;
+ case SL28CPLD_GPO:
+ /* we are output only, thus just return the output value */
+ reg = SL28CPLD_GPO_OUT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ val = sl28cpld_read(dev, reg);
+
+ return val < 0 ? val : !!(val & BIT(gpio));
+}
+
+static int sl28cpld_gpio_set_value(struct udevice *dev, unsigned int gpio,
+ int value)
+{
+ ulong type = dev_get_driver_data(dev);
+ uint reg;
+
+ switch (type) {
+ case SL28CPLD_GPIO:
+ reg = SL28CPLD_GPIO_OUT;
+ break;
+ case SL28CPLD_GPO:
+ reg = SL28CPLD_GPO_OUT;
+ break;
+ case SL28CPLD_GPI:
+ default:
+ return -EINVAL;
+ }
+
+ if (value)
+ return sl28cpld_update(dev, reg, 0, BIT(gpio));
+ else
+ return sl28cpld_update(dev, reg, BIT(gpio), 0);
+}
+
+static int sl28cpld_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+ ulong type = dev_get_driver_data(dev);
+
+ switch (type) {
+ case SL28CPLD_GPI:
+ return 0;
+ case SL28CPLD_GPIO:
+ return sl28cpld_update(dev, SL28CPLD_GPIO_DIR, BIT(gpio), 0);
+ case SL28CPLD_GPO:
+ default:
+ return -EINVAL;
+ }
+}
+
+static int sl28cpld_gpio_direction_output(struct udevice *dev,
+ unsigned int gpio, int value)
+{
+ ulong type = dev_get_driver_data(dev);
+ int ret;
+
+ /* set_value() will report an error if we are input-only */
+ ret = sl28cpld_gpio_set_value(dev, gpio, value);
+ if (ret)
+ return ret;
+
+ if (type == SL28CPLD_GPIO)
+ return sl28cpld_update(dev, SL28CPLD_GPIO_DIR, 0, BIT(gpio));
+
+ return 0;
+}
+
+static int sl28cpld_gpio_get_function(struct udevice *dev, unsigned int gpio)
+{
+ ulong type = dev_get_driver_data(dev);
+ int val;
+
+ switch (type) {
+ case SL28CPLD_GPIO:
+ val = sl28cpld_read(dev, SL28CPLD_GPIO_DIR);
+ if (val < 0)
+ return val;
+ if (val & BIT(gpio))
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+ case SL28CPLD_GPI:
+ return GPIOF_INPUT;
+ case SL28CPLD_GPO:
+ return GPIOF_OUTPUT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct dm_gpio_ops sl28cpld_gpio_ops = {
+ .direction_input = sl28cpld_gpio_direction_input,
+ .direction_output = sl28cpld_gpio_direction_output,
+ .get_value = sl28cpld_gpio_get_value,
+ .set_value = sl28cpld_gpio_set_value,
+ .get_function = sl28cpld_gpio_get_function,
+};
+
+static int sl28cpld_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = 8;
+ uc_priv->bank_name = dev_read_name(dev);
+
+ return 0;
+}
+
+static const struct udevice_id sl28cpld_gpio_ids[] = {
+ { .compatible = "kontron,sl28cpld-gpio", .data = SL28CPLD_GPIO},
+ { .compatible = "kontron,sl28cpld-gpo", .data = SL28CPLD_GPO},
+ { .compatible = "kontron,sl28cpld-gpi", .data = SL28CPLD_GPI},
+ { }
+};
+
+U_BOOT_DRIVER(sl28cpld_gpio) = {
+ .name = "sl28cpld_gpio",
+ .id = UCLASS_GPIO,
+ .of_match = sl28cpld_gpio_ids,
+ .probe = sl28cpld_gpio_probe,
+ .ops = &sl28cpld_gpio_ops,
+};
PCA9546,
PCA9547,
PCA9548,
- PCA9646
+ PCA9646,
+ PCA9847,
};
struct chip_desc {
.muxtype = pca954x_isswi,
.width = 4,
},
+ [PCA9847] = {
+ .enable = 0x8,
+ .muxtype = pca954x_ismux,
+ .width = 8,
+ },
};
static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
{ .compatible = "nxp,pca9547", .data = PCA9547 },
{ .compatible = "nxp,pca9548", .data = PCA9548 },
{ .compatible = "nxp,pca9646", .data = PCA9646 },
+ { .compatible = "nxp,pca9847", .data = PCA9847 },
{ }
};
struct omap_i2c *priv = dev_get_priv(bus);
return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay,
- chip_addr);
+ chip_addr) ? -EREMOTEIO : 0;
}
static int omap_i2c_probe(struct udevice *bus)
and is only used by novena. For new boards, use driver model
instead.
+config APPLE_SPI_KEYB
+ bool "Enable Apple SPI keyboard support"
+ depends on DM_KEYBOARD && DM_SPI
+ help
+ This adds a driver for the keyboards found on various
+ laptops based on Apple SoCs. These keyboards use an
+ Apple-specific HID-over-SPI protocol.
+
config CROS_EC_KEYB
bool "Enable Chrome OS EC keyboard support"
depends on INPUT
ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_APPLE_SPI_KEYB) += apple_spi_kbd.o
obj-$(CONFIG_I8042_KEYB) += i8042.o
obj-$(CONFIG_TEGRA_KEYBOARD) += input.o tegra-kbc.o
obj-$(CONFIG_TWL4030_INPUT) += twl4030.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <keyboard.h>
+#include <spi.h>
+#include <stdio_dev.h>
+#include <asm-generic/gpio.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+
+/*
+ * The Apple SPI keyboard controller implements a protocol that
+ * closely resembles HID Keyboard Boot protocol. The key codes are
+ * mapped according to the HID Keyboard/Keypad Usage Table.
+ */
+
+/* Modifier key bits */
+#define HID_MOD_LEFTCTRL BIT(0)
+#define HID_MOD_LEFTSHIFT BIT(1)
+#define HID_MOD_LEFTALT BIT(2)
+#define HID_MOD_LEFTGUI BIT(3)
+#define HID_MOD_RIGHTCTRL BIT(4)
+#define HID_MOD_RIGHTSHIFT BIT(5)
+#define HID_MOD_RIGHTALT BIT(6)
+#define HID_MOD_RIGHTGUI BIT(7)
+
+static const u8 hid_kbd_keymap[] = {
+ KEY_RESERVED, 0xff, 0xff, 0xff,
+ KEY_A, KEY_B, KEY_C, KEY_D,
+ KEY_E, KEY_F, KEY_G, KEY_H,
+ KEY_I, KEY_J, KEY_K, KEY_L,
+ KEY_M, KEY_N, KEY_O, KEY_P,
+ KEY_Q, KEY_R, KEY_S, KEY_T,
+ KEY_U, KEY_V, KEY_W, KEY_X,
+ KEY_Y, KEY_Z, KEY_1, KEY_2,
+ KEY_3, KEY_4, KEY_5, KEY_6,
+ KEY_7, KEY_8, KEY_9, KEY_0,
+ KEY_ENTER, KEY_ESC, KEY_BACKSPACE, KEY_TAB,
+ KEY_SPACE, KEY_MINUS, KEY_EQUAL, KEY_LEFTBRACE,
+ KEY_RIGHTBRACE, KEY_BACKSLASH, 0xff, KEY_SEMICOLON,
+ KEY_APOSTROPHE, KEY_GRAVE, KEY_COMMA, KEY_DOT,
+ KEY_SLASH, KEY_CAPSLOCK, KEY_F1, KEY_F2,
+ KEY_F3, KEY_F4, KEY_F5, KEY_F6,
+ KEY_F7, KEY_F8, KEY_F9, KEY_F10,
+ KEY_F11, KEY_F12, KEY_SYSRQ, KEY_SCROLLLOCK,
+ KEY_PAUSE, KEY_INSERT, KEY_HOME, KEY_PAGEUP,
+ KEY_DELETE, KEY_END, KEY_PAGEDOWN, KEY_RIGHT,
+ KEY_LEFT, KEY_DOWN, KEY_UP, KEY_NUMLOCK,
+ KEY_KPSLASH, KEY_KPASTERISK, KEY_KPMINUS, KEY_KPPLUS,
+ KEY_KPENTER, KEY_KP1, KEY_KP2, KEY_KP3,
+ KEY_KP4, KEY_KP5, KEY_KP6, KEY_KP7,
+ KEY_KP8, KEY_KP9, KEY_KP0, KEY_KPDOT,
+ KEY_BACKSLASH, KEY_COMPOSE, KEY_POWER, KEY_KPEQUAL,
+};
+
+/* Report ID used for keyboard input reports. */
+#define KBD_REPORTID 0x01
+
+struct apple_spi_kbd_report {
+ u8 reportid;
+ u8 modifiers;
+ u8 reserved;
+ u8 keycode[6];
+ u8 fn;
+};
+
+struct apple_spi_kbd_priv {
+ struct gpio_desc enable;
+ struct apple_spi_kbd_report old; /* previous keyboard input report */
+ struct apple_spi_kbd_report new; /* current keyboard input report */
+};
+
+/* Keyboard device. */
+#define KBD_DEVICE 0x01
+
+/* The controller sends us fixed-size packets of 256 bytes. */
+struct apple_spi_kbd_packet {
+ u8 flags;
+#define PACKET_READ 0x20
+ u8 device;
+ u16 offset;
+ u16 remaining;
+ u16 len;
+ u8 data[246];
+ u16 crc;
+};
+
+/* Packets contain a single variable-sized message. */
+struct apple_spi_kbd_msg {
+ u8 type;
+#define MSG_REPORT 0x10
+ u8 device;
+ u8 unknown;
+ u8 msgid;
+ u16 rsplen;
+ u16 cmdlen;
+ u8 data[0];
+};
+
+static void apple_spi_kbd_service_modifiers(struct input_config *input)
+{
+ struct apple_spi_kbd_priv *priv = dev_get_priv(input->dev);
+ u8 new = priv->new.modifiers;
+ u8 old = priv->old.modifiers;
+
+ if ((new ^ old) & HID_MOD_LEFTCTRL)
+ input_add_keycode(input, KEY_LEFTCTRL,
+ old & HID_MOD_LEFTCTRL);
+ if ((new ^ old) & HID_MOD_RIGHTCTRL)
+ input_add_keycode(input, KEY_RIGHTCTRL,
+ old & HID_MOD_RIGHTCTRL);
+ if ((new ^ old) & HID_MOD_LEFTSHIFT)
+ input_add_keycode(input, KEY_LEFTSHIFT,
+ old & HID_MOD_LEFTSHIFT);
+ if ((new ^ old) & HID_MOD_RIGHTSHIFT)
+ input_add_keycode(input, KEY_RIGHTSHIFT,
+ old & HID_MOD_RIGHTSHIFT);
+ if ((new ^ old) & HID_MOD_LEFTALT)
+ input_add_keycode(input, KEY_LEFTALT,
+ old & HID_MOD_LEFTALT);
+ if ((new ^ old) & HID_MOD_RIGHTALT)
+ input_add_keycode(input, KEY_RIGHTALT,
+ old & HID_MOD_RIGHTALT);
+ if ((new ^ old) & HID_MOD_LEFTGUI)
+ input_add_keycode(input, KEY_LEFTMETA,
+ old & HID_MOD_LEFTGUI);
+ if ((new ^ old) & HID_MOD_RIGHTGUI)
+ input_add_keycode(input, KEY_RIGHTMETA,
+ old & HID_MOD_RIGHTGUI);
+}
+
+static void apple_spi_kbd_service_key(struct input_config *input, int i,
+ int released)
+{
+ struct apple_spi_kbd_priv *priv = dev_get_priv(input->dev);
+ u8 *new;
+ u8 *old;
+
+ if (released) {
+ new = priv->new.keycode;
+ old = priv->old.keycode;
+ } else {
+ new = priv->old.keycode;
+ old = priv->new.keycode;
+ }
+
+ if (memscan(new, old[i], sizeof(priv->new.keycode)) ==
+ new + sizeof(priv->new.keycode) &&
+ old[i] < ARRAY_SIZE(hid_kbd_keymap))
+ input_add_keycode(input, hid_kbd_keymap[old[i]], released);
+}
+
+static int apple_spi_kbd_check(struct input_config *input)
+{
+ struct udevice *dev = input->dev;
+ struct apple_spi_kbd_priv *priv = dev_get_priv(dev);
+ struct apple_spi_kbd_packet packet;
+ struct apple_spi_kbd_msg *msg;
+ struct apple_spi_kbd_report *report;
+ int i, ret;
+
+ memset(&packet, 0, sizeof(packet));
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * The keyboard controller needs delays after asserting CS#
+ * and before deasserting CS#.
+ */
+ ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN);
+ if (ret < 0)
+ goto fail;
+ udelay(100);
+ ret = dm_spi_xfer(dev, sizeof(packet) * 8, NULL, &packet, 0);
+ if (ret < 0)
+ goto fail;
+ udelay(100);
+ ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+ if (ret < 0)
+ goto fail;
+
+ dm_spi_release_bus(dev);
+
+ /*
+ * The keyboard controller needs a delay between subsequent
+ * SPI transfers.
+ */
+ udelay(250);
+
+ msg = (struct apple_spi_kbd_msg *)packet.data;
+ report = (struct apple_spi_kbd_report *)msg->data;
+ if (packet.flags == PACKET_READ && packet.device == KBD_DEVICE &&
+ msg->type == MSG_REPORT && msg->device == KBD_DEVICE &&
+ msg->cmdlen == sizeof(struct apple_spi_kbd_report) &&
+ report->reportid == KBD_REPORTID) {
+ memcpy(&priv->new, report,
+ sizeof(struct apple_spi_kbd_report));
+ apple_spi_kbd_service_modifiers(input);
+ for (i = 0; i < sizeof(priv->new.keycode); i++) {
+ apple_spi_kbd_service_key(input, i, 1);
+ apple_spi_kbd_service_key(input, i, 0);
+ }
+ memcpy(&priv->old, &priv->new,
+ sizeof(struct apple_spi_kbd_report));
+ return 1;
+ }
+
+ return 0;
+
+fail:
+ /*
+ * Make sure CS# is deasserted. If this fails there is nothing
+ * we can do, so ignore any errors.
+ */
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+ dm_spi_release_bus(dev);
+ return ret;
+}
+
+static int apple_spi_kbd_probe(struct udevice *dev)
+{
+ struct apple_spi_kbd_priv *priv = dev_get_priv(dev);
+ struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct stdio_dev *sdev = &uc_priv->sdev;
+ struct input_config *input = &uc_priv->input;
+ int ret;
+
+ ret = gpio_request_by_name(dev, "spien-gpios", 0, &priv->enable,
+ GPIOD_IS_OUT);
+ if (ret < 0)
+ return ret;
+
+ /* Reset the keyboard controller. */
+ dm_gpio_set_value(&priv->enable, 1);
+ udelay(5000);
+ dm_gpio_set_value(&priv->enable, 0);
+ udelay(5000);
+
+ /* Enable the keyboard controller. */
+ dm_gpio_set_value(&priv->enable, 1);
+
+ input->dev = dev;
+ input->read_keys = apple_spi_kbd_check;
+ input_add_tables(input, false);
+ strcpy(sdev->name, "spikbd");
+
+ return input_stdio_register(sdev);
+}
+
+static const struct keyboard_ops apple_spi_kbd_ops = {
+};
+
+static const struct udevice_id apple_spi_kbd_of_match[] = {
+ { .compatible = "apple,spi-hid-transport" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(apple_spi_kbd) = {
+ .name = "apple_spi_kbd",
+ .id = UCLASS_KEYBOARD,
+ .of_match = apple_spi_kbd_of_match,
+ .probe = apple_spi_kbd_probe,
+ .priv_auto = sizeof(struct apple_spi_kbd_priv),
+ .ops = &apple_spi_kbd_ops,
+};
static const struct udevice_id apple_dart_ids[] = {
{ .compatible = "apple,t8103-dart" },
+ { .compatible = "apple,t6000-dart" },
{ /* sentinel */ }
};
the basis of a variety of inter-process/inter-CPU communication
protocols.
+config APPLE_MBOX
+ bool "Enable Apple IOP controller support"
+ depends on DM_MAILBOX && ARCH_APPLE
+ default y
+ help
+ Enable support for the mailboxes that provide a comminucation
+ channel with Apple IOP controllers integrated on Apple SoCs.
+ These IOP controllers are used to implement various functions
+ such as the System Management Controller (SMC) and NVMe and this
+ driver is required to get that functionality up and running.
+
config SANDBOX_MBOX
bool "Enable the sandbox mailbox test driver"
depends on DM_MAILBOX && SANDBOX
#
obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o
+obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+#include <asm/io.h>
+#include <linux/apple-mailbox.h>
+#include <linux/delay.h>
+
+#define REG_A2I_STAT 0x110
+#define REG_A2I_STAT_EMPTY BIT(17)
+#define REG_A2I_STAT_FULL BIT(16)
+#define REG_I2A_STAT 0x114
+#define REG_I2A_STAT_EMPTY BIT(17)
+#define REG_I2A_STAT_FULL BIT(16)
+#define REG_A2I_MSG0 0x800
+#define REG_A2I_MSG1 0x808
+#define REG_I2A_MSG0 0x830
+#define REG_I2A_MSG1 0x838
+
+struct apple_mbox_priv {
+ void *base;
+};
+
+static int apple_mbox_of_xlate(struct mbox_chan *chan,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int apple_mbox_send(struct mbox_chan *chan, const void *data)
+{
+ struct apple_mbox_priv *priv = dev_get_priv(chan->dev);
+ const struct apple_mbox_msg *msg = data;
+
+ writeq(msg->msg0, priv->base + REG_A2I_MSG0);
+ writeq(msg->msg1, priv->base + REG_A2I_MSG1);
+ while (readl(priv->base + REG_A2I_STAT) & REG_A2I_STAT_FULL)
+ udelay(1);
+
+ return 0;
+}
+
+static int apple_mbox_recv(struct mbox_chan *chan, void *data)
+{
+ struct apple_mbox_priv *priv = dev_get_priv(chan->dev);
+ struct apple_mbox_msg *msg = data;
+
+ if (readl(priv->base + REG_I2A_STAT) & REG_I2A_STAT_EMPTY)
+ return -ENODATA;
+
+ msg->msg0 = readq(priv->base + REG_I2A_MSG0);
+ msg->msg1 = readq(priv->base + REG_I2A_MSG1);
+ return 0;
+}
+
+struct mbox_ops apple_mbox_ops = {
+ .of_xlate = apple_mbox_of_xlate,
+ .send = apple_mbox_send,
+ .recv = apple_mbox_recv,
+};
+
+static int apple_mbox_probe(struct udevice *dev)
+{
+ struct apple_mbox_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id apple_mbox_of_match[] = {
+ { .compatible = "apple,asc-mailbox-v4" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(apple_mbox) = {
+ .name = "apple-mbox",
+ .id = UCLASS_MAILBOX,
+ .of_match = apple_mbox_of_match,
+ .probe = apple_mbox_probe,
+ .priv_auto = sizeof(struct apple_mbox_priv),
+ .ops = &apple_mbox_ops,
+};
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
+config SPL_FS_LOADER
+ bool "Enable loader driver for file system"
+ help
+ This is file system generic loader which can be used to load
+ the file image from the storage into target such as memory.
+
+ The consumer driver would then use this loader to program whatever,
+ ie. the FPGA device.
+
config GDSYS_SOC
bool "Enable gdsys SOC driver"
depends on MISC
config FSL_IFC
bool
+config SL28CPLD
+ bool "Enable Kontron sl28cpld multi-function driver"
+ depends on DM_I2C
+ help
+ Support for the Kontron sl28cpld management controller. This is
+ the base driver which provides common access methods for the
+ sub-drivers.
+
endmenu
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
-obj-$(CONFIG_FS_LOADER) += fs_loader.o
+obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
obj-$(CONFIG_K3_AVS0) += k3_avs.o
obj-$(CONFIG_ESM_K3) += k3_esm.o
obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
+obj-$(CONFIG_SL28CPLD) += sl28cpld.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Michael Walle <michael@walle.cc>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+
+struct sl28cpld_child_plat {
+ uint offset;
+};
+
+/*
+ * The access methods works either with the first argument being a child
+ * device or with the MFD device itself.
+ */
+static int sl28cpld_read_child(struct udevice *dev, uint offset)
+{
+ struct sl28cpld_child_plat *plat = dev_get_parent_plat(dev);
+ struct udevice *mfd = dev_get_parent(dev);
+
+ return dm_i2c_reg_read(mfd, offset + plat->offset);
+}
+
+int sl28cpld_read(struct udevice *dev, uint offset)
+{
+ if (dev->driver == DM_DRIVER_GET(sl28cpld))
+ return dm_i2c_reg_read(dev, offset);
+ else
+ return sl28cpld_read_child(dev, offset);
+}
+
+static int sl28cpld_write_child(struct udevice *dev, uint offset,
+ uint8_t value)
+{
+ struct sl28cpld_child_plat *plat = dev_get_parent_plat(dev);
+ struct udevice *mfd = dev_get_parent(dev);
+
+ return dm_i2c_reg_write(mfd, offset + plat->offset, value);
+}
+
+int sl28cpld_write(struct udevice *dev, uint offset, uint8_t value)
+{
+ if (dev->driver == DM_DRIVER_GET(sl28cpld))
+ return dm_i2c_reg_write(dev, offset, value);
+ else
+ return sl28cpld_write_child(dev, offset, value);
+}
+
+int sl28cpld_update(struct udevice *dev, uint offset, uint8_t clear,
+ uint8_t set)
+{
+ int val;
+
+ val = sl28cpld_read(dev, offset);
+ if (val < 0)
+ return val;
+
+ val &= ~clear;
+ val |= set;
+
+ return sl28cpld_write(dev, offset, val);
+}
+
+static int sl28cpld_probe(struct udevice *dev)
+{
+ i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
+ DM_I2C_CHIP_WR_ADDRESS);
+
+ return 0;
+}
+
+static int sl28cpld_child_post_bind(struct udevice *dev)
+{
+ struct sl28cpld_child_plat *plat = dev_get_parent_plat(dev);
+ int offset;
+
+ if (!dev_has_ofnode(dev))
+ return 0;
+
+ offset = dev_read_u32_default(dev, "reg", -1);
+ if (offset == -1)
+ return -EINVAL;
+
+ plat->offset = offset;
+
+ return 0;
+}
+
+static const struct udevice_id sl28cpld_ids[] = {
+ { .compatible = "kontron,sl28cpld" },
+ {}
+};
+
+U_BOOT_DRIVER(sl28cpld) = {
+ .name = "sl28cpld",
+ .id = UCLASS_NOP,
+ .of_match = sl28cpld_ids,
+ .probe = sl28cpld_probe,
+ .bind = dm_scan_fdt_dev,
+ .flags = DM_FLAG_PRE_RELOC,
+ .per_child_plat_auto = sizeof(struct sl28cpld_child_plat),
+ .child_post_bind = sl28cpld_child_post_bind,
+};
}
}
- if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
- esdhc_setup_watermark_level(priv, data);
- else
+ esdhc_setup_watermark_level(priv, data);
+ if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
esdhc_setup_dma(priv, data);
/* Calculate the timeout period for data transactions */
/* Send the command */
esdhc_write32(®s->cmdarg, cmd->cmdarg);
- if IS_ENABLED(CONFIG_FSL_USDHC) {
+ if (IS_ENABLED(CONFIG_FSL_USDHC)) {
u32 mixctrl = esdhc_read32(®s->mixctrl);
esdhc_write32(®s->mixctrl,
int sdhc_clk = priv->sdhc_clk;
uint clk;
- if (IS_ENABLED(ARCH_MXC)) {
#if IS_ENABLED(CONFIG_MX53)
- /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
- pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
#else
- pre_div = 1;
+ pre_div = 1;
#endif
- } else {
- pre_div = 2;
- }
while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
pre_div *= 2;
while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
div++;
+ mmc->clock = sdhc_clk / pre_div / div / ddr_pre_div;
+
pre_div >>= 1;
div -= 1;
else
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
- mmc->clock = sdhc_clk / pre_div / div;
priv->clock = clock;
}
esdhc_write32(®s->dllctrl, 0x0);
}
-#ifndef ARCH_MXC
- /* Enable cache snooping */
- esdhc_write32(®s->scr, 0x00000040);
-#endif
-
if (IS_ENABLED(CONFIG_FSL_USDHC))
esdhc_setbits32(®s->vendorspec,
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
esdhc_write32(®s->tuning_ctrl, val);
}
- }
+ /*
+ * UHS doesn't have explicit ESDHC flags, so if it's
+ * not supported, disable it in config.
+ */
+ if (CONFIG_IS_ENABLED(MMC_UHS_SUPPORT))
+ cfg->host_caps |= UHS_CAPS;
+
+ if (CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)) {
+ if (priv->flags & ESDHC_FLAG_HS200)
+ cfg->host_caps |= MMC_CAP(MMC_HS_200);
+ }
+
+ if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) {
+ if (priv->flags & ESDHC_FLAG_HS400)
+ cfg->host_caps |= MMC_CAP(MMC_HS_400);
+ }
+
+ if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) {
+ if (priv->flags & ESDHC_FLAG_HS400_ES)
+ cfg->host_caps |= MMC_CAP(MMC_HS_400_ES);
+ }
+ }
return 0;
}
continue;
sprintf(cfi_mtd_names[i], "nor%d", i);
+#ifdef CONFIG_CFI_FLASH
+ mtd->dev = fi->dev;
+#endif
mtd->name = cfi_mtd_names[i];
mtd->type = MTD_NORFLASH;
mtd->flags = MTD_CAP_NORFLASH;
#define CSR_OPS 0x0000000F
#define CSR_OPS_CONFIG BIT(1)
+#define APSR_RDM BIT(13)
#define APSR_TDM BIT(14)
#define TCCR_TSRQ0 BIT(0)
struct ravb_priv *eth = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
int ret = 0;
+ int mode = 0;
+ unsigned int delay;
+ bool explicit_delay = false;
/* Set CONFIG mode */
ret = ravb_reset(dev);
(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
return 0;
- if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
- (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
- writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
+ if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) {
+ /* Valid values are 0 and 1800, according to DT bindings */
+ if (delay) {
+ mode |= APSR_RDM;
+ explicit_delay = true;
+ }
+ }
+
+ if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) {
+ /* Valid values are 0 and 2000, according to DT bindings */
+ if (delay) {
+ mode |= APSR_TDM;
+ explicit_delay = true;
+ }
+ }
+
+ if (!explicit_delay) {
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ mode |= APSR_RDM;
+
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ mode |= APSR_TDM;
+ }
+
+ writel(mode, eth->iobase + RAVB_REG_APSR);
return 0;
}
.ops = &am65_cpsw_ops,
.priv_auto = sizeof(struct am65_cpsw_priv),
.plat_auto = sizeof(struct eth_pdata),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
+ .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
};
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
- plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
- offset, "reg");
+ plat->dmatx = (struct axidma_reg *)fdtdec_get_addr_size_auto_parent
+ (gd->fdt_blob, 0, offset, "reg", 0, NULL, false);
if (!plat->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
config NVME
bool "NVM Express device support"
- depends on BLK && PCI
+ depends on BLK
select HAVE_BLOCK_DEVICE
help
This option enables support for NVM Express devices.
It supports basic functions of NVMe (read/write).
+
+config NVME_APPLE
+ bool "Apple NVMe controller support"
+ select NVME
+ help
+ This option enables support for the NVMe storage
+ controller integrated on Apple SoCs. This controller
+ isn't PCI-based based and deviates from the NVMe
+ standard implementation in its implementation of
+ the command submission queue and the integration
+ of an NVMMU that needs to be managed.
+
+config NVME_PCI
+ bool "NVM Express PCI device support"
+ depends on PCI
+ select NVME
+ help
+ This option enables support for NVM Express PCI
+ devices.
# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
obj-y += nvme-uclass.o nvme.o nvme_show.o
+obj-$(CONFIG_NVME_APPLE) += nvme_apple.o
+obj-$(CONFIG_NVME_PCI) += nvme_pci.o
#include <log.h>
#include <malloc.h>
#include <memalign.h>
-#include <pci.h>
#include <time.h>
#include <dm/device-internal.h>
#include <linux/compat.h>
#define IO_TIMEOUT 30
#define MAX_PRP_POOL 512
-enum nvme_queue_id {
- NVME_ADMIN_Q,
- NVME_IO_Q,
- NVME_Q_NUM,
-};
-
-/*
- * An NVM Express queue. Each device has at least two (one for admin
- * commands and one for I/O commands).
- */
-struct nvme_queue {
- struct nvme_dev *dev;
- struct nvme_command *sq_cmds;
- struct nvme_completion *cqes;
- wait_queue_head_t sq_full;
- u32 __iomem *q_db;
- u16 q_depth;
- s16 cq_vector;
- u16 sq_head;
- u16 sq_tail;
- u16 cq_head;
- u16 qid;
- u8 cq_phase;
- u8 cqe_seen;
- unsigned long cmdid_data[];
-};
-
static int nvme_wait_ready(struct nvme_dev *dev, bool enabled)
{
u32 bit = enabled ? NVME_CSTS_RDY : 0;
*/
static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
{
+ struct nvme_ops *ops;
u16 tail = nvmeq->sq_tail;
memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
flush_dcache_range((ulong)&nvmeq->sq_cmds[tail],
(ulong)&nvmeq->sq_cmds[tail] + sizeof(*cmd));
+ ops = (struct nvme_ops *)nvmeq->dev->udev->driver->ops;
+ if (ops && ops->submit_cmd) {
+ ops->submit_cmd(nvmeq, cmd);
+ return;
+ }
+
if (++tail == nvmeq->q_depth)
tail = 0;
writel(tail, nvmeq->q_db);
struct nvme_command *cmd,
u32 *result, unsigned timeout)
{
+ struct nvme_ops *ops;
u16 head = nvmeq->cq_head;
u16 phase = nvmeq->cq_phase;
u16 status;
return -ETIMEDOUT;
}
+ ops = (struct nvme_ops *)nvmeq->dev->udev->driver->ops;
+ if (ops && ops->complete_cmd)
+ ops->complete_cmd(nvmeq, cmd);
+
status >>= 1;
if (status) {
printf("ERROR: status = %x, phase = %d, head = %d\n",
static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev,
int qid, int depth)
{
+ struct nvme_ops *ops;
struct nvme_queue *nvmeq = malloc(sizeof(*nvmeq));
if (!nvmeq)
return NULL;
dev->queue_count++;
dev->queues[qid] = nvmeq;
+ ops = (struct nvme_ops *)dev->udev->driver->ops;
+ if (ops && ops->setup_queue)
+ ops->setup_queue(nvmeq);
+
return nvmeq;
free_queue:
struct blk_desc *desc = dev_get_uclass_plat(udev);
struct nvme_ns *ns = dev_get_priv(udev);
u8 flbas;
- struct pci_child_plat *pplat;
struct nvme_id_ns *id;
id = memalign(ndev->page_size, sizeof(struct nvme_id_ns));
desc->log2blksz = ns->lba_shift;
desc->blksz = 1 << ns->lba_shift;
desc->bdev = udev;
- pplat = dev_get_parent_plat(udev->parent);
- sprintf(desc->vendor, "0x%.4x", pplat->vendor);
+ memcpy(desc->vendor, ndev->vendor, sizeof(ndev->vendor));
memcpy(desc->product, ndev->serial, sizeof(ndev->serial));
memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev));
.priv_auto = sizeof(struct nvme_ns),
};
-static int nvme_bind(struct udevice *udev)
-{
- static int ndev_num;
- char name[20];
-
- sprintf(name, "nvme#%d", ndev_num++);
-
- return device_set_name(udev, name);
-}
-
-static int nvme_probe(struct udevice *udev)
+int nvme_init(struct udevice *udev)
{
- int ret;
struct nvme_dev *ndev = dev_get_priv(udev);
struct nvme_id_ns *id;
+ int ret;
- ndev->instance = trailing_strtol(udev->name);
-
+ ndev->udev = udev;
INIT_LIST_HEAD(&ndev->namespaces);
- ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0,
- PCI_REGION_MEM);
if (readl(&ndev->bar->csts) == -1) {
ret = -ENODEV;
printf("Error: %s: Out of memory!\n", udev->name);
return ret;
}
-U_BOOT_DRIVER(nvme) = {
- .name = "nvme",
- .id = UCLASS_NVME,
- .bind = nvme_bind,
- .probe = nvme_probe,
- .priv_auto = sizeof(struct nvme_dev),
-};
-
-struct pci_device_id nvme_supported[] = {
- { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) },
- {}
-};
+int nvme_shutdown(struct udevice *udev)
+{
+ struct nvme_dev *ndev = dev_get_priv(udev);
-U_BOOT_PCI_DEVICE(nvme, nvme_supported);
+ return nvme_disable_ctrl(ndev);
+}
/* Represents an NVM Express device. Each nvme_dev is a PCI function. */
struct nvme_dev {
+ struct udevice *udev;
struct list_head node;
struct nvme_queue **queues;
u32 __iomem *dbs;
u32 ctrl_config;
struct nvme_bar __iomem *bar;
struct list_head namespaces;
+ char vendor[8];
char serial[20];
char model[40];
char firmware_rev[8];
u32 nn;
};
+/* Admin queue and a single I/O queue. */
+enum nvme_queue_id {
+ NVME_ADMIN_Q,
+ NVME_IO_Q,
+ NVME_Q_NUM,
+};
+
+/*
+ * An NVM Express queue. Each device has at least two (one for admin
+ * commands and one for I/O commands).
+ */
+struct nvme_queue {
+ struct nvme_dev *dev;
+ struct nvme_command *sq_cmds;
+ struct nvme_completion *cqes;
+ u32 __iomem *q_db;
+ u16 q_depth;
+ s16 cq_vector;
+ u16 sq_head;
+ u16 sq_tail;
+ u16 cq_head;
+ u16 qid;
+ u8 cq_phase;
+ u8 cqe_seen;
+ unsigned long cmdid_data[];
+};
+
/*
* An NVM Express namespace is equivalent to a SCSI LUN.
* Each namespace is operated as an independent "device".
u8 flbas;
};
+struct nvme_ops {
+ /**
+ * setup_queue - Controller-specific NVM Express queue setup.
+ *
+ * @nvmeq: NVM Express queue
+ * Return: 0 if OK, -ve on error
+ */
+ int (*setup_queue)(struct nvme_queue *nvmeq);
+ /**
+ * submit_cmd - Controller-specific NVM Express command submission.
+ *
+ * If this function pointer is set to NULL, normal command
+ * submission is performed according to the NVM Express spec.
+ *
+ * @nvmeq: NVM Express queue
+ * @cmd: NVM Express command
+ */
+ void (*submit_cmd)(struct nvme_queue *nvmeq, struct nvme_command *cmd);
+ /**
+ * complete_cmd - Controller-specific NVM Express command completion
+ *
+ * @nvmeq: NVM Express queue
+ * @cmd: NVM Express command
+ */
+ void (*complete_cmd)(struct nvme_queue *nvmeq, struct nvme_command *cmd);
+};
+
+/**
+ * nvme_init() - Initialize NVM Express device
+ * @udev: The NVM Express device
+ * Return: 0 if OK, -ve on error
+ */
+int nvme_init(struct udevice *udev);
+
+/**
+ * nvme_shutdown() - Shutdown NVM Express device
+ * @udev: The NVM Express device
+ * Return: 0 if OK, -ve on error
+ */
+int nvme_shutdown(struct udevice *udev);
+
#endif /* __DRIVER_NVME_H__ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox.h>
+#include <mapmem.h>
+#include "nvme.h"
+#include <reset.h>
+
+#include <asm/io.h>
+#include <asm/arch/rtkit.h>
+#include <linux/iopoll.h>
+
+/* ASC registers */
+#define REG_CPU_CTRL 0x0044
+#define REG_CPU_CTRL_RUN BIT(4)
+
+/* Apple NVMe registers */
+#define ANS_MAX_PEND_CMDS_CTRL 0x01210
+#define ANS_MAX_QUEUE_DEPTH 64
+#define ANS_BOOT_STATUS 0x01300
+#define ANS_BOOT_STATUS_OK 0xde71ce55
+#define ANS_MODESEL 0x01304
+#define ANS_UNKNOWN_CTRL 0x24008
+#define ANS_PRP_NULL_CHECK (1 << 11)
+#define ANS_LINEAR_SQ_CTRL 0x24908
+#define ANS_LINEAR_SQ_CTRL_EN (1 << 0)
+#define ANS_ASQ_DB 0x2490c
+#define ANS_IOSQ_DB 0x24910
+#define ANS_NVMMU_NUM 0x28100
+#define ANS_NVMMU_BASE_ASQ 0x28108
+#define ANS_NVMMU_BASE_IOSQ 0x28110
+#define ANS_NVMMU_TCB_INVAL 0x28118
+#define ANS_NVMMU_TCB_STAT 0x28120
+
+#define ANS_NVMMU_TCB_SIZE 0x4000
+#define ANS_NVMMU_TCB_PITCH 0x80
+
+/*
+ * The Apple NVMe controller includes an IOMMU known as NVMMU. The
+ * NVMMU is programmed through an array of TCBs. These TCBs are paired
+ * with the corresponding slot in the submission queues and need to be
+ * configured with the command details before a command is allowed to
+ * execute. This is necessary even for commands that don't do DMA.
+ */
+struct ans_nvmmu_tcb {
+ u8 opcode;
+ u8 flags;
+ u8 slot;
+ u8 pad0;
+ u32 prpl_len;
+ u8 pad1[16];
+ u64 prp1;
+ u64 prp2;
+};
+
+#define ANS_NVMMU_TCB_WRITE BIT(0)
+#define ANS_NVMMU_TCB_READ BIT(1)
+
+struct apple_nvme_priv {
+ struct nvme_dev ndev;
+ void *base; /* NVMe registers */
+ void *asc; /* ASC registers */
+ struct reset_ctl_bulk resets; /* ASC reset */
+ struct mbox_chan chan;
+ struct ans_nvmmu_tcb *tcbs[NVME_Q_NUM]; /* Submission queue TCBs */
+ u32 __iomem *q_db[NVME_Q_NUM]; /* Submission queue doorbell */
+};
+
+static int apple_nvme_setup_queue(struct nvme_queue *nvmeq)
+{
+ struct apple_nvme_priv *priv =
+ container_of(nvmeq->dev, struct apple_nvme_priv, ndev);
+ struct nvme_dev *dev = nvmeq->dev;
+
+ switch (nvmeq->qid) {
+ case NVME_ADMIN_Q:
+ case NVME_IO_Q:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ priv->tcbs[nvmeq->qid] = (void *)memalign(4096, ANS_NVMMU_TCB_SIZE);
+ memset((void *)priv->tcbs[nvmeq->qid], 0, ANS_NVMMU_TCB_SIZE);
+
+ switch (nvmeq->qid) {
+ case NVME_ADMIN_Q:
+ priv->q_db[nvmeq->qid] =
+ ((void __iomem *)dev->bar) + ANS_ASQ_DB;
+ nvme_writeq((ulong)priv->tcbs[nvmeq->qid],
+ ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_ASQ);
+ break;
+ case NVME_IO_Q:
+ priv->q_db[nvmeq->qid] =
+ ((void __iomem *)dev->bar) + ANS_IOSQ_DB;
+ nvme_writeq((ulong)priv->tcbs[nvmeq->qid],
+ ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_IOSQ);
+ break;
+ }
+
+ return 0;
+}
+
+static void apple_nvme_submit_cmd(struct nvme_queue *nvmeq,
+ struct nvme_command *cmd)
+{
+ struct apple_nvme_priv *priv =
+ container_of(nvmeq->dev, struct apple_nvme_priv, ndev);
+ struct ans_nvmmu_tcb *tcb;
+ u16 tail = nvmeq->sq_tail;
+
+ tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH;
+ memset(tcb, 0, sizeof(*tcb));
+ tcb->opcode = cmd->common.opcode;
+ tcb->flags = ANS_NVMMU_TCB_WRITE | ANS_NVMMU_TCB_READ;
+ tcb->slot = tail;
+ tcb->prpl_len = cmd->rw.length;
+ tcb->prp1 = cmd->common.prp1;
+ tcb->prp2 = cmd->common.prp2;
+
+ writel(tail, priv->q_db[nvmeq->qid]);
+}
+
+static void apple_nvme_complete_cmd(struct nvme_queue *nvmeq,
+ struct nvme_command *cmd)
+{
+ struct apple_nvme_priv *priv =
+ container_of(nvmeq->dev, struct apple_nvme_priv, ndev);
+ struct ans_nvmmu_tcb *tcb;
+ u16 tail = nvmeq->sq_tail;
+
+ tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH;
+ memset(tcb, 0, sizeof(*tcb));
+ writel(tail, ((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_INVAL);
+ readl(((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_STAT);
+
+ if (++tail == nvmeq->q_depth)
+ tail = 0;
+ nvmeq->sq_tail = tail;
+}
+
+static int apple_nvme_probe(struct udevice *dev)
+{
+ struct apple_nvme_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ u32 ctrl, stat;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->asc = map_sysmem(addr, 0);
+
+ ret = reset_get_bulk(dev, &priv->resets);
+ if (ret < 0)
+ return ret;
+
+ ret = mbox_get_by_index(dev, 0, &priv->chan);
+ if (ret < 0)
+ return ret;
+
+ ctrl = readl(priv->asc + REG_CPU_CTRL);
+ writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
+
+ ret = apple_rtkit_init(&priv->chan);
+ if (ret < 0)
+ return ret;
+
+ ret = readl_poll_sleep_timeout(priv->base + ANS_BOOT_STATUS, stat,
+ (stat == ANS_BOOT_STATUS_OK), 100,
+ 500000);
+ if (ret < 0) {
+ printf("%s: NVMe firmware didn't boot\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ writel(ANS_LINEAR_SQ_CTRL_EN, priv->base + ANS_LINEAR_SQ_CTRL);
+ writel(((ANS_MAX_QUEUE_DEPTH << 16) | ANS_MAX_QUEUE_DEPTH),
+ priv->base + ANS_MAX_PEND_CMDS_CTRL);
+
+ writel(readl(priv->base + ANS_UNKNOWN_CTRL) & ~ANS_PRP_NULL_CHECK,
+ priv->base + ANS_UNKNOWN_CTRL);
+
+ strcpy(priv->ndev.vendor, "Apple");
+
+ writel((ANS_NVMMU_TCB_SIZE / ANS_NVMMU_TCB_PITCH) - 1,
+ priv->base + ANS_NVMMU_NUM);
+ writel(0, priv->base + ANS_MODESEL);
+
+ priv->ndev.bar = priv->base;
+ return nvme_init(dev);
+}
+
+static int apple_nvme_remove(struct udevice *dev)
+{
+ struct apple_nvme_priv *priv = dev_get_priv(dev);
+ u32 ctrl;
+
+ nvme_shutdown(dev);
+
+ apple_rtkit_shutdown(&priv->chan, APPLE_RTKIT_PWR_STATE_SLEEP);
+
+ ctrl = readl(priv->asc + REG_CPU_CTRL);
+ writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
+
+ reset_assert_bulk(&priv->resets);
+ reset_deassert_bulk(&priv->resets);
+
+ return 0;
+}
+
+static const struct nvme_ops apple_nvme_ops = {
+ .setup_queue = apple_nvme_setup_queue,
+ .submit_cmd = apple_nvme_submit_cmd,
+ .complete_cmd = apple_nvme_complete_cmd,
+};
+
+static const struct udevice_id apple_nvme_ids[] = {
+ { .compatible = "apple,nvme-ans2" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(apple_nvme) = {
+ .name = "apple_nvme",
+ .id = UCLASS_NVME,
+ .of_match = apple_nvme_ids,
+ .priv_auto = sizeof(struct apple_nvme_priv),
+ .probe = apple_nvme_probe,
+ .remove = apple_nvme_remove,
+ .ops = &apple_nvme_ops,
+ .flags = DM_FLAG_OS_PREPARE,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 NXP Semiconductors
+ * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include "nvme.h"
+
+static int nvme_bind(struct udevice *udev)
+{
+ static int ndev_num;
+ char name[20];
+
+ sprintf(name, "nvme#%d", ndev_num++);
+
+ return device_set_name(udev, name);
+}
+
+static int nvme_probe(struct udevice *udev)
+{
+ struct nvme_dev *ndev = dev_get_priv(udev);
+ struct pci_child_plat *pplat;
+
+ pplat = dev_get_parent_plat(udev);
+ sprintf(ndev->vendor, "0x%.4x", pplat->vendor);
+
+ ndev->instance = trailing_strtol(udev->name);
+ ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0,
+ PCI_REGION_MEM);
+ return nvme_init(udev);
+}
+
+U_BOOT_DRIVER(nvme) = {
+ .name = "nvme",
+ .id = UCLASS_NVME,
+ .bind = nvme_bind,
+ .probe = nvme_probe,
+ .priv_auto = sizeof(struct nvme_dev),
+};
+
+struct pci_device_id nvme_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) },
+ {}
+};
+
+U_BOOT_PCI_DEVICE(nvme, nvme_supported);
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
- default "fsl,lx2160a-pcie" if ARCH_LX2160A
- default "fsl,ls2088a-pcie" if ARCH_LX2162A
+ default "fsl,ls2088a-pcie" if ARCH_LX2160A || ARCH_LX2162A
default "fsl,ls1021a-pcie" if ARCH_LS1021A
help
This compatible is used to find pci controller node in Kernel DT
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
- default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
default "fsl,ls-pcie-ep"
help
This compatible is used to find pci controller ep node in Kernel DT
#include <linux/delay.h>
#include <linux/ioport.h>
-/* PCIe core registers */
-#define PCIE_CORE_CMD_STATUS_REG 0x4
-#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
-#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
-#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
-#define PCIE_CORE_DEV_REV_REG 0x8
-#define PCIE_CORE_EXP_ROM_BAR_REG 0x30
-#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0
-#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
-#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
-#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
-#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2
-#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5
-#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2
-#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
-#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
-#define PCIE_CORE_LINK_TRAINING BIT(5)
-#define PCIE_CORE_ERR_CAPCTL_REG 0x118
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
-
-/* PIO registers base address and register offsets */
-#define PIO_BASE_ADDR 0x4000
-#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
-#define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
-#define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
-#define PIO_STAT (PIO_BASE_ADDR + 0x4)
-#define PIO_COMPLETION_STATUS_SHIFT 7
-#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
-#define PIO_COMPLETION_STATUS_OK 0
-#define PIO_COMPLETION_STATUS_UR 1
-#define PIO_COMPLETION_STATUS_CRS 2
-#define PIO_COMPLETION_STATUS_CA 4
-#define PIO_NON_POSTED_REQ BIT(10)
-#define PIO_ERR_STATUS BIT(11)
-#define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
-#define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
-#define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
-#define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
-#define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
-#define PIO_START (PIO_BASE_ADDR + 0x1c)
-#define PIO_ISR (PIO_BASE_ADDR + 0x20)
-
-/* Aardvark Control registers */
-#define CONTROL_BASE_ADDR 0x4800
-#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
-#define PCIE_GEN_SEL_MSK 0x3
-#define PCIE_GEN_SEL_SHIFT 0x0
-#define SPEED_GEN_1 0
-#define SPEED_GEN_2 1
-#define SPEED_GEN_3 2
-#define IS_RC_MSK 1
-#define IS_RC_SHIFT 2
-#define LANE_CNT_MSK 0x18
-#define LANE_CNT_SHIFT 0x3
-#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
-#define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
-#define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
-#define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
-#define LINK_TRAINING_EN BIT(6)
-#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
-#define PCIE_CORE_CTRL2_RESERVED 0x7
-#define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
-#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
-#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
-
-/* PCIe window configuration */
-#define OB_WIN_BASE_ADDR 0x4c00
-#define OB_WIN_BLOCK_SIZE 0x20
-#define OB_WIN_COUNT 8
-#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
- OB_WIN_BLOCK_SIZE * (win) + \
- (offset))
-#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
-#define OB_WIN_ENABLE BIT(0)
-#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
-#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
-#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
-#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
-#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
-#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
-#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
-#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
-#define OB_WIN_FUNC_NUM_SHIFT 24
-#define OB_WIN_FUNC_NUM_ENABLE BIT(23)
-#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
-#define OB_WIN_BUS_NUM_BITS_SHIFT 20
-#define OB_WIN_MSG_CODE_ENABLE BIT(22)
-#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
-#define OB_WIN_MSG_CODE_SHIFT 14
-#define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
-#define OB_WIN_ATTR_ENABLE BIT(11)
-#define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
-#define OB_WIN_ATTR_TC_SHIFT 8
-#define OB_WIN_ATTR_RELAXED BIT(7)
-#define OB_WIN_ATTR_NOSNOOP BIT(6)
-#define OB_WIN_ATTR_POISON BIT(5)
-#define OB_WIN_ATTR_IDO BIT(4)
-#define OB_WIN_TYPE_MASK GENMASK(3, 0)
-#define OB_WIN_TYPE_SHIFT 0
-#define OB_WIN_TYPE_MEM 0x0
-#define OB_WIN_TYPE_IO 0x4
-#define OB_WIN_TYPE_CONFIG_TYPE0 0x8
-#define OB_WIN_TYPE_CONFIG_TYPE1 0x9
-#define OB_WIN_TYPE_MSG 0xc
-
-/* LMI registers base address and register offsets */
-#define LMI_BASE_ADDR 0x6000
-#define CFG_REG (LMI_BASE_ADDR + 0x0)
-#define LTSSM_SHIFT 24
-#define LTSSM_MASK 0x3f
-#define LTSSM_L0 0x10
-#define LTSSM_DISABLED 0x20
-#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
-
-/* PCIe core controller registers */
-#define CTRL_CORE_BASE_ADDR 0x18000
-#define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
-#define CTRL_MODE_SHIFT 0x0
-#define CTRL_MODE_MASK 0x1
-#define PCIE_CORE_MODE_DIRECT 0x0
-#define PCIE_CORE_MODE_COMMAND 0x1
-
-/* Transaction types */
-#define PCIE_CONFIG_RD_TYPE0 0x8
-#define PCIE_CONFIG_RD_TYPE1 0x9
-#define PCIE_CONFIG_WR_TYPE0 0xa
-#define PCIE_CONFIG_WR_TYPE1 0xb
+/* PCIe Root Port register offsets */
+#define ADVK_ROOT_PORT_PCI_CFG_OFF 0x0
+#define ADVK_ROOT_PORT_PCI_EXP_OFF 0xc0
+#define ADVK_ROOT_PORT_PCI_ERR_OFF 0x100
+
+/* PIO registers */
+#define ADVK_PIO_BASE_ADDR 0x4000
+#define ADVK_PIO_CTRL (ADVK_PIO_BASE_ADDR + 0x0)
+#define ADVK_PIO_CTRL_TYPE_MASK GENMASK(3, 0)
+#define ADVK_PIO_CTRL_TYPE_SHIFT 0
+#define ADVK_PIO_CTRL_TYPE_RD_TYPE0 0x8
+#define ADVK_PIO_CTRL_TYPE_RD_TYPE1 0x9
+#define ADVK_PIO_CTRL_TYPE_WR_TYPE0 0xa
+#define ADVK_PIO_CTRL_TYPE_WR_TYPE1 0xb
+#define ADVK_PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
+#define ADVK_PIO_STAT (ADVK_PIO_BASE_ADDR + 0x4)
+#define ADVK_PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
+#define ADVK_PIO_COMPLETION_STATUS_SHIFT 7
+#define ADVK_PIO_COMPLETION_STATUS_OK 0
+#define ADVK_PIO_COMPLETION_STATUS_UR 1
+#define ADVK_PIO_COMPLETION_STATUS_CRS 2
+#define ADVK_PIO_COMPLETION_STATUS_CA 4
+#define ADVK_PIO_NON_POSTED_REQ BIT(10)
+#define ADVK_PIO_ERR_STATUS BIT(11)
+#define ADVK_PIO_ADDR_LS (ADVK_PIO_BASE_ADDR + 0x8)
+#define ADVK_PIO_ADDR_MS (ADVK_PIO_BASE_ADDR + 0xc)
+#define ADVK_PIO_WR_DATA (ADVK_PIO_BASE_ADDR + 0x10)
+#define ADVK_PIO_WR_DATA_STRB (ADVK_PIO_BASE_ADDR + 0x14)
+#define ADVK_PIO_RD_DATA (ADVK_PIO_BASE_ADDR + 0x18)
+#define ADVK_PIO_START (ADVK_PIO_BASE_ADDR + 0x1c)
+#define ADVK_PIO_ISR (ADVK_PIO_BASE_ADDR + 0x20)
+
+/* Global Control registers */
+#define ADVK_GLOBAL_CTRL_BASE_ADDR 0x4800
+#define ADVK_GLOBAL_CTRL0 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x0)
+#define ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK GENMASK(1, 0)
+#define ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT 0
+#define ADVK_GLOBAL_CTRL0_SPEED_GEN_1 0
+#define ADVK_GLOBAL_CTRL0_SPEED_GEN_2 1
+#define ADVK_GLOBAL_CTRL0_SPEED_GEN_3 2
+#define ADVK_GLOBAL_CTRL0_IS_RC BIT(2)
+#define ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK GENMASK(4, 3)
+#define ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT 3
+#define ADVK_GLOBAL_CTRL0_LANE_COUNT_1 0
+#define ADVK_GLOBAL_CTRL0_LANE_COUNT_2 1
+#define ADVK_GLOBAL_CTRL0_LANE_COUNT_4 2
+#define ADVK_GLOBAL_CTRL0_LANE_COUNT_8 3
+#define ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN BIT(6)
+#define ADVK_GLOBAL_CTRL2 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x8)
+#define ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN BIT(5)
+#define ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN BIT(6)
+
+/* PCIe window configuration registers */
+#define ADVK_OB_WIN_BASE_ADDR 0x4c00
+#define ADVK_OB_WIN_BLOCK_SIZE 0x20
+#define ADVK_OB_WIN_COUNT 8
+#define ADVK_OB_WIN_REG_ADDR(win, offset) (ADVK_OB_WIN_BASE_ADDR + ADVK_OB_WIN_BLOCK_SIZE * (win) + (offset))
+#define ADVK_OB_WIN_MATCH_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x00)
+#define ADVK_OB_WIN_ENABLE BIT(0)
+#define ADVK_OB_WIN_MATCH_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x04)
+#define ADVK_OB_WIN_REMAP_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x08)
+#define ADVK_OB_WIN_REMAP_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x0c)
+#define ADVK_OB_WIN_MASK_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x10)
+#define ADVK_OB_WIN_MASK_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x14)
+#define ADVK_OB_WIN_ACTIONS(win) ADVK_OB_WIN_REG_ADDR(win, 0x18)
+#define ADVK_OB_WIN_DEFAULT_ACTIONS (ADVK_OB_WIN_ACTIONS(ADVK_OB_WIN_COUNT-1) + 0x4)
+#define ADVK_OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
+#define ADVK_OB_WIN_FUNC_NUM_SHIFT 24
+#define ADVK_OB_WIN_FUNC_NUM_ENABLE BIT(23)
+#define ADVK_OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
+#define ADVK_OB_WIN_BUS_NUM_BITS_SHIFT 20
+#define ADVK_OB_WIN_MSG_CODE_ENABLE BIT(22)
+#define ADVK_OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
+#define ADVK_OB_WIN_MSG_CODE_SHIFT 14
+#define ADVK_OB_WIN_MSG_PAYLOAD_LEN BIT(12)
+#define ADVK_OB_WIN_ATTR_ENABLE BIT(11)
+#define ADVK_OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
+#define ADVK_OB_WIN_ATTR_TC_SHIFT 8
+#define ADVK_OB_WIN_ATTR_RELAXED BIT(7)
+#define ADVK_OB_WIN_ATTR_NOSNOOP BIT(6)
+#define ADVK_OB_WIN_ATTR_POISON BIT(5)
+#define ADVK_OB_WIN_ATTR_IDO BIT(4)
+#define ADVK_OB_WIN_TYPE_MASK GENMASK(3, 0)
+#define ADVK_OB_WIN_TYPE_SHIFT 0
+#define ADVK_OB_WIN_TYPE_MEM 0x0
+#define ADVK_OB_WIN_TYPE_IO 0x4
+#define ADVK_OB_WIN_TYPE_CONFIG_TYPE0 0x8
+#define ADVK_OB_WIN_TYPE_CONFIG_TYPE1 0x9
+#define ADVK_OB_WIN_TYPE_MSG 0xc
+
+/* Local Management Interface registers */
+#define ADVK_LMI_BASE_ADDR 0x6000
+#define ADVK_LMI_PHY_CFG0 (ADVK_LMI_BASE_ADDR + 0x0)
+#define ADVK_LMI_PHY_CFG0_LTSSM_MASK GENMASK(29, 24)
+#define ADVK_LMI_PHY_CFG0_LTSSM_SHIFT 24
+#define ADVK_LMI_PHY_CFG0_LTSSM_L0 0x10
+#define ADVK_LMI_PHY_CFG0_LTSSM_DISABLED 0x20
+#define ADVK_LMI_VENDOR_ID (ADVK_LMI_BASE_ADDR + 0x44)
+
+/* Core Control registers */
+#define ADVK_CORE_CTRL_BASE_ADDR 0x18000
+#define ADVK_CORE_CTRL_CONFIG (ADVK_CORE_CTRL_BASE_ADDR + 0x0)
+#define ADVK_CORE_CTRL_CONFIG_COMMAND_MODE BIT(0)
/* PCIe Retries & Timeout definitions */
#define PIO_MAX_RETRIES 1500
#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 100000
-#define CFG_RD_CRS_VAL 0xFFFF0001
+#define CFG_RD_CRS_VAL 0xFFFF0001
/**
* struct pcie_advk - Advk PCIe controller state
*
* @base: The base address of the register space.
- * @first_busno: Bus number of the PCIe root-port.
- * This may vary depending on the PCIe setup.
* @sec_busno: Bus number for the device behind the PCIe root-port.
* @dev: The pointer to PCI uclass device.
* @reset_gpio: GPIO descriptor for PERST.
*/
struct pcie_advk {
void *base;
- int first_busno;
int sec_busno;
struct udevice *dev;
struct gpio_desc reset_gpio;
}
/**
+ * pcie_advk_link_up() - Check if PCIe link is up or not
+ *
+ * @pcie: The PCI device to access
+ *
+ * Return true on link up.
+ * Return false on link down.
+ */
+static bool pcie_advk_link_up(struct pcie_advk *pcie)
+{
+ u32 val, ltssm_state;
+
+ val = advk_readl(pcie, ADVK_LMI_PHY_CFG0);
+ ltssm_state = (val & ADVK_LMI_PHY_CFG0_LTSSM_MASK) >> ADVK_LMI_PHY_CFG0_LTSSM_SHIFT;
+ return ltssm_state >= ADVK_LMI_PHY_CFG0_LTSSM_L0 && ltssm_state < ADVK_LMI_PHY_CFG0_LTSSM_DISABLED;
+}
+
+/**
* pcie_advk_addr_valid() - Check for valid bus address
*
* @pcie: Pointer to the PCI bus
static bool pcie_advk_addr_valid(struct pcie_advk *pcie,
int busno, u8 dev, u8 func)
{
- /* On the primary (local) bus there is only one PCI Bridge */
- if (busno == pcie->first_busno && (dev != 0 || func != 0))
+ /* On the root bus there is only one PCI Bridge */
+ if (busno == 0 && (dev != 0 || func != 0))
+ return false;
+
+ /* Access to other buses is possible when link is up */
+ if (busno != 0 && !pcie_advk_link_up(pcie))
return false;
/*
uint count;
for (count = 1; count <= PIO_MAX_RETRIES; count++) {
- start = advk_readl(pcie, PIO_START);
- isr = advk_readl(pcie, PIO_ISR);
+ start = advk_readl(pcie, ADVK_PIO_START);
+ isr = advk_readl(pcie, ADVK_PIO_ISR);
if (!start && isr)
return count;
/*
unsigned int status;
char *strcomp_status, *str_posted;
- reg = advk_readl(pcie, PIO_STAT);
- status = (reg & PIO_COMPLETION_STATUS_MASK) >>
- PIO_COMPLETION_STATUS_SHIFT;
+ reg = advk_readl(pcie, ADVK_PIO_STAT);
+ status = (reg & ADVK_PIO_COMPLETION_STATUS_MASK) >>
+ ADVK_PIO_COMPLETION_STATUS_SHIFT;
switch (status) {
- case PIO_COMPLETION_STATUS_OK:
- if (reg & PIO_ERR_STATUS) {
+ case ADVK_PIO_COMPLETION_STATUS_OK:
+ if (reg & ADVK_PIO_ERR_STATUS) {
strcomp_status = "COMP_ERR";
ret = -EFAULT;
break;
}
/* Get the read result */
if (read_val)
- *read_val = advk_readl(pcie, PIO_RD_DATA);
+ *read_val = advk_readl(pcie, ADVK_PIO_RD_DATA);
/* No error */
strcomp_status = NULL;
ret = 0;
break;
- case PIO_COMPLETION_STATUS_UR:
+ case ADVK_PIO_COMPLETION_STATUS_UR:
strcomp_status = "UR";
ret = -EOPNOTSUPP;
break;
- case PIO_COMPLETION_STATUS_CRS:
+ case ADVK_PIO_COMPLETION_STATUS_CRS:
if (allow_crs && read_val) {
/* For reading, CRS is not an error status. */
*read_val = CFG_RD_CRS_VAL;
ret = -EAGAIN;
}
break;
- case PIO_COMPLETION_STATUS_CA:
+ case ADVK_PIO_COMPLETION_STATUS_CA:
strcomp_status = "CA";
ret = -ECANCELED;
break;
if (!strcomp_status)
return ret;
- if (reg & PIO_NON_POSTED_REQ)
+ if (reg & ADVK_PIO_NON_POSTED_REQ)
str_posted = "Non-posted";
else
str_posted = "Posted";
dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
str_posted, strcomp_status, reg,
- advk_readl(pcie, PIO_ADDR_LS));
+ advk_readl(pcie, ADVK_PIO_ADDR_LS));
return ret;
}
}
/*
- * The configuration space of the PCI Bridge on primary (first) bus is
+ * The configuration space of the PCI Bridge on the root bus (zero) is
* not accessible via PIO transfers like all other PCIe devices. PCI
* Bridge config registers are available directly in Aardvark memory
* space starting at offset zero. The PCI Bridge config space is of
* Type 0, but the BAR registers (including ROM BAR) don't have the same
* meaning as in the PCIe specification. Therefore do not access BAR
* registers and non-common registers (those which have different
- * meaning for Type 0 and Type 1 config space) of the primary PCI Bridge
+ * meaning for Type 0 and Type 1 config space) of the PCI Bridge
* and instead read their content from driver virtual cfgcache[].
*/
- if (busno == pcie->first_busno) {
+ if (busno == 0) {
if ((offset >= 0x10 && offset < 0x34) || (offset >= 0x38 && offset < 0x3c))
data = pcie->cfgcache[(offset - 0x10) / 4];
else
- data = advk_readl(pcie, offset & ~3);
+ data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
/*
data |= PCI_HEADER_TYPE_BRIDGE << 16;
}
- if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) {
+ if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL) {
/* CRSSVE bit is stored only in cache */
if (pcie->cfgcrssve)
data |= PCI_EXP_RTCTL_CRSSVE;
}
- if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF +
- (PCI_EXP_RTCAP & ~3)) {
+ if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + (PCI_EXP_RTCAP & ~3)) {
/* CRS is emulated below, so set CRSVIS capability */
data |= PCI_EXP_RTCAP_CRSVIS << 16;
}
*/
allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
- if (advk_readl(pcie, PIO_START)) {
+ if (advk_readl(pcie, ADVK_PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
if (allow_crs) {
}
/* Program the control register */
- reg = advk_readl(pcie, PIO_CTRL);
- reg &= ~PIO_CTRL_TYPE_MASK;
+ reg = advk_readl(pcie, ADVK_PIO_CTRL);
+ reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
if (busno == pcie->sec_busno)
- reg |= PCIE_CONFIG_RD_TYPE0;
+ reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
else
- reg |= PCIE_CONFIG_RD_TYPE1;
- advk_writel(pcie, reg, PIO_CTRL);
+ reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
+ advk_writel(pcie, reg, ADVK_PIO_CTRL);
/* Program the address registers */
reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
- advk_writel(pcie, reg, PIO_ADDR_LS);
- advk_writel(pcie, 0, PIO_ADDR_MS);
+ advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
+ advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
/* Program the data strobe */
- advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
+ advk_writel(pcie, 0xf, ADVK_PIO_WR_DATA_STRB);
retry_count = 0;
retry:
/* Start the transfer */
- advk_writel(pcie, 1, PIO_ISR);
- advk_writel(pcie, 1, PIO_START);
+ advk_writel(pcie, 1, ADVK_PIO_ISR);
+ advk_writel(pcie, 1, ADVK_PIO_START);
ret = pcie_advk_wait_pio(pcie);
if (ret < 0) {
* zero. Type 1 specific registers are not available, so we write their
* content only into driver virtual cfgcache[].
*/
- if (busno == pcie->first_busno) {
+ if (busno == 0) {
if ((offset >= 0x10 && offset < 0x34) ||
(offset >= 0x38 && offset < 0x3c)) {
data = pcie->cfgcache[(offset - 0x10) / 4];
data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
} else {
- data = advk_readl(pcie, offset & ~3);
+ data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
data = pci_conv_size_to_32(data, value, offset, size);
- advk_writel(pcie, data, offset & ~3);
+ advk_writel(pcie, data, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
}
- if (offset == PCI_PRIMARY_BUS)
- pcie->first_busno = data & 0xff;
-
if (offset == PCI_SECONDARY_BUS ||
(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
pcie->sec_busno = (data >> 8) & 0xff;
- if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL)
+ if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL)
pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
return 0;
}
- if (advk_readl(pcie, PIO_START)) {
+ if (advk_readl(pcie, ADVK_PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
return -EAGAIN;
}
/* Program the control register */
- reg = advk_readl(pcie, PIO_CTRL);
- reg &= ~PIO_CTRL_TYPE_MASK;
+ reg = advk_readl(pcie, ADVK_PIO_CTRL);
+ reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
if (busno == pcie->sec_busno)
- reg |= PCIE_CONFIG_WR_TYPE0;
+ reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
else
- reg |= PCIE_CONFIG_WR_TYPE1;
- advk_writel(pcie, reg, PIO_CTRL);
+ reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
+ advk_writel(pcie, reg, ADVK_PIO_CTRL);
/* Program the address registers */
reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
- advk_writel(pcie, reg, PIO_ADDR_LS);
- advk_writel(pcie, 0, PIO_ADDR_MS);
+ advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
+ advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
/* Program the data register */
reg = pci_conv_size_to_32(0, value, offset, size);
- advk_writel(pcie, reg, PIO_WR_DATA);
+ advk_writel(pcie, reg, ADVK_PIO_WR_DATA);
dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
/* Program the data strobe */
reg = pcie_calc_datastrobe(offset, size);
- advk_writel(pcie, reg, PIO_WR_DATA_STRB);
+ advk_writel(pcie, reg, ADVK_PIO_WR_DATA_STRB);
dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
retry_count = 0;
retry:
/* Start the transfer */
- advk_writel(pcie, 1, PIO_ISR);
- advk_writel(pcie, 1, PIO_START);
+ advk_writel(pcie, 1, ADVK_PIO_ISR);
+ advk_writel(pcie, 1, ADVK_PIO_START);
ret = pcie_advk_wait_pio(pcie);
if (ret < 0)
}
/**
- * pcie_advk_link_up() - Check if PCIe link is up or not
- *
- * @pcie: The PCI device to access
- *
- * Return 1 (true) on link up.
- * Return 0 (false) on link down.
- */
-static int pcie_advk_link_up(struct pcie_advk *pcie)
-{
- u32 val, ltssm_state;
-
- val = advk_readl(pcie, CFG_REG);
- ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
- return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
-}
-
-/**
* pcie_advk_wait_for_link() - Wait for link training to be accomplished
*
* @pcie: The PCI device to access
*
* Wait up to 1 second for link training to be accomplished.
- *
- * Return 1 (true) if link training ends up with link up success.
- * Return 0 (false) if link training ends up with link up failure.
*/
-static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
+static void pcie_advk_wait_for_link(struct pcie_advk *pcie)
{
int retries;
for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
printf("PCIe: Link up\n");
- return 0;
+ return;
}
udelay(LINK_WAIT_TIMEOUT);
}
printf("PCIe: Link down\n");
-
- return -ETIMEDOUT;
}
/*
phys_addr_t match, phys_addr_t remap,
phys_addr_t mask, u32 actions)
{
- advk_writel(pcie, OB_WIN_ENABLE |
- lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
- advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
- advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
- advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
- advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
- advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
- advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
+ advk_writel(pcie, ADVK_OB_WIN_ENABLE |
+ lower_32_bits(match), ADVK_OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, upper_32_bits(match), ADVK_OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, lower_32_bits(remap), ADVK_OB_WIN_REMAP_LS(win_num));
+ advk_writel(pcie, upper_32_bits(remap), ADVK_OB_WIN_REMAP_MS(win_num));
+ advk_writel(pcie, lower_32_bits(mask), ADVK_OB_WIN_MASK_LS(win_num));
+ advk_writel(pcie, upper_32_bits(mask), ADVK_OB_WIN_MASK_MS(win_num));
+ advk_writel(pcie, actions, ADVK_OB_WIN_ACTIONS(win_num));
}
static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
{
- advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
- advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
- advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
- advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
- advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
- advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
- advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
+ advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_LS(win_num));
+ advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_MS(win_num));
+ advk_writel(pcie, 0, ADVK_OB_WIN_MASK_LS(win_num));
+ advk_writel(pcie, 0, ADVK_OB_WIN_MASK_MS(win_num));
+ advk_writel(pcie, 0, ADVK_OB_WIN_ACTIONS(win_num));
}
static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
* because lower 16 bits of mask must be zero. Remapped address
* may have set only bits from the mask.
*/
- while (*wins < OB_WIN_COUNT && size > 0) {
+ while (*wins < ADVK_OB_WIN_COUNT && size > 0) {
/* Calculate the largest aligned window size */
win_size = (1ULL << (fls64(size) - 1)) |
(phys_start ? (1ULL << __ffs64(phys_start)) : 0);
int i, wins;
u32 reg;
- /* Set to Direct mode */
- reg = advk_readl(pcie, CTRL_CONFIG_REG);
- reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
- reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
- advk_writel(pcie, reg, CTRL_CONFIG_REG);
+ /* Set from Command to Direct mode */
+ reg = advk_readl(pcie, ADVK_CORE_CTRL_CONFIG);
+ reg &= ~ADVK_CORE_CTRL_CONFIG_COMMAND_MODE;
+ advk_writel(pcie, reg, ADVK_CORE_CTRL_CONFIG);
/* Set PCI global control register to RC mode */
- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg |= (IS_RC_MSK << IS_RC_SHIFT);
- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+ reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+ reg |= ADVK_GLOBAL_CTRL0_IS_RC;
+ advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/*
* Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
- * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
+ * ADVK_LMI_VENDOR_ID contains vendor id in low 16 bits and subsystem vendor
* id in high 16 bits. Updating this register changes readback value of
- * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
+ * read-only vendor id bits in Root Port PCI_VENDOR_ID register. Workaround
* for erratum 4.1: "The value of device and vendor ID is incorrect".
*/
- advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
+ advk_writel(pcie, 0x11ab11ab, ADVK_LMI_VENDOR_ID);
/*
* Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
* Type 1 registers is redirected to the virtual cfgcache[] buffer,
* which avoids changing unrelated registers.
*/
- reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
+ reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
reg &= ~0xffffff00;
reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
- advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
-
- /* Set Advanced Error Capabilities and Control PF0 register */
- reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
- advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
-
- /* Set PCIe Device Control and Status 1 PF0 register */
- reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
- (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
- PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
- (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
- PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
- advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+ advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
+
+ /* Enable generation and checking of ECRC on PCIe Root Port */
+ reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
+ reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE;
+ advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
+
+ /* Set PCIe Device Control register on PCIe Root Port */
+ reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
+ reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
+ reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
+ reg &= ~PCI_EXP_DEVCTL_READRQ;
+ reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
+ reg |= PCI_EXP_DEVCTL_READRQ_512B;
+ advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
/* Program PCIe Control 2 to disable strict ordering */
- reg = PCIE_CORE_CTRL2_RESERVED |
- PCIE_CORE_CTRL2_TD_ENABLE;
- advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+ reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
+ reg &= ~ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN;
+ advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
/* Set GEN2 */
- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg &= ~PCIE_GEN_SEL_MSK;
- reg |= SPEED_GEN_2;
- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+ reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+ reg &= ~ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK;
+ reg |= ADVK_GLOBAL_CTRL0_SPEED_GEN_2 << ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT;
+ advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* Set lane X1 */
- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg &= ~LANE_CNT_MSK;
- reg |= LANE_COUNT_1;
- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+ reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+ reg &= ~ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK;
+ reg |= ADVK_GLOBAL_CTRL0_LANE_COUNT_1 << ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT;
+ advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* Enable link training */
- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg |= LINK_TRAINING_EN;
- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+ reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+ reg |= ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
+ advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/*
* Enable AXI address window location generation:
* access when default outbound window configuration
* is set for memory access.
*/
- reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
- reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
- advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+ reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
+ reg |= ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN;
+ advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
/*
* Bypass the address window mapping for PIO:
* info over AXI interface by PIO registers, the
* address window is not required.
*/
- reg = advk_readl(pcie, PIO_CTRL);
- reg |= PIO_CTRL_ADDR_WIN_DISABLE;
- advk_writel(pcie, reg, PIO_CTRL);
+ reg = advk_readl(pcie, ADVK_PIO_CTRL);
+ reg |= ADVK_PIO_CTRL_ADDR_WIN_DISABLE;
+ advk_writel(pcie, reg, ADVK_PIO_CTRL);
/*
* Set memory access in Default User Field so it
* is not required to configure PCIe address for
* transparent memory access.
*/
- advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
+ advk_writel(pcie, ADVK_OB_WIN_TYPE_MEM, ADVK_OB_WIN_DEFAULT_ACTIONS);
/*
* Configure PCIe address windows for non-memory or
wins = 0;
pci_get_regions(pcie->dev, &io, &mem, &pref);
if (io)
- pcie_advk_set_ob_region(pcie, &wins, io, OB_WIN_TYPE_IO);
+ pcie_advk_set_ob_region(pcie, &wins, io, ADVK_OB_WIN_TYPE_IO);
if (mem && mem->phys_start != mem->bus_start)
- pcie_advk_set_ob_region(pcie, &wins, mem, OB_WIN_TYPE_MEM);
+ pcie_advk_set_ob_region(pcie, &wins, mem, ADVK_OB_WIN_TYPE_MEM);
if (pref && pref->phys_start != pref->bus_start)
- pcie_advk_set_ob_region(pcie, &wins, pref, OB_WIN_TYPE_MEM);
+ pcie_advk_set_ob_region(pcie, &wins, pref, ADVK_OB_WIN_TYPE_MEM);
/* Disable remaining PCIe outbound windows */
- for (i = ((wins >= 0) ? wins : 0); i < OB_WIN_COUNT; i++)
+ for (i = ((wins >= 0) ? wins : 0); i < ADVK_OB_WIN_COUNT; i++)
pcie_advk_disable_ob_win(pcie, i);
if (wins == -1)
return -EINVAL;
/* Wait for PCIe link up */
- if (pcie_advk_wait_for_link(pcie))
- return -ENXIO;
+ pcie_advk_wait_for_link(pcie);
return 0;
}
u32 reg;
int i;
- for (i = 0; i < OB_WIN_COUNT; i++)
+ for (i = 0; i < ADVK_OB_WIN_COUNT; i++)
pcie_advk_disable_ob_win(pcie, i);
- reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
- reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN |
- PCIE_CORE_CMD_IO_ACCESS_EN |
- PCIE_CORE_CMD_MEM_IO_REQ_EN);
- advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
+ reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
+ reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg &= ~LINK_TRAINING_EN;
- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+ reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+ reg &= ~ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
+ advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
return 0;
}
struct pcie_advk *pcie = dev_get_priv(dev);
/* Get the register base address */
- pcie->base = (void *)dev_read_addr_index(dev, 0);
+ pcie->base = (void *)dev_read_addr(dev);
if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
return -EINVAL;
bool is_x4;
int devfn;
u32 lane_mask;
- int first_busno;
int sec_busno;
char name[16];
unsigned int mem_target;
static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
int busno, int dev, int func)
{
- /* On primary bus is only one PCI Bridge */
- if (busno == pcie->first_busno && (dev != 0 || func != 0))
+ /* On the root bus is only one PCI Bridge */
+ if (busno == 0 && (dev != 0 || func != 0))
return false;
/* Access to other buses is possible when link is up */
- if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie))
+ if (busno != 0 && !mvebu_pcie_link_up(pcie))
return false;
/* On secondary bus can be only one PCIe device */
}
/*
- * The configuration space of the PCI Bridge on primary (first) bus is
+ * The configuration space of the PCI Bridge on the root bus (zero) is
* of Type 0 but the BAR registers (including ROM BAR) don't have the
* same meaning as in the PCIe specification. Therefore do not access
* BAR registers and non-common registers (those which have different
* meaning for Type 0 and Type 1 config space) of the PCI Bridge and
* instead read their content from driver virtual cfgcache[].
*/
- if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
- (offset >= 0x38 && offset < 0x3c))) {
+ if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
+ (offset >= 0x38 && offset < 0x3c))) {
data = pcie->cfgcache[(offset - 0x10) / 4];
debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
offset, size, data);
}
/*
- * PCI bridge is device 0 at primary bus but mvebu has it mapped on
- * secondary bus with device number 1.
+ * PCI bridge is device 0 at the root bus (zero) but mvebu has it
+ * mapped on secondary bus with device number 1.
*/
- if (busno == pcie->first_busno)
+ if (busno == 0)
addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
else
addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
return -EINVAL;
}
- if (busno == pcie->first_busno &&
- (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
+ if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
/*
* Change Header Type of PCI Bridge device to Type 1
* (0x01, used by PCI Bridges) because mvebu reports
* config registers are not available, so we write their content only
* into driver virtual cfgcache[].
* And as explained in mvebu_pcie_probe(), mvebu has its own specific
- * way for configuring primary and secondary bus numbers.
+ * way for configuring secondary bus number.
*/
- if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
- (offset >= 0x38 && offset < 0x3c))) {
+ if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
+ (offset >= 0x38 && offset < 0x3c))) {
debug("Writing to cfgcache only\n");
data = pcie->cfgcache[(offset - 0x10) / 4];
data = pci_conv_size_to_32(data, value, offset, size);
(offset & ~3) == PCI_ROM_ADDRESS1)
data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
- /* mvebu has its own way how to set PCI primary bus number */
- if (offset == PCI_PRIMARY_BUS) {
- pcie->first_busno = data & 0xff;
- debug("Primary bus number was changed to %d\n",
- pcie->first_busno);
- }
/* mvebu has its own way how to set PCI secondary bus number */
if (offset == PCI_SECONDARY_BUS ||
(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
}
/*
- * PCI bridge is device 0 at primary bus but mvebu has it mapped on
- * secondary bus with device number 1.
+ * PCI bridge is device 0 at the root bus (zero) but mvebu has it
+ * mapped on secondary bus with device number 1.
*/
- if (busno == pcie->first_busno)
+ if (busno == 0)
addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
else
addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
* target device equals local device number then request is routed to
* PCI Bridge which represent local PCIe Root Port.
*
- * It means that PCI primary and secondary buses shares one bus number
+ * It means that PCI root and secondary buses shares one bus number
* which is configured via local bus number. Determination if config
- * request should go to primary or secondary bus is done based on local
+ * request should go to root or secondary bus is done based on local
* device number.
*
* PCIe is point-to-point bus, so at secondary bus is always exactly one
* secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
* later configure it via config write requests to the correct value.
* mvebu_pcie_write_config() catches config write requests which tries
- * to change primary/secondary bus number and correctly updates local
- * bus number based on new secondary bus number.
+ * to change secondary bus number and correctly updates local bus number
+ * based on new secondary bus number.
*
* With this configuration is PCI Bridge available at secondary bus as
- * device number 1. But it must be available at primary bus as device
+ * device number 1. But it must be available at root bus (zero) as device
* number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
- * functions rewrite address to the real one when accessing primary bus.
+ * functions rewrite address to the real one when accessing the root bus.
*/
mvebu_pcie_set_local_bus_nr(pcie, 0);
mvebu_pcie_set_local_dev_nr(pcie, 1);
}
if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS))
- goto skip;
+ return;
list_for_each_entry(pcie_rc, &ls_pcie_list, list) {
nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
}
free(entries);
}
-
-skip:
- pcie_board_fix_fdt(blob);
}
#endif
{
struct ls_pcie_rc *pcie_rc;
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+ pcie_board_fix_fdt(blob);
+#endif
+
list_for_each_entry(pcie_rc, &ls_pcie_list, list)
ft_pcie_ls_setup(blob, pcie_rc);
*/
#include <common.h>
#include <clk.h>
+#include <linux/delay.h>
+#include <linux/clk-provider.h>
#include <generic-phy.h>
#include <reset.h>
#include <dm/device.h>
#include <dm/devres.h>
#include <linux/io.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
#include <regmap.h>
+#define usleep_range(a, b) udelay((b))
+
+#define NUM_SSC_MODE 3
+#define NUM_PHY_TYPE 4
+
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG 0x0
+#define SIERRA_CMN_PLLLC_GEN_PREG 0x42
#define SIERRA_CMN_PLLLC_MODE_PREG 0x48
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
+#define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51
+#define SIERRA_CMN_PLLLC_SS_PREG 0x52
+#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53
+#define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
+#define SIERRA_CMN_REFRCV_PREG 0x98
+#define SIERRA_CMN_REFRCV1_PREG 0xB8
+#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
+#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
+#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
+#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
+#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
#define SIERRA_DET_STANDEC_E_PREG 0x004
#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008
#define SIERRA_PSM_A0IN_TMR_PREG 0x009
+#define SIERRA_PSM_A3IN_TMR_PREG 0x00C
#define SIERRA_PSM_DIAG_PREG 0x015
+#define SIERRA_PSC_LN_A3_PREG 0x023
+#define SIERRA_PSC_LN_A4_PREG 0x024
+#define SIERRA_PSC_LN_IDLE_PREG 0x026
#define SIERRA_PSC_TX_A0_PREG 0x028
#define SIERRA_PSC_TX_A1_PREG 0x029
#define SIERRA_PSC_TX_A2_PREG 0x02A
#define SIERRA_PSC_RX_A2_PREG 0x032
#define SIERRA_PSC_RX_A3_PREG 0x033
#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
+#define SIERRA_PLLCTRL_GEN_A_PREG 0x03B
#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F
#define SIERRA_PLLCTRL_STATUS_PREG 0x044
#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B
#define SIERRA_DFE_BIASTRIM_PREG 0x04C
#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
+#define SIERRA_DRVCTRL_BOOST_PREG 0x06F
#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081
#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086
#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
+#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C
#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E
+#define SIERRA_RX_CTLE_CAL_PREG 0x08F
#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091
#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092
#define SIERRA_CREQ_EQ_CTRL_PREG 0x093
#define SIERRA_DEQ_ALUT12 0x114
#define SIERRA_DEQ_ALUT13 0x115
#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128
+#define SIERRA_DEQ_DFETAP0 0x129
+#define SIERRA_DEQ_DFETAP1 0x12B
+#define SIERRA_DEQ_DFETAP2 0x12D
+#define SIERRA_DEQ_DFETAP3 0x12F
+#define SIERRA_DEQ_DFETAP4 0x131
#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134
+#define SIERRA_DEQ_PRECUR_PREG 0x138
+#define SIERRA_DEQ_POSTCUR_PREG 0x140
+#define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
+#define SIERRA_DEQ_TAU_CTRL3_PREG 0x152
+#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158
#define SIERRA_DEQ_PICTRL_PREG 0x161
#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
+#define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E
+#define SIERRA_CPI_TRIM_PREG 0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183
+#define SIERRA_EPI_CTRL_PREG 0x187
#define SIERRA_LFPSDET_SUPPORT_PREG 0x188
#define SIERRA_LFPSFILT_NS_PREG 0x18A
#define SIERRA_LFPSFILT_RD_PREG 0x18B
#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
-#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000
+#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
+#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
+/* PHY PMA common registers */
+#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000
+#define SIERRA_PHY_PMA_CMN_CTRL 0x0
+
+/* PHY PCS lane registers */
+#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, offset) \
+ (0xD000 + ((ln) * (0x800 >> (3 - (offset)))))
+#define SIERRA_PHY_ISO_LINK_CTRL 0xB
+
+/* PHY PMA lane registers */
+#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, offset) \
+ (0xF000 + ((ln) * (0x800 >> (3 - (offset)))))
+#define SIERRA_PHY_PMA_XCVR_CTRL 0x000
+
#define SIERRA_MACRO_ID 0x00007364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
+#define CDNS_SIERRA_INPUT_CLOCKS 5
+enum cdns_sierra_clock_input {
+ PHY_CLK,
+ CMN_REFCLK_DIG_DIV,
+ CMN_REFCLK1_DIG_DIV,
+ PLL0_REFCLK,
+ PLL1_REFCLK,
+};
+
+#define SIERRA_NUM_CMN_PLLC 2
+#define SIERRA_NUM_CMN_PLLC_PARENTS 2
+
static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
+static const struct reg_field pma_cmn_ready =
+ REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const struct reg_field phy_iso_link_ctrl_1 =
+ REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
+
+static const char * const clk_names[] = {
+ [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
+ [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
+};
+
+enum cdns_sierra_cmn_plllc {
+ CMN_PLLLC,
+ CMN_PLLLC1,
+};
+
+struct cdns_sierra_pll_mux_reg_fields {
+ struct reg_field pfdclk_sel_preg;
+ struct reg_field plllc1en_field;
+ struct reg_field termen_field;
+};
+
+static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
+ [CMN_PLLLC] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
+ },
+ [CMN_PLLLC1] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
+ },
+};
+
+struct cdns_sierra_pll_mux {
+ struct cdns_sierra_phy *sp;
+ struct clk *clk;
+ struct clk *parent_clks[2];
+ struct regmap_field *pfdclk_sel_preg;
+ struct regmap_field *plllc1en_field;
+ struct regmap_field *termen_field;
+};
#define reset_control_assert(rst) cdns_reset_assert(rst)
#define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl
+enum cdns_sierra_phy_type {
+ TYPE_NONE,
+ TYPE_PCIE,
+ TYPE_USB,
+ TYPE_QSGMII
+};
+
+enum cdns_sierra_ssc_mode {
+ NO_SSC,
+ EXTERNAL_SSC,
+ INTERNAL_SSC
+};
+
struct cdns_sierra_inst {
- u32 phy_type;
+ enum cdns_sierra_phy_type phy_type;
u32 num_lanes;
u32 mlane;
struct reset_ctl_bulk *lnk_rst;
+ enum cdns_sierra_ssc_mode ssc_mode;
};
struct cdns_reg_pairs {
u32 off;
};
+struct cdns_sierra_vals {
+ const struct cdns_reg_pairs *reg_pairs;
+ u32 num_regs;
+};
+
struct cdns_sierra_data {
u32 id_value;
u8 block_offset_shift;
u8 reg_offset_shift;
- u32 pcie_cmn_regs;
- u32 pcie_ln_regs;
- u32 usb_cmn_regs;
- u32 usb_ln_regs;
- struct cdns_reg_pairs *pcie_cmn_vals;
- struct cdns_reg_pairs *pcie_ln_vals;
- struct cdns_reg_pairs *usb_cmn_vals;
- struct cdns_reg_pairs *usb_ln_vals;
-};
-
-struct cdns_regmap_cdb_context {
- struct udevice *dev;
- void __iomem *base;
- u8 reg_offset_shift;
+ struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
+ struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
+ struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
+ struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
};
struct cdns_sierra_phy {
size_t size;
struct regmap *regmap;
struct cdns_sierra_data *init_data;
- struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
+ struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
- struct regmap *regmap_phy_config_ctrl;
+ struct regmap *regmap_phy_pcs_common_cdb;
+ struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
+ struct regmap *regmap_phy_pma_common_cdb;
+ struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
+ struct regmap_field *pma_cmn_ready;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
- struct clk *clk;
- struct clk *cmn_refclk;
- struct clk *cmn_refclk1;
+ struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
+ struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
+ struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
int nsubnodes;
u32 num_lanes;
bool autoconf;
+ unsigned int already_configured;
};
static inline int cdns_reset_assert(struct reset_control *rst)
return NULL;
for (index = 0; index < sp->nsubnodes; index++) {
- if (phy->id == sp->phys[index].mlane)
- return &sp->phys[index];
+ if (phy->id == sp->phys[index]->mlane)
+ return sp->phys[index];
}
return NULL;
{
struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
+ struct cdns_sierra_data *init_data = phy->init_data;
+ struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
+ enum cdns_sierra_phy_type phy_type = ins->phy_type;
+ enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
+ struct cdns_sierra_vals *phy_pma_ln_vals;
+ const struct cdns_reg_pairs *reg_pairs;
+ struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap;
+ u32 num_regs;
int i, j;
- struct cdns_reg_pairs *cmn_vals, *ln_vals;
- u32 num_cmn_regs, num_ln_regs;
/* Initialise the PHY registers, unless auto configured */
- if (phy->autoconf)
+ if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1)
return 0;
- clk_set_rate(phy->cmn_refclk, 25000000);
- clk_set_rate(phy->cmn_refclk1, 25000000);
-
- if (ins->phy_type == PHY_TYPE_PCIE) {
- num_cmn_regs = phy->init_data->pcie_cmn_regs;
- num_ln_regs = phy->init_data->pcie_ln_regs;
- cmn_vals = phy->init_data->pcie_cmn_vals;
- ln_vals = phy->init_data->pcie_ln_vals;
- } else if (ins->phy_type == PHY_TYPE_USB3) {
- num_cmn_regs = phy->init_data->usb_cmn_regs;
- num_ln_regs = phy->init_data->usb_ln_regs;
- cmn_vals = phy->init_data->usb_cmn_vals;
- ln_vals = phy->init_data->usb_ln_vals;
- } else {
- return -EINVAL;
+ clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
+ clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
+
+ /* PHY PCS common registers configurations */
+ pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pcs_cmn_vals) {
+ reg_pairs = pcs_cmn_vals->reg_pairs;
+ num_regs = pcs_cmn_vals->num_regs;
+ regmap = phy->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
}
- regmap = phy->regmap_common_cdb;
- for (j = 0; j < num_cmn_regs ; j++)
- regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
+ /* PHY PMA lane registers configurations */
+ phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (phy_pma_ln_vals) {
+ reg_pairs = phy_pma_ln_vals->reg_pairs;
+ num_regs = phy_pma_ln_vals->num_regs;
+ for (i = 0; i < ins->num_lanes; i++) {
+ regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
+ }
+ }
+
+ /* PMA common registers configurations */
+ pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_cmn_vals) {
+ reg_pairs = pma_cmn_vals->reg_pairs;
+ num_regs = pma_cmn_vals->num_regs;
+ regmap = phy->regmap_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
+ }
- for (i = 0; i < ins->num_lanes; i++) {
- for (j = 0; j < num_ln_regs ; j++) {
+ /* PMA TX lane registers configurations */
+ pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_ln_vals) {
+ reg_pairs = pma_ln_vals->reg_pairs;
+ num_regs = pma_ln_vals->num_regs;
+ for (i = 0; i < ins->num_lanes; i++) {
regmap = phy->regmap_lane_cdb[i + ins->mlane];
- regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
}
}
u32 val;
int ret;
+ if (sp->already_configured) {
+ usleep_range(5000, 10000);
+ return 0;
+ }
+
+ if (sp->nsubnodes == 1) {
+ /* Take the PHY out of reset */
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
+ }
+
/* Take the PHY lane group out of reset */
ret = reset_deassert_bulk(ins->lnk_rst);
if (ret) {
return ret;
}
+ if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
+ ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
+ val, !val, 1000, PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for PHY status ready\n");
+ return ret;
+ }
+ }
+
+ /*
+ * Wait for cmn_ready assertion
+ * PHY_PMA_CMN_CTRL[0] == 1
+ */
+ ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,
+ 1000, PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for CMN ready\n");
+ return ret;
+ }
+
ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
val, val, 1000, PLL_LOCK_TIME);
if (ret < 0)
.reset = cdns_sierra_phy_reset,
};
+struct cdns_sierra_pll_mux_sel {
+ enum cdns_sierra_cmn_plllc mux_sel;
+ u32 table[2];
+ const char *node_name;
+ u32 num_parents;
+ u32 parents[2];
+};
+
+static struct cdns_sierra_pll_mux_sel pll_clk_mux_sel[] = {
+ {
+ .num_parents = 2,
+ .parents = { PLL0_REFCLK, PLL1_REFCLK },
+ .mux_sel = CMN_PLLLC,
+ .table = { 0, 1 },
+ .node_name = "pll_cmnlc",
+ },
+ {
+ .num_parents = 2,
+ .parents = { PLL1_REFCLK, PLL0_REFCLK },
+ .mux_sel = CMN_PLLLC1,
+ .table = { 1, 0 },
+ .node_name = "pll_cmnlc1",
+ },
+};
+
+static int cdns_sierra_pll_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct udevice *dev = clk->dev;
+ struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
+ struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
+ struct cdns_sierra_phy *sp = priv->sp;
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
+ if (parent->dev == priv->parent_clks[i]->dev)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(priv->parent_clks))
+ return -EINVAL;
+
+ ret = regmap_field_write(sp->cmn_refrcv_refclk_plllc1en_preg[data[clk->id].mux_sel], i);
+ ret |= regmap_field_write(sp->cmn_refrcv_refclk_termen_preg[data[clk->id].mux_sel], i);
+ ret |= regmap_field_write(sp->cmn_plllc_pfdclk1_sel_preg[data[clk->id].mux_sel],
+ data[clk->id].table[i]);
+
+ return ret;
+}
+
+static const struct clk_ops cdns_sierra_pll_mux_ops = {
+ .set_parent = cdns_sierra_pll_mux_set_parent,
+};
+
+int cdns_sierra_pll_mux_probe(struct udevice *dev)
+{
+ struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
+ struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
+ struct clk *clk;
+ int i, j;
+
+ for (j = 0; j < SIERRA_NUM_CMN_PLLC; j++) {
+ for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
+ clk = sp->input_clks[data[j].parents[i]];
+ if (IS_ERR_OR_NULL(clk)) {
+ dev_err(dev, "No parent clock for PLL mux clocks\n");
+ return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
+ }
+ priv->parent_clks[i] = clk;
+ }
+ }
+
+ priv->sp = dev_get_priv(dev->parent);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(cdns_sierra_pll_mux_clk) = {
+ .name = "cdns_sierra_mux_clk",
+ .id = UCLASS_CLK,
+ .priv_auto = sizeof(struct cdns_sierra_pll_mux),
+ .ops = &cdns_sierra_pll_mux_ops,
+ .probe = cdns_sierra_pll_mux_probe,
+ .plat_auto = sizeof(struct cdns_sierra_pll_mux_sel) * SIERRA_NUM_CMN_PLLC,
+};
+
+static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct driver *cdns_sierra_clk_drv;
+ struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel;
+ int i, rc;
+
+ cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk");
+ if (!cdns_sierra_clk_drv) {
+ dev_err(dev, "Can not find driver 'cdns_sierra_mux_clk'\n");
+ return -ENOENT;
+ }
+
+ rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk",
+ data, dev_ofnode(dev), NULL);
+ if (rc) {
+ dev_err(dev, "cannot bind driver for clock %s\n",
+ clk_names[i]);
+ }
+
+ return 0;
+}
+
static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
ofnode child)
{
+ u32 phy_type;
+
if (ofnode_read_u32(child, "reg", &inst->mlane))
return -EINVAL;
if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
return -EINVAL;
- if (ofnode_read_u32(child, "cdns,phy-type", &inst->phy_type))
+ if (ofnode_read_u32(child, "cdns,phy-type", &phy_type))
+ return -EINVAL;
+
+ switch (phy_type) {
+ case PHY_TYPE_PCIE:
+ inst->phy_type = TYPE_PCIE;
+ break;
+ case PHY_TYPE_USB3:
+ inst->phy_type = TYPE_USB;
+ break;
+ case PHY_TYPE_QSGMII:
+ inst->phy_type = TYPE_QSGMII;
+ break;
+ default:
return -EINVAL;
+ }
+
+ inst->ssc_mode = EXTERNAL_SSC;
+ ofnode_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);
return 0;
}
{
struct udevice *dev = sp->dev;
struct regmap_field *field;
+ struct reg_field reg_field;
struct regmap *regmap;
int i;
}
sp->macro_id_type = field;
- regmap = sp->regmap_phy_config_ctrl;
+ for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
+ reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
+ field = devm_regmap_field_alloc(dev, regmap, reg_field);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->cmn_plllc_pfdclk1_sel_preg[i] = field;
+
+ reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
+ field = devm_regmap_field_alloc(dev, regmap, reg_field);
+ if (IS_ERR(field)) {
+ dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;
+
+ reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
+ field = devm_regmap_field_alloc(dev, regmap, reg_field);
+ if (IS_ERR(field)) {
+ dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->cmn_refrcv_refclk_termen_preg[i] = field;
+ }
+
+ regmap = sp->regmap_phy_pcs_common_cdb;
field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
if (IS_ERR(field)) {
dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
}
sp->phy_pll_cfg_1 = field;
+ regmap = sp->regmap_phy_pma_common_cdb;
+ field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ sp->pma_cmn_ready = field;
+
for (i = 0; i < SIERRA_MAX_LANES; i++) {
regmap = sp->regmap_lane_cdb[i];
field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
return PTR_ERR(field);
}
- sp->pllctrl_lock[i] = field;
+ sp->pllctrl_lock[i] = field;
+ }
+
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ regmap = sp->regmap_phy_pcs_lane_cdb[i];
+ field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->phy_iso_link_ctrl_1[i] = field;
}
return 0;
}
sp->regmap_common_cdb = regmap;
- regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET,
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PCS_COMMON_OFFSET,
block_offset_shift, reg_offset_shift);
if (IS_ERR(regmap)) {
- dev_err(dev, "Failed to init PHY config and control regmap\n");
+ dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
return PTR_ERR(regmap);
}
- sp->regmap_phy_config_ctrl = regmap;
+ sp->regmap_phy_pcs_common_cdb = regmap;
+
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, reg_offset_shift);
+ regmap = cdns_regmap_init(dev, base, block_offset,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pcs_lane_cdb[i] = regmap;
+ }
+
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pma_common_cdb = regmap;
+
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, reg_offset_shift);
+ regmap = cdns_regmap_init(dev, base, block_offset,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pma_lane_cdb[i] = regmap;
+ }
+
+ return 0;
+}
+
+static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
+{
+ const struct cdns_sierra_data *init_data = sp->init_data;
+ enum cdns_sierra_phy_type phy_t1, phy_t2, tmp_phy_type;
+ struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
+ struct cdns_sierra_vals *phy_pma_ln_vals;
+ const struct cdns_reg_pairs *reg_pairs;
+ struct cdns_sierra_vals *pcs_cmn_vals;
+ int i, j, node, mlane, num_lanes, ret;
+ enum cdns_sierra_ssc_mode ssc;
+ struct regmap *regmap;
+ u32 num_regs;
+
+ /* Maximum 2 links (subnodes) are supported */
+ if (sp->nsubnodes != 2)
+ return -EINVAL;
+
+ clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
+ clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
+
+ /* PHY configured to use both PLL LC and LC1 */
+ regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+
+ phy_t1 = sp->phys[0]->phy_type;
+ phy_t2 = sp->phys[1]->phy_type;
+
+ /*
+ * First configure the PHY for first link with phy_t1. Get the array
+ * values as [phy_t1][phy_t2][ssc].
+ */
+ for (node = 0; node < sp->nsubnodes; node++) {
+ if (node == 1) {
+ /*
+ * If first link with phy_t1 is configured, then
+ * configure the PHY for second link with phy_t2.
+ * Get the array values as [phy_t2][phy_t1][ssc].
+ */
+ tmp_phy_type = phy_t1;
+ phy_t1 = phy_t2;
+ phy_t2 = tmp_phy_type;
+ }
+
+ mlane = sp->phys[node]->mlane;
+ ssc = sp->phys[node]->ssc_mode;
+ num_lanes = sp->phys[node]->num_lanes;
+
+ /* PHY PCS common registers configurations */
+ pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
+ if (pcs_cmn_vals) {
+ reg_pairs = pcs_cmn_vals->reg_pairs;
+ num_regs = pcs_cmn_vals->num_regs;
+ regmap = sp->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
+ }
+
+ /* PHY PMA lane registers configurations */
+ phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc];
+ if (phy_pma_ln_vals) {
+ reg_pairs = phy_pma_ln_vals->reg_pairs;
+ num_regs = phy_pma_ln_vals->num_regs;
+ for (i = 0; i < num_lanes; i++) {
+ regmap = sp->regmap_phy_pma_lane_cdb[i + mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
+ }
+ }
+
+ /* PMA common registers configurations */
+ pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc];
+ if (pma_cmn_vals) {
+ reg_pairs = pma_cmn_vals->reg_pairs;
+ num_regs = pma_cmn_vals->num_regs;
+ regmap = sp->regmap_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
+ }
+
+ /* PMA TX lane registers configurations */
+ pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc];
+ if (pma_ln_vals) {
+ reg_pairs = pma_ln_vals->reg_pairs;
+ num_regs = pma_ln_vals->num_regs;
+ for (i = 0; i < num_lanes; i++) {
+ regmap = sp->regmap_lane_cdb[i + mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
+ }
+ }
+
+ if (phy_t1 == TYPE_QSGMII)
+ reset_deassert_bulk(sp->phys[node]->lnk_rst);
+ }
+
+ /* Take the PHY out of reset */
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
+
+ clk = devm_clk_get_optional(dev, "pll0_refclk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll0_refclk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->input_clks[PLL0_REFCLK] = clk;
+
+ clk = devm_clk_get_optional(dev, "pll1_refclk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll1_refclk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->input_clks[PLL1_REFCLK] = clk;
return 0;
}
+static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->input_clks[PHY_CLK] = clk;
+
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct reset_control *rst;
+
+ rst = devm_reset_control_get(dev, "sierra_reset");
+ if (IS_ERR(rst)) {
+ dev_err(dev, "failed to get reset\n");
+ return PTR_ERR(rst);
+ }
+ sp->phy_rst = rst;
+
+ return 0;
+}
+
+static int cdns_sierra_bind_link_nodes(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct driver *link_drv;
+ ofnode child;
+ int rc;
+
+ link_drv = lists_driver_lookup_name("sierra_phy_link");
+ if (!link_drv) {
+ dev_err(dev, "Cannot find driver 'sierra_phy_link'\n");
+ return -ENOENT;
+ }
+
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (!(ofnode_name_eq(child, "phy") ||
+ ofnode_name_eq(child, "link")))
+ continue;
+
+ rc = device_bind(dev, link_drv, "link", NULL, child, NULL);
+ if (rc) {
+ dev_err(dev, "cannot bind driver for link\n");
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int cdns_sierra_link_probe(struct udevice *dev)
+{
+ struct cdns_sierra_inst *inst = dev_get_priv(dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
+ struct reset_ctl_bulk *rst;
+ int ret, node;
+
+ rst = devm_reset_bulk_get_by_node(dev, dev_ofnode(dev));
+ if (IS_ERR(rst)) {
+ ret = PTR_ERR(rst);
+ dev_err(dev, "failed to get reset\n");
+ return ret;
+ }
+ inst->lnk_rst = rst;
+
+ ret = cdns_sierra_get_optional(inst, dev_ofnode(dev));
+ if (ret) {
+ dev_err(dev, "missing property in node\n");
+ return ret;
+ }
+ node = sp->nsubnodes;
+ sp->phys[node] = inst;
+ sp->nsubnodes += 1;
+ sp->num_lanes += inst->num_lanes;
+
+ /* If more than one subnode, configure the PHY as multilink */
+ if (!sp->autoconf && !sp->already_configured && sp->nsubnodes > 1) {
+ ret = cdns_sierra_phy_configure_multilink(sp);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sierra_phy_link) = {
+ .name = "sierra_phy_link",
+ .id = UCLASS_PHY,
+ .probe = cdns_sierra_link_probe,
+ .priv_auto = sizeof(struct cdns_sierra_inst),
+};
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
- int ret, node = 0;
- struct clk *clk;
- ofnode child;
+ int ret;
sp->dev = dev;
if (ret)
return ret;
- sp->clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(sp->clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(sp->clk);
- }
-
- sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
- if (IS_ERR(sp->phy_rst)) {
- dev_err(dev, "failed to get reset\n");
- return PTR_ERR(sp->phy_rst);
- }
-
- clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk = clk;
-
- clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk1 clock not found\n");
- ret = PTR_ERR(clk);
+ ret = cdns_sierra_phy_get_clocks(sp, dev);
+ if (ret)
return ret;
- }
- sp->cmn_refclk1 = clk;
- ret = clk_prepare_enable(sp->clk);
+ ret = cdns_sierra_pll_bind_of_clocks(sp);
if (ret)
return ret;
+ regmap_field_read(sp->pma_cmn_ready, &sp->already_configured);
+
+ if (!sp->already_configured) {
+ ret = cdns_sierra_phy_clk(sp);
+ if (ret)
+ return ret;
+
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
+ }
+
/* Check that PHY is present */
regmap_field_read(sp->macro_id_type, &id_value);
if (sp->init_data->id_value != id_value) {
}
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
+ /* Binding link nodes as children to serdes */
+ ret = cdns_sierra_bind_link_nodes(sp);
+ if (ret)
+ goto clk_disable;
- ofnode_for_each_subnode(child, dev_ofnode(dev)) {
- sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
- child);
- if (IS_ERR(sp->phys[node].lnk_rst)) {
- ret = PTR_ERR(sp->phys[node].lnk_rst);
- dev_err(dev, "failed to get reset %s\n",
- ofnode_get_name(child));
- goto put_child2;
- }
-
- if (!sp->autoconf) {
- ret = cdns_sierra_get_optional(&sp->phys[node], child);
- if (ret) {
- dev_err(dev, "missing property in node %s\n",
- ofnode_get_name(child));
- goto put_child;
- }
- }
- sp->num_lanes += sp->phys[node].num_lanes;
-
- node++;
- }
- sp->nsubnodes = node;
-
- /* If more than one subnode, configure the PHY as multilink */
- if (!sp->autoconf && sp->nsubnodes > 1)
- regmap_field_write(sp->phy_pll_cfg_1, 0x1);
-
- reset_control_deassert(sp->phy_rst);
dev_info(dev, "sierra probed\n");
return 0;
-put_child:
- node++;
-put_child2:
-
clk_disable:
- clk_disable_unprepare(sp->clk);
+ if (!sp->already_configured)
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
return ret;
}
* Need to put the subnode resets here though.
*/
for (i = 0; i < phy->nsubnodes; i++)
- reset_assert_bulk(phy->phys[i].lnk_rst);
+ reset_assert_bulk(phy->phys[i]->lnk_rst);
+
+ clk_disable_unprepare(phy->input_clks[PHY_CLK]);
return 0;
}
+/* QSGMII PHY PMA lane configuration */
+static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
+ {0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
+};
+
+static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {
+ .reg_pairs = qsgmii_phy_pma_ln_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),
+};
+
+/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {
+ {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
+};
+
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x0252, SIERRA_DET_STANDEC_E_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x0FFE, SIERRA_PSC_RX_A0_PREG},
+ {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
+ {0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
+ {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
+ {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
+ {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
+ {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
+ {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
+ {0x8422, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG},
+ {0x4111, SIERRA_DFE_SMP_RATESEL_PREG},
+ {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
+ {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG},
+ {0x0186, SIERRA_DEQ_GLUT0},
+ {0x0186, SIERRA_DEQ_GLUT1},
+ {0x0186, SIERRA_DEQ_GLUT2},
+ {0x0186, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x0861, SIERRA_DEQ_ALUT0},
+ {0x07E0, SIERRA_DEQ_ALUT1},
+ {0x079E, SIERRA_DEQ_ALUT2},
+ {0x071D, SIERRA_DEQ_ALUT3},
+ {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
+ {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
+ {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0033, SIERRA_DEQ_PICTRL_PREG},
+ {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
+ {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG},
+ {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
+ {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = {
+ .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs),
+};
+
+static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = {
+ .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs),
+};
+
+/* PCIE PHY PCS common configuration */
+static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
+ {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
+};
+
+static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
+ .reg_pairs = pcie_phy_pcs_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */
+static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = {
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
+};
+
+/*
+ * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,
+ * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
+ */
+static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x0004, SIERRA_PSC_LN_A3_PREG},
+ {0x0004, SIERRA_PSC_LN_A4_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = {
+ .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs),
+};
+
+static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = {
+ .reg_pairs = ml_pcie_100_no_ssc_ln_regs,
+ .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */
+static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = {
+ {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
+ {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
+ {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
+ {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
+ {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
+ {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
+ {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
+};
+
+/*
+ * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,
+ * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
+ */
+static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x0004, SIERRA_PSC_LN_A3_PREG},
+ {0x0004, SIERRA_PSC_LN_A4_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = {
+ .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs),
+};
+
+static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = {
+ .reg_pairs = ml_pcie_100_int_ssc_ln_regs,
+ .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */
+static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = {
+ {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
+ {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
+};
+
+/*
+ * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,
+ * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
+ */
+static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x0004, SIERRA_PSC_LN_A3_PREG},
+ {0x0004, SIERRA_PSC_LN_A4_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = {
+ .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs),
+};
+
+static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = {
+ .reg_pairs = ml_pcie_100_ext_ssc_ln_regs,
+ .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
+static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
+};
+
+/* refclk100MHz_32b_PCIe_ln_no_ssc */
+static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = {
+ .reg_pairs = cdns_pcie_cmn_regs_no_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc),
+};
+
+static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = {
+ .reg_pairs = cdns_pcie_ln_regs_no_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */
+static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = {
+ {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
+ {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
+ {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
+ {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
+ {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
+ {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
+ {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
+};
+
+/* refclk100MHz_32b_PCIe_ln_int_ssc */
+static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = {
+ .reg_pairs = cdns_pcie_cmn_regs_int_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc),
+};
+
+static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = {
+ .reg_pairs = cdns_pcie_ln_regs_int_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc),
+};
+
/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
/* refclk100MHz_32b_PCIe_ln_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
- {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
+ .reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
+};
+
+static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
+ .reg_pairs = cdns_pcie_ln_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
};
/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
{0x000F, SIERRA_DET_STANDEC_B_PREG},
- {0x00A5, SIERRA_DET_STANDEC_C_PREG},
+ {0x55A5, SIERRA_DET_STANDEC_C_PREG},
{0x69ad, SIERRA_DET_STANDEC_D_PREG},
{0x0241, SIERRA_DET_STANDEC_E_PREG},
- {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
+ {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
{0xCF00, SIERRA_PSM_DIAG_PREG},
{0x001F, SIERRA_PSC_TX_A0_PREG},
{0x0003, SIERRA_PSC_TX_A2_PREG},
{0x0003, SIERRA_PSC_TX_A3_PREG},
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
- {0x0619, SIERRA_PSC_RX_A1_PREG},
+ {0x0003, SIERRA_PSC_RX_A1_PREG},
{0x0003, SIERRA_PSC_RX_A2_PREG},
{0x0001, SIERRA_PSC_RX_A3_PREG},
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
- {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG},
- {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
- {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
- {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
- {0x8000, SIERRA_CREQ_SPARE_PREG},
+ {0x0000, SIERRA_CREQ_SPARE_PREG},
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
- {0x8453, SIERRA_CTLELUT_CTRL_PREG},
- {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG},
- {0x4110, SIERRA_DFE_SMP_RATESEL_PREG},
- {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
+ {0x8452, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
+ {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
+ {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
- {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG},
+ {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
{0x0014, SIERRA_DEQ_GLUT0},
{0x0014, SIERRA_DEQ_GLUT1},
{0x0014, SIERRA_DEQ_GLUT2},
{0x000F, SIERRA_LFPSFILT_NS_PREG},
{0x0009, SIERRA_LFPSFILT_RD_PREG},
{0x0001, SIERRA_LFPSFILT_MP_PREG},
+ {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
{0x8009, SIERRA_SDFILT_L2H_PREG},
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
};
+static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
+ .reg_pairs = cdns_usb_cmn_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
+};
+
+static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
+ .reg_pairs = cdns_usb_ln_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
+};
+
static const struct cdns_sierra_data cdns_map_sierra = {
- SIERRA_MACRO_ID,
- 0x2,
- 0x2,
- ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
- cdns_pcie_cmn_regs_ext_ssc,
- cdns_pcie_ln_regs_ext_ssc,
- cdns_usb_cmn_regs_ext_ssc,
- cdns_usb_ln_regs_ext_ssc,
+ .id_value = SIERRA_MACRO_ID,
+ .block_offset_shift = 0x2,
+ .reg_offset_shift = 0x2,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
+ },
+ },
+ .pma_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals
+ },
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
+ },
+ },
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ },
+ },
+ },
+ .pma_ln_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &pcie_100_no_ssc_ln_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
+ },
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
+ [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
+ },
+ },
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ },
+ },
+
+ },
};
static const struct cdns_sierra_data cdns_ti_map_sierra = {
- SIERRA_MACRO_ID,
- 0x0,
- 0x1,
- ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
- cdns_pcie_cmn_regs_ext_ssc,
- cdns_pcie_ln_regs_ext_ssc,
- cdns_usb_cmn_regs_ext_ssc,
- cdns_usb_ln_regs_ext_ssc,
+ .id_value = SIERRA_MACRO_ID,
+ .block_offset_shift = 0x0,
+ .reg_offset_shift = 0x1,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
+ },
+ },
+ .phy_pma_ln_vals = {
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_phy_pma_ln_vals,
+ [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
+ [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
+ },
+ },
+ },
+ .pma_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
+ },
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
+ },
+ },
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ },
+ },
+ },
+ .pma_ln_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &pcie_100_no_ssc_ln_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
+ },
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
+ [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
+ },
+ },
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ },
+ },
+ },
};
static const struct udevice_id cdns_sierra_id_table[] = {
*/
if (usb32 == 0) {
node = fdt_node_offset_by_compatible(
- blob, -1, "marvell,armada3700-ehci");
+ blob, -1, "marvell,armada-3700-ehci");
} else {
node = fdt_node_offset_by_compatible(
blob, -1, "marvell,armada3700-xhci");
if (IS_ERR(chip_cfg->hpipe3_base_addr))
return PTR_ERR(chip_cfg->hpipe3_base_addr);
- if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
+ if (device_is_compatible(dev, "marvell,comphy-a3700")) {
chip_cfg->comphy_init_map = comphy_a3700_init_serdes_map;
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
chip_cfg->rx_training = NULL;
static const struct udevice_id comphy_ids[] = {
{ .compatible = "marvell,mvebu-comphy" },
+ { .compatible = "marvell,comphy-a3700" },
{ }
};
#include <dm/device.h>
#include <dm/device_compat.h>
#include <generic-phy.h>
+#include <asm-generic/gpio.h>
struct nop_phy_priv {
struct clk_bulk bulk;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
+#if CONFIG_IS_ENABLED(DM_GPIO)
+static int nop_phy_reset(struct phy *phy)
+{
+ struct nop_phy_priv *priv = dev_get_priv(phy->dev);
+
+ /* Return if there is no gpio since it's optional */
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return 0;
+
+ return dm_gpio_set_value(&priv->reset_gpio, true);
+}
+#endif
+
static int nop_phy_init(struct phy *phy)
{
struct nop_phy_priv *priv = dev_get_priv(phy->dev);
+ int ret = 0;
- if (CONFIG_IS_ENABLED(CLK))
- return clk_enable_bulk(&priv->bulk);
+ if (CONFIG_IS_ENABLED(CLK)) {
+ ret = clk_enable_bulk(&priv->bulk);
+ if (ret)
+ return ret;
+ }
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ /* Take phy out of reset */
+ if (dm_gpio_is_valid(&priv->reset_gpio)) {
+ ret = dm_gpio_set_value(&priv->reset_gpio, false);
+ if (ret) {
+ if (CONFIG_IS_ENABLED(CLK))
+ clk_disable_bulk(&priv->bulk);
+ return ret;
+ }
+ }
+#endif
return 0;
}
static int nop_phy_probe(struct udevice *dev)
{
struct nop_phy_priv *priv = dev_get_priv(dev);
- int ret;
+ int ret = 0;
if (CONFIG_IS_ENABLED(CLK)) {
ret = clk_get_bulk(dev, &priv->bulk);
return ret;
}
}
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
+ &priv->reset_gpio,
+ GPIOD_IS_OUT);
+#endif
+ if (ret != -ENOENT)
+ return ret;
return 0;
}
static struct phy_ops nop_phy_ops = {
.init = nop_phy_init,
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ .reset = nop_phy_reset,
+#endif
};
U_BOOT_DRIVER(nop_phy) = {
tphy->phys[index] = instance;
index++;
- err = clk_get_optional_nodev(subnode, "ref",
- &instance->ref_clk);
+ err = clk_get_by_name_nodev_optional(subnode, "ref",
+ &instance->ref_clk);
if (err)
return err;
- err = clk_get_optional_nodev(subnode, "da_ref",
- &instance->da_ref_clk);
+ err = clk_get_by_name_nodev_optional(subnode, "da_ref",
+ &instance->da_ref_clk);
if (err)
return err;
}
int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk)
{
int i, ret, count;
+ struct udevice *phydev = dev;
bulk->count = 0;
/* Return if no phy declared */
- if (!dev_read_prop(dev, "phys", NULL))
- return 0;
+ if (!dev_read_prop(dev, "phys", NULL)) {
+ phydev = dev->parent;
+ if (!dev_read_prop(phydev, "phys", NULL)) {
+ pr_err("%s : no phys property\n", __func__);
+ return 0;
+ }
+ }
- count = dev_count_phandle_with_args(dev, "phys", "#phy-cells", 0);
- if (count < 1)
+ count = dev_count_phandle_with_args(phydev, "phys", "#phy-cells", 0);
+ if (count < 1) {
+ pr_err("%s : no phys found %d\n", __func__, count);
return count;
+ }
- bulk->phys = devm_kcalloc(dev, count, sizeof(struct phy), GFP_KERNEL);
+ bulk->phys = devm_kcalloc(phydev, count, sizeof(struct phy), GFP_KERNEL);
if (!bulk->phys)
return -ENOMEM;
for (i = 0; i < count; i++) {
- ret = generic_phy_get_by_index(dev, i, &bulk->phys[i]);
+ ret = generic_phy_get_by_index(phydev, i, &bulk->phys[i]);
if (ret) {
pr_err("Failed to get PHY%d for %s\n", i, dev->name);
return ret;
xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
}
+/* DP-specific initialization. */
+static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
+{
+ xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
+ L0_TXPMD_TM_45_OVER_DP_MAIN |
+ L0_TXPMD_TM_45_ENABLE_DP_MAIN |
+ L0_TXPMD_TM_45_OVER_DP_POST1 |
+ L0_TXPMD_TM_45_OVER_DP_POST2 |
+ L0_TXPMD_TM_45_ENABLE_DP_POST2);
+ xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
+ L0_TX_ANA_TM_118_FORCE_17_0);
+}
+
+/* SATA-specific initialization. */
+static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
+{
+ struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
+
+ xpsgtr_bypass_scrambler_8b10b(gtr_phy);
+
+ writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
+}
+
/* SGMII-specific initialization. */
static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
{
case ICM_PROTOCOL_SGMII:
xpsgtr_phy_init_sgmii(gtr_phy);
break;
- case ICM_PROTOCOL_DP:
case ICM_PROTOCOL_SATA:
- return -EINVAL;
+ xpsgtr_phy_init_sata(gtr_phy);
+ break;
+ case ICM_PROTOCOL_DP:
+ xpsgtr_phy_init_dp(gtr_phy);
+ break;
}
dev_dbg(gtr_dev->dev, "lane %u (type %u, protocol %u): init done\n",
return ret;
}
- if (wiz->lane_phy_type[id - 1] == PHY_TYPE_PCIE)
+ if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
else
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
help
Generic power domain implementation for TI K3 devices.
+config ZYNQMP_POWER_DOMAIN
+ bool "Enable the Xilinx ZynqMP Power domain driver"
+ depends on POWER_DOMAIN && ZYNQMP_FIRMWARE
+ help
+ Generic power domain implementation for Xilinx ZynqMP devices.
+ The driver should be enabled when system starts in very minimal
+ configuration and it is extended at run time. Then enabling
+ the driver will ensure that PMUFW enable access to requested IP.
+
endmenu
obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
+obj-$(CONFIG_ZYNQMP_POWER_DOMAIN) += zynqmp-power-domain.o
#include <common.h>
#include <asm/io.h>
#include <dm.h>
+#include <dm/device-internal.h>
#include <linux/err.h>
#include <linux/bitfield.h>
#include <power-domain-uclass.h>
+#include <reset-uclass.h>
#include <regmap.h>
#include <syscon.h>
-#define APPLE_PMGR_PS_TARGET GENMASK(3, 0)
+#define APPLE_PMGR_RESET BIT(31)
+#define APPLE_PMGR_DEV_DISABLE BIT(10)
+#define APPLE_PMGR_WAS_CLKGATED BIT(9)
+#define APPLE_PMGR_WAS_PWRGATED BIT(8)
#define APPLE_PMGR_PS_ACTUAL GENMASK(7, 4)
+#define APPLE_PMGR_PS_TARGET GENMASK(3, 0)
+
+#define APPLE_PMGR_FLAGS (APPLE_PMGR_WAS_CLKGATED | APPLE_PMGR_WAS_PWRGATED)
#define APPLE_PMGR_PS_ACTIVE 0xf
#define APPLE_PMGR_PS_PWRGATE 0x0
u32 offset; /* offset within regmap for this domain */
};
+static int apple_reset_of_xlate(struct reset_ctl *reset_ctl,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int apple_reset_request(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int apple_reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int apple_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct apple_pmgr_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+
+ regmap_update_bits(priv->regmap, priv->offset,
+ APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE,
+ APPLE_PMGR_DEV_DISABLE);
+ regmap_update_bits(priv->regmap, priv->offset,
+ APPLE_PMGR_FLAGS | APPLE_PMGR_RESET,
+ APPLE_PMGR_RESET);
+
+ return 0;
+}
+
+static int apple_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct apple_pmgr_priv *priv = dev_get_priv(reset_ctl->dev->parent);
+
+ regmap_update_bits(priv->regmap, priv->offset,
+ APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, 0);
+ regmap_update_bits(priv->regmap, priv->offset,
+ APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE, 0);
+
+ return 0;
+}
+
+struct reset_ops apple_reset_ops = {
+ .of_xlate = apple_reset_of_xlate,
+ .request = apple_reset_request,
+ .rfree = apple_reset_free,
+ .rst_assert = apple_reset_assert,
+ .rst_deassert = apple_reset_deassert,
+};
+
+static struct driver apple_reset_driver = {
+ .name = "apple_reset",
+ .id = UCLASS_RESET,
+ .ops = &apple_reset_ops,
+};
+
static int apple_pmgr_request(struct power_domain *power_domain)
{
return 0;
static int apple_pmgr_probe(struct udevice *dev)
{
struct apple_pmgr_priv *priv = dev_get_priv(dev);
+ struct udevice *child;
int ret;
ret = dev_power_domain_on(dev);
if (ret < 0)
return ret;
+ device_bind(dev, &apple_reset_driver, "apple_reset", NULL,
+ dev_ofnode(dev), &child);
+
return 0;
}
.family = "J7200",
.data = &j7200_pd_platdata,
},
+#elif CONFIG_SOC_K3_J721S2
+ {
+ .family = "J721S2",
+ .data = &j721s2_pd_platdata,
+ },
#endif
{ /* sentinel */ }
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, Xilinx. Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <misc.h>
+#include <power-domain-uclass.h>
+#include <linux/bitops.h>
+
+#include <zynqmp_firmware.h>
+
+#define NODE_ID_LOCATION 5
+
+static unsigned int xpm_configobject[] = {
+ /* HEADER */
+ 2, /* Number of remaining words in the header */
+ 1, /* Number of sections included in config object */
+ PM_CONFIG_OBJECT_TYPE_OVERLAY, /* Type of Config object as overlay */
+ /* SLAVE SECTION */
+
+ PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
+ 1, /* Number of slaves */
+
+ 0, /* Node ID which will be changed below */
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK |
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK |
+ PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+};
+
+static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
+ const u32 qos, const enum zynqmp_pm_request_ack ack)
+{
+ return xilinx_pm_request(PM_REQUEST_NODE, node, capabilities,
+ qos, ack, NULL);
+}
+
+static int zynqmp_power_domain_request(struct power_domain *power_domain)
+{
+ /* Record power domain id */
+ xpm_configobject[NODE_ID_LOCATION] = power_domain->id;
+
+ zynqmp_pmufw_load_config_object(xpm_configobject, sizeof(xpm_configobject));
+
+ return 0;
+}
+
+static int zynqmp_power_domain_free(struct power_domain *power_domain)
+{
+ /* nop now */
+ return 0;
+}
+
+static int zynqmp_power_domain_on(struct power_domain *power_domain)
+{
+ return zynqmp_pm_request_node(power_domain->id,
+ ZYNQMP_PM_CAPABILITY_ACCESS,
+ ZYNQMP_PM_MAX_QOS,
+ ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+}
+
+static int zynqmp_power_domain_off(struct power_domain *power_domain)
+{
+ /* nop now */
+ return 0;
+}
+
+struct power_domain_ops zynqmp_power_domain_ops = {
+ .request = zynqmp_power_domain_request,
+ .rfree = zynqmp_power_domain_free,
+ .on = zynqmp_power_domain_on,
+ .off = zynqmp_power_domain_off,
+};
+
+static int zynqmp_power_domain_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+U_BOOT_DRIVER(zynqmp_power_domain) = {
+ .name = "zynqmp_power_domain",
+ .id = UCLASS_POWER_DOMAIN,
+ .probe = zynqmp_power_domain_probe,
+ .ops = &zynqmp_power_domain_ops,
+};
static const struct udevice_id tps65941_ids[] = {
{ .compatible = "ti,tps659411", .data = TPS659411 },
+ { .compatible = "ti,tps659412", .data = TPS659411 },
{ .compatible = "ti,tps659413", .data = TPS659413 },
{ .compatible = "ti,lp876441", .data = LP876441 },
{ }
* reseted to snvs state. Hence we can't set the state here.
*/
if (plat->enablemask == HW_STATE_CONTROL)
- return -EINVAL;
+ return enable ? 0 : -EINVAL;
if (enable)
val = plat->enablemask;
val);
}
+static int bd71837_get_value(struct udevice *dev)
+{
+ unsigned int reg, range;
+ unsigned int tmp;
+ struct bd71837_plat *plat = dev_get_plat(dev);
+ int i;
+
+ reg = pmic_reg_read(dev->parent, plat->volt_reg);
+ if (((int)reg) < 0)
+ return reg;
+
+ range = reg & plat->rangemask;
+
+ reg &= plat->volt_mask;
+ reg >>= ffs(plat->volt_mask) - 1;
+
+ for (i = 0; i < plat->numranges; i++) {
+ struct bd71837_vrange *r = &plat->ranges[i];
+
+ if (plat->rangemask && ((plat->rangemask & range) !=
+ r->rangeval))
+ continue;
+
+ if (!vrange_find_value(r, reg, &tmp))
+ return tmp;
+ }
+
+ pr_err("Unknown voltage value read from pmic\n");
+
+ return -EINVAL;
+}
+
static int bd71837_set_value(struct udevice *dev, int uvolt)
{
unsigned int sel;
*/
if (!plat->dvs)
if (bd71837_get_enable(dev)) {
+ /* If the value is already set, skip the warning. */
+ if (bd71837_get_value(dev) == uvolt)
+ return 0;
pr_err("Only DVS bucks can be changed when enabled\n");
return -EINVAL;
}
plat->rangemask, sel);
}
-static int bd71837_get_value(struct udevice *dev)
-{
- unsigned int reg, range;
- unsigned int tmp;
- struct bd71837_plat *plat = dev_get_plat(dev);
- int i;
-
- reg = pmic_reg_read(dev->parent, plat->volt_reg);
- if (((int)reg) < 0)
- return reg;
-
- range = reg & plat->rangemask;
-
- reg &= plat->volt_mask;
- reg >>= ffs(plat->volt_mask) - 1;
-
- for (i = 0; i < plat->numranges; i++) {
- struct bd71837_vrange *r = &plat->ranges[i];
-
- if (plat->rangemask && ((plat->rangemask & range) !=
- r->rangeval))
- continue;
-
- if (!vrange_find_value(r, reg, &tmp))
- return tmp;
- }
-
- pr_err("Unknown voltage value read from pmic\n");
-
- return -EINVAL;
-}
-
static int bd71837_regulator_probe(struct udevice *dev)
{
struct bd71837_plat *plat = dev_get_plat(dev);
idx = 1;
} else if (idx == 34) {
idx = 3;
+ } else if (idx == 123) {
+ idx = 1;
} else if (idx == 1234) {
idx = 1;
} else {
depends on K3_DDRSS
prompt "K3 DDRSS Arch Support"
- default K3_J721E_DDRSS if SOC_K3_J721E
+ default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
default K3_AM64_DDRSS if SOC_K3_AM642
config K3_J721E_DDRSS
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
+#define SINGLE_DDR_SUBSYSTEM 0x1
+#define MULTI_DDR_SUBSYSTEM 0x2
+
+#define MULTI_DDR_CFG0 0x00114100
+#define MULTI_DDR_CFG1 0x00114104
+#define DDR_CFG_LOAD 0x00114110
+
+enum intrlv_gran {
+ GRAN_128B,
+ GRAN_512B,
+ GRAN_2KB,
+ GRAN_4KB,
+ GRAN_16KB,
+ GRAN_32KB,
+ GRAN_512KB,
+ GRAN_1GB,
+ GRAN_1_5GB,
+ GRAN_2GB,
+ GRAN_3GB,
+ GRAN_4GB,
+ GRAN_6GB,
+ GRAN_8GB,
+ GRAN_16GB
+};
+
+enum intrlv_size {
+ SIZE_0,
+ SIZE_128MB,
+ SIZE_256MB,
+ SIZE_512MB,
+ SIZE_1GB,
+ SIZE_2GB,
+ SIZE_3GB,
+ SIZE_4GB,
+ SIZE_6GB,
+ SIZE_8GB,
+ SIZE_12GB,
+ SIZE_16GB,
+ SIZE_32GB
+};
+
+struct k3_ddrss_data {
+ u32 flags;
+};
+
+enum ecc_enable {
+ DISABLE_ALL = 0,
+ ENABLE_0,
+ ENABLE_1,
+ ENABLE_ALL
+};
+
+enum emif_config {
+ INTERLEAVE_ALL = 0,
+ SEPR0,
+ SEPR1
+};
+
+enum emif_active {
+ EMIF_0 = 1,
+ EMIF_1,
+ EMIF_ALL
+};
+
+struct k3_msmc {
+ enum intrlv_gran gran;
+ enum intrlv_size size;
+ enum ecc_enable enable;
+ enum emif_config config;
+ enum emif_active active;
+};
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
u32 ddr_freq2;
u32 ddr_fhs_cnt;
struct udevice *vtt_supply;
+ u32 instance;
+ lpddr4_obj *driverdt;
+ lpddr4_config config;
+ lpddr4_privatedata pd;
};
-static lpddr4_obj *driverdt;
-static lpddr4_config config;
-static lpddr4_privatedata pd;
-
-static struct k3_ddrss_desc *ddrss;
-
struct reginitdata {
u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
offset = offset * 10 + (*i - '0'); } \
} while (0)
-static u32 k3_lpddr4_read_ddr_type(void)
+static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
{
u32 status = 0U;
u32 offset = 0U;
u32 regval = 0U;
u32 dram_class = 0U;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
- status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
+ status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val);
if (status > 0U) {
printf("%s: Failed to read DRAM_CLASS\n", __func__);
hang();
return dram_class;
}
-static void k3_lpddr4_freq_update(void)
+static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
{
unsigned int req_type, counter;
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
true, 10000, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
req_type = readl(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;
- debug("%s: received freq change req: req type = %d, req no. = %d\n",
- __func__, req_type, counter);
+ debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
+ __func__, req_type, counter, ddrss->instance);
if (req_type == 1)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
printf("%s: Invalid freq request type\n", __func__);
writel(0x1, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
false, 10, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
writel(0x0, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
}
}
-static void k3_lpddr4_ack_freq_upd_req(void)
+static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{
u32 dram_class;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
- dram_class = k3_lpddr4_read_ddr_type();
+ dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
- k3_lpddr4_freq_update();
+ k3_lpddr4_freq_update(ddrss);
break;
default:
printf("Unrecognized dram_class cannot update frequency!\n");
{
u32 dram_class;
int ret;
+ lpddr4_privatedata *pd = &ddrss->pd;
- dram_class = k3_lpddr4_read_ddr_type();
+ dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
lpddr4_infotype infotype)
{
if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
- k3_lpddr4_ack_freq_upd_req();
+ k3_lpddr4_ack_freq_upd_req(pd);
}
static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
{
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
+ struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
phys_addr_t reg;
int ret;
if (ret)
dev_err(dev, "clk get failed for osc clk %d\n", ret);
+ /* Reading instance number for multi ddr subystems */
+ if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) {
+ ret = dev_read_u32(dev, "instance", &ddrss->instance);
+ if (ret) {
+ dev_err(dev, "missing instance property");
+ return -EINVAL;
+ }
+ } else {
+ ddrss->instance = 0;
+ }
+
ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
if (ret)
dev_err(dev, "ddr freq1 not populated %d\n", ret);
return ret;
}
-void k3_lpddr4_probe(void)
+void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
u16 configsize = 0U;
+ lpddr4_config *config = &ddrss->config;
- status = driverdt->probe(&config, &configsize);
+ status = ddrss->driverdt->probe(config, &configsize);
if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
|| (configsize > SRAM_MAX)) {
}
}
-void k3_lpddr4_init(void)
+void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
+ lpddr4_config *config = &ddrss->config;
+ lpddr4_obj *driverdt = ddrss->driverdt;
+ lpddr4_privatedata *pd = &ddrss->pd;
- if ((sizeof(pd) != sizeof(lpddr4_privatedata))
- || (sizeof(pd) > SRAM_MAX)) {
+ if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) {
printf("%s: FAIL\n", __func__);
hang();
}
- config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
- config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
+ config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
+ config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
+
+ status = driverdt->init(pd, config);
- status = driverdt->init(&pd, &config);
+ /* linking ddr instance to lpddr4 */
+ pd->ddr_instance = (void *)ddrss;
if ((status > 0U) ||
- (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
- (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
- (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
+ (pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) ||
+ (pd->ctlinterrupthandler != config->ctlinterrupthandler) ||
+ (pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) {
printf("%s: FAIL\n", __func__);
hang();
} else {
}
}
-void populate_data_array_from_dt(struct reginitdata *reginit_data)
+void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss,
+ struct reginitdata *reginit_data)
{
int ret, i;
reginit_data->phy_regs_offs[i] = i;
}
-void k3_lpddr4_hardware_reg_init(void)
+void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
struct reginitdata reginitdata;
+ lpddr4_obj *driverdt = ddrss->driverdt;
+ lpddr4_privatedata *pd = &ddrss->pd;
- populate_data_array_from_dt(®initdata);
+ populate_data_array_from_dt(ddrss, ®initdata);
- status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs,
+ status = driverdt->writectlconfig(pd, reginitdata.ctl_regs,
reginitdata.ctl_regs_offs,
LPDDR4_INTR_CTL_REG_COUNT);
if (!status)
- status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs,
+ status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs,
reginitdata.pi_regs_offs,
LPDDR4_INTR_PHY_INDEP_REG_COUNT);
if (!status)
- status = driverdt->writephyconfig(&pd, reginitdata.phy_regs,
+ status = driverdt->writephyconfig(pd, reginitdata.phy_regs,
reginitdata.phy_regs_offs,
LPDDR4_INTR_PHY_REG_COUNT);
if (status) {
}
}
-void k3_lpddr4_start(void)
+void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
u32 regval = 0U;
u32 offset = 0U;
+ lpddr4_obj *driverdt = ddrss->driverdt;
+ lpddr4_privatedata *pd = &ddrss->pd;
TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
- status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
+ status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
printf("%s: Pre start FAIL\n", __func__);
hang();
}
- status = driverdt->start(&pd);
+ status = driverdt->start(pd);
if (status > 0U) {
printf("%s: FAIL\n", __func__);
hang();
}
- status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
+ status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
printf("%s: Post start FAIL\n", __func__);
hang();
static int k3_ddrss_probe(struct udevice *dev)
{
int ret;
-
- ddrss = dev_get_priv(dev);
+ struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
debug("%s(dev=%p)\n", __func__, dev);
writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
#endif
- driverdt = lpddr4_getinstance();
- k3_lpddr4_probe();
- k3_lpddr4_init();
- k3_lpddr4_hardware_reg_init();
+ ddrss->driverdt = lpddr4_getinstance();
+
+ k3_lpddr4_probe(ddrss);
+ k3_lpddr4_init(ddrss);
+ k3_lpddr4_hardware_reg_init(ddrss);
ret = k3_ddrss_init_freq(ddrss);
if (ret)
return ret;
- k3_lpddr4_start();
+ k3_lpddr4_start(ddrss);
return ret;
}
.get_info = k3_ddrss_get_info,
};
+static const struct k3_ddrss_data k3_data = {
+ .flags = SINGLE_DDR_SUBSYSTEM,
+};
+
+static const struct k3_ddrss_data j721s2_data = {
+ .flags = MULTI_DDR_SUBSYSTEM,
+};
+
static const struct udevice_id k3_ddrss_ids[] = {
- {.compatible = "ti,am64-ddrss"},
- {.compatible = "ti,j721e-ddrss"},
+ {.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
+ {.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
+ {.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
{}
};
.probe = k3_ddrss_probe,
.priv_auto = sizeof(struct k3_ddrss_desc),
};
+
+static int k3_msmc_set_config(struct k3_msmc *msmc)
+{
+ u32 ddr_cfg0 = 0;
+ u32 ddr_cfg1 = 0;
+
+ ddr_cfg0 |= msmc->gran << 24;
+ ddr_cfg0 |= msmc->size << 16;
+ /* heartbeat_per, bit[4:0] setting to 3 is advisable */
+ ddr_cfg0 |= 3;
+
+ /* Program MULTI_DDR_CFG0 */
+ writel(ddr_cfg0, MULTI_DDR_CFG0);
+
+ ddr_cfg1 |= msmc->enable << 16;
+ ddr_cfg1 |= msmc->config << 8;
+ ddr_cfg1 |= msmc->active;
+
+ /* Program MULTI_DDR_CFG1 */
+ writel(ddr_cfg1, MULTI_DDR_CFG1);
+
+ /* Program DDR_CFG_LOAD */
+ writel(0x60000000, DDR_CFG_LOAD);
+
+ return 0;
+}
+
+static int k3_msmc_probe(struct udevice *dev)
+{
+ struct k3_msmc *msmc = dev_get_priv(dev);
+ int ret = 0;
+
+ /* Read the granular size from DT */
+ ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran);
+ if (ret) {
+ dev_err(dev, "missing intrlv-gran property");
+ return -EINVAL;
+ }
+
+ /* Read the interleave region from DT */
+ ret = dev_read_u32(dev, "intrlv-size", &msmc->size);
+ if (ret) {
+ dev_err(dev, "missing intrlv-size property");
+ return -EINVAL;
+ }
+
+ /* Read ECC enable config */
+ ret = dev_read_u32(dev, "ecc-enable", &msmc->enable);
+ if (ret) {
+ dev_err(dev, "missing ecc-enable property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF configuration */
+ ret = dev_read_u32(dev, "emif-config", &msmc->config);
+ if (ret) {
+ dev_err(dev, "missing emif-config property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF active */
+ ret = dev_read_u32(dev, "emif-active", &msmc->active);
+ if (ret) {
+ dev_err(dev, "missing emif-active property");
+ return -EINVAL;
+ }
+
+ ret = k3_msmc_set_config(msmc);
+ if (ret) {
+ dev_err(dev, "error setting msmc config");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id k3_msmc_ids[] = {
+ { .compatible = "ti,j721s2-msmc"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_msmc) = {
+ .name = "k3_msmc",
+ .of_match = k3_msmc_ids,
+ .id = UCLASS_MISC,
+ .probe = k3_msmc_probe,
+ .priv_auto = sizeof(struct k3_msmc),
+ .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
+ void *ddr_instance;
};
struct lpddr4_debuginfo_s {
help
Say 'y' here to add support for TI' K3 remoteproc driver.
+config REMOTEPROC_TI_IPU
+ bool "Support for TI's K3 based IPU remoteproc driver"
+ select REMOTEPROC
+ depends on DM
+ depends on SPL_DRIVERS_MISC
+ depends on SPL_FS_LOADER
+ depends on OF_CONTROL
+ help
+ Say 'y' here to add support for TI' K3 remoteproc driver.
+
endmenu
obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
+obj-$(CONFIG_REMOTEPROC_TI_IPU) += ipu_rproc.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPU remoteproc driver for various SoCs
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Angela Stegmaier <angelabaker@ti.com>
+ * Venkateswara Rao Mandela <venkat.mandela@ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <elf.h>
+#include <env.h>
+#include <dm/of_access.h>
+#include <fs_loader.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <misc.h>
+#include <power-domain.h>
+#include <timer.h>
+#include <fs.h>
+#include <spl.h>
+#include <timer.h>
+#include <reset.h>
+#include <linux/bitmap.h>
+
+#define IPU1_LOAD_ADDR (0xa17ff000)
+#define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
+
+enum ipu_num {
+ IPU1 = 0,
+ IPU2,
+ RPROC_END_ENUMS,
+};
+
+#define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
+
+#define PAGE_SHIFT 12
+#define PAGESIZE_1M 0x0
+#define PAGESIZE_64K 0x1
+#define PAGESIZE_4K 0x2
+#define PAGESIZE_16M 0x3
+#define LE 0
+#define BE 1
+#define ELEMSIZE_8 0x0
+#define ELEMSIZE_16 0x1
+#define ELEMSIZE_32 0x2
+#define MIXED_TLB 0x0
+#define MIXED_CPU 0x1
+
+#define PGT_SMALLPAGE_SIZE 0x00001000
+#define PGT_LARGEPAGE_SIZE 0x00010000
+#define PGT_SECTION_SIZE 0x00100000
+#define PGT_SUPERSECTION_SIZE 0x01000000
+
+#define PGT_L1_DESC_PAGE 0x00001
+#define PGT_L1_DESC_SECTION 0x00002
+#define PGT_L1_DESC_SUPERSECTION 0x40002
+
+#define PGT_L1_DESC_PAGE_MASK 0xfffffC00
+#define PGT_L1_DESC_SECTION_MASK 0xfff00000
+#define PGT_L1_DESC_SUPERSECTION_MASK 0xff000000
+
+#define PGT_L1_DESC_SMALLPAGE_INDEX_SHIFT 12
+#define PGT_L1_DESC_LARGEPAGE_INDEX_SHIFT 16
+#define PGT_L1_DESC_SECTION_INDEX_SHIFT 20
+#define PGT_L1_DESC_SUPERSECTION_INDEX_SHIFT 24
+
+#define PGT_L2_DESC_SMALLPAGE 0x02
+#define PGT_L2_DESC_LARGEPAGE 0x01
+
+#define PGT_L2_DESC_SMALLPAGE_MASK 0xfffff000
+#define PGT_L2_DESC_LARGEPAGE_MASK 0xffff0000
+
+/*
+ * The memory for the page tables (256 KB per IPU) is placed just before
+ * the carveout memories for the remote processors. 16 KB of memory is
+ * needed for the L1 page table (4096 entries * 4 bytes per 1 MB section).
+ * Any smaller page (64 KB or 4 KB) entries are supported through L2 page
+ * tables (1 KB per table). The remaining 240 KB can provide support for
+ * 240 L2 page tables. Any remoteproc firmware image requiring more than
+ * 240 L2 page table entries would need more memory to be reserved.
+ */
+#define PAGE_TABLE_SIZE_L1 (0x00004000)
+#define PAGE_TABLE_SIZE_L2 (0x400)
+#define MAX_NUM_L2_PAGE_TABLES (240)
+#define PAGE_TABLE_SIZE_L2_TOTAL (MAX_NUM_L2_PAGE_TABLES * PAGE_TABLE_SIZE_L2)
+#define PAGE_TABLE_SIZE (PAGE_TABLE_SIZE_L1 + (PAGE_TABLE_SIZE_L2_TOTAL))
+
+/**
+ * struct omap_rproc_mem - internal memory structure
+ * @cpu_addr: MPU virtual address of the memory region
+ * @bus_addr: bus address used to access the memory region
+ * @dev_addr: device address of the memory region from DSP view
+ * @size: size of the memory region
+ */
+struct omap_rproc_mem {
+ void __iomem *cpu_addr;
+ phys_addr_t bus_addr;
+ u32 dev_addr;
+ size_t size;
+};
+
+struct ipu_privdata {
+ struct omap_rproc_mem mem;
+ struct list_head mappings;
+ const char *fw_name;
+ u32 bootaddr;
+ int id;
+ struct udevice *rdev;
+};
+
+typedef int (*handle_resource_t) (void *, int offset, int avail);
+
+unsigned int *page_table_l1 = (unsigned int *)0x0;
+unsigned int *page_table_l2 = (unsigned int *)0x0;
+
+/*
+ * Set maximum carveout size to 96 MB
+ */
+#define DRA7_RPROC_MAX_CO_SIZE (96 * 0x100000)
+
+/*
+ * These global variables are used for deriving the MMU page tables. They
+ * are initialized for each core with the appropriate values. The length
+ * of the array mem_bitmap is set as per a 96 MB carveout which the
+ * maximum set aside in the current memory map.
+ */
+unsigned long mem_base;
+unsigned long mem_size;
+unsigned long
+
+mem_bitmap[BITS_TO_LONGS(DRA7_RPROC_MAX_CO_SIZE >> PAGE_SHIFT)];
+unsigned long mem_count;
+
+unsigned int pgtable_l2_map[MAX_NUM_L2_PAGE_TABLES];
+unsigned int pgtable_l2_cnt;
+
+void *ipu_alloc_mem(struct udevice *dev, unsigned long len, unsigned long align)
+{
+ unsigned long mask;
+ unsigned long pageno;
+ int count;
+
+ count = ((len + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1)) >> PAGE_SHIFT;
+ mask = (1 << align) - 1;
+ pageno =
+ bitmap_find_next_zero_area(mem_bitmap, mem_count, 0, count, mask);
+ debug("%s: count %d mask %#lx pageno %#lx\n", __func__, count, mask,
+ pageno);
+
+ if (pageno >= mem_count) {
+ debug("%s: %s Error allocating memory; "
+ "Please check carveout size\n", __FILE__, __func__);
+ return NULL;
+ }
+
+ bitmap_set(mem_bitmap, pageno, count);
+ return (void *)(mem_base + (pageno << PAGE_SHIFT));
+}
+
+int find_pagesz(unsigned int virt, unsigned int phys, unsigned int len)
+{
+ int pg_sz_ind = -1;
+ unsigned int min_align = __ffs(virt);
+
+ if (min_align > __ffs(phys))
+ min_align = __ffs(phys);
+
+ if (min_align >= PGT_L1_DESC_SUPERSECTION_INDEX_SHIFT &&
+ len >= 0x1000000) {
+ pg_sz_ind = PAGESIZE_16M;
+ goto ret_block;
+ }
+ if (min_align >= PGT_L1_DESC_SECTION_INDEX_SHIFT &&
+ len >= 0x100000) {
+ pg_sz_ind = PAGESIZE_1M;
+ goto ret_block;
+ }
+ if (min_align >= PGT_L1_DESC_LARGEPAGE_INDEX_SHIFT &&
+ len >= 0x10000) {
+ pg_sz_ind = PAGESIZE_64K;
+ goto ret_block;
+ }
+ if (min_align >= PGT_L1_DESC_SMALLPAGE_INDEX_SHIFT &&
+ len >= 0x1000) {
+ pg_sz_ind = PAGESIZE_4K;
+ goto ret_block;
+ }
+
+ ret_block:
+ return pg_sz_ind;
+}
+
+int get_l2_pg_tbl_addr(unsigned int virt, unsigned int *pg_tbl_addr)
+{
+ int ret = -1;
+ int i = 0;
+ int match_found = 0;
+ unsigned int tag = (virt & PGT_L1_DESC_SECTION_MASK);
+
+ *pg_tbl_addr = 0;
+ for (i = 0; (i < pgtable_l2_cnt) && (match_found == 0); i++) {
+ if (tag == pgtable_l2_map[i]) {
+ *pg_tbl_addr =
+ ((unsigned int)page_table_l2) +
+ (i * PAGE_TABLE_SIZE_L2);
+ match_found = 1;
+ ret = 0;
+ }
+ }
+
+ if (match_found == 0 && i < MAX_NUM_L2_PAGE_TABLES) {
+ pgtable_l2_map[i] = tag;
+ pgtable_l2_cnt++;
+ *pg_tbl_addr =
+ ((unsigned int)page_table_l2) + (i * PAGE_TABLE_SIZE_L2);
+ ret = 0;
+ }
+
+ return ret;
+}
+
+int
+config_l2_pagetable(unsigned int virt, unsigned int phys,
+ unsigned int pg_sz, unsigned int pg_tbl_addr)
+{
+ int ret = -1;
+ unsigned int desc = 0;
+ int i = 0;
+ unsigned int *pg_tbl = (unsigned int *)pg_tbl_addr;
+
+ /*
+ * Pick bit 19:12 of the virtual address as index
+ */
+ unsigned int index = (virt & (~PGT_L1_DESC_SECTION_MASK)) >> PAGE_SHIFT;
+
+ switch (pg_sz) {
+ case PAGESIZE_64K:
+ desc =
+ (phys & PGT_L2_DESC_LARGEPAGE_MASK) | PGT_L2_DESC_LARGEPAGE;
+ for (i = 0; i < 16; i++)
+ pg_tbl[index + i] = desc;
+ ret = 0;
+ break;
+ case PAGESIZE_4K:
+ desc =
+ (phys & PGT_L2_DESC_SMALLPAGE_MASK) | PGT_L2_DESC_SMALLPAGE;
+ pg_tbl[index] = desc;
+ ret = 0;
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+unsigned int
+ipu_config_pagetable(struct udevice *dev, unsigned int virt, unsigned int phys,
+ unsigned int len)
+{
+ unsigned int index;
+ unsigned int l = len;
+ unsigned int desc;
+ int pg_sz = 0;
+ int i = 0, err = 0;
+ unsigned int pg_tbl_l2_addr = 0;
+ unsigned int tmp_pgsz;
+
+ if ((len & 0x0FFF) != 0)
+ return 0;
+
+ while (l > 0) {
+ pg_sz = find_pagesz(virt, phys, l);
+ index = virt >> PGT_L1_DESC_SECTION_INDEX_SHIFT;
+ switch (pg_sz) {
+ /*
+ * 16 MB super section
+ */
+ case PAGESIZE_16M:
+ /*
+ * Program the next 16 descriptors
+ */
+ desc =
+ (phys & PGT_L1_DESC_SUPERSECTION_MASK) |
+ PGT_L1_DESC_SUPERSECTION;
+ for (i = 0; i < 16; i++)
+ page_table_l1[index + i] = desc;
+ l -= PGT_SUPERSECTION_SIZE;
+ phys += PGT_SUPERSECTION_SIZE;
+ virt += PGT_SUPERSECTION_SIZE;
+ break;
+ /*
+ * 1 MB section
+ */
+ case PAGESIZE_1M:
+ desc =
+ (phys & PGT_L1_DESC_SECTION_MASK) |
+ PGT_L1_DESC_SECTION;
+ page_table_l1[index] = desc;
+ l -= PGT_SECTION_SIZE;
+ phys += PGT_SECTION_SIZE;
+ virt += PGT_SECTION_SIZE;
+ break;
+ /*
+ * 64 KB large page
+ */
+ case PAGESIZE_64K:
+ case PAGESIZE_4K:
+ if (pg_sz == PAGESIZE_64K)
+ tmp_pgsz = 0x10000;
+ else
+ tmp_pgsz = 0x1000;
+
+ err = get_l2_pg_tbl_addr(virt, &pg_tbl_l2_addr);
+ if (err != 0) {
+ debug
+ ("Unable to get level 2 PT address\n");
+ hang();
+ }
+ err =
+ config_l2_pagetable(virt, phys, pg_sz,
+ pg_tbl_l2_addr);
+ desc =
+ (pg_tbl_l2_addr & PGT_L1_DESC_PAGE_MASK) |
+ PGT_L1_DESC_PAGE;
+ page_table_l1[index] = desc;
+ l -= tmp_pgsz;
+ phys += tmp_pgsz;
+ virt += tmp_pgsz;
+ break;
+ case -1:
+ default:
+ return 0;
+ }
+ }
+
+ return len;
+}
+
+int da_to_pa(struct udevice *dev, int da)
+{
+ struct rproc_mem_entry *maps = NULL;
+ struct ipu_privdata *priv = dev_get_priv(dev);
+
+ list_for_each_entry(maps, &priv->mappings, node) {
+ if (da >= maps->da && da < (maps->da + maps->len))
+ return maps->dma + (da - maps->da);
+ }
+
+ return 0;
+}
+
+u32 ipu_config_mmu(u32 core_id, struct rproc *cfg)
+{
+ u32 i = 0;
+ u32 reg = 0;
+
+ /*
+ * Clear the entire pagetable location before programming the
+ * address into the MMU
+ */
+ memset((void *)cfg->page_table_addr, 0x00, PAGE_TABLE_SIZE);
+
+ for (i = 0; i < cfg->num_iommus; i++) {
+ u32 mmu_base = cfg->mmu_base_addr[i];
+
+ __raw_writel((int)cfg->page_table_addr, mmu_base + 0x4c);
+ reg = __raw_readl(mmu_base + 0x88);
+
+ /*
+ * enable bus-error back
+ */
+ __raw_writel(reg | 0x1, mmu_base + 0x88);
+
+ /*
+ * Enable the MMU IRQs during MMU programming for the
+ * late attachcase. This is to allow the MMU fault to be
+ * detected by the kernel.
+ *
+ * MULTIHITFAULT|EMMUMISS|TRANSLATIONFAULT|TABLEWALKFAULT
+ */
+ __raw_writel(0x1E, mmu_base + 0x1c);
+
+ /*
+ * emutlbupdate|TWLENABLE|MMUENABLE
+ */
+ __raw_writel(0x6, mmu_base + 0x44);
+ }
+
+ return 0;
+}
+
+/**
+ * enum ipu_mem - PRU core memory range identifiers
+ */
+enum ipu_mem {
+ PRU_MEM_IRAM = 0,
+ PRU_MEM_CTRL,
+ PRU_MEM_DEBUG,
+ PRU_MEM_MAX,
+};
+
+static int ipu_start(struct udevice *dev)
+{
+ struct ipu_privdata *priv;
+ struct reset_ctl reset;
+ struct rproc *cfg = NULL;
+ int ret;
+
+ priv = dev_get_priv(dev);
+
+ cfg = rproc_cfg_arr[priv->id];
+ if (cfg->config_peripherals)
+ cfg->config_peripherals(priv->id, cfg);
+
+ /*
+ * Start running the remote core
+ */
+ ret = reset_get_by_index(dev, 0, &reset);
+ if (ret < 0) {
+ dev_err(dev, "%s: error getting reset index %d\n", __func__, 0);
+ return ret;
+ }
+
+ ret = reset_deassert(&reset);
+ if (ret < 0) {
+ dev_err(dev, "%s: error deasserting reset %d\n", __func__, 0);
+ return ret;
+ }
+
+ ret = reset_get_by_index(dev, 1, &reset);
+ if (ret < 0) {
+ dev_err(dev, "%s: error getting reset index %d\n", __func__, 1);
+ return ret;
+ }
+
+ ret = reset_deassert(&reset);
+ if (ret < 0) {
+ dev_err(dev, "%s: error deasserting reset %d\n", __func__, 1);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ipu_stop(struct udevice *dev)
+{
+ return 0;
+}
+
+/**
+ * ipu_init() - Initialize the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int ipu_init(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ipu_add_res(struct udevice *dev, struct rproc_mem_entry *mapping)
+{
+ struct ipu_privdata *priv = dev_get_priv(dev);
+
+ list_add_tail(&mapping->node, &priv->mappings);
+ return 0;
+}
+
+static int ipu_load(struct udevice *dev, ulong addr, ulong size)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf32_Phdr *phdr; /* Program header structure pointer */
+ Elf32_Phdr proghdr;
+ int va;
+ int pa;
+ int i;
+
+ ehdr = (Elf32_Ehdr *)addr;
+ phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
+ /*
+ * Load each program header
+ */
+ for (i = 0; i < ehdr->e_phnum; ++i) {
+ memcpy(&proghdr, phdr, sizeof(Elf32_Phdr));
+
+ if (proghdr.p_type != PT_LOAD) {
+ ++phdr;
+ continue;
+ }
+
+ va = proghdr.p_paddr;
+ pa = da_to_pa(dev, va);
+ if (pa)
+ proghdr.p_paddr = pa;
+
+ void *dst = (void *)(uintptr_t)proghdr.p_paddr;
+ void *src = (void *)addr + proghdr.p_offset;
+
+ debug("Loading phdr %i to 0x%p (%i bytes)\n", i, dst,
+ proghdr.p_filesz);
+ if (proghdr.p_filesz)
+ memcpy(dst, src, proghdr.p_filesz);
+
+ flush_cache((unsigned long)dst, proghdr.p_memsz);
+
+ ++phdr;
+ }
+
+ return 0;
+}
+
+static const struct dm_rproc_ops ipu_ops = {
+ .init = ipu_init,
+ .start = ipu_start,
+ .stop = ipu_stop,
+ .load = ipu_load,
+ .add_res = ipu_add_res,
+ .config_pagetable = ipu_config_pagetable,
+ .alloc_mem = ipu_alloc_mem,
+};
+
+/*
+ * If the remotecore binary expects any peripherals to be setup before it has
+ * booted, configure them here.
+ *
+ * These functions are left empty by default as their operation is usecase
+ * specific.
+ */
+
+u32 ipu1_config_peripherals(u32 core_id, struct rproc *cfg)
+{
+ return 0;
+}
+
+u32 ipu2_config_peripherals(u32 core_id, struct rproc *cfg)
+{
+ return 0;
+}
+
+struct rproc_intmem_to_l3_mapping ipu1_intmem_to_l3_mapping = {
+ .num_entries = 1,
+ .mappings = {
+ /*
+ * L2 SRAM
+ */
+ {
+ .priv_addr = 0x55020000,
+ .l3_addr = 0x58820000,
+ .len = (64 * 1024)},
+ }
+};
+
+struct rproc_intmem_to_l3_mapping ipu2_intmem_to_l3_mapping = {
+ .num_entries = 1,
+ .mappings = {
+ /*
+ * L2 SRAM
+ */
+ {
+ .priv_addr = 0x55020000,
+ .l3_addr = 0x55020000,
+ .len = (64 * 1024)},
+ }
+};
+
+struct rproc ipu1_config = {
+ .num_iommus = 1,
+ .mmu_base_addr = {0x58882000, 0},
+ .load_addr = IPU1_LOAD_ADDR,
+ .core_name = "IPU1",
+ .firmware_name = "dra7-ipu1-fw.xem4",
+ .config_mmu = ipu_config_mmu,
+ .config_peripherals = ipu1_config_peripherals,
+ .intmem_to_l3_mapping = &ipu1_intmem_to_l3_mapping
+};
+
+struct rproc ipu2_config = {
+ .num_iommus = 1,
+ .mmu_base_addr = {0x55082000, 0},
+ .load_addr = IPU2_LOAD_ADDR,
+ .core_name = "IPU2",
+ .firmware_name = "dra7-ipu2-fw.xem4",
+ .config_mmu = ipu_config_mmu,
+ .config_peripherals = ipu2_config_peripherals,
+ .intmem_to_l3_mapping = &ipu2_intmem_to_l3_mapping
+};
+
+struct rproc *rproc_cfg_arr[2] = {
+ [IPU2] = &ipu2_config,
+ [IPU1] = &ipu1_config,
+};
+
+u32 spl_pre_boot_core(struct udevice *dev, u32 core_id)
+{
+ struct rproc *cfg = NULL;
+ unsigned long load_elf_status = 0;
+ int tablesz;
+
+ cfg = rproc_cfg_arr[core_id];
+ /*
+ * Check for valid elf image
+ */
+ if (!valid_elf_image(cfg->load_addr))
+ return 1;
+
+ if (rproc_find_resource_table(dev, cfg->load_addr, &tablesz))
+ cfg->has_rsc_table = 1;
+ else
+ cfg->has_rsc_table = 0;
+
+ /*
+ * Configure the MMU
+ */
+ if (cfg->config_mmu && cfg->has_rsc_table)
+ cfg->config_mmu(core_id, cfg);
+
+ /*
+ * Load the remote core. Fill the page table of the first(possibly
+ * only) IOMMU during ELF loading. Copy the page table to the second
+ * IOMMU before running the remote core.
+ */
+
+ page_table_l1 = (unsigned int *)cfg->page_table_addr;
+ page_table_l2 =
+ (unsigned int *)(cfg->page_table_addr + PAGE_TABLE_SIZE_L1);
+ mem_base = cfg->cma_base;
+ mem_size = cfg->cma_size;
+ memset(mem_bitmap, 0x00, sizeof(mem_bitmap));
+ mem_count = (cfg->cma_size >> PAGE_SHIFT);
+
+ /*
+ * Clear variables used for level 2 page table allocation
+ */
+ memset(pgtable_l2_map, 0x00, sizeof(pgtable_l2_map));
+ pgtable_l2_cnt = 0;
+
+ load_elf_status = rproc_parse_resource_table(dev, cfg);
+ if (load_elf_status == 0) {
+ debug("load_elf_image_phdr returned error for core %s\n",
+ cfg->core_name);
+ return 1;
+ }
+
+ flush_cache(cfg->page_table_addr, PAGE_TABLE_SIZE);
+
+ return 0;
+}
+
+static fdt_addr_t ipu_parse_mem_nodes(struct udevice *dev, char *name,
+ int privid, fdt_size_t *sizep)
+{
+ int ret;
+ u32 sp;
+ ofnode mem_node;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), name, &sp);
+ if (ret) {
+ dev_err(dev, "memory-region node fetch failed %d\n", ret);
+ return ret;
+ }
+
+ mem_node = ofnode_get_by_phandle(sp);
+ if (!ofnode_valid(mem_node))
+ return -EINVAL;
+
+ return ofnode_get_addr_size_index(mem_node, 0, sizep);
+}
+
+/**
+ * ipu_probe() - Basic probe
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int ipu_probe(struct udevice *dev)
+{
+ struct ipu_privdata *priv;
+ struct rproc *cfg = NULL;
+ struct reset_ctl reset;
+ static const char *const ipu_mem_names[] = { "l2ram" };
+ int ret;
+ fdt_size_t sizep;
+
+ priv = dev_get_priv(dev);
+
+ priv->mem.bus_addr =
+ devfdt_get_addr_size_name(dev,
+ ipu_mem_names[0],
+ (fdt_addr_t *)&priv->mem.size);
+
+ ret = reset_get_by_index(dev, 2, &reset);
+ if (ret < 0) {
+ dev_err(dev, "%s: error getting reset index %d\n", __func__, 2);
+ return ret;
+ }
+
+ ret = reset_deassert(&reset);
+ if (ret < 0) {
+ dev_err(dev, "%s: error deasserting reset %d\n", __func__, 2);
+ return ret;
+ }
+
+ if (priv->mem.bus_addr == FDT_ADDR_T_NONE) {
+ dev_err(dev, "%s bus address not found\n", ipu_mem_names[0]);
+ return -EINVAL;
+ }
+ priv->mem.cpu_addr = map_physmem(priv->mem.bus_addr,
+ priv->mem.size, MAP_NOCACHE);
+
+ if (devfdt_get_addr(dev) == 0x58820000)
+ priv->id = 0;
+ else
+ priv->id = 1;
+
+ cfg = rproc_cfg_arr[priv->id];
+ cfg->cma_base = ipu_parse_mem_nodes(dev, "memory-region", priv->id,
+ &sizep);
+ cfg->cma_size = sizep;
+
+ cfg->page_table_addr = ipu_parse_mem_nodes(dev, "pg-tbl", priv->id,
+ &sizep);
+
+ dev_info(dev,
+ "ID %d memory %8s: bus addr %pa size 0x%zx va %p da 0x%x\n",
+ priv->id, ipu_mem_names[0], &priv->mem.bus_addr,
+ priv->mem.size, priv->mem.cpu_addr, priv->mem.dev_addr);
+
+ INIT_LIST_HEAD(&priv->mappings);
+ if (spl_pre_boot_core(dev, priv->id))
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id ipu_ids[] = {
+ {.compatible = "ti,dra7-ipu"},
+ {}
+};
+
+U_BOOT_DRIVER(ipu) = {
+ .name = "ipu",
+ .of_match = ipu_ids,
+ .id = UCLASS_REMOTEPROC,
+ .ops = &ipu_ops,
+ .probe = ipu_probe,
+ .priv_auto = sizeof(struct ipu_privdata),
+};
* struct k3_sysctrler_privdata - Structure representing System Controller data.
* @chan_tx: Transmit mailbox channel
* @chan_rx: Receive mailbox channel
+ * @chan_boot_notify: Boot notification channel
* @desc: SoC description for this instance
* @seq_nr: Counter for number of messages sent.
+ * @has_boot_notify: Has separate boot notification channel
*/
struct k3_sysctrler_privdata {
struct mbox_chan chan_tx;
struct mbox_chan chan_rx;
+ struct mbox_chan chan_boot_notify;
struct k3_sysctrler_desc *desc;
u32 seq_nr;
+ bool has_boot_notify;
};
static inline
debug("%s(dev=%p)\n", __func__, dev);
/* Receive the boot notification. Note that it is sent only once. */
- ret = mbox_recv(&priv->chan_rx, &msg, priv->desc->max_rx_timeout_us);
+ ret = mbox_recv(priv->has_boot_notify ? &priv->chan_boot_notify :
+ &priv->chan_rx, &msg, priv->desc->max_rx_timeout_us);
if (ret) {
dev_err(dev, "%s: Boot Notification response failed. ret = %d\n",
__func__, ret);
return ret;
}
+ /* Some SoCs may have a optional channel for boot notification. */
+ priv->has_boot_notify = 1;
+ ret = mbox_get_by_name(dev, "boot_notify", &priv->chan_boot_notify);
+ if (ret == -ENODATA) {
+ dev_dbg(dev, "%s: Acquiring optional Boot_notify failed. ret = %d. Using Rx\n",
+ __func__, ret);
+ priv->has_boot_notify = 0;
+ } else if (ret) {
+ dev_err(dev, "%s: Acquiring boot_notify channel failed. ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
return 0;
}
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <common.h>
+#include <elf.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
+#include <virtio_ring.h>
#include <remoteproc.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm.h>
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct resource_table {
+ u32 ver;
+ u32 num;
+ u32 reserved[2];
+ u32 offset[0];
+} __packed;
+
+typedef int (*handle_resource_t) (struct udevice *, void *, int offset, int avail);
+
+static struct resource_table *rsc_table;
/**
* for_each_remoteproc_device() - iterate through the list of rproc devices
return 0;
}
+/**
+ * rproc_add_res() - After parsing the resource table add the mappings
+ * @dev: device we finished probing
+ * @mapping: rproc_mem_entry for the resource
+ *
+ * Return: if the remote proc driver has a add_res routine, invokes it and
+ * hands over the return value. overall, 0 if all went well, else appropriate
+ * error value.
+ */
+static int rproc_add_res(struct udevice *dev, struct rproc_mem_entry *mapping)
+{
+ const struct dm_rproc_ops *ops = rproc_get_ops(dev);
+
+ if (!ops->add_res)
+ return -ENOSYS;
+
+ return ops->add_res(dev, mapping);
+}
+
+/**
+ * rproc_alloc_mem() - After parsing the resource table allocat mem
+ * @dev: device we finished probing
+ * @len: rproc_mem_entry for the resource
+ * @align: alignment for the resource
+ *
+ * Return: if the remote proc driver has a add_res routine, invokes it and
+ * hands over the return value. overall, 0 if all went well, else appropriate
+ * error value.
+ */
+static void *rproc_alloc_mem(struct udevice *dev, unsigned long len,
+ unsigned long align)
+{
+ const struct dm_rproc_ops *ops;
+
+ ops = rproc_get_ops(dev);
+ if (!ops) {
+ debug("%s driver has no ops?\n", dev->name);
+ return NULL;
+ }
+
+ if (ops->alloc_mem)
+ return ops->alloc_mem(dev, len, align);
+
+ return NULL;
+}
+
+/**
+ * rproc_config_pagetable() - Configure page table for remote processor
+ * @dev: device we finished probing
+ * @virt: Virtual address of the resource
+ * @phys: Physical address the resource
+ * @len: length the resource
+ *
+ * Return: if the remote proc driver has a add_res routine, invokes it and
+ * hands over the return value. overall, 0 if all went well, else appropriate
+ * error value.
+ */
+static int rproc_config_pagetable(struct udevice *dev, unsigned int virt,
+ unsigned int phys, unsigned int len)
+{
+ const struct dm_rproc_ops *ops;
+
+ ops = rproc_get_ops(dev);
+ if (!ops) {
+ debug("%s driver has no ops?\n", dev->name);
+ return -EINVAL;
+ }
+
+ if (ops->config_pagetable)
+ return ops->config_pagetable(dev, virt, phys, len);
+
+ return 0;
+}
+
UCLASS_DRIVER(rproc) = {
.id = UCLASS_REMOTEPROC,
.name = "remoteproc",
{
return _rproc_ops_wrapper(id, RPROC_RUNNING);
};
+
+
+static int handle_trace(struct udevice *dev, struct fw_rsc_trace *rsc,
+ int offset, int avail)
+{
+ if (sizeof(*rsc) > avail) {
+ debug("trace rsc is truncated\n");
+ return -EINVAL;
+ }
+
+ /*
+ * make sure reserved bytes are zeroes
+ */
+ if (rsc->reserved) {
+ debug("trace rsc has non zero reserved bytes\n");
+ return -EINVAL;
+ }
+
+ debug("trace rsc: da 0x%x, len 0x%x\n", rsc->da, rsc->len);
+
+ return 0;
+}
+
+static int handle_devmem(struct udevice *dev, struct fw_rsc_devmem *rsc,
+ int offset, int avail)
+{
+ struct rproc_mem_entry *mapping;
+
+ if (sizeof(*rsc) > avail) {
+ debug("devmem rsc is truncated\n");
+ return -EINVAL;
+ }
+
+ /*
+ * make sure reserved bytes are zeroes
+ */
+ if (rsc->reserved) {
+ debug("devmem rsc has non zero reserved bytes\n");
+ return -EINVAL;
+ }
+
+ debug("devmem rsc: pa 0x%x, da 0x%x, len 0x%x\n",
+ rsc->pa, rsc->da, rsc->len);
+
+ rproc_config_pagetable(dev, rsc->da, rsc->pa, rsc->len);
+
+ mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
+ if (!mapping)
+ return -ENOMEM;
+
+ /*
+ * We'll need this info later when we'll want to unmap everything
+ * (e.g. on shutdown).
+ *
+ * We can't trust the remote processor not to change the resource
+ * table, so we must maintain this info independently.
+ */
+ mapping->dma = rsc->pa;
+ mapping->da = rsc->da;
+ mapping->len = rsc->len;
+ rproc_add_res(dev, mapping);
+
+ debug("mapped devmem pa 0x%x, da 0x%x, len 0x%x\n",
+ rsc->pa, rsc->da, rsc->len);
+
+ return 0;
+}
+
+static int handle_carveout(struct udevice *dev, struct fw_rsc_carveout *rsc,
+ int offset, int avail)
+{
+ struct rproc_mem_entry *mapping;
+
+ if (sizeof(*rsc) > avail) {
+ debug("carveout rsc is truncated\n");
+ return -EINVAL;
+ }
+
+ /*
+ * make sure reserved bytes are zeroes
+ */
+ if (rsc->reserved) {
+ debug("carveout rsc has non zero reserved bytes\n");
+ return -EINVAL;
+ }
+
+ debug("carveout rsc: da %x, pa %x, len %x, flags %x\n",
+ rsc->da, rsc->pa, rsc->len, rsc->flags);
+
+ rsc->pa = (uintptr_t)rproc_alloc_mem(dev, rsc->len, 8);
+ if (!rsc->pa) {
+ debug
+ ("failed to allocate carveout rsc: da %x, pa %x, len %x, flags %x\n",
+ rsc->da, rsc->pa, rsc->len, rsc->flags);
+ return -ENOMEM;
+ }
+ rproc_config_pagetable(dev, rsc->da, rsc->pa, rsc->len);
+
+ /*
+ * Ok, this is non-standard.
+ *
+ * Sometimes we can't rely on the generic iommu-based DMA API
+ * to dynamically allocate the device address and then set the IOMMU
+ * tables accordingly, because some remote processors might
+ * _require_ us to use hard coded device addresses that their
+ * firmware was compiled with.
+ *
+ * In this case, we must use the IOMMU API directly and map
+ * the memory to the device address as expected by the remote
+ * processor.
+ *
+ * Obviously such remote processor devices should not be configured
+ * to use the iommu-based DMA API: we expect 'dma' to contain the
+ * physical address in this case.
+ */
+ mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
+ if (!mapping)
+ return -ENOMEM;
+
+ /*
+ * We'll need this info later when we'll want to unmap
+ * everything (e.g. on shutdown).
+ *
+ * We can't trust the remote processor not to change the
+ * resource table, so we must maintain this info independently.
+ */
+ mapping->dma = rsc->pa;
+ mapping->da = rsc->da;
+ mapping->len = rsc->len;
+ rproc_add_res(dev, mapping);
+
+ debug("carveout mapped 0x%x to 0x%x\n", rsc->da, rsc->pa);
+
+ return 0;
+}
+
+#define RPROC_PAGE_SHIFT 12
+#define RPROC_PAGE_SIZE BIT(RPROC_PAGE_SHIFT)
+#define RPROC_PAGE_ALIGN(x) (((x) + (RPROC_PAGE_SIZE - 1)) & ~(RPROC_PAGE_SIZE - 1))
+
+static int alloc_vring(struct udevice *dev, struct fw_rsc_vdev *rsc, int i)
+{
+ struct fw_rsc_vdev_vring *vring = &rsc->vring[i];
+ int size;
+ int order;
+ void *pa;
+
+ debug("vdev rsc: vring%d: da %x, qsz %d, align %d\n",
+ i, vring->da, vring->num, vring->align);
+
+ /*
+ * verify queue size and vring alignment are sane
+ */
+ if (!vring->num || !vring->align) {
+ debug("invalid qsz (%d) or alignment (%d)\n", vring->num,
+ vring->align);
+ return -EINVAL;
+ }
+
+ /*
+ * actual size of vring (in bytes)
+ */
+ size = RPROC_PAGE_ALIGN(vring_size(vring->num, vring->align));
+ order = vring->align >> RPROC_PAGE_SHIFT;
+
+ pa = rproc_alloc_mem(dev, size, order);
+ if (!pa) {
+ debug("failed to allocate vring rsc\n");
+ return -ENOMEM;
+ }
+ debug("alloc_mem(%#x, %d): %p\n", size, order, pa);
+ vring->da = (uintptr_t)pa;
+
+ return !pa;
+}
+
+static int handle_vdev(struct udevice *dev, struct fw_rsc_vdev *rsc,
+ int offset, int avail)
+{
+ int i, ret;
+ void *pa;
+
+ /*
+ * make sure resource isn't truncated
+ */
+ if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct fw_rsc_vdev_vring)
+ + rsc->config_len > avail) {
+ debug("vdev rsc is truncated\n");
+ return -EINVAL;
+ }
+
+ /*
+ * make sure reserved bytes are zeroes
+ */
+ if (rsc->reserved[0] || rsc->reserved[1]) {
+ debug("vdev rsc has non zero reserved bytes\n");
+ return -EINVAL;
+ }
+
+ debug("vdev rsc: id %d, dfeatures %x, cfg len %d, %d vrings\n",
+ rsc->id, rsc->dfeatures, rsc->config_len, rsc->num_of_vrings);
+
+ /*
+ * we currently support only two vrings per rvdev
+ */
+ if (rsc->num_of_vrings > 2) {
+ debug("too many vrings: %d\n", rsc->num_of_vrings);
+ return -EINVAL;
+ }
+
+ /*
+ * allocate the vrings
+ */
+ for (i = 0; i < rsc->num_of_vrings; i++) {
+ ret = alloc_vring(dev, rsc, i);
+ if (ret)
+ goto alloc_error;
+ }
+
+ pa = rproc_alloc_mem(dev, RPMSG_TOTAL_BUF_SPACE, 6);
+ if (!pa) {
+ debug("failed to allocate vdev rsc\n");
+ return -ENOMEM;
+ }
+ debug("vring buffer alloc_mem(%#x, 6): %p\n", RPMSG_TOTAL_BUF_SPACE,
+ pa);
+
+ return 0;
+
+ alloc_error:
+ return ret;
+}
+
+/*
+ * A lookup table for resource handlers. The indices are defined in
+ * enum fw_resource_type.
+ */
+static handle_resource_t loading_handlers[RSC_LAST] = {
+ [RSC_CARVEOUT] = (handle_resource_t)handle_carveout,
+ [RSC_DEVMEM] = (handle_resource_t)handle_devmem,
+ [RSC_TRACE] = (handle_resource_t)handle_trace,
+ [RSC_VDEV] = (handle_resource_t)handle_vdev,
+};
+
+/*
+ * handle firmware resource entries before booting the remote processor
+ */
+static int handle_resources(struct udevice *dev, int len,
+ handle_resource_t handlers[RSC_LAST])
+{
+ handle_resource_t handler;
+ int ret = 0, i;
+
+ for (i = 0; i < rsc_table->num; i++) {
+ int offset = rsc_table->offset[i];
+ struct fw_rsc_hdr *hdr = (void *)rsc_table + offset;
+ int avail = len - offset - sizeof(*hdr);
+ void *rsc = (void *)hdr + sizeof(*hdr);
+
+ /*
+ * make sure table isn't truncated
+ */
+ if (avail < 0) {
+ debug("rsc table is truncated\n");
+ return -EINVAL;
+ }
+
+ debug("rsc: type %d\n", hdr->type);
+
+ if (hdr->type >= RSC_LAST) {
+ debug("unsupported resource %d\n", hdr->type);
+ continue;
+ }
+
+ handler = handlers[hdr->type];
+ if (!handler)
+ continue;
+
+ ret = handler(dev, rsc, offset + sizeof(*hdr), avail);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
+static int
+handle_intmem_to_l3_mapping(struct udevice *dev,
+ struct rproc_intmem_to_l3_mapping *l3_mapping)
+{
+ u32 i = 0;
+
+ for (i = 0; i < l3_mapping->num_entries; i++) {
+ struct l3_map *curr_map = &l3_mapping->mappings[i];
+ struct rproc_mem_entry *mapping;
+
+ mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
+ if (!mapping)
+ return -ENOMEM;
+
+ mapping->dma = curr_map->l3_addr;
+ mapping->da = curr_map->priv_addr;
+ mapping->len = curr_map->len;
+ rproc_add_res(dev, mapping);
+ }
+
+ return 0;
+}
+
+static Elf32_Shdr *rproc_find_table(unsigned int addr)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf32_Shdr *shdr; /* Section header structure pointer */
+ Elf32_Shdr sectionheader;
+ int i;
+ u8 *elf_data;
+ char *name_table;
+ struct resource_table *ptable;
+
+ ehdr = (Elf32_Ehdr *)(uintptr_t)addr;
+ elf_data = (u8 *)ehdr;
+ shdr = (Elf32_Shdr *)(elf_data + ehdr->e_shoff);
+ memcpy(§ionheader, &shdr[ehdr->e_shstrndx], sizeof(sectionheader));
+ name_table = (char *)(elf_data + sectionheader.sh_offset);
+
+ for (i = 0; i < ehdr->e_shnum; i++, shdr++) {
+ memcpy(§ionheader, shdr, sizeof(sectionheader));
+ u32 size = sectionheader.sh_size;
+ u32 offset = sectionheader.sh_offset;
+
+ if (strcmp
+ (name_table + sectionheader.sh_name, ".resource_table"))
+ continue;
+
+ ptable = (struct resource_table *)(elf_data + offset);
+
+ /*
+ * make sure table has at least the header
+ */
+ if (sizeof(struct resource_table) > size) {
+ debug("header-less resource table\n");
+ return NULL;
+ }
+
+ /*
+ * we don't support any version beyond the first
+ */
+ if (ptable->ver != 1) {
+ debug("unsupported fw ver: %d\n", ptable->ver);
+ return NULL;
+ }
+
+ /*
+ * make sure reserved bytes are zeroes
+ */
+ if (ptable->reserved[0] || ptable->reserved[1]) {
+ debug("non zero reserved bytes\n");
+ return NULL;
+ }
+
+ /*
+ * make sure the offsets array isn't truncated
+ */
+ if (ptable->num * sizeof(ptable->offset[0]) +
+ sizeof(struct resource_table) > size) {
+ debug("resource table incomplete\n");
+ return NULL;
+ }
+
+ return shdr;
+ }
+
+ return NULL;
+}
+
+struct resource_table *rproc_find_resource_table(struct udevice *dev,
+ unsigned int addr,
+ int *tablesz)
+{
+ Elf32_Shdr *shdr;
+ Elf32_Shdr sectionheader;
+ struct resource_table *ptable;
+ u8 *elf_data = (u8 *)(uintptr_t)addr;
+
+ shdr = rproc_find_table(addr);
+ if (!shdr) {
+ debug("%s: failed to get resource section header\n", __func__);
+ return NULL;
+ }
+
+ memcpy(§ionheader, shdr, sizeof(sectionheader));
+ ptable = (struct resource_table *)(elf_data + sectionheader.sh_offset);
+ if (tablesz)
+ *tablesz = sectionheader.sh_size;
+
+ return ptable;
+}
+
+unsigned long rproc_parse_resource_table(struct udevice *dev, struct rproc *cfg)
+{
+ struct resource_table *ptable = NULL;
+ int tablesz;
+ int ret;
+ unsigned long addr;
+
+ addr = cfg->load_addr;
+
+ ptable = rproc_find_resource_table(dev, addr, &tablesz);
+ if (!ptable) {
+ debug("%s : failed to find resource table\n", __func__);
+ return 0;
+ }
+
+ debug("%s : found resource table\n", __func__);
+ rsc_table = kzalloc(tablesz, GFP_KERNEL);
+ if (!rsc_table) {
+ debug("resource table alloc failed!\n");
+ return 0;
+ }
+
+ /*
+ * Copy the resource table into a local buffer before handling the
+ * resource table.
+ */
+ memcpy(rsc_table, ptable, tablesz);
+ if (cfg->intmem_to_l3_mapping)
+ handle_intmem_to_l3_mapping(dev, cfg->intmem_to_l3_mapping);
+ ret = handle_resources(dev, tablesz, loading_handlers);
+ if (ret) {
+ debug("handle_resources failed: %d\n", ret);
+ return 0;
+ }
+
+ /*
+ * Instead of trying to mimic the kernel flow of copying the
+ * processed resource table into its post ELF load location in DDR
+ * copying it into its original location.
+ */
+ memcpy(ptable, rsc_table, tablesz);
+ free(rsc_table);
+ rsc_table = NULL;
+
+ return 1;
+}
passing request via Xilinx firmware interface to TF-A and PMU
firmware.
+config RESET_DRA7
+ bool "Support for TI's DRA7 Reset driver"
+ depends on DM_RESET
+ help
+ Support for TI DRA7-RESET subsystem. Basic Assert/Deassert
+ is supported.
endmenu
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
+obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Texas Instruments DRA7 reset driver
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Keerthy <j-keerthy@ti.com>
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <dm/device_compat.h>
+
+struct dra7_reset_priv {
+ u32 rstctrl;
+ u32 rstst;
+ u8 nreset;
+};
+
+static int dra7_reset_request(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int dra7_reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static inline void dra7_reset_rmw(u32 addr, u32 value, u32 mask)
+{
+ writel(((readl(addr) & (~mask)) | (value & mask)), addr);
+}
+
+static int dra7_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct dra7_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int mask = 1 << reset_ctl->id;
+
+ if (reset_ctl->id < 0 || reset_ctl->id >= priv->nreset)
+ return -EINVAL;
+
+ dra7_reset_rmw(priv->rstctrl, 0x0, mask);
+
+ while ((readl(priv->rstst) & mask) != mask)
+ ;
+
+ return 0;
+}
+
+static int dra7_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct dra7_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int mask = 1 << reset_ctl->id;
+
+ if (reset_ctl->id < 0 || reset_ctl->id >= priv->nreset)
+ return -EINVAL;
+
+ dra7_reset_rmw(priv->rstctrl, mask, 0x0);
+
+ return 0;
+}
+
+struct reset_ops dra7_reset_ops = {
+ .request = dra7_reset_request,
+ .rfree = dra7_reset_free,
+ .rst_assert = dra7_reset_assert,
+ .rst_deassert = dra7_reset_deassert,
+};
+
+static const struct udevice_id dra7_reset_ids[] = {
+ { .compatible = "ti,dra7-reset" },
+ { }
+};
+
+static int dra7_reset_probe(struct udevice *dev)
+{
+ struct dra7_reset_priv *priv = dev_get_priv(dev);
+
+ priv->rstctrl = dev_read_addr(dev);
+ priv->rstst = priv->rstctrl + 0x4;
+ priv->nreset = dev_read_u32_default(dev, "ti,nresets", 1);
+
+ dev_info(dev, "dra7-reset successfully probed %s\n", dev->name);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(dra7_reset) = {
+ .name = "dra7_reset",
+ .id = UCLASS_RESET,
+ .of_match = dra7_reset_ids,
+ .probe = dra7_reset_probe,
+ .ops = &dra7_reset_ops,
+ .priv_auto = sizeof(struct dra7_reset_priv),
+};
return -ENODEV;
/* Get optional "core" clock */
- err = clk_get_by_name(dev, "core", &pdata->clk);
- if (err && err != -ENODATA)
+ err = clk_get_by_name_optional(dev, "core", &pdata->clk);
+ if (err)
return err;
return 0;
{ .compatible = "dallas,ds1337", .data = ds_1337 },
{ .compatible = "dallas,ds1339", .data = ds_1339 },
{ .compatible = "dallas,ds1340", .data = ds_1340 },
+ { .compatible = "microchip,mcp7940x", .data = mcp794xx },
{ .compatible = "microchip,mcp7941x", .data = mcp794xx },
{ .compatible = "st,m41t11", .data = m41t11 },
{ }
};
static const struct udevice_id pcf2127_rtc_ids[] = {
- { .compatible = "pcf2127-rtc" },
+ { .compatible = "nxp,pcf2127" },
+ { .compatible = "nxp,pcf2129" },
+ { .compatible = "nxp,pca2129" },
{ }
};
which supports SCSI and SATA HDDs. For every device configuration
(IDs/LUNs) a block device is created with RAW read/write and
filesystem support.
+
+if SCSI && !DM_SCSI
+
+config SCSI_AHCI_PLAT
+ bool "Platform-specific init of AHCI"
+ help
+ This enables a way for boards to set up an AHCI device manually, by
+ called ahci_init() and providing an ahci_reset() mechanism.
+
+ This is deprecated. An AHCI driver should be provided instead.
+
+config SYS_SCSI_MAX_SCSI_ID
+ int "Maximum supporedt SCSI ID"
+ default 1
+ help
+ Sets the maximum number of SCSI IDs to scan when looking for devices.
+ IDs from 0 to (this value - 1) are scanned.
+
+ This is deprecated and is not needed when BLK is enabled.
+
+config SYS_SCSI_MAX_LUN
+ int "Maximum support SCSI LUN"
+ default 1
+ help
+ Sets the maximum number of SCSI Logical Unit Numbers (LUNs) to scan on
+ devices. LUNs from 0 to (this value - 1) are scanned.
+
+ This is deprecated and is not needed when CONFIG_DM_SCSI is enabled.
+
+endif
endif
endif
+ifdef CONFIG_SCSI
obj-$(CONFIG_SANDBOX) += sandbox_scsi.o
+endif
static int scsi_curr_dev; /* current device */
-static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
+static struct blk_desc scsi_dev_desc[SCSI_MAX_DEVICE];
#endif
/* almost the maximum amount of the scsi_ext command.. */
if (verbose)
printf("scanning bus for devices...\n");
- for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++)
+ for (i = 0; i < SCSI_MAX_DEVICE; i++)
scsi_init_dev_desc(&scsi_dev_desc[i], i);
scsi_max_devs = 0;
U_BOOT_LEGACY_BLK(scsi) = {
.if_typename = "scsi",
.if_type = IF_TYPE_SCSI,
- .max_devs = CONFIG_SYS_SCSI_MAX_DEVICE,
+ .max_devs = SCSI_MAX_DEVICE,
.desc = scsi_dev_desc,
};
#endif
If you have a machine based on a Marvell XScale PXA2xx CPU you
can enable its onboard serial ports by enabling this option.
+config HTIF_CONSOLE
+ bool "RISC-V HTIF console support"
+ depends on DM_SERIAL && 64BIT
+ help
+ Select this to enable host transfer interface (HTIF) based serial
+ console. The HTIF device is quite common in RISC-V emulators and
+ RISC-V ISS so this driver allows using U-Boot on such platforms.
+
config SIFIVE_SERIAL
bool "SiFive UART support"
depends on DM_SERIAL
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o
+obj-$(CONFIG_HTIF_CONSOLE) += serial_htif.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
{
_serial_putc(sdev->priv, ch);
}
-#endif
static void serial_stub_puts(struct stdio_dev *sdev, const char *str)
{
return _serial_tstc(sdev->priv);
}
#endif
+#endif
/**
* on_baudrate() - Update the actual baudrate when the env var changes
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <watchdog.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <serial.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HTIF_DATA_BITS 48
+#define HTIF_DATA_MASK ((1ULL << HTIF_DATA_BITS) - 1)
+#define HTIF_DATA_SHIFT 0
+#define HTIF_CMD_BITS 8
+#define HTIF_CMD_MASK ((1ULL << HTIF_CMD_BITS) - 1)
+#define HTIF_CMD_SHIFT 48
+#define HTIF_DEV_BITS 8
+#define HTIF_DEV_MASK ((1ULL << HTIF_DEV_BITS) - 1)
+#define HTIF_DEV_SHIFT 56
+
+#define HTIF_DEV_SYSTEM 0
+#define HTIF_DEV_CONSOLE 1
+
+#define HTIF_CONSOLE_CMD_GETC 0
+#define HTIF_CONSOLE_CMD_PUTC 1
+
+#if __riscv_xlen == 64
+# define TOHOST_CMD(dev, cmd, payload) \
+ (((u64)(dev) << HTIF_DEV_SHIFT) | \
+ ((u64)(cmd) << HTIF_CMD_SHIFT) | \
+ (u64)(payload))
+#else
+# define TOHOST_CMD(dev, cmd, payload) ({ \
+ if ((dev) || (cmd)) \
+ __builtin_trap(); \
+ (payload); })
+#endif
+#define FROMHOST_DEV(fromhost_value) \
+ ((u64)((fromhost_value) >> HTIF_DEV_SHIFT) & HTIF_DEV_MASK)
+#define FROMHOST_CMD(fromhost_value) \
+ ((u64)((fromhost_value) >> HTIF_CMD_SHIFT) & HTIF_CMD_MASK)
+#define FROMHOST_DATA(fromhost_value) \
+ ((u64)((fromhost_value) >> HTIF_DATA_SHIFT) & HTIF_DATA_MASK)
+
+struct htif_plat {
+ void *fromhost;
+ void *tohost;
+ int console_char;
+};
+
+static void __check_fromhost(struct htif_plat *plat)
+{
+ u64 fh = readq(plat->fromhost);
+
+ if (!fh)
+ return;
+ writeq(0, plat->fromhost);
+
+ /* this should be from the console */
+ if (FROMHOST_DEV(fh) != HTIF_DEV_CONSOLE)
+ __builtin_trap();
+ switch (FROMHOST_CMD(fh)) {
+ case HTIF_CONSOLE_CMD_GETC:
+ plat->console_char = 1 + (u8)FROMHOST_DATA(fh);
+ break;
+ case HTIF_CONSOLE_CMD_PUTC:
+ break;
+ default:
+ __builtin_trap();
+ }
+}
+
+static void __set_tohost(struct htif_plat *plat,
+ u64 dev, u64 cmd, u64 data)
+{
+ while (readq(plat->tohost))
+ __check_fromhost(plat);
+ writeq(TOHOST_CMD(dev, cmd, data), plat->tohost);
+}
+
+static int htif_serial_putc(struct udevice *dev, const char ch)
+{
+ struct htif_plat *plat = dev_get_plat(dev);
+
+ __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_PUTC, ch);
+ return 0;
+}
+
+static int htif_serial_getc(struct udevice *dev)
+{
+ int ch;
+ struct htif_plat *plat = dev_get_plat(dev);
+
+ if (plat->console_char < 0)
+ __check_fromhost(plat);
+
+ if (plat->console_char >= 0) {
+ ch = plat->console_char;
+ plat->console_char = -1;
+ __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_GETC, 0);
+ return (ch) ? ch - 1 : -EAGAIN;
+ }
+
+ return -EAGAIN;
+}
+
+static int htif_serial_pending(struct udevice *dev, bool input)
+{
+ struct htif_plat *plat = dev_get_plat(dev);
+
+ if (!input)
+ return 0;
+
+ if (plat->console_char < 0)
+ __check_fromhost(plat);
+
+ return (plat->console_char >= 0) ? 1 : 0;
+}
+
+static int htif_serial_probe(struct udevice *dev)
+{
+ struct htif_plat *plat = dev_get_plat(dev);
+
+ /* Queue first getc request */
+ __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_GETC, 0);
+
+ return 0;
+}
+
+static int htif_serial_of_to_plat(struct udevice *dev)
+{
+ fdt_addr_t addr;
+ struct htif_plat *plat = dev_get_plat(dev);
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+ plat->fromhost = (void *)(uintptr_t)addr;
+ plat->tohost = plat->fromhost + sizeof(u64);
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr != FDT_ADDR_T_NONE)
+ plat->tohost = (void *)(uintptr_t)addr;
+
+ plat->console_char = -1;
+
+ return 0;
+}
+
+static const struct dm_serial_ops htif_serial_ops = {
+ .putc = htif_serial_putc,
+ .getc = htif_serial_getc,
+ .pending = htif_serial_pending,
+};
+
+static const struct udevice_id htif_serial_ids[] = {
+ { .compatible = "ucb,htif0" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_htif) = {
+ .name = "serial_htif",
+ .id = UCLASS_SERIAL,
+ .of_match = htif_serial_ids,
+ .of_to_plat = htif_serial_of_to_plat,
+ .plat_auto = sizeof(struct htif_plat),
+ .probe = htif_serial_probe,
+ .ops = &htif_serial_ops,
+};
return 0;
}
-static int nulldev_serial_input(struct udevice *dev)
-{
- return 0;
-}
-
static int nulldev_serial_putc(struct udevice *dev, const char ch)
{
return 0;
#define J721E 0xbb64
#define J7200 0xbb6d
#define AM64X 0xbb38
-
-#define REV_SR1_0 0
-#define REV_SR2_0 1
+#define J721S2 0xbb75
#define JTAG_ID_VARIANT_SHIFT 28
#define JTAG_ID_VARIANT_MASK (0xf << 28)
case AM64X:
family = "AM64X";
break;
+ case J721S2:
+ family = "J721S2";
+ break;
default:
family = "Unknown Silicon";
};
return family;
}
+static char *j721e_rev_string_map[] = {
+ "1.0", "1.1",
+};
+
+static char *am65x_rev_string_map[] = {
+ "1.0", "2.0",
+};
+
static const char *get_rev_string(u32 idreg)
{
- const char *revision;
u32 rev;
+ u32 soc;
rev = (idreg & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
+ soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
- switch (rev) {
- case REV_SR1_0:
- revision = "1.0";
- break;
- case REV_SR2_0:
- revision = "2.0";
- break;
+ switch (soc) {
+ case J721E:
+ if (rev > ARRAY_SIZE(j721e_rev_string_map))
+ goto bail;
+ return j721e_rev_string_map[rev];
+
+ case AM65X:
+ if (rev > ARRAY_SIZE(am65x_rev_string_map))
+ goto bail;
+ return am65x_rev_string_map[rev];
+
+ case AM64X:
+ case J7200:
default:
- revision = "Unknown Revision";
+ if (!rev)
+ return "1.0";
};
- return revision;
+bail:
+ return "Unknown Revision";
}
static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size)
IP core. Please find details on the "Embedded Peripherals IP
User Guide" of Altera.
+config APPLE_SPI
+ bool "Apple SPI driver"
+ default y if ARCH_APPLE
+ help
+ Enable the Apple SPI driver. This driver can be used to
+ access the SPI flash and keyboard on machines based on Apple SoCs.
+
config ATCSPI200_SPI
bool "Andestech ATCSPI200 SPI driver"
help
endif
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
+obj-$(CONFIG_APPLE_SPI) += apple_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
+ * Copyright The Asahi Linux Contributors
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+
+#define APPLE_SPI_CTRL 0x000
+#define APPLE_SPI_CTRL_RUN BIT(0)
+#define APPLE_SPI_CTRL_TX_RESET BIT(2)
+#define APPLE_SPI_CTRL_RX_RESET BIT(3)
+
+#define APPLE_SPI_CFG 0x004
+#define APPLE_SPI_CFG_CPHA BIT(1)
+#define APPLE_SPI_CFG_CPOL BIT(2)
+#define APPLE_SPI_CFG_MODE GENMASK(6, 5)
+#define APPLE_SPI_CFG_MODE_POLLED 0
+#define APPLE_SPI_CFG_MODE_IRQ 1
+#define APPLE_SPI_CFG_MODE_DMA 2
+#define APPLE_SPI_CFG_IE_RXCOMPLETE BIT(7)
+#define APPLE_SPI_CFG_IE_TXRXTHRESH BIT(8)
+#define APPLE_SPI_CFG_LSB_FIRST BIT(13)
+#define APPLE_SPI_CFG_WORD_SIZE GENMASK(16, 15)
+#define APPLE_SPI_CFG_WORD_SIZE_8B 0
+#define APPLE_SPI_CFG_WORD_SIZE_16B 1
+#define APPLE_SPI_CFG_WORD_SIZE_32B 2
+#define APPLE_SPI_CFG_FIFO_THRESH GENMASK(18, 17)
+#define APPLE_SPI_CFG_FIFO_THRESH_8B 0
+#define APPLE_SPI_CFG_FIFO_THRESH_4B 1
+#define APPLE_SPI_CFG_FIFO_THRESH_1B 2
+#define APPLE_SPI_CFG_IE_TXCOMPLETE BIT(21)
+
+#define APPLE_SPI_STATUS 0x008
+#define APPLE_SPI_STATUS_RXCOMPLETE BIT(0)
+#define APPLE_SPI_STATUS_TXRXTHRESH BIT(1)
+#define APPLE_SPI_STATUS_TXCOMPLETE BIT(2)
+
+#define APPLE_SPI_PIN 0x00c
+#define APPLE_SPI_PIN_KEEP_MOSI BIT(0)
+#define APPLE_SPI_PIN_CS BIT(1)
+
+#define APPLE_SPI_TXDATA 0x010
+#define APPLE_SPI_RXDATA 0x020
+#define APPLE_SPI_CLKDIV 0x030
+#define APPLE_SPI_CLKDIV_MIN 0x002
+#define APPLE_SPI_CLKDIV_MAX 0x7ff
+#define APPLE_SPI_RXCNT 0x034
+#define APPLE_SPI_WORD_DELAY 0x038
+#define APPLE_SPI_TXCNT 0x04c
+
+#define APPLE_SPI_FIFOSTAT 0x10c
+#define APPLE_SPI_FIFOSTAT_TXFULL BIT(4)
+#define APPLE_SPI_FIFOSTAT_LEVEL_TX GENMASK(15, 8)
+#define APPLE_SPI_FIFOSTAT_RXEMPTY BIT(20)
+#define APPLE_SPI_FIFOSTAT_LEVEL_RX GENMASK(31, 24)
+
+#define APPLE_SPI_IE_XFER 0x130
+#define APPLE_SPI_IF_XFER 0x134
+#define APPLE_SPI_XFER_RXCOMPLETE BIT(0)
+#define APPLE_SPI_XFER_TXCOMPLETE BIT(1)
+
+#define APPLE_SPI_IE_FIFO 0x138
+#define APPLE_SPI_IF_FIFO 0x13c
+#define APPLE_SPI_FIFO_RXTHRESH BIT(4)
+#define APPLE_SPI_FIFO_TXTHRESH BIT(5)
+#define APPLE_SPI_FIFO_RXFULL BIT(8)
+#define APPLE_SPI_FIFO_TXEMPTY BIT(9)
+#define APPLE_SPI_FIFO_RXUNDERRUN BIT(16)
+#define APPLE_SPI_FIFO_TXOVERFLOW BIT(17)
+
+#define APPLE_SPI_SHIFTCFG 0x150
+#define APPLE_SPI_SHIFTCFG_CLK_ENABLE BIT(0)
+#define APPLE_SPI_SHIFTCFG_CS_ENABLE BIT(1)
+#define APPLE_SPI_SHIFTCFG_AND_CLK_DATA BIT(8)
+#define APPLE_SPI_SHIFTCFG_CS_AS_DATA BIT(9)
+#define APPLE_SPI_SHIFTCFG_TX_ENABLE BIT(10)
+#define APPLE_SPI_SHIFTCFG_RX_ENABLE BIT(11)
+#define APPLE_SPI_SHIFTCFG_BITS GENMASK(21, 16)
+#define APPLE_SPI_SHIFTCFG_OVERRIDE_CS BIT(24)
+
+#define APPLE_SPI_PINCFG 0x154
+#define APPLE_SPI_PINCFG_KEEP_CLK BIT(0)
+#define APPLE_SPI_PINCFG_KEEP_CS BIT(1)
+#define APPLE_SPI_PINCFG_KEEP_MOSI BIT(2)
+#define APPLE_SPI_PINCFG_CLK_IDLE_VAL BIT(8)
+#define APPLE_SPI_PINCFG_CS_IDLE_VAL BIT(9)
+#define APPLE_SPI_PINCFG_MOSI_IDLE_VAL BIT(10)
+
+#define APPLE_SPI_DELAY_PRE 0x160
+#define APPLE_SPI_DELAY_POST 0x168
+#define APPLE_SPI_DELAY_ENABLE BIT(0)
+#define APPLE_SPI_DELAY_NO_INTERBYTE BIT(1)
+#define APPLE_SPI_DELAY_SET_SCK BIT(4)
+#define APPLE_SPI_DELAY_SET_MOSI BIT(6)
+#define APPLE_SPI_DELAY_SCK_VAL BIT(8)
+#define APPLE_SPI_DELAY_MOSI_VAL BIT(12)
+
+#define APPLE_SPI_FIFO_DEPTH 16
+
+#define APPLE_SPI_TIMEOUT_MS 200
+
+struct apple_spi_priv {
+ void *base;
+ u32 clkfreq; /* Input clock frequency */
+};
+
+static void apple_spi_set_cs(struct apple_spi_priv *priv, int on)
+{
+ writel(on ? 0 : APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN);
+}
+
+/* Fill Tx FIFO. */
+static void apple_spi_tx(struct apple_spi_priv *priv, uint *len,
+ const void **dout)
+{
+ const u8 *out = *dout;
+ u32 data, fifostat;
+ uint count;
+
+ fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT);
+ count = APPLE_SPI_FIFO_DEPTH -
+ FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_TX, fifostat);
+ while (*len > 0 && count > 0) {
+ data = out ? *out++ : 0;
+ writel(data, priv->base + APPLE_SPI_TXDATA);
+ (*len)--;
+ count--;
+ }
+
+ *dout = out;
+}
+
+/* Empty Rx FIFO. */
+static void apple_spi_rx(struct apple_spi_priv *priv, uint *len,
+ void **din)
+{
+ u8 *in = *din;
+ u32 data, fifostat;
+ uint count;
+
+ fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT);
+ count = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_RX, fifostat);
+ while (*len > 0 && count > 0) {
+ data = readl(priv->base + APPLE_SPI_RXDATA);
+ if (in)
+ *in++ = data;
+ (*len)--;
+ count--;
+ }
+
+ *din = in;
+}
+
+static int apple_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct apple_spi_priv *priv = dev_get_priv(dev->parent);
+ unsigned long start = get_timer(0);
+ uint txlen, rxlen;
+ int ret = 0;
+
+ if ((bitlen % 8) != 0)
+ return -EINVAL;
+ txlen = rxlen = bitlen / 8;
+
+ if (flags & SPI_XFER_BEGIN)
+ apple_spi_set_cs(priv, 1);
+
+ if (txlen > 0) {
+ /* Reset FIFOs */
+ writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET,
+ priv->base + APPLE_SPI_CTRL);
+
+ /* Set the transfer length */
+ writel(txlen, priv->base + APPLE_SPI_TXCNT);
+ writel(rxlen, priv->base + APPLE_SPI_RXCNT);
+
+ /* Prime transmit FIFO */
+ apple_spi_tx(priv, &txlen, &dout);
+
+ /* Start transfer */
+ writel(APPLE_SPI_CTRL_RUN, priv->base + APPLE_SPI_CTRL);
+
+ while ((txlen > 0 || rxlen > 0)) {
+ apple_spi_rx(priv, &rxlen, &din);
+ apple_spi_tx(priv, &txlen, &dout);
+
+ if (get_timer(start) > APPLE_SPI_TIMEOUT_MS) {
+ ret = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ /* Stop transfer. */
+ writel(0, priv->base + APPLE_SPI_CTRL);
+ }
+
+ if (flags & SPI_XFER_END)
+ apple_spi_set_cs(priv, 0);
+
+ return ret;
+}
+
+static int apple_spi_set_speed(struct udevice *dev, uint speed)
+{
+ struct apple_spi_priv *priv = dev_get_priv(dev);
+ u32 div;
+
+ div = DIV_ROUND_UP(priv->clkfreq, speed);
+ if (div < APPLE_SPI_CLKDIV_MIN)
+ div = APPLE_SPI_CLKDIV_MIN;
+ if (div > APPLE_SPI_CLKDIV_MAX)
+ div = APPLE_SPI_CLKDIV_MAX;
+
+ writel(div, priv->base + APPLE_SPI_CLKDIV);
+
+ return 0;
+}
+
+static int apple_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+struct dm_spi_ops apple_spi_ops = {
+ .xfer = apple_spi_xfer,
+ .set_speed = apple_spi_set_speed,
+ .set_mode = apple_spi_set_mode,
+};
+
+static int apple_spi_probe(struct udevice *dev)
+{
+ struct apple_spi_priv *priv = dev_get_priv(dev);
+ struct clk clkdev;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &clkdev);
+ if (ret)
+ return ret;
+ priv->clkfreq = clk_get_rate(&clkdev);
+
+ /* Set CS high (inactive) and disable override and auto-CS */
+ writel(APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN);
+ writel(readl(priv->base + APPLE_SPI_SHIFTCFG) & ~APPLE_SPI_SHIFTCFG_OVERRIDE_CS,
+ priv->base + APPLE_SPI_SHIFTCFG);
+ writel((readl(priv->base + APPLE_SPI_PINCFG) & ~APPLE_SPI_PINCFG_CS_IDLE_VAL) |
+ APPLE_SPI_PINCFG_KEEP_CS, priv->base + APPLE_SPI_PINCFG);
+
+ /* Reset FIFOs */
+ writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET,
+ priv->base + APPLE_SPI_CTRL);
+
+ /* Configure defaults */
+ writel(FIELD_PREP(APPLE_SPI_CFG_MODE, APPLE_SPI_CFG_MODE_IRQ) |
+ FIELD_PREP(APPLE_SPI_CFG_WORD_SIZE, APPLE_SPI_CFG_WORD_SIZE_8B) |
+ FIELD_PREP(APPLE_SPI_CFG_FIFO_THRESH, APPLE_SPI_CFG_FIFO_THRESH_8B),
+ priv->base + APPLE_SPI_CFG);
+
+ return 0;
+}
+
+static const struct udevice_id apple_spi_of_match[] = {
+ { .compatible = "apple,spi" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(apple_spi) = {
+ .name = "apple_spi",
+ .id = UCLASS_SPI,
+ .of_match = apple_spi_of_match,
+ .probe = apple_spi_probe,
+ .priv_auto = sizeof(struct apple_spi_priv),
+ .ops = &apple_spi_ops,
+};
nbytes = DIV_ROUND_UP(bitlen, 8);
- cnt = nbytes % 32;
-
if (bitlen % 32) {
data = reg_read(®s->rxdata);
cnt = (bitlen % 32) / 8;
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <spi-mem.h>
DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
+#define ZYNQ_QSPI_MAX_BAUD_RATE 0x7
+#define ZYNQ_QSPI_DEFAULT_BAUD_RATE 0x2
+
#define ZYNQ_QSPI_FIFO_DEPTH 63
#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
priv->rx_buf += 1;
break;
case 2:
- *((u16 *)priv->rx_buf) = data;
- priv->rx_buf += 2;
+ *((u8 *)priv->rx_buf) = data;
+ priv->rx_buf += 1;
+ *((u8 *)priv->rx_buf) = (u8)(data >> 8);
+ priv->rx_buf += 1;
break;
case 3:
- *((u16 *)priv->rx_buf) = data;
- priv->rx_buf += 2;
+ *((u8 *)priv->rx_buf) = data;
+ priv->rx_buf += 1;
+ *((u8 *)priv->rx_buf) = (u8)(data >> 8);
+ priv->rx_buf += 1;
byte3 = (u8)(data >> 16);
*((u8 *)priv->rx_buf) = byte3;
priv->rx_buf += 1;
*data |= 0xFFFFFF00;
break;
case 2:
- *data = *((u16 *)priv->tx_buf);
- priv->tx_buf += 2;
+ *data = *((u8 *)priv->tx_buf);
+ priv->tx_buf += 1;
+ *data |= (*((u8 *)priv->tx_buf) << 8);
+ priv->tx_buf += 1;
*data |= 0xFFFF0000;
break;
case 3:
- *data = *((u16 *)priv->tx_buf);
- priv->tx_buf += 2;
+ *data = *((u8 *)priv->tx_buf);
+ priv->tx_buf += 1;
+ *data |= (*((u8 *)priv->tx_buf) << 8);
+ priv->tx_buf += 1;
*data |= (*((u8 *)priv->tx_buf) << 16);
priv->tx_buf += 1;
*data |= 0xFF000000;
(2 << baud_rate_val)) > speed))
baud_rate_val++;
+ if (baud_rate_val > ZYNQ_QSPI_MAX_BAUD_RATE)
+ baud_rate_val = ZYNQ_QSPI_DEFAULT_BAUD_RATE;
+
plat->speed_hz = speed / (2 << baud_rate_val);
}
confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
return 0;
}
+static int zynq_qspi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ int op_len, pos = 0, ret, i;
+ unsigned int flag = 0;
+ const u8 *tx_buf = NULL;
+ u8 *rx_buf = NULL;
+
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ rx_buf = op->data.buf.in;
+ else
+ tx_buf = op->data.buf.out;
+ }
+
+ op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
+
+ u8 op_buf[op_len];
+
+ op_buf[pos++] = op->cmd.opcode;
+
+ if (op->addr.nbytes) {
+ for (i = 0; i < op->addr.nbytes; i++)
+ op_buf[pos + i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ pos += op->addr.nbytes;
+ }
+
+ if (op->dummy.nbytes)
+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+ /* 1st transfer: opcode + address + dummy cycles */
+ /* Make sure to set END bit if no tx or rx data messages follow */
+ if (!tx_buf && !rx_buf)
+ flag |= SPI_XFER_END;
+
+ ret = zynq_qspi_xfer(slave->dev, op_len * 8, op_buf, NULL,
+ flag | SPI_XFER_BEGIN);
+ if (ret)
+ return ret;
+
+ /* 2nd transfer: rx or tx data path */
+ if (tx_buf || rx_buf) {
+ ret = zynq_qspi_xfer(slave->dev, op->data.nbytes * 8, tx_buf,
+ rx_buf, flag | SPI_XFER_END);
+ if (ret)
+ return ret;
+ }
+
+ spi_release_bus(slave);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
+ .exec_op = zynq_qspi_exec_op,
+};
+
static const struct dm_spi_ops zynq_qspi_ops = {
.claim_bus = zynq_qspi_claim_bus,
.release_bus = zynq_qspi_release_bus,
.xfer = zynq_qspi_xfer,
.set_speed = zynq_qspi_set_speed,
.set_mode = zynq_qspi_set_mode,
+ .mem_ops = &zynq_qspi_mem_ops,
};
static const struct udevice_id zynq_qspi_ids[] = {
mdelay(100);
}
+static void dwc3_core_stop(struct dwc3 *dwc)
+{
+ u32 reg;
+
+ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
+ dwc3_writel(dwc->regs, DWC3_DCTL, reg & ~(DWC3_DCTL_RUN_STOP));
+}
+
static void dwc3_core_exit_mode(struct dwc3 *dwc)
{
switch (dwc->dr_mode) {
dwc3_core_exit_mode(dwc);
dwc3_event_buffers_cleanup(dwc);
dwc3_free_event_buffers(dwc);
+ dwc3_core_stop(dwc);
dwc3_core_exit(dwc);
kfree(dwc->mem);
}
struct dwc3_generic_plat *plat = dev_get_plat(dev);
ofnode node = dev_ofnode(dev);
- plat->base = dev_read_addr(dev);
+ if (!strncmp(dev->name, "port", 4) || !strncmp(dev->name, "hub", 3)) {
+ /* This is a leaf so check the parent */
+ plat->base = dev_read_addr(dev->parent);
+ } else {
+ plat->base = dev_read_addr(dev);
+ }
plat->maximum_speed = usb_get_maximum_speed(node);
if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
plat->dr_mode = usb_get_dr_mode(node);
if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
- pr_err("Invalid usb mode setup\n");
- return -ENODEV;
+ /* might be a leaf so check the parent for mode */
+ node = dev_ofnode(dev->parent);
+ plat->dr_mode = usb_get_dr_mode(node);
+ if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
+ pr_err("Invalid usb mode setup\n");
+ return -ENODEV;
+ }
}
return 0;
{
ofnode node;
int ret;
+ enum usb_dr_mode dr_mode;
+
+ dr_mode = usb_get_dr_mode(dev_ofnode(parent));
ofnode_for_each_subnode(node, dev_ofnode(parent)) {
const char *name = ofnode_get_name(node);
- enum usb_dr_mode dr_mode;
struct udevice *dev;
const char *driver = NULL;
debug("%s: subnode name: %s\n", __func__, name);
- dr_mode = usb_get_dr_mode(node);
+ /* if the parent node doesn't have a mode check the leaf */
+ if (!dr_mode)
+ dr_mode = usb_get_dr_mode(node);
switch (dr_mode) {
case USB_DR_MODE_PERIPHERAL:
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "qcom,dwc3" },
+ { .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
{ }
};
flush:
hwaddr = (unsigned long)ci_req->hw_buf;
+ if (!hwaddr)
+ return 0;
+
aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN);
flush_dcache_range(hwaddr, hwaddr + aligned_used_len);
unsigned long hwaddr = (unsigned long)ci_req->hw_buf;
uint32_t aligned_used_len;
- if (in)
+ if (in || !hwaddr)
return;
aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN);
config USB_EHCI_OMAP
bool "Support for OMAP3+ on-chip EHCI USB controller"
depends on ARCH_OMAP2PLUS
+ select PHY
+ imply NOP_PHY
default y
---help---
Enables support for the on-chip EHCI controller on OMAP3 and later
SoCs.
-if USB_EHCI_OMAP
-
-config HAS_OMAP_EHCI_PHY1_RESET_GPIO
- bool "PHY #1 requires a GPIO hold to it in RESET while PHY settles"
- help
- Enable this to be able to configure the GPIO number used to hold the
- PHY in RESET for enough time until the PHY is settled and ready.
-
-config OMAP_EHCI_PHY1_RESET_GPIO
- int "GPIO number to hold PHY #1 in RESET"
- depends on HAS_OMAP_EHCI_PHY1_RESET_GPIO
-
-config HAS_OMAP_EHCI_PHY2_RESET_GPIO
- bool "PHY #2 requires a GPIO hold to it in RESET while PHY settles"
- help
- Enable this to be able to configure the GPIO number used to hold the
- PHY in RESET for enough time until the PHY is settled and ready.
-
-config OMAP_EHCI_PHY2_RESET_GPIO
- int "GPIO number to hold PHY #2 in RESET"
- depends on HAS_OMAP_EHCI_PHY2_RESET_GPIO
-
-config HAS_OMAP_EHCI_PHY3_RESET_GPIO
- bool "PHY #3 requires a GPIO hold to it in RESET while PHY settles"
- help
- Enable this to be able to configure the GPIO number used to hold the
- PHY in RESET for enough time until the PHY is settled and ready.
-
-config OMAP_EHCI_PHY3_RESET_GPIO
- int "GPIO number to hold PHY #3 in RESET"
- depends on HAS_OMAP_EHCI_PHY3_RESET_GPIO
-
-endif
-
config USB_EHCI_VF
bool "Support for Vybrid on-chip EHCI USB controller"
depends on ARCH_VF610
* Also, the address decoder doesn't need to get setup with this
* SoC, so don't call usb_brg_adrdec_setup().
*/
- if (device_is_compatible(dev, "marvell,armada3700-ehci"))
+ if (device_is_compatible(dev, "marvell,armada-3700-ehci"))
marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
else
usb_brg_adrdec_setup((void *)priv->hcd_base);
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "marvell,orion-ehci", },
- { .compatible = "marvell,armada3700-ehci", },
+ { .compatible = "marvell,armada-3700-ehci", },
{ }
};
plat->init_type = USB_INIT_DEVICE;
else
plat->init_type = USB_INIT_HOST;
- } else if (is_mx7()) {
+ } else if (is_mx7() || is_imx8mm() || is_imx8mn()) {
phy_status = (void __iomem *)(addr +
USBNC_PHY_STATUS_OFFSET);
val = readl(phy_status);
case USB_DR_MODE_PERIPHERAL:
plat->init_type = USB_INIT_DEVICE;
break;
- case USB_DR_MODE_OTG:
- case USB_DR_MODE_UNKNOWN:
- return ehci_usb_phy_mode(dev);
+ default:
+ plat->init_type = USB_INIT_UNKNOWN;
};
return 0;
mdelay(1);
#endif
+ /*
+ * If the device tree didn't specify host or device,
+ * the default is USB_INIT_UNKNOWN, so we need to check
+ * the register. For imx8mm and imx8mn, the clocks need to be
+ * running first, so we defer the check until they are.
+ */
+ if (priv->init_type == USB_INIT_UNKNOWN) {
+ ret = ehci_usb_phy_mode(dev);
+ if (ret)
+ goto err_clk;
+ else
+ priv->init_type = plat->init_type;
+ }
+
#if CONFIG_IS_ENABLED(DM_REGULATOR)
ret = device_get_supply_regulator(dev, "vbus-supply",
&priv->vbus_supply);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply)
regulator_set_enable(priv->vbus_supply, false);
-err_clk:
#endif
+err_clk:
#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk);
#else
}
#endif
-#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
- defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
- defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
-/* controls PHY(s) reset signal(s) */
-static inline void omap_ehci_phy_reset(int on, int delay)
-{
- /*
- * Refer ISSUE1:
- * Hold the PHY in RESET for enough time till
- * PHY is settled and ready
- */
- if (delay && !on)
- udelay(delay);
-#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
-#endif
-#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
-#endif
-#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
-#endif
-
- /* Hold the PHY in RESET for enough time till DIR is high */
- /* Refer: ISSUE1 */
- if (delay && on)
- udelay(delay);
-}
-#else
-#define omap_ehci_phy_reset(on, delay) do {} while (0)
+struct ehci_omap_priv_data {
+ struct ehci_ctrl ctrl;
+ struct omap_ehci *ehci;
+#ifdef CONFIG_DM_REGULATOR
+ struct udevice *vbus_supply;
#endif
-
-/* Reset is needed otherwise the kernel-driver will throw an error. */
-int omap_ehci_hcd_stop(void)
-{
- debug("Resetting OMAP EHCI\n");
- omap_ehci_phy_reset(1, 0);
-
- if (omap_uhh_reset() < 0)
- return -1;
-
- if (omap_ehci_tll_reset() < 0)
- return -1;
-
- return 0;
-}
+ enum usb_init_type init_type;
+ int portnr;
+ struct phy phy[OMAP_HS_USB_PORTS];
+ int nports;
+};
/*
* Initialize the OMAP EHCI controller and PHY.
* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
* See there for additional Copyrights.
*/
-int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata)
+static int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
+ struct udevice *dev)
{
int ret;
unsigned int i, reg = 0, rev = 0;
if (ret < 0)
return ret;
- /* Put the PHY in RESET */
- omap_ehci_phy_reset(1, 10);
+ /* Hold the PHY in RESET for enough time till DIR is high */
+ /* Refer: ISSUE1 */
+ udelay(10);
ret = omap_uhh_reset();
if (ret < 0)
if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
omap_usbhs_hsic_init(i);
- omap_ehci_phy_reset(0, 10);
+ /*
+ * Refer ISSUE1:
+ * Hold the PHY in RESET for enough time till
+ * PHY is settled and ready
+ */
+ udelay(10);
/*
* An undocumented "feature" in the OMAP3 EHCI controller,
omap_usbhs_set_mode(i, mode);
}
- return omap_ehci_hcd_init(0, &usbhs_bdata);
+ return 0;
}
static const struct udevice_id omap_usbhs_dt_ids[] = {
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-struct ehci_omap_priv_data {
- struct ehci_ctrl ctrl;
- struct omap_ehci *ehci;
-#ifdef CONFIG_DM_REGULATOR
- struct udevice *vbus_supply;
-#endif
- enum usb_init_type init_type;
- int portnr;
- struct phy phy[OMAP_HS_USB_PORTS];
- int nports;
-};
-
static int ehci_usb_of_to_plat(struct udevice *dev)
{
struct usb_plat *plat = dev_get_plat(dev);
return 0;
}
+/*
+ * This driver references phys based on the USB port. If
+ * the port is unused, the corresponding phy is listed as NULL
+ * which generic_phy_init_bulk treats as an error, so we need
+ * a custom one that tolerates empty phys
+ */
+static int omap_ehci_phy_get(struct udevice *dev)
+{
+ struct ehci_omap_priv_data *priv = dev_get_priv(dev);
+ int i, ret;
+
+ for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
+ ret = generic_phy_get_by_index(dev, i, &priv->phy[i]);
+ if (ret && ret != -ENOENT)
+ return ret;
+ };
+
+ return 0;
+};
+
static int omap_ehci_probe(struct udevice *dev)
{
struct usb_plat *plat = dev_get_plat(dev);
struct ehci_omap_priv_data *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
+ int ret;
priv->ehci = dev_read_addr_ptr(dev);
priv->portnr = dev_seq(dev);
hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;
+ /* Identify Phys */
+ ret = omap_ehci_phy_get(dev);
+ if (ret) {
+ printf("Failed to get phys\n");
+ return ret;
+ }
+
+ /* Register the EHCI */
+ ret = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+ if (ret) {
+ printf("Failed to register EHCI\n");
+ return ret;
+ }
+
+ ret = omap_ehci_hcd_init(0, &usbhs_bdata, dev);
+ if (ret)
+ return ret;
+
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
}
/*
+ * Send reset endpoint command for given endpoint. This recovers from a
+ * halted endpoint (e.g. due to a stall error).
+ */
+static void reset_ep(struct usb_device *udev, int ep_index)
+{
+ struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
+ struct xhci_ring *ring = ctrl->devs[udev->slot_id]->eps[ep_index].ring;
+ union xhci_trb *event;
+ u32 field;
+
+ printf("Resetting EP %d...\n", ep_index);
+ xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_RESET_EP);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ field = le32_to_cpu(event->trans_event.flags);
+ BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
+ xhci_acknowledge_event(ctrl);
+
+ xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue |
+ ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+ != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
+ event->event_cmd.status)) != COMP_SUCCESS);
+ xhci_acknowledge_event(ctrl);
+}
+
+/*
* Stops transfer processing for an endpoint and throws away all unprocessed
* TRBs by setting the xHC's dequeue pointer to our enqueue pointer. The next
* xhci_bulk_tx/xhci_ctrl_tx on this enpoint will add new transfers there and
record_transfer_result(udev, event, length);
xhci_acknowledge_event(ctrl);
+ if (udev->status == USB_ST_STALLED) {
+ reset_ep(udev, ep_index);
+ return -EPIPE;
+ }
/* Invalidate buffer to make it available to usb-core */
if (length > 0)
config VIDEO_SEPS525
bool "Enable video support for Seps525"
- depends on DM_VIDEO
+ depends on DM_VIDEO && DM_GPIO
help
Enable support for the Syncoam PM-OLED display driver (RGB 160x128).
Currently driver is supporting only SPI interface.
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.
+config WDT_SL28CPLD
+ bool "sl28cpld watchdog timer support"
+ depends on WDT && SL28CPLD
+ help
+ Enable support for the watchdog timer in the Kontron sl28cpld
+ management controller.
+
config WDT_SP805
bool "SP805 watchdog timer support"
depends on WDT
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
+obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
struct a37xx_wdt *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = dev_read_addr_index(dev, 0);
- if (addr == FDT_ADDR_T_NONE)
- goto err;
- priv->sel_reg = (void __iomem *)addr;
+ priv->sel_reg = (void __iomem *)MVEBU_REGISTER(0x0d064);
- addr = dev_read_addr_index(dev, 1);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
goto err;
priv->reg = (void __iomem *)addr;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog driver for the sl28cpld
+ *
+ * Copyright (c) 2021 Michael Walle <michael@walle.cc>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <sl28cpld.h>
+#include <div64.h>
+
+#define SL28CPLD_WDT_CTRL 0x00
+#define WDT_CTRL_EN0 BIT(0)
+#define WDT_CTRL_EN1 BIT(1)
+#define WDT_CTRL_EN_MASK GENMASK(1, 0)
+#define WDT_CTRL_LOCK BIT(2)
+#define WDT_CTRL_ASSERT_SYS_RESET BIT(6)
+#define WDT_CTRL_ASSERT_WDT_TIMEOUT BIT(7)
+#define SL28CPLD_WDT_TIMEOUT 0x01
+#define SL28CPLD_WDT_KICK 0x02
+#define WDT_KICK_VALUE 0x6b
+
+static int sl28cpld_wdt_reset(struct udevice *dev)
+{
+ return sl28cpld_write(dev, SL28CPLD_WDT_KICK, WDT_KICK_VALUE);
+}
+
+static int sl28cpld_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ int ret, val;
+
+ val = sl28cpld_read(dev, SL28CPLD_WDT_CTRL);
+ if (val < 0)
+ return val;
+
+ /* (1) disable watchdog */
+ val &= ~WDT_CTRL_EN_MASK;
+ ret = sl28cpld_write(dev, SL28CPLD_WDT_CTRL, val);
+ if (ret)
+ return ret;
+
+ /* (2) set timeout */
+ ret = sl28cpld_write(dev, SL28CPLD_WDT_TIMEOUT, lldiv(timeout, 1000));
+ if (ret)
+ return ret;
+
+ /* (3) kick it, will reset timer to the timeout value */
+ ret = sl28cpld_wdt_reset(dev);
+ if (ret)
+ return ret;
+
+ /* (4) enable either recovery or normal one */
+ if (flags & BIT(0))
+ val |= WDT_CTRL_EN1;
+ else
+ val |= WDT_CTRL_EN0;
+
+ if (flags & BIT(1))
+ val |= WDT_CTRL_LOCK;
+
+ if (flags & BIT(2))
+ val &= ~WDT_CTRL_ASSERT_SYS_RESET;
+ else
+ val |= WDT_CTRL_ASSERT_SYS_RESET;
+
+ if (flags & BIT(3))
+ val |= WDT_CTRL_ASSERT_WDT_TIMEOUT;
+ else
+ val &= ~WDT_CTRL_ASSERT_WDT_TIMEOUT;
+
+ return sl28cpld_write(dev, SL28CPLD_WDT_CTRL, val);
+}
+
+static int sl28cpld_wdt_stop(struct udevice *dev)
+{
+ int val;
+
+ val = sl28cpld_read(dev, SL28CPLD_WDT_CTRL);
+ if (val < 0)
+ return val;
+
+ return sl28cpld_write(dev, SL28CPLD_WDT_CTRL, val & ~WDT_CTRL_EN_MASK);
+}
+
+static int sl28cpld_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ return sl28cpld_wdt_start(dev, 0, flags);
+}
+
+static const struct wdt_ops sl28cpld_wdt_ops = {
+ .start = sl28cpld_wdt_start,
+ .reset = sl28cpld_wdt_reset,
+ .stop = sl28cpld_wdt_stop,
+ .expire_now = sl28cpld_wdt_expire_now,
+};
+
+static const struct udevice_id sl28cpld_wdt_ids[] = {
+ { .compatible = "kontron,sl28cpld-wdt", },
+ {}
+};
+
+U_BOOT_DRIVER(sl28cpld_wdt) = {
+ .name = "sl28cpld-wdt",
+ .id = UCLASS_WDT,
+ .of_match = sl28cpld_wdt_ids,
+ .ops = &sl28cpld_wdt_ops,
+};
.dtsi files that will also be used.
config OF_LIST
- string "List of device tree files to include for DT control"
- depends on SPL_LOAD_FIT || MULTI_DTB_FIT
+ string "List of device tree files to include for DT control" if SPL_LOAD_FIT || MULTI_DTB_FIT
+ depends on OF_CONTROL
default DEFAULT_DEVICE_TREE
help
This option specifies a list of device tree files to use for DT
capabilities, pad configurations).
config SPL_OF_LIST
- string "List of device tree files to include for DT control in SPL"
- depends on SPL_MULTI_DTB_FIT
+ string "List of device tree files to include for DT control in SPL" if SPL_MULTI_DTB_FIT
+ depends on SPL_OF_CONTROL
default OF_LIST
help
This option specifies a list of device tree files to use for DT
*/
int acpi_fill_csrt(struct acpi_ctx *ctx);
+/**
+ * write_acpi_tables() - Write out the ACPI tables
+ *
+ * This writes all ACPI tables to the given address
+ *
+ * @start: Start address for the tables
+ * @return address of end of tables, where the next tables can be written
+ */
+ulong write_acpi_tables(ulong start);
+
#endif /* !__ACPI__*/
#include <asm/acpi_table.h>
* 8-bit (register) and 16-bit (data) accesses might use different
* address spaces. This is implemented by the following definitions.
*/
-#ifndef CONFIG_SYS_ATA_STRIDE
-#define CONFIG_SYS_ATA_STRIDE 1
-#endif
#define ATA_IO_DATA(x) (CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE))
#define ATA_IO_REG(x) (CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
u32 spare;
};
-/* access CONFIG_BLOBLIST_ADDR, dealing with it possibly not being defined */
-static inline ulong bloblist_addr(void)
-{
-#ifdef CONFIG_BLOBLIST_FIXED
- return CONFIG_BLOBLIST_ADDR;
-#else
- return 0;
-#endif
-}
-
/**
* bloblist_check_magic() - return a bloblist if the magic matches
*
/**
* struct clk_ops - The functions that a clock driver must implement.
+ * @of_xlate: Translate a client's device-tree (OF) clock specifier.
+ * @request: Request a translated clock.
+ * @rfree: Free a previously requested clock.
+ * @round_rate: Adjust a rate to the exact rate a clock can provide.
+ * @get_rate: Get current clock rate.
+ * @set_rate: Set current clock rate.
+ * @set_parent: Set current clock parent
+ * @enable: Enable a clock.
+ * @disable: Disable a clock.
+ *
+ * The individual methods are described more fully below.
*/
struct clk_ops {
- /**
- * of_xlate - Translate a client's device-tree (OF) clock specifier.
- *
- * The clock core calls this function as the first step in implementing
- * a client's clk_get_by_*() call.
- *
- * If this function pointer is set to NULL, the clock core will use a
- * default implementation, which assumes #clock-cells = <1>, and that
- * the DT cell contains a simple integer clock ID.
- *
- * At present, the clock API solely supports device-tree. If this
- * changes, other xxx_xlate() functions may be added to support those
- * other mechanisms.
- *
- * @clock: The clock struct to hold the translation result.
- * @args: The clock specifier values from device tree.
- * @return 0 if OK, or a negative error code.
- */
int (*of_xlate)(struct clk *clock,
struct ofnode_phandle_args *args);
- /**
- * request - Request a translated clock.
- *
- * The clock core calls this function as the second step in
- * implementing a client's clk_get_by_*() call, following a successful
- * xxx_xlate() call, or as the only step in implementing a client's
- * clk_request() call.
- *
- * @clock: The clock struct to request; this has been fille in by
- * a previoux xxx_xlate() function call, or by the caller
- * of clk_request().
- * @return 0 if OK, or a negative error code.
- */
int (*request)(struct clk *clock);
- /**
- * rfree - Free a previously requested clock.
- *
- * This is the implementation of the client clk_free() API.
- *
- * @clock: The clock to free.
- * @return 0 if OK, or a negative error code.
- */
int (*rfree)(struct clk *clock);
- /**
- * round_rate() - Adjust a rate to the exact rate a clock can provide.
- *
- * @clk: The clock to manipulate.
- * @rate: Desidered clock rate in Hz.
- * @return rounded rate in Hz, or -ve error code.
- */
ulong (*round_rate)(struct clk *clk, ulong rate);
- /**
- * get_rate() - Get current clock rate.
- *
- * @clk: The clock to query.
- * @return clock rate in Hz, or -ve error code
- */
ulong (*get_rate)(struct clk *clk);
- /**
- * set_rate() - Set current clock rate.
- *
- * @clk: The clock to manipulate.
- * @rate: New clock rate in Hz.
- * @return new rate, or -ve error code.
- */
ulong (*set_rate)(struct clk *clk, ulong rate);
- /**
- * set_parent() - Set current clock parent
- *
- * @clk: The clock to manipulate.
- * @parent: New clock parent.
- * @return zero on success, or -ve error code.
- */
int (*set_parent)(struct clk *clk, struct clk *parent);
- /**
- * enable() - Enable a clock.
- *
- * @clk: The clock to manipulate.
- * @return zero on success, or -ve error code.
- */
int (*enable)(struct clk *clk);
- /**
- * disable() - Disable a clock.
- *
- * @clk: The clock to manipulate.
- * @return zero on success, or -ve error code.
- */
int (*disable)(struct clk *clk);
};
+#if 0 /* For documentation only */
+/**
+ * of_xlate() - Translate a client's device-tree (OF) clock specifier.
+ * @clock: The clock struct to hold the translation result.
+ * @args: The clock specifier values from device tree.
+ *
+ * The clock core calls this function as the first step in implementing
+ * a client's clk_get_by_*() call.
+ *
+ * If this function pointer is set to NULL, the clock core will use a
+ * default implementation, which assumes #clock-cells = <1>, and that
+ * the DT cell contains a simple integer clock ID.
+ *
+ * At present, the clock API solely supports device-tree. If this
+ * changes, other xxx_xlate() functions may be added to support those
+ * other mechanisms.
+ *
+ * Return: 0 if OK, or a negative error code.
+ */
+int of_xlate(struct clk *clock, struct ofnode_phandle_args *args);
+
+/**
+ * request() - Request a translated clock.
+ * @clock: The clock struct to request; this has been fille in by
+ * a previoux xxx_xlate() function call, or by the caller
+ * of clk_request().
+ *
+ * The clock core calls this function as the second step in
+ * implementing a client's clk_get_by_*() call, following a successful
+ * xxx_xlate() call, or as the only step in implementing a client's
+ * clk_request() call.
+ *
+ * Return: 0 if OK, or a negative error code.
+ */
+int request(struct clk *clock);
+
+/**
+ * rfree() - Free a previously requested clock.
+ * @clock: The clock to free.
+ *
+ * This is the implementation of the client clk_free() API.
+ *
+ * Return: 0 if OK, or a negative error code.
+ */
+int rfree(struct clk *clock);
+
+/**
+ * round_rate() - Adjust a rate to the exact rate a clock can provide.
+ * @clk: The clock to manipulate.
+ * @rate: Desidered clock rate in Hz.
+ *
+ * Return: rounded rate in Hz, or -ve error code.
+ */
+ulong round_rate(struct clk *clk, ulong rate);
+
+/**
+ * get_rate() - Get current clock rate.
+ * @clk: The clock to query.
+ *
+ * Return: clock rate in Hz, or -ve error code
+ */
+ulong get_rate(struct clk *clk);
+
+/**
+ * set_rate() - Set current clock rate.
+ * @clk: The clock to manipulate.
+ * @rate: New clock rate in Hz.
+ *
+ * Return: new rate, or -ve error code.
+ */
+ulong set_rate(struct clk *clk, ulong rate);
+
+/**
+ * set_parent() - Set current clock parent
+ * @clk: The clock to manipulate.
+ * @parent: New clock parent.
+ *
+ * Return: zero on success, or -ve error code.
+ */
+int set_parent(struct clk *clk, struct clk *parent);
+
+/**
+ * enable() - Enable a clock.
+ * @clk: The clock to manipulate.
+ *
+ * Return: zero on success, or -ve error code.
+ */
+int enable(struct clk *clk);
+
+/**
+ * disable() - Disable a clock.
+ * @clk: The clock to manipulate.
+ *
+ * Return: zero on success, or -ve error code.
+ */
+int disable(struct clk *clk);
+#endif
+
#endif
#include <linux/types.h>
/**
+ * DOC: Overview
+ *
* A clock is a hardware signal that oscillates autonomously at a specific
* frequency and duty cycle. Most hardware modules require one or more clock
* signal to drive their operation. Clock signals are typically generated
/**
* struct clk - A handle to (allowing control of) a single clock.
- *
- * Clients provide storage for clock handles. The content of the structure is
- * managed solely by the clock API and clock drivers. A clock struct is
- * initialized by "get"ing the clock struct. The clock struct is passed to all
- * other clock APIs to identify which clock signal to operate upon.
- *
* @dev: The device which implements the clock signal.
* @rate: The clock rate (in HZ).
- * @flags: Flags used across common clock structure (e.g. CLK_)
+ * @flags: Flags used across common clock structure (e.g. %CLK_)
* Clock IP blocks specific flags (i.e. mux, div, gate, etc) are defined
- * in struct's for those devices (e.g. struct clk_mux).
+ * in struct's for those devices (e.g. &struct clk_mux).
+ * @enable_count: The number of times this clock has been enabled.
* @id: The clock signal ID within the provider.
* @data: An optional data field for scenarios where a single integer ID is not
* sufficient. If used, it can be populated through an .of_xlate op and
* processed during the various clock ops.
*
+ * Clients provide storage for clock handles. The content of the structure is
+ * managed solely by the clock API and clock drivers. A clock struct is
+ * initialized by "get"ing the clock struct. The clock struct is passed to all
+ * other clock APIs to identify which clock signal to operate upon.
+ *
* Should additional information to identify and configure any clock signal
* for any provider be required in the future, the struct could be expanded to
* either (a) add more fields to allow clock providers to store additional
/**
* struct clk_bulk - A handle to (allowing control of) a bulk of clocks.
+ * @clks: An array of clock handles.
+ * @count: The number of clock handles in the clks array.
*
* Clients provide storage for the clock bulk. The content of the structure is
* managed solely by the clock API. A clock bulk struct is
* initialized by "get"ing the clock bulk struct.
* The clock bulk struct is passed to all other bulk clock APIs to apply
* the API to all the clock in the bulk struct.
- *
- * @clks: An array of clock handles.
- * @count: The number of clock handles in the clks array.
*/
struct clk_bulk {
struct clk *clks;
struct phandle_1_arg;
/**
* clk_get_by_phandle() - Get a clock by its phandle information (of-platadata)
+ * @dev: Device containing the phandle
+ * @cells: Phandle info
+ * @clk: A pointer to a clock struct to initialise
*
* This function is used when of-platdata is enabled.
*
* This looks up a clock using the phandle info. With dtoc, each phandle in the
- * 'clocks' property is transformed into an idx representing the device. For
- * example:
+ * 'clocks' property is transformed into an idx representing the device.
+ * For example::
*
* clocks = <&dpll_mpu_ck 23>;
*
- * might result in:
+ * might result in::
*
* .clocks = {1, {23}},},
*
* this example it would return a clock containing the 'dpll_mpu_ck' device and
* the clock ID 23.
*
- * @dev: Device containing the phandle
- * @cells: Phandle info
- * @clock: A pointer to a clock struct to initialise
* Return: 0 if OK, or a negative error code.
*/
int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells,
/**
* clk_get_by_index() - Get/request a clock by integer index.
+ * @dev: The client device.
+ * @index: The index of the clock to request, within the client's list of
+ * clocks.
+ * @clk: A pointer to a clock struct to initialize.
*
* This looks up and requests a clock. The index is relative to the client
* device; each device is assumed to have n clocks associated with it somehow,
* device clock indices to provider clocks may be via device-tree properties,
* board-provided mapping tables, or some other mechanism.
*
- * @dev: The client device.
- * @index: The index of the clock to request, within the client's list of
- * clocks.
- * @clock A pointer to a clock struct to initialize.
* Return: 0 if OK, or a negative error code.
*/
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
/**
- * clk_get_by_index_nodev - Get/request a clock by integer index
- * without a device.
- *
- * This is a version of clk_get_by_index() that does not use a device.
- *
+ * clk_get_by_index_nodev() - Get/request a clock by integer index without a
+ * device.
* @node: The client ofnode.
* @index: The index of the clock to request, within the client's list of
* clocks.
- * @clock A pointer to a clock struct to initialize.
+ * @clk: A pointer to a clock struct to initialize.
+ *
* Return: 0 if OK, or a negative error code.
*/
int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk);
/**
- * clk_get_bulk - Get/request all clocks of a device.
+ * clk_get_bulk() - Get/request all clocks of a device.
+ * @dev: The client device.
+ * @bulk: A pointer to a clock bulk struct to initialize.
*
* This looks up and requests all clocks of the client device; each device is
* assumed to have n clocks associated with it somehow, and this function finds
* device clock indices to provider clocks may be via device-tree properties,
* board-provided mapping tables, or some other mechanism.
*
- * @dev: The client device.
- * @bulk A pointer to a clock bulk struct to initialize.
* Return: 0 if OK, or a negative error code.
*/
int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk);
/**
- * clk_get_by_name - Get/request a clock by name.
+ * clk_get_by_name() - Get/request a clock by name.
+ * @dev: The client device.
+ * @name: The name of the clock to request, within the client's list of
+ * clocks.
+ * @clk: A pointer to a clock struct to initialize.
*
* This looks up and requests a clock. The name is relative to the client
* device; each device is assumed to have n clocks associated with it somehow,
* device clock names to provider clocks may be via device-tree properties,
* board-provided mapping tables, or some other mechanism.
*
- * @dev: The client device.
- * @name: The name of the clock to request, within the client's list of
- * clocks.
- * @clock: A pointer to a clock struct to initialize.
* Return: 0 if OK, or a negative error code.
*/
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
/**
* clk_get_by_name_nodev - Get/request a clock by name without a device.
- *
- * This is a version of clk_get_by_name() that does not use a device.
- *
* @node: The client ofnode.
* @name: The name of the clock to request, within the client's list of
* clocks.
- * @clock: A pointer to a clock struct to initialize.
+ * @clk: A pointer to a clock struct to initialize.
+ *
* Return: 0 if OK, or a negative error code.
*/
int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk);
/**
- * clk_get_optional_nodev - Get/request an optinonal clock by name
- * without a device.
- * @node: The client ofnode.
- * @name: The name of the clock to request.
- * @name: The name of the clock to request, within the client's list of
- * clocks.
- * @clock: A pointer to a clock struct to initialize.
- *
- * Behaves the same as clk_get_by_name_nodev() except where there is
- * no clock producer, in this case, skip the error number -ENODATA, and
- * the function returns 0.
- */
-int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk);
-
-/**
- * devm_clk_get - lookup and obtain a managed reference to a clock producer.
+ * devm_clk_get() - lookup and obtain a managed reference to a clock producer.
* @dev: device for clock "consumer"
* @id: clock consumer ID
*
- * Returns a struct clk corresponding to the clock producer, or
- * valid IS_ERR() condition containing errno. The implementation
- * uses @dev and @id to determine the clock consumer, and thereby
- * the clock producer. (IOW, @id may be identical strings, but
- * clk_get may return different clock producers depending on @dev.)
+ * The implementation uses @dev and @id to determine the clock consumer, and
+ * thereby the clock producer. (IOW, @id may be identical strings, but clk_get
+ * may return different clock producers depending on @dev.)
*
* Drivers must assume that the clock source is not enabled.
*
- * devm_clk_get should not be called from within interrupt context.
- *
* The clock will automatically be freed when the device is unbound
* from the bus.
+ *
+ * Return:
+ * a struct clk corresponding to the clock producer, or
+ * valid IS_ERR() condition containing errno
*/
struct clk *devm_clk_get(struct udevice *dev, const char *id);
/**
- * devm_clk_get_optional - lookup and obtain a managed reference to an optional
- * clock producer.
+ * devm_clk_get_optional() - lookup and obtain a managed reference to an
+ * optional clock producer.
* @dev: device for clock "consumer"
* @id: clock consumer ID
*
* Behaves the same as devm_clk_get() except where there is no clock producer.
- * In this case, instead of returning -ENOENT, the function returns NULL.
+ * In this case, instead of returning -%ENOENT, the function returns NULL.
*/
-struct clk *devm_clk_get_optional(struct udevice *dev, const char *id);
+static inline struct clk *devm_clk_get_optional(struct udevice *dev,
+ const char *id)
+{
+ struct clk *clk = devm_clk_get(dev, id);
+
+ if (PTR_ERR(clk) == -ENODATA)
+ return NULL;
+
+ return clk;
+}
/**
* clk_release_all() - Disable (turn off)/Free an array of previously
* requested clocks.
+ * @clk: A clock struct array that was previously successfully
+ * requested by clk_request/get_by_*().
+ * @count: Number of clock contained in the array
*
* For each clock contained in the clock array, this function will check if
* clock has been previously requested and then will disable and free it.
*
- * @clk: A clock struct array that was previously successfully
- * requested by clk_request/get_by_*().
- * @count Number of clock contained in the array
* Return: zero on success, or -ve error code.
*/
int clk_release_all(struct clk *clk, int count);
return -ENOSYS;
}
-static inline int
-clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
+static inline int clk_release_all(struct clk *clk, int count)
{
return -ENOSYS;
}
+#endif
-static inline int clk_release_all(struct clk *clk, int count)
+/**
+ * clk_get_by_name_optional() - Get/request a optional clock by name.
+ * @dev: The client device.
+ * @name: The name of the clock to request, within the client's list of
+ * clocks.
+ * @clk: A pointer to a clock struct to initialize.
+ *
+ * Behaves the same as clk_get_by_name(), except when there is no clock
+ * provider. In the latter case, return 0.
+ *
+ * Return: 0 if OK, or a negative error code.
+ */
+static inline int clk_get_by_name_optional(struct udevice *dev,
+ const char *name, struct clk *clk)
{
- return -ENOSYS;
+ int ret;
+
+ ret = clk_get_by_name(dev, name, clk);
+ if (ret == -ENODATA)
+ return 0;
+
+ return ret;
+}
+
+/**
+ * clk_get_by_name_nodev_optional - Get/request an optinonal clock by name
+ * without a device.
+ * @node: The client ofnode.
+ * @name: The name of the clock to request, within the client's list of
+ * clocks.
+ * @clk: A pointer to a clock struct to initialize.
+ *
+ * Behaves the same as clk_get_by_name_nodev() except where there is
+ * no clock producer, in this case, skip the error number -%ENODATA, and
+ * the function returns 0.
+ */
+static inline int clk_get_by_name_nodev_optional(ofnode node, const char *name,
+ struct clk *clk)
+{
+ int ret;
+
+ ret = clk_get_by_name_nodev(node, name, clk);
+ if (ret == -ENODATA)
+ return 0;
+
+ return ret;
}
-#endif
/**
* enum clk_defaults_stage - What stage clk_set_defaults() is called at
#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(CLK)
/**
- * clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}'
+ * clk_set_defaults - Process ``assigned-{clocks/clock-parents/clock-rates}``
* properties to configure clocks
- *
* @dev: A device to process (the ofnode associated with this device
* will be processed).
* @stage: The stage of the probing process this function is called during.
+ *
+ * Return: zero on success, or -ve error code.
*/
int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage);
#else
/**
* clk_release_bulk() - Disable (turn off)/Free an array of previously
* requested clocks in a clock bulk struct.
+ * @bulk: A clock bulk struct that was previously successfully
+ * requested by clk_get_bulk().
*
* For each clock contained in the clock bulk struct, this function will check
* if clock has been previously requested and then will disable and free it.
*
- * @clk: A clock bulk struct that was previously successfully
- * requested by clk_get_bulk().
* Return: zero on success, or -ve error code.
*/
static inline int clk_release_bulk(struct clk_bulk *bulk)
#if CONFIG_IS_ENABLED(CLK)
/**
- * clk_request - Request a clock by provider-specific ID.
+ * clk_request() - Request a clock by provider-specific ID.
+ * @dev: The clock provider device.
+ * @clk: A pointer to a clock struct to initialize. The caller must
+ * have already initialized any field in this struct which the
+ * clock provider uses to identify the clock.
*
* This requests a clock using a provider-specific ID. Generally, this function
* should not be used, since clk_get_by_index/name() provide an interface that
* better separates clients from intimate knowledge of clock providers.
* However, this function may be useful in core SoC-specific code.
*
- * @dev: The clock provider device.
- * @clock: A pointer to a clock struct to initialize. The caller must
- * have already initialized any field in this struct which the
- * clock provider uses to identify the clock.
* Return: 0 if OK, or a negative error code.
*/
int clk_request(struct udevice *dev, struct clk *clk);
/**
- * clk_free - Free a previously requested clock.
- *
- * @clock: A clock struct that was previously successfully requested by
+ * clk_free() - Free a previously requested clock.
+ * @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
+ *
* Return: 0 if OK, or a negative error code.
*/
int clk_free(struct clk *clk);
/**
* clk_get_rate() - Get current clock rate.
- *
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
+ *
* Return: clock rate in Hz on success, 0 for invalid clock, or -ve error code
* for other errors.
*/
/**
* clk_get_parent() - Get current clock's parent.
- *
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
+ *
* Return: pointer to parent's struct clk, or error code passed as pointer
*/
struct clk *clk_get_parent(struct clk *clk);
/**
* clk_get_parent_rate() - Get parent of current clock rate.
- *
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
+ *
* Return: clock rate in Hz, or -ve error code.
*/
long long clk_get_parent_rate(struct clk *clk);
/**
* clk_round_rate() - Adjust a rate to the exact rate a clock can provide
+ * @clk: A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @rate: desired clock rate in Hz.
*
* This answers the question "if I were to pass @rate to clk_set_rate(),
* what clock rate would I end up with?" without changing the hardware
- * in any way. In other words:
+ * in any way. In other words::
*
* rate = clk_round_rate(clk, r);
*
- * and:
+ * and::
*
* rate = clk_set_rate(clk, r);
*
* are equivalent except the former does not modify the clock hardware
* in any way.
*
- * @clk: A clock struct that was previously successfully requested by
- * clk_request/get_by_*().
- * @rate: desired clock rate in Hz.
* Return: rounded rate in Hz, or -ve error code.
*/
ulong clk_round_rate(struct clk *clk, ulong rate);
/**
* clk_set_rate() - Set current clock rate.
- *
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
* @rate: New clock rate in Hz.
+ *
* Return: new rate, or -ve error code.
*/
ulong clk_set_rate(struct clk *clk, ulong rate);
/**
* clk_set_parent() - Set current clock parent.
- *
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
* @parent: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
+ *
* Return: new rate, or -ve error code.
*/
int clk_set_parent(struct clk *clk, struct clk *parent);
/**
* clk_enable() - Enable (turn on) a clock.
- *
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
+ *
* Return: zero on success, or -ve error code.
*/
int clk_enable(struct clk *clk);
/**
* clk_enable_bulk() - Enable (turn on) all clocks in a clock bulk struct.
- *
* @bulk: A clock bulk struct that was previously successfully requested
* by clk_get_bulk().
+ *
* Return: zero on success, or -ve error code.
*/
int clk_enable_bulk(struct clk_bulk *bulk);
/**
* clk_disable() - Disable (turn off) a clock.
- *
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
+ *
* Return: zero on success, or -ve error code.
*/
int clk_disable(struct clk *clk);
/**
* clk_disable_bulk() - Disable (turn off) all clocks in a clock bulk struct.
- *
* @bulk: A clock bulk struct that was previously successfully requested
* by clk_get_bulk().
+ *
* Return: zero on success, or -ve error code.
*/
int clk_disable_bulk(struct clk_bulk *bulk);
* @p: clk compared against q
* @q: clk compared against p
*
- * Returns true if the two struct clk pointers both point to the same hardware
- * clock node.
- *
- * Returns false otherwise. Note that two NULL clks are treated as matching.
+ * Return:
+ * %true if the two struct clk pointers both point to the same hardware clock
+ * node, and %false otherwise. Note that two %NULL clks are treated as matching.
*/
bool clk_is_match(const struct clk *p, const struct clk *q);
/**
* clk_get_by_id() - Get the clock by its ID
- *
* @id: The clock ID to search for
- *
* @clkp: A pointer to clock struct that has been found among added clocks
* to UCLASS_CLK
+ *
* Return: zero on success, or -ENOENT on error
*/
int clk_get_by_id(ulong id, struct clk **clkp);
/**
* clk_dev_binded() - Check whether the clk has a device binded
- *
- * @clk A pointer to the clk
+ * @clk: A pointer to the clk
*
* Return: true on binded, or false on no
*/
/**
* clk_valid() - check if clk is valid
- *
* @clk: the clock to check
+ *
* Return: true if valid, or false
*/
static inline bool clk_valid(struct clk *clk)
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
-/*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-
-
#endif /* __CONFIG_H */
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
-/*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-
-
#endif /* __CONFIG_H */
#ifdef CONFIG_IDE
/* ATA */
-# define CONFIG_IDE_RESET 1
# define CONFIG_IDE_PREINIT 1
-# define CONFIG_ATAPI
# undef CONFIG_LBA48
-
-# define CONFIG_SYS_IDE_MAXBUS 1
-# define CONFIG_SYS_IDE_MAXDEVICE 2
-
-# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
-# define CONFIG_SYS_ATA_IDE0_OFFSET 0
-
-# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
-# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
-# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
-# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
#endif
#define CONFIG_DRIVER_DM9000
/*
* SATA
*/
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_PCIE3
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
#define CONFIG_SYS_SRIO
/* SATA */
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_NET_RETRY_COUNT 10
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x040000 : QSPI.SPL (256KiB)
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
#include <linux/sizes.h>
#include <linux/stringify.h>
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "bootcmd=run distro_bootcmd ; " \
- "usb start ; " \
- "setenv stdout serial,vidconsole; " \
- "setenv stdin serial,usbkbd\0" \
"boot_file=zImage\0" \
"console=ttymxc0\0" \
"defargs=enable_wait_mode=off vmalloc=400M\0" \
/* Environment */
#define ENV_DEVICE_SETTINGS \
- "stdin=serial,usbkbd\0" \
+ "stdin=serial,usbkbd,spikbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define ENV_MEM_LAYOUT_SETTINGS \
- "fdt_addr_r=0x960100000\0" \
- "kernel_addr_r=0x960200000\0"
+#if CONFIG_IS_ENABLED(CMD_NVME)
+ #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0)
+#else
+ #define BOOT_TARGET_NVME(func)
+#endif
#if CONFIG_IS_ENABLED(CMD_USB)
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#endif
#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_NVME(func) \
BOOT_TARGET_USB(func)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_DEVICE_SETTINGS \
- ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif
#define CONFIG_FACTORYSET
-#define CONFIG_REMAKE_ELF
-
/* ENET Config */
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
-#define CONFIG_REMAKE_ELF
-
/* Flat Device Tree Definitions */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_PCI_SCAN_SHOW
#endif
-/* SATA support */
-#ifdef CONFIG_SCSI
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
/* SATA */
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
-
-/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE)
+#endif
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
#include <linux/sizes.h>
#include <linux/stringify.h>
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "bootcmd=run distro_bootcmd; " \
- "usb start ; " \
- "setenv stdout serial,vidconsole; " \
- "setenv stdin serial,usbkbd\0" \
"boot_file=zImage\0" \
"console=ttymxc0\0" \
"defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/* environment organization */
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE)
+#endif
+
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6318.h>
-#define CONFIG_REMAKE_ELF
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6328.h>
-#define CONFIG_REMAKE_ELF
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6348.h>
-#define CONFIG_REMAKE_ELF
#include <configs/bmips_common.h>
#include <configs/bmips_bcm63268.h>
-#define CONFIG_REMAKE_ELF
-
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif /* CONFIG_MTD_RAW_NAND */
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6368.h>
-#define CONFIG_REMAKE_ELF
* U-Boot into it.
*/
-/*
- * SATA/SCSI/AHCI configuration
- */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
"stderr=serial,vidconsole\0"
/* ATA/IDE support */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_ATAPI
#endif /* __CONFIG_H */
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
/* I2C */
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-/*
- * SATA/SCSI/AHCI configuration
- */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
/* PCIe support */
/* FEC ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_FEC_MXC_PHYADDR 7
#define CONFIG_ARP_TIMEOUT 200UL
/* MMC Configs */
"ramdisk_addr_r=0x18000000\0" \
"scriptaddr=0x14000000\0" \
"fdtfile=imx6q-dhcom-pdk2.dtb\0"\
+ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+ "load mmc 0:1 ${loadaddr} /boot/u-boot-with-spl.imx && "\
+ "sf probe && sf erase 0x0 0xa0000 && " \
+ "sf write ${loadaddr} 0x400 ${filesize}\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
/* SPDX-License-Identifier: GPL-2.0+ */
/*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.h originally written by
#include "mv-common.h"
/*
- * Environment variables configurations
- */
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-
-/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT \
"kernel=/boot/uImage\0" \
"initrd=/boot/uInitrd\0" \
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
/*
* Ethernet Driver configuration
*/
-#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
-/*
- * File system
- */
+#ifdef CONFIG_RESET_PHY_R
+#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
+#endif
#endif /* _CONFIG_DOCKSTAR_H */
/* SPI SPL */
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
#include <asm/arch/sysmap-apq8016.h>
/* Build new ELF image from u-boot.bin (U-Boot + appended DTB) */
-#define CONFIG_REMAKE_ELF
/* Physical Memory Map */
#define PHYS_SDRAM_1 0x80000000
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2011
- * Jason Cooper <u-boot@lakedaemon.net>
+ * (C) Copyright 2022 Tony Dinh <mibodhi@gmail.com>
+ * (C) Copyright 2011 Jason Cooper <u-boot@lakedaemon.net>
*
* Based on work by:
* Marvell Semiconductor <www.marvell.com>
#include "mv-common.h"
/*
- * Environment variables configurations
- */
-
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-
-/*
* Default environment variables
*/
/*
* Ethernet Driver configuration
*/
-#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
+#ifdef CONFIG_RESET_PHY_R
+#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
+#endif
/*
* SATA Driver configuration
*/
-#ifdef CONFIG_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
-#endif /* CONFIG_SATA */
#endif /* _CONFIG_DREAMPLUG_H */
/* PCI CONFIG */
#define CONFIG_PCI_SCAN_SHOW
-/* SCSI */
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE 128
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SATA_MAX_DEVICE 4
-
/* BOOT */
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
#ifdef CONFIG_IDE
#define __io
/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* A single bus, a single device */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
-#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
/* end of IDE defines */
#endif /* CMD_IDE */
"stderr=serial,vidconsole\0"
/* ATA/IDE support */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_ATAPI
#endif /* __CONFIG_H */
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#endif
/* SATA driver configuration */
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#endif /* _CONFIG_GOFLEXHOME_H */
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
- #define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
"splashpos=m,m\0" \
- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \
"bootdevs=usb mmc sata flash\0" \
#define CONFIG_PCI_SCAN_SHOW
#endif
-/* SATA support */
-#ifdef CONFIG_SCSI
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
#define CONFIG_POWER_HI6553
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* Physical Memory Map */
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6358.h>
-#define CONFIG_REMAKE_ELF
*/
#ifdef CONFIG_IDE
#define __io
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /* CONFIG_IDE */
#endif /* _CONFIG_IB62x0_H */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* (C) Copyright 2009-2012
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
* Luka Perkov <luka@openwrt.org>
#include "mv-common.h"
-/*
- * Environment variables configuration
- */
-
-/*
- * Default environment variables
- */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT \
"kernel=/boot/uImage\0" \
"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
/*
* Ethernet driver configuration
+ *
+ * This board has PCIe Wifi card, so allow Ethernet to be disabled
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 11
-#undef CONFIG_RESET_PHY_R
+#ifdef CONFIG_RESET_PHY_R
+#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
+#endif
#endif /* CONFIG_CMD_NET */
-/*
- * File system
- */
-
#endif /* _CONFIG_ICONNECT_H */
"fdt_addr=0x43000000\0" \
"fdt_addr_r=0x43000000\0" \
"boot_fit=no\0" \
- "dfu_alt_info=mmc 2=flash-bin raw 0x42 0x250 mmcpart 1;" \
- "u-boot-itb raw 0x300 0x1B00 mmcpart 1\0" \
+ "dfu_alt_info=mmc 2=flash-bin raw 0x42 0x1D00 mmcpart 1\0" \
"fdt_file=sb-iotgimx8.dtb\0" \
"fdtfile=sb-iotgimx8.dtb\0" \
"initrd_addr=0x43800000\0" \
"ramdisk_addr_r=0x46400000\0" \
"scriptaddr=0x46000000\0"
-/* Link Definitions */
-
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
MEM_LAYOUT_ENV_SETTINGS \
"script=boot.scr\0" \
"bootm_size=0x10000000\0" \
- "ipaddr=192.168.1.22\0" \
- "serverip=192.168.1.146\0" \
"dev=2\0" \
"preboot=gsc wd-disable\0" \
"console=ttymxc1,115200\0" \
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE 0x30BE0000
#endif
#endif /* CONFIG_SPL_BUILD */
-#define CONFIG_REMAKE_ELF
-
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+#ifndef __IMX8MN_VAR_SOM_H
+#define __IMX8MN_VAR_SOM_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+
+#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define CONFIG_SPL_STACK 0x980000
+#define CONFIG_SPL_BSS_START_ADDR 0x950000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na) \
+
+#include <config_distro_bootcmd.h>
+
+/* ENET */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_XCV_TYPE RGMII
+#endif /* CONFIG_FEC_MXC */
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramdisk_addr_r=0x43800000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fastboot_partition_alias_all=" \
+ __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \
+ "fastboot_partition_alias_bootloader=" \
+ __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \
+ "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \
+ "emmc_ack=1\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ MEM_LAYOUT_ENV_SETTINGS \
+ BOOTENV
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
+
+#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED 400000
+
+#endif /* __IMX8MN_VAR_SOM_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#ifndef __IMX8MM_VENICE_H
+#define __IMX8MM_VENICE_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x980000
+#define CONFIG_SPL_BSS_START_ADDR 0x950000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#endif
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x44000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "scriptaddr=0x46000000\0"
+
+/* Enable Distro Boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef CONFIG_ISO_PARTITION
+#else
+#define BOOTENV
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "bootm_size=0x10000000\0" \
+ "dev=2\0" \
+ "preboot=gsc wd-disable\0" \
+ "console=ttymxc1,115200\0" \
+ "update_firmware=" \
+ "tftpboot $loadaddr $image && " \
+ "setexpr blkcnt $filesize + 0x1ff && " \
+ "setexpr blkcnt $blkcnt / 0x200 && " \
+ "mmc dev $dev && " \
+ "mmc write $loadaddr 0x40 $blkcnt\0" \
+ "boot_net=" \
+ "tftpboot $kernel_addr_r $image && " \
+ "booti $kernel_addr_r - $fdtcontroladdr\0" \
+ "update_rootfs=" \
+ "tftpboot $loadaddr $image && " \
+ "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
+ "update_all=" \
+ "tftpboot $loadaddr $image && " \
+ "gzwrite mmc $dev $loadaddr $filesize\0" \
+ "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+
+/* SDRAM configuration */
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE SZ_1G
+#define CONFIG_SYS_BOOTM_LEN SZ_256M
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+/* FEC */
+#define CONFIG_ETHPRIME "eth0"
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Linaro
+ */
+
+#ifndef __IMX8MP_RSB3720_H
+#define __IMX8MP_RSB3720_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+
+#define CONFIG_SPL_MAX_SIZE (152 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x960000
+#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
+#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+
+#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \
+ * GD_FLG_FULL_MALLOC_INIT \
+ * set \
+ */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DMA
+#define CONFIG_SPL_NAND_MXS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of \
+ * first 64MB boot area \
+ */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full
+ * boot image (not only FIT part) to the mtdpart, so we check both two offsets
+ */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+ (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+
+#endif
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 4
+#define FEC_QUIRK_ENET_MAC
+
+#define DWC_NET_PHYADDR 4
+#ifdef CONFIG_DWC_ETH_QOS
+#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
+#endif
+
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_MMC)
+# define BOOT_TARGET_MMC(func) \
+ func(MMC, mmc, 2) \
+ func(MMC, mmc, 1)
+#else
+# define BOOT_TARGET_MMC(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_PXE)
+# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_MMC(func) \
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func)
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "splashimage=0x50000000\0" \
+ "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "boot_fit=no\0" \
+ "dfu_alt_info=mmc 2=flash-bin raw 0 0x1B00 mmcpart 1\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "initrd_addr=0x43800000\0" \
+ "bootm_size=0x10000000\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=1\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "kernel_addr_r=0x40480000\0" \
+ "pxefile_addr_r=0x40480000\0" \
+ "ramdisk_addr_r=0x43800000\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;\0" \
+ "netargs=setenv bootargs ${jh_clk} console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;\0"
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Totally 6GB or 4G DDR */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
+#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
+#define PHYS_SDRAM_2 0xC0000000
+#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
+#endif
+
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#ifdef CONFIG_FSL_FSPI
+#define FSL_FSPI_FLASH_SIZE SZ_32M
+#define FSL_FSPI_FLASH_NUM 1
+#define FSPI0_BASE_ADDR 0x30bb0000
+#define FSPI0_AMBA_BASE 0x0
+#define CONFIG_FSPI_QUAD_SUPPORT
+
+#define CONFIG_SYS_FSL_FSPI_AHB
+#endif
+
+#ifdef CONFIG_NAND_MXS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#endif /* __IMX8MP_RSB3720_H */
#endif
-#define CONFIG_REMAKE_ELF
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#endif
-#define CONFIG_REMAKE_ELF
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "scriptaddr=0x43500000\0" \
- "kernel_addr_r=0x40880000\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc0,115200\0" \
- "fdt_addr=0x43000000\0" \
+ "fdt_addr_r=0x43000000\0" \
"boot_fdt=try\0" \
- "fdt_file=imx8mq-evk.dtb\0" \
+ "fdtfile=imx8mq-evk.dtb\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
#undef CONFIG_DM_MMC
#endif
-#define CONFIG_REMAKE_ELF
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_REMAKE_ELF
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
/* FUSE command */
/* Boot M4 */
"image=Image\0" \
"panel=NULL\0" \
"console=ttyLP0\0" \
- "fdt_addr=0x83000000\0" \
+ "fdt_addr=0x84000000\0" \
"boot_fdt=try\0" \
"fdt_file=imx8qm-rom7720-a1.dtb\0" \
"initrd_addr=0x83800000\0" \
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#endif
-#define CONFIG_REMAKE_ELF
-
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
#define CONFIG_ETHPRIME "FEC"
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"findfdt=" \
"setenv name_fdt ${default_device_tree};" \
+ "if test $board_name = j721e; then " \
+ "setenv name_fdt k3-j721e-common-proc-board.dtb; fi;" \
+ "if test $board_name = j721e-eaik || test $board_name = j721e-sk; then " \
+ "setenv name_fdt k3-j721e-sk.dtb; fi;" \
"setenv fdtfile ${name_fdt}\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
/* Set the default list of remote processors to boot */
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "dorprocboot=1\0" \
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+ "gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit=" \
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
#endif
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
- "do_main_cpsw0_qsgmii_phyinit=1\0" \
- "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
- "gpio clear gpio@22_16\0" \
- "main_cpsw0_qsgmii_phyinit=" \
- "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
- "test ${boot} = mmc; then " \
- "run init_main_cpsw0_qsgmii_phy;" \
- "fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 J721S2 EVM
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * David Huang <d-huang@ti.com>
+ */
+
+#ifndef __CONFIG_J721S2_EVM_H
+#define __CONFIG_J721S2_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+#include <environment/ti/k3_rproc.h>
+#include <environment/ti/ufs.h>
+#include <environment/ti/k3_dfu.h>
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+
+/* SPL Loader Configuration */
+#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#define CONFIG_SYS_UBOOT_BASE 0x50280000
+/* Image load address in RAM for DFU boot*/
+#else
+#define CONFIG_SYS_UBOOT_BASE 0x50080000
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE 0xA000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR (0x41c80000 -\
+ CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
+/* Image load address in RAM for DFU boot*/
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
+#endif
+
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_CQSPI_REF_CLK 133333333
+
+/* HyperFlash related configuration */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_J721S2_BOARD_SETTINGS \
+ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "findfdt=" \
+ "setenv name_fdt ${default_device_tree};" \
+ "setenv fdtfile ${name_fdt}\0" \
+ "name_kern=Image\0" \
+ "console=ttyS2,115200n8\0" \
+ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000 " \
+ "${mtdparts}\0" \
+ "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+
+#define PARTS_DEFAULT \
+ /* Linux partitions */ \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#if defined(CONFIG_TARGET_J721S2_R5_EVM)
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
+ "addr_mcur5f0_0load=0x89000000\0" \
+ "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"
+#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
+ "addr_mcur5f0_0load=0x89000000\0" \
+ "name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0"
+#endif /* CONFIG_TARGET_J721S2_R5_EVM */
+#else
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC ""
+#endif /* CONFIG_SYS_K3_SPL_ATF */
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \
+ "boot=mmc\0" \
+ "mmcdev=1\0" \
+ "bootpart=1:2\0" \
+ "bootdir=/boot\0" \
+ EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
+ "rd_spec=-\0" \
+ "init_mmc=run args_all args_mmc\0" \
+ "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
+ "get_overlay_mmc=" \
+ "fdt address ${fdtaddr};" \
+ "fdt resize 0x100000;" \
+ "for overlay in $name_overlays;" \
+ "do;" \
+ "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
+ "fdt apply ${dtboaddr};" \
+ "done;\0" \
+ "partitions=" PARTS_DEFAULT \
+ "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
+ "${bootdir}/${name_kern}\0" \
+ "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
+ "${bootdir}/${name_fit}\0" \
+ "partitions=" PARTS_DEFAULT
+
+/* Set the default list of remote processors to boot */
+#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
+#endif
+
+#ifdef CONFIG_TARGET_J721S2_A72_EVM
+#define DEFAULT_RPROCS "" \
+ "2 /lib/firmware/j721s2-main-r5f0_0-fw " \
+ "3 /lib/firmware/j721s2-main-r5f0_1-fw " \
+ "4 /lib/firmware/j721s2-main-r5f1_0-fw " \
+ "5 /lib/firmware/j721s2-main-r5f1_1-fw " \
+ "6 /lib/firmware/j721s2-c71_0-fw " \
+ "7 /lib/firmware/j721s2-c71_1-fw "
+#endif /* CONFIG_TARGET_J721S2_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+ "gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit=" \
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
+#define DEFAULT_RPROCS "" \
+ "2 /lib/firmware/j7200-main-r5f0_0-fw " \
+ "3 /lib/firmware/j7200-main-r5f0_1-fw "
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
+
+#ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
+#endif
+
+/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
+#define EXTRA_ENV_DFUARGS \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_EMMC \
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_OSPI
+
+#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#else
+#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD
+#endif
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
+ EXTRA_ENV_J721S2_BOARD_SETTINGS \
+ EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \
+ EXTRA_ENV_RPROC_SETTINGS \
+ EXTRA_ENV_DFUARGS \
+ DEFAULT_UFS_TI_ARGS \
+ EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \
+ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+/* MMC ENV related defines */
+
+#endif /* __CONFIG_J721S2_EVM_H */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
+#define CONFIG_MISC_INIT_F
+
#endif
#define FEC_QUIRK_ENET_MAC
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_addr_r=0x42000000\0" \
- "fdt_addr_r=0x44000000\0" \
- "ramdisk_addr_r=0x46400000\0" \
- "pxefile_addr_r=0x46000000\0" \
- "scriptaddr=0x46000000\0" \
+ "fdt_addr_r=0x48000000\0" \
+ "fdtoverlay_addr_r=0x49000000\0" \
+ "ramdisk_addr_r=0x48080000\0" \
+ "scriptaddr=0x40000000\0"\
+ "pxefile_addr_r=0x40100000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
"dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \
"bootdelay=3\0" \
"hostname=" CONFIG_HOSTNAME "\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif /* __KONTRON_MX8MM_CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __KONTRON_PITX_IMX8M_H
+#define __KONTRON_PITX_IMX8M_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+
+#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR 0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x182000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+/* ENET1 Config */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE 0x30BE0000
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "kernel_addr_r=0x40880000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "scriptaddr=0x43500000\0" \
+ "initrd_addr=0x43800000\0" \
+ "pxefile_addr_r=0x43500000\0" \
+ "bootm_size=0x10000000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, na) \
+ func(PXE, pxe, 0)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "image=Image\0" \
+ "console=ttymxc2,115200\0" \
+ "boot_fdt=try\0" \
+ "fdtfile=freescale/imx8mq-kontron-pitx-imx8m.dtb\0" \
+ "dfu_alt_info=mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1\0"\
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
+
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
+
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#endif
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_SYS_IDE_MAXBUS
-#undef CONFIG_SYS_IDE_MAXDEVICE
/*
* Enable platform initialisation via misc_init_r() function
#define CONFIG_LBA48
#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#else
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#endif
#endif /* CONFIG_SATA */
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/* I2C */
/* GPIO */
*/
/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
#endif
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
PCI_DEVICE_ID_FREESCALE_AHCI}
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/* SPI */
/*
#ifndef __L1028A_COMMON_H
#define __L1028A_COMMON_H
-#define CONFIG_REMAKE_ELF
-
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
#endif
/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#ifndef SPL_NO_ENV
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#endif
/* SATA */
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#define SCSI_VEND_ID 0x1b4b
#define SCSI_DEV_ID 0x9170
#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
/* Initial environment variables */
#define SPL_NO_IFC
#endif
-#define CONFIG_REMAKE_ELF
-
#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>
#endif
/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/*
* IFC Definitions
*/
/* SATA */
#ifndef SPL_NO_SATA
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 2
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#define SCSI_VEND_ID 0x1b4b
#define SCSI_DEV_ID 0x9170
#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
#define SPL_NO_IFC
#endif
-#define CONFIG_REMAKE_ELF
-
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
/* SATA */
#ifndef SPL_NO_SATA
-#define CONFIG_SCSI_AHCI_PLAT
-
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#endif
/* FMan ucode */
#undef CONFIG_DISPLAY_CPUINFO
#endif
-#define CONFIG_REMAKE_ELF
-
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
/* SATA */
#ifdef CONFIG_SCSI
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#endif
/* Physical Memory Map */
#ifndef __LS2_COMMON_H
#define __LS2_COMMON_H
-#define CONFIG_REMAKE_ELF
-
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#endif
/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
#endif
/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#endif /* CONFIG_CMD_NET */
#ifdef CONFIG_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_LBA48
#endif
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
-#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_MEMAC
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* SATA */
#ifdef CONFIG_SCSI
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#endif
/* USB */
"run distro_bootcmd;run sd2_bootcmd;" \
"env exists secureboot && esbc_halt;"
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_SCSI
+#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
+#else
+#define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
- func(USB, usb, 0) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(SCSI, scsi, 0) \
- func(DHCP, dhcp, na)
+ BOOT_TARGET_DEVICES_USB(func) \
+ BOOT_TARGET_DEVICES_MMC(func, 0) \
+ BOOT_TARGET_DEVICES_MMC(func, 1) \
+ BOOT_TARGET_DEVICES_SCSI(func) \
+ BOOT_TARGET_DEVICES_DHCP(func)
#include <config_distro_bootcmd.h>
#endif /* __LX2_COMMON_H */
* SATA
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_LBA48
/*
* IDE/ATA
*/
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
/*
* Commands
#define STDIN_CFG "serial"
#endif
-#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_CBSIZE 1024
/* Microblaze is microblaze_0 */
#define XILINX_FSL_NUMBER 3
-/* MicroBlaze CPU */
-#define MICROBLAZE_V5 1
-
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
/* uart */
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/*
* PCI configuration
*/
#define CONFIG_BOARD_SIZE_LIMIT 785408
#ifdef CONFIG_CMD_SATA
- #define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_LBA48
/* SATA Configuration */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
+#ifdef CONFIG_SPL
+#include "imx7ulp_spl.h"
+#endif
+
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_SYS_BOOTM_LEN 0x1000000
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_ARMV7_SECURE_BASE 0x2F000000
+
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif /* __CONFIG_H */
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6362.h>
-#define CONFIG_REMAKE_ELF
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_FB_16BPP_WORD_SWAP
-/* functions for cfb_console */
-#define VIDEO_KBD_INIT_FCT rx51_kp_init()
-#define VIDEO_TSTC_FCT rx51_kp_tstc
-#define VIDEO_GETC_FCT rx51_kp_getc
-#ifndef __ASSEMBLY__
-struct stdio_dev;
-int rx51_kp_init(void);
-int rx51_kp_tstc(struct stdio_dev *sdev);
-int rx51_kp_getc(struct stdio_dev *sdev);
-#endif
-
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
- "stdin=usbtty,serial,vga\0" \
+ "stdin=usbtty,serial,keyboard\0" \
"stdout=usbtty,serial,vga\0" \
"stderr=usbtty,serial,vga\0" \
"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
/* SATA driver configuration */
#ifdef CONFIG_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#endif /* CONFIG_SATA */
#define CONSOLEDEV "ttyS2"
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
#endif /* __CONFIG_OMAP5_EVM_H */
/*
* SATA Driver configuration
*/
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_OPENRD_BASE_H */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
#define CONFIG_HWCONFIG
#undef CONFIG_DM_MMC
#endif
-#define CONFIG_REMAKE_ELF
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#include "mv-common.h"
/*
- * Environment variables configurations
- */
-
-/*
* Default environment variables
*/
/*
* Ethernet Driver configuration
*/
-#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
-/*
- * File system
- */
+#ifdef CONFIG_RESET_PHY_R
+#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
+#endif
#endif /* _CONFIG_POGO_E02_H */
#endif
/*
- * SATA Driver configuration
- */
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-
-/*
* Support large disk for SATA and USB
*/
#define CONFIG_SYS_64BIT_LBA
#ifndef __PRESIDIO_ASIC_H
#define __PRESIDIO_ASIC_H
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
#define CONFIG_SYS_BOOTM_LEN 0x00c00000
* - Only legacy IDE controller is supported for QEMU '-M pc' target
* - AHCI controller is supported for QEMU '-M q35' target
*/
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_ATAPI
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
- * IDE support
- */
-#define CONFIG_IDE_RESET 1
-#define CONFIG_SYS_PIO_MODE 1
-#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
-#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
-
-/*
* SuperH PCI Bridge Configration
*/
#define CONFIG_SH7751_PCI
#include <asm/arch/rmobile.h>
-#define CONFIG_REMAKE_ELF
-
#ifdef CONFIG_SPL
#define CONFIG_SPL_TARGET "spl/u-boot-spl.scif"
#endif
#define CONFIG_SANDBOX_SDL
#endif
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_ATA_BASE_ADDR 0x100
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 1
-#define CONFIG_SYS_ATA_ALT_OFFSET 2
-#define CONFIG_SYS_ATA_STRIDE 4
-#endif
-
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_DEVICE 2
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
-#define CONFIG_SYS_SCSI_MAX_LUN 4
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-
#endif
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6358.h>
-#define CONFIG_REMAKE_ELF
* SATA driver configuration
*/
#ifdef CONFIG_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
#endif /* CONFIG_SATA */
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-
/* Environment options */
#ifndef CONFIG_SPL_BUILD
* U-Boot general configurations
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_REMAKE_ELF
/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
#define CPU_RELEASE_ADDR 0xFFD12210
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for new Allwinner F-series (suniv) CPU
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
/* Serial & console */
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
+#ifdef CONFIG_MACH_SUNIV
+/* suniv doesn't have apb2 and uart is connected to apb1 */
+#define CONFIG_SYS_NS16550_CLK 100000000
+#else
#define CONFIG_SYS_NS16550_CLK 24000000
+#endif
#ifndef CONFIG_DM_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE -4
# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
+#elif defined(CONFIG_MACH_SUNIV)
+#define SDRAM_OFFSET(x) 0x8##x
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
+ * since it needs to fit in with the other values. By also #defining it
+ * we get warnings if the Kconfig value mismatches.
+ */
+#define CONFIG_SPL_STACK_R_ADDR 0x81e00000
+#define CONFIG_SPL_BSS_START_ADDR 0x81f80000
#else
#define SDRAM_OFFSET(x) 0x4##x
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#endif
/* mmc config */
-#ifdef CONFIG_MMC
#define CONFIG_MMC_SUNXI_SLOT 0
-#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
-
-#ifdef CONFIG_ARM64
/*
* This is actually (CONFIG_ENV_OFFSET -
* (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used
#endif
#define CONFIG_SYS_MMC_MAX_DEVICE 4
-#endif
/*
* Miscellaneous configurable options
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
-#define CONFIG_SPL_BOARD_LOAD_IMAGE
-
/*
* We cannot use expressions here, because expressions won't be evaluated in
* autoconf.mk.
#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000))
+#elif defined(CONFIG_MACH_SUN8I_V3S)
+/*
+ * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
+ * 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
+ */
+#define BOOTM_SIZE __stringify(0x2e00000)
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
+#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000))
+
+#elif defined(CONFIG_MACH_SUNIV)
+/*
+ * 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc.
+ * 8M uncompressed kernel, 4M compressed kernel, 512K fdt,
+ * 512K script, 512K pxe and the ramdisk at the end.
+ */
+#define BOOTM_SIZE __stringify(0x1700000)
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0500000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(0C00000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(0C50000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(0D00000))
+#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(0D50000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000))
+
#else
/*
* 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
*/
-#ifndef CONFIG_MACH_SUN8I_V3S
#define BOOTM_SIZE __stringify(0xa000000)
#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000))
-#else
-/*
- * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
- * 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
- * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
- */
-#define BOOTM_SIZE __stringify(0x2e00000)
-#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
-#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
-#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
-#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
-#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
-#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000))
-#endif
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
/* SATA */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ * Copyright 2019-2021 Traverse Technologies
+ */
+
+#ifndef __TEN64_H
+#define __TEN64_H
+
+#include "ls1088a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
+#define SD_BOOTCOMMAND "run distro_bootcmd"
+
+#define QSPI_MC_INIT_CMD \
+ "sf probe 0:0 && sf read 0x80000000 0x300000 0x200000 &&" \
+ "sf read 0x80200000 0x5C0000 0x40000 &&" \
+ "fsl_mc start mc 0x80000000 0x80200000 && " \
+ "sf read 0x80300000 0x580000 0x40000 && fsl_mc lazyapply DPL 0x80300000\0"
+#define SD_MC_INIT_CMD \
+ "mmcinfo; fatload mmc 0 0x80000000 mcfirmware/mc_ls1088a.itb; "\
+ "fatload mmc 0 0x80200000 dpaa2config/dpc.0x1D-0x0D.dtb; "\
+ "fsl_mc start mc 0x80000000 0x80200000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(NVME, nvme, 0) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0) \
+ func(DHCP, dhcp, 0) \
+ func(PXE, pxe, 0)
+#include <config_distro_bootcmd.h>
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "BOARD=ten64\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "load_addr=0xa0000000\0" \
+ BOOTENV \
+ "load_efi_dtb=mtd read devicetree $fdt_addr_r && fdt addr $fdt_addr_r && " \
+ "fdt resize && fdt boardsetup\0" \
+ "bootcmd_recovery=mtd read recovery 0xa0000000; mtd read dpl 0x80100000 && " \
+ "fsl_mc apply DPL 0x80100000 && bootm 0xa0000000#ten64\0"
+
+#endif /* __TEN64_H */
"initrd_high=0x10000000\0"
/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
/* Enable LCD and reserve 512KB from top of memory*/
#ifndef __THUNDERX_88XX_H__
#define __THUNDERX_88XX_H__
-#define CONFIG_REMAKE_ELF
-
#define CONFIG_THUNDERX
#define CONFIG_SYS_64BIT
#ifndef __TOTAL_COMPUTE_H
#define __TOTAL_COMPUTE_H
-#define CONFIG_REMAKE_ELF
-
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2022 Toradex
+ */
+
+#ifndef __VERDIN_IMX8MP_H
+#define __VERDIN_IMX8MP_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SPL_MAX_SIZE (152 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x960000
+#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x184000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_POWER_PCA9450
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_REMAKE_ELF
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ETHPRIME "eth0" /* eqos is aliased on-module Ethernet interface */
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 7
+#define FEC_QUIRK_ENET_MAC
+
+#define PHY_ANEG_TIMEOUT 20000
+#endif /* CONFIG_CMD_NET */
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x43000000\0" \
+ "kernel_addr_r=0x40000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "scriptaddr=0x46000000\0"
+
+/* Enable Distro Boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef CONFIG_ISO_PARTITION
+#else
+#define BOOTENV
+#endif
+
+#if defined(CONFIG_TDX_EASY_INSTALLER)
+# define BOOT_SCRIPT "boot-tezi.scr"
+#else
+# define BOOT_SCRIPT "boot.scr"
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "bootcmd_mfg=fastboot 0\0" \
+ "boot_file=Image\0" \
+ "boot_scripts=" BOOT_SCRIPT "\0" \
+ "boot_script_dhcp=" BOOT_SCRIPT "\0" \
+ "console=ttymxc2\0" \
+ "fdt_board=dev\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
+ "\0" \
+ "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \
+ "tftp ${fdt_addr} verdin/${fdtfile}; " \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "setup=setenv setupargs console=${console},${baudrate} console=tty1 " \
+ "consoleblank=0 earlycon\0" \
+ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
+ "if test \"$confirm\" = \"y\"; then " \
+ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+ "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \
+ "${blkcnt}; fi\0"
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
+
+/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G)
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#endif /* __VERDIN_IMX8MP_H */
#include <linux/stringify.h>
-#define CONFIG_REMAKE_ELF
-
/* Link Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#ifndef __XILINX_VERSAL_H
#define __XILINX_VERSAL_H
-#define CONFIG_REMAKE_ELF
-
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */
#ifndef __XILINX_ZYNQMP_H
#define __XILINX_ZYNQMP_H
-#define CONFIG_REMAKE_ELF
-
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */
#ifndef __CONFIG_ZYNQ_COMMON_H
#define __CONFIG_ZYNQ_COMMON_H
-#define CONFIG_REMAKE_ELF
-
/* Cache options */
#ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310
int dfu_write_from_mem_addr(struct dfu_entity *dfu, void *buf, int size);
/* Device specific */
+/* Each entity has 5 arguments in maximum. */
+#define DFU_MAX_ENTITY_ARGS 5
+
#if CONFIG_IS_ENABLED(DFU_MMC)
-extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s);
+extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc);
#else
static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr,
- char *s)
+ char **argv, int argc)
{
puts("MMC support not available!\n");
return -1;
#endif
#if CONFIG_IS_ENABLED(DFU_NAND)
-extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s);
+extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc);
#else
static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr,
- char *s)
+ char **argv, int argc)
{
puts("NAND support not available!\n");
return -1;
#endif
#if CONFIG_IS_ENABLED(DFU_RAM)
-extern int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s);
+extern int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc);
#else
static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr,
- char *s)
+ char **argv, int argc)
{
puts("RAM support not available!\n");
return -1;
#endif
#if CONFIG_IS_ENABLED(DFU_SF)
-extern int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s);
+extern int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc);
#else
static inline int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr,
- char *s)
+ char **argv, int argc)
{
puts("SF support not available!\n");
return -1;
#endif
#if CONFIG_IS_ENABLED(DFU_MTD)
-int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s);
+extern int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc);
#else
static inline int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr,
- char *s)
+ char **argv, int argc)
{
puts("MTD support not available!\n");
return -1;
#endif
#ifdef CONFIG_DFU_VIRT
-int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, char *s);
+int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr,
+ char **argv, int argc);
int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
void *buf, long *len);
int dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size);
void *buf, long *len);
#else
static inline int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr,
- char *s)
+ char **argv, int argc)
{
puts("VIRT support not available!\n");
return -1;
#define DM_MAX_SEQ_STR 3
/* Returns the operations for a device */
-#define device_get_ops(dev) (dev->driver->ops)
+#define device_get_ops(dev) ((dev)->driver->ops)
#if CONFIG_IS_ENABLED(OF_PLATDATA_RT)
u32 dev_get_flags(const struct udevice *dev);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Constant for device tree bindings for Turris Mox module configuration bus
+ *
+ * Copyright (C) 2019 Marek Behún <kabel@kernel.org>
+ */
+
+#ifndef _DT_BINDINGS_BUS_MOXTET_H
+#define _DT_BINDINGS_BUS_MOXTET_H
+
+#define MOXTET_IRQ_PCI 0
+#define MOXTET_IRQ_USB3 4
+#define MOXTET_IRQ_PERIDOT(n) (8 + (n))
+#define MOXTET_IRQ_TOPAZ 12
+
+#endif /* _DT_BINDINGS_BUS_MOXTET_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ *
+ * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+
+#define CLK_CPU 11
+
+#define CLK_BUS_DMA 14
+#define CLK_BUS_MMC0 15
+#define CLK_BUS_MMC1 16
+#define CLK_BUS_DRAM 17
+#define CLK_BUS_SPI0 18
+#define CLK_BUS_SPI1 19
+#define CLK_BUS_OTG 20
+#define CLK_BUS_VE 21
+#define CLK_BUS_LCD 22
+#define CLK_BUS_DEINTERLACE 23
+#define CLK_BUS_CSI 24
+#define CLK_BUS_TVD 25
+#define CLK_BUS_TVE 26
+#define CLK_BUS_DE_BE 27
+#define CLK_BUS_DE_FE 28
+#define CLK_BUS_CODEC 29
+#define CLK_BUS_SPDIF 30
+#define CLK_BUS_IR 31
+#define CLK_BUS_RSB 32
+#define CLK_BUS_I2S0 33
+#define CLK_BUS_I2C0 34
+#define CLK_BUS_I2C1 35
+#define CLK_BUS_I2C2 36
+#define CLK_BUS_PIO 37
+#define CLK_BUS_UART0 38
+#define CLK_BUS_UART1 39
+#define CLK_BUS_UART2 40
+
+#define CLK_MMC0 41
+#define CLK_MMC0_SAMPLE 42
+#define CLK_MMC0_OUTPUT 43
+#define CLK_MMC1 44
+#define CLK_MMC1_SAMPLE 45
+#define CLK_MMC1_OUTPUT 46
+#define CLK_I2S 47
+#define CLK_SPDIF 48
+
+#define CLK_USB_PHY0 49
+
+#define CLK_DRAM_VE 50
+#define CLK_DRAM_CSI 51
+#define CLK_DRAM_DEINTERLACE 52
+#define CLK_DRAM_TVD 53
+#define CLK_DRAM_DE_FE 54
+#define CLK_DRAM_DE_BE 55
+
+#define CLK_DE_BE 56
+#define CLK_DE_FE 57
+#define CLK_TCON 58
+#define CLK_DEINTERLACE 59
+#define CLK_TVE2_CLK 60
+#define CLK_TVE1_CLK 61
+#define CLK_TVD 62
+#define CLK_CSI 63
+#define CLK_VE 64
+#define CLK_CODEC 65
+#define CLK_AVS 66
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Interconnect framework driver for i.MX SoC
+ *
+ * Copyright (c) 2019-2020, NXP
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
+#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
+
+#define IMX8MQ_ICN_NOC 1
+#define IMX8MQ_ICS_DRAM 2
+#define IMX8MQ_ICS_OCRAM 3
+#define IMX8MQ_ICM_A53 4
+
+#define IMX8MQ_ICM_VPU 5
+#define IMX8MQ_ICN_VIDEO 6
+
+#define IMX8MQ_ICM_GPU 7
+#define IMX8MQ_ICN_GPU 8
+
+#define IMX8MQ_ICM_DCSS 9
+#define IMX8MQ_ICN_DCSS 10
+
+#define IMX8MQ_ICM_USB1 11
+#define IMX8MQ_ICM_USB2 12
+#define IMX8MQ_ICN_USB 13
+
+#define IMX8MQ_ICM_CSI1 14
+#define IMX8MQ_ICM_CSI2 15
+#define IMX8MQ_ICM_LCDIF 16
+#define IMX8MQ_ICN_DISPLAY 17
+
+#define IMX8MQ_ICM_SDMA2 18
+#define IMX8MQ_ICN_AUDIO 19
+
+#define IMX8MQ_ICN_ENET 20
+#define IMX8MQ_ICM_ENET 21
+
+#define IMX8MQ_ICM_SDMA1 22
+#define IMX8MQ_ICM_NAND 23
+#define IMX8MQ_ICM_USDHC1 24
+#define IMX8MQ_ICM_USDHC2 25
+#define IMX8MQ_ICM_PCIE1 26
+#define IMX8MQ_ICM_PCIE2 27
+#define IMX8MQ_ICN_MAIN 28
+
+#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */
#define AM64_SERDES0_LANE0_PCIE0 0x0
#define AM64_SERDES0_LANE0_USB 0x1
+/* J721S2 */
+
+#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0
+#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0
+#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J721S2_SERDES0_LANE1_USB 0x2
+#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
+#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
+#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J721S2_SERDES0_LANE3_USB 0x2
+#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
+
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
#define CDNS_SIERRA_PLL_CMNLC 0
#define CDNS_SIERRA_PLL_CMNLC1 1
+#define SIERRA_SERDES_NO_SSC 0
+#define SIERRA_SERDES_EXTERNAL_SSC 1
+#define SIERRA_SERDES_INTERNAL_SSC 2
+
#endif /* _DT_BINDINGS_CADENCE_SERDES_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * This header provides constants for i.MX8 PCIe.
+ */
+
+#ifndef _DT_BINDINGS_IMX8_PCIE_H
+#define _DT_BINDINGS_IMX8_PCIE_H
+
+/* Reference clock PAD mode */
+#define IMX8_PCIE_REFCLK_PAD_UNUSED 0
+#define IMX8_PCIE_REFCLK_PAD_INPUT 1
+#define IMX8_PCIE_REFCLK_PAD_OUTPUT 2
+
+#endif /* _DT_BINDINGS_IMX8_PCIE_H */
#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ *
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ */
+
+#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+
+#define RST_USB_PHY0 0
+#define RST_BUS_DMA 1
+#define RST_BUS_MMC0 2
+#define RST_BUS_MMC1 3
+#define RST_BUS_DRAM 4
+#define RST_BUS_SPI0 5
+#define RST_BUS_SPI1 6
+#define RST_BUS_OTG 7
+#define RST_BUS_VE 8
+#define RST_BUS_LCD 9
+#define RST_BUS_DEINTERLACE 10
+#define RST_BUS_CSI 11
+#define RST_BUS_TVD 12
+#define RST_BUS_TVE 13
+#define RST_BUS_DE_BE 14
+#define RST_BUS_DE_FE 15
+#define RST_BUS_CODEC 16
+#define RST_BUS_SPDIF 17
+#define RST_BUS_IR 18
+#define RST_BUS_RSB 19
+#define RST_BUS_I2S0 20
+#define RST_BUS_I2C0 21
+#define RST_BUS_I2C1 22
+#define RST_BUS_I2C2 23
+#define RST_BUS_UART0 24
+#define RST_BUS_UART1 25
+#define RST_BUS_UART2 26
+
+#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */
efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path,
struct efi_device_path **device_path,
struct efi_device_path **file_path);
+struct efi_device_path *efi_dp_from_uart(void);
efi_status_t efi_dp_from_name(const char *dev, const char *devnr,
const char *path,
struct efi_device_path **device,
efi_uintn_t capsule_size,
void **image, efi_uintn_t *image_size);
-#define EFI_CAPSULE_DIR L"\\EFI\\UpdateCapsule\\"
+#define EFI_CAPSULE_DIR u"\\EFI\\UpdateCapsule\\"
/**
* Install the ESRT system table.
#define EFI_ST_SUCCESS 0
#define EFI_ST_FAILURE 1
-#define EFI_ST_SUCCESS_STR L"SUCCESS"
+#define EFI_ST_SUCCESS_STR u"SUCCESS"
/**
* efi_st_printf() - print a message
* efi_st_translate_code() - translate a scan code to a human readable string
*
* This function translates the scan code returned by the simple text input
- * protocol to a human readable string, e.g. 0x04 is translated to L"Left".
+ * protocol to a human readable string, e.g. 0x04 is translated to u"Left".
*
* @code: scan code
* Return: Unicode string
*/
int fdtdec_board_setup(const void *fdt_blob);
-#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
/**
* fdtdec_resetup() - Set up the device tree again
*
* Return: 0 if OK, -ve on error
*/
int fdtdec_resetup(int *rescan);
-#endif
/**
* Board-specific FDT initialization. Returns the address to a device tree blob.
int ide_device_present(int dev);
#endif
-#if defined(CONFIG_IDE_AHB)
-unsigned char ide_read_register(int dev, unsigned int port);
-void ide_write_register(int dev, unsigned int port, unsigned char val);
-void ide_read_data(int dev, ulong *sect_buf, int words);
-void ide_write_data(int dev, const ulong *sect_buf, int words);
-#endif
-
/*
* I/O function overrides
*/
extern const struct ti_k3_clk_platdata j721e_clk_platdata;
extern const struct ti_k3_clk_platdata j7200_clk_platdata;
+extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
void __iomem *reg);
extern const struct ti_k3_pd_platdata j721e_pd_platdata;
extern const struct ti_k3_pd_platdata j7200_pd_platdata;
+extern const struct ti_k3_pd_platdata j721s2_pd_platdata;
u8 ti_pd_state(struct ti_pd *pd);
u8 lpsc_get_state(struct ti_lpsc *lpsc);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Apple mailbox message format
+ *
+ * Copyright (C) 2021 The Asahi Linux Contributors
+ */
+
+#ifndef _LINUX_APPLE_MAILBOX_H_
+#define _LINUX_APPLE_MAILBOX_H_
+
+#include <linux/types.h>
+
+/* encodes a single 96bit message sent over the single channel */
+struct apple_mbox_msg {
+ u64 msg0;
+ u32 msg1;
+};
+
+#endif
(bit) < (size); \
(bit) = find_next_bit((addr), (size), (bit) + 1))
+static inline unsigned long
+bitmap_find_next_zero_area(unsigned long *map,
+ unsigned long size,
+ unsigned long start,
+ unsigned int nr, unsigned long align_mask)
+{
+ unsigned long index, end, i;
+again:
+ index = find_next_zero_bit(map, size, start);
+
+ /*
+ * Align allocation
+ */
+ index = (index + align_mask) & ~align_mask;
+
+ end = index + nr;
+ if (end > size)
+ return end;
+ i = find_next_bit(map, end, index);
+ if (i < end) {
+ start = i + 1;
+ goto again;
+ }
+ return index;
+}
+
static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
{
if (small_const_nbits(nbits)) {
* the last step cherry picks the 2nd arg, we get a zero.
*/
#define __ARG_PLACEHOLDER_1 0,
-#define config_enabled(cfg) _config_enabled(cfg)
-#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value)
-#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0)
+#define config_enabled(cfg, def_val) _config_enabled(cfg, def_val)
+#define _config_enabled(value, def_val) __config_enabled(__ARG_PLACEHOLDER_##value, def_val)
+#define __config_enabled(arg1_or_junk, def_val) ___config_enabled(arg1_or_junk 1, def_val)
#define ___config_enabled(__ignored, val, ...) val
/*
* IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y',
* 0 otherwise.
- *
*/
-#define IS_ENABLED(option) \
- (config_enabled(option))
+#define IS_ENABLED(option) config_enabled(option, 0)
/*
* U-Boot add-on: Helper macros to reference to different macros (prefixed by
#define CONFIG_VAL(option) config_val(option)
/*
+ * This uses a similar mechanism to config_enabled() above. If cfg is enabled,
+ * it resolves to the value of opt_cfg, otherwise it resolves to def_val
+ */
+#define config_opt_enabled(cfg, opt_cfg, def_val) _config_opt_enabled(cfg, opt_cfg, def_val)
+#define _config_opt_enabled(cfg_val, opt_value, def_val) \
+ __config_opt_enabled(__ARG_PLACEHOLDER_##cfg_val, opt_value, def_val)
+#define __config_opt_enabled(arg1_or_junk, arg2, def_val) \
+ ___config_opt_enabled(arg1_or_junk arg2, def_val)
+#define ___config_opt_enabled(__ignored, val, ...) val
+
+#ifndef __ASSEMBLY__
+/*
+ * Detect usage of a the value when the conditional is not enabled. When used
+ * in assembly context, this likely produces a assembly error, or hopefully at
+ * least something recognisable.
+ */
+long invalid_use_of_IF_ENABLED_INT(void);
+#endif
+
+/* Evaluates to int_option if option is defined, otherwise a build error */
+#define IF_ENABLED_INT(option, int_option) \
+ config_opt_enabled(option, int_option, invalid_use_of_IF_ENABLED_INT())
+
+/*
* Count number of arguments to a variadic macro. Currently only need
* it for 1, 2 or 3 arguments.
*/
#define __CONFIG_IS_ENABLED_1(option) __CONFIG_IS_ENABLED_3(option, (1), (0))
#define __CONFIG_IS_ENABLED_2(option, case1) __CONFIG_IS_ENABLED_3(option, case1, ())
#define __CONFIG_IS_ENABLED_3(option, case1, case0) \
- __concat(__unwrap, config_enabled(CONFIG_VAL(option))) (case1, case0)
+ __concat(__unwrap, config_enabled(CONFIG_VAL(option), 0)) (case1, case0)
/*
* CONFIG_IS_ENABLED(FOO) expands to
#define CONFIG_IS_ENABLED(option, ...) \
__concat(__CONFIG_IS_ENABLED_, __count_args(option, ##__VA_ARGS__)) (option, ##__VA_ARGS__)
+#ifndef __ASSEMBLY__
+/*
+ * Detect usage of a the value when the conditional is not enabled. When used
+ * in assembly context, this likely produces a assembly error, or hopefully at
+ * least something recognisable.
+ */
+long invalid_use_of_CONFIG_IF_ENABLED_INT(void);
+#endif
+
+/*
+ * Evaluates to SPL_/TPL_int_option if SPL_/TPL_/option is not defined,
+ * otherwise build error
+ */
+#define CONFIG_IF_ENABLED_INT(option, int_option) \
+ CONFIG_IS_ENABLED(option, (CONFIG_VAL(int_option)), \
+ (invalid_use_of_CONFIG_IF_ENABLED_INT()))
#endif /* __LINUX_KCONFIG_H */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
+#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
+#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
+#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
+#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
+#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */
+/* Advanced Error Reporting */
+#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
+#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
+#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
+#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
+#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
+#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
+
/* Single Root I/O Virtualization Registers */
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
* initrd - path to the initrd to use for this label.
* attempted - 0 if we haven't tried to boot this label, 1 if we have.
* localboot - 1 if this label specified 'localboot', 0 otherwise.
+ * kaslrseed - 1 if generate kaslrseed from hw_rng
* list - lets these form a list, which a pxe_menu struct will hold.
*/
struct pxe_label {
int attempted;
int localboot;
int localboot_val;
+ int kaslrseed;
struct list_head list;
};
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015
* Texas Instruments Incorporated - http://www.ti.com/
#include <dm/platdata.h> /* For platform data support - non dt world */
/**
+ * struct fw_rsc_hdr - firmware resource entry header
+ * @type: resource type
+ * @data: resource data
+ *
+ * Every resource entry begins with a 'struct fw_rsc_hdr' header providing
+ * its @type. The content of the entry itself will immediately follow
+ * this header, and it should be parsed according to the resource type.
+ */
+struct fw_rsc_hdr {
+ u32 type;
+ u8 data[0];
+};
+
+/**
+ * enum fw_resource_type - types of resource entries
+ *
+ * @RSC_CARVEOUT: request for allocation of a physically contiguous
+ * memory region.
+ * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
+ * @RSC_TRACE: announces the availability of a trace buffer into which
+ * the remote processor will be writing logs.
+ * @RSC_VDEV: declare support for a virtio device, and serve as its
+ * virtio header.
+ * @RSC_PRELOAD_VENDOR: a vendor resource type that needs to be handled by
+ * remoteproc implementations before loading
+ * @RSC_POSTLOAD_VENDOR: a vendor resource type that needs to be handled by
+ * remoteproc implementations after loading
+ * @RSC_LAST: just keep this one at the end
+ *
+ * For more details regarding a specific resource type, please see its
+ * dedicated structure below.
+ *
+ * Please note that these values are used as indices to the rproc_handle_rsc
+ * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to
+ * check the validity of an index before the lookup table is accessed, so
+ * please update it as needed.
+ */
+enum fw_resource_type {
+ RSC_CARVEOUT = 0,
+ RSC_DEVMEM = 1,
+ RSC_TRACE = 2,
+ RSC_VDEV = 3,
+ RSC_PRELOAD_VENDOR = 4,
+ RSC_POSTLOAD_VENDOR = 5,
+ RSC_LAST = 6,
+};
+
+#define FW_RSC_ADDR_ANY (-1)
+
+/**
+ * struct fw_rsc_carveout - physically contiguous memory request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested memory region
+ *
+ * This resource entry requests the host to allocate a physically contiguous
+ * memory region.
+ *
+ * These request entries should precede other firmware resource entries,
+ * as other entries might request placing other data objects inside
+ * these memory regions (e.g. data/code segments, trace resource entries, ...).
+ *
+ * Allocating memory this way helps utilizing the reserved physical memory
+ * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries
+ * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
+ * pressure is important; it may have a substantial impact on performance.
+ *
+ * If the firmware is compiled with static addresses, then @da should specify
+ * the expected device address of this memory region. If @da is set to
+ * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then
+ * overwrite @da with the dynamically allocated address.
+ *
+ * We will always use @da to negotiate the device addresses, even if it
+ * isn't using an iommu. In that case, though, it will obviously contain
+ * physical addresses.
+ *
+ * Some remote processors needs to know the allocated physical address
+ * even if they do use an iommu. This is needed, e.g., if they control
+ * hardware accelerators which access the physical memory directly (this
+ * is the case with OMAP4 for instance). In that case, the host will
+ * overwrite @pa with the dynamically allocated physical address.
+ * Generally we don't want to expose physical addresses if we don't have to
+ * (remote processors are generally _not_ trusted), so we might want to
+ * change this to happen _only_ when explicitly required by the hardware.
+ *
+ * @flags is used to provide IOMMU protection flags, and @name should
+ * (optionally) contain a human readable name of this carveout region
+ * (mainly for debugging purposes).
+ */
+struct fw_rsc_carveout {
+ u32 da;
+ u32 pa;
+ u32 len;
+ u32 flags;
+ u32 reserved;
+ u8 name[32];
+};
+
+/**
+ * struct fw_rsc_devmem - iommu mapping request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested region to be mapped
+ *
+ * This resource entry requests the host to iommu map a physically contiguous
+ * memory region. This is needed in case the remote processor requires
+ * access to certain memory-based peripherals; _never_ use it to access
+ * regular memory.
+ *
+ * This is obviously only needed if the remote processor is accessing memory
+ * via an iommu.
+ *
+ * @da should specify the required device address, @pa should specify
+ * the physical address we want to map, @len should specify the size of
+ * the mapping and @flags is the IOMMU protection flags. As always, @name may
+ * (optionally) contain a human readable name of this mapping (mainly for
+ * debugging purposes).
+ *
+ * Note: at this point we just "trust" those devmem entries to contain valid
+ * physical addresses, but this isn't safe and will be changed: eventually we
+ * want remoteproc implementations to provide us ranges of physical addresses
+ * the firmware is allowed to request, and not allow firmwares to request
+ * access to physical addresses that are outside those ranges.
+ */
+struct fw_rsc_devmem {
+ u32 da;
+ u32 pa;
+ u32 len;
+ u32 flags;
+ u32 reserved;
+ u8 name[32];
+};
+
+/**
+ * struct fw_rsc_trace - trace buffer declaration
+ * @da: device address
+ * @len: length (in bytes)
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the trace buffer
+ *
+ * This resource entry provides the host information about a trace buffer
+ * into which the remote processor will write log messages.
+ *
+ * @da specifies the device address of the buffer, @len specifies
+ * its size, and @name may contain a human readable name of the trace buffer.
+ *
+ * After booting the remote processor, the trace buffers are exposed to the
+ * user via debugfs entries (called trace0, trace1, etc..).
+ */
+struct fw_rsc_trace {
+ u32 da;
+ u32 len;
+ u32 reserved;
+ u8 name[32];
+};
+
+/**
+ * struct fw_rsc_vdev_vring - vring descriptor entry
+ * @da: device address
+ * @align: the alignment between the consumer and producer parts of the vring
+ * @num: num of buffers supported by this vring (must be power of two)
+ * @notifyid is a unique rproc-wide notify index for this vring. This notify
+ * index is used when kicking a remote processor, to let it know that this
+ * vring is triggered.
+ * @pa: physical address
+ *
+ * This descriptor is not a resource entry by itself; it is part of the
+ * vdev resource type (see below).
+ *
+ * Note that @da should either contain the device address where
+ * the remote processor is expecting the vring, or indicate that
+ * dynamically allocation of the vring's device address is supported.
+ */
+struct fw_rsc_vdev_vring {
+ u32 da;
+ u32 align;
+ u32 num;
+ u32 notifyid;
+ u32 pa;
+};
+
+/**
+ * struct fw_rsc_vdev - virtio device header
+ * @id: virtio device id (as in virtio_ids.h)
+ * @notifyid is a unique rproc-wide notify index for this vdev. This notify
+ * index is used when kicking a remote processor, to let it know that the
+ * status/features of this vdev have changes.
+ * @dfeatures specifies the virtio device features supported by the firmware
+ * @gfeatures is a place holder used by the host to write back the
+ * negotiated features that are supported by both sides.
+ * @config_len is the size of the virtio config space of this vdev. The config
+ * space lies in the resource table immediate after this vdev header.
+ * @status is a place holder where the host will indicate its virtio progress.
+ * @num_of_vrings indicates how many vrings are described in this vdev header
+ * @reserved: reserved (must be zero)
+ * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'.
+ *
+ * This resource is a virtio device header: it provides information about
+ * the vdev, and is then used by the host and its peer remote processors
+ * to negotiate and share certain virtio properties.
+ *
+ * By providing this resource entry, the firmware essentially asks remoteproc
+ * to statically allocate a vdev upon registration of the rproc (dynamic vdev
+ * allocation is not yet supported).
+ *
+ * Note: unlike virtualization systems, the term 'host' here means
+ * the Linux side which is running remoteproc to control the remote
+ * processors. We use the name 'gfeatures' to comply with virtio's terms,
+ * though there isn't really any virtualized guest OS here: it's the host
+ * which is responsible for negotiating the final features.
+ * Yeah, it's a bit confusing.
+ *
+ * Note: immediately following this structure is the virtio config space for
+ * this vdev (which is specific to the vdev; for more info, read the virtio
+ * spec). the size of the config space is specified by @config_len.
+ */
+struct fw_rsc_vdev {
+ u32 id;
+ u32 notifyid;
+ u32 dfeatures;
+ u32 gfeatures;
+ u32 config_len;
+ u8 status;
+ u8 num_of_vrings;
+ u8 reserved[2];
+ struct fw_rsc_vdev_vring vring[0];
+};
+
+/**
+ * struct rproc_mem_entry - memory entry descriptor
+ * @va: virtual address
+ * @dma: dma address
+ * @len: length, in bytes
+ * @da: device address
+ * @priv: associated data
+ * @name: associated memory region name (optional)
+ * @node: list node
+ */
+struct rproc_mem_entry {
+ void *va;
+ dma_addr_t dma;
+ int len;
+ u32 da;
+ void *priv;
+ char name[32];
+ struct list_head node;
+};
+
+struct rproc;
+
+typedef u32(*init_func_proto) (u32 core_id, struct rproc *cfg);
+
+struct l3_map {
+ u32 priv_addr;
+ u32 l3_addr;
+ u32 len;
+};
+
+struct rproc_intmem_to_l3_mapping {
+ u32 num_entries;
+ struct l3_map mappings[16];
+};
+
+/**
+ * enum rproc_crash_type - remote processor crash types
+ * @RPROC_MMUFAULT: iommu fault
+ * @RPROC_WATCHDOG: watchdog bite
+ * @RPROC_FATAL_ERROR fatal error
+ *
+ * Each element of the enum is used as an array index. So that, the value of
+ * the elements should be always something sane.
+ *
+ * Feel free to add more types when needed.
+ */
+enum rproc_crash_type {
+ RPROC_MMUFAULT,
+ RPROC_WATCHDOG,
+ RPROC_FATAL_ERROR,
+};
+
+/* we currently support only two vrings per rvdev */
+#define RVDEV_NUM_VRINGS 2
+
+#define RPMSG_NUM_BUFS (512)
+#define RPMSG_BUF_SIZE (512)
+#define RPMSG_TOTAL_BUF_SPACE (RPMSG_NUM_BUFS * RPMSG_BUF_SIZE)
+
+/**
+ * struct rproc_vring - remoteproc vring state
+ * @va: virtual address
+ * @dma: dma address
+ * @len: length, in bytes
+ * @da: device address
+ * @align: vring alignment
+ * @notifyid: rproc-specific unique vring index
+ * @rvdev: remote vdev
+ * @vq: the virtqueue of this vring
+ */
+struct rproc_vring {
+ void *va;
+ dma_addr_t dma;
+ int len;
+ u32 da;
+ u32 align;
+ int notifyid;
+ struct rproc_vdev *rvdev;
+ struct virtqueue *vq;
+};
+
+/** struct rproc - structure with all processor specific information for
+ * loading remotecore from boot loader.
+ *
+ * @num_iommus: Number of IOMMUs for this remote core. Zero indicates that the
+ * processor does not have an IOMMU.
+ *
+ * @cma_base: Base address of the carveout for this remotecore.
+ *
+ * @cma_size: Length of the carveout in bytes.
+ *
+ * @page_table_addr: array with the physical address of the page table. We are
+ * using the same page table for both IOMMU's. There is currently no strong
+ * usecase for maintaining different page tables for different MMU's servicing
+ * the same CPU.
+ *
+ * @mmu_base_addr: base address of the MMU
+ *
+ * @entry_point: address that is the entry point for the remote core. This
+ * address is in the memory view of the remotecore.
+ *
+ * @load_addr: Address to which the bootloader loads the firmware from
+ * persistent storage before invoking the ELF loader. Keeping this address
+ * configurable allows future optimizations such as loading the firmware from
+ * storage for remotecore2 via EDMA while the CPU is processing the ELF image
+ * of remotecore1. This address is in the memory view of the A15.
+ *
+ * @firmware_name: Name of the file that is expected to contain the ELF image.
+ *
+ * @has_rsc_table: Flag populated after parsing the ELF binary on target.
+ */
+
+struct rproc {
+ u32 num_iommus;
+ unsigned long cma_base;
+ u32 cma_size;
+ unsigned long page_table_addr;
+ unsigned long mmu_base_addr[2];
+ unsigned long load_addr;
+ unsigned long entry_point;
+ char *core_name;
+ char *firmware_name;
+ char *ptn;
+ init_func_proto start_clocks;
+ init_func_proto config_mmu;
+ init_func_proto config_peripherals;
+ init_func_proto start_core;
+ u32 has_rsc_table;
+ struct rproc_intmem_to_l3_mapping *intmem_to_l3_mapping;
+ u32 trace_pa;
+ u32 trace_len;
+};
+
+extern struct rproc *rproc_cfg_arr[2];
+/**
* enum rproc_mem_type - What type of memory model does the rproc use
* @RPROC_INTERNAL_MEMORY_MAPPED: Remote processor uses own memory and is memory
* mapped to the host processor over an address range.
* @return virtual address.
*/
void * (*device_to_virt)(struct udevice *dev, ulong da, ulong size);
+ int (*add_res)(struct udevice *dev,
+ struct rproc_mem_entry *mapping);
+ void * (*alloc_mem)(struct udevice *dev, unsigned long len,
+ unsigned long align);
+ unsigned int (*config_pagetable)(struct udevice *dev, unsigned int virt,
+ unsigned int phys, unsigned int len);
};
/* Accessor */
*/
int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr,
ulong fw_size, ulong *rsc_addr, ulong *rsc_size);
+
+unsigned long rproc_parse_resource_table(struct udevice *dev,
+ struct rproc *cfg);
+
+struct resource_table *rproc_find_resource_table(struct udevice *dev,
+ unsigned int addr,
+ int *tablesz);
#else
static inline int rproc_init(void) { return -ENOSYS; }
static inline int rproc_dev_init(int id) { return -ENOSYS; }
#include <asm/cache.h>
#include <linux/dma-direction.h>
+/* Fix this to the maximum */
+#define SCSI_MAX_DEVICE \
+ (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+
struct udevice;
struct scsi_cmd {
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Michael Walle <michael@walle.cc>
+ */
+
+#ifndef __SL28CPLD_H
+#define __SL28CPLD_H
+
+#define SL28CPLD_VERSION 0x03
+
+int sl28cpld_read(struct udevice *dev, uint offset);
+int sl28cpld_write(struct udevice *dev, uint offset, uint8_t value);
+int sl28cpld_update(struct udevice *dev, uint offset, uint8_t clear,
+ uint8_t set);
+
+#endif
*/
binman_sym_extern(ulong, u_boot_any, image_pos);
binman_sym_extern(ulong, u_boot_any, size);
-binman_sym_extern(ulong, spl, image_pos);
-binman_sym_extern(ulong, spl, size);
+binman_sym_extern(ulong, u_boot_spl, image_pos);
+binman_sym_extern(ulong, u_boot_spl, size);
/**
* spl_get_image_pos() - get the image position of the next phase
*/
enum usb_init_type {
USB_INIT_HOST,
- USB_INIT_DEVICE
+ USB_INIT_DEVICE,
+ USB_INIT_UNKNOWN,
};
/**********************************************************************
IOCTL_AIE_ISR_CLEAR = 24,
};
-#define PM_SIP_SVC 0xc2000000
+#define PM_SIP_SVC 0xc2000000
-#define ZYNQMP_PM_VERSION_MAJOR 1
-#define ZYNQMP_PM_VERSION_MINOR 0
-#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
-#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
+#define ZYNQMP_PM_VERSION_MAJOR 1
+#define ZYNQMP_PM_VERSION_MINOR 0
+#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
+#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
#define ZYNQMP_PM_VERSION \
((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
ZYNQMP_PM_VERSION_MINOR)
-#define ZYNQMP_PM_VERSION_INVALID ~0
+#define ZYNQMP_PM_VERSION_INVALID ~0
-#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
+#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
/*
* Return payload size
#define PAYLOAD_ARG_CNT 5U
unsigned int zynqmp_firmware_version(void);
+int zynqmp_pmufw_node(u32 id);
+int zynqmp_pmufw_config_close(void);
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
+/* Type of Config Object */
+#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
+#define PM_CONFIG_OBJECT_TYPE_OVERLAY 0x2U
+
+/* Section Id */
+#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
+#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
+
+/* Flag Option */
+#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
+#define PM_MASTER_USING_SLAVE_MASK 0x2U
+
+/* IPI Mask for Master */
+#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
+#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
+#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
+
+enum zynqmp_pm_request_ack {
+ ZYNQMP_PM_REQUEST_ACK_NO = 1,
+ ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
+ ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
+};
+
+/* Node capabilities */
+#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
+#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
+#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
+#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
+
+#define ZYNQMP_PM_MAX_QOS 100U
+
#endif /* _ZYNQMP_FIRMWARE_H_ */
ifndef CONFIG_QEMU
obj-y += base.o
obj-y += csrt.o
+obj-y += mcfg.o
# Sandbox does not build a .asl file
ifndef CONFIG_SANDBOX
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Write an ACPI MCFG table
+ *
+ * Copyright 2022 Google LLC
+ */
+
+#define LOG_CATEGORY LOGC_ACPI
+
+#include <common.h>
+#include <mapmem.h>
+#include <tables_csum.h>
+#include <acpi/acpi_table.h>
+#include <dm/acpi.h>
+
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end)
+{
+ memset(mmconfig, 0, sizeof(*mmconfig));
+ mmconfig->base_address_l = base;
+ mmconfig->base_address_h = 0;
+ mmconfig->pci_segment_group_number = seg_nr;
+ mmconfig->start_bus_number = start;
+ mmconfig->end_bus_number = end;
+
+ return sizeof(struct acpi_mcfg_mmconfig);
+}
+
+__weak int acpi_fill_mcfg(struct acpi_ctx *ctx)
+{
+ return -ENOENT;
+}
+
+/* MCFG is defined in the PCI Firmware Specification 3.0 */
+int acpi_write_mcfg(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_mcfg *mcfg;
+ int ret;
+
+ mcfg = ctx->current;
+ header = &mcfg->header;
+
+ memset(mcfg, '\0', sizeof(struct acpi_mcfg));
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "MCFG");
+ header->length = sizeof(struct acpi_mcfg);
+ header->revision = 1;
+ acpi_inc(ctx, sizeof(*mcfg));
+
+ ret = acpi_fill_mcfg(ctx);
+ if (ret)
+ return log_msg_ret("fill", ret);
+
+ /* (Re)calculate length and checksum */
+ header->length = (ulong)ctx->current - (ulong)mcfg;
+ header->checksum = table_compute_checksum(mcfg, header->length);
+
+ acpi_add_table(ctx, mcfg);
+
+ return 0;
+}
+ACPI_WRITER(5mcfg, "MCFG", acpi_write_mcfg, 0);
void **load_options)
{
struct efi_load_option lo;
- u16 varname[] = L"Boot0000";
- u16 hexmap[] = L"0123456789ABCDEF";
+ u16 varname[] = u"Boot0000";
+ u16 hexmap[] = u"0123456789ABCDEF";
void *load_option;
efi_uintn_t size;
efi_status_t ret;
attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS;
- ret = efi_set_variable_int(L"BootCurrent",
+ ret = efi_set_variable_int(u"BootCurrent",
&efi_global_variable_guid,
attributes, sizeof(n), &n, false);
if (ret != EFI_SUCCESS)
/* BootNext */
size = sizeof(bootnext);
- ret = efi_get_variable_int(L"BootNext",
+ ret = efi_get_variable_int(u"BootNext",
&efi_global_variable_guid,
NULL, &size, &bootnext, NULL);
if (ret == EFI_SUCCESS || ret == EFI_BUFFER_TOO_SMALL) {
log_err("BootNext must be 16-bit integer\n");
/* delete BootNext */
- ret = efi_set_variable_int(L"BootNext",
+ ret = efi_set_variable_int(u"BootNext",
&efi_global_variable_guid,
0, 0, NULL, false);
}
/* BootOrder */
- bootorder = efi_get_var(L"BootOrder", &efi_global_variable_guid, &size);
+ bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid, &size);
if (!bootorder) {
log_info("BootOrder not defined\n");
ret = EFI_NOT_FOUND;
{
efi_status_t r;
- EFI_ENTRY("%d, %zd, %p", pool_type, size, buffer);
+ EFI_ENTRY("%d, %zu, %p", pool_type, size, buffer);
r = efi_allocate_pool(pool_type, size, buffer);
return EFI_EXIT(r);
}
{
int i;
- EFI_ENTRY("%zd, %p, %p", num_events, event, index);
+ EFI_ENTRY("%zu, %p, %p", num_events, event, index);
/* Check parameters */
if (!num_events || !event)
efi_status_t ret;
void *dest_buffer;
- EFI_ENTRY("%d, %p, %pD, %p, %zd, %p", boot_policy, parent_image,
+ EFI_ENTRY("%d, %p, %pD, %p, %zu, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
if (!image_handle || (!source_buffer && !file_path) ||
.create_event_ex = efi_create_event_ex,
};
-static u16 __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
+static u16 __efi_runtime_data firmware_vendor[] = u"Das U-Boot";
struct efi_system_table __efi_runtime_data systab = {
.hdr = {
#include <env.h>
#include <fdtdec.h>
#include <fs.h>
+#include <hang.h>
#include <malloc.h>
#include <mapmem.h>
#include <sort.h>
int i;
size = sizeof(value16);
- ret = efi_get_variable_int(L"CapsuleLast", &efi_guid_capsule_report,
+ ret = efi_get_variable_int(u"CapsuleLast", &efi_guid_capsule_report,
NULL, &size, value16, NULL);
if (ret != EFI_SUCCESS || size != 22 ||
- u16_strncmp(value16, L"Capsule", 7))
+ u16_strncmp(value16, u"Capsule", 7))
goto err;
for (i = 0; i < 4; ++i) {
u16 c = value16[i + 7];
}
/* Variable CapsuleLast must not include terminating 0x0000 */
- ret = efi_set_variable_int(L"CapsuleLast", &efi_guid_capsule_report,
+ ret = efi_set_variable_int(u"CapsuleLast", &efi_guid_capsule_report,
EFI_VARIABLE_READ_ONLY |
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
22, variable_name16, false);
if (ret != EFI_SUCCESS)
- log_err("Setting %ls failed\n", L"CapsuleLast");
+ log_err("Setting %ls failed\n", u"CapsuleLast");
}
#ifdef CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT
/* find active boot device in BootNext */
bootnext = 0;
size = sizeof(bootnext);
- ret = efi_get_variable_int(L"BootNext",
+ ret = efi_get_variable_int(u"BootNext",
(efi_guid_t *)&efi_global_variable_guid,
NULL, &size, &bootnext, NULL);
if (ret == EFI_SUCCESS || ret == EFI_BUFFER_TOO_SMALL) {
skip:
/* find active boot device in BootOrder */
size = 0;
- ret = efi_get_variable_int(L"BootOrder", &efi_global_variable_guid,
+ ret = efi_get_variable_int(u"BootOrder", &efi_global_variable_guid,
NULL, &size, NULL, NULL);
if (ret == EFI_BUFFER_TOO_SMALL) {
boot_order = malloc(size);
goto out;
}
- ret = efi_get_variable_int(L"BootOrder",
+ ret = efi_get_variable_int(u"BootOrder",
&efi_global_variable_guid,
NULL, &size, boot_order, NULL);
}
break;
if (!(dirent->attribute & EFI_FILE_DIRECTORY) &&
- u16_strcmp(dirent->file_name, L".") &&
- u16_strcmp(dirent->file_name, L".."))
+ u16_strcmp(dirent->file_name, u".") &&
+ u16_strcmp(dirent->file_name, u".."))
tmp_files[count++] = u16_strdup(dirent->file_name);
}
/* ignore an error */
efi_status_t r;
size = sizeof(os_indications);
- r = efi_get_variable_int(L"OsIndications", &efi_global_variable_guid,
+ r = efi_get_variable_int(u"OsIndications", &efi_global_variable_guid,
NULL, &size, &os_indications, NULL);
if (r != EFI_SUCCESS || size != sizeof(os_indications))
return EFI_NOT_FOUND;
EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED) {
os_indications &=
~EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED;
- r = efi_set_variable_int(L"OsIndications",
+ r = efi_set_variable_int(u"OsIndications",
&efi_global_variable_guid,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
index = 0;
ret = efi_capsule_read_file(files[i], &capsule);
if (ret == EFI_SUCCESS) {
- ret = EFI_CALL(efi_update_capsule(&capsule, 1, 0));
+ ret = efi_capsule_update_firmware(capsule);
if (ret != EFI_SUCCESS)
- log_err("Applying capsule %ls failed\n",
+ log_err("Applying capsule %ls failed.\n",
files[i]);
+ else
+ log_info("Applying capsule %ls succeeded.\n",
+ files[i]);
/* create CapsuleXXXX */
set_capsule_result(index, capsule, ret);
free(files[i]);
free(files);
- return ret;
+ /*
+ * UEFI spec requires to reset system after complete processing capsule
+ * update on the storage.
+ */
+ log_info("Reboot after firmware update");
+ /* Cold reset is required for loading the new firmware. */
+ do_reset(NULL, 0, 0, NULL);
+ hang();
+ /* not reach here */
+
+ return 0;
}
#endif /* CONFIG_EFI_CAPSULE_ON_DISK */
int present;
};
+__maybe_unused static struct efi_object uart_obj;
+
static struct cout_mode efi_cout_modes[] = {
/* EFI Mode 0 is 80x25 and always present */
{
efi_status_t efi_console_register(void)
{
efi_status_t r;
- efi_handle_t console_output_handle;
- efi_handle_t console_input_handle;
+ struct efi_device_path *dp;
/* Set up mode information */
query_console_size();
- /* Create handles */
- r = efi_create_handle(&console_output_handle);
- if (r != EFI_SUCCESS)
- goto out_of_memory;
-
- r = efi_add_protocol(console_output_handle,
- &efi_guid_text_output_protocol, &efi_con_out);
- if (r != EFI_SUCCESS)
- goto out_of_memory;
- systab.con_out_handle = console_output_handle;
- systab.stderr_handle = console_output_handle;
-
- r = efi_create_handle(&console_input_handle);
- if (r != EFI_SUCCESS)
- goto out_of_memory;
-
- r = efi_add_protocol(console_input_handle,
- &efi_guid_text_input_protocol, &efi_con_in);
- if (r != EFI_SUCCESS)
- goto out_of_memory;
- systab.con_in_handle = console_input_handle;
- r = efi_add_protocol(console_input_handle,
- &efi_guid_text_input_ex_protocol, &efi_con_in_ex);
- if (r != EFI_SUCCESS)
- goto out_of_memory;
+ /* Install protocols on root node */
+ r = EFI_CALL(efi_install_multiple_protocol_interfaces
+ (&efi_root,
+ &efi_guid_text_output_protocol, &efi_con_out,
+ &efi_guid_text_input_protocol, &efi_con_in,
+ &efi_guid_text_input_ex_protocol, &efi_con_in_ex,
+ NULL));
+
+ /* Create console node and install device path protocols */
+ if (CONFIG_IS_ENABLED(DM_SERIAL)) {
+ dp = efi_dp_from_uart();
+ if (!dp)
+ goto out_of_memory;
+
+ /* Hook UART up to the device list */
+ efi_add_handle(&uart_obj);
+
+ /* Install device path */
+ r = efi_add_protocol(&uart_obj, &efi_guid_device_path, dp);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ }
/* Create console events */
r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK, efi_key_notify,
if (!dev || !dev->driver)
return sizeof(ROOT);
- switch (dev->driver->id) {
+ switch (device_get_uclass_id(dev)) {
case UCLASS_ROOT:
case UCLASS_SIMPLE_BUS:
/* stop traversing parents at this point: */
if (!dev || !dev->driver)
return buf;
- switch (dev->driver->id) {
+ switch (device_get_uclass_id(dev)) {
case UCLASS_ROOT:
case UCLASS_SIMPLE_BUS: {
/* stop traversing parents at this point: */
return &udp[1];
}
default:
- debug("%s(%u) %s: unhandled device class: %s (%u)\n",
- __FILE__, __LINE__, __func__,
- dev->name, dev->driver->id);
+ /* If the uclass driver is missing, this will show NULL */
+ log_debug("unhandled device class: %s (%s)\n", dev->name,
+ dev_get_uclass_name(dev));
return dp_fill(buf, dev->parent);
}
}
static unsigned dp_part_size(struct blk_desc *desc, int part)
{
unsigned dpsize;
- struct udevice *dev;
- int ret;
+ struct udevice *dev = desc->bdev;
- ret = blk_find_device(desc->if_type, desc->devnum, &dev);
-
- if (ret)
- dev = desc->bdev->parent;
dpsize = dp_size(dev);
if (part == 0) /* the actual disk, not a partition */
*/
static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
{
- struct udevice *dev;
- int ret;
-
- ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+ struct udevice *dev = desc->bdev;
- if (ret)
- dev = desc->bdev->parent;
buf = dp_fill(buf, dev);
if (part == 0) /* the actual disk, not a partition */
#include <common.h>
#include <blk.h>
#include <efi_loader.h>
+#include <malloc.h>
#define MAC_OUTPUT_LEN 22
#define UNKNOWN_OUTPUT_LEN 23
case DEVICE_PATH_SUB_TYPE_MSG_UART: {
struct efi_device_path_uart *uart =
(struct efi_device_path_uart *)dp;
- s += sprintf(s, "Uart(%lld,%d,%d,", uart->baud_rate,
- uart->data_bits, uart->parity);
- switch (uart->stop_bits) {
- case 2:
- s += sprintf(s, "1.5)");
- break;
- default:
+ const char parity_str[6] = {'D', 'N', 'E', 'O', 'M', 'S'};
+ const char *stop_bits_str[4] = { "D", "1", "1.5", "2" };
+
+ s += sprintf(s, "Uart(%lld,%d,", uart->baud_rate,
+ uart->data_bits);
+
+ /*
+ * Parity and stop bits can either both use keywords or both use
+ * numbers but numbers and keywords should not be mixed. Let's
+ * go for keywords as this is what EDK II does. For illegal
+ * values fall back to numbers.
+ */
+ if (uart->parity < 6)
+ s += sprintf(s, "%c,", parity_str[uart->parity]);
+ else
+ s += sprintf(s, "%d,", uart->parity);
+ if (uart->stop_bits < 4)
+ s += sprintf(s, "%s)", stop_bits_str[uart->stop_bits]);
+ else
s += sprintf(s, "%d)", uart->stop_bits);
- break;
- }
break;
}
case DEVICE_PATH_SUB_TYPE_MSG_USB: {
case DEVICE_PATH_SUB_TYPE_FILE_PATH: {
struct efi_device_path_file_path *fp =
(struct efi_device_path_file_path *)dp;
- int slen = (dp->length - sizeof(*dp)) / 2;
- if (slen > MAX_NODE_LEN - 2)
- slen = MAX_NODE_LEN - 2;
- s += sprintf(s, "%-.*ls", slen, fp->str);
+ u16 *buffer;
+ int slen = dp->length - sizeof(*dp);
+
+ /* two bytes for \0, extra byte if dp->length is odd */
+ buffer = calloc(1, slen + 3);
+ if (!buffer) {
+ log_err("Out of memory\n");
+ return s;
+ }
+ memcpy(buffer, fp->str, dp->length - sizeof(*dp));
+ s += snprintf(s, MAX_NODE_LEN - 1, "%ls", buffer);
+ free(buffer);
break;
}
default:
efi_status_t (*progress)(efi_uintn_t completion),
u16 **abort_reason)
{
- EFI_ENTRY("%p %d %p %zd %p %p %p\n", this, image_index, image,
+ EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
if (!image || image_index != 1)
efi_status_t status;
efi_uintn_t capsule_payload_size;
- EFI_ENTRY("%p %d %p %zd %p %p %p\n", this, image_index, image,
+ EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
if (!image)
u16 *pos;
boot_current_size = sizeof(boot_current);
- ret = efi_get_variable_int(L"BootCurrent",
+ ret = efi_get_variable_int(u"BootCurrent",
&efi_global_variable_guid, NULL,
&boot_current_size, &boot_current, NULL);
if (ret != EFI_SUCCESS)
#ifdef CONFIG_EFI_SECURE_BOOT
/**
- * efi_image_unsigned_authenticate() - authenticate unsigned image with
- * SHA256 hash
- * @regs: List of regions to be verified
- *
- * If an image is not signed, it doesn't have a signature. In this case,
- * its message digest is calculated and it will be compared with one of
- * hash values stored in signature databases.
- *
- * Return: true if authenticated, false if not
- */
-static bool efi_image_unsigned_authenticate(struct efi_image_regions *regs)
-{
- struct efi_signature_store *db = NULL, *dbx = NULL;
- bool ret = false;
-
- dbx = efi_sigstore_parse_sigdb(L"dbx");
- if (!dbx) {
- EFI_PRINT("Getting signature database(dbx) failed\n");
- goto out;
- }
-
- db = efi_sigstore_parse_sigdb(L"db");
- if (!db) {
- EFI_PRINT("Getting signature database(db) failed\n");
- goto out;
- }
-
- /* try black-list first */
- if (efi_signature_lookup_digest(regs, dbx, true)) {
- EFI_PRINT("Image is not signed and its digest found in \"dbx\"\n");
- goto out;
- }
-
- /* try white-list */
- if (efi_signature_lookup_digest(regs, db, false))
- ret = true;
- else
- EFI_PRINT("Image is not signed and its digest not found in \"db\" or \"dbx\"\n");
-
-out:
- efi_sigstore_free(db);
- efi_sigstore_free(dbx);
-
- return ret;
-}
-
-/**
* efi_image_authenticate() - verify a signature of signed image
* @efi: Pointer to image
* @efi_size: Size of @efi
if (!efi_image_parse(new_efi, efi_size, ®s, &wincerts,
&wincerts_len)) {
EFI_PRINT("Parsing PE executable image failed\n");
- goto err;
- }
-
- if (!wincerts) {
- /* The image is not signed */
- ret = efi_image_unsigned_authenticate(regs);
-
- goto err;
+ goto out;
}
/*
* verify signature using db and dbx
*/
- db = efi_sigstore_parse_sigdb(L"db");
+ db = efi_sigstore_parse_sigdb(u"db");
if (!db) {
EFI_PRINT("Getting signature database(db) failed\n");
- goto err;
+ goto out;
}
- dbx = efi_sigstore_parse_sigdb(L"dbx");
+ dbx = efi_sigstore_parse_sigdb(u"dbx");
if (!dbx) {
EFI_PRINT("Getting signature database(dbx) failed\n");
- goto err;
+ goto out;
}
if (efi_signature_lookup_digest(regs, dbx, true)) {
EFI_PRINT("Image's digest was found in \"dbx\"\n");
- goto err;
+ goto out;
}
/*
if (guidcmp(auth, &efi_guid_cert_type_pkcs7)) {
EFI_PRINT("Certificate type not supported: %pUs\n",
auth);
- continue;
+ ret = false;
+ goto out;
}
auth += sizeof(efi_guid_t);
} else if (wincert->wCertificateType
!= WIN_CERT_TYPE_PKCS_SIGNED_DATA) {
EFI_PRINT("Certificate type not supported\n");
- continue;
+ ret = false;
+ goto out;
}
msg = pkcs7_parse_message(auth, auth_size);
*/
/* try black-list first */
if (efi_signature_verify_one(regs, msg, dbx)) {
+ ret = false;
EFI_PRINT("Signature was rejected by \"dbx\"\n");
- continue;
+ goto out;
}
if (!efi_signature_check_signers(msg, dbx)) {
+ ret = false;
EFI_PRINT("Signer(s) in \"dbx\"\n");
- continue;
+ goto out;
}
/* try white-list */
if (efi_signature_verify(regs, msg, db, dbx)) {
ret = true;
- break;
+ continue;
}
EFI_PRINT("Signature was not verified by \"db\"\n");
+ }
- if (efi_signature_lookup_digest(regs, db, false)) {
- ret = true;
- break;
- }
- EFI_PRINT("Image's digest was not found in \"db\" or \"dbx\"\n");
- }
+ /* last resort try the image sha256 hash in db */
+ if (!ret && efi_signature_lookup_digest(regs, db, false))
+ ret = true;
-err:
+out:
efi_sigstore_free(db);
efi_sigstore_free(dbx);
pkcs7_free_message(msg);
* Variable PlatformLangCodes defines the language codes that the
* machine can support.
*/
- ret = efi_set_variable_int(L"PlatformLangCodes",
+ ret = efi_set_variable_int(u"PlatformLangCodes",
&efi_global_variable_guid,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS |
* Variable PlatformLang defines the language that the machine has been
* configured for.
*/
- ret = efi_get_variable_int(L"PlatformLang",
+ ret = efi_get_variable_int(u"PlatformLang",
&efi_global_variable_guid,
NULL, &data_size, &pos, NULL);
if (ret == EFI_BUFFER_TOO_SMALL) {
if (pos)
*pos = 0;
- ret = efi_set_variable_int(L"PlatformLang",
+ ret = efi_set_variable_int(u"PlatformLang",
&efi_global_variable_guid,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
};
efi_status_t ret;
- ret = efi_set_variable_int(L"SignatureSupport",
+ ret = efi_set_variable_int(u"SignatureSupport",
&efi_global_variable_guid,
EFI_VARIABLE_READ_ONLY |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
efi_status_t ret = EFI_SUCCESS;
if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_UPDATE)) {
- ret = efi_set_variable_int(L"CapsuleMax",
+ ret = efi_set_variable_int(u"CapsuleMax",
&efi_guid_capsule_report,
EFI_VARIABLE_READ_ONLY |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
- 22, L"CapsuleFFFF", false);
+ 22, u"CapsuleFFFF", false);
if (ret != EFI_SUCCESS)
printf("EFI: cannot initialize CapsuleMax variable\n");
}
os_indications_supported |=
EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED;
- return efi_set_variable_int(L"OsIndicationsSupported",
+ return efi_set_variable_int(u"OsIndicationsSupported",
&efi_global_variable_guid,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS |
goto out;
EFI_PRINT("Verifying last certificate in chain\n");
- if (signer->self_signed) {
- if (efi_lookup_certificate(signer, db))
- if (efi_signature_check_revocation(sinfo,
- signer, dbx))
- break;
- } else if (efi_verify_certificate(signer, db, &root)) {
+ if (efi_lookup_certificate(signer, db))
+ if (efi_signature_check_revocation(sinfo, signer, dbx))
+ break;
+ if (!signer->self_signed &&
+ efi_verify_certificate(signer, db, &root)) {
bool check;
check = efi_signature_check_revocation(sinfo, root,
* @index: Index
*
* Create a utf-16 string with @name, appending @index.
- * For example, L"Capsule0001"
+ * For example, u"Capsule0001"
*
* The caller must ensure that the buffer has enough space for the resulting
* string including the trailing L'\0'.
{
u16 *boot_order;
u16 *boot_index;
- u16 var_name[] = L"BootOrder";
- u16 boot_name[] = L"Boot####";
+ u16 var_name[] = u"BootOrder";
+ u16 boot_name[] = u"Boot####";
u8 *bootvar;
efi_uintn_t var_data_size;
u32 count, i;
efi_secure_boot = secure_boot;
- ret = efi_set_variable_int(L"SecureBoot", &efi_global_variable_guid,
+ ret = efi_set_variable_int(u"SecureBoot", &efi_global_variable_guid,
attributes_ro, sizeof(secure_boot),
&secure_boot, false);
if (ret != EFI_SUCCESS)
goto err;
- ret = efi_set_variable_int(L"SetupMode", &efi_global_variable_guid,
+ ret = efi_set_variable_int(u"SetupMode", &efi_global_variable_guid,
attributes_ro, sizeof(setup_mode),
&setup_mode, false);
if (ret != EFI_SUCCESS)
goto err;
- ret = efi_set_variable_int(L"AuditMode", &efi_global_variable_guid,
+ ret = efi_set_variable_int(u"AuditMode", &efi_global_variable_guid,
audit_mode || setup_mode ?
attributes_ro : attributes_rw,
sizeof(audit_mode), &audit_mode, false);
if (ret != EFI_SUCCESS)
goto err;
- ret = efi_set_variable_int(L"DeployedMode",
+ ret = efi_set_variable_int(u"DeployedMode",
&efi_global_variable_guid,
audit_mode || deployed_mode || setup_mode ?
attributes_ro : attributes_rw,
if (ret != EFI_SUCCESS)
goto err;
} else if (mode == EFI_MODE_AUDIT) {
- ret = efi_set_variable_int(L"PK", &efi_global_variable_guid,
+ ret = efi_set_variable_int(u"PK", &efi_global_variable_guid,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
0, NULL, false);
return ret;
/* As we do not provide vendor keys this variable is always 0. */
- ret = efi_set_variable_int(L"VendorKeys",
+ ret = efi_set_variable_int(u"VendorKeys",
&efi_global_variable_guid,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS |
case EFI_AUTH_VAR_PK:
case EFI_AUTH_VAR_KEK:
/* with PK */
- truststore = efi_sigstore_parse_sigdb(L"PK");
+ truststore = efi_sigstore_parse_sigdb(u"PK");
if (!truststore)
goto err;
break;
case EFI_AUTH_VAR_DB:
case EFI_AUTH_VAR_DBX:
/* with PK and KEK */
- truststore = efi_sigstore_parse_sigdb(L"KEK");
- truststore2 = efi_sigstore_parse_sigdb(L"PK");
+ truststore = efi_sigstore_parse_sigdb(u"KEK");
+ truststore2 = efi_sigstore_parse_sigdb(u"PK");
if (!truststore) {
if (!truststore2)
goto err;
if (alt_ret != EFI_SUCCESS)
goto out;
- if (!u16_strcmp(variable_name, L"PK"))
+ if (!u16_strcmp(variable_name, u"PK"))
alt_ret = efi_init_secure_state();
out:
free(comm_buf);
printf("ERROR: Failed to register watchdog event\n");
return r;
}
- /*
- * The UEFI standard requires that the watchdog timer is set to five
- * minutes when invoking an EFI boot option.
- *
- * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A
- * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer
- */
- r = efi_set_watchdog(300);
- if (r != EFI_SUCCESS) {
- printf("ERROR: Failed to set watchdog timer\n");
- return r;
- }
+
return EFI_SUCCESS;
}
*/
static void print_uefi_revision(void)
{
- u16 rev[] = L"0.0.0";
+ u16 rev[] = u"0.0.0";
rev[0] = (systable->hdr.revision >> 16) + '0';
rev[4] = systable->hdr.revision & 0xffff;
else
rev[3] = 0;
- con_out->output_string(con_out, L"Running on UEFI ");
+ con_out->output_string(con_out, u"Running on UEFI ");
con_out->output_string(con_out, rev);
- con_out->output_string(con_out, L"\r\n");
+ con_out->output_string(con_out, u"\r\n");
}
/**
if (!memcmp(&systable->tables[i].guid, &fdt_guid,
sizeof(efi_guid_t)))
con_out->output_string
- (con_out, L"Have device tree\r\n");
+ (con_out, u"Have device tree\r\n");
if (!memcmp(&systable->tables[i].guid, &acpi_guid,
sizeof(efi_guid_t)))
con_out->output_string
- (con_out, L"Have ACPI 2.0 table\r\n");
+ (con_out, u"Have ACPI 2.0 table\r\n");
if (!memcmp(&systable->tables[i].guid, &smbios_guid,
sizeof(efi_guid_t)))
con_out->output_string
- (con_out, L"Have SMBIOS table\r\n");
+ (con_out, u"Have SMBIOS table\r\n");
}
}
void print_load_options(struct efi_loaded_image *loaded_image)
{
/* Output the load options */
- con_out->output_string(con_out, L"Load options: ");
+ con_out->output_string(con_out, u"Load options: ");
if (loaded_image->load_options_size && loaded_image->load_options)
con_out->output_string(con_out,
(u16 *)loaded_image->load_options);
else
- con_out->output_string(con_out, L"<none>");
- con_out->output_string(con_out, L"\r\n");
+ con_out->output_string(con_out, u"<none>");
+ con_out->output_string(con_out, u"\r\n");
}
/**
efi_status_t ret;
if (!device_path) {
- con_out->output_string(con_out, L"<none>\r\n");
+ con_out->output_string(con_out, u"<none>\r\n");
return EFI_SUCCESS;
}
string = dp2txt->convert_device_path_to_text(device_path, true, false);
if (!string) {
con_out->output_string
- (con_out, L"Cannot convert device path to text\r\n");
+ (con_out, u"Cannot convert device path to text\r\n");
return EFI_OUT_OF_RESOURCES;
}
con_out->output_string(con_out, string);
- con_out->output_string(con_out, L"\r\n");
+ con_out->output_string(con_out, u"\r\n");
ret = boottime->free_pool(string);
if (ret != EFI_SUCCESS) {
- con_out->output_string(con_out, L"Cannot free pool memory\r\n");
+ con_out->output_string(con_out, u"Cannot free pool memory\r\n");
return ret;
}
return EFI_SUCCESS;
con_out = systable->con_out;
/* UEFI requires CR LF */
- con_out->output_string(con_out, L"Hello, world!\r\n");
+ con_out->output_string(con_out, u"Hello, world!\r\n");
print_uefi_revision();
print_config_tables();
(void **)&loaded_image);
if (ret != EFI_SUCCESS) {
con_out->output_string
- (con_out, L"Cannot open loaded image protocol\r\n");
+ (con_out, u"Cannot open loaded image protocol\r\n");
goto out;
}
print_load_options(loaded_image);
NULL, (void **)&device_path_to_text);
if (ret != EFI_SUCCESS) {
con_out->output_string
- (con_out, L"Cannot open device path to text protocol\r\n");
+ (con_out, u"Cannot open device path to text protocol\r\n");
goto out;
}
if (!loaded_image->device_handle) {
con_out->output_string
- (con_out, L"Missing device handle\r\n");
+ (con_out, u"Missing device handle\r\n");
goto out;
}
ret = boottime->handle_protocol(loaded_image->device_handle,
(void **)&device_path);
if (ret != EFI_SUCCESS) {
con_out->output_string
- (con_out, L"Missing device path for device handle\r\n");
+ (con_out, u"Missing device path for device handle\r\n");
goto out;
}
- con_out->output_string(con_out, L"Boot device: ");
+ con_out->output_string(con_out, u"Boot device: ");
ret = print_device_path(device_path, device_path_to_text);
if (ret != EFI_SUCCESS)
goto out;
- con_out->output_string(con_out, L"File path: ");
+ con_out->output_string(con_out, u"File path: ");
ret = print_device_path(loaded_image->file_path, device_path_to_text);
if (ret != EFI_SUCCESS)
goto out;
struct efi_input_key key = {0};
efi_uintn_t index;
efi_uintn_t pos = 0;
- u16 outbuf[2] = L" ";
+ u16 outbuf[2] = u" ";
efi_status_t ret;
/* Drain the console input */
continue;
switch (key.scan_code) {
case 0x17: /* Escape */
- print(L"\r\nAborted\r\n");
+ print(u"\r\nAborted\r\n");
return EFI_ABORTED;
default:
break;
case 0x08: /* Backspace */
if (pos) {
buffer[pos--] = 0;
- print(L"\b \b");
+ print(u"\b \b");
}
break;
case 0x0a: /* Linefeed */
case 0x0d: /* Carriage return */
- print(L"\r\n");
+ print(u"\r\n");
return EFI_SUCCESS;
default:
break;
*/
void do_help(void)
{
- error(L"load <dtb> - load device-tree from file\r\n");
- error(L"save <dtb> - save device-tree to file\r\n");
- error(L"exit - exit the shell\r\n");
+ error(u"load <dtb> - load device-tree from file\r\n");
+ error(u"save <dtb> - save device-tree to file\r\n");
+ error(u"exit - exit the shell\r\n");
}
/**
(void **)&loaded_image, NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL);
if (ret != EFI_SUCCESS) {
- error(L"Loaded image protocol not found\r\n");
+ error(u"Loaded image protocol not found\r\n");
return ret;
}
(void **)file_system, NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL);
if (ret != EFI_SUCCESS)
- error(L"Failed to open simple file system protocol\r\n");
+ error(u"Failed to open simple file system protocol\r\n");
if (handle)
bs->free_pool(handle_buffer);
ret = bs->locate_protocol(&efi_dt_fixup_protocol_guid, NULL,
(void **)&dt_fixup_prot);
if (ret != EFI_SUCCESS) {
- error(L"Device-tree fix-up protocol not found\r\n");
+ error(u"Device-tree fix-up protocol not found\r\n");
return ret;
}
/* Open volume */
ret = file_system->open_volume(file_system, &root);
if (ret != EFI_SUCCESS) {
- error(L"Failed to open volume\r\n");
+ error(u"Failed to open volume\r\n");
goto out;
}
/* Open file */
ret = root->open(root, &file, filename, EFI_FILE_MODE_READ, 0);
if (ret != EFI_SUCCESS) {
- error(L"File not found\r\n");
+ error(u"File not found\r\n");
goto out;
}
/* Get file size */
buffer_size = 0;
ret = file->getinfo(file, &efi_file_info_guid, &buffer_size, NULL);
if (ret != EFI_BUFFER_TOO_SMALL) {
- error(L"Can't get file info size\r\n");
+ error(u"Can't get file info size\r\n");
goto out;
}
ret = bs->allocate_pool(EFI_LOADER_DATA, buffer_size, (void **)&info);
if (ret != EFI_SUCCESS) {
- error(L"Out of memory\r\n");
+ error(u"Out of memory\r\n");
goto out;
}
ret = file->getinfo(file, &efi_file_info_guid, &buffer_size, info);
if (ret != EFI_SUCCESS) {
- error(L"Can't get file info\r\n");
+ error(u"Can't get file info\r\n");
goto out;
}
buffer_size = info->file_size;
pages = efi_size_in_pages(buffer_size);
ret = bs->free_pool(info);
if (ret != EFI_SUCCESS)
- error(L"Can't free memory pool\r\n");
+ error(u"Can't free memory pool\r\n");
/* Read file */
ret = bs->allocate_pages(EFI_ALLOCATE_ANY_PAGES,
EFI_ACPI_RECLAIM_MEMORY,
pages, &addr);
if (ret != EFI_SUCCESS) {
- error(L"Out of memory\r\n");
+ error(u"Out of memory\r\n");
goto out;
}
dtb = (struct fdt_header *)(uintptr_t)addr;
ret = file->read(file, &buffer_size, dtb);
if (ret != EFI_SUCCESS) {
- error(L"Can't read file\r\n");
+ error(u"Can't read file\r\n");
goto out;
}
/* Fixup file, expecting EFI_BUFFER_TOO_SMALL */
/* Read file into larger buffer */
ret = bs->free_pages(addr, pages);
if (ret != EFI_SUCCESS)
- error(L"Can't free memory pages\r\n");
+ error(u"Can't free memory pages\r\n");
pages = efi_size_in_pages(buffer_size);
ret = bs->allocate_pages(EFI_ALLOCATE_ANY_PAGES,
EFI_ACPI_RECLAIM_MEMORY,
pages, &addr);
if (ret != EFI_SUCCESS) {
- error(L"Out of memory\r\n");
+ error(u"Out of memory\r\n");
goto out;
}
dtb = (struct fdt_header *)(uintptr_t)addr;
ret = file->setpos(file, 0);
if (ret != EFI_SUCCESS) {
- error(L"Can't position file\r\n");
+ error(u"Can't position file\r\n");
goto out;
}
ret = file->read(file, &buffer_size, dtb);
if (ret != EFI_SUCCESS) {
- error(L"Can't read file\r\n");
+ error(u"Can't read file\r\n");
goto out;
}
buffer_size = pages << EFI_PAGE_SHIFT;
EFI_DT_INSTALL_TABLE);
}
if (ret == EFI_SUCCESS)
- print(L"device-tree installed\r\n");
+ print(u"device-tree installed\r\n");
else
- error(L"Device-tree fix-up failed\r\n");
+ error(u"Device-tree fix-up failed\r\n");
out:
if (addr) {
ret2 = bs->free_pages(addr, pages);
if (ret2 != EFI_SUCCESS)
- error(L"Can't free memory pages\r\n");
+ error(u"Can't free memory pages\r\n");
}
if (file) {
ret2 = file->close(file);
if (ret2 != EFI_SUCCESS)
- error(L"Can't close file\r\n");
+ error(u"Can't close file\r\n");
}
if (root) {
ret2 = root->close(root);
if (ret2 != EFI_SUCCESS)
- error(L"Can't close volume\r\n");
+ error(u"Can't close volume\r\n");
}
return ret;
}
dtb = get_dtb(systable);
if (!dtb) {
- error(L"DTB not found\r\n");
+ error(u"DTB not found\r\n");
return EFI_NOT_FOUND;
}
if (f2h(dtb->magic) != FDT_MAGIC) {
- error(L"Wrong device tree magic\r\n");
+ error(u"Wrong device tree magic\r\n");
return EFI_NOT_FOUND;
}
dtb_size = f2h(dtb->totalsize);
/* Open volume */
ret = file_system->open_volume(file_system, &root);
if (ret != EFI_SUCCESS) {
- error(L"Failed to open volume\r\n");
+ error(u"Failed to open volume\r\n");
return ret;
}
/* Check if file already exists */
ret = root->open(root, &file, filename, EFI_FILE_MODE_READ, 0);
if (ret == EFI_SUCCESS) {
file->close(file);
- print(L"Overwrite existing file (y/n)? ");
+ print(u"Overwrite existing file (y/n)? ");
ret = efi_input_yn();
- print(L"\r\n");
+ print(u"\r\n");
if (ret != EFI_SUCCESS) {
root->close(root);
- error(L"Aborted by user\r\n");
+ error(u"Aborted by user\r\n");
return ret;
}
}
/* Write file */
ret = file->write(file, &dtb_size, dtb);
if (ret != EFI_SUCCESS)
- error(L"Failed to write file\r\n");
+ error(u"Failed to write file\r\n");
file->close(file);
} else {
- error(L"Failed to open file\r\n");
+ error(u"Failed to open file\r\n");
}
root->close(root);
if (ret == EFI_SUCCESS) {
print(filename);
- print(L" written\r\n");
+ print(u" written\r\n");
}
return ret;
cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
cout->clear_screen(cout);
cout->set_attribute(cout, EFI_WHITE | EFI_BACKGROUND_BLACK);
- print(L"DTB Dump\r\n========\r\n\r\n");
+ print(u"DTB Dump\r\n========\r\n\r\n");
cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
for (;;) {
u16 *pos;
efi_uintn_t ret;
- print(L"=> ");
+ print(u"=> ");
ret = efi_input(command, sizeof(command));
if (ret == EFI_ABORTED)
break;
pos = skip_whitespace(command);
- if (starts_with(pos, L"exit"))
+ if (starts_with(pos, u"exit"))
break;
- else if (starts_with(pos, L"load "))
+ else if (starts_with(pos, u"load "))
do_load(pos + 5);
- else if (starts_with(pos, L"save "))
+ else if (starts_with(pos, u"save "))
do_save(pos + 5);
else
do_help();
static const struct efi_boot_services *boottime;
static const struct efi_runtime_services *runtime;
static efi_handle_t handle;
-static u16 reset_message[] = L"Selftest completed";
+static u16 reset_message[] = u"Selftest completed";
static int *setup_status;
/*
}
/* Read file */
- ret = root->open(root, &file, L"hello.txt", EFI_FILE_MODE_READ,
+ ret = root->open(root, &file, u"hello.txt", EFI_FILE_MODE_READ,
0);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to open file\n");
#ifdef CONFIG_FAT_WRITE
/* Write file */
- ret = root->open(root, &file, L"u-boot.txt", EFI_FILE_MODE_READ |
+ ret = root->open(root, &file, u"u-boot.txt", EFI_FILE_MODE_READ |
EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE, 0);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to open file\n");
/* Verify file */
boottime->set_mem(buf, sizeof(buf), 0);
- ret = root->open(root, &file, L"u-boot.txt", EFI_FILE_MODE_READ,
+ ret = root->open(root, &file, u"u-boot.txt", EFI_FILE_MODE_READ,
0);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to open file\n");
{ DEVICE_PATH_TYPE_MEDIA_DEVICE,
DEVICE_PATH_SUB_TYPE_FILE_PATH,
sizeof(struct efi_device_path) + 12},
- L"u-boot.bin",
+ u"u-boot.bin",
};
u16 *string;
efi_status_t ret;
DEVICE_PATH_SUB_TYPE_FILE_PATH,
sizeof(dp.dp) + sizeof(dp.filename),
},
- L"bug.efi",
+ u"bug.efi",
{
DEVICE_PATH_TYPE_END,
DEVICE_PATH_SUB_TYPE_END,
// SPDX-License-Identifier: GPL-2.0+
/*
- * efi_selftest_pos
+ * efi_selftest_fdt
*
* Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ * Copyright (c) 2022 Ventana Micro Systems Inc
*
- * Test the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.
- *
- * The following services are tested:
- * OutputString, TestString, SetAttribute.
+ * Check the device tree, test the RISCV_EFI_BOOT_PROTOCOL.
*/
+#include <efi_riscv.h>
#include <efi_selftest.h>
#include <linux/libfdt.h>
static const efi_guid_t fdt_guid = EFI_FDT_GUID;
static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID;
+static const efi_guid_t riscv_efi_boot_protocol_guid =
+ RISCV_EFI_BOOT_PROTOCOL_GUID;
/**
* f2h() - convert FDT value to host endianness.
return EFI_ST_SUCCESS;
}
+__maybe_unused static efi_status_t get_boot_hartid(efi_uintn_t *efi_hartid)
+{
+ efi_status_t ret;
+ struct riscv_efi_boot_protocol *prot;
+
+ /* Get RISC-V boot protocol */
+ ret = boottime->locate_protocol(&riscv_efi_boot_protocol_guid, NULL,
+ (void **)&prot);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("RISC-V Boot Protocol not available\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Get boot hart ID from EFI protocol */
+ ret = prot->get_boot_hartid(prot, efi_hartid);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Could not retrieve boot hart ID\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
/*
* Execute unit test.
*
char *str;
efi_status_t ret;
- str = get_property(L"compatible", NULL);
+ str = get_property(u"compatible", NULL);
if (str) {
efi_st_printf("compatible: %s\n", str);
ret = boottime->free_pool(str);
efi_st_error("Missing property 'compatible'\n");
return EFI_ST_FAILURE;
}
- str = get_property(L"serial-number", NULL);
+ str = get_property(u"serial-number", NULL);
if (str) {
efi_st_printf("serial-number: %s\n", str);
ret = boottime->free_pool(str);
return EFI_ST_FAILURE;
}
}
- str = get_property(L"boot-hartid", L"chosen");
if (IS_ENABLED(CONFIG_RISCV)) {
- if (str) {
- efi_st_printf("boot-hartid: %u\n",
- f2h(*(fdt32_t *)str));
- ret = boottime->free_pool(str);
- if (ret != EFI_SUCCESS) {
- efi_st_error("FreePool failed\n");
+ u32 fdt_hartid;
+
+ str = get_property(u"boot-hartid", u"chosen");
+ if (!str) {
+ efi_st_error("boot-hartid missing in devicetree\n");
+ return EFI_ST_FAILURE;
+ }
+ fdt_hartid = f2h(*(fdt32_t *)str);
+ efi_st_printf("boot-hartid: %u\n", fdt_hartid);
+
+ ret = boottime->free_pool(str);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ if (IS_ENABLED(CONFIG_EFI_RISCV_BOOT_PROTOCOL)) {
+ efi_uintn_t efi_hartid;
+ int r;
+
+ r = get_boot_hartid(&efi_hartid);
+ if (r != EFI_ST_SUCCESS)
+ return r;
+ /* Boot hart ID should be same */
+ if (efi_hartid != fdt_hartid) {
+ efi_st_error("boot-hartid differs: prot 0x%p, DT 0x%.8x\n",
+ (void *)(uintptr_t)efi_hartid,
+ fdt_hartid);
return EFI_ST_FAILURE;
}
- } else {
- efi_st_error("boot-hartid not found\n");
- return EFI_ST_FAILURE;
}
}
ret = hii_string_protocol->new_string(hii_string_protocol, handle,
&id, (u8 *)"en-US",
- L"Japanese", L"Japanese", NULL);
+ u"Japanese", u"Japanese", NULL);
if (ret != EFI_SUCCESS) {
efi_st_error("new_string returned %u\n",
(unsigned int)ret);
ret = hii_string_protocol->new_string(hii_string_protocol, handle,
&id, (u8 *)"en-US",
- L"Japanese", L"Japanese", NULL);
+ u"Japanese", u"Japanese", NULL);
if (ret != EFI_SUCCESS) {
efi_st_error("new_string returned %u\n",
(unsigned int)ret);
ret = hii_string_protocol->new_string(hii_string_protocol, handle,
&id, (u8 *)"en-US",
- L"Japanese", L"Japanese", NULL);
+ u"Japanese", u"Japanese", NULL);
if (ret != EFI_SUCCESS) {
efi_st_error("new_string returned %u\n",
(unsigned int)ret);
ret = hii_string_protocol->set_string(hii_string_protocol, handle,
id, (u8 *)"en-US",
- L"Nihongo", NULL);
+ u"Nihongo", NULL);
if (ret != EFI_SUCCESS) {
efi_st_error("set_string returned %u\n",
(unsigned int)ret);
FILE_NAME_SIZE * sizeof(u16),
}
},
- L"\\lf.efi",
+ u"\\lf.efi",
{
DEVICE_PATH_TYPE_END,
DEVICE_PATH_SUB_TYPE_END,
FILE_NAME_SIZE * sizeof(u16),
}
},
- L"\\lf2.efi",
+ u"\\lf2.efi",
{
DEVICE_PATH_TYPE_END,
DEVICE_PATH_SUB_TYPE_END,
/* Binary logarithm of the block size */
#define LB_BLOCK_SIZE 9
-#define FILE_NAME L"app.efi"
-#define VOLUME_NAME L"EfiDisk"
+#define FILE_NAME u"app.efi"
+#define VOLUME_NAME u"EfiDisk"
static struct efi_boot_services *boottime;
static efi_handle_t handle_image;
struct efi_simple_text_output_protocol *con_out = systable->con_out;
con_out->output_string(con_out,
- L"EFI application triggers exception.\n");
+ u"EFI application triggers exception.\n");
#if defined(CONFIG_ARM)
/*
#elif defined(CONFIG_X86)
asm volatile (".word 0xffff\n");
#endif
- con_out->output_string(con_out, L"Exception not triggered.\n");
+ con_out->output_string(con_out, u"Exception not triggered.\n");
return EFI_ABORTED;
}
NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
if (ret != EFI_SUCCESS) {
cout->output_string(cout,
- L"Could not open loaded image protocol");
+ u"Could not open loaded image protocol");
return ret;
}
if ((void *)check_loaded_image_protocol <
loaded_image_protocol->image_base +
loaded_image_protocol->image_size) {
cout->output_string(cout,
- L"Incorrect image_base or image_size\n");
+ u"Incorrect image_base or image_size\n");
return EFI_NOT_FOUND;
}
return EFI_SUCCESS;
efi_status_t ret;
u16 text[] = EFI_ST_SUCCESS_STR;
- con_out->output_string(con_out, L"EFI application calling Exit\n");
+ con_out->output_string(con_out, u"EFI application calling Exit\n");
if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS) {
con_out->output_string(con_out,
- L"Loaded image protocol missing\n");
+ u"Loaded image protocol missing\n");
ret = EFI_NOT_FOUND;
goto out;
}
struct efi_simple_text_output_protocol *con_out = systable->con_out;
con_out->output_string(con_out,
- L"EFI application returning w/o calling Exit\n");
+ u"EFI application returning w/o calling Exit\n");
/* The return value is checked by the calling test */
return EFI_INCOMPATIBLE_VERSION;
*/
static int execute(void)
{
- u16 reset_data[] = L"Reset by selftest";
+ u16 reset_data[] = u"Reset by selftest";
runtime->reset_system(EFI_RESET_COLD, EFI_SUCCESS,
sizeof(reset_data), reset_data);
}
/* TestString */
ret = con_out->test_string(con_out,
- L" !\"#$%&'()*+,-./0-9:;<=>?@A-Z[\\]^_`a-z{|}~\n");
+ u" !\"#$%&'()*+,-./0-9:;<=>?@A-Z[\\]^_`a-z{|}~\n");
if (ret != EFI_ST_SUCCESS) {
efi_st_error("TestString failed for ANSI characters\n");
return EFI_ST_FAILURE;
}
/* OutputString */
ret = con_out->output_string(con_out,
- L"Testing cursor column update\n");
+ u"Testing cursor column update\n");
if (ret != EFI_ST_SUCCESS) {
efi_st_error("OutputString failed for ANSI characters");
return EFI_ST_FAILURE;
efi_st_error("Cursor column not 0 at beginning of line\n");
return EFI_ST_FAILURE;
}
- ret = con_out->output_string(con_out, L"123");
+ ret = con_out->output_string(con_out, u"123");
if (ret != EFI_ST_SUCCESS) {
efi_st_error("OutputString failed for ANSI characters\n");
return EFI_ST_FAILURE;
efi_st_error("Cursor column not incremented properly\n");
return EFI_ST_FAILURE;
}
- ret = con_out->output_string(con_out, L"\b");
+ ret = con_out->output_string(con_out, u"\b");
if (ret != EFI_ST_SUCCESS) {
efi_st_error("OutputString failed for backspace\n");
return EFI_ST_FAILURE;
efi_st_error("Cursor column not decremented properly\n");
return EFI_ST_FAILURE;
}
- ret = con_out->output_string(con_out, L"\b\b");
+ ret = con_out->output_string(con_out, u"\b\b");
if (ret != EFI_ST_SUCCESS) {
efi_st_error("OutputString failed for backspace\n");
return EFI_ST_FAILURE;
efi_st_error("Cursor column not decremented properly\n");
return EFI_ST_FAILURE;
}
- ret = con_out->output_string(con_out, L"\b\b");
+ ret = con_out->output_string(con_out, u"\b\b");
if (ret != EFI_ST_SUCCESS) {
efi_st_error("OutputString failed for backspace\n");
return EFI_ST_FAILURE;
static int test_stri_coll(void)
{
efi_intn_t ret;
- u16 c1[] = L"first";
- u16 c2[] = L"FIRST";
- u16 c3[] = L"second";
+ u16 c1[] = u"first";
+ u16 c2[] = u"FIRST";
+ u16 c3[] = u"second";
ret = unicode_collation_protocol->stri_coll(unicode_collation_protocol,
c1, c2);
static int test_metai_match(void)
{
bool ret;
- const u16 c[] = L"Das U-Boot";
+ const u16 c[] = u"Das U-Boot";
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"*");
+ unicode_collation_protocol, c, u"*");
if (!ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"Da[rstu] U-Boot");
+ unicode_collation_protocol, c, u"Da[rstu] U-Boot");
if (!ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"Da[q-v] U-Boot");
+ unicode_collation_protocol, c, u"Da[q-v] U-Boot");
if (!ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"Da? U-Boot");
+ unicode_collation_protocol, c, u"Da? U-Boot");
if (!ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"D*Bo*t");
+ unicode_collation_protocol, c, u"D*Bo*t");
if (!ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"Da[xyz] U-Boot");
+ unicode_collation_protocol, c, u"Da[xyz] U-Boot");
if (ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"Da[a-d] U-Boot");
+ unicode_collation_protocol, c, u"Da[a-d] U-Boot");
if (ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"Da?? U-Boot");
+ unicode_collation_protocol, c, u"Da?? U-Boot");
if (ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
}
ret = unicode_collation_protocol->metai_match(
- unicode_collation_protocol, c, L"D*Bo*tt");
+ unicode_collation_protocol, c, u"D*Bo*tt");
if (ret) {
efi_st_error("metai_match returned %u\n", ret);
return EFI_ST_FAILURE;
static int test_str_lwr(void)
{
- u16 c[] = L"U-Boot";
+ u16 c[] = u"U-Boot";
unicode_collation_protocol->str_lwr(unicode_collation_protocol, c);
if (efi_st_strcmp_16_8(c, "u-boot")) {
static int test_str_upr(void)
{
- u16 c[] = L"U-Boot";
+ u16 c[] = u"U-Boot";
unicode_collation_protocol->str_upr(unicode_collation_protocol, c);
if (efi_st_strcmp_16_8(c, "U-BOOT")) {
boottime->set_mem(fat, sizeof(fat), 0);
ret = unicode_collation_protocol->str_to_fat(unicode_collation_protocol,
- L"U -Boo.t", 6, fat);
- if (ret || efi_st_strcmp_16_8(L"U-BOOT", fat)) {
+ u"U -Boo.t", 6, fat);
+ if (ret || efi_st_strcmp_16_8(u"U-BOOT", fat)) {
efi_st_error("str_to_fat returned %u, \"%s\"\n", ret, fat);
return EFI_ST_FAILURE;
}
boottime->set_mem(fat, 16, 0);
ret = unicode_collation_protocol->str_to_fat(unicode_collation_protocol,
- L"U\\Boot", 6, fat);
- if (!ret || efi_st_strcmp_16_8(L"U_BOOT", fat)) {
+ u"U\\Boot", 6, fat);
+ if (!ret || efi_st_strcmp_16_8(u"U_BOOT", fat)) {
efi_st_error("str_to_fat returned %u, \"%s\"\n", ret, fat);
return EFI_ST_FAILURE;
}
};
static struct efi_st_translate efi_st_control_characters[] = {
- {0, L"Null"},
- {8, L"BS"},
- {9, L"TAB"},
- {10, L"LF"},
- {13, L"CR"},
+ {0, u"Null"},
+ {8, u"BS"},
+ {9, u"TAB"},
+ {10, u"LF"},
+ {13, u"CR"},
{0, NULL},
};
-static u16 efi_st_ch[] = L"' '";
-static u16 efi_st_unknown[] = L"unknown";
+static u16 efi_st_ch[] = u"' '";
+static u16 efi_st_unknown[] = u"unknown";
static struct efi_st_translate efi_st_scan_codes[] = {
- {0x00, L"Null"},
- {0x01, L"Up"},
- {0x02, L"Down"},
- {0x03, L"Right"},
- {0x04, L"Left"},
- {0x05, L"Home"},
- {0x06, L"End"},
- {0x07, L"Insert"},
- {0x08, L"Delete"},
- {0x09, L"Page Up"},
- {0x0a, L"Page Down"},
- {0x0b, L"FN 1"},
- {0x0c, L"FN 2"},
- {0x0d, L"FN 3"},
- {0x0e, L"FN 4"},
- {0x0f, L"FN 5"},
- {0x10, L"FN 6"},
- {0x11, L"FN 7"},
- {0x12, L"FN 8"},
- {0x13, L"FN 9"},
- {0x14, L"FN 10"},
- {0x15, L"FN 11"},
- {0x16, L"FN 12"},
- {0x17, L"Escape"},
- {0x68, L"FN 13"},
- {0x69, L"FN 14"},
- {0x6a, L"FN 15"},
- {0x6b, L"FN 16"},
- {0x6c, L"FN 17"},
- {0x6d, L"FN 18"},
- {0x6e, L"FN 19"},
- {0x6f, L"FN 20"},
- {0x70, L"FN 21"},
- {0x71, L"FN 22"},
- {0x72, L"FN 23"},
- {0x73, L"FN 24"},
- {0x7f, L"Mute"},
- {0x80, L"Volume Up"},
- {0x81, L"Volume Down"},
- {0x100, L"Brightness Up"},
- {0x101, L"Brightness Down"},
- {0x102, L"Suspend"},
- {0x103, L"Hibernate"},
- {0x104, L"Toggle Display"},
- {0x105, L"Recovery"},
- {0x106, L"Reject"},
+ {0x00, u"Null"},
+ {0x01, u"Up"},
+ {0x02, u"Down"},
+ {0x03, u"Right"},
+ {0x04, u"Left"},
+ {0x05, u"Home"},
+ {0x06, u"End"},
+ {0x07, u"Insert"},
+ {0x08, u"Delete"},
+ {0x09, u"Page Up"},
+ {0x0a, u"Page Down"},
+ {0x0b, u"FN 1"},
+ {0x0c, u"FN 2"},
+ {0x0d, u"FN 3"},
+ {0x0e, u"FN 4"},
+ {0x0f, u"FN 5"},
+ {0x10, u"FN 6"},
+ {0x11, u"FN 7"},
+ {0x12, u"FN 8"},
+ {0x13, u"FN 9"},
+ {0x14, u"FN 10"},
+ {0x15, u"FN 11"},
+ {0x16, u"FN 12"},
+ {0x17, u"Escape"},
+ {0x68, u"FN 13"},
+ {0x69, u"FN 14"},
+ {0x6a, u"FN 15"},
+ {0x6b, u"FN 16"},
+ {0x6c, u"FN 17"},
+ {0x6d, u"FN 18"},
+ {0x6e, u"FN 19"},
+ {0x6f, u"FN 20"},
+ {0x70, u"FN 21"},
+ {0x71, u"FN 22"},
+ {0x72, u"FN 23"},
+ {0x73, u"FN 24"},
+ {0x7f, u"Mute"},
+ {0x80, u"Volume Up"},
+ {0x81, u"Volume Down"},
+ {0x100, u"Brightness Up"},
+ {0x101, u"Brightness Down"},
+ {0x102, u"Suspend"},
+ {0x103, u"Hibernate"},
+ {0x104, u"Toggle Display"},
+ {0x105, u"Recovery"},
+ {0x106, u"Reject"},
{0x0, NULL},
};
return EFI_ST_FAILURE;
}
/* Set variable 0 */
- ret = runtime->set_variable(L"efi_st_var0", &guid_vendor0,
+ ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0,
EFI_VARIABLE_BOOTSERVICE_ACCESS,
3, v + 4);
if (ret != EFI_SUCCESS) {
}
data[3] = 0xff;
len = 3;
- ret = runtime->get_variable(L"efi_st_var0", &guid_vendor0,
+ ret = runtime->get_variable(u"efi_st_var0", &guid_vendor0,
&attr, &len, data);
if (ret != EFI_SUCCESS) {
efi_st_error("GetVariable failed\n");
return EFI_ST_FAILURE;
}
/* Set variable 1 */
- ret = runtime->set_variable(L"efi_st_var1", &guid_vendor1,
+ ret = runtime->set_variable(u"efi_st_var1", &guid_vendor1,
EFI_VARIABLE_BOOTSERVICE_ACCESS,
8, v);
if (ret != EFI_SUCCESS) {
return EFI_ST_FAILURE;
}
len = EFI_ST_MAX_DATA_SIZE;
- ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
+ ret = runtime->get_variable(u"efi_st_var1", &guid_vendor1,
&attr, &len, data);
if (ret != EFI_SUCCESS) {
efi_st_error("GetVariable failed\n");
return EFI_ST_FAILURE;
}
/* Append variable 1 */
- ret = runtime->set_variable(L"efi_st_var1", &guid_vendor1,
+ ret = runtime->set_variable(u"efi_st_var1", &guid_vendor1,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_APPEND_WRITE,
7, v + 8);
return EFI_ST_FAILURE;
}
len = EFI_ST_MAX_DATA_SIZE;
- ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
+ ret = runtime->get_variable(u"efi_st_var1", &guid_vendor1,
&attr, &len, data);
if (ret != EFI_SUCCESS) {
efi_st_error("GetVariable failed\n");
if (memcmp(data, v, len))
efi_st_todo("GetVariable returned wrong value\n");
/* Append variable 2 */
- ret = runtime->set_variable(L"efi_none", &guid_vendor1,
+ ret = runtime->set_variable(u"efi_none", &guid_vendor1,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_APPEND_WRITE,
15, v);
return EFI_ST_FAILURE;
}
/* Delete variable 1 */
- ret = runtime->set_variable(L"efi_st_var1", &guid_vendor1,
+ ret = runtime->set_variable(u"efi_st_var1", &guid_vendor1,
0, 0, NULL);
if (ret != EFI_SUCCESS) {
efi_st_error("SetVariable failed\n");
return EFI_ST_FAILURE;
}
len = EFI_ST_MAX_DATA_SIZE;
- ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
+ ret = runtime->get_variable(u"efi_st_var1", &guid_vendor1,
&attr, &len, data);
if (ret != EFI_NOT_FOUND) {
efi_st_error("Variable was not deleted\n");
return EFI_ST_FAILURE;
}
/* Delete variable 0 */
- ret = runtime->set_variable(L"efi_st_var0", &guid_vendor0,
+ ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0,
0, 0, NULL);
if (ret != EFI_SUCCESS) {
efi_st_error("SetVariable failed\n");
return EFI_ST_FAILURE;
}
len = EFI_ST_MAX_DATA_SIZE;
- ret = runtime->get_variable(L"efi_st_var0", &guid_vendor0,
+ ret = runtime->get_variable(u"efi_st_var0", &guid_vendor0,
&attr, &len, data);
if (ret != EFI_NOT_FOUND) {
efi_st_error("Variable was not deleted\n");
return EFI_ST_FAILURE;
}
- ret = runtime->set_variable(L"efi_st_var0", &guid_vendor0,
+ ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
3, v + 4);
return EFI_ST_FAILURE;
}
len = EFI_ST_MAX_DATA_SIZE;
- ret = runtime->get_variable(L"PlatformLangCodes", &guid_vendor0,
+ ret = runtime->get_variable(u"PlatformLangCodes", &guid_vendor0,
&attr, &len, data);
if (ret != EFI_SUCCESS) {
efi_st_error("GetVariable failed\n");
struct efi_input_key key = {0};
efi_uintn_t index;
efi_uintn_t pos = 0;
- u16 outbuf[2] = L" ";
+ u16 outbuf[2] = u" ";
efi_status_t ret;
/* Drain the console input */
continue;
switch (key.scan_code) {
case 0x17: /* Escape */
- print(L"\r\nAborted\r\n");
+ print(u"\r\nAborted\r\n");
return EFI_ABORTED;
default:
break;
case 0x08: /* Backspace */
if (pos) {
buffer[pos--] = 0;
- print(L"\b \b");
+ print(u"\b \b");
}
break;
case 0x0a: /* Linefeed */
case 0x0d: /* Carriage return */
- print(L"\r\n");
+ print(u"\r\n");
return EFI_SUCCESS;
default:
break;
*/
static void do_help(void)
{
- error(L"load - show length and CRC32 of initial RAM disk\r\n");
- error(L"save <initrd> - save initial RAM disk to file\r\n");
- error(L"exit - exit the shell\r\n");
+ error(u"load - show length and CRC32 of initial RAM disk\r\n");
+ error(u"save <initrd> - save initial RAM disk to file\r\n");
+ error(u"exit - exit the shell\r\n");
}
/**
*initrd_size = 0;
ret = bs->locate_device_path(&load_file2_guid, &dp, &handle);
if (ret != EFI_SUCCESS) {
- error(L"Load File2 protocol not found\r\n");
+ error(u"Load File2 protocol not found\r\n");
return ret;
}
ret = bs->handle_protocol(handle, &load_file2_guid,
ret = load_file2_prot->load_file(load_file2_prot, dp, false,
initrd_size, NULL);
if (ret != EFI_BUFFER_TOO_SMALL) {
- error(L"Load File2 protocol does not provide file length\r\n");
+ error(u"Load File2 protocol does not provide file length\r\n");
return EFI_LOAD_ERROR;
}
ret = bs->allocate_pages(EFI_ALLOCATE_ANY_PAGES, EFI_LOADER_DATA,
efi_size_in_pages(*initrd_size), &buffer);
if (ret != EFI_SUCCESS) {
- error(L"Out of memory\r\n");
+ error(u"Out of memory\r\n");
return ret;
}
*initrd = (void *)(uintptr_t)buffer;
ret = load_file2_prot->load_file(load_file2_prot, dp, false,
initrd_size, *initrd);
if (ret != EFI_SUCCESS) {
- error(L"Load File2 protocol failed to provide file\r\n");
+ error(u"Load File2 protocol failed to provide file\r\n");
bs->free_pages(buffer, efi_size_in_pages(*initrd_size));
return EFI_LOAD_ERROR;
}
ret = get_initrd(&initrd, &initrd_size);
if (ret != EFI_SUCCESS)
return ret;
- print(L"length: 0x");
+ print(u"length: 0x");
printx(initrd_size, 1);
- print(L"\r\n");
+ print(u"\r\n");
ret = bs->calculate_crc32(initrd, initrd_size, &crc32);
if (ret != EFI_SUCCESS) {
- error(L"Calculating CRC32 failed\r\n");
+ error(u"Calculating CRC32 failed\r\n");
return EFI_LOAD_ERROR;
}
- print(L"crc32: 0x");
+ print(u"crc32: 0x");
printx(crc32, 8);
- print(L"\r\n");
+ print(u"\r\n");
return EFI_SUCCESS;
}
(void **)&loaded_image, NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL);
if (ret != EFI_SUCCESS) {
- error(L"Loaded image protocol not found\r\n");
+ error(u"Loaded image protocol not found\r\n");
goto out;
}
(void **)&file_system, NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL);
if (ret != EFI_SUCCESS) {
- error(L"Failed to open simple file system protocol\r\n");
+ error(u"Failed to open simple file system protocol\r\n");
goto out;
}
/* Open volume */
ret = file_system->open_volume(file_system, &root);
if (ret != EFI_SUCCESS) {
- error(L"Failed to open volume\r\n");
+ error(u"Failed to open volume\r\n");
goto out;
}
/* Check if file already exists */
ret = root->open(root, &file, filename, EFI_FILE_MODE_READ, 0);
if (ret == EFI_SUCCESS) {
file->close(file);
- print(L"Overwrite existing file (y/n)? ");
+ print(u"Overwrite existing file (y/n)? ");
ret = efi_input_yn();
- print(L"\r\n");
+ print(u"\r\n");
if (ret != EFI_SUCCESS) {
root->close(root);
- error(L"Aborted by user\r\n");
+ error(u"Aborted by user\r\n");
goto out;
}
}
/* Write file */
ret = file->write(file, &initrd_size, initrd);
if (ret != EFI_SUCCESS) {
- error(L"Failed to write file\r\n");
+ error(u"Failed to write file\r\n");
} else {
print(filename);
- print(L" written\r\n");
+ print(u" written\r\n");
}
file->close(file);
} else {
- error(L"Failed to open file\r\n");
+ error(u"Failed to open file\r\n");
}
root->close(root);
cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
cout->clear_screen(cout);
cout->set_attribute(cout, EFI_WHITE | EFI_BACKGROUND_BLACK);
- print(L"INITRD Dump\r\n========\r\n\r\n");
+ print(u"INITRD Dump\r\n========\r\n\r\n");
cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK);
for (;;) {
u16 *pos;
efi_uintn_t ret;
- print(L"=> ");
+ print(u"=> ");
ret = efi_input(command, sizeof(command));
if (ret == EFI_ABORTED)
break;
pos = skip_whitespace(command);
- if (starts_with(pos, L"exit"))
+ if (starts_with(pos, u"exit"))
break;
- else if (starts_with(pos, L"load"))
+ else if (starts_with(pos, u"load"))
do_load();
- else if (starts_with(pos, L"save "))
+ else if (starts_with(pos, u"save "))
do_save(pos + 5);
else
do_help();
#else
#define CHAR_PATH_SEPARATOR '/'
-#define WCHAR_PATH_SEPARATOR L'/'
+#define WCHAR_PATH_SEPARATOR u'/'
#define STRING_PATH_SEPARATOR "/"
-#define WSTRING_PATH_SEPARATOR L"/"
+#define WSTRING_PATH_SEPARATOR u"/"
#endif
static __maybe_unused char *string16(char *buf, char *end, u16 *s,
int field_width, int precision, int flags)
{
- const u16 *str = s ? s : L"<NULL>";
+ const u16 *str = s ? s : u"<NULL>";
ssize_t i, len = utf16_strnlen(str, precision);
if (!(flags & LEFT))
for (; len < field_width; --field_width)
ADDCH(buf, ' ');
- for (i = 0; i < len && buf + utf16_utf8_strnlen(str, 1) <= end; ++i) {
+ if (buf < end)
+ *buf = 0;
+ for (i = 0; i < len; ++i) {
+ int slen = utf16_utf8_strnlen(str, 1);
s32 s = utf16_get(&str);
if (s < 0)
s = '?';
- utf8_put(s, &buf);
+ if (buf + slen < end) {
+ utf8_put(s, &buf);
+ if (buf < end)
+ *buf = 0;
+ } else {
+ buf += slen;
+ }
}
for (; len < field_width; --field_width)
ADDCH(buf, ' ');
+
return buf;
}
always := $(hostprogs-y)
# Let clean descend into subdirs
-subdir- += basic kconfig
+subdir- += basic kconfig dtc
cmd_u_boot_cfg = \
$(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \
grep 'define CONFIG_' $@.tmp | \
- sed '/define CONFIG_IS_ENABLED(/d;/define CONFIG_VAL(/d;' > $@; \
+ sed '/define CONFIG_IS_ENABLED(/d;/define CONFIG_IF_ENABLED_INT(/d;/define CONFIG_VAL(/d;' > $@; \
rm $@.tmp; \
} || { \
rm $@.tmp; false; \
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_$(SPL_)OF_LIST)))
# which is pure ASL code. The Intel ASL (ACPI (Advanced Configuration and Power
# Interface) Source Language compiler (iasl) then converts this ASL code into a
# C file containing the hex data to build into U-Boot. This file is called
-# dsdt.hex (despite us setting the prefix to .../dsdt.asl.tmp) so must be
-# renamed to dsdt.c for consumption by the build system.
+# dsdt_generated.hex (despite us setting the prefix to .../dsdt_generated.asl.tmp)
+# so must be renamed to dsdt_generated.c for consumption by the build system.
ASL_TMP = $(patsubst %.c,%.asl.tmp,$@)
quiet_cmd_acpi_c_asl= ASL $<
$(if $(KBUILD_VERBOSE:1=), >/dev/null) && \
mv $(patsubst %.c,%.hex,$@) $@
-$(obj)/dsdt.c: $(src)/dsdt.asl
+$(obj)/dsdt_generated.c: $(src)/dsdt.asl
$(call cmd,acpi_c_asl)
- $(Q)sed -i -e "s,dsdt_aml_code,AmlCode," $@
+ $(Q)sed -i -e "s,dsdt_generated_aml_code,AmlCode," $@
# Bzip2
# ---------------------------------------------------------------------------
my $spelling_file = "$D/spelling.txt";
my $codespell = 0;
my $codespellfile = "/usr/share/codespell/dictionary.txt";
+my $user_codespellfile = "";
my $conststructsfile = "$D/const_structs.checkpatch";
my $u_boot = 0;
my $docsfile = "$D/../doc/develop/checkpatch.rst";
--ignore-perl-version override checking of perl version. expect
runtime errors.
--codespell Use the codespell dictionary for spelling/typos
- (default:/usr/share/codespell/dictionary.txt)
+ (default:$codespellfile)
--codespellfile Use this codespell dictionary
--typedefsfile Read additional types from this file
--color[=WHEN] Use colors 'always', 'never', or only when output
'debug=s' => \%debug,
'test-only=s' => \$tst_only,
'codespell!' => \$codespell,
- 'codespellfile=s' => \$codespellfile,
+ 'codespellfile=s' => \$user_codespellfile,
'typedefsfile=s' => \$typedefsfile,
'u-boot' => \$u_boot,
'color=s' => \$color,
'kconfig-prefix=s' => \${CONFIG_},
'h|help' => \$help,
'version' => \$help
-) or help(1);
+) or $help = 2;
+
+if ($user_codespellfile) {
+ # Use the user provided codespell file unconditionally
+ $codespellfile = $user_codespellfile;
+} elsif (!(-f $codespellfile)) {
+ # If /usr/share/codespell/dictionary.txt is not present, try to find it
+ # under codespell's install directory: <codespell_root>/data/dictionary.txt
+ if (($codespell || $help) && which("codespell") ne "" && which("python") ne "") {
+ my $python_codespell_dict = << "EOF";
+
+import os.path as op
+import codespell_lib
+codespell_dir = op.dirname(codespell_lib.__file__)
+codespell_file = op.join(codespell_dir, 'data', 'dictionary.txt')
+print(codespell_file, end='')
+EOF
+
+ my $codespell_dict = `python -c "$python_codespell_dict" 2> /dev/null`;
+ $codespellfile = $codespell_dict if (-f $codespell_dict);
+ }
+}
-help(0) if ($help);
+# $help is 1 if either -h, --help or --version is passed as option - exitcode: 0
+# $help is 2 if invalid option is passed - exitcode: 1
+help($help - 1) if ($help);
die "$P: --git cannot be used with --file or --fix\n" if ($git && ($file || $fix));
die "$P: --verbose cannot be used with --terse\n" if ($verbose && $terse);
____cacheline_aligned|
____cacheline_aligned_in_smp|
____cacheline_internodealigned_in_smp|
- __weak
+ __weak|
+ __alloc_size\s*\(\s*\d+\s*(?:,\s*\d+\s*)?\)
}x;
our $Modifier;
our $Inline = qr{inline|__always_inline|noinline|__inline|__inline__};
our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?};
our $Int = qr{[0-9]+$Int_type?};
our $Octal = qr{0[0-7]+$Int_type?};
-our $String = qr{"[X\t]*"};
+our $String = qr{(?:\b[Lu])?"[X\t]*"};
our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?};
sub is_SPDX_License_valid {
my ($license) = @_;
- return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$gitroot"));
+ return 1 if (!$tree || which("python3") eq "" || !(-x "$root/scripts/spdxcheck.py") || !(-e "$gitroot"));
my $root_path = abs_path($root);
- my $status = `cd "$root_path"; echo "$license" | python scripts/spdxcheck.py -`;
+ my $status = `cd "$root_path"; echo "$license" | scripts/spdxcheck.py -`;
return 0 if ($status ne "");
return 1;
}
# git log --format='%H %s' -1 $line |
# echo "commit $(cut -c 1-12,41-)"
# done
- } elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\./) {
+ } elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\./ ||
+ $lines[0] =~ /^fatal: bad object $commit/) {
$id = undef;
} else {
$id = substr($lines[0], 0, 12);
my $reported_maintainer_file = 0;
my $non_utf8_charset = 0;
+ my $last_git_commit_id_linenr = -1;
+
my $last_blank_line = 0;
my $last_coalesced_string_linenr = -1;
my ($email_name, $email_comment, $email_address, $comment1) = parse_email($ctx);
my ($author_name, $author_comment, $author_address, $comment2) = parse_email($author);
- if ($email_address eq $author_address && $email_name eq $author_name) {
+ if (lc $email_address eq lc $author_address && $email_name eq $author_name) {
$author_sob = $ctx;
$authorsignoff = 2;
- } elsif ($email_address eq $author_address) {
+ } elsif (lc $email_address eq lc $author_address) {
$author_sob = $ctx;
$authorsignoff = 3;
} elsif ($email_name eq $author_name) {
}
# Check for git id commit length and improperly formed commit descriptions
- if ($in_commit_log && !$commit_log_possible_stack_dump &&
+# A correctly formed commit description is:
+# commit <SHA-1 hash length 12+ chars> ("Complete commit subject")
+# with the commit subject '("' prefix and '")' suffix
+# This is a fairly compilicated block as it tests for what appears to be
+# bare SHA-1 hash with minimum length of 5. It also avoids several types of
+# possible SHA-1 matches.
+# A commit match can span multiple lines so this block attempts to find a
+# complete typical commit on a maximum of 3 lines
+ if ($perl_version_ok &&
+ $in_commit_log && !$commit_log_possible_stack_dump &&
$line !~ /^\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i &&
$line !~ /^This reverts commit [0-9a-f]{7,40}/ &&
- ($line =~ /\bcommit\s+[0-9a-f]{5,}\b/i ||
+ (($line =~ /\bcommit\s+[0-9a-f]{5,}\b/i ||
+ ($line =~ /\bcommit\s*$/i && defined($rawlines[$linenr]) && $rawlines[$linenr] =~ /^\s*[0-9a-f]{5,}\b/i)) ||
($line =~ /(?:\s|^)[0-9a-f]{12,40}(?:[\s"'\(\[]|$)/i &&
$line !~ /[\<\[][0-9a-f]{12,40}[\>\]]/i &&
$line !~ /\bfixes:\s*[0-9a-f]{12,40}/i))) {
my $long = 0;
my $case = 1;
my $space = 1;
- my $hasdesc = 0;
- my $hasparens = 0;
my $id = '0123456789ab';
my $orig_desc = "commit description";
my $description = "";
+ my $herectx = $herecurr;
+ my $has_parens = 0;
+ my $has_quotes = 0;
+
+ my $input = $line;
+ if ($line =~ /(?:\bcommit\s+[0-9a-f]{5,}|\bcommit\s*$)/i) {
+ for (my $n = 0; $n < 2; $n++) {
+ if ($input =~ /\bcommit\s+[0-9a-f]{5,}\s*($balanced_parens)/i) {
+ $orig_desc = $1;
+ $has_parens = 1;
+ # Always strip leading/trailing parens then double quotes if existing
+ $orig_desc = substr($orig_desc, 1, -1);
+ if ($orig_desc =~ /^".*"$/) {
+ $orig_desc = substr($orig_desc, 1, -1);
+ $has_quotes = 1;
+ }
+ last;
+ }
+ last if ($#lines < $linenr + $n);
+ $input .= " " . trim($rawlines[$linenr + $n]);
+ $herectx .= "$rawlines[$linenr + $n]\n";
+ }
+ $herectx = $herecurr if (!$has_parens);
+ }
- if ($line =~ /\b(c)ommit\s+([0-9a-f]{5,})\b/i) {
+ if ($input =~ /\b(c)ommit\s+([0-9a-f]{5,})\b/i) {
$init_char = $1;
$orig_commit = lc($2);
- } elsif ($line =~ /\b([0-9a-f]{12,40})\b/i) {
+ $short = 0 if ($input =~ /\bcommit\s+[0-9a-f]{12,40}/i);
+ $long = 1 if ($input =~ /\bcommit\s+[0-9a-f]{41,}/i);
+ $space = 0 if ($input =~ /\bcommit [0-9a-f]/i);
+ $case = 0 if ($input =~ /\b[Cc]ommit\s+[0-9a-f]{5,40}[^A-F]/);
+ } elsif ($input =~ /\b([0-9a-f]{12,40})\b/i) {
$orig_commit = lc($1);
}
- $short = 0 if ($line =~ /\bcommit\s+[0-9a-f]{12,40}/i);
- $long = 1 if ($line =~ /\bcommit\s+[0-9a-f]{41,}/i);
- $space = 0 if ($line =~ /\bcommit [0-9a-f]/i);
- $case = 0 if ($line =~ /\b[Cc]ommit\s+[0-9a-f]{5,40}[^A-F]/);
- if ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)"\)/i) {
- $orig_desc = $1;
- $hasparens = 1;
- } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s*$/i &&
- defined $rawlines[$linenr] &&
- $rawlines[$linenr] =~ /^\s*\("([^"]+)"\)/) {
- $orig_desc = $1;
- $hasparens = 1;
- } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("[^"]+$/i &&
- defined $rawlines[$linenr] &&
- $rawlines[$linenr] =~ /^\s*[^"]+"\)/) {
- $line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)$/i;
- $orig_desc = $1;
- $rawlines[$linenr] =~ /^\s*([^"]+)"\)/;
- $orig_desc .= " " . $1;
- $hasparens = 1;
- }
-
($id, $description) = git_commit_info($orig_commit,
$id, $orig_desc);
if (defined($id) &&
- ($short || $long || $space || $case || ($orig_desc ne $description) || !$hasparens)) {
+ ($short || $long || $space || $case || ($orig_desc ne $description) || !$has_quotes) &&
+ $last_git_commit_id_linenr != $linenr - 1) {
ERROR("GIT_COMMIT_ID",
- "Please use git commit description style 'commit <12+ chars of sha1> (\"<title line>\")' - ie: '${init_char}ommit $id (\"$description\")'\n" . $herecurr);
+ "Please use git commit description style 'commit <12+ chars of sha1> (\"<title line>\")' - ie: '${init_char}ommit $id (\"$description\")'\n" . $herectx);
}
+ #don't report the next line if this line ends in commit and the sha1 hash is the next line
+ $last_git_commit_id_linenr = $linenr if ($line =~ /\bcommit\s*$/i);
}
# Check for added, moved or deleted files
# XXX(foo);
# EXPORT_SYMBOL(something_foo);
my $name = $1;
+ $name =~ s/^\s*($Ident).*/$1/;
if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ &&
$name =~ /^${Ident}_$2/) {
#print "FOO C name<$name>\n";
}
}
-#goto labels aren't indented, allow a single space however
- if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
- !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
+# check that goto labels aren't indented (allow a single space indentation)
+# and ignore bitfield definitions like foo:1
+# Strictly, labels can have whitespace after the identifier and before the :
+# but this is not allowed here as many ?: uses would appear to be labels
+ if ($sline =~ /^.\s+[A-Za-z_][A-Za-z\d_]*:(?!\s*\d+)/ &&
+ $sline !~ /^. [A-Za-z\d_][A-Za-z\d_]*:/ &&
+ $sline !~ /^.\s+default:/) {
if (WARN("INDENTED_LABEL",
"labels should not be indented\n" . $herecurr) &&
$fix) {
# Return of what appears to be an errno should normally be negative
if ($sline =~ /\breturn(?:\s*\(+\s*|\s+)(E[A-Z]+)(?:\s*\)+\s*|\s*)[;:,]/) {
my $name = $1;
- if ($name ne 'EOF' && $name ne 'ERROR') {
+ if ($name ne 'EOF' && $name ne 'ERROR' && $name !~ /^EPOLL/) {
WARN("USE_NEGATIVE_ERRNO",
"return of an errno should typically be negative (ie: return -$1)\n" . $herecurr);
}
}
# concatenated string without spaces between elements
- if ($line =~ /$String[A-Za-z0-9_]/ || $line =~ /[A-Za-z0-9_]$String/) {
+ if ($line =~ /$String[A-Z_]/ ||
+ ($line =~ /([A-Za-z0-9_]+)$String/ && $1 !~ /^[Lu]$/)) {
if (CHK("CONCATENATED_STRING",
"Concatenated strings should use spaces between elements\n" . $herecurr) &&
$fix) {
}
# uncoalesced string fragments
- if ($line =~ /$String\s*"/) {
+ if ($line =~ /$String\s*[Lu]?"/) {
if (WARN("STRING_FRAGMENTS",
"Consecutive strings are generally better as a single string\n" . $herecurr) &&
$fix) {
CONFIG_AT91_GPIO_PULLUP
CONFIG_AT91_LED
CONFIG_AT91_WANTS_COMMON_PHY
-CONFIG_ATAPI
CONFIG_ATMEL_LCD
CONFIG_ATMEL_LCD_BGR555
CONFIG_ATMEL_LCD_RGB565
CONFIG_ICACHE
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_PREINIT
-CONFIG_IDE_RESET
CONFIG_IMX
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IMX_HDMI
CONFIG_RAMDISK_BOOT
CONFIG_RD_LVL
CONFIG_RED_LED
-CONFIG_REMAKE_ELF
CONFIG_RESERVED_01_BASE
CONFIG_RESERVED_02_BASE
CONFIG_RESERVED_03_BASE
CONFIG_SATA1
CONFIG_SATA2
CONFIG_SCIF_A
-CONFIG_SCSI_AHCI_PLAT
CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
CONFIG_SDCARD
CONFIG_SYS_AT91_PLLA
CONFIG_SYS_AT91_PLLB
CONFIG_SYS_AT91_SLOW_CLOCK
-CONFIG_SYS_ATA_ALT_OFFSET
-CONFIG_SYS_ATA_BASE_ADDR
-CONFIG_SYS_ATA_DATA_OFFSET
-CONFIG_SYS_ATA_IDE0_OFFSET
-CONFIG_SYS_ATA_IDE1_OFFSET
-CONFIG_SYS_ATA_REG_OFFSET
-CONFIG_SYS_ATA_STRIDE
CONFIG_SYS_AUTOLOAD
CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
CONFIG_SYS_AUXCORE_BOOTDATA
CONFIG_SYS_I2C_TCA642X_ADDR
CONFIG_SYS_I2C_TCA642X_BUS_NUM
CONFIG_SYS_ICACHE_INV
-CONFIG_SYS_IDE_MAXBUS
-CONFIG_SYS_IDE_MAXDEVICE
CONFIG_SYS_IFC_ADDR
CONFIG_SYS_IFC_CCR
CONFIG_SYS_INIT_DBCR
CONFIG_SYS_PIOC_PPUDR_VAL
CONFIG_SYS_PIOD_PDR_VAL1
CONFIG_SYS_PIOD_PPUDR_VAL
-CONFIG_SYS_PIO_MODE
CONFIG_SYS_PJPAR
CONFIG_SYS_PL310_BASE
CONFIG_SYS_PLLAR_VAL
CONFIG_SYS_RCAR_I2C1_BASE
CONFIG_SYS_RCAR_I2C2_BASE
CONFIG_SYS_RCAR_I2C3_BASE
-CONFIG_SYS_RESET_ADDR
-CONFIG_SYS_RESET_ADDRESS
CONFIG_SYS_RFD
CONFIG_SYS_RGMII1_PHY_ADDR
CONFIG_SYS_RGMII2_PHY_ADDR
CONFIG_SYS_SATA2_FLAGS
CONFIG_SYS_SATA2_OFFSET
CONFIG_SYS_SATA_FAT_BOOT_PARTITION
-CONFIG_SYS_SATA_MAX_DEVICE
CONFIG_SYS_SBFHDR_DATA_OFFSET
CONFIG_SYS_SBFHDR_SIZE
CONFIG_SYS_SCCR_SATACM
CONFIG_SYS_SCCR_TSEC2CM
CONFIG_SYS_SCCR_USBDRCM
CONFIG_SYS_SCR
-CONFIG_SYS_SCSI_MAX_DEVICE
-CONFIG_SYS_SCSI_MAX_LUN
-CONFIG_SYS_SCSI_MAX_SCSI_ID
CONFIG_SYS_SDRAM
CONFIG_SYS_SDRAM_BASE
CONFIG_SYS_SDRAM_BASE0
}
}
}
-#endif
+#else
+int fdt_check_full(const void __always_unused *fdt,
+ size_t __always_unused bufsize)
+{
+ return 0;
+}
+#endif /* #if !defined(FDT_ASSUME_MASK) || FDT_ASSUME_MASK != 0xff */
-test_conftest.py 6.43
-test_multiplexed_log.py 7.20
+test_conftest.py 6.56
+test_multiplexed_log.py 7.49
test_test.py 8.18
test_tests_test_000_version.py 7.50
test_tests_test_android_test_ab.py 6.50
test_tests_test_button.py 3.33
test_tests_test_dfu.py 5.45
test_tests_test_dm.py 9.52
-test_tests_test_efi_capsule_capsule_defs.py 5.00
-test_tests_test_efi_capsule_conftest.py 1.25
-test_tests_test_efi_capsule_test_capsule_firmware.py 3.89
-test_tests_test_efi_fit.py 7.59
+test_tests_test_efi_capsule_capsule_defs.py 6.67
+test_tests_test_efi_capsule_conftest.py 1.86
+test_tests_test_efi_capsule_test_capsule_firmware.py 4.52
+test_tests_test_efi_capsule_test_capsule_firmware_signed.py 4.85
+test_tests_test_efi_fit.py 8.16
test_tests_test_efi_loader.py 7.38
-test_tests_test_efi_secboot_conftest.py -3.84
+test_tests_test_efi_secboot_conftest.py -3.29
test_tests_test_efi_secboot_defs.py 6.67
test_tests_test_efi_secboot_test_authvar.py 8.93
-test_tests_test_efi_secboot_test_signed.py 8.38
+test_tests_test_efi_secboot_test_signed.py 8.41
test_tests_test_efi_secboot_test_signed_intca.py 8.10
test_tests_test_efi_secboot_test_unsigned.py 8.00
test_tests_test_efi_selftest.py 6.36
-test_tests_test_env.py 7.08
+test_tests_test_env.py 7.15
test_tests_test_extension.py 2.14
-test_tests_test_fit.py 6.20
-test_tests_test_fit_ecdsa.py 7.50
+test_tests_test_fit.py 6.83
+test_tests_test_fit_ecdsa.py 7.94
test_tests_test_fit_hashes.py 7.70
test_tests_test_fpga.py 1.81
-test_tests_test_fs_conftest.py 4.62
+test_tests_test_fs_conftest.py 5.13
test_tests_test_fs_fstest_defs.py 8.33
test_tests_test_fs_fstest_helpers.py 4.29
-test_tests_test_fs_test_basic.py 0.40
-test_tests_test_fs_test_ext.py -0.25
+test_tests_test_fs_test_basic.py 0.60
+test_tests_test_fs_test_ext.py 0.00
test_tests_test_fs_test_fs_cmd.py 8.00
test_tests_test_fs_test_mkdir.py 1.96
-test_tests_test_fs_test_squashfs_sqfs_common.py 8.12
-test_tests_test_fs_test_squashfs_test_sqfs_load.py 7.12
+test_tests_test_fs_test_squashfs_sqfs_common.py 8.41
+test_tests_test_fs_test_squashfs_test_sqfs_load.py 7.46
test_tests_test_fs_test_squashfs_test_sqfs_ls.py 8.00
-test_tests_test_fs_test_symlink.py 0.82
-test_tests_test_fs_test_unlink.py 2.22
+test_tests_test_fs_test_symlink.py 1.22
+test_tests_test_fs_test_unlink.py 2.78
test_tests_test_gpio.py 6.09
test_tests_test_gpt.py 7.67
test_tests_test_handoff.py 5.00
test_tests_test_qfw.py 8.75
test_tests_test_sandbox_exit.py 6.50
test_tests_test_scp03.py 3.33
-test_tests_test_sf.py 7.02
+test_tests_test_sf.py 7.13
test_tests_test_shell_basics.py 9.58
test_tests_test_sleep.py 7.78
test_tests_test_spl.py 2.22
test_tests_test_ums.py 6.32
test_tests_test_unknown_cmd.py 5.00
test_tests_test_ut.py 7.06
-test_tests_test_vboot.py 6.00
+test_tests_test_vboot.py 6.01
test_tests_vboot_evil.py 8.95
test_tests_vboot_forge.py 9.22
-test_u_boot_console_base.py 6.80
-test_u_boot_console_exec_attach.py 8.85
-test_u_boot_console_sandbox.py 7.22
-test_u_boot_spawn.py 7.39
-test_u_boot_utils.py 6.25
+test_u_boot_console_base.py 7.08
+test_u_boot_console_exec_attach.py 9.23
+test_u_boot_console_sandbox.py 8.06
+test_u_boot_spawn.py 7.65
+test_u_boot_utils.py 6.94
tools_binman_bintool 8.59
tools_binman_bintool_test 9.87
tools_binman_btool__testing 6.09
-tools_binman_btool_cbfstool 7.39
+tools_binman_btool_cbfstool 7.83
tools_binman_btool_fiptool 7.62
-tools_binman_btool_futility 6.96
-tools_binman_btool_ifwitool 3.33
-tools_binman_btool_lz4 5.93
-tools_binman_btool_lzma_alone 6.67
-tools_binman_btool_mkimage 6.79
-tools_binman_cbfs_util 7.77
-tools_binman_cbfs_util_test 9.27
+tools_binman_btool_futility 7.39
+tools_binman_btool_ifwitool 3.81
+tools_binman_btool_lz4 6.30
+tools_binman_btool_lzma_alone 6.97
+tools_binman_btool_mkimage 7.86
+tools_binman_cbfs_util 8.46
+tools_binman_cbfs_util_test 9.38
tools_binman_cmdline 9.03
-tools_binman_comp_util 6.25
-tools_binman_control 4.60
-tools_binman_elf 6.42
-tools_binman_elf_test 5.41
-tools_binman_entry 2.48
+tools_binman_comp_util 6.88
+tools_binman_control 5.01
+tools_binman_elf 6.98
+tools_binman_elf_test 5.62
+tools_binman_entry 3.55
tools_binman_entry_test 5.34
tools_binman_etype__testing 0.83
tools_binman_etype_atf_bl31 -6.00
tools_binman_etype_blob_named_by_arg -7.78
tools_binman_etype_blob_phase -5.00
tools_binman_etype_cbfs -1.44
-tools_binman_etype_collection 2.33
+tools_binman_etype_collection 2.67
tools_binman_etype_cros_ec_rw -6.00
-tools_binman_etype_fdtmap -3.61
+tools_binman_etype_fdtmap -3.28
tools_binman_etype_files -7.43
tools_binman_etype_fill -6.43
-tools_binman_etype_fit 5.18
-tools_binman_etype_fmap -0.59
+tools_binman_etype_fit 6.31
+tools_binman_etype_fmap -0.29
tools_binman_etype_gbb 0.83
-tools_binman_etype_image_header 5.58
+tools_binman_etype_image_header 5.77
tools_binman_etype_intel_cmc -12.50
tools_binman_etype_intel_descriptor 4.62
tools_binman_etype_intel_fit 0.00
tools_binman_etype_intel_refcode -10.00
tools_binman_etype_intel_vbt -12.50
tools_binman_etype_intel_vga -12.50
-tools_binman_etype_mkimage 2.31
+tools_binman_etype_mkimage 1.47
tools_binman_etype_opensbi -6.00
tools_binman_etype_powerpc_mpc85xx_bootpg_resetvec -10.00
tools_binman_etype_scp -6.00
-tools_binman_etype_section 4.12
+tools_binman_etype_section 4.57
+tools_binman_etype_tee_os -6.00
tools_binman_etype_text -0.48
tools_binman_etype_u_boot -15.71
tools_binman_etype_u_boot_dtb -12.22
tools_binman_etype_u_boot_tpl_with_ucode_ptr -20.83
tools_binman_etype_u_boot_ucode 1.52
tools_binman_etype_u_boot_with_ucode_ptr -0.71
-tools_binman_etype_vblock 0.00
+tools_binman_etype_vblock 0.27
tools_binman_etype_x86_reset16 -15.71
tools_binman_etype_x86_reset16_spl -15.71
tools_binman_etype_x86_reset16_tpl -15.71
tools_binman_fdt_test 3.23
tools_binman_fip_util 9.85
tools_binman_fip_util_test 10.00
-tools_binman_fmap_util 6.67
-tools_binman_ftest 7.39
-tools_binman_image 6.48
+tools_binman_fmap_util 6.88
+tools_binman_ftest 7.46
+tools_binman_image 7.12
tools_binman_image_test 4.48
-tools_binman_main 4.29
+tools_binman_main 4.86
tools_binman_setup 5.00
-tools_binman_state 3.43
-tools_buildman_board 7.11
-tools_buildman_bsettings 0.98
-tools_buildman_builder 6.55
-tools_buildman_builderthread 7.35
-tools_buildman_cmdline 8.85
-tools_buildman_control 7.04
-tools_buildman_func_test 6.38
-tools_buildman_kconfiglib 7.48
-tools_buildman_main 1.43
-tools_buildman_test 6.10
-tools_buildman_toolchain 5.62
-tools_concurrencytest_concurrencytest 6.77
-tools_dtoc_dtb_platdata 7.82
-tools_dtoc_fdt 3.47
-tools_dtoc_fdt_util 5.00
-tools_dtoc_main 7.33
+tools_binman_state 4.15
+tools_buildman_board 7.82
+tools_buildman_bsettings 1.71
+tools_buildman_builder 6.92
+tools_buildman_builderthread 7.48
+tools_buildman_cfgutil 7.83
+tools_buildman_cmdline 8.89
+tools_buildman_control 8.12
+tools_buildman_func_test 7.18
+tools_buildman_kconfiglib 7.49
+tools_buildman_main -1.11
+tools_buildman_test 6.56
+tools_buildman_toolchain 6.44
+tools_concurrencytest_concurrencytest 7.26
+tools_dtoc_dtb_platdata 7.90
+tools_dtoc_fdt 4.46
+tools_dtoc_fdt_util 6.80
+tools_dtoc_main 7.78
tools_dtoc_setup 5.00
-tools_dtoc_src_scan 8.75
-tools_dtoc_test_dtoc 8.54
-tools_dtoc_test_fdt 6.92
+tools_dtoc_src_scan 8.91
+tools_dtoc_test_dtoc 8.56
+tools_dtoc_test_fdt 6.88
tools_dtoc_test_src_scan 9.43
tools_efivar 6.71
-tools_endian-swap 8.93
-tools_genboardscfg 7.27
-tools_microcode-tool 7.19
-tools_moveconfig 8.11
+tools_endian-swap 9.29
+tools_genboardscfg 7.95
+tools_microcode-tool 7.25
+tools_moveconfig 8.34
tools_patman___init__ 0.00
-tools_patman_checkpatch 7.61
-tools_patman_command 4.23
-tools_patman_commit 2.75
+tools_patman_checkpatch 8.48
+tools_patman_command 5.51
+tools_patman_commit 4.50
tools_patman_control 8.14
-tools_patman_cros_subprocess 7.41
-tools_patman_func_test 7.87
-tools_patman_get_maintainer 4.71
-tools_patman_gitutil 4.58
-tools_patman_main 8.23
-tools_patman_patchstream 9.04
-tools_patman_project 3.33
-tools_patman_series 5.95
-tools_patman_settings 5.63
+tools_patman_cros_subprocess 7.76
+tools_patman_func_test 8.51
+tools_patman_get_maintainer 7.06
+tools_patman_gitutil 6.65
+tools_patman_main 7.90
+tools_patman_patchstream 9.11
+tools_patman_project 7.78
+tools_patman_series 6.16
+tools_patman_settings 5.89
tools_patman_setup 5.00
-tools_patman_status 8.43
-tools_patman_terminal 6.29
-tools_patman_test_checkpatch 6.81
-tools_patman_test_util 6.51
-tools_patman_tools 3.98
-tools_patman_tout 2.97
-tools_rkmux 6.76
+tools_patman_status 8.62
+tools_patman_terminal 8.00
+tools_patman_test_checkpatch 7.75
+tools_patman_test_util 7.64
+tools_patman_tools 5.68
+tools_patman_tout 5.31
+tools_rkmux 6.90
tools_rmboard 7.76
tools_zynqmp_pm_cfg_obj_convert 6.67
# We are interested only in CONFIG_LOCALVERSION and
# CONFIG_LOCALVERSION_AUTO, so extract these in a safe
# way (i.e. w/o sourcing auto.conf)
- CONFIG_LOCALVERSION=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION=/ {print $2}'`
- CONFIG_LOCALVERSION_AUTO=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION_AUTO=/ {print $2}'`
+ # xargs echo removes quotes
+ CONFIG_LOCALVERSION=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION=/ {print $2}' | xargs echo`
+ CONFIG_LOCALVERSION_AUTO=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION_AUTO=/ {print $2}' | xargs echo`
else
echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2
exit 1
continue
exception = None
- for l in open(el.path).readlines():
+ for l in open(el.path, encoding="utf-8").readlines():
if l.startswith('Valid-License-Identifier:'):
lid = l.split(':')[1].strip().upper()
if lid in spdx.licenses:
snprintf(str, 0, "testing none");
ut_asserteq('x', *str);
- sprintf(big_str, "_%ls_", L"foo");
+ sprintf(big_str, "_%ls_", u"foo");
ut_assertok(strcmp("_foo_", big_str));
/* Test the banner function */
char buf[10] = "xxxxxxxxx";
int ret;
+ ret = snprintf(buf, 5, "%d", 12345678);
+ ut_asserteq_str("1234", buf);
+ ut_asserteq(8, ret);
+ ret = snprintf(buf, 5, "0x%x", 0x1234);
+ ut_asserteq_str("0x12", buf);
+ ut_asserteq(6, ret);
+ ret = snprintf(buf, 5, "0x%08x", 0x1234);
+ ut_asserteq_str("0x00", buf);
+ ut_asserteq(10, ret);
+ ret = snprintf(buf, 3, "%s", "abc");
+ ut_asserteq_str("ab", buf);
+ ut_asserteq(3, ret);
ret = snprintf(buf, 4, "%s:%s", "abc", "def");
ut_asserteq(0, buf[3]);
ut_asserteq(7, ret);
# Directories
CAPSULE_DATA_DIR = '/EFI/CapsuleTestData'
CAPSULE_INSTALL_DIR = '/EFI/UpdateCapsule'
+
+# v1.5.1 or earlier of efitools has a bug in sha256 calculation, and
+# you need build a newer version on your own.
+# The path must terminate with '/' if it is not null.
+EFITOOLS_PATH = ''
from capsule_defs import *
#
-# Fixture for UEFI secure boot test
+# Fixture for UEFI capsule test
#
-
@pytest.fixture(scope='session')
def efi_capsule_data(request, u_boot_config):
- """Set up a file system to be used in UEFI capsule test.
+ """Set up a file system to be used in UEFI capsule and
+ authentication test.
Args:
request: Pytest request object.
check_call('mkdir -p %s' % data_dir, shell=True)
check_call('mkdir -p %s' % install_dir, shell=True)
+ capsule_auth_enabled = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_authenticate')
+ if capsule_auth_enabled:
+ # Create private key (SIGNER.key) and certificate (SIGNER.crt)
+ check_call('cd %s; '
+ 'openssl req -x509 -sha256 -newkey rsa:2048 '
+ '-subj /CN=TEST_SIGNER/ -keyout SIGNER.key '
+ '-out SIGNER.crt -nodes -days 365'
+ % data_dir, shell=True)
+ check_call('cd %s; %scert-to-efi-sig-list SIGNER.crt SIGNER.esl'
+ % (data_dir, EFITOOLS_PATH), shell=True)
+
+ # Update dtb adding capsule certificate
+ check_call('cd %s; '
+ 'cp %s/test/py/tests/test_efi_capsule/signature.dts .'
+ % (data_dir, u_boot_config.source_dir), shell=True)
+ check_call('cd %s; '
+ 'dtc -@ -I dts -O dtb -o signature.dtbo signature.dts; '
+ 'fdtoverlay -i %s/arch/sandbox/dts/test.dtb '
+ '-o test_sig.dtb signature.dtbo'
+ % (data_dir, u_boot_config.build_dir), shell=True)
+
+ # Create *malicious* private key (SIGNER2.key) and certificate
+ # (SIGNER2.crt)
+ check_call('cd %s; '
+ 'openssl req -x509 -sha256 -newkey rsa:2048 '
+ '-subj /CN=TEST_SIGNER/ -keyout SIGNER2.key '
+ '-out SIGNER2.crt -nodes -days 365'
+ % data_dir, shell=True)
+
# Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old -> u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir,
check_call('cd %s; %s/tools/mkimage -f uboot_bin_env.its uboot_bin_env.itb' %
(data_dir, u_boot_config.build_dir),
shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --fit uboot_bin_env.itb --index 1 Test01' %
+ check_call('cd %s; %s/tools/mkeficapsule --index 1 --fit uboot_bin_env.itb Test01' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+ check_call('cd %s; %s/tools/mkeficapsule --index 1 --raw u-boot.bin.new Test02' %
(data_dir, u_boot_config.build_dir),
shell=True)
- check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new --index 1 Test02' %
+ check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid E2BB9C06-70E9-4B14-97A3-5A7913176E3F u-boot.bin.new Test03' %
(data_dir, u_boot_config.build_dir),
shell=True)
+ if capsule_auth_enabled:
+ # firmware signed with proper key
+ check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+ '--private-key SIGNER.key --certificate SIGNER.crt '
+ '--raw u-boot.bin.new Test11'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
+ # firmware signed with *mal* key
+ check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+ '--private-key SIGNER2.key '
+ '--certificate SIGNER2.crt '
+ '--raw u-boot.bin.new Test12'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
# Create a disk image with EFI system partition
check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s' %
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ signature {
+ capsule-key = /incbin/("SIGNER.esl");
+ };
+};
'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
assert 'Test01' in ''.join(output)
- # reboot
- u_boot_console.restart_uboot()
-
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
+ capsule_auth = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_authenticate')
+
+ # reboot
+ u_boot_console.restart_uboot(expect_reset = capsule_early)
+
with u_boot_console.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
# make sure that dfu_alt_info exists even persistent variables
# need to run uefi command to initiate capsule handling
output = u_boot_console.run_command(
- 'env print -e Capsule0000')
+ 'env print -e Capsule0000', wait_for_reboot = True)
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'sf probe 0:0',
'sf read 4000000 100000 10',
'md.b 4000000 10'])
- assert 'u-boot:New' in ''.join(output)
+ if capsule_auth:
+ assert 'u-boot:Old' in ''.join(output)
+ else:
+ assert 'u-boot:New' in ''.join(output)
output = u_boot_console.run_command_list([
'sf read 4000000 150000 10',
'md.b 4000000 10'])
- assert 'u-boot-env:New' in ''.join(output)
+ if capsule_auth:
+ assert 'u-boot-env:Old' in ''.join(output)
+ else:
+ assert 'u-boot-env:New' in ''.join(output)
def test_efi_capsule_fw3(
self, u_boot_config, u_boot_console, efi_capsule_data):
'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
assert 'Test02' in ''.join(output)
- # reboot
- u_boot_console.restart_uboot()
-
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
+ capsule_auth = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_authenticate')
+
+ # reboot
+ u_boot_console.restart_uboot(expect_reset = capsule_early)
+
with u_boot_console.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
# make sure that dfu_alt_info exists even persistent variables
# need to run uefi command to initiate capsule handling
output = u_boot_console.run_command(
- 'env print -e Capsule0000')
+ 'env print -e Capsule0000', wait_for_reboot = True)
- output = u_boot_console.run_command_list(['efidebug capsule esrt'])
+ # make sure the dfu_alt_info exists because it is required for making ESRT.
+ output = u_boot_console.run_command_list([
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'efidebug capsule esrt'])
# ensure that EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID is in the ESRT.
assert 'AE13FF2D-9AD4-4E25-9AC8-6D80B3B22147' in ''.join(output)
'sf probe 0:0',
'sf read 4000000 100000 10',
'md.b 4000000 10'])
- assert 'u-boot:New' in ''.join(output)
+ if capsule_auth:
+ assert 'u-boot:Old' in ''.join(output)
+ else:
+ assert 'u-boot:New' in ''.join(output)
+
+ def test_efi_capsule_fw4(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """
+ Test Case 4 - Test "--guid" option of mkeficapsule
+ The test scenario is the same as Case 3.
+ """
+ disk_img = efi_capsule_data
+ with u_boot_console.log.section('Test Case 4-a, before reboot'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
+ 'efidebug boot order 1',
+ 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'env save'])
+
+ # initialize content
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR,
+ 'sf write 4000000 100000 10',
+ 'sf read 5000000 100000 10',
+ 'md.b 5000000 10'])
+ assert 'Old' in ''.join(output)
+
+ # place a capsule file
+ output = u_boot_console.run_command_list([
+ 'fatload host 0:1 4000000 %s/Test03' % CAPSULE_DATA_DIR,
+ 'fatwrite host 0:1 4000000 %s/Test03 $filesize' % CAPSULE_INSTALL_DIR,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test03' in ''.join(output)
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ capsule_auth = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_authenticate')
+
+ # reboot
+ u_boot_console.restart_uboot(expect_reset = capsule_early)
+
+ with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ if not capsule_early:
+ # make sure that dfu_alt_info exists even persistent variables
+ # are not available.
+ output = u_boot_console.run_command_list([
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test03' in ''.join(output)
+
+ # need to run uefi command to initiate capsule handling
+ output = u_boot_console.run_command(
+ 'env print -e Capsule0000', wait_for_reboot = True)
+
+ # make sure the dfu_alt_info exists because it is required for making ESRT.
+ output = u_boot_console.run_command_list([
+ 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'efidebug capsule esrt'])
+
+ # ensure that EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID is in the ESRT.
+ assert 'E2BB9C06-70E9-4B14-97A3-5A7913176E3F' in ''.join(output)
+
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test03' not in ''.join(output)
+
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'sf read 4000000 100000 10',
+ 'md.b 4000000 10'])
+ if capsule_auth:
+ assert 'u-boot:Old' in ''.join(output)
+ else:
+ assert 'u-boot:New' in ''.join(output)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2021, Linaro Limited
+# Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
+#
+# U-Boot UEFI: Firmware Update (Signed capsule) Test
+
+"""
+This test verifies capsule-on-disk firmware update
+with signed capsule files
+"""
+
+import pytest
+from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('efi_capsule_firmware_raw')
+@pytest.mark.buildconfigspec('efi_capsule_authenticate')
+@pytest.mark.buildconfigspec('dfu')
+@pytest.mark.buildconfigspec('dfu_sf')
+@pytest.mark.buildconfigspec('cmd_efidebug')
+@pytest.mark.buildconfigspec('cmd_fat')
+@pytest.mark.buildconfigspec('cmd_memory')
+@pytest.mark.buildconfigspec('cmd_nvedit_efi')
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.slow
+class TestEfiCapsuleFirmwareSigned(object):
+ def test_efi_capsule_auth1(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """
+ Test Case 1 - Update U-Boot on SPI Flash, raw image format
+ 0x100000-0x150000: U-Boot binary (but dummy)
+
+ If the capsule is properly signed, the authentication
+ should pass and the firmware be updated.
+ """
+ disk_img = efi_capsule_data
+ with u_boot_console.log.section('Test Case 1-a, before reboot'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
+ 'efidebug boot order 1',
+ 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
+ 'env set dfu_alt_info '
+ '"sf 0:0=u-boot-bin raw 0x100000 '
+ '0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'env save'])
+
+ # initialize content
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'fatload host 0:1 4000000 %s/u-boot.bin.old'
+ % CAPSULE_DATA_DIR,
+ 'sf write 4000000 100000 10',
+ 'sf read 5000000 100000 10',
+ 'md.b 5000000 10'])
+ assert 'Old' in ''.join(output)
+
+ # place a capsule file
+ output = u_boot_console.run_command_list([
+ 'fatload host 0:1 4000000 %s/Test11' % CAPSULE_DATA_DIR,
+ 'fatwrite host 0:1 4000000 %s/Test11 $filesize'
+ % CAPSULE_INSTALL_DIR,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test11' in ''.join(output)
+
+ # reboot
+ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
+ u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+ + '/test_sig.dtb'
+ u_boot_console.restart_uboot()
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 1-b, after reboot'):
+ if not capsule_early:
+ # make sure that dfu_alt_info exists even persistent variables
+ # are not available.
+ output = u_boot_console.run_command_list([
+ 'env set dfu_alt_info '
+ '"sf 0:0=u-boot-bin raw 0x100000 '
+ '0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test11' in ''.join(output)
+
+ # need to run uefi command to initiate capsule handling
+ output = u_boot_console.run_command(
+ 'env print -e Capsule0000')
+
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test11' not in ''.join(output)
+
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'sf read 4000000 100000 10',
+ 'md.b 4000000 10'])
+ assert 'u-boot:New' in ''.join(output)
+
+ def test_efi_capsule_auth2(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """
+ Test Case 2 - Update U-Boot on SPI Flash, raw image format
+ 0x100000-0x150000: U-Boot binary (but dummy)
+
+ If the capsule is signed but with an invalid key,
+ the authentication should fail and the firmware
+ not be updated.
+ """
+ disk_img = efi_capsule_data
+ with u_boot_console.log.section('Test Case 2-a, before reboot'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
+ 'efidebug boot order 1',
+ 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
+ 'env set dfu_alt_info '
+ '"sf 0:0=u-boot-bin raw 0x100000 '
+ '0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'env save'])
+
+ # initialize content
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'fatload host 0:1 4000000 %s/u-boot.bin.old'
+ % CAPSULE_DATA_DIR,
+ 'sf write 4000000 100000 10',
+ 'sf read 5000000 100000 10',
+ 'md.b 5000000 10'])
+ assert 'Old' in ''.join(output)
+
+ # place a capsule file
+ output = u_boot_console.run_command_list([
+ 'fatload host 0:1 4000000 %s/Test12' % CAPSULE_DATA_DIR,
+ 'fatwrite host 0:1 4000000 %s/Test12 $filesize'
+ % CAPSULE_INSTALL_DIR,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test12' in ''.join(output)
+
+ # reboot
+ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
+ u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+ + '/test_sig.dtb'
+ u_boot_console.restart_uboot()
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 2-b, after reboot'):
+ if not capsule_early:
+ # make sure that dfu_alt_info exists even persistent variables
+ # are not available.
+ output = u_boot_console.run_command_list([
+ 'env set dfu_alt_info '
+ '"sf 0:0=u-boot-bin raw 0x100000 '
+ '0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test12' in ''.join(output)
+
+ # need to run uefi command to initiate capsule handling
+ output = u_boot_console.run_command(
+ 'env print -e Capsule0000')
+
+ # deleted any way
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test12' not in ''.join(output)
+
+ # TODO: check CapsuleStatus in CapsuleXXXX
+
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'sf read 4000000 100000 10',
+ 'md.b 4000000 10'])
+ assert 'u-boot:Old' in ''.join(output)
+
+ def test_efi_capsule_auth3(
+ self, u_boot_config, u_boot_console, efi_capsule_data):
+ """
+ Test Case 3 - Update U-Boot on SPI Flash, raw image format
+ 0x100000-0x150000: U-Boot binary (but dummy)
+
+ If the capsule is not signed, the authentication
+ should fail and the firmware not be updated.
+ """
+ disk_img = efi_capsule_data
+ with u_boot_console.log.section('Test Case 3-a, before reboot'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
+ 'efidebug boot order 1',
+ 'env set -e -nv -bs -rt OsIndications =0x0000000000000004',
+ 'env set dfu_alt_info '
+ '"sf 0:0=u-boot-bin raw 0x100000 '
+ '0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'env save'])
+
+ # initialize content
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'fatload host 0:1 4000000 %s/u-boot.bin.old'
+ % CAPSULE_DATA_DIR,
+ 'sf write 4000000 100000 10',
+ 'sf read 5000000 100000 10',
+ 'md.b 5000000 10'])
+ assert 'Old' in ''.join(output)
+
+ # place a capsule file
+ output = u_boot_console.run_command_list([
+ 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR,
+ 'fatwrite host 0:1 4000000 %s/Test02 $filesize'
+ % CAPSULE_INSTALL_DIR,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test02' in ''.join(output)
+
+ # reboot
+ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
+ u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+ + '/test_sig.dtb'
+ u_boot_console.restart_uboot()
+
+ capsule_early = u_boot_config.buildconfig.get(
+ 'config_efi_capsule_on_disk_early')
+ with u_boot_console.log.section('Test Case 3-b, after reboot'):
+ if not capsule_early:
+ # make sure that dfu_alt_info exists even persistent variables
+ # are not available.
+ output = u_boot_console.run_command_list([
+ 'env set dfu_alt_info '
+ '"sf 0:0=u-boot-bin raw 0x100000 '
+ '0x50000;u-boot-env raw 0x150000 0x200000"',
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test02' in ''.join(output)
+
+ # need to run uefi command to initiate capsule handling
+ output = u_boot_console.run_command(
+ 'env print -e Capsule0000')
+
+ # deleted any way
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+ assert 'Test02' not in ''.join(output)
+
+ # TODO: check CapsuleStatus in CapsuleXXXX
+
+ output = u_boot_console.run_command_list([
+ 'sf probe 0:0',
+ 'sf read 4000000 100000 10',
+ 'md.b 4000000 10'])
+ assert 'u-boot:Old' in ''.join(output)
assert 'Hello, world!' in ''.join(output)
with u_boot_console.log.section('Test Case 5c'):
- # Test Case 5c, not rejected if one of signatures (digest of
+ # Test Case 5c, rejected if one of signatures (digest of
# certificate) is revoked
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 dbx_hash.auth',
output = u_boot_console.run_command_list([
'efidebug boot next 1',
'efidebug test bootmgr'])
- assert 'Hello, world!' in ''.join(output)
+ assert '\'HELLO\' failed' in ''.join(output)
+ assert 'efi_start_image() returned: 26' in ''.join(output)
with u_boot_console.log.section('Test Case 5d'):
# Test Case 5d, rejected if both of signatures are revoked
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
+ # Try rejection in reverse order.
+ u_boot_console.restart_uboot()
+ with u_boot_console.log.section('Test Case 5e'):
+ # Test Case 5e, authenticated even if only one of signatures
+ # is verified. Same as before but reject dbx_hash1.auth only
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % disk_img,
+ 'fatload host 0:1 4000000 db.auth',
+ 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
+ 'fatload host 0:1 4000000 KEK.auth',
+ 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
+ 'fatload host 0:1 4000000 PK.auth',
+ 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
+ 'fatload host 0:1 4000000 db1.auth',
+ 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db',
+ 'fatload host 0:1 4000000 dbx_hash1.auth',
+ 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
+ assert 'Failed to set EFI variable' not in ''.join(output)
+ output = u_boot_console.run_command_list([
+ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
+ 'efidebug boot next 1',
+ 'efidebug test bootmgr'])
+ assert '\'HELLO\' failed' in ''.join(output)
+ assert 'efi_start_image() returned: 26' in ''.join(output)
+
def test_efi_signed_image_auth6(self, u_boot_console, efi_boot_env):
"""
Test Case 6 - using digest of signed image in database
# Only run the full suite on a few combinations, since it doesn't add any more
# test coverage.
TESTDATA = [
- ['sha1-basic', 'sha1', '', None, False, True],
- ['sha1-pad', 'sha1', '', '-E -p 0x10000', False, False],
- ['sha1-pss', 'sha1', '-pss', None, False, False],
- ['sha1-pss-pad', 'sha1', '-pss', '-E -p 0x10000', False, False],
- ['sha256-basic', 'sha256', '', None, False, False],
- ['sha256-pad', 'sha256', '', '-E -p 0x10000', False, False],
- ['sha256-pss', 'sha256', '-pss', None, False, False],
- ['sha256-pss-pad', 'sha256', '-pss', '-E -p 0x10000', False, False],
- ['sha256-pss-required', 'sha256', '-pss', None, True, False],
- ['sha256-pss-pad-required', 'sha256', '-pss', '-E -p 0x10000', True, True],
- ['sha384-basic', 'sha384', '', None, False, False],
- ['sha384-pad', 'sha384', '', '-E -p 0x10000', False, False],
+ ['sha1-basic', 'sha1', '', None, False, True, False],
+ ['sha1-pad', 'sha1', '', '-E -p 0x10000', False, False, False],
+ ['sha1-pss', 'sha1', '-pss', None, False, False, False],
+ ['sha1-pss-pad', 'sha1', '-pss', '-E -p 0x10000', False, False, False],
+ ['sha256-basic', 'sha256', '', None, False, False, False],
+ ['sha256-pad', 'sha256', '', '-E -p 0x10000', False, False, False],
+ ['sha256-pss', 'sha256', '-pss', None, False, False, False],
+ ['sha256-pss-pad', 'sha256', '-pss', '-E -p 0x10000', False, False, False],
+ ['sha256-pss-required', 'sha256', '-pss', None, True, False, False],
+ ['sha256-pss-pad-required', 'sha256', '-pss', '-E -p 0x10000', True, True, False],
+ ['sha384-basic', 'sha384', '', None, False, False, False],
+ ['sha384-pad', 'sha384', '', '-E -p 0x10000', False, False, False],
+ ['algo-arg', 'algo-arg', '', '-o sha256,rsa2048', False, False, True],
]
@pytest.mark.boardspec('sandbox')
@pytest.mark.requiredtool('fdtget')
@pytest.mark.requiredtool('fdtput')
@pytest.mark.requiredtool('openssl')
-@pytest.mark.parametrize("name,sha_algo,padding,sign_options,required,full_test",
+@pytest.mark.parametrize("name,sha_algo,padding,sign_options,required,full_test,algo_arg",
TESTDATA)
def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
- full_test):
+ full_test, algo_arg):
"""Test verified boot signing with mkimage and verification with 'bootm'.
This works using sandbox only as it needs to update the device tree used
# Build the FIT, but don't sign anything yet
cons.log.action('%s: Test FIT with signed images' % sha_algo)
make_fit('sign-images-%s%s.its' % (sha_algo, padding))
- run_bootm(sha_algo, 'unsigned images', 'dev-', True)
+ run_bootm(sha_algo, 'unsigned images', ' - OK' if algo_arg else 'dev-', True)
# Sign images with our dev keys
sign_fit(sha_algo, sign_options)
cons.log.action('%s: Test FIT with signed configuration' % sha_algo)
make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
- run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True)
+ run_bootm(sha_algo, 'unsigned config', '%s+ OK' % ('sha256' if algo_arg else sha_algo), True)
# Sign images with our dev keys
sign_fit(sha_algo, sign_options)
--- /dev/null
+/dts-v1/;
+
+/ {
+ description = "Chrome OS kernel image with one or more FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ data = /incbin/("test-kernel.bin");
+ type = "kernel_noload";
+ arch = "sandbox";
+ os = "linux";
+ compression = "none";
+ load = <0x4>;
+ entry = <0x8>;
+ kernel-version = <1>;
+ hash-1 {
+ algo = "sha256";
+ };
+ };
+ fdt-1 {
+ description = "snow";
+ data = /incbin/("sandbox-kernel.dtb");
+ type = "flat_dt";
+ arch = "sandbox";
+ compression = "none";
+ fdt-version = <1>;
+ hash-1 {
+ algo = "sha256";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ signature {
+ key-name-hint = "dev";
+ sign-images = "fdt", "kernel";
+ };
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ description = "Chrome OS kernel image with one or more FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ data = /incbin/("test-kernel.bin");
+ type = "kernel_noload";
+ arch = "sandbox";
+ os = "linux";
+ compression = "none";
+ load = <0x4>;
+ entry = <0x8>;
+ kernel-version = <1>;
+ signature {
+ key-name-hint = "dev";
+ };
+ };
+ fdt-1 {
+ description = "snow";
+ data = /incbin/("sandbox-kernel.dtb");
+ type = "flat_dt";
+ arch = "sandbox";
+ compression = "none";
+ fdt-version = <1>;
+ signature {
+ key-name-hint = "dev";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ };
+ };
+};
self.p.close()
self.logstream.close()
+ def wait_for_boot_prompt(self, loop_num = 1):
+ """Wait for the boot up until command prompt. This is for internal use only.
+ """
+ try:
+ bcfg = self.config.buildconfig
+ config_spl = bcfg.get('config_spl', 'n') == 'y'
+ config_spl_serial = bcfg.get('config_spl_serial', 'n') == 'y'
+ env_spl_skipped = self.config.env.get('env__spl_skipped', False)
+ env_spl2_skipped = self.config.env.get('env__spl2_skipped', True)
+
+ while loop_num > 0:
+ loop_num -= 1
+ if config_spl and config_spl_serial and not env_spl_skipped:
+ m = self.p.expect([pattern_u_boot_spl_signon] +
+ self.bad_patterns)
+ if m != 0:
+ raise Exception('Bad pattern found on SPL console: ' +
+ self.bad_pattern_ids[m - 1])
+ if not env_spl2_skipped:
+ m = self.p.expect([pattern_u_boot_spl2_signon] +
+ self.bad_patterns)
+ if m != 0:
+ raise Exception('Bad pattern found on SPL2 console: ' +
+ self.bad_pattern_ids[m - 1])
+ m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns)
+ if m != 0:
+ raise Exception('Bad pattern found on console: ' +
+ self.bad_pattern_ids[m - 1])
+ self.u_boot_version_string = self.p.after
+ while True:
+ m = self.p.expect([self.prompt_compiled,
+ pattern_stop_autoboot_prompt] + self.bad_patterns)
+ if m == 0:
+ break
+ if m == 1:
+ self.p.send(' ')
+ continue
+ raise Exception('Bad pattern found on console: ' +
+ self.bad_pattern_ids[m - 2])
+
+ except Exception as ex:
+ self.log.error(str(ex))
+ self.cleanup_spawn()
+ raise
+ finally:
+ self.log.timestamp()
+
def run_command(self, cmd, wait_for_echo=True, send_nl=True,
- wait_for_prompt=True):
+ wait_for_prompt=True, wait_for_reboot=False):
"""Execute a command via the U-Boot console.
The command is always sent to U-Boot.
wait_for_prompt: Boolean indicating whether to wait for the
command prompt to be sent by U-Boot. This typically occurs
immediately after the command has been executed.
+ wait_for_reboot: Boolean indication whether to wait for the
+ reboot U-Boot. If this sets True, wait_for_prompt must also
+ be True.
Returns:
If wait_for_prompt == False:
self.bad_pattern_ids[m - 1])
if not wait_for_prompt:
return
- m = self.p.expect([self.prompt_compiled] + self.bad_patterns)
- if m != 0:
- self.at_prompt = False
- raise Exception('Bad pattern found on console: ' +
- self.bad_pattern_ids[m - 1])
+ if wait_for_reboot:
+ self.wait_for_boot_prompt()
+ else:
+ m = self.p.expect([self.prompt_compiled] + self.bad_patterns)
+ if m != 0:
+ self.at_prompt = False
+ raise Exception('Bad pattern found on console: ' +
+ self.bad_pattern_ids[m - 1])
self.at_prompt = True
self.at_prompt_logevt = self.logstream.logfile.cur_evt
# Only strip \r\n; space/TAB might be significant if testing
finally:
self.p.timeout = orig_timeout
- def ensure_spawned(self):
+ def ensure_spawned(self, expect_reset=False):
"""Ensure a connection to a correctly running U-Boot instance.
This may require spawning a new Sandbox process or resetting target
This is an internal function and should not be called directly.
Args:
- None.
+ expect_reset: Boolean indication whether this boot is expected
+ to be reset while the 1st boot process after main boot before
+ prompt. False by default.
Returns:
Nothing.
if not self.config.gdbserver:
self.p.timeout = 30000
self.p.logfile_read = self.logstream
- bcfg = self.config.buildconfig
- config_spl = bcfg.get('config_spl', 'n') == 'y'
- config_spl_serial = bcfg.get('config_spl_serial',
- 'n') == 'y'
- env_spl_skipped = self.config.env.get('env__spl_skipped',
- False)
- env_spl2_skipped = self.config.env.get('env__spl2_skipped',
- True)
- if config_spl and config_spl_serial and not env_spl_skipped:
- m = self.p.expect([pattern_u_boot_spl_signon] +
- self.bad_patterns)
- if m != 0:
- raise Exception('Bad pattern found on SPL console: ' +
- self.bad_pattern_ids[m - 1])
- if not env_spl2_skipped:
- m = self.p.expect([pattern_u_boot_spl2_signon] +
- self.bad_patterns)
- if m != 0:
- raise Exception('Bad pattern found on SPL2 console: ' +
- self.bad_pattern_ids[m - 1])
- m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns)
- if m != 0:
- raise Exception('Bad pattern found on console: ' +
- self.bad_pattern_ids[m - 1])
- self.u_boot_version_string = self.p.after
- while True:
- m = self.p.expect([self.prompt_compiled,
- pattern_stop_autoboot_prompt] + self.bad_patterns)
- if m == 0:
- break
- if m == 1:
- self.p.send(' ')
- continue
- raise Exception('Bad pattern found on console: ' +
- self.bad_pattern_ids[m - 2])
+ if expect_reset:
+ loop_num = 2
+ else:
+ loop_num = 1
+ self.wait_for_boot_prompt(loop_num = loop_num)
self.at_prompt = True
self.at_prompt_logevt = self.logstream.logfile.cur_evt
except Exception as ex:
pass
self.p = None
- def restart_uboot(self):
+ def restart_uboot(self, expect_reset=False):
"""Shut down and restart U-Boot."""
self.cleanup_spawn()
- self.ensure_spawned()
+ self.ensure_spawned(expect_reset)
def get_spawn_output(self):
"""Return the start-up output from U-Boot
cmd += self.sandbox_flags
return Spawn(cmd, cwd=self.config.source_dir)
- def restart_uboot_with_flags(self, flags):
+ def restart_uboot_with_flags(self, flags, expect_reset=False):
"""Run U-Boot with the given command-line flags
Args:
flags: List of flags to pass, each a string
+ expect_reset: Boolean indication whether this boot is expected
+ to be reset while the 1st boot process after main boot before
+ prompt. False by default.
Returns:
A u_boot_spawn.Spawn object that is attached to U-Boot.
try:
self.sandbox_flags = flags
- return self.restart_uboot()
+ return self.restart_uboot(expect_reset)
finally:
self.sandbox_flags = []
static int unicode_test_string16(struct unit_test_state *uts)
{
char buf[20];
+ int ret;
/* Test length and precision */
memset(buf, 0xff, sizeof(buf));
sprintf(buf, "%ls", i3);
ut_asserteq_str("i3?", buf);
+ memset(buf, 0xff, sizeof(buf));
+ ret = snprintf(buf, 4, "%ls", c1);
+ ut_asserteq(6, ret);
+ ut_asserteq_str("U-B", buf);
+
+ memset(buf, 0xff, sizeof(buf));
+ ret = snprintf(buf, 6, "%ls", c2);
+ ut_asserteq_str("kafb", buf);
+ ut_asserteq(9, ret);
+
+ memset(buf, 0xff, sizeof(buf));
+ ret = snprintf(buf, 7, "%ls", c2);
+ ut_asserteq_str("kafb\xC3\xA1", buf);
+ ut_asserteq(9, ret);
+
+ memset(buf, 0xff, sizeof(buf));
+ ret = snprintf(buf, 8, "%ls", c3);
+ ut_asserteq_str("\xE6\xBD\x9C\xE6\xB0\xB4", buf);
+ ut_asserteq(9, ret);
+
+ memset(buf, 0xff, sizeof(buf));
+ ret = snprintf(buf, 11, "%ls", c4);
+ ut_asserteq_str("\xF0\x90\x92\x8D\xF0\x90\x92\x96", buf);
+ ut_asserteq(12, ret);
+
+ memset(buf, 0xff, sizeof(buf));
+ ret = snprintf(buf, 4, "%ls", c4);
+ ut_asserteq_str("", buf);
+ ut_asserteq(12, ret);
+
return 0;
}
UNICODE_TEST(unicode_test_string16);
pos = buf;
utf8_utf16_strcpy(&pos, j1);
ut_asserteq(4, pos - buf);
- ut_assert(!unicode_test_u16_strcmp(buf, L"j1?l", SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, u"j1?l", SIZE_MAX));
pos = buf;
utf8_utf16_strcpy(&pos, j2);
ut_asserteq(4, pos - buf);
- ut_assert(!unicode_test_u16_strcmp(buf, L"j2?l", SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, u"j2?l", SIZE_MAX));
pos = buf;
utf8_utf16_strcpy(&pos, j3);
ut_asserteq(3, pos - buf);
- ut_assert(!unicode_test_u16_strcmp(buf, L"j3?", SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, u"j3?", SIZE_MAX));
return 0;
}
static int unicode_test_u16_strncmp(struct unit_test_state *uts)
{
- ut_assert(u16_strncmp(L"abc", L"abc", 3) == 0);
- ut_assert(u16_strncmp(L"abcdef", L"abcghi", 3) == 0);
- ut_assert(u16_strncmp(L"abcdef", L"abcghi", 6) < 0);
- ut_assert(u16_strncmp(L"abcghi", L"abcdef", 6) > 0);
- ut_assert(u16_strcmp(L"abc", L"abc") == 0);
- ut_assert(u16_strcmp(L"abcdef", L"deghi") < 0);
- ut_assert(u16_strcmp(L"deghi", L"abcdef") > 0);
+ ut_assert(u16_strncmp(u"abc", u"abc", 3) == 0);
+ ut_assert(u16_strncmp(u"abcdef", u"abcghi", 3) == 0);
+ ut_assert(u16_strncmp(u"abcdef", u"abcghi", 6) < 0);
+ ut_assert(u16_strncmp(u"abcghi", u"abcdef", 6) > 0);
+ ut_assert(u16_strcmp(u"abc", u"abc") == 0);
+ ut_assert(u16_strcmp(u"abcdef", u"deghi") < 0);
+ ut_assert(u16_strcmp(u"deghi", u"abcdef") > 0);
return 0;
}
UNICODE_TEST(unicode_test_u16_strncmp);
static int unicode_test_efi_create_indexed_name(struct unit_test_state *uts)
{
u16 buf[16];
- u16 const expected[] = L"Capsule0AF9";
+ u16 const expected[] = u"Capsule0AF9";
u16 *pos;
memset(buf, 0xeb, sizeof(buf));
help
Enable SHA512 support in the tools builds
+config TOOLS_MKEFICAPSULE
+ bool "Build efimkcapsule command"
+ default y if EFI_CAPSULE_ON_DISK
+ help
+ This command allows users to create a UEFI capsule file and,
+ optionally sign that file. If you want to enable UEFI capsule
+ update feature on your target, you certainly need this.
+
endmenu
hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler
HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
-mkeficapsule-objs := mkeficapsule.o $(LIBFDT_OBJS)
-hostprogs-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += mkeficapsule
+HOSTLDLIBS_mkeficapsule += -lgnutls -luuid
+hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
Binman is intended to replace the last step. The U-Boot build system builds
u-boot.bin and sunxi-spl.bin. Binman can then take over creation of
-sunxi-spl.bin (by calling mksunxiboot, or hopefully one day mkimage). In any
-case, it would then create the image from the component parts.
+sunxi-spl.bin by calling mksunxiboot or mkimage. In any case, it would then
+create the image from the component parts.
This simplifies the U-Boot Makefile somewhat, since various pieces of logic
can be replaced by a call to binman.
difficult. This avoids any use of ThreadPoolExecutor.
+Collecting data for an entry type
+---------------------------------
+
+Some entry types deal with data obtained from others. For example,
+`Entry_mkimage` calls the `mkimage` tool with data from its subnodes::
+
+ mkimage {
+ args = "-n test -T script";
+
+ u-boot-spl {
+ };
+
+ u-boot {
+ };
+ };
+
+This shows mkimage being passed a file consisting of SPL and U-Boot proper. It
+is create by calling `Entry.collect_contents_to_file()`. Note that in this case,
+the data is passed to mkimage for processing but does not appear separately in
+the image. It may not appear at all, depending on what mkimage does. The
+contents of the `mkimage` entry are entirely dependent on the processing done
+by the entry, with the provided subnodes (`u-boot-spl` and `u-boot`) simply
+providing the input data for that processing.
+
+Note that `Entry.collect_contents_to_file()` simply concatenates the data from
+the different entries together, with no control over alignment, etc. Another
+approach is to subclass `Entry_section` so that those features become available,
+such as `size` and `pad-byte`. Then the contents of the entry can be obtained by
+calling `BuildSectionData()`.
+
+There are other ways to obtain data also, depending on the situation. If the
+entry type is simply signing data which exists elsewhere in the image, then
+you can use `Entry_collection` as a base class. It lets you use a property
+called `content` which lists the entries containing data to be processed. This
+is used by `Entry_vblock`, for example::
+
+ u_boot: u-boot {
+ };
+ vblock {
+ content = <&u_boot &dtb>;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <1>;
+ };
+
+ dtb: u-boot-dtb {
+ };
+
+which shows an image containing `u-boot` and `u-boot-dtb`, with the `vblock`
+image collecting their contents to produce input for its signing process,
+without affecting those entries, which still appear in the final image
+untouched.
+
+Another example is where an entry type needs several independent pieces of input
+to function. For example, `Entry_fip` allows a number of different binary blobs
+to be placed in their own individual places in a custom data structure in the
+output image. To make that work you can add subnodes for each of them and call
+`Entry.Create()` on each subnode, as `Entry_fip` does. Then the data for each
+blob can come from any suitable place, such as an `Entry_u_boot` or an
+`Entry_blob` or anything else::
+
+ atf-fip {
+ fip-hdr-flags = /bits/ 64 <0x123>;
+ soc-fw {
+ fip-flags = /bits/ 64 <0x123456789abcdef>;
+ filename = "bl31.bin";
+ };
+
+ u-boot {
+ fip-uuid = [fc 65 13 92 4a 5b 11 ec
+ 94 35 ff 2d 1c fc 79 9c];
+ };
+ };
+
+The `soc-fw` node is a `blob-ext` (i.e. it reads in a named binary file) whereas
+`u-boot` is a normal entry type. This works because `Entry_fip` selects the
+`blob-ext` entry type if the node name (here `soc-fw`) is recognised as being
+a known blob type.
+
+When adding new entry types you are encouraged to use subnodes to provide the
+data for processing, unless the `content` approach is more suitable. Ad-hoc
+properties and other methods of obtaining data are discouraged, since it adds to
+confusion for users.
+
History / Credits
-----------------
- Detect invalid properties in nodes
- Sort the fdtmap by offset
- Output temporary files to a different directory
+- Rationalise the fdt, fdt_util and pylibfdt modules which currently have some
+ overlapping and confusing functionality
+- Update the fdt library to use a better format for Prop.value (the current one
+ is useful for dtoc but not much else)
+- Figure out how to make Fdt support changing the node order, so that
+ Node.AddSubnode() can support adding a node before another, existing node.
+ Perhaps it should completely regenerate the flat tree?
+
--
Simon Glass <sjg@chromium.org>
res = self.fetch(meth)
except urllib.error.URLError as uerr:
message = uerr.reason
- print(col.Color(col.RED, f'- {message}'))
+ print(col.build(col.RED, f'- {message}'))
except ValueError as exc:
print(f'Exception: {exc}')
if skip_present and self.is_present():
return PRESENT
- print(col.Color(col.YELLOW, 'Fetch: %s' % self.name))
+ print(col.build(col.YELLOW, 'Fetch: %s' % self.name))
if method == FETCH_ANY:
for try_method in range(1, FETCH_COUNT):
print(f'- trying method: {FETCH_NAMES[try_method]}')
True on success, False on failure
"""
def show_status(color, prompt, names):
- print(col.Color(
+ print(col.build(
color, f'{prompt}:%s{len(names):2}: %s' %
(' ' * (16 - len(prompt)), ' '.join(names))))
name_list = Bintool.get_tool_list()
if names_to_fetch[0] == 'missing':
skip_present = True
- print(col.Color(col.YELLOW,
+ print(col.build(col.YELLOW,
'Fetching tools: %s' % ' '.join(name_list)))
status = collections.defaultdict(list)
for name in name_list:
name = os.path.expanduser(self.name) # Expand paths containing ~
all_args = (name,) + args
env = tools.get_env_with_path()
- tout.Detail(f"bintool: {' '.join(all_args)}")
- result = command.RunPipe(
+ tout.detail(f"bintool: {' '.join(all_args)}")
+ result = command.run_pipe(
[all_args], capture=True, capture_stderr=True, env=env,
raise_on_error=False, binary=binary)
# try to run it (as above) since RunPipe() allows faking the tool's
# output
if not any([result.stdout, result.stderr, tools.tool_find(name)]):
- tout.Info(f"bintool '{name}' not found")
+ tout.info(f"bintool '{name}' not found")
return None
if raise_on_error:
- tout.Info(f"bintool '{name}' failed")
+ tout.info(f"bintool '{name}' failed")
raise ValueError("Error %d running '%s': %s" %
(result.return_code, ' '.join(all_args),
result.stderr or result.stdout))
if result.stdout:
- tout.Debug(result.stdout)
+ tout.debug(result.stdout)
if result.stderr:
- tout.Debug(result.stderr)
+ tout.debug(result.stderr)
return result
def run_cmd(self, *args, binary=False):
"""
tmpdir = tempfile.mkdtemp(prefix='binmanf.')
print(f"- clone git repo '{git_repo}' to '{tmpdir}'")
- tools.Run('git', 'clone', '--depth', '1', git_repo, tmpdir)
+ tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir)
print(f"- build target '{make_target}'")
- tools.Run('make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
+ tools.run('make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
make_target)
fname = os.path.join(tmpdir, bintool_path)
if not os.path.exists(fname):
str: Filename of fetched file to copy to a suitable directory
str: Name of temp directory to remove, or None
"""
- fname, tmpdir = tools.Download(url)
- tools.Run('chmod', 'a+x', fname)
+ fname, tmpdir = tools.download(url)
+ tools.run('chmod', 'a+x', fname)
return fname, tmpdir
@classmethod
"""
args = ['sudo', 'apt', 'install', '-y', package]
print('- %s' % ' '.join(args))
- tools.Run(*args)
+ tools.run(*args)
return True
@staticmethod
Args:
fake_download (function): Function to call instead of
- tools.Download()
+ tools.download()
method (bintool.FETCH_...: Fetch method to use
Returns:
"""
btest = Bintool.create('_testing')
col = terminal.Color()
- with unittest.mock.patch.object(tools, 'Download',
+ with unittest.mock.patch.object(tools, 'download',
side_effect=fake_download):
with test_util.capture_sys_output() as (stdout, _):
btest.fetch_tool(method, col, False)
def test_fetch_url_err(self):
"""Test an error while fetching a tool from a URL"""
def fail_download(url):
- """Take the tools.Download() function by raising an exception"""
+ """Take the tools.download() function by raising an exception"""
raise urllib.error.URLError('my error')
stdout = self.check_fetch_url(fail_download, bintool.FETCH_ANY)
def test_fetch_method(self):
"""Test fetching using a particular method"""
def fail_download(url):
- """Take the tools.Download() function by raising an exception"""
+ """Take the tools.download() function by raising an exception"""
raise urllib.error.URLError('my error')
stdout = self.check_fetch_url(fail_download, bintool.FETCH_BIN)
def test_fetch_pass_fail(self):
"""Test fetching multiple tools with some passing and some failing"""
def handle_download(_):
- """Take the tools.Download() function by writing a file"""
+ """Take the tools.download() function by writing a file"""
if self.seq:
raise urllib.error.URLError('not found')
self.seq += 1
- tools.WriteFile(fname, expected)
+ tools.write_file(fname, expected)
return fname, dirname
expected = b'this is a test'
self.seq = 0
with unittest.mock.patch.object(bintool, 'DOWNLOAD_DESTDIR', destdir):
- with unittest.mock.patch.object(tools, 'Download',
+ with unittest.mock.patch.object(tools, 'download',
side_effect=handle_download):
with test_util.capture_sys_output() as (stdout, _):
Bintool.fetch_tools(bintool.FETCH_ANY, ['_testing'] * 2)
self.assertTrue(os.path.exists(dest_fname))
- data = tools.ReadFile(dest_fname)
+ data = tools.read_file(dest_fname)
self.assertEqual(expected, data)
lines = stdout.getvalue().splitlines()
tmpdir = cmd[2]
self.fname = os.path.join(tmpdir, 'pathname')
if write_file:
- tools.WriteFile(self.fname, b'hello')
+ tools.write_file(self.fname, b'hello')
btest = Bintool.create('_testing')
col = terminal.Color()
self.fname = None
with unittest.mock.patch.object(bintool, 'DOWNLOAD_DESTDIR',
self._indir):
- with unittest.mock.patch.object(tools, 'Run', side_effect=fake_run):
+ with unittest.mock.patch.object(tools, 'run', side_effect=fake_run):
with test_util.capture_sys_output() as (stdout, _):
btest.fetch_tool(bintool.FETCH_BUILD, col, False)
fname = os.path.join(self._indir, '_testing')
btest = Bintool.create('_testing')
btest.install = True
col = terminal.Color()
- with unittest.mock.patch.object(tools, 'Run', return_value=None):
+ with unittest.mock.patch.object(tools, 'run', return_value=None):
with test_util.capture_sys_output() as _:
result = btest.fetch_tool(bintool.FETCH_BIN, col, False)
self.assertEqual(bintool.FETCHED, result)
def test_all_bintools(self):
"""Test that all bintools can handle all available fetch types"""
def handle_download(_):
- """Take the tools.Download() function by writing a file"""
- tools.WriteFile(fname, expected)
+ """Take the tools.download() function by writing a file"""
+ tools.write_file(fname, expected)
return fname, dirname
def fake_run(*cmd):
# See Bintool.build_from_git()
tmpdir = cmd[2]
self.fname = os.path.join(tmpdir, 'pathname')
- tools.WriteFile(self.fname, b'hello')
+ tools.write_file(self.fname, b'hello')
expected = b'this is a test'
dirname = os.path.join(self._indir, 'download_dir')
os.mkdir(dirname)
fname = os.path.join(dirname, 'downloaded')
- with unittest.mock.patch.object(tools, 'Run', side_effect=fake_run):
- with unittest.mock.patch.object(tools, 'Download',
+ with unittest.mock.patch.object(tools, 'run', side_effect=fake_run):
+ with unittest.mock.patch.object(tools, 'download',
side_effect=handle_download):
with test_util.capture_sys_output() as _:
for name in Bintool.get_tool_list():
if result is not True and result is not None:
result_fname, _ = result
self.assertTrue(os.path.exists(result_fname))
- data = tools.ReadFile(result_fname)
+ data = tools.read_file(result_fname)
self.assertEqual(expected, data)
os.remove(result_fname)
bytes: Compressed data
"""
with tempfile.NamedTemporaryFile(prefix='comp.tmp',
- dir=tools.GetOutputDir()) as tmp:
- tools.WriteFile(tmp.name, indata)
+ dir=tools.get_output_dir()) as tmp:
+ tools.write_file(tmp.name, indata)
args = ['--no-frame-crc', '-B4', '-5', '-c', tmp.name]
return self.run_cmd(*args, binary=True)
bytes: Decompressed data
"""
with tempfile.NamedTemporaryFile(prefix='decomp.tmp',
- dir=tools.GetOutputDir()) as inf:
- tools.WriteFile(inf.name, indata)
+ dir=tools.get_output_dir()) as inf:
+ tools.write_file(inf.name, indata)
args = ['-cd', inf.name]
return self.run_cmd(*args, binary=True)
bytes: Compressed data
"""
with tempfile.NamedTemporaryFile(prefix='comp.tmp',
- dir=tools.GetOutputDir()) as inf:
- tools.WriteFile(inf.name, indata)
+ dir=tools.get_output_dir()) as inf:
+ tools.write_file(inf.name, indata)
with tempfile.NamedTemporaryFile(prefix='compo.otmp',
- dir=tools.GetOutputDir()) as outf:
+ dir=tools.get_output_dir()) as outf:
args = ['e', inf.name, outf.name, '-lc1', '-lp0', '-pb0', '-d8']
self.run_cmd(*args, binary=True)
- return tools.ReadFile(outf.name)
+ return tools.read_file(outf.name)
def decompress(self, indata):
"""Decompress data with lzma_alone
bytes: Decompressed data
"""
with tempfile.NamedTemporaryFile(prefix='decomp.tmp',
- dir=tools.GetOutputDir()) as inf:
- tools.WriteFile(inf.name, indata)
+ dir=tools.get_output_dir()) as inf:
+ tools.write_file(inf.name, indata)
with tempfile.NamedTemporaryFile(prefix='compo.otmp',
- dir=tools.GetOutputDir()) as outf:
+ dir=tools.get_output_dir()) as outf:
args = ['d', inf.name, outf.name]
self.run_cmd(*args, binary=True)
- return tools.ReadFile(outf.name, binary=True)
+ return tools.read_file(outf.name, binary=True)
def fetch(self, method):
"""Fetch handler for lzma_alone
Returns:
String with required padding (at least one 0x00 byte) at the end
"""
- val = tools.ToBytes(instr)
+ val = tools.to_bytes(instr)
pad_len = align_int(len(val) + 1, FILENAME_ALIGN)
- return val + tools.GetBytes(0, pad_len - len(val))
+ return val + tools.get_bytes(0, pad_len - len(val))
class CbfsFile(object):
FILE_ATTR_TAG_COMPRESSION, ATTR_COMPRESSION_LEN,
self.compress, self.memlen)
elif self.ftype == TYPE_EMPTY:
- data = tools.GetBytes(self.erase_byte, self.size)
+ data = tools.get_bytes(self.erase_byte, self.size)
else:
raise ValueError('Unknown type %#x when writing\n' % self.ftype)
if attr:
# possible.
raise ValueError("Internal error: CBFS file '%s': Requested offset %#x but current output position is %#x" %
(self.name, self.cbfs_offset, offset))
- pad = tools.GetBytes(pad_byte, pad_len)
+ pad = tools.get_bytes(pad_byte, pad_len)
hdr_len += pad_len
# This is the offset of the start of the file's data,
Usage is something like:
cbw = CbfsWriter(size)
- cbw.add_file_raw('u-boot', tools.ReadFile('u-boot.bin'))
+ cbw.add_file_raw('u-boot', tools.read_file('u-boot.bin'))
...
data, cbfs_offset = cbw.get_data_and_offset()
if fd.tell() > offset:
raise ValueError('No space for data before offset %#x (current offset %#x)' %
(offset, fd.tell()))
- fd.write(tools.GetBytes(self._erase_byte, offset - fd.tell()))
+ fd.write(tools.get_bytes(self._erase_byte, offset - fd.tell()))
def _pad_to(self, fd, offset):
"""Write out pad bytes and/or an empty file until a given offset
def setUpClass(cls):
# Create a temporary directory for test files
cls._indir = tempfile.mkdtemp(prefix='cbfs_util.')
- tools.SetInputDirs([cls._indir])
+ tools.set_input_dirs([cls._indir])
# Set up some useful data files
TestCbfs._make_input_file('u-boot.bin', U_BOOT_DATA)
# Set up a temporary output directory, used by the tools library when
# compressing files
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
cls.cbfstool = bintool.Bintool.create('cbfstool')
cls.have_cbfstool = cls.cbfstool.is_present()
if cls._indir:
shutil.rmtree(cls._indir)
cls._indir = None
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
@classmethod
def _make_input_file(cls, fname, contents):
Full pathname of file created
"""
pathname = os.path.join(cls._indir, fname)
- tools.WriteFile(pathname, contents)
+ tools.write_file(pathname, contents)
return pathname
def _check_hdr(self, data, size, offset=0, arch=cbfs_util.ARCHITECTURE_X86):
base = [(1 << 32) - size + b for b in base]
self.cbfstool.add_raw(
cbfs_fname, 'u-boot',
- tools.GetInputFilename(compress and 'compress' or 'u-boot.bin'),
+ tools.get_input_filename(compress and 'compress' or 'u-boot.bin'),
compress[0] if compress else None,
base[0] if base else None)
self.cbfstool.add_raw(
cbfs_fname, 'u-boot-dtb',
- tools.GetInputFilename(compress and 'compress' or 'u-boot.dtb'),
+ tools.get_input_filename(compress and 'compress' or 'u-boot.dtb'),
compress[1] if compress else None,
base[1] if base else None)
return cbfs_fname
"""
if not self.have_cbfstool or not self.have_lz4:
return
- expect = tools.ReadFile(cbfstool_fname)
+ expect = tools.read_file(cbfstool_fname)
if expect != data:
- tools.WriteFile('/tmp/expect', expect)
- tools.WriteFile('/tmp/actual', data)
+ tools.write_file('/tmp/expect', expect)
+ tools.write_file('/tmp/actual', data)
print('diff -y <(xxd -g1 /tmp/expect) <(xxd -g1 /tmp/actual) | colordiff')
self.fail('cbfstool produced a different result')
size = 0xb0
cbw = CbfsWriter(size)
- cbw.add_file_stage('u-boot', tools.ReadFile(elf_fname))
+ cbw.add_file_stage('u-boot', tools.read_file(elf_fname))
data = cbw.get_data()
cbfs = self._check_hdr(data, size)
return result
def _ShowBlobHelp(path, text):
- tout.Warning('\n%s:' % path)
+ tout.warning('\n%s:' % path)
for line in text.splitlines():
- tout.Warning(' %s' % line)
+ tout.warning(' %s' % line)
def _ShowHelpForMissingBlobs(missing_list):
"""Show help for each missing blob to help the user take action
raise ValueError('Must specify exactly one entry path to write with -f')
entry = image.FindEntryPath(entry_paths[0])
data = entry.ReadData(decomp, alt_format)
- tools.WriteFile(output_fname, data)
- tout.Notice("Wrote %#x bytes to file '%s'" % (len(data), output_fname))
+ tools.write_file(output_fname, data)
+ tout.notice("Wrote %#x bytes to file '%s'" % (len(data), output_fname))
return
# Otherwise we will output to a path given by the entry path of each entry.
# This means that entries will appear in subdirectories if they are part of
# a sub-section.
einfos = image.GetListEntries(entry_paths)[0]
- tout.Notice('%d entries match and will be written' % len(einfos))
+ tout.notice('%d entries match and will be written' % len(einfos))
for einfo in einfos:
entry = einfo.entry
data = entry.ReadData(decomp, alt_format)
if fname and not os.path.exists(fname):
os.makedirs(fname)
fname = os.path.join(fname, 'root')
- tout.Notice("Write entry '%s' size %x to '%s'" %
+ tout.notice("Write entry '%s' size %x to '%s'" %
(entry.GetPath(), len(data), fname))
- tools.WriteFile(fname, data)
+ tools.write_file(fname, data)
return einfos
of the entries), False to raise an exception
write_map: True to write a map file
"""
- tout.Info('Processing image')
+ tout.info('Processing image')
ProcessImage(image, update_fdt=True, write_map=write_map,
get_contents=False, allow_resize=allow_resize)
def WriteEntryToImage(image, entry, data, do_compress=True, allow_resize=True,
write_map=False):
BeforeReplace(image, allow_resize)
- tout.Info('Writing data to %s' % entry.GetPath())
+ tout.info('Writing data to %s' % entry.GetPath())
ReplaceOneEntry(image, entry, data, do_compress, allow_resize)
AfterReplace(image, allow_resize=allow_resize, write_map=write_map)
Returns:
Image object that was updated
"""
- tout.Info("Write entry '%s', file '%s'" % (entry_path, image_fname))
+ tout.info("Write entry '%s', file '%s'" % (entry_path, image_fname))
image = Image.FromFile(image_fname)
entry = image.FindEntryPath(entry_path)
WriteEntryToImage(image, entry, data, do_compress=do_compress,
if len(entry_paths) != 1:
raise ValueError('Must specify exactly one entry path to write with -f')
entry = image.FindEntryPath(entry_paths[0])
- data = tools.ReadFile(input_fname)
- tout.Notice("Read %#x bytes from file '%s'" % (len(data), input_fname))
+ data = tools.read_file(input_fname)
+ tout.notice("Read %#x bytes from file '%s'" % (len(data), input_fname))
WriteEntryToImage(image, entry, data, do_compress=do_compress,
allow_resize=allow_resize, write_map=write_map)
return
# This means that files must appear in subdirectories if they are part of
# a sub-section.
einfos = image.GetListEntries(entry_paths)[0]
- tout.Notice("Replacing %d matching entries in image '%s'" %
+ tout.notice("Replacing %d matching entries in image '%s'" %
(len(einfos), image_fname))
BeforeReplace(image, allow_resize)
for einfo in einfos:
entry = einfo.entry
if entry.GetEntries():
- tout.Info("Skipping section entry '%s'" % entry.GetPath())
+ tout.info("Skipping section entry '%s'" % entry.GetPath())
continue
path = entry.GetPath()[1:]
fname = os.path.join(indir, path)
if os.path.exists(fname):
- tout.Notice("Write entry '%s' from file '%s'" %
+ tout.notice("Write entry '%s' from file '%s'" %
(entry.GetPath(), fname))
- data = tools.ReadFile(fname)
+ data = tools.read_file(fname)
ReplaceOneEntry(image, entry, data, do_compress, allow_resize)
else:
- tout.Warning("Skipping entry '%s' from missing file '%s'" %
+ tout.warning("Skipping entry '%s' from missing file '%s'" %
(entry.GetPath(), fname))
AfterReplace(image, allow_resize=allow_resize, write_map=write_map)
# output into a file in our output directly. Then scan it for use
# in binman.
dtb_fname = fdt_util.EnsureCompiled(dtb_fname)
- fname = tools.GetOutputFilename('u-boot.dtb.out')
- tools.WriteFile(fname, tools.ReadFile(dtb_fname))
+ fname = tools.get_output_filename('u-boot.dtb.out')
+ tools.write_file(fname, tools.read_file(dtb_fname))
dtb = fdt.FdtScan(fname)
node = _FindBinmanNode(dtb)
else:
skip.append(name)
images = new_images
- tout.Notice('Skipping images: %s' % ', '.join(skip))
+ tout.notice('Skipping images: %s' % ', '.join(skip))
state.Prepare(images, dtb)
if sizes_ok:
break
image.ResetForPack()
- tout.Info('Pack completed after %d pass(es)' % (pack_pass + 1))
+ tout.info('Pack completed after %d pass(es)' % (pack_pass + 1))
if not sizes_ok:
image.Raise('Entries changed size after packing (tried %s passes)' %
passes)
missing_list = []
image.CheckMissing(missing_list)
if missing_list:
- tout.Warning("Image '%s' is missing external blobs and is non-functional: %s" %
+ tout.warning("Image '%s' is missing external blobs and is non-functional: %s" %
(image.name, ' '.join([e.name for e in missing_list])))
_ShowHelpForMissingBlobs(missing_list)
faked_list = []
image.CheckFakedBlobs(faked_list)
if faked_list:
- tout.Warning(
+ tout.warning(
"Image '%s' has faked external blobs and is non-functional: %s" %
(image.name, ' '.join([os.path.basename(e.GetDefaultFilename())
for e in faked_list])))
missing_bintool_list = []
image.check_missing_bintools(missing_bintool_list)
if missing_bintool_list:
- tout.Warning(
+ tout.warning(
"Image '%s' has missing bintools and is non-functional: %s" %
(image.name, ' '.join([os.path.basename(bintool.name)
for bintool in missing_bintool_list])))
global state
if args.full_help:
- tools.PrintFullHelp(
+ tools.print_full_help(
os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README.rst')
)
return 0
if args.cmd in ['ls', 'extract', 'replace', 'tool']:
try:
- tout.Init(args.verbosity)
- tools.PrepareOutputDir(None)
+ tout.init(args.verbosity)
+ tools.prepare_output_dir(None)
if args.cmd == 'ls':
ListEntries(args.image, args.paths)
allow_resize=not args.fix_size, write_map=args.map)
if args.cmd == 'tool':
- tools.SetToolPaths(args.toolpath)
+ tools.set_tool_paths(args.toolpath)
if args.list:
bintool.Bintool.list_all()
elif args.fetch:
except:
raise
finally:
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
return 0
elf_params = None
args.indir.append(board_pathname)
try:
- tout.Init(args.verbosity)
+ tout.init(args.verbosity)
elf.debug = args.debug
cbfs_util.VERBOSE = args.verbosity > 2
state.use_fake_dtb = args.fake_dtb
# runtime.
use_expanded = not args.no_expanded
try:
- tools.SetInputDirs(args.indir)
- tools.PrepareOutputDir(args.outdir, args.preserve)
- tools.SetToolPaths(args.toolpath)
+ tools.set_input_dirs(args.indir)
+ tools.prepare_output_dir(args.outdir, args.preserve)
+ tools.set_tool_paths(args.toolpath)
state.SetEntryArgs(args.entry_arg)
state.SetThreads(args.threads)
# Write the updated FDTs to our output files
for dtb_item in state.GetAllFdts():
- tools.WriteFile(dtb_item._fname, dtb_item.GetContents())
+ tools.write_file(dtb_item._fname, dtb_item.GetContents())
if elf_params:
data = state.GetFdtForEtype('u-boot-dtb').GetContents()
elf.UpdateFile(*elf_params, data)
if invalid:
- tout.Warning("\nSome images are invalid")
+ tout.warning("\nSome images are invalid")
# Use this to debug the time take to pack the image
#state.TimingShow()
finally:
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
finally:
- tout.Uninit()
+ tout.uninit()
return 0
ELF_TOOLS = True
try:
from elftools.elf.elffile import ELFFile
+ from elftools.elf.elffile import ELFError
from elftools.elf.sections import SymbolTableSection
except: # pragma: no cover
ELF_TOOLS = False
key: Name of symbol
value: Hex value of symbol
"""
- stdout = tools.Run('objdump', '-t', fname)
+ stdout = tools.run('objdump', '-t', fname)
lines = stdout.splitlines()
if patterns:
re_syms = re.compile('|'.join(patterns))
entry: Entry to process
section: Section which can be used to lookup symbol values
"""
- fname = tools.GetInputFilename(elf_fname)
+ fname = tools.get_input_filename(elf_fname)
syms = GetSymbols(fname, ['image', 'binman'])
if not syms:
return
value = -1
pack_string = pack_string.lower()
value_bytes = struct.pack(pack_string, value)
- tout.Debug('%s:\n insert %s, offset %x, value %x, length %d' %
+ tout.debug('%s:\n insert %s, offset %x, value %x, length %d' %
(msg, name, offset, value, len(value_bytes)))
entry.data = (entry.data[:offset] + value_bytes +
entry.data[offset + sym.size:])
# text section at the start
# -m32: Build for 32-bit x86
# -T...: Specifies the link script, which sets the start address
- cc, args = tools.GetTargetCompileTool('cc')
+ cc, args = tools.get_target_compile_tool('cc')
args += ['-static', '-nostdlib', '-Wl,--build-id=none', '-m32', '-T',
lds_file, '-o', elf_fname, s_file]
- stdout = command.Output(cc, *args)
+ stdout = command.output(cc, *args)
shutil.rmtree(outdir)
def DecodeElf(data, location):
mem_end - data_start)
def UpdateFile(infile, outfile, start_sym, end_sym, insert):
- tout.Notice("Creating file '%s' with data length %#x (%d) between symbols '%s' and '%s'" %
+ tout.notice("Creating file '%s' with data length %#x (%d) between symbols '%s' and '%s'" %
(outfile, len(insert), len(insert), start_sym, end_sym))
syms = GetSymbolFileOffset(infile, [start_sym, end_sym])
if len(syms) != 2:
raise ValueError("Not enough space in '%s' for data length %#x (%d); size is %#x (%d)" %
(infile, len(insert), len(insert), size, size))
- data = tools.ReadFile(infile)
+ data = tools.read_file(infile)
newdata = data[:syms[start_sym].offset]
- newdata += insert + tools.GetBytes(0, size - len(insert))
+ newdata += insert + tools.get_bytes(0, size - len(insert))
newdata += data[syms[end_sym].offset:]
- tools.WriteFile(outfile, newdata)
- tout.Info('Written to offset %#x' % syms[start_sym].offset)
+ tools.write_file(outfile, newdata)
+ tout.info('Written to offset %#x' % syms[start_sym].offset)
+
+def read_segments(data):
+ """Read segments from an ELF file
+
+ Args:
+ data (bytes): Contents of file
+
+ Returns:
+ tuple:
+ list of segments, each:
+ int: Segment number (0 = first)
+ int: Start address of segment in memory
+ bytes: Contents of segment
+ int: entry address for image
+
+ Raises:
+ ValueError: elftools is not available
+ """
+ if not ELF_TOOLS:
+ raise ValueError('Python elftools package is not available')
+ with io.BytesIO(data) as inf:
+ try:
+ elf = ELFFile(inf)
+ except ELFError as err:
+ raise ValueError(err)
+ entry = elf.header['e_entry']
+ segments = []
+ for i in range(elf.num_segments()):
+ segment = elf.get_segment(i)
+ if segment['p_type'] != 'PT_LOAD' or not segment['p_memsz']:
+ skipped = 1 # To make code-coverage see this line
+ continue
+ start = segment['p_offset']
+ rend = start + segment['p_filesz']
+ segments.append((i, segment['p_paddr'], data[start:rend]))
+ return segments, entry
"""
def __init__(self, contents_size):
self.contents_size = contents_size
- self.data = tools.GetBytes(ord('a'), contents_size)
+ self.data = tools.get_bytes(ord('a'), contents_size)
def GetPath(self):
return 'entry_path'
def BuildElfTestFiles(target_dir):
"""Build ELF files used for testing in binman
- This compiles and links the test files into the specified directory. It the
- Makefile and source files in the binman test/ directory.
+ This compiles and links the test files into the specified directory. It uses
+ the Makefile and source files in the binman test/ directory.
Args:
target_dir: Directory to put the files into
if 'MAKEFLAGS' in os.environ:
del os.environ['MAKEFLAGS']
try:
- tools.Run('make', '-C', target_dir, '-f',
+ tools.run('make', '-C', target_dir, '-f',
os.path.join(testdir, 'Makefile'), 'SRC=%s/' % testdir)
except ValueError as e:
# The test system seems to suppress this in a strange way
@classmethod
def setUpClass(cls):
cls._indir = tempfile.mkdtemp(prefix='elf.')
- tools.SetInputDirs(['.'])
+ tools.set_input_dirs(['.'])
BuildElfTestFiles(cls._indir)
@classmethod
section = FakeSection(sym_value=None)
elf_fname = self.ElfTestFile('u_boot_binman_syms')
syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
- self.assertEqual(tools.GetBytes(255, 20) + tools.GetBytes(ord('a'), 4),
+ self.assertEqual(tools.get_bytes(255, 20) + tools.get_bytes(ord('a'), 4),
entry.data)
def testDebug(self):
"""Check that enabling debug in the elf module produced debug output"""
try:
- tout.Init(tout.DEBUG)
+ tout.init(tout.DEBUG)
entry = FakeEntry(20)
section = FakeSection()
elf_fname = self.ElfTestFile('u_boot_binman_syms')
syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
self.assertTrue(len(stdout.getvalue()) > 0)
finally:
- tout.Init(tout.WARNING)
+ tout.init(tout.WARNING)
def testMakeElf(self):
"""Test for the MakeElf function"""
# Make an Elf file and then convert it to a fkat binary file. This
# should produce the original data.
elf.MakeElf(elf_fname, expected_text, expected_data)
- objcopy, args = tools.GetTargetCompileTool('objcopy')
+ objcopy, args = tools.get_target_compile_tool('objcopy')
args += ['-O', 'binary', elf_fname, bin_fname]
- stdout = command.Output(objcopy, *args)
+ stdout = command.output(objcopy, *args)
with open(bin_fname, 'rb') as fd:
data = fd.read()
self.assertEqual(expected_text + expected_data, data)
expected_data = b'wxyz'
elf_fname = os.path.join(outdir, 'elf')
elf.MakeElf(elf_fname, expected_text, expected_data)
- data = tools.ReadFile(elf_fname)
+ data = tools.read_file(elf_fname)
load = 0xfef20000
entry = load + 2
offset = elf.GetSymbolFileOffset(fname, ['embed_start', 'embed_end'])
start = offset['embed_start'].offset
end = offset['embed_end'].offset
- data = tools.ReadFile(fname)
+ data = tools.read_file(fname)
embed_data = data[start:end]
expect = struct.pack('<III', 0x1234, 0x5678, 0)
self.assertEqual(expect, embed_data)
offset = elf.GetSymbolFileOffset(fname, ['missing_sym'])
self.assertEqual({}, offset)
+ def test_read_segments(self):
+ """Test for read_segments()"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ fname = self.ElfTestFile('embed_data')
+ segments, entry = elf.read_segments(tools.read_file(fname))
+
+ def test_read_segments_fail(self):
+ """Test for read_segments() without elftools"""
+ try:
+ old_val = elf.ELF_TOOLS
+ elf.ELF_TOOLS = False
+ fname = self.ElfTestFile('embed_data')
+ with self.assertRaises(ValueError) as e:
+ elf.read_segments(tools.read_file(fname))
+ self.assertIn('Python elftools package is not available',
+ str(e.exception))
+ finally:
+ elf.ELF_TOOLS = old_val
+
+ def test_read_segments_bad_data(self):
+ """Test for read_segments() with an invalid ELF file"""
+ fname = self.ElfTestFile('embed_data')
+ with self.assertRaises(ValueError) as e:
+ elf.read_segments(tools.get_bytes(100, 100))
+ self.assertIn('Magic number does not match', str(e.exception))
+
if __name__ == '__main__':
unittest.main()
};
};
+More complex setups can be created, with generated nodes, as described
+below.
+
+Properties (in the 'fit' node itself)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Special properties have a `fit,` prefix, indicating that they should be
+processed but not included in the final FIT.
+
+The top-level 'fit' node supports the following special properties:
+
+ fit,external-offset
+ Indicates that the contents of the FIT are external and provides the
+ external offset. This is passed to mkimage via the -E and -p flags.
+
+ fit,fdt-list
+ Indicates the entry argument which provides the list of device tree
+ files for the gen-fdt-nodes operation (as below). This is often
+ `of-list` meaning that `-a of-list="dtb1 dtb2..."` should be passed
+ to binman.
+
+Substitutions
+~~~~~~~~~~~~~
+
+Node names and property values support a basic string-substitution feature.
+Available substitutions for '@' nodes (and property values) are:
+
+SEQ:
+ Sequence number of the generated fdt (1, 2, ...)
+NAME
+ Name of the dtb as provided (i.e. without adding '.dtb')
+
+The `default` property, if present, will be automatically set to the name
+if of configuration whose devicetree matches the `default-dt` entry
+argument, e.g. with `-a default-dt=sun50i-a64-pine64-lts`.
+
+Available substitutions for property values in these nodes are:
+
+DEFAULT-SEQ:
+ Sequence number of the default fdt, as provided by the 'default-dt'
+ entry argument
+
+Available operations
+~~~~~~~~~~~~~~~~~~~~
+
+You can add an operation to an '@' node to indicate which operation is
+required::
+
+ @fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
+ ...
+ };
+
+Available operations are:
+
+gen-fdt-nodes
+ Generate FDT nodes as above. This is the default if there is no
+ `fit,operation` property.
+
+Generating nodes from an FDT list (gen-fdt-nodes)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
U-Boot supports creating fdt and config nodes automatically. To do this,
-pass an of-list property (e.g. -a of-list=file1 file2). This tells binman
-that you want to generates nodes for two files: file1.dtb and file2.dtb
-The fit,fdt-list property (see above) indicates that of-list should be used.
-If the property is missing you will get an error.
+pass an `of-list` property (e.g. `-a of-list=file1 file2`). This tells
+binman that you want to generates nodes for two files: `file1.dtb` and
+`file2.dtb`. The `fit,fdt-list` property (see above) indicates that
+`of-list` should be used. If the property is missing you will get an error.
Then add a 'generator node', a node with a name starting with '@'::
};
};
-This tells binman to create nodes fdt-1 and fdt-2 for each of your two
+This tells binman to create nodes `fdt-1` and `fdt-2` for each of your two
files. All the properties you specify will be included in the node. This
node acts like a template to generate the nodes. The generator node itself
does not appear in the output - it is replaced with what binman generates.
+A 'data' property is created with the contents of the FDT file.
You can create config nodes in a similar way::
};
};
-This tells binman to create nodes config-1 and config-2, i.e. a config for
-each of your two files.
-
-Available substitutions for '@' nodes are:
-
-SEQ:
- Sequence number of the generated fdt (1, 2, ...)
-NAME
- Name of the dtb as provided (i.e. without adding '.dtb')
+This tells binman to create nodes `config-1` and `config-2`, i.e. a config
+for each of your two files.
Note that if no devicetree files are provided (with '-a of-list' as above)
then no nodes will be generated.
-The 'default' property, if present, will be automatically set to the name
-if of configuration whose devicetree matches the 'default-dt' entry
-argument, e.g. with '-a default-dt=sun50i-a64-pine64-lts'.
-
-Available substitutions for '@' property values are
-
-DEFAULT-SEQ:
- Sequence number of the default fdt,as provided by the 'default-dt' entry
- argument
-
-Properties (in the 'fit' node itself):
- fit,external-offset: Indicates that the contents of the FIT are external
- and provides the external offset. This is passsed to mkimage via
- the -E and -p flags.
-
-
Entry: fmap: An entry which contains an Fmap section
file. The output from mkimage then becomes part of the image produced by
binman.
+To use CONFIG options in the arguments, use a string list instead, as in
+this example which also produces four arguments::
+
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T imximage";
+
+ u-boot-spl {
+ };
+ };
+
+
Entry: opensbi: RISC-V OpenSBI fw_dynamic blob
+Entry: tee-os: Entry containing an OP-TEE Trusted OS (TEE) blob
+---------------------------------------------------------------
+
+Properties / Entry arguments:
+ - tee-os-path: Filename of file to read into entry. This is typically
+ called tee-pager.bin
+
+This entry holds the run-time firmware, typically started by U-Boot SPL.
+See the U-Boot README for your architecture or board for how to use it. See
+https://github.com/OP-TEE/optee_os for more information about OP-TEE.
+
+
+
Entry: text: An entry which contains text
-----------------------------------------
from binman import comp_util
from dtoc import fdt_util
from patman import tools
-from patman.tools import ToHex, ToHexSize
+from patman.tools import to_hex, to_hex_size
from patman import tout
modules = {}
external: True if this entry contains an external binary blob
bintools: Bintools used by this entry (only populated for Image)
missing_bintools: List of missing bintools for this entry
+ update_hash: True if this entry's "hash" subnode should be
+ updated with a hash of the entry contents
"""
def __init__(self, section, etype, node, name_prefix=''):
# Put this here to allow entry-docs and help to work without libfdt
self.allow_fake = False
self.bintools = {}
self.missing_bintools = []
+ self.update_hash = True
@staticmethod
def FindEntryClass(etype, expanded):
self.uncomp_size = fdt_util.GetInt(self._node, 'uncomp-size')
self.align = fdt_util.GetInt(self._node, 'align')
- if tools.NotPowerOfTwo(self.align):
+ if tools.not_power_of_two(self.align):
raise ValueError("Node '%s': Alignment %s must be a power of two" %
(self._node.path, self.align))
if self.section and self.align is None:
self.pad_before = fdt_util.GetInt(self._node, 'pad-before', 0)
self.pad_after = fdt_util.GetInt(self._node, 'pad-after', 0)
self.align_size = fdt_util.GetInt(self._node, 'align-size')
- if tools.NotPowerOfTwo(self.align_size):
+ if tools.not_power_of_two(self.align_size):
self.Raise("Alignment size %s must be a power of two" %
self.align_size)
self.align_end = fdt_util.GetInt(self._node, 'align-end')
if self.compress != 'none':
state.AddZeroProp(self._node, 'uncomp-size')
- err = state.CheckAddHashProp(self._node)
- if err:
- self.Raise(err)
+
+ if self.update_hash:
+ err = state.CheckAddHashProp(self._node)
+ if err:
+ self.Raise(err)
def SetCalculatedProperties(self):
"""Set the value of device-tree properties calculated by binman"""
state.SetInt(self._node, 'orig-size', self.orig_size, True)
if self.uncomp_size is not None:
state.SetInt(self._node, 'uncomp-size', self.uncomp_size)
- state.CheckSetHashValue(self._node, self.GetData)
+
+ if self.update_hash:
+ state.CheckSetHashValue(self._node, self.GetData)
def ProcessFdt(self, fdt):
"""Allow entries to adjust the device tree
# Don't let the data shrink. Pad it if necessary
if size_ok and new_size < self.contents_size:
- data += tools.GetBytes(0, self.contents_size - new_size)
+ data += tools.get_bytes(0, self.contents_size - new_size)
if not size_ok:
- tout.Debug("Entry '%s' size change from %s to %s" % (
- self._node.path, ToHex(self.contents_size),
- ToHex(new_size)))
+ tout.debug("Entry '%s' size change from %s to %s" % (
+ self._node.path, to_hex(self.contents_size),
+ to_hex(new_size)))
self.SetContents(data)
return size_ok
def ResetForPack(self):
"""Reset offset/size fields so that packing can be done again"""
self.Detail('ResetForPack: offset %s->%s, size %s->%s' %
- (ToHex(self.offset), ToHex(self.orig_offset),
- ToHex(self.size), ToHex(self.orig_size)))
+ (to_hex(self.offset), to_hex(self.orig_offset),
+ to_hex(self.size), to_hex(self.orig_size)))
self.pre_reset_size = self.size
self.offset = self.orig_offset
self.size = self.orig_size
New section offset pointer (after this entry)
"""
self.Detail('Packing: offset=%s, size=%s, content_size=%x' %
- (ToHex(self.offset), ToHex(self.size),
+ (to_hex(self.offset), to_hex(self.size),
self.contents_size))
if self.offset is None:
if self.offset_unset:
self.Raise('No offset set with offset-unset: should another '
'entry provide this correct offset?')
- self.offset = tools.Align(offset, self.align)
+ self.offset = tools.align(offset, self.align)
needed = self.pad_before + self.contents_size + self.pad_after
- needed = tools.Align(needed, self.align_size)
+ needed = tools.align(needed, self.align_size)
size = self.size
if not size:
size = needed
new_offset = self.offset + size
- aligned_offset = tools.Align(new_offset, self.align_end)
+ aligned_offset = tools.align(new_offset, self.align_end)
if aligned_offset != new_offset:
size = aligned_offset - self.offset
new_offset = aligned_offset
# Check that the alignment is correct. It could be wrong if the
# and offset or size values were provided (i.e. not calculated), but
# conflict with the provided alignment values
- if self.size != tools.Align(self.size, self.align_size):
+ if self.size != tools.align(self.size, self.align_size):
self.Raise("Size %#x (%d) does not match align-size %#x (%d)" %
(self.size, self.size, self.align_size, self.align_size))
- if self.offset != tools.Align(self.offset, self.align):
+ if self.offset != tools.align(self.offset, self.align):
self.Raise("Offset %#x (%d) does not match align %#x (%d)" %
(self.offset, self.offset, self.align, self.align))
self.Detail(' - packed: offset=%#x, size=%#x, content_size=%#x, next_offset=%x' %
def Info(self, msg):
"""Convenience function to log info referencing a node"""
tag = "Info '%s'" % self._node.path
- tout.Detail('%30s: %s' % (tag, msg))
+ tout.detail('%30s: %s' % (tag, msg))
def Detail(self, msg):
"""Convenience function to log detail referencing a node"""
tag = "Node '%s'" % self._node.path
- tout.Detail('%30s: %s' % (tag, msg))
+ tout.detail('%30s: %s' % (tag, msg))
def GetEntryArgsOrProps(self, props, required=False):
"""Return the values of a set of properties
bytes content of the entry, excluding any padding. If the entry is
compressed, the compressed data is returned
"""
- self.Detail('GetData: size %s' % ToHexSize(self.data))
+ self.Detail('GetData: size %s' % to_hex_size(self.data))
return self.data
def GetPaddedData(self, data=None):
"""
# Use True here so that we get an uncompressed section to work from,
# although compressed sections are currently not supported
- tout.Debug("ReadChildData section '%s', entry '%s'" %
+ tout.debug("ReadChildData section '%s', entry '%s'" %
(self.section.GetPath(), self.GetPath()))
data = self.section.ReadChildData(self, decomp, alt_format)
return data
fname (str): Filename of faked file
"""
if self.allow_fake and not pathlib.Path(fname).is_file():
- outfname = tools.GetOutputFilename(os.path.basename(fname))
+ outfname = tools.get_output_filename(os.path.basename(fname))
with open(outfname, "wb") as out:
out.truncate(1024)
self.faked = True
Returns:
True to use this entry type, False to use the original one
"""
- tout.Info("Node '%s': etype '%s': %s selected" %
+ tout.info("Node '%s': etype '%s': %s selected" %
(node.path, etype, new_etype))
return True
btool = bintool.Bintool.create(name)
tools[name] = btool
return btool
+
+ def SetUpdateHash(self, update_hash):
+ """Set whether this entry's "hash" subnode should be updated
+
+ Args:
+ update_hash: True if hash should be updated, False if not
+ """
+ self.update_hash = update_hash
+
+ def collect_contents_to_file(self, entries, prefix):
+ """Put the contents of a list of entries into a file
+
+ Args:
+ entries (list of Entry): Entries to collect
+ prefix (str): Filename prefix of file to write to
+
+ If any entry does not have contents yet, this function returns False
+ for the data.
+
+ Returns:
+ Tuple:
+ bytes: Concatenated data from all the entries (or False)
+ str: Filename of file written (or False if no data)
+ str: Unique portion of filename (or False if no data)
+ """
+ data = b''
+ for entry in entries:
+ # First get the input data and put it in a file. If not available,
+ # try later.
+ if not entry.ObtainContents():
+ return False, False, False
+ data += entry.GetData()
+ uniq = self.GetUniqueName()
+ fname = tools.get_output_filename(f'{prefix}.{uniq}')
+ tools.write_file(fname, data)
+ return data, fname, uniq
class TestEntry(unittest.TestCase):
def setUp(self):
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
def tearDown(self):
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
def GetNode(self):
binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
self._fip_flags = fdt_util.GetInt64(self._node, 'fip-hdr-flags', 0)
self._fip_align = fdt_util.GetInt(self._node, 'fip-align', 1)
- if tools.NotPowerOfTwo(self._fip_align):
+ if tools.not_power_of_two(self._fip_align):
raise ValueError("Node '%s': FIP alignment %s must be a power of two" %
(self._node.path, self._fip_align))
self.ReadEntries()
def ObtainContents(self):
self._filename = self.GetDefaultFilename()
- self._pathname = tools.GetInputFilename(self._filename,
+ self._pathname = tools.get_input_filename(self._filename,
self.external and self.section.GetAllowMissing())
# Allow the file to be missing
if not self._pathname:
bytes: Data read
"""
state.TimingStart('read')
- indata = tools.ReadFile(pathname)
+ indata = tools.read_file(pathname)
state.TimingAccum('read')
state.TimingStart('compress')
data = self.CompressData(indata)
pathnames = []
for fname in self._filenames:
fname = self.check_fake_fname(fname)
- pathname = tools.GetInputFilename(
+ pathname = tools.get_input_filename(
fname, self.external and self.section.GetAllowMissing())
# Allow the file to be missing
if not pathname:
fdt.pack()
outfdt = Fdt.FromData(fdt.as_bytearray())
data = outfdt.GetContents()
- data = FDTMAP_MAGIC + tools.GetBytes(0, 8) + data
+ data = FDTMAP_MAGIC + tools.get_bytes(0, 8) + data
return data
def ObtainContents(self):
'require-matches')
def ExpandEntries(self):
- files = tools.GetInputFilenameGlob(self._pattern)
+ files = tools.get_input_filename_glob(self._pattern)
if self._require_matches and not files:
self.Raise("Pattern '%s' matched no files" % self._pattern)
for fname in files:
self.fill_value = fdt_util.GetByte(self._node, 'fill-byte', 0)
def ObtainContents(self):
- self.SetContents(tools.GetBytes(self.fill_value, self.size))
+ self.SetContents(tools.get_bytes(self.fill_value, self.size))
return True
import libfdt
from binman.entry import Entry, EntryArg
+from binman.etype.section import Entry_section
from dtoc import fdt_util
from dtoc.fdt import Fdt
from patman import tools
-class Entry_fit(Entry):
+# Supported operations, with the fit,operation property
+OP_GEN_FDT_NODES = range(1)
+OPERATIONS = {
+ 'gen-fdt-nodes': OP_GEN_FDT_NODES,
+ }
+
+class Entry_fit(Entry_section):
+
"""Flat Image Tree (FIT)
This calls mkimage to create a FIT (U-Boot Flat Image Tree) based on the
};
};
+ More complex setups can be created, with generated nodes, as described
+ below.
+
+ Properties (in the 'fit' node itself)
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ Special properties have a `fit,` prefix, indicating that they should be
+ processed but not included in the final FIT.
+
+ The top-level 'fit' node supports the following special properties:
+
+ fit,external-offset
+ Indicates that the contents of the FIT are external and provides the
+ external offset. This is passed to mkimage via the -E and -p flags.
+
+ fit,fdt-list
+ Indicates the entry argument which provides the list of device tree
+ files for the gen-fdt-nodes operation (as below). This is often
+ `of-list` meaning that `-a of-list="dtb1 dtb2..."` should be passed
+ to binman.
+
+ Substitutions
+ ~~~~~~~~~~~~~
+
+ Node names and property values support a basic string-substitution feature.
+ Available substitutions for '@' nodes (and property values) are:
+
+ SEQ:
+ Sequence number of the generated fdt (1, 2, ...)
+ NAME
+ Name of the dtb as provided (i.e. without adding '.dtb')
+
+ The `default` property, if present, will be automatically set to the name
+ if of configuration whose devicetree matches the `default-dt` entry
+ argument, e.g. with `-a default-dt=sun50i-a64-pine64-lts`.
+
+ Available substitutions for property values in these nodes are:
+
+ DEFAULT-SEQ:
+ Sequence number of the default fdt, as provided by the 'default-dt'
+ entry argument
+
+ Available operations
+ ~~~~~~~~~~~~~~~~~~~~
+
+ You can add an operation to an '@' node to indicate which operation is
+ required::
+
+ @fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
+ ...
+ };
+
+ Available operations are:
+
+ gen-fdt-nodes
+ Generate FDT nodes as above. This is the default if there is no
+ `fit,operation` property.
+
+ Generating nodes from an FDT list (gen-fdt-nodes)
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
U-Boot supports creating fdt and config nodes automatically. To do this,
- pass an of-list property (e.g. -a of-list=file1 file2). This tells binman
- that you want to generates nodes for two files: file1.dtb and file2.dtb
- The fit,fdt-list property (see above) indicates that of-list should be used.
- If the property is missing you will get an error.
+ pass an `of-list` property (e.g. `-a of-list=file1 file2`). This tells
+ binman that you want to generates nodes for two files: `file1.dtb` and
+ `file2.dtb`. The `fit,fdt-list` property (see above) indicates that
+ `of-list` should be used. If the property is missing you will get an error.
Then add a 'generator node', a node with a name starting with '@'::
};
};
- This tells binman to create nodes fdt-1 and fdt-2 for each of your two
+ This tells binman to create nodes `fdt-1` and `fdt-2` for each of your two
files. All the properties you specify will be included in the node. This
node acts like a template to generate the nodes. The generator node itself
does not appear in the output - it is replaced with what binman generates.
+ A 'data' property is created with the contents of the FDT file.
You can create config nodes in a similar way::
};
};
- This tells binman to create nodes config-1 and config-2, i.e. a config for
- each of your two files.
-
- Available substitutions for '@' nodes are:
-
- SEQ:
- Sequence number of the generated fdt (1, 2, ...)
- NAME
- Name of the dtb as provided (i.e. without adding '.dtb')
+ This tells binman to create nodes `config-1` and `config-2`, i.e. a config
+ for each of your two files.
Note that if no devicetree files are provided (with '-a of-list' as above)
then no nodes will be generated.
-
- The 'default' property, if present, will be automatically set to the name
- if of configuration whose devicetree matches the 'default-dt' entry
- argument, e.g. with '-a default-dt=sun50i-a64-pine64-lts'.
-
- Available substitutions for '@' property values are
-
- DEFAULT-SEQ:
- Sequence number of the default fdt,as provided by the 'default-dt' entry
- argument
-
- Properties (in the 'fit' node itself):
- fit,external-offset: Indicates that the contents of the FIT are external
- and provides the external offset. This is passsed to mkimage via
- the -E and -p flags.
-
"""
def __init__(self, section, etype, node):
"""
Members:
_fit: FIT file being built
- _fit_sections: dict:
+ _entries: dict from Entry_section:
key: relative path to entry Node (from the base of the FIT)
value: Entry_section object comprising the contents of this
node
"""
super().__init__(section, etype, node)
self._fit = None
- self._fit_sections = {}
self._fit_props = {}
+
for pname, prop in self._node.props.items():
if pname.startswith('fit,'):
self._fit_props[pname] = prop
self.ReadEntries()
super().ReadNode()
+ def _get_operation(self, subnode):
+ """Get the operation referenced by a subnode
+
+ Args:
+ subnode (Node): Subnode (of the FIT) to check
+
+ Returns:
+ int: Operation to perform
+
+ Raises:
+ ValueError: Invalid operation name
+ """
+ oper_name = subnode.props.get('fit,operation')
+ if not oper_name:
+ return OP_GEN_FDT_NODES
+ oper = OPERATIONS.get(oper_name.value)
+ if not oper:
+ self.Raise(f"Unknown operation '{oper_name.value}'")
+ return oper
+
def ReadEntries(self):
+ def _process_prop(pname, prop):
+ """Process special properties
+
+ Handles properties with generated values. At present the only
+ supported property is 'default', i.e. the default device tree in
+ the configurations node.
+
+ Args:
+ pname (str): Name of property
+ prop (Prop): Property to process
+ """
+ if pname == 'default':
+ val = prop.value
+ # Handle the 'default' property
+ if val.startswith('@'):
+ if not self._fdts:
+ return
+ if not self._fit_default_dt:
+ self.Raise("Generated 'default' node requires default-dt entry argument")
+ if self._fit_default_dt not in self._fdts:
+ self.Raise("default-dt entry argument '%s' not found in fdt list: %s" %
+ (self._fit_default_dt,
+ ', '.join(self._fdts)))
+ seq = self._fdts.index(self._fit_default_dt)
+ val = val[1:].replace('DEFAULT-SEQ', str(seq + 1))
+ fsw.property_string(pname, val)
+ return
+ fsw.property(pname, prop.bytes)
+
+ def _scan_gen_fdt_nodes(subnode, depth, in_images):
+ """Generate FDT nodes
+
+ This creates one node for each member of self._fdts using the
+ provided template. If a property value contains 'NAME' it is
+ replaced with the filename of the FDT. If a property value contains
+ SEQ it is replaced with the node sequence number, where 1 is the
+ first.
+
+ Args:
+ subnode (None): Generator node to process
+ depth: Current node depth (0 is the base 'fit' node)
+ in_images: True if this is inside the 'images' node, so that
+ 'data' properties should be generated
+ """
+ if self._fdts:
+ # Generate nodes for each FDT
+ for seq, fdt_fname in enumerate(self._fdts):
+ node_name = subnode.name[1:].replace('SEQ', str(seq + 1))
+ fname = tools.get_input_filename(fdt_fname + '.dtb')
+ with fsw.add_node(node_name):
+ for pname, prop in subnode.props.items():
+ val = prop.bytes.replace(
+ b'NAME', tools.to_bytes(fdt_fname))
+ val = val.replace(
+ b'SEQ', tools.to_bytes(str(seq + 1)))
+ fsw.property(pname, val)
+
+ # Add data for 'images' nodes (but not 'config')
+ if depth == 1 and in_images:
+ fsw.property('data', tools.read_file(fname))
+ else:
+ if self._fdts is None:
+ if self._fit_list_prop:
+ self.Raise("Generator node requires '%s' entry argument" %
+ self._fit_list_prop.value)
+ else:
+ self.Raise("Generator node requires 'fit,fdt-list' property")
+
+ def _scan_node(subnode, depth, in_images):
+ """Generate nodes from a template
+
+ This creates one node for each member of self._fdts using the
+ provided template. If a property value contains 'NAME' it is
+ replaced with the filename of the FDT. If a property value contains
+ SEQ it is replaced with the node sequence number, where 1 is the
+ first.
+
+ Args:
+ subnode (None): Generator node to process
+ depth: Current node depth (0 is the base 'fit' node)
+ in_images: True if this is inside the 'images' node, so that
+ 'data' properties should be generated
+ """
+ oper = self._get_operation(subnode)
+ if oper == OP_GEN_FDT_NODES:
+ _scan_gen_fdt_nodes(subnode, depth, in_images)
+
def _AddNode(base_node, depth, node):
"""Add a node to the FIT
Args:
base_node: Base Node of the FIT (with 'description' property)
- depth: Current node depth (0 is the base node)
+ depth: Current node depth (0 is the base 'fit' node)
node: Current node to process
There are two cases to deal with:
"""
for pname, prop in node.props.items():
if not pname.startswith('fit,'):
- if pname == 'default':
- val = prop.value
- # Handle the 'default' property
- if val.startswith('@'):
- if not self._fdts:
- continue
- if not self._fit_default_dt:
- self.Raise("Generated 'default' node requires default-dt entry argument")
- if self._fit_default_dt not in self._fdts:
- self.Raise("default-dt entry argument '%s' not found in fdt list: %s" %
- (self._fit_default_dt,
- ', '.join(self._fdts)))
- seq = self._fdts.index(self._fit_default_dt)
- val = val[1:].replace('DEFAULT-SEQ', str(seq + 1))
- fsw.property_string(pname, val)
- continue
- fsw.property(pname, prop.bytes)
+ _process_prop(pname, prop)
rel_path = node.path[len(base_node.path):]
in_images = rel_path.startswith('/images')
# 'data' property later.
entry = Entry.Create(self.section, node, etype='section')
entry.ReadNode()
- self._fit_sections[rel_path] = entry
+ # The hash subnodes here are for mkimage, not binman.
+ entry.SetUpdateHash(False)
+ self._entries[rel_path] = entry
for subnode in node.subnodes:
if has_images and not (subnode.name.startswith('hash') or
# fsw.add_node() or _AddNode() for it.
pass
elif self.GetImage().generate and subnode.name.startswith('@'):
- if self._fdts:
- # Generate notes for each FDT
- for seq, fdt_fname in enumerate(self._fdts):
- node_name = subnode.name[1:].replace('SEQ',
- str(seq + 1))
- fname = tools.GetInputFilename(fdt_fname + '.dtb')
- with fsw.add_node(node_name):
- for pname, prop in subnode.props.items():
- val = prop.bytes.replace(
- b'NAME', tools.ToBytes(fdt_fname))
- val = val.replace(
- b'SEQ', tools.ToBytes(str(seq + 1)))
- fsw.property(pname, val)
-
- # Add data for 'fdt' nodes (but not 'config')
- if depth == 1 and in_images:
- fsw.property('data',
- tools.ReadFile(fname))
- else:
- if self._fdts is None:
- if self._fit_list_prop:
- self.Raise("Generator node requires '%s' entry argument" %
- self._fit_list_prop.value)
- else:
- self.Raise("Generator node requires 'fit,fdt-list' property")
+ _scan_node(subnode, depth, in_images)
else:
with fsw.add_node(subnode.name):
_AddNode(base_node, depth + 1, subnode)
self._fdt = Fdt.FromData(fdt.as_bytearray())
self._fdt.Scan()
- def ObtainContents(self):
- """Obtain the contents of the FIT
+ def BuildSectionData(self, required):
+ """Build FIT entry contents
This adds the 'data' properties to the input ITB (Image-tree Binary)
then runs mkimage to process it.
+
+ Args:
+ required: True if the data must be present, False if it is OK to
+ return None
+
+ Returns:
+ Contents of the section (bytes)
"""
- # self._BuildInput() either returns bytes or raises an exception.
data = self._BuildInput(self._fdt)
uniq = self.GetUniqueName()
- input_fname = tools.GetOutputFilename('%s.itb' % uniq)
- output_fname = tools.GetOutputFilename('%s.fit' % uniq)
- tools.WriteFile(input_fname, data)
- tools.WriteFile(output_fname, data)
+ input_fname = tools.get_output_filename('%s.itb' % uniq)
+ output_fname = tools.get_output_filename('%s.fit' % uniq)
+ tools.write_file(input_fname, data)
+ tools.write_file(output_fname, data)
args = {}
ext_offset = self._fit_props.get('fit,external-offset')
'pad': fdt_util.fdt32_to_cpu(ext_offset.value)
}
if self.mkimage.run(reset_timestamp=True, output_fname=output_fname,
- **args) is not None:
- self.SetContents(tools.ReadFile(output_fname))
- else:
+ **args) is None:
# Bintool is missing; just use empty data as the output
self.record_missing_bintool(self.mkimage)
- self.SetContents(tools.GetBytes(0, 1024))
+ return tools.get_bytes(0, 1024)
- return True
+ return tools.read_file(output_fname)
def _BuildInput(self, fdt):
"""Finish the FIT by adding the 'data' properties to it
Returns:
New fdt contents (bytes)
"""
- for path, section in self._fit_sections.items():
+ for path, section in self._entries.items():
node = fdt.GetNode(path)
- # Entry_section.ObtainContents() either returns True or
- # raises an exception.
- section.ObtainContents()
- section.Pack(0)
data = section.GetData()
node.AddData('data', data)
data = fdt.GetContents()
return data
- def CheckMissing(self, missing_list):
- """Check if any entries in this FIT have missing external blobs
+ def SetImagePos(self, image_pos):
+ """Set the position in the image
- If there are missing blobs, the entries are added to the list
+ This sets each subentry's offsets, sizes and positions-in-image
+ according to where they ended up in the packed FIT file.
Args:
- missing_list: List of Entry objects to be added to
+ image_pos: Position of this entry in the image
"""
- for path, section in self._fit_sections.items():
- section.CheckMissing(missing_list)
+ super().SetImagePos(image_pos)
+
+ # If mkimage is missing we'll have empty data,
+ # which will cause a FDT_ERR_BADMAGIC error
+ if self.mkimage in self.missing_bintools:
+ return
+
+ fdt = Fdt.FromData(self.GetData())
+ fdt.Scan()
+
+ for path, section in self._entries.items():
+ node = fdt.GetNode(path)
+
+ data_prop = node.props.get("data")
+ data_pos = fdt_util.GetInt(node, "data-position")
+ data_offset = fdt_util.GetInt(node, "data-offset")
+ data_size = fdt_util.GetInt(node, "data-size")
+
+ # Contents are inside the FIT
+ if data_prop is not None:
+ # GetOffset() returns offset of a fdt_property struct,
+ # which has 3 fdt32_t members before the actual data.
+ offset = data_prop.GetOffset() + 12
+ size = len(data_prop.bytes)
+
+ # External offset from the base of the FIT
+ elif data_pos is not None:
+ offset = data_pos
+ size = data_size
+
+ # External offset from the end of the FIT, not used in binman
+ elif data_offset is not None: # pragma: no cover
+ offset = fdt.GetFdtObj().totalsize() + data_offset
+ size = data_size
+
+ # This should never happen
+ else: # pragma: no cover
+ self.Raise("%s: missing data properties" % (path))
- def SetAllowMissing(self, allow_missing):
- for section in self._fit_sections.values():
- section.SetAllowMissing(allow_missing)
+ section.SetOffsetSize(offset, size)
+ section.SetImagePos(self.image_pos)
def AddBintools(self, tools):
+ super().AddBintools(tools)
self.mkimage = self.AddBintool(tools, 'mkimage')
from binman.entry import Entry
from binman import fmap_util
from patman import tools
-from patman.tools import ToHexSize
+from patman.tools import to_hex_size
from patman import tout
"""
def _AddEntries(areas, entry):
entries = entry.GetEntries()
- tout.Debug("fmap: Add entry '%s' type '%s' (%s subentries)" %
- (entry.GetPath(), entry.etype, ToHexSize(entries)))
+ tout.debug("fmap: Add entry '%s' type '%s' (%s subentries)" %
+ (entry.GetPath(), entry.etype, to_hex_size(entries)))
if entries and entry.etype != 'cbfs':
# Create an area for the section, which encompasses all entries
# within it
def ObtainContents(self):
gbb = 'gbb.bin'
- fname = tools.GetOutputFilename(gbb)
+ fname = tools.get_output_filename(gbb)
if not self.size:
self.Raise('GBB must have a fixed size')
gbb_size = self.size
bmpfv_size = gbb_size - 0x2180
if bmpfv_size < 0:
self.Raise('GBB is too small (minimum 0x2180 bytes)')
- keydir = tools.GetInputFilename(self.keydir)
+ keydir = tools.get_input_filename(self.keydir)
stdout = self.futility.gbb_create(
fname, [0x100, 0x1000, bmpfv_size, 0x1000])
rootkey='%s/root_key.vbpubk' % keydir,
recoverykey='%s/recovery_key.vbpubk' % keydir,
flags=self.gbb_flags,
- bmpfv=tools.GetInputFilename(self.bmpblk))
+ bmpfv=tools.get_input_filename(self.bmpblk))
if stdout is not None:
- self.SetContents(tools.ReadFile(fname))
+ self.SetContents(tools.read_file(fname))
else:
# Bintool is missing; just use the required amount of zero data
self.record_missing_bintool(self.futility)
- self.SetContents(tools.GetBytes(0, gbb_size))
+ self.SetContents(tools.get_bytes(0, gbb_size))
return True
# Create the IFWI file if needed
if self._convert_fit:
inname = self._pathname
- outname = tools.GetOutputFilename('ifwi.bin')
+ outname = tools.get_output_filename('ifwi.bin')
if self.ifwitool.create_ifwi(inname, outname) is None:
# Bintool is missing; just create a zeroed ifwi.bin
self.record_missing_bintool(self.ifwitool)
- self.SetContents(tools.GetBytes(0, 1024))
+ self.SetContents(tools.get_bytes(0, 1024))
self._filename = 'ifwi.bin'
self._pathname = outname
if self.ifwitool.delete_subpart(outname, 'OBBP') is None:
# Bintool is missing; just use zero data
self.record_missing_bintool(self.ifwitool)
- self.SetContents(tools.GetBytes(0, 1024))
+ self.SetContents(tools.get_bytes(0, 1024))
return True
for entry in self._ifwi_entries.values():
# First get the input data and put it in a file
data = entry.GetPaddedData()
uniq = self.GetUniqueName()
- input_fname = tools.GetOutputFilename('input.%s' % uniq)
- tools.WriteFile(input_fname, data)
+ input_fname = tools.get_output_filename('input.%s' % uniq)
+ tools.write_file(input_fname, data)
# At this point we know that ifwitool is present, so we don't need
# to check for None here
After that we delete the OBBP sub-partition and add each of the files
that we want in the IFWI file, one for each sub-entry of the IWFI node.
"""
- self._pathname = tools.GetInputFilename(self._filename,
+ self._pathname = tools.get_input_filename(self._filename,
self.section.GetAllowMissing())
# Allow the file to be missing
if not self._pathname:
This calls mkimage to create an imximage with u-boot-spl.bin as the input
file. The output from mkimage then becomes part of the image produced by
binman.
+
+ To use CONFIG options in the arguments, use a string list instead, as in
+ this example which also produces four arguments::
+
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T imximage";
+
+ u-boot-spl {
+ };
+ };
+
"""
def __init__(self, section, etype, node):
super().__init__(section, etype, node)
- self._args = fdt_util.GetString(self._node, 'args').split(' ')
+ self._args = fdt_util.GetArgs(self._node, 'args')
self._mkimage_entries = OrderedDict()
self.align_default = None
self.ReadEntries()
def ObtainContents(self):
- data = b''
- for entry in self._mkimage_entries.values():
- # First get the input data and put it in a file. If not available,
- # try later.
- if not entry.ObtainContents():
- return False
- data += entry.GetData()
- uniq = self.GetUniqueName()
- input_fname = tools.GetOutputFilename('mkimage.%s' % uniq)
- tools.WriteFile(input_fname, data)
- output_fname = tools.GetOutputFilename('mkimage-out.%s' % uniq)
+ data, input_fname, uniq = self.collect_contents_to_file(
+ self._mkimage_entries.values(), 'mkimage')
+ if data is False:
+ return False
+ output_fname = tools.get_output_filename('mkimage-out.%s' % uniq)
if self.mkimage.run_cmd('-d', input_fname, *self._args,
output_fname) is not None:
- self.SetContents(tools.ReadFile(output_fname))
+ self.SetContents(tools.read_file(output_fname))
else:
# Bintool is missing; just use the input data as the output
self.record_missing_bintool(self.mkimage)
from dtoc import fdt_util
from patman import tools
from patman import tout
-from patman.tools import ToHexSize
+from patman.tools import to_hex_size
class Entry_section(Entry):
data = bytearray()
# Handle padding before the entry
if entry.pad_before:
- data += tools.GetBytes(self._pad_byte, entry.pad_before)
+ data += tools.get_bytes(self._pad_byte, entry.pad_before)
# Add in the actual entry data
data += entry_data
# Handle padding after the entry
if entry.pad_after:
- data += tools.GetBytes(self._pad_byte, entry.pad_after)
+ data += tools.get_bytes(self._pad_byte, entry.pad_after)
if entry.size:
- data += tools.GetBytes(pad_byte, entry.size - len(data))
+ data += tools.get_bytes(pad_byte, entry.size - len(data))
- self.Detail('GetPaddedDataForEntry: size %s' % ToHexSize(self.data))
+ self.Detail('GetPaddedDataForEntry: size %s' % to_hex_size(self.data))
return data
# Handle empty space before the entry
pad = (entry.offset or 0) - self._skip_at_start - len(section_data)
if pad > 0:
- section_data += tools.GetBytes(self._pad_byte, pad)
+ section_data += tools.get_bytes(self._pad_byte, pad)
# Add in the actual entry data
section_data += data
if not size:
data = self.GetPaddedData(self.data)
size = len(data)
- size = tools.Align(size, self.align_size)
+ size = tools.align(size, self.align_size)
if self.size and contents_size > self.size:
self._Raise("contents size %#x (%d) exceeds section size %#x (%d)" %
(contents_size, contents_size, self.size, self.size))
if not self.size:
self.size = size
- if self.size != tools.Align(self.size, self.align_size):
+ if self.size != tools.align(self.size, self.align_size):
self._Raise("Size %#x (%d) does not match align-size %#x (%d)" %
(self.size, self.size, self.align_size,
self.align_size))
return self._sort
def ReadData(self, decomp=True, alt_format=None):
- tout.Info("ReadData path='%s'" % self.GetPath())
+ tout.info("ReadData path='%s'" % self.GetPath())
parent_data = self.section.ReadData(True, alt_format)
offset = self.offset - self.section._skip_at_start
data = parent_data[offset:offset + self.size]
- tout.Info(
+ tout.info(
'%s: Reading data from offset %#x-%#x (real %#x), size %#x, got %#x' %
(self.GetPath(), self.offset, self.offset + self.size, offset,
self.size, len(data)))
return data
def ReadChildData(self, child, decomp=True, alt_format=None):
- tout.Debug(f"ReadChildData for child '{child.GetPath()}'")
+ tout.debug(f"ReadChildData for child '{child.GetPath()}'")
parent_data = self.ReadData(True, alt_format)
offset = child.offset - self._skip_at_start
- tout.Debug("Extract for child '%s': offset %#x, skip_at_start %#x, result %#x" %
+ tout.debug("Extract for child '%s': offset %#x, skip_at_start %#x, result %#x" %
(child.GetPath(), child.offset, self._skip_at_start, offset))
data = parent_data[offset:offset + child.size]
if decomp:
indata = data
data = comp_util.decompress(indata, child.compress)
if child.uncomp_size:
- tout.Info("%s: Decompressing data size %#x with algo '%s' to data size %#x" %
+ tout.info("%s: Decompressing data size %#x with algo '%s' to data size %#x" %
(child.GetPath(), len(indata), child.compress,
len(data)))
if alt_format:
Args:
missing_list: List of Bintool objects to be added to
"""
+ super().check_missing_bintools(missing_list)
for entry in self._entries.values():
entry.check_missing_bintools(missing_list)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Entry-type module for OP-TEE Trusted OS firmware blob
+#
+
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
+
+class Entry_tee_os(Entry_blob_named_by_arg):
+ """Entry containing an OP-TEE Trusted OS (TEE) blob
+
+ Properties / Entry arguments:
+ - tee-os-path: Filename of file to read into entry. This is typically
+ called tee-pager.bin
+
+ This entry holds the run-time firmware, typically started by U-Boot SPL.
+ See the U-Boot README for your architecture or board for how to use it. See
+ https://github.com/OP-TEE/optee_os for more information about OP-TEE.
+ """
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node, 'tee-os')
+ self.external = True
super().__init__(section, etype, node)
value = fdt_util.GetString(self._node, 'text')
if value:
- value = tools.ToBytes(value)
+ value = tools.to_bytes(value)
else:
label, = self.GetEntryArgsOrProps([EntryArg('text-label', str)])
self.text_label = label
if self.text_label:
value, = self.GetEntryArgsOrProps([EntryArg(self.text_label,
str)])
- value = tools.ToBytes(value) if value is not None else value
+ value = tools.to_bytes(value) if value is not None else value
self.value = value
def ObtainContents(self):
def ReadBlobContents(self):
if self._strip:
uniq = self.GetUniqueName()
- out_fname = tools.GetOutputFilename('%s.stripped' % uniq)
- tools.WriteFile(out_fname, tools.ReadFile(self._pathname))
- tools.Run('strip', out_fname)
+ out_fname = tools.get_output_filename('%s.stripped' % uniq)
+ tools.write_file(out_fname, tools.read_file(self._pathname))
+ tools.run('strip', out_fname)
self._pathname = out_fname
super().ReadBlobContents()
return True
self.fill_value = fdt_util.GetByte(self._node, 'fill-byte', 0)
def ReadBlobContents(self):
- indata = tools.ReadFile(self._pathname)
+ indata = tools.read_file(self._pathname)
data = b''
for line in indata.splitlines():
data += line + b'\0'
pad = self.size - len(data) - 5
if pad < 0:
self.Raise("'u-boot-env' entry too small to hold data (need %#x more bytes)" % -pad)
- data += tools.GetBytes(self.fill_value, pad)
+ data += tools.get_bytes(self.fill_value, pad)
crc = zlib.crc32(data)
buf = struct.pack('<I', crc) + b'\x01' + data
self.SetContents(buf)
super().__init__(section, etype, node)
def ObtainContents(self):
- fname = tools.GetInputFilename('spl/u-boot-spl')
+ fname = tools.get_input_filename('spl/u-boot-spl')
bss_size = elf.GetSymbolAddress(fname, '__bss_size')
if not bss_size:
self.Raise('Expected __bss_size symbol in spl/u-boot-spl')
- self.SetContents(tools.GetBytes(0, bss_size))
+ self.SetContents(tools.get_bytes(0, bss_size))
return True
@classmethod
def UseExpanded(cls, node, etype, new_etype):
val = state.GetEntryArgBool('spl-dtb')
- tout.DoOutput(tout.INFO if val else tout.DETAIL,
+ tout.do_output(tout.INFO if val else tout.DETAIL,
"Node '%s': etype '%s': %s %sselected" %
(node.path, etype, new_etype, '' if val else 'not '))
return val
super().__init__(section, etype, node)
def ObtainContents(self):
- fname = tools.GetInputFilename('tpl/u-boot-tpl')
+ fname = tools.get_input_filename('tpl/u-boot-tpl')
bss_size = elf.GetSymbolAddress(fname, '__bss_size')
if not bss_size:
self.Raise('Expected __bss_size symbol in tpl/u-boot-tpl')
- self.SetContents(tools.GetBytes(0, bss_size))
+ self.SetContents(tools.get_bytes(0, bss_size))
return True
@classmethod
def UseExpanded(cls, node, etype, new_etype):
val = state.GetEntryArgBool('tpl-dtb')
- tout.DoOutput(tout.INFO if val else tout.DETAIL,
+ tout.do_output(tout.INFO if val else tout.DETAIL,
"Node '%s': etype '%s': %s %sselected" %
(node.path, etype, new_etype, '' if val else 'not '))
return val
return True
# Write it out to a file
- self._pathname = tools.GetOutputFilename('u-boot-ucode.bin')
- tools.WriteFile(self._pathname, fdt_entry.ucode_data)
+ self._pathname = tools.get_output_filename('u-boot-ucode.bin')
+ tools.write_file(self._pathname, fdt_entry.ucode_data)
self.ReadBlobContents()
def ProcessFdt(self, fdt):
# Figure out where to put the microcode pointer
- fname = tools.GetInputFilename(self.elf_fname)
+ fname = tools.get_input_filename(self.elf_fname)
sym = elf.GetSymbolAddress(fname, '_dt_ucode_base_size')
if sym:
self.target_offset = sym
return None
uniq = self.GetUniqueName()
- output_fname = tools.GetOutputFilename('vblock.%s' % uniq)
- input_fname = tools.GetOutputFilename('input.%s' % uniq)
- tools.WriteFile(input_fname, input_data)
+ output_fname = tools.get_output_filename('vblock.%s' % uniq)
+ input_fname = tools.get_output_filename('input.%s' % uniq)
+ tools.write_file(input_fname, input_data)
prefix = self.keydir + '/'
stdout = self.futility.sign_firmware(
vblock=output_fname,
kernelkey=prefix + self.kernelkey,
flags=f'{self.preamble_flags}')
if stdout is not None:
- data = tools.ReadFile(output_fname)
+ data = tools.read_file(output_fname)
else:
# Bintool is missing; just use 4KB of zero data
self.record_missing_bintool(self.futility)
- data = tools.GetBytes(0, 4096)
+ data = tools.get_bytes(0, 4096)
return data
def ObtainContents(self):
def setUpClass(self):
self._binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
self._indir = tempfile.mkdtemp(prefix='binmant.')
- tools.PrepareOutputDir(self._indir, True)
+ tools.prepare_output_dir(self._indir, True)
@classmethod
def tearDownClass(self):
- tools._FinaliseForTest()
+ tools._finalise_for_test()
def TestFile(self, fname):
return os.path.join(self._binman_dir, 'test', fname)
self.flags = flags
self.fip_type = None
self.data = None
- self.valid = uuid != tools.GetBytes(0, UUID_LEN)
+ self.valid = uuid != tools.get_bytes(0, UUID_LEN)
if self.valid:
# Look up the friendly name
matches = {val for (key, val) in FIP_TYPES.items()
Usage is something like:
fip = FipWriter(size)
- fip.add_entry('scp-fwu-cfg', tools.ReadFile('something.bin'))
+ fip.add_entry('scp-fwu-cfg', tools.read_file('something.bin'))
...
data = cbw.get_data()
offset += ENTRY_SIZE # terminating entry
for fent in self._fip_entries:
- offset = tools.Align(offset, self._align)
+ offset = tools.align(offset, self._align)
fent.offset = offset
offset += fent.size
re_uuid = re.compile('0x[0-9a-fA-F]{2}')
re_comment = re.compile(r'^/\* (.*) \*/$')
fname = os.path.join(srcdir, 'include/tools_share/firmware_image_package.h')
- data = tools.ReadFile(fname, binary=False)
+ data = tools.read_file(fname, binary=False)
macros = collections.OrderedDict()
comment = None
for linenum, line in enumerate(data.splitlines()):
re_data = re.compile(r'\.name = "([^"]*)",\s*\.uuid = (UUID_\w*),\s*\.cmdline_name = "([^"]+)"',
re.S)
fname = os.path.join(srcdir, 'tools/fiptool/tbbr_config.c')
- data = tools.ReadFile(fname, binary=False)
+ data = tools.read_file(fname, binary=False)
# Example entry:
# {
raise ValueError(
f"Expected file '{readme_fname}' - try using -s to specify the "
'arm-trusted-firmware directory')
- readme = tools.ReadFile(readme_fname, binary=False)
+ readme = tools.read_file(readme_fname, binary=False)
first_line = 'Trusted Firmware-A'
if readme.splitlines()[0] != first_line:
raise ValueError(f"'{readme_fname}' does not start with '{first_line}'")
macros = parse_macros(srcdir)
names = parse_names(srcdir)
output = create_code_output(macros, names)
- orig = tools.ReadFile(oldfile, binary=False)
+ orig = tools.read_file(oldfile, binary=False)
re_fip_list = re.compile(r'(.*FIP_TYPE_LIST = \[).*?( ] # end.*)', re.S)
mat = re_fip_list.match(orig)
new_code = mat.group(1) + '\n' + output + mat.group(2) if mat else output
if new_code == orig:
print(f"Existing code in '{oldfile}' is up-to-date")
else:
- tools.WriteFile(dstfile, new_code, binary=False)
+ tools.write_file(dstfile, new_code, binary=False)
print(f'Needs update, try:\n\tmeld {dstfile} {oldfile}')
def setUp(self):
# Create a temporary directory for test files
self._indir = tempfile.mkdtemp(prefix='fip_util.')
- tools.SetInputDirs([self._indir])
+ tools.set_input_dirs([self._indir])
# Set up a temporary output directory, used by the tools library when
# compressing files
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
self.src_file = os.path.join(self._indir, 'orig.py')
- self.outname = tools.GetOutputFilename('out.py')
+ self.outname = tools.get_output_filename('out.py')
self.args = ['-D', '-s', self._indir, '-o', self.outname]
self.readme = os.path.join(self._indir, 'readme.rst')
self.macro_dir = os.path.join(self._indir, 'include/tools_share')
def setup_readme(self):
"""Set up the readme.txt file"""
- tools.WriteFile(self.readme, 'Trusted Firmware-A\n==================',
+ tools.write_file(self.readme, 'Trusted Firmware-A\n==================',
binary=False)
def setup_macro(self, data=macro_contents):
"""Set up the tbbr_config.c file"""
os.makedirs(self.macro_dir)
- tools.WriteFile(self.macro_fname, data, binary=False)
+ tools.write_file(self.macro_fname, data, binary=False)
def setup_name(self, data=name_contents):
"""Set up the firmware_image_package.h file"""
os.makedirs(self.name_dir)
- tools.WriteFile(self.name_fname, data, binary=False)
+ tools.write_file(self.name_fname, data, binary=False)
def tearDown(self):
"""Remove the temporary input directory and its contents"""
if self._indir:
shutil.rmtree(self._indir)
self._indir = None
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
def test_no_readme(self):
"""Test handling of a missing readme.rst"""
def test_invalid_readme(self):
"""Test that an invalid readme.rst is detected"""
- tools.WriteFile(self.readme, 'blah', binary=False)
+ tools.write_file(self.readme, 'blah', binary=False)
with self.assertRaises(Exception) as err:
fip_util.main(self.args, self.src_file)
self.assertIn('does not start with', str(err.exception))
self.setup_name()
# Check generating the file when changes are needed
- tools.WriteFile(self.src_file, '''
+ tools.write_file(self.src_file, '''
# This is taken from tbbr_config.c in ARM Trusted Firmware
FIP_TYPE_LIST = [
self.assertIn('Needs update', stdout.getvalue())
# Check generating the file when no changes are needed
- tools.WriteFile(self.src_file, '''
+ tools.write_file(self.src_file, '''
# This is taken from tbbr_config.c in ARM Trusted Firmware
FIP_TYPE_LIST = [
# ToC Entry UUIDs
args = self.args.copy()
args.remove('-D')
- tools.WriteFile(self.src_file, '', binary=False)
+ tools.write_file(self.src_file, '', binary=False)
with test_util.capture_sys_output():
fip_util.main(args, self.src_file)
fip.add_entry('tb-fw', tb_fw, 0)
fip.add_entry(bytes(range(16)), tb_fw, 0)
data = fip.get_data()
- fname = tools.GetOutputFilename('data.fip')
- tools.WriteFile(fname, data)
+ fname = tools.get_output_filename('data.fip')
+ tools.write_file(fname, data)
result = FIPTOOL.info(fname)
self.assertEqual(
'''Firmware Updater NS_BL2U: offset=0xB0, size=0x7, cmdline="--fwu"
FipReader: reader for the image
"""
fwu = os.path.join(self._indir, 'fwu')
- tools.WriteFile(fwu, self.fwu_data)
+ tools.write_file(fwu, self.fwu_data)
tb_fw = os.path.join(self._indir, 'tb_fw')
- tools.WriteFile(tb_fw, self.tb_fw_data)
+ tools.write_file(tb_fw, self.tb_fw_data)
other_fw = os.path.join(self._indir, 'other_fw')
- tools.WriteFile(other_fw, self.other_fw_data)
+ tools.write_file(other_fw, self.other_fw_data)
- fname = tools.GetOutputFilename('data.fip')
+ fname = tools.get_output_filename('data.fip')
uuid = 'e3b78d9e-4a64-11ec-b45c-fba2b9b49788'
FIPTOOL.create_new(fname, 8, 0x123, fwu, tb_fw, uuid, other_fw)
- return fip_util.FipReader(tools.ReadFile(fname))
+ return fip_util.FipReader(tools.read_file(fname))
@unittest.skipIf(not HAVE_FIPTOOL, 'No fiptool available')
def test_fiptool_create(self):
value: value of that field (string for the ones we support)
"""
name_index = field_names.index('name')
- fields[name_index] = tools.ToBytes(NameToFmap(fields[name_index]))
+ fields[name_index] = tools.to_bytes(NameToFmap(fields[name_index]))
def DecodeFmap(data):
"""Decode a flashmap into a header and list of areas
U_BOOT_NODTB_DATA = b'nodtb with microcode pointer somewhere in here'
U_BOOT_SPL_NODTB_DATA = b'splnodtb with microcode pointer somewhere in here'
U_BOOT_TPL_NODTB_DATA = b'tplnodtb with microcode pointer somewhere in here'
+U_BOOT_EXP_DATA = U_BOOT_NODTB_DATA + U_BOOT_DTB_DATA
+U_BOOT_SPL_EXP_DATA = U_BOOT_SPL_NODTB_DATA + U_BOOT_SPL_DTB_DATA
+U_BOOT_TPL_EXP_DATA = U_BOOT_TPL_NODTB_DATA + U_BOOT_TPL_DTB_DATA
FSP_DATA = b'fsp'
CMC_DATA = b'cmc'
VBT_DATA = b'vbt'
FSP_S_DATA = b'fsp_s'
FSP_T_DATA = b'fsp_t'
ATF_BL31_DATA = b'bl31'
+TEE_OS_DATA = b'this is some tee OS data'
ATF_BL2U_DATA = b'bl2u'
OPENSBI_DATA = b'opensbi'
SCP_DATA = b'scp'
# ELF file with a '_dt_ucode_base_size' symbol
TestFunctional._MakeInputFile('u-boot',
- tools.ReadFile(cls.ElfTestFile('u_boot_ucode_ptr')))
+ tools.read_file(cls.ElfTestFile('u_boot_ucode_ptr')))
# Intel flash descriptor file
cls._SetupDescriptor()
TestFunctional._MakeInputFile('compress', COMPRESS_DATA)
TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG)
TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA)
+ TestFunctional._MakeInputFile('tee-pager.bin', TEE_OS_DATA)
TestFunctional._MakeInputFile('bl2u.bin', ATF_BL2U_DATA)
TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA)
TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
if self.preserve_outdirs:
print('Preserving output dir: %s' % tools.outdir)
else:
- tools._FinaliseForTest()
+ tools._finalise_for_test()
def setUp(self):
# Enable this to turn on debugging output
- # tout.Init(tout.DEBUG)
+ # tout.init(tout.DEBUG)
command.test_result = None
def tearDown(self):
Temporary directory to use
New image filename
"""
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
tmpdir = tempfile.mkdtemp(prefix='binman.')
updated_fname = os.path.join(tmpdir, 'image-updated.bin')
- tools.WriteFile(updated_fname, tools.ReadFile(image_fname))
+ tools.write_file(updated_fname, tools.read_file(image_fname))
self._CleanupOutputDir()
return tmpdir, updated_fname
Arguments to pass, as a list of strings
kwargs: Arguments to pass to Command.RunPipe()
"""
- result = command.RunPipe([[self._binman_pathname] + list(args)],
+ result = command.run_pipe([[self._binman_pathname] + list(args)],
capture=True, capture_stderr=True, raise_on_error=False)
if result.return_code and kwargs.get('raise_on_error', True):
raise Exception("Error running '%s': %s" % (' '.join(args),
use_expanded=use_expanded, extra_indirs=extra_indirs,
threads=threads)
self.assertEqual(0, retcode)
- out_dtb_fname = tools.GetOutputFilename('u-boot.dtb.out')
+ out_dtb_fname = tools.get_output_filename('u-boot.dtb.out')
# Find the (only) image, read it and return its contents
image = control.images['image']
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
self.assertTrue(os.path.exists(image_fname))
if map:
- map_fname = tools.GetOutputFilename('image.map')
+ map_fname = tools.get_output_filename('image.map')
with open(map_fname) as fd:
map_data = fd.read()
else:
Filename of ELF file to use as SPL
"""
TestFunctional._MakeInputFile('spl/u-boot-spl',
- tools.ReadFile(cls.ElfTestFile(src_fname)))
+ tools.read_file(cls.ElfTestFile(src_fname)))
@classmethod
def _SetupTplElf(cls, src_fname='bss_data'):
Filename of ELF file to use as TPL
"""
TestFunctional._MakeInputFile('tpl/u-boot-tpl',
- tools.ReadFile(cls.ElfTestFile(src_fname)))
+ tools.read_file(cls.ElfTestFile(src_fname)))
@classmethod
def _SetupDescriptor(cls):
image = control.images['image1']
self.assertEqual(len(U_BOOT_DATA), image.size)
- fname = tools.GetOutputFilename('image1.bin')
+ fname = tools.get_output_filename('image1.bin')
self.assertTrue(os.path.exists(fname))
with open(fname, 'rb') as fd:
data = fd.read()
image = control.images['image2']
self.assertEqual(3 + len(U_BOOT_DATA) + 5, image.size)
- fname = tools.GetOutputFilename('image2.bin')
+ fname = tools.get_output_filename('image2.bin')
self.assertTrue(os.path.exists(fname))
with open(fname, 'rb') as fd:
data = fd.read()
self.assertEqual(U_BOOT_DATA, data[3:7])
- self.assertEqual(tools.GetBytes(0, 3), data[:3])
- self.assertEqual(tools.GetBytes(0, 5), data[7:])
+ self.assertEqual(tools.get_bytes(0, 3), data[:3])
+ self.assertEqual(tools.get_bytes(0, 5), data[7:])
def testBadAlign(self):
"""Test that an invalid alignment value is detected"""
self.assertEqual(3, entry.pad_before)
self.assertEqual(3 + 5 + len(U_BOOT_DATA), entry.size)
self.assertEqual(U_BOOT_DATA, entry.data)
- self.assertEqual(tools.GetBytes(0, 3) + U_BOOT_DATA +
- tools.GetBytes(0, 5), data[:entry.size])
+ self.assertEqual(tools.get_bytes(0, 3) + U_BOOT_DATA +
+ tools.get_bytes(0, 5), data[:entry.size])
pos = entry.size
# Second u-boot has an aligned size, but it has no effect
self.assertEqual(pos, entry.offset)
self.assertEqual(32, entry.size)
self.assertEqual(U_BOOT_DATA, entry.data)
- self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 32 - len(U_BOOT_DATA)),
+ self.assertEqual(U_BOOT_DATA + tools.get_bytes(0, 32 - len(U_BOOT_DATA)),
data[pos:pos + entry.size])
pos += entry.size
self.assertEqual(48, entry.offset)
self.assertEqual(16, entry.size)
self.assertEqual(U_BOOT_DATA, entry.data[:len(U_BOOT_DATA)])
- self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 16 - len(U_BOOT_DATA)),
+ self.assertEqual(U_BOOT_DATA + tools.get_bytes(0, 16 - len(U_BOOT_DATA)),
data[pos:pos + entry.size])
pos += entry.size
self.assertEqual(64, entry.offset)
self.assertEqual(64, entry.size)
self.assertEqual(U_BOOT_DATA, entry.data[:len(U_BOOT_DATA)])
- self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 64 - len(U_BOOT_DATA)),
+ self.assertEqual(U_BOOT_DATA + tools.get_bytes(0, 64 - len(U_BOOT_DATA)),
data[pos:pos + entry.size])
self.CheckNoGaps(entries)
"""Test that the image pad byte can be specified"""
self._SetupSplElf()
data = self._DoReadFile('021_image_pad.dts')
- self.assertEqual(U_BOOT_SPL_DATA + tools.GetBytes(0xff, 1) +
+ self.assertEqual(U_BOOT_SPL_DATA + tools.get_bytes(0xff, 1) +
U_BOOT_DATA, data)
def testImageName(self):
retcode = self._DoTestFile('022_image_name.dts')
self.assertEqual(0, retcode)
image = control.images['image1']
- fname = tools.GetOutputFilename('test-name')
+ fname = tools.get_output_filename('test-name')
self.assertTrue(os.path.exists(fname))
image = control.images['image2']
- fname = tools.GetOutputFilename('test-name.xx')
+ fname = tools.get_output_filename('test-name.xx')
self.assertTrue(os.path.exists(fname))
def testBlobFilename(self):
"""Test that entries can be sorted"""
self._SetupSplElf()
data = self._DoReadFile('024_sorted.dts')
- self.assertEqual(tools.GetBytes(0, 1) + U_BOOT_SPL_DATA +
- tools.GetBytes(0, 2) + U_BOOT_DATA, data)
+ self.assertEqual(tools.get_bytes(0, 1) + U_BOOT_SPL_DATA +
+ tools.get_bytes(0, 2) + U_BOOT_DATA, data)
def testPackZeroOffset(self):
"""Test that an entry at offset 0 is not given a new offset"""
"""Test that a basic x86 ROM can be created"""
self._SetupSplElf()
data = self._DoReadFile('029_x86_rom.dts')
- self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 3) + U_BOOT_SPL_DATA +
- tools.GetBytes(0, 2), data)
+ self.assertEqual(U_BOOT_DATA + tools.get_bytes(0, 3) + U_BOOT_SPL_DATA +
+ tools.get_bytes(0, 2), data)
def testPackX86RomMeNoDesc(self):
"""Test that an invalid Intel descriptor entry is detected"""
def testPackX86RomMe(self):
"""Test that an x86 ROM with an ME region can be created"""
data = self._DoReadFile('031_x86_rom_me.dts')
- expected_desc = tools.ReadFile(self.TestFile('descriptor.bin'))
+ expected_desc = tools.read_file(self.TestFile('descriptor.bin'))
if data[:0x1000] != expected_desc:
self.fail('Expected descriptor binary at start of image')
self.assertEqual(ME_DATA, data[0x1000:0x1000 + len(ME_DATA)])
fdt_len = self.GetFdtLen(dtb_with_ucode)
ucode_content = dtb_with_ucode[fdt_len:]
ucode_pos = len(nodtb_data) + fdt_len
- fname = tools.GetOutputFilename('test.dtb')
+ fname = tools.get_output_filename('test.dtb')
with open(fname, 'wb') as fd:
fd.write(dtb_with_ucode)
dtb = fdt.FdtScan(fname)
# ELF file without a '_dt_ucode_base_size' symbol
try:
TestFunctional._MakeInputFile('u-boot',
- tools.ReadFile(self.ElfTestFile('u_boot_no_ucode_ptr')))
+ tools.read_file(self.ElfTestFile('u_boot_no_ucode_ptr')))
with self.assertRaises(ValueError) as e:
self._RunPackUbootSingleMicrocode()
finally:
# Put the original file back
TestFunctional._MakeInputFile('u-boot',
- tools.ReadFile(self.ElfTestFile('u_boot_ucode_ptr')))
+ tools.read_file(self.ElfTestFile('u_boot_ucode_ptr')))
def testMicrocodeNotInImage(self):
"""Test that microcode must be placed within the image"""
def testWithoutMicrocode(self):
"""Test that we can cope with an image without microcode (e.g. qemu)"""
TestFunctional._MakeInputFile('u-boot',
- tools.ReadFile(self.ElfTestFile('u_boot_no_ucode_ptr')))
+ tools.read_file(self.ElfTestFile('u_boot_no_ucode_ptr')))
data, dtb, _, _ = self._DoReadFileDtb('044_x86_optional_ucode.dts', True)
# Now check the device tree has no microcode
used_len = len(U_BOOT_NODTB_DATA) + fdt_len
third = data[used_len:]
- self.assertEqual(tools.GetBytes(0, 0x200 - used_len), third)
+ self.assertEqual(tools.get_bytes(0, 0x200 - used_len), third)
def testUnknownPosSize(self):
"""Test that microcode must be placed within the image"""
# ELF file with a '__bss_size' symbol
self._SetupSplElf()
data = self._DoReadFile('047_spl_bss_pad.dts')
- self.assertEqual(U_BOOT_SPL_DATA + tools.GetBytes(0, 10) + U_BOOT_DATA,
+ self.assertEqual(U_BOOT_SPL_DATA + tools.get_bytes(0, 10) + U_BOOT_DATA,
data)
def testSplBssPadMissing(self):
u_boot_offset + len(U_BOOT_DATA),
0x10 + u_boot_offset, 0x04)
expected = (sym_values + base_data[20:] +
- tools.GetBytes(0xff, 1) + U_BOOT_DATA + sym_values +
+ tools.get_bytes(0xff, 1) + U_BOOT_DATA + sym_values +
base_data[20:])
self.assertEqual(expected, data)
def testSections(self):
"""Basic test of sections"""
data = self._DoReadFile('055_sections.dts')
- expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) +
- U_BOOT_DATA + tools.GetBytes(ord('a'), 12) +
- U_BOOT_DATA + tools.GetBytes(ord('&'), 4))
+ expected = (U_BOOT_DATA + tools.get_bytes(ord('!'), 12) +
+ U_BOOT_DATA + tools.get_bytes(ord('a'), 12) +
+ U_BOOT_DATA + tools.get_bytes(ord('&'), 4))
self.assertEqual(expected, data)
def testMap(self):
}
data, _, _, _ = self._DoReadFileDtb('066_text.dts',
entry_args=entry_args)
- expected = (tools.ToBytes(TEXT_DATA) +
- tools.GetBytes(0, 8 - len(TEXT_DATA)) +
- tools.ToBytes(TEXT_DATA2) + tools.ToBytes(TEXT_DATA3) +
+ expected = (tools.to_bytes(TEXT_DATA) +
+ tools.get_bytes(0, 8 - len(TEXT_DATA)) +
+ tools.to_bytes(TEXT_DATA2) + tools.to_bytes(TEXT_DATA3) +
b'some text' + b'more text')
self.assertEqual(expected, data)
"""Basic test of generation of a flashrom fmap"""
data = self._DoReadFile('067_fmap.dts')
fhdr, fentries = fmap_util.DecodeFmap(data[32:])
- expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) +
- U_BOOT_DATA + tools.GetBytes(ord('a'), 12))
+ expected = (U_BOOT_DATA + tools.get_bytes(ord('!'), 12) +
+ U_BOOT_DATA + tools.get_bytes(ord('a'), 12))
self.assertEqual(expected, data[:32])
self.assertEqual(b'__FMAP__', fhdr.signature)
self.assertEqual(1, fhdr.ver_major)
def testFill(self):
"""Test for an fill entry type"""
data = self._DoReadFile('069_fill.dts')
- expected = tools.GetBytes(0xff, 8) + tools.GetBytes(0, 8)
+ expected = tools.get_bytes(0xff, 8) + tools.get_bytes(0, 8)
self.assertEqual(expected, data)
def testFillNoSize(self):
data, _, _, _ = self._DoReadFileDtb('071_gbb.dts', entry_args=entry_args)
# Since futility
- expected = (GBB_DATA + GBB_DATA + tools.GetBytes(0, 8) +
- tools.GetBytes(0, 0x2180 - 16))
+ expected = (GBB_DATA + GBB_DATA + tools.get_bytes(0, 8) +
+ tools.get_bytes(0, 0x2180 - 16))
self.assertEqual(expected, data)
def testGbbTooSmall(self):
if self._hash_data:
infile = pipe_list[0][11]
m = hashlib.sha256()
- data = tools.ReadFile(infile)
+ data = tools.read_file(infile)
m.update(data)
fd.write(m.digest())
else:
def testFillZero(self):
"""Test for an fill entry type with a size of 0"""
data = self._DoReadFile('080_fill_empty.dts')
- self.assertEqual(tools.GetBytes(0, 16), data)
+ self.assertEqual(tools.get_bytes(0, 16), data)
def testTextMissing(self):
"""Test for a text entry type where there is no text"""
else:
self.assertNotIn(expected, stdout.getvalue())
- self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin')))
- self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin')))
+ self.assertFalse(os.path.exists(tools.get_output_filename('image1.bin')))
+ self.assertTrue(os.path.exists(tools.get_output_filename('image2.bin')))
self._CleanupOutputDir()
def testUpdateFdtAll(self):
'tpl/u-boot-tpl.dtb.out']:
dtb = fdt.Fdt.FromData(data[start:])
size = dtb._fdt_obj.totalsize()
- pathname = tools.GetOutputFilename(os.path.split(fname)[1])
- outdata = tools.ReadFile(pathname)
+ pathname = tools.get_output_filename(os.path.split(fname)[1])
+ outdata = tools.read_file(pathname)
name = os.path.split(fname)[0]
if name:
"""Test an expanding entry"""
data, _, map_data, _ = self._DoReadFileDtb('088_expand_size.dts',
map=True)
- expect = (tools.GetBytes(ord('a'), 8) + U_BOOT_DATA +
- MRC_DATA + tools.GetBytes(ord('b'), 1) + U_BOOT_DATA +
- tools.GetBytes(ord('c'), 8) + U_BOOT_DATA +
- tools.GetBytes(ord('d'), 8))
+ expect = (tools.get_bytes(ord('a'), 8) + U_BOOT_DATA +
+ MRC_DATA + tools.get_bytes(ord('b'), 1) + U_BOOT_DATA +
+ tools.get_bytes(ord('c'), 8) + U_BOOT_DATA +
+ tools.get_bytes(ord('d'), 8))
self.assertEqual(expect, data)
self.assertEqual('''ImagePos Offset Size Name
00000000 00000000 00000028 main-section
def testHashBadAlgo(self):
with self.assertRaises(ValueError) as e:
self._DoReadFileDtb('092_hash_bad_algo.dts', update_dtb=True)
- self.assertIn("Node '/binman/u-boot': Unknown hash algorithm",
+ self.assertIn("Node '/binman/u-boot': Unknown hash algorithm 'invalid'",
str(e.exception))
def testHashSection(self):
hash_node = dtb.GetNode('/binman/section/hash').props['value']
m = hashlib.sha256()
m.update(U_BOOT_DATA)
- m.update(tools.GetBytes(ord('a'), 16))
+ m.update(tools.get_bytes(ord('a'), 16))
self.assertEqual(m.digest(), b''.join(hash_node.value))
def testPackUBootTplMicrocode(self):
"""Basic test of generation of a flashrom fmap"""
data = self._DoReadFile('094_fmap_x86.dts')
fhdr, fentries = fmap_util.DecodeFmap(data[32:])
- expected = U_BOOT_DATA + MRC_DATA + tools.GetBytes(ord('a'), 32 - 7)
+ expected = U_BOOT_DATA + MRC_DATA + tools.get_bytes(ord('a'), 32 - 7)
self.assertEqual(expected, data[:32])
fhdr, fentries = fmap_util.DecodeFmap(data[32:])
def testFmapX86Section(self):
"""Basic test of generation of a flashrom fmap"""
data = self._DoReadFile('095_fmap_x86_section.dts')
- expected = U_BOOT_DATA + MRC_DATA + tools.GetBytes(ord('b'), 32 - 7)
+ expected = U_BOOT_DATA + MRC_DATA + tools.get_bytes(ord('b'), 32 - 7)
self.assertEqual(expected, data[:32])
fhdr, fentries = fmap_util.DecodeFmap(data[36:])
with test_util.capture_sys_output() as (stdout, stderr):
with self.assertRaises(ValueError) as e:
self._DoTestFile('014_pack_overlap.dts', map=True)
- map_fname = tools.GetOutputFilename('image.map')
+ map_fname = tools.get_output_filename('image.map')
self.assertEqual("Wrote map file '%s' to show errors\n" % map_fname,
stdout.getvalue())
# We should not get an inmage, but there should be a map file
- self.assertFalse(os.path.exists(tools.GetOutputFilename('image.bin')))
+ self.assertFalse(os.path.exists(tools.get_output_filename('image.bin')))
self.assertTrue(os.path.exists(map_fname))
- map_data = tools.ReadFile(map_fname, binary=False)
+ map_data = tools.read_file(map_fname, binary=False)
self.assertEqual('''ImagePos Offset Size Name
<none> 00000000 00000008 main-section
<none> 00000000 00000004 u-boot
0000002c 00000000 00000004 u-boot
''', map_data)
self.assertEqual(data,
- tools.GetBytes(0x26, 4) + U_BOOT_DATA +
- tools.GetBytes(0x21, 12) +
- tools.GetBytes(0x26, 4) + U_BOOT_DATA +
- tools.GetBytes(0x61, 12) +
- tools.GetBytes(0x26, 4) + U_BOOT_DATA +
- tools.GetBytes(0x26, 8))
+ tools.get_bytes(0x26, 4) + U_BOOT_DATA +
+ tools.get_bytes(0x21, 12) +
+ tools.get_bytes(0x26, 4) + U_BOOT_DATA +
+ tools.get_bytes(0x61, 12) +
+ tools.get_bytes(0x26, 4) + U_BOOT_DATA +
+ tools.get_bytes(0x26, 8))
def testCbfsRaw(self):
"""Test base handling of a Coreboot Filesystem (CBFS)
Args:
data: Conents of output file
"""
- expected_desc = tools.ReadFile(self.TestFile('descriptor.bin'))
+ expected_desc = tools.read_file(self.TestFile('descriptor.bin'))
if data[:0x1000] != expected_desc:
self.fail('Expected descriptor binary at start of image')
# We expect to find the TPL wil in subpart IBBP entry IBBL
- image_fname = tools.GetOutputFilename('image.bin')
- tpl_fname = tools.GetOutputFilename('tpl.out')
+ image_fname = tools.get_output_filename('image.bin')
+ tpl_fname = tools.get_output_filename('tpl.out')
ifwitool = bintool.Bintool.create('ifwitool')
ifwitool.extract(image_fname, 'IBBP', 'IBBL', tpl_fname)
- tpl_data = tools.ReadFile(tpl_fname)
+ tpl_data = tools.read_file(tpl_fname)
self.assertEqual(U_BOOT_TPL_DATA, tpl_data[:len(U_BOOT_TPL_DATA)])
def testPackX86RomIfwi(self):
fdtmap_data = data[len(U_BOOT_DATA):]
magic = fdtmap_data[:8]
self.assertEqual(b'_FDTMAP_', magic)
- self.assertEqual(tools.GetBytes(0, 8), fdtmap_data[8:16])
+ self.assertEqual(tools.get_bytes(0, 8), fdtmap_data[8:16])
fdt_data = fdtmap_data[16:]
dtb = fdt.Fdt.FromData(fdt_data)
"""Test reading an image and accessing its FDT map"""
self._CheckLz4()
data = self.data = self._DoReadFileRealDtb('128_decode_image.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
orig_image = control.images['image']
image = Image.FromFile(image_fname)
self.assertEqual(orig_image.GetEntries().keys(),
"""Test accessing an image's FDT map without an image header"""
self._CheckLz4()
data = self._DoReadFileRealDtb('129_decode_image_nohdr.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
image = Image.FromFile(image_fname)
self.assertTrue(isinstance(image, Image))
self.assertEqual('image', image.image_name[-5:])
def testReadImageFail(self):
"""Test failing to read an image image's FDT map"""
self._DoReadFile('005_simple.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
with self.assertRaises(ValueError) as e:
image = Image.FromFile(image_fname)
self.assertIn("Cannot find FDT map in image", str(e.exception))
"""
self._CheckLz4()
self._DoReadFileRealDtb('130_list_fdtmap.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
image = Image.FromFile(image_fname)
lines = image.GetListEntries(paths)[1]
files = [line[0].strip() for line in lines[1:]]
"""
self._CheckLz4()
self._DoReadFileRealDtb('130_list_fdtmap.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
return control.ReadEntry(image_fname, entry_name, decomp)
def testExtractSimple(self):
def testExtractBadFile(self):
"""Test extracting an invalid file"""
fname = os.path.join(self._indir, 'badfile')
- tools.WriteFile(fname, b'')
+ tools.write_file(fname, b'')
with self.assertRaises(ValueError) as e:
control.ReadEntry(fname, 'name')
'-f', fname)
finally:
shutil.rmtree(tmpdir)
- data = tools.ReadFile(fname)
+ data = tools.read_file(fname)
self.assertEqual(U_BOOT_DATA, data)
def testExtractOneEntry(self):
"""Test extracting a single entry fron an image """
self._CheckLz4()
self._DoReadFileRealDtb('130_list_fdtmap.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
fname = os.path.join(self._indir, 'output.extact')
control.ExtractEntries(image_fname, fname, None, ['u-boot'])
- data = tools.ReadFile(fname)
+ data = tools.read_file(fname)
self.assertEqual(U_BOOT_DATA, data)
def _CheckExtractOutput(self, decomp):
expect_size: Size of data to expect in file, or None to skip
"""
path = os.path.join(outdir, entry_path)
- data = tools.ReadFile(path)
+ data = tools.read_file(path)
os.remove(path)
if expect_data:
self.assertEqual(expect_data, data)
os.rmdir(path)
self._DoReadFileRealDtb('130_list_fdtmap.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
outdir = os.path.join(self._indir, 'extract')
einfos = control.ExtractEntries(image_fname, None, outdir, [], decomp)
_CheckPresent('section/root', section.data)
cbfs = section_entries['cbfs']
_CheckPresent('section/cbfs/root', cbfs.data)
- data = tools.ReadFile(image_fname)
+ data = tools.read_file(image_fname)
_CheckPresent('root', data)
# There should be no files left. Remove all the directories to check.
"""Test extracting some entries"""
self._CheckLz4()
self._DoReadFileRealDtb('130_list_fdtmap.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
outdir = os.path.join(self._indir, 'extract')
einfos = control.ExtractEntries(image_fname, None, outdir,
['*cb*', '*head*'])
"""Test extracting some entries"""
self._CheckLz4()
self._DoReadFileRealDtb('130_list_fdtmap.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
with self.assertRaises(ValueError) as e:
control.ExtractEntries(image_fname, 'fname', None, [])
self.assertIn('Must specify an entry path to write with -f',
"""Test extracting some entries"""
self._CheckLz4()
self._DoReadFileRealDtb('130_list_fdtmap.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
with self.assertRaises(ValueError) as e:
control.ExtractEntries(image_fname, 'fname', None, ['a', 'b'])
self.assertIn('Must specify exactly one entry path to write with -f',
orig_dtb_data = entries['u-boot-dtb'].data
orig_fdtmap_data = entries['fdtmap'].data
- image_fname = tools.GetOutputFilename('image.bin')
- updated_fname = tools.GetOutputFilename('image-updated.bin')
- tools.WriteFile(updated_fname, tools.ReadFile(image_fname))
+ image_fname = tools.get_output_filename('image.bin')
+ updated_fname = tools.get_output_filename('image-updated.bin')
+ tools.write_file(updated_fname, tools.read_file(image_fname))
image = control.WriteEntry(updated_fname, entry_name, data, decomp,
allow_resize)
data = control.ReadEntry(updated_fname, entry_name, decomp)
data = self._DoReadFileDtb('133_replace_multi.dts', use_real_dtb=True,
update_dtb=True)[0]
expected = b'x' * len(U_BOOT_DATA)
- updated_fname = tools.GetOutputFilename('image-updated.bin')
- tools.WriteFile(updated_fname, data)
+ updated_fname = tools.get_output_filename('image-updated.bin')
+ tools.write_file(updated_fname, data)
entry_name = 'u-boot'
control.WriteEntry(updated_fname, entry_name, expected,
allow_resize=False)
self.assertEqual('/binman/image', state.fdt_path_prefix)
# Now check we can write the first image
- image_fname = tools.GetOutputFilename('first-image.bin')
- updated_fname = tools.GetOutputFilename('first-updated.bin')
- tools.WriteFile(updated_fname, tools.ReadFile(image_fname))
+ image_fname = tools.get_output_filename('first-image.bin')
+ updated_fname = tools.get_output_filename('first-updated.bin')
+ tools.write_file(updated_fname, tools.read_file(image_fname))
entry_name = 'u-boot'
control.WriteEntry(updated_fname, entry_name, expected,
allow_resize=False)
self._CheckLz4()
expected = b'x' * len(U_BOOT_DATA)
data = self._DoReadFileRealDtb('142_replace_cbfs.dts')
- updated_fname = tools.GetOutputFilename('image-updated.bin')
- tools.WriteFile(updated_fname, data)
+ updated_fname = tools.get_output_filename('image-updated.bin')
+ tools.write_file(updated_fname, data)
entry_name = 'section/cbfs/u-boot'
control.WriteEntry(updated_fname, entry_name, expected,
allow_resize=True)
self._CheckLz4()
expected = U_BOOT_DATA + b'x'
data = self._DoReadFileRealDtb('142_replace_cbfs.dts')
- updated_fname = tools.GetOutputFilename('image-updated.bin')
- tools.WriteFile(updated_fname, data)
+ updated_fname = tools.get_output_filename('image-updated.bin')
+ tools.write_file(updated_fname, data)
entry_name = 'section/cbfs/u-boot'
control.WriteEntry(updated_fname, entry_name, expected,
allow_resize=True)
"""
data = self._DoReadFileRealDtb('143_replace_all.dts')
- updated_fname = tools.GetOutputFilename('image-updated.bin')
- tools.WriteFile(updated_fname, data)
+ updated_fname = tools.get_output_filename('image-updated.bin')
+ tools.write_file(updated_fname, data)
outdir = os.path.join(self._indir, 'extract')
einfos = control.ExtractEntries(updated_fname, None, outdir, [])
expected1 = b'x' + U_BOOT_DATA + b'y'
u_boot_fname1 = os.path.join(outdir, 'u-boot')
- tools.WriteFile(u_boot_fname1, expected1)
+ tools.write_file(u_boot_fname1, expected1)
expected2 = b'a' + U_BOOT_DATA + b'b'
u_boot_fname2 = os.path.join(outdir, 'u-boot2')
- tools.WriteFile(u_boot_fname2, expected2)
+ tools.write_file(u_boot_fname2, expected2)
expected_text = b'not the same text'
text_fname = os.path.join(outdir, 'text')
- tools.WriteFile(text_fname, expected_text)
+ tools.write_file(text_fname, expected_text)
dtb_fname = os.path.join(outdir, 'u-boot-dtb')
dtb = fdt.FdtScan(dtb_fname)
fname = os.path.join(tmpdir, 'update-u-boot.bin')
expected = b'x' * len(U_BOOT_DATA)
- tools.WriteFile(fname, expected)
+ tools.write_file(fname, expected)
self._DoBinman('replace', '-i', updated_fname, 'u-boot', '-f', fname)
- data = tools.ReadFile(updated_fname)
+ data = tools.read_file(updated_fname)
self.assertEqual(expected, data[:len(expected)])
map_fname = os.path.join(tmpdir, 'image-updated.map')
self.assertFalse(os.path.exists(map_fname))
self._DoBinman('replace', '-i', updated_fname, '-I', outdir,
'u-boot2', 'text')
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
image = Image.FromFile(updated_fname)
image.LoadData()
entries = image.GetEntries()
fname = os.path.join(self._indir, 'update-u-boot.bin')
expected = b'x' * len(U_BOOT_DATA)
- tools.WriteFile(fname, expected)
+ tools.write_file(fname, expected)
self._DoBinman('replace', '-i', updated_fname, 'u-boot',
'-f', fname, '-m')
def testReplaceNoEntryPaths(self):
"""Test replacing an entry without an entry path"""
self._DoReadFileRealDtb('143_replace_all.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
with self.assertRaises(ValueError) as e:
control.ReplaceEntries(image_fname, 'fname', None, [])
self.assertIn('Must specify an entry path to read with -f',
def testReplaceTooManyEntryPaths(self):
"""Test extracting some entries"""
self._DoReadFileRealDtb('143_replace_all.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
with self.assertRaises(ValueError) as e:
control.ReplaceEntries(image_fname, 'fname', None, ['a', 'b'])
self.assertIn('Must specify exactly one entry path to write with -f',
data = self._DoReadFile(dts)
sym_values = struct.pack('<LQLL', *expected_vals)
upto1 = 4 + len(U_BOOT_SPL_DATA)
- expected1 = tools.GetBytes(0xff, 4) + sym_values + U_BOOT_SPL_DATA[20:]
+ expected1 = tools.get_bytes(0xff, 4) + sym_values + U_BOOT_SPL_DATA[20:]
self.assertEqual(expected1, data[:upto1])
upto2 = upto1 + 1 + len(U_BOOT_SPL_DATA)
- expected2 = tools.GetBytes(0xff, 1) + sym_values + U_BOOT_SPL_DATA[20:]
+ expected2 = tools.get_bytes(0xff, 1) + sym_values + U_BOOT_SPL_DATA[20:]
self.assertEqual(expected2, data[upto1:upto2])
upto3 = 0x34 + len(U_BOOT_DATA)
- expected3 = tools.GetBytes(0xff, 1) + U_BOOT_DATA
+ expected3 = tools.get_bytes(0xff, 1) + U_BOOT_DATA
self.assertEqual(expected3, data[upto2:upto3])
expected4 = sym_values + U_BOOT_TPL_DATA[20:]
"""Test that zero-size overlapping regions are ignored"""
self._DoTestFile('160_pack_overlap_zero.dts')
- def testSimpleFit(self):
- """Test an image with a FIT inside"""
- data = self._DoReadFile('161_fit.dts')
- self.assertEqual(U_BOOT_DATA, data[:len(U_BOOT_DATA)])
- self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
- fit_data = data[len(U_BOOT_DATA):-len(U_BOOT_NODTB_DATA)]
-
+ def _CheckSimpleFitData(self, fit_data, kernel_data, fdt1_data):
# The data should be inside the FIT
dtb = fdt.Fdt.FromData(fit_data)
dtb.Scan()
self.assertIn('data', fnode.props)
fname = os.path.join(self._indir, 'fit_data.fit')
- tools.WriteFile(fname, fit_data)
- out = tools.Run('dumpimage', '-l', fname)
+ tools.write_file(fname, fit_data)
+ out = tools.run('dumpimage', '-l', fname)
# Check a few features to make sure the plumbing works. We don't need
# to test the operation of mkimage or dumpimage here. First convert the
self.assertIsNotNone(data_sizes)
self.assertEqual(2, len(data_sizes))
# Format is "4 Bytes = 0.00 KiB = 0.00 MiB" so take the first word
- self.assertEqual(len(U_BOOT_DATA), int(data_sizes[0].split()[0]))
- self.assertEqual(len(U_BOOT_SPL_DTB_DATA), int(data_sizes[1].split()[0]))
+ self.assertEqual(len(kernel_data), int(data_sizes[0].split()[0]))
+ self.assertEqual(len(fdt1_data), int(data_sizes[1].split()[0]))
+
+ def testSimpleFit(self):
+ """Test an image with a FIT inside"""
+ data = self._DoReadFile('161_fit.dts')
+ self.assertEqual(U_BOOT_DATA, data[:len(U_BOOT_DATA)])
+ self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
+ fit_data = data[len(U_BOOT_DATA):-len(U_BOOT_NODTB_DATA)]
+
+ self._CheckSimpleFitData(fit_data, U_BOOT_DATA, U_BOOT_SPL_DTB_DATA)
+
+ def testSimpleFitExpandsSubentries(self):
+ """Test that FIT images expand their subentries"""
+ data = self._DoReadFileDtb('161_fit.dts', use_expanded=True)[0]
+ self.assertEqual(U_BOOT_EXP_DATA, data[:len(U_BOOT_EXP_DATA)])
+ self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
+ fit_data = data[len(U_BOOT_EXP_DATA):-len(U_BOOT_NODTB_DATA)]
+
+ self._CheckSimpleFitData(fit_data, U_BOOT_EXP_DATA, U_BOOT_SPL_DTB_DATA)
+
+ def testSimpleFitImagePos(self):
+ """Test that we have correct image-pos for FIT subentries"""
+ data, _, _, out_dtb_fname = self._DoReadFileDtb('161_fit.dts',
+ update_dtb=True)
+ dtb = fdt.Fdt(out_dtb_fname)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, BASE_DTB_PROPS + REPACK_DTB_PROPS)
+
+ self.assertEqual({
+ 'image-pos': 0,
+ 'offset': 0,
+ 'size': 1890,
+
+ 'u-boot:image-pos': 0,
+ 'u-boot:offset': 0,
+ 'u-boot:size': 4,
+
+ 'fit:image-pos': 4,
+ 'fit:offset': 4,
+ 'fit:size': 1840,
+
+ 'fit/images/kernel:image-pos': 160,
+ 'fit/images/kernel:offset': 156,
+ 'fit/images/kernel:size': 4,
+
+ 'fit/images/kernel/u-boot:image-pos': 160,
+ 'fit/images/kernel/u-boot:offset': 0,
+ 'fit/images/kernel/u-boot:size': 4,
+
+ 'fit/images/fdt-1:image-pos': 456,
+ 'fit/images/fdt-1:offset': 452,
+ 'fit/images/fdt-1:size': 6,
+
+ 'fit/images/fdt-1/u-boot-spl-dtb:image-pos': 456,
+ 'fit/images/fdt-1/u-boot-spl-dtb:offset': 0,
+ 'fit/images/fdt-1/u-boot-spl-dtb:size': 6,
+
+ 'u-boot-nodtb:image-pos': 1844,
+ 'u-boot-nodtb:offset': 1844,
+ 'u-boot-nodtb:size': 46,
+ }, props)
+
+ # Actually check the data is where we think it is
+ for node, expected in [
+ ("u-boot", U_BOOT_DATA),
+ ("fit/images/kernel", U_BOOT_DATA),
+ ("fit/images/kernel/u-boot", U_BOOT_DATA),
+ ("fit/images/fdt-1", U_BOOT_SPL_DTB_DATA),
+ ("fit/images/fdt-1/u-boot-spl-dtb", U_BOOT_SPL_DTB_DATA),
+ ("u-boot-nodtb", U_BOOT_NODTB_DATA),
+ ]:
+ image_pos = props[f"{node}:image-pos"]
+ size = props[f"{node}:size"]
+ self.assertEqual(len(expected), size)
+ self.assertEqual(expected, data[image_pos:image_pos+size])
def testFitExternal(self):
"""Test an image with an FIT with external images"""
# Size of the external-data region as set up by mkimage
external_data_size = len(U_BOOT_DATA) + 2
expected_size = (len(U_BOOT_DATA) + 0x400 +
- tools.Align(external_data_size, 4) +
+ tools.align(external_data_size, 4) +
len(U_BOOT_NODTB_DATA))
# The data should be outside the FIT
self.assertEqual(U_BOOT_DATA + b'aa',
data[actual_pos:actual_pos + external_data_size])
+ def testFitExternalImagePos(self):
+ """Test that we have correct image-pos for external FIT subentries"""
+ data, _, _, out_dtb_fname = self._DoReadFileDtb('162_fit_external.dts',
+ update_dtb=True)
+ dtb = fdt.Fdt(out_dtb_fname)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, BASE_DTB_PROPS + REPACK_DTB_PROPS)
+
+ self.assertEqual({
+ 'image-pos': 0,
+ 'offset': 0,
+ 'size': 1082,
+
+ 'u-boot:image-pos': 0,
+ 'u-boot:offset': 0,
+ 'u-boot:size': 4,
+
+ 'fit:size': 1032,
+ 'fit:offset': 4,
+ 'fit:image-pos': 4,
+
+ 'fit/images/kernel:size': 4,
+ 'fit/images/kernel:offset': 1024,
+ 'fit/images/kernel:image-pos': 1028,
+
+ 'fit/images/kernel/u-boot:size': 4,
+ 'fit/images/kernel/u-boot:offset': 0,
+ 'fit/images/kernel/u-boot:image-pos': 1028,
+
+ 'fit/images/fdt-1:size': 2,
+ 'fit/images/fdt-1:offset': 1028,
+ 'fit/images/fdt-1:image-pos': 1032,
+
+ 'fit/images/fdt-1/_testing:size': 2,
+ 'fit/images/fdt-1/_testing:offset': 0,
+ 'fit/images/fdt-1/_testing:image-pos': 1032,
+
+ 'u-boot-nodtb:image-pos': 1036,
+ 'u-boot-nodtb:offset': 1036,
+ 'u-boot-nodtb:size': 46,
+ }, props)
+
+ # Actually check the data is where we think it is
+ for node, expected in [
+ ("u-boot", U_BOOT_DATA),
+ ("fit/images/kernel", U_BOOT_DATA),
+ ("fit/images/kernel/u-boot", U_BOOT_DATA),
+ ("fit/images/fdt-1", b'aa'),
+ ("fit/images/fdt-1/_testing", b'aa'),
+ ("u-boot-nodtb", U_BOOT_NODTB_DATA),
+ ]:
+ image_pos = props[f"{node}:image-pos"]
+ size = props[f"{node}:size"]
+ self.assertEqual(len(expected), size)
+ self.assertEqual(expected, data[image_pos:image_pos+size])
+
def testFitMissing(self):
"""Test that binman still produces a FIT image if mkimage is missing"""
with test_util.capture_sys_output() as (_, stderr):
"""Test pad-before, pad-after for entries in sections"""
data, _, _, out_dtb_fname = self._DoReadFileDtb(
'166_pad_in_sections.dts', update_dtb=True)
- expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) +
- U_BOOT_DATA + tools.GetBytes(ord('!'), 6) +
+ expected = (U_BOOT_DATA + tools.get_bytes(ord('!'), 12) +
+ U_BOOT_DATA + tools.get_bytes(ord('!'), 6) +
U_BOOT_DATA)
self.assertEqual(expected, data)
def testFitImageSubentryAlignment(self):
"""Test relative alignability of FIT image subentries"""
+ self._SetupSplElf()
entry_args = {
'test-id': TEXT_DATA,
}
node = dtb.GetNode('/images/kernel')
data = dtb.GetProps(node)["data"].bytes
align_pad = 0x10 - (len(U_BOOT_SPL_DATA) % 0x10)
- expected = (tools.GetBytes(0, 0x20) + U_BOOT_SPL_DATA +
- tools.GetBytes(0, align_pad) + U_BOOT_DATA)
+ expected = (tools.get_bytes(0, 0x20) + U_BOOT_SPL_DATA +
+ tools.get_bytes(0, align_pad) + U_BOOT_DATA)
self.assertEqual(expected, data)
node = dtb.GetNode('/images/fdt-1')
data = dtb.GetProps(node)["data"].bytes
- expected = (U_BOOT_SPL_DTB_DATA + tools.GetBytes(0, 20) +
- tools.ToBytes(TEXT_DATA) + tools.GetBytes(0, 30) +
+ expected = (U_BOOT_SPL_DTB_DATA + tools.get_bytes(0, 20) +
+ tools.to_bytes(TEXT_DATA) + tools.get_bytes(0, 30) +
U_BOOT_DTB_DATA)
self.assertEqual(expected, data)
def testSkipAtStartPad(self):
"""Test handling of skip-at-start section with padded entry"""
data = self._DoReadFile('178_skip_at_start_pad.dts')
- before = tools.GetBytes(0, 8)
- after = tools.GetBytes(0, 4)
+ before = tools.get_bytes(0, 8)
+ after = tools.get_bytes(0, 4)
all = before + U_BOOT_DATA + after
self.assertEqual(all, data)
def testSkipAtStartSectionPad(self):
"""Test handling of skip-at-start section with padding"""
data = self._DoReadFile('179_skip_at_start_section_pad.dts')
- before = tools.GetBytes(0, 8)
- after = tools.GetBytes(0, 4)
+ before = tools.get_bytes(0, 8)
+ after = tools.get_bytes(0, 4)
all = before + U_BOOT_DATA + after
self.assertEqual(all, data)
def testSectionPad(self):
"""Testing padding with sections"""
data = self._DoReadFile('180_section_pad.dts')
- expected = (tools.GetBytes(ord('&'), 3) +
- tools.GetBytes(ord('!'), 5) +
+ expected = (tools.get_bytes(ord('&'), 3) +
+ tools.get_bytes(ord('!'), 5) +
U_BOOT_DATA +
- tools.GetBytes(ord('!'), 1) +
- tools.GetBytes(ord('&'), 2))
+ tools.get_bytes(ord('!'), 1) +
+ tools.get_bytes(ord('&'), 2))
self.assertEqual(expected, data)
def testSectionAlign(self):
"""Testing alignment with sections"""
data = self._DoReadFileDtb('181_section_align.dts', map=True)[0]
expected = (b'\0' + # fill section
- tools.GetBytes(ord('&'), 1) + # padding to section align
+ tools.get_bytes(ord('&'), 1) + # padding to section align
b'\0' + # fill section
- tools.GetBytes(ord('!'), 3) + # padding to u-boot align
+ tools.get_bytes(ord('!'), 3) + # padding to u-boot align
U_BOOT_DATA +
- tools.GetBytes(ord('!'), 4) + # padding to u-boot size
- tools.GetBytes(ord('!'), 4)) # padding to section size
+ tools.get_bytes(ord('!'), 4) + # padding to u-boot size
+ tools.get_bytes(ord('!'), 4)) # padding to section size
self.assertEqual(expected, data)
def testCompressImage(self):
'188_image_entryarg.dts',use_real_dtb=True, update_dtb=True,
entry_args=entry_args)
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
orig_image = control.images['image']
# This should not generate an error about the missing 'cros-ec-rw-path'
def testReadImageSkip(self):
"""Test reading an image and accessing its FDT map"""
data = self.data = self._DoReadFileRealDtb('191_read_image_skip.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
orig_image = control.images['image']
image = Image.FromFile(image_fname)
self.assertEqual(orig_image.GetEntries().keys(),
# ELF file with a '__bss_size' symbol
self._SetupTplElf()
data = self._DoReadFile('193_tpl_bss_pad.dts')
- self.assertEqual(U_BOOT_TPL_DATA + tools.GetBytes(0, 10) + U_BOOT_DATA,
+ self.assertEqual(U_BOOT_TPL_DATA + tools.get_bytes(0, 10) + U_BOOT_DATA,
data)
def testTplBssPadMissing(self):
"""Test a collection"""
data = self._DoReadFile('198_collection.dts')
self.assertEqual(U_BOOT_NODTB_DATA + U_BOOT_DTB_DATA +
- tools.GetBytes(0xff, 2) + U_BOOT_NODTB_DATA +
- tools.GetBytes(0xfe, 3) + U_BOOT_DTB_DATA,
+ tools.get_bytes(0xff, 2) + U_BOOT_NODTB_DATA +
+ tools.get_bytes(0xfe, 3) + U_BOOT_DTB_DATA,
data)
def testCollectionSection(self):
# missing.
data = self._DoReadFile('199_collection_section.dts')
section = U_BOOT_NODTB_DATA + U_BOOT_DTB_DATA
- self.assertEqual(section + U_BOOT_DATA + tools.GetBytes(0xff, 2) +
- section + tools.GetBytes(0xfe, 3) + U_BOOT_DATA,
+ self.assertEqual(section + U_BOOT_DATA + tools.get_bytes(0xff, 2) +
+ section + tools.get_bytes(0xfe, 3) + U_BOOT_DATA,
data)
def testAlignDefault(self):
"""Test that default alignment works on sections"""
data = self._DoReadFile('200_align_default.dts')
- expected = (U_BOOT_DATA + tools.GetBytes(0, 8 - len(U_BOOT_DATA)) +
+ expected = (U_BOOT_DATA + tools.get_bytes(0, 8 - len(U_BOOT_DATA)) +
U_BOOT_DATA)
# Special alignment for section
- expected += tools.GetBytes(0, 32 - len(expected))
+ expected += tools.get_bytes(0, 32 - len(expected))
# No alignment within the nested section
expected += U_BOOT_DATA + U_BOOT_NODTB_DATA;
# Now the final piece, which should be default-aligned
- expected += tools.GetBytes(0, 88 - len(expected)) + U_BOOT_NODTB_DATA
+ expected += tools.get_bytes(0, 88 - len(expected)) + U_BOOT_NODTB_DATA
self.assertEqual(expected, data)
def testPackOpenSBI(self):
def testSectionsSingleThread(self):
"""Test sections without multithreading"""
data = self._DoReadFileDtb('055_sections.dts', threads=0)[0]
- expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) +
- U_BOOT_DATA + tools.GetBytes(ord('a'), 12) +
- U_BOOT_DATA + tools.GetBytes(ord('&'), 4))
+ expected = (U_BOOT_DATA + tools.get_bytes(ord('!'), 12) +
+ U_BOOT_DATA + tools.get_bytes(ord('a'), 12) +
+ U_BOOT_DATA + tools.get_bytes(ord('&'), 4))
self.assertEqual(expected, data)
def testThreadTimeout(self):
# definition in the correct place
syms = elf.GetSymbolFileOffset(infile,
['dtb_embed_begin', 'dtb_embed_end'])
- data = tools.ReadFile(outfile)
+ data = tools.read_file(outfile)
dtb_data = data[syms['dtb_embed_begin'].offset:
syms['dtb_embed_end'].offset]
# Set up a version file to make sure that works
version = 'v2025.01-rc2'
- tools.WriteFile(os.path.join(self._indir, 'version'), version,
+ tools.write_file(os.path.join(self._indir, 'version'), version,
binary=False)
self.assertEqual(version, state.GetVersion(self._indir))
# Check that we can read it and it can be scanning, meaning it does
# not have a 16-byte fdtmap header
- data = tools.ReadFile(dtb)
+ data = tools.read_file(dtb)
dtb = fdt.Fdt.FromData(data)
dtb.Scan()
fname = os.path.join(tmpdir, 'fdt.dtb')
self._DoBinman('extract', '-i', updated_fname, '-F', 'dummy',
'-f', fname, 'u-boot')
- data = tools.ReadFile(fname)
+ data = tools.read_file(fname)
self.assertEqual(U_BOOT_DATA, data)
finally:
fdtmap_data = data[fdtmap.image_pos:fdtmap.image_pos + fdtmap.size]
magic = fdtmap_data[:8]
self.assertEqual(b'_FDTMAP_', magic)
- self.assertEqual(tools.GetBytes(0, 8), fdtmap_data[8:16])
+ self.assertEqual(tools.get_bytes(0, 8), fdtmap_data[8:16])
fdt_data = fdtmap_data[16:]
dtb = fdt.Fdt.FromData(fdt_data)
def testFipExtractOneEntry(self):
"""Test extracting a single entry fron an FIP"""
self._DoReadFileRealDtb('207_fip_ls.dts')
- image_fname = tools.GetOutputFilename('image.bin')
+ image_fname = tools.get_output_filename('image.bin')
fname = os.path.join(self._indir, 'output.extact')
control.ExtractEntries(image_fname, fname, None, ['atf-fip/u-boot'])
- data = tools.ReadFile(fname)
+ data = tools.read_file(fname)
self.assertEqual(U_BOOT_DATA, data)
def testFipReplace(self):
"""Test replacing a single file in a FIP"""
- expected = U_BOOT_DATA + tools.GetBytes(0x78, 50)
+ expected = U_BOOT_DATA + tools.get_bytes(0x78, 50)
data = self._DoReadFileRealDtb('208_fip_replace.dts')
- updated_fname = tools.GetOutputFilename('image-updated.bin')
- tools.WriteFile(updated_fname, data)
+ updated_fname = tools.get_output_filename('image-updated.bin')
+ tools.write_file(updated_fname, data)
entry_name = 'atf-fip/u-boot'
control.WriteEntry(updated_fname, entry_name, expected,
allow_resize=True)
actual = control.ReadEntry(updated_fname, entry_name)
self.assertEqual(expected, actual)
- new_data = tools.ReadFile(updated_fname)
+ new_data = tools.read_file(updated_fname)
hdr, fents = fip_util.decode_fip(new_data)
self.assertEqual(2, len(fents))
self.assertEqual(True, fent.valid)
rest = data[0x60 + len(ATF_BL31_DATA):0x100]
- self.assertEqual(tools.GetBytes(0xff, len(rest)), rest)
+ self.assertEqual(tools.get_bytes(0xff, len(rest)), rest)
def testFipBadAlign(self):
"""Test that an invalid alignment value in a FIP is detected"""
def testFetchBintools(self):
def fail_download(url):
- """Take the tools.Download() function by raising an exception"""
+ """Take the tools.download() function by raising an exception"""
raise urllib.error.URLError('my error')
args = ['tool']
self.assertIn('Please specify bintools to fetch', str(e.exception))
args = ['tool', '--fetch', '_testing']
- with unittest.mock.patch.object(tools, 'Download',
+ with unittest.mock.patch.object(tools, 'download',
side_effect=fail_download):
with test_util.capture_sys_output() as (stdout, _):
self._DoBinman(*args)
finally:
shutil.rmtree(tmpdir)
+ def testFitSubentryUsesBintool(self):
+ """Test that binman FIT subentries can use bintools"""
+ command.test_result = self._HandleGbbCommand
+ entry_args = {
+ 'keydir': 'devkeys',
+ 'bmpblk': 'bmpblk.bin',
+ }
+ data, _, _, _ = self._DoReadFileDtb('220_fit_subentry_bintool.dts',
+ entry_args=entry_args)
+
+ expected = (GBB_DATA + GBB_DATA + tools.get_bytes(0, 8) +
+ tools.get_bytes(0, 0x2180 - 16))
+ self.assertIn(expected, data)
+
+ def testFitSubentryMissingBintool(self):
+ """Test that binman reports missing bintools for FIT subentries"""
+ entry_args = {
+ 'keydir': 'devkeys',
+ }
+ with test_util.capture_sys_output() as (_, stderr):
+ self._DoTestFile('220_fit_subentry_bintool.dts',
+ force_missing_bintools='futility', entry_args=entry_args)
+ err = stderr.getvalue()
+ self.assertRegex(err,
+ "Image 'main-section'.*missing bintools.*: futility")
+
+ def testFitSubentryHashSubnode(self):
+ """Test an image with a FIT inside"""
+ data, _, _, out_dtb_name = self._DoReadFileDtb(
+ '221_fit_subentry_hash.dts', use_real_dtb=True, update_dtb=True)
+
+ mkimage_dtb = fdt.Fdt.FromData(data)
+ mkimage_dtb.Scan()
+ binman_dtb = fdt.Fdt(out_dtb_name)
+ binman_dtb.Scan()
+
+ # Check that binman didn't add hash values
+ fnode = binman_dtb.GetNode('/binman/fit/images/kernel/hash')
+ self.assertNotIn('value', fnode.props)
+
+ fnode = binman_dtb.GetNode('/binman/fit/images/fdt-1/hash')
+ self.assertNotIn('value', fnode.props)
+
+ # Check that mkimage added hash values
+ fnode = mkimage_dtb.GetNode('/images/kernel/hash')
+ self.assertIn('value', fnode.props)
+
+ fnode = mkimage_dtb.GetNode('/images/fdt-1/hash')
+ self.assertIn('value', fnode.props)
+
+ def testPackTeeOs(self):
+ """Test that an image with an TEE binary can be created"""
+ data = self._DoReadFile('222_tee_os.dts')
+ self.assertEqual(TEE_OS_DATA, data[:len(TEE_OS_DATA)])
+
+ def testFitFdtOper(self):
+ """Check handling of a specified FIT operation"""
+ entry_args = {
+ 'of-list': 'test-fdt1 test-fdt2',
+ 'default-dt': 'test-fdt2',
+ }
+ self._DoReadFileDtb(
+ '223_fit_fdt_oper.dts',
+ entry_args=entry_args,
+ extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
+
+ def testFitFdtBadOper(self):
+ """Check handling of an FDT map when the section cannot be found"""
+ with self.assertRaises(ValueError) as exc:
+ self._DoReadFileDtb('224_fit_bad_oper.dts')
+ self.assertIn("Node '/binman/fit': Unknown operation 'unknown'",
+ str(exc.exception))
+
if __name__ == "__main__":
unittest.main()
Raises:
ValueError if something goes wrong
"""
- data = tools.ReadFile(fname)
+ data = tools.read_file(fname)
size = len(data)
# First look for an image header
dtb_size = probe_dtb.GetFdtObj().totalsize()
fdtmap_data = data[pos:pos + dtb_size + fdtmap.FDTMAP_HDR_LEN]
fdt_data = fdtmap_data[fdtmap.FDTMAP_HDR_LEN:]
- out_fname = tools.GetOutputFilename('fdtmap.in.dtb')
- tools.WriteFile(out_fname, fdt_data)
+ out_fname = tools.get_output_filename('fdtmap.in.dtb')
+ tools.write_file(out_fname, fdt_data)
dtb = fdt.Fdt(out_fname)
dtb.Scan()
def BuildImage(self):
"""Write the image to a file"""
- fname = tools.GetOutputFilename(self._filename)
- tout.Info("Writing image to '%s'" % fname)
+ fname = tools.get_output_filename(self._filename)
+ tout.info("Writing image to '%s'" % fname)
with open(fname, 'wb') as fd:
data = self.GetPaddedData()
fd.write(data)
- tout.Info("Wrote %#x bytes" % len(data))
+ tout.info("Wrote %#x bytes" % len(data))
def WriteMap(self):
"""Write a map of the image to a .map file
Filename of map file written
"""
filename = '%s.map' % self.image_name
- fname = tools.GetOutputFilename(filename)
+ fname = tools.get_output_filename(filename)
with open(fname, 'w') as fd:
print('%8s %8s %8s %s' % ('ImagePos', 'Offset', 'Size', 'Name'),
file=fd)
return entry
def ReadData(self, decomp=True, alt_format=None):
- tout.Debug("Image '%s' ReadData(), size=%#x" %
+ tout.debug("Image '%s' ReadData(), size=%#x" %
(self.GetPath(), len(self._data)))
return self._data
# Run the entry tests first ,since these need to be the first to import the
# 'entry' module.
- test_util.RunTestSuites(
+ test_util.run_test_suites(
result, debug, verbosity, test_preserve_dirs, processes, test_name,
toolpath,
[bintool_test.TestBintool, entry_test.TestEntry, ftest.TestFunctional,
fdt_test.TestFdt, elf_test.TestElf, image_test.TestImage,
cbfs_util_test.TestCbfs, fip_util_test.TestFip])
- return test_util.ReportResult('binman', test_name, result)
+ return test_util.report_result('binman', test_name, result)
def RunTestCoverage(toolpath):
"""Run the tests and check that we get 100% coverage"""
if toolpath:
for path in toolpath:
extra_args += ' --toolpath %s' % path
- test_util.RunTestCoverage('tools/binman/binman', None,
+ test_util.run_test_coverage('tools/binman/binman', None,
['*test*', '*main.py', 'tools/patman/*', 'tools/dtoc/*'],
args.build_dir, all_set, extra_args or None)
If CONFIG_WDT_K3_RTI_LOAD_FW is enabled, a firmware image is needed for
the R5F core(s) to trigger the system reset. One possible source is
https://github.com/siemens/k3-rti-wdt.
+
+tee-os:
+See the documentation for your board. You may need to build Open Portable
+Trusted Execution Environment (OP-TEE) with TEE=/path/to/tee.bin
data = GetFdtForEtype(etype).GetContents()
else:
fname = output_fdt_info[etype][1]
- pathname = tools.GetInputFilename(fname)
- data = tools.ReadFile(pathname)
+ pathname = tools.get_input_filename(fname)
+ data = tools.read_file(pathname)
return pathname, data
def UpdateFdtContents(etype, data):
"""
dtb, fname = output_fdt_info[etype]
dtb_fname = dtb.GetFilename()
- tools.WriteFile(dtb_fname, data)
+ tools.write_file(dtb_fname, data)
dtb = fdt.FdtScan(dtb_fname)
output_fdt_info[etype] = [dtb, fname]
global entry_args
entry_args = {}
- tout.Debug('Processing entry args:')
+ tout.debug('Processing entry args:')
if args:
for arg in args:
m = re.match('([^=]*)=(.*)', arg)
if not m:
raise ValueError("Invalid entry arguemnt '%s'" % arg)
name, value = m.groups()
- tout.Debug(' %20s = %s' % (name, value))
+ tout.debug(' %20s = %s' % (name, value))
entry_args[name] = value
- tout.Debug('Processing entry args done')
+ tout.debug('Processing entry args done')
def GetEntryArg(name):
"""Get the value of an entry argument
else:
fdt_set = {}
for etype, fname in DTB_TYPE_FNAME.items():
- infile = tools.GetInputFilename(fname, allow_missing=True)
+ infile = tools.get_input_filename(fname, allow_missing=True)
if infile and os.path.exists(infile):
fname_dtb = fdt_util.EnsureCompiled(infile)
- out_fname = tools.GetOutputFilename('%s.out' %
+ out_fname = tools.get_output_filename('%s.out' %
os.path.split(fname)[1])
- tools.WriteFile(out_fname, tools.ReadFile(fname_dtb))
+ tools.write_file(out_fname, tools.read_file(fname_dtb))
other_dtb = fdt.FdtScan(out_fname)
output_fdt_info[etype] = [other_dtb, out_fname]
"""
global output_fdt_info, main_dtb, fdt_path_prefix
- tout.Info('Preparing device trees')
+ tout.info('Preparing device trees')
output_fdt_info.clear()
fdt_path_prefix = ''
output_fdt_info['fdtmap'] = [image.fdtmap_dtb, 'u-boot.dtb']
main_dtb = None
- tout.Info(" Found device tree type 'fdtmap' '%s'" % image.fdtmap_dtb.name)
+ tout.info(" Found device tree type 'fdtmap' '%s'" % image.fdtmap_dtb.name)
for etype, value in image.GetFdts().items():
entry, fname = value
- out_fname = tools.GetOutputFilename('%s.dtb' % entry.etype)
- tout.Info(" Found device tree type '%s' at '%s' path '%s'" %
+ out_fname = tools.get_output_filename('%s.dtb' % entry.etype)
+ tout.info(" Found device tree type '%s' at '%s' path '%s'" %
(etype, out_fname, entry.GetPath()))
entry._filename = entry.GetDefaultFilename()
data = entry.ReadData()
- tools.WriteFile(out_fname, data)
+ tools.write_file(out_fname, data)
dtb = fdt.Fdt(out_fname)
dtb.Scan()
image_node = dtb.GetNode('/binman')
image_node = dtb.GetNode('/binman/%s' % image.image_node)
fdt_path_prefix = image_node.path
output_fdt_info[etype] = [dtb, None]
- tout.Info(" FDT path prefix '%s'" % fdt_path_prefix)
+ tout.info(" FDT path prefix '%s'" % fdt_path_prefix)
def GetAllFdts():
for_repack: True is this property is only needed for repacking
"""
for n in GetUpdateNodes(node, for_repack):
- tout.Detail("File %s: Update node '%s' prop '%s' to %#x" %
+ tout.detail("File %s: Update node '%s' prop '%s' to %#x" %
(n.GetFdt().name, n.path, prop, value))
n.SetInt(prop, value)
if algo.value == 'sha256':
size = 32
else:
- return "Unknown hash algorithm '%s'" % algo
+ return "Unknown hash algorithm '%s'" % algo.value
for n in GetUpdateNodes(hash_node):
n.AddEmptyProp('value', size)
"""
version_fname = os.path.join(path, 'version')
if os.path.exists(version_fname):
- version = tools.ReadFile(version_fname, binary=False)
+ version = tools.read_file(version_fname, binary=False)
else:
version = '(unreleased)'
return version
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ fit {
+ description = "test-desc";
+ #address-cells = <1>;
+
+ images {
+ test {
+ description = "Something using a bintool";
+ type = "kernel";
+ arch = "arm";
+ os = "linux";
+ compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
+
+ gbb {
+ size = <0x2180>;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ description = "Boot bintool output";
+ kernel = "kernel";
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ fit {
+ description = "test-desc";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Vanilla Linux kernel";
+ type = "kernel";
+ arch = "ppc";
+ os = "linux";
+ compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
+ hash {
+ algo = "sha1";
+ };
+ u-boot {
+ };
+ };
+ fdt-1 {
+ description = "Flattened Device Tree blob";
+ type = "flat_dt";
+ arch = "ppc";
+ compression = "none";
+ hash {
+ algo = "crc32";
+ };
+ u-boot-spl-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ description = "Boot Linux kernel with FDT blob";
+ kernel = "kernel";
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ tee-os {
+ filename = "tee-pager.bin";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ fit {
+ description = "test-desc";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+
+ images {
+ kernel {
+ description = "Vanilla Linux kernel";
+ type = "kernel";
+ arch = "ppc";
+ os = "linux";
+ compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
+ hash-1 {
+ algo = "crc32";
+ };
+ hash-2 {
+ algo = "sha1";
+ };
+ u-boot {
+ };
+ };
+ @fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
+ description = "fdt-NAME.dtb";
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+ @config-SEQ {
+ description = "conf-NAME.dtb";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt-SEQ";
+ };
+ };
+ };
+ u-boot-nodtb {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ fit {
+ description = "test-desc";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+
+ images {
+ @fdt-SEQ {
+ fit,operation = "unknown";
+ description = "fdt-NAME.dtb";
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+ };
+ fdtmap {
+ };
+ };
+};
LDS_BINMAN_BAD := -T $(SRC)u_boot_binman_syms_bad.lds
LDS_BINMAN_X86 := -T $(SRC)u_boot_binman_syms_x86.lds
LDS_BINMAN_EMBED := -T $(SRC)u_boot_binman_embed.lds
+LDS_EFL_SECTIONS := -T $(SRC)elf_sections.lds
TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data \
u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \
u_boot_binman_syms_size u_boot_binman_syms_x86 embed_data \
- u_boot_binman_embed u_boot_binman_embed_sm
+ u_boot_binman_embed u_boot_binman_embed_sm elf_sections
all: $(TARGETS)
u_boot_binman_embed_sm: CFLAGS += $(LDS_BINMAN_EMBED)
u_boot_binman_embed_sm: u_boot_binman_embed_sm.c
+elf_sections: CFLAGS += $(LDS_EFL_SECTIONS)
+elf_sections: elf_sections.c
+
clean:
rm -f $(TARGETS)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Google LLC
+ *
+ * Program containing two text sections
+ */
+
+int __attribute__((section(".sram_data"))) data[29];
+
+int __attribute__((section(".sram_code"))) calculate(int x)
+{
+ data[0] = x;
+
+ return x * x;
+}
+
+int main(void)
+{
+ return calculate(123);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000010;
+ _start = .;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = 0x00001000;
+ .sram :
+ {
+ *(.sram*)
+ }
+
+ /DISCARD/ : {
+ *(.comment)
+ *(.dyn*)
+ }
+}
specify the output directory with -o when using -w.
+Changing the configuration
+==========================
+
+Sometimes it is useful to change the CONFIG options for a build on the fly. This
+can be used to build a board (or multiple) with a few changes to see the impact.
+The -a option supports this:
+
+ -a <cfg>
+
+where <cfg> is a CONFIG option (with or without the CONFIG_ prefix) to enable.
+For example:
+
+ buildman -a CMD_SETEXPR_FMT
+
+will build with CONFIG_CMD_SETEXPR_FMT enabled.
+
+You can disable options by preceding them with tilde (~). You can specify the
+-a option multiple times:
+
+ buildman -a CMD_SETEXPR_FMT -a ~CMDLINE
+
+Some options have values, in which case you can change them:
+
+ buildman -a 'BOOTCOMMAND="echo hello"' CONFIG_SYS_LOAD_ADDR=0x1000
+
+Note that you must put quotes around string options and the whole thing must be
+in single quotes, to make sure the shell leave it alone.
+
+If you try to set an option that does not exist, or that cannot be changed for
+some other reason (e.g. it is 'selected' by another option), then buildman
+shows an error:
+
+ buildman --board sandbox -a FRED
+ Building current source for 1 boards (1 thread, 32 jobs per thread)
+ 0 0 0 /1 -1 (starting)errs
+ Some CONFIG adjustments did not take effect. This may be because
+ the request CONFIGs do not exist or conflict with others.
+
+ Failed adjustments:
+
+ FRED Missing expected line: CONFIG_FRED=y
+
+
+One major caveat with this feature with branches (-b) is that buildman does not
+name the output directories differently when you change the configuration, so
+doing the same build again with different configuration will not trigger a
+rebuild. You can use -f to work around that.
+
+
Other options
=============
from patman import command
from patman import gitutil
from patman import terminal
-from patman.terminal import Print
+from patman.terminal import tprint
# This indicates an new int or hex Kconfig property with no default
# It hangs the build since the 'conf' tool cannot proceed without valid input.
mrproper=False, per_board_out_dir=False,
config_only=False, squash_config_y=False,
warnings_as_errors=False, work_in_output=False,
- test_thread_exceptions=False):
+ test_thread_exceptions=False, adjust_cfg=None):
"""Create a new Builder object
Args:
test_thread_exceptions: Uses for tests only, True to make the
threads raise an exception instead of reporting their result.
This simulates a failure in the code somewhere
+ adjust_cfg_list (list of str): List of changes to make to .config
+ file before building. Each is one of (where C is the config
+ option with or without the CONFIG_ prefix)
+
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig
+
"""
self.toolchains = toolchains
self.base_dir = base_dir
self.squash_config_y = squash_config_y
self.config_filenames = BASE_CONFIG_FILENAMES
self.work_in_output = work_in_output
+ self.adjust_cfg = adjust_cfg
+
if not self.squash_config_y:
self.config_filenames += EXTRA_CONFIG_FILENAMES
self._terminated = False
"""
self.commit = commit
if checkout and self.checkout:
- gitutil.Checkout(commit.hash)
+ gitutil.checkout(commit.hash)
def Make(self, commit, brd, stage, cwd, *args, **kwargs):
"""Run make
stage: Stage that we are at (mrproper, config, build)
cwd: Directory where make should be run
args: Arguments to pass to make
- kwargs: Arguments to pass to command.RunPipe()
+ kwargs: Arguments to pass to command.run_pipe()
"""
def check_output(stream, data):
self._restarting_config = False
self._terminated = False
cmd = [self.gnu_make] + list(args)
- result = command.RunPipe([cmd], capture=True, capture_stderr=True,
+ result = command.run_pipe([cmd], capture=True, capture_stderr=True,
cwd=cwd, raise_on_error=False, infile='/dev/null',
output_func=check_output, **kwargs)
if result.already_done:
self.already_done += 1
if self._verbose:
- terminal.PrintClear()
+ terminal.print_clear()
boards_selected = {target : result.brd}
self.ResetResultSummary(boards_selected)
self.ProduceResultSummary(result.commit_upto, self.commits,
# Display separate counts for ok, warned and fail
ok = self.upto - self.warned - self.fail
- line = '\r' + self.col.Color(self.col.GREEN, '%5d' % ok)
- line += self.col.Color(self.col.YELLOW, '%5d' % self.warned)
- line += self.col.Color(self.col.RED, '%5d' % self.fail)
+ line = '\r' + self.col.build(self.col.GREEN, '%5d' % ok)
+ line += self.col.build(self.col.YELLOW, '%5d' % self.warned)
+ line += self.col.build(self.col.RED, '%5d' % self.fail)
line += ' /%-5d ' % self.count
remaining = self.count - self.upto
if remaining:
- line += self.col.Color(self.col.MAGENTA, ' -%-5d ' % remaining)
+ line += self.col.build(self.col.MAGENTA, ' -%-5d ' % remaining)
else:
line += ' ' * 8
line += '%s : ' % self._complete_delay
line += target
- terminal.PrintClear()
- Print(line, newline=False, limit_to_line=True)
+ terminal.print_clear()
+ tprint(line, newline=False, limit_to_line=True)
def _GetOutputDir(self, commit_upto):
"""Get the name of the output directory for a commit number
if line.strip():
size, type, name = line[:-1].split()
except:
- Print("Invalid line in file '%s': '%s'" % (fname, line[:-1]))
+ tprint("Invalid line in file '%s': '%s'" % (fname, line[:-1]))
continue
if type in 'tTdDbB':
# function names begin with '.' on 64-bit powerpc
arch = board_dict[target].arch
else:
arch = 'unknown'
- str = self.col.Color(color, ' ' + target)
+ str = self.col.build(color, ' ' + target)
if not arch in done_arch:
- str = ' %s %s' % (self.col.Color(color, char), str)
+ str = ' %s %s' % (self.col.build(color, char), str)
done_arch[arch] = True
if not arch in arch_list:
arch_list[arch] = str
color = self.col.RED if num > 0 else self.col.GREEN
if num == 0:
return '0'
- return self.col.Color(color, str(num))
+ return self.col.build(color, str(num))
def ResetResultSummary(self, board_selected):
"""Reset the results summary ready for use.
return
args = [self.ColourNum(x) for x in args]
indent = ' ' * 15
- Print('%s%s: add: %s/%s, grow: %s/%s bytes: %s/%s (%s)' %
- tuple([indent, self.col.Color(self.col.YELLOW, fname)] + args))
- Print('%s %-38s %7s %7s %+7s' % (indent, 'function', 'old', 'new',
+ tprint('%s%s: add: %s/%s, grow: %s/%s bytes: %s/%s (%s)' %
+ tuple([indent, self.col.build(self.col.YELLOW, fname)] + args))
+ tprint('%s %-38s %7s %7s %+7s' % (indent, 'function', 'old', 'new',
'delta'))
for diff, name in delta:
if diff:
color = self.col.RED if diff > 0 else self.col.GREEN
msg = '%s %-38s %7s %7s %+7d' % (indent, name,
old.get(name, '-'), new.get(name,'-'), diff)
- Print(msg, colour=color)
+ tprint(msg, colour=color)
def PrintSizeDetail(self, target_list, show_bloat):
color = self.col.RED if diff > 0 else self.col.GREEN
msg = ' %s %+d' % (name, diff)
if not printed_target:
- Print('%10s %-15s:' % ('', result['_target']),
+ tprint('%10s %-15s:' % ('', result['_target']),
newline=False)
printed_target = True
- Print(msg, colour=color, newline=False)
+ tprint(msg, colour=color, newline=False)
if printed_target:
- Print()
+ tprint()
if show_bloat:
target = result['_target']
outcome = result['_outcome']
color = self.col.RED if avg_diff > 0 else self.col.GREEN
msg = ' %s %+1.1f' % (name, avg_diff)
if not printed_arch:
- Print('%10s: (for %d/%d boards)' % (arch, count,
+ tprint('%10s: (for %d/%d boards)' % (arch, count,
arch_count[arch]), newline=False)
printed_arch = True
- Print(msg, colour=color, newline=False)
+ tprint(msg, colour=color, newline=False)
if printed_arch:
- Print()
+ tprint()
if show_detail:
self.PrintSizeDetail(target_list, show_bloat)
col = self.col.RED
elif line[0] == 'c':
col = self.col.YELLOW
- Print(' ' + line, newline=True, colour=col)
+ tprint(' ' + line, newline=True, colour=col)
def _OutputErrLines(err_lines, colour):
"""Output the line of error/warning lines, if not empty
names = [board.target for board in line.boards]
board_str = ' '.join(names) if names else ''
if board_str:
- out = self.col.Color(colour, line.char + '(')
- out += self.col.Color(self.col.MAGENTA, board_str,
+ out = self.col.build(colour, line.char + '(')
+ out += self.col.build(self.col.MAGENTA, board_str,
bright=False)
- out += self.col.Color(colour, ') %s' % line.errline)
+ out += self.col.build(colour, ') %s' % line.errline)
else:
- out = self.col.Color(colour, line.char + line.errline)
+ out = self.col.build(colour, line.char + line.errline)
out_list.append(out)
- Print('\n'.join(out_list))
+ tprint('\n'.join(out_list))
self._error_lines += 1
self.AddOutcome(board_selected, arch_list, unknown_boards, '?',
self.col.MAGENTA)
for arch, target_list in arch_list.items():
- Print('%10s: %s' % (arch, target_list))
+ tprint('%10s: %s' % (arch, target_list))
self._error_lines += 1
_OutputErrLines(better_err, colour=self.col.GREEN)
_OutputErrLines(worse_err, colour=self.col.RED)
_AddConfig(lines, 'all', all_plus, all_minus, all_change)
#arch_summary[target] = '\n'.join(lines)
if lines:
- Print('%s:' % arch)
+ tprint('%s:' % arch)
_OutputConfigInfo(lines)
for lines, targets in lines_by_target.items():
if not lines:
continue
- Print('%s :' % ' '.join(sorted(targets)))
+ tprint('%s :' % ' '.join(sorted(targets)))
_OutputConfigInfo(lines.split('\n'))
if not board in board_dict:
not_built.append(board)
if not_built:
- Print("Boards not built (%d): %s" % (len(not_built),
+ tprint("Boards not built (%d): %s" % (len(not_built),
', '.join(not_built)))
def ProduceResultSummary(self, commit_upto, commits, board_selected):
if commits:
msg = '%02d: %s' % (commit_upto + 1,
commits[commit_upto].subject)
- Print(msg, colour=self.col.BLUE)
+ tprint(msg, colour=self.col.BLUE)
self.PrintResultSummary(board_selected, board_dict,
err_lines if self._show_errors else [], err_line_boards,
warn_lines if self._show_errors else [], warn_line_boards,
for commit_upto in range(0, self.commit_count, self._step):
self.ProduceResultSummary(commit_upto, commits, board_selected)
if not self._error_lines:
- Print('(no errors to report)', colour=self.col.GREEN)
+ tprint('(no errors to report)', colour=self.col.GREEN)
def SetupBuild(self, board_selected, commits):
if os.path.isdir(git_dir):
# This is a clone of the src_dir repo, we can keep using
# it but need to fetch from src_dir.
- Print('\rFetching repo for thread %d' % thread_num,
+ tprint('\rFetching repo for thread %d' % thread_num,
newline=False)
- gitutil.Fetch(git_dir, thread_dir)
- terminal.PrintClear()
+ gitutil.fetch(git_dir, thread_dir)
+ terminal.print_clear()
elif os.path.isfile(git_dir):
# This is a worktree of the src_dir repo, we don't need to
# create it again or update it in any way.
raise ValueError('Git dir %s exists, but is not a file '
'or a directory.' % git_dir)
elif setup_git == 'worktree':
- Print('\rChecking out worktree for thread %d' % thread_num,
+ tprint('\rChecking out worktree for thread %d' % thread_num,
newline=False)
- gitutil.AddWorktree(src_dir, thread_dir)
- terminal.PrintClear()
+ gitutil.add_worktree(src_dir, thread_dir)
+ terminal.print_clear()
elif setup_git == 'clone' or setup_git == True:
- Print('\rCloning repo for thread %d' % thread_num,
+ tprint('\rCloning repo for thread %d' % thread_num,
newline=False)
- gitutil.Clone(src_dir, thread_dir)
- terminal.PrintClear()
+ gitutil.clone(src_dir, thread_dir)
+ terminal.print_clear()
else:
raise ValueError("Can't setup git repo with %s." % setup_git)
builderthread.Mkdir(self._working_dir)
if setup_git and self.git_dir:
src_dir = os.path.abspath(self.git_dir)
- if gitutil.CheckWorktreeIsAvailable(src_dir):
+ if gitutil.check_worktree_is_available(src_dir):
setup_git = 'worktree'
# If we previously added a worktree but the directory for it
# got deleted, we need to prune its files from the repo so
# that we can check out another in its place.
- gitutil.PruneWorktrees(src_dir)
+ gitutil.prune_worktrees(src_dir)
else:
setup_git = 'clone'
"""
to_remove = self._GetOutputSpaceRemovals()
if to_remove:
- Print('Removing %d old build directories...' % len(to_remove),
+ tprint('Removing %d old build directories...' % len(to_remove),
newline=False)
for dirname in to_remove:
shutil.rmtree(dirname)
- terminal.PrintClear()
+ terminal.print_clear()
def BuildBoards(self, commits, board_selected, keep_outputs, verbose):
"""Build all commits for a list of boards
self._PrepareWorkingSpace(min(self.num_threads, len(board_selected)),
commits is not None)
self._PrepareOutputSpace()
- Print('\rStarting build...', newline=False)
+ tprint('\rStarting build...', newline=False)
self.SetupBuild(board_selected, commits)
self.ProcessResult(None)
self.thread_exceptions = []
job.commits = commits
job.keep_outputs = keep_outputs
job.work_in_output = self.work_in_output
+ job.adjust_cfg = self.adjust_cfg
job.step = self._step
if self.num_threads:
self.queue.put(job)
# Wait until we have processed all output
self.out_queue.join()
- Print()
+ tprint()
msg = 'Completed: %d total built' % self.count
if self.already_done:
duration = duration - timedelta(microseconds=duration.microseconds)
rate = float(self.count) / duration.total_seconds()
msg += ', duration %s, rate %1.2f' % (duration, rate)
- Print(msg)
+ tprint(msg)
if self.thread_exceptions:
- Print('Failed: %d thread exceptions' % len(self.thread_exceptions),
+ tprint('Failed: %d thread exceptions' % len(self.thread_exceptions),
colour=self.col.RED)
return (self.fail, self.warned, self.thread_exceptions)
import sys
import threading
+from buildman import cfgutil
from patman import command
from patman import gitutil
config - called to configure for a board
build - the main make invocation - it does the build
args: A list of arguments to pass to 'make'
- kwargs: A list of keyword arguments to pass to command.RunPipe()
+ kwargs: A list of keyword arguments to pass to command.run_pipe()
Returns:
CommandResult object
**kwargs)
def RunCommit(self, commit_upto, brd, work_dir, do_config, config_only,
- force_build, force_build_failures, work_in_output):
+ force_build, force_build_failures, work_in_output,
+ adjust_cfg):
"""Build a particular commit.
If the build is already done, and we are not forcing a build, we skip
failure
work_in_output: Use the output directory as the work directory and
don't write to a separate output directory.
+ adjust_cfg (list of str): List of changes to make to .config file
+ before building. Each is one of (where C is either CONFIG_xxx
+ or just xxx):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig
Returns:
tuple containing:
commit = self.builder.commits[commit_upto]
if self.builder.checkout:
git_dir = os.path.join(work_dir, '.git')
- gitutil.Checkout(commit.hash, git_dir, work_dir,
+ gitutil.checkout(commit.hash, git_dir, work_dir,
force=True)
else:
commit = 'current'
os.remove(fname)
# If we need to reconfigure, do that now
- if do_config:
+ cfg_file = os.path.join(out_dir, '.config')
+ if do_config or adjust_cfg:
config_out = ''
if self.mrproper:
result = self.Make(commit, brd, 'mrproper', cwd,
*(args + config_args), env=env)
config_out += result.combined
do_config = False # No need to configure next time
+ if adjust_cfg:
+ cfgutil.adjust_cfg_file(cfg_file, adjust_cfg)
if result.return_code == 0:
if config_only:
args.append('cfg')
result = self.Make(commit, brd, 'build', cwd, *args,
env=env)
+ if adjust_cfg:
+ errs = cfgutil.check_cfg_file(cfg_file, adjust_cfg)
+ if errs:
+ print('errs', errs)
+ result.stderr += errs
+ result.return_code = 1
result.stderr = result.stderr.replace(src_dir + '/', '')
if self.builder.verbose_build:
result.stdout = config_out + result.stdout
lines = []
for fname in BASE_ELF_FILENAMES:
cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname]
- nm_result = command.RunPipe([cmd], capture=True,
+ nm_result = command.run_pipe([cmd], capture=True,
capture_stderr=True, cwd=result.out_dir,
raise_on_error=False, env=env)
if nm_result.stdout:
print(nm_result.stdout, end=' ', file=fd)
cmd = ['%sobjdump' % self.toolchain.cross, '-h', fname]
- dump_result = command.RunPipe([cmd], capture=True,
+ dump_result = command.run_pipe([cmd], capture=True,
capture_stderr=True, cwd=result.out_dir,
raise_on_error=False, env=env)
rodata_size = ''
rodata_size = fields[2]
cmd = ['%ssize' % self.toolchain.cross, fname]
- size_result = command.RunPipe([cmd], capture=True,
+ size_result = command.run_pipe([cmd], capture=True,
capture_stderr=True, cwd=result.out_dir,
raise_on_error=False, env=env)
if size_result.stdout:
cmd = ['%sobjcopy' % self.toolchain.cross, '-O', 'binary',
'-j', '.rodata.default_environment',
'env/built-in.o', 'uboot.env']
- command.RunPipe([cmd], capture=True,
+ command.run_pipe([cmd], capture=True,
capture_stderr=True, cwd=result.out_dir,
raise_on_error=False, env=env)
ubootenv = os.path.join(result.out_dir, 'uboot.env')
work_dir, do_config, self.builder.config_only,
force_build or self.builder.force_build,
self.builder.force_build_failures,
- work_in_output=job.work_in_output)
+ job.work_in_output, job.adjust_cfg)
failed = result.return_code or result.stderr
did_config = do_config
if failed and not do_config:
if self.builder.force_config_on_failure:
result, request_config = self.RunCommit(commit_upto,
brd, work_dir, True, False, True, False,
- work_in_output=job.work_in_output)
+ job.work_in_output, job.adjust_cfg)
did_config = True
if not self.builder.force_reconfig:
do_config = request_config
# Just build the currently checked-out build
result, request_config = self.RunCommit(None, brd, work_dir, True,
self.builder.config_only, True,
- self.builder.force_build_failures,
- work_in_output=job.work_in_output)
+ self.builder.force_build_failures, job.work_in_output,
+ job.adjust_cfg)
result.commit_upto = 0
self._WriteResult(result, job.keep_outputs, job.work_in_output)
self._SendResult(result)
try:
self.RunJob(job)
except Exception as e:
- print('Thread exception:', e)
+ print('Thread exception (use -T0 to run without threads):', e)
self.builder.thread_exceptions.append(e)
self.builder.queue.task_done()
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2022 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+"""Utility functions for dealing with Kconfig .confing files"""
+
+import re
+
+from patman import tools
+
+RE_LINE = re.compile(r'(# )?CONFIG_([A-Z0-9_]+)(=(.*)| is not set)')
+RE_CFG = re.compile(r'(~?)(CONFIG_)?([A-Z0-9_]+)(=.*)?')
+
+def make_cfg_line(opt, adj):
+ """Make a new config line for an option
+
+ Args:
+ opt (str): Option to process, without CONFIG_ prefix
+ adj (str): Adjustment to make (C is config option without prefix):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig)
+
+ Returns:
+ str: New line to use, one of:
+ CONFIG_opt=y - option is enabled
+ # CONFIG_opt is not set - option is disabled
+ CONFIG_opt=val - option is getting a new value (val is
+ in quotes if this is a string)
+ """
+ if adj[0] == '~':
+ return f'# CONFIG_{opt} is not set'
+ if '=' in adj:
+ return f'CONFIG_{adj}'
+ return f'CONFIG_{opt}=y'
+
+def adjust_cfg_line(line, adjust_cfg, done=None):
+ """Make an adjustment to a single of line from a .config file
+
+ This processes a .config line, producing a new line if a change for this
+ CONFIG is requested in adjust_cfg
+
+ Args:
+ line (str): line to process, e.g. '# CONFIG_FRED is not set' or
+ 'CONFIG_FRED=y' or 'CONFIG_FRED=0x123' or 'CONFIG_FRED="fred"'
+ adjust_cfg (dict of str): Changes to make to .config file before
+ building:
+ key: str config to change, without the CONFIG_ prefix, e.g.
+ FRED
+ value: str change to make (C is config option without prefix):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig)
+ done (set of set): Adds the config option to this set if it is changed
+ in some way. This is used to track which ones have been processed.
+ None to skip.
+
+ Returns:
+ tuple:
+ str: New string for this line (maybe unchanged)
+ str: Adjustment string that was used
+ """
+ out_line = line
+ m_line = RE_LINE.match(line)
+ adj = None
+ if m_line:
+ _, opt, _, _ = m_line.groups()
+ adj = adjust_cfg.get(opt)
+ if adj:
+ out_line = make_cfg_line(opt, adj)
+ if done is not None:
+ done.add(opt)
+
+ return out_line, adj
+
+def adjust_cfg_lines(lines, adjust_cfg):
+ """Make adjustments to a list of lines from a .config file
+
+ Args:
+ lines (list of str): List of lines to process
+ adjust_cfg (dict of str): Changes to make to .config file before
+ building:
+ key: str config to change, without the CONFIG_ prefix, e.g.
+ FRED
+ value: str change to make (C is config option without prefix):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig)
+
+ Returns:
+ list of str: New list of lines resulting from the processing
+ """
+ out_lines = []
+ done = set()
+ for line in lines:
+ out_line, _ = adjust_cfg_line(line, adjust_cfg, done)
+ out_lines.append(out_line)
+
+ for opt in adjust_cfg:
+ if opt not in done:
+ adj = adjust_cfg.get(opt)
+ out_line = make_cfg_line(opt, adj)
+ out_lines.append(out_line)
+
+ return out_lines
+
+def adjust_cfg_file(fname, adjust_cfg):
+ """Make adjustments to a .config file
+
+ Args:
+ fname (str): Filename of .config file to change
+ adjust_cfg (dict of str): Changes to make to .config file before
+ building:
+ key: str config to change, without the CONFIG_ prefix, e.g.
+ FRED
+ value: str change to make (C is config option without prefix):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig)
+ """
+ lines = tools.ReadFile(fname, binary=False).splitlines()
+ out_lines = adjust_cfg_lines(lines, adjust_cfg)
+ out = '\n'.join(out_lines) + '\n'
+ tools.WriteFile(fname, out, binary=False)
+
+def convert_list_to_dict(adjust_cfg_list):
+ """Convert a list of config changes into the dict used by adjust_cfg_file()
+
+ Args:
+ adjust_cfg_list (list of str): List of changes to make to .config file
+ before building. Each is one of (where C is the config option with
+ or without the CONFIG_ prefix)
+
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig
+
+ Returns:
+ dict of str: Changes to make to .config file before building:
+ key: str config to change, without the CONFIG_ prefix, e.g. FRED
+ value: str change to make (C is config option without prefix):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig)
+
+ Raises:
+ ValueError: if an item in adjust_cfg_list has invalid syntax
+ """
+ result = {}
+ for cfg in adjust_cfg_list or []:
+ m_cfg = RE_CFG.match(cfg)
+ if not m_cfg:
+ raise ValueError(f"Invalid CONFIG adjustment '{cfg}'")
+ negate, _, opt, val = m_cfg.groups()
+ result[opt] = f'%s{opt}%s' % (negate or '', val or '')
+
+ return result
+
+def check_cfg_lines(lines, adjust_cfg):
+ """Check that lines do not conflict with the requested changes
+
+ If a line enables a CONFIG which was requested to be disabled, etc., then
+ this is an error. This function finds such errors.
+
+ Args:
+ lines (list of str): List of lines to process
+ adjust_cfg (dict of str): Changes to make to .config file before
+ building:
+ key: str config to change, without the CONFIG_ prefix, e.g.
+ FRED
+ value: str change to make (C is config option without prefix):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig)
+
+ Returns:
+ list of tuple: list of errors, each a tuple:
+ str: cfg adjustment requested
+ str: line of the config that conflicts
+ """
+ bad = []
+ done = set()
+ for line in lines:
+ out_line, adj = adjust_cfg_line(line, adjust_cfg, done)
+ if out_line != line:
+ bad.append([adj, line])
+
+ for opt in adjust_cfg:
+ if opt not in done:
+ adj = adjust_cfg.get(opt)
+ out_line = make_cfg_line(opt, adj)
+ bad.append([adj, f'Missing expected line: {out_line}'])
+
+ return bad
+
+def check_cfg_file(fname, adjust_cfg):
+ """Check that a config file has been adjusted according to adjust_cfg
+
+ Args:
+ fname (str): Filename of .config file to change
+ adjust_cfg (dict of str): Changes to make to .config file before
+ building:
+ key: str config to change, without the CONFIG_ prefix, e.g.
+ FRED
+ value: str change to make (C is config option without prefix):
+ C to enable C
+ ~C to disable C
+ C=val to set the value of C (val must have quotes if C is
+ a string Kconfig)
+
+ Returns:
+ str: None if OK, else an error string listing the problems
+ """
+ lines = tools.ReadFile(fname, binary=False).splitlines()
+ bad_cfgs = check_cfg_lines(lines, adjust_cfg)
+ if bad_cfgs:
+ out = [f'{cfg:20} {line}' for cfg, line in bad_cfgs]
+ content = '\\n'.join(out)
+ return f'''
+Some CONFIG adjustments did not take effect. This may be because
+the request CONFIGs do not exist or conflict with others.
+
+Failed adjustments:
+
+{content}
+'''
+ return None
args: command lin arguments
"""
parser = OptionParser()
+ parser.add_option('-a', '--adjust-cfg', type=str, action='append',
+ help='Adjust the Kconfig settings in .config before building')
parser.add_option('-A', '--print-prefix', action='store_true',
help='Print the tool-chain prefix for a board (CROSS_COMPILE=)')
parser.add_option('-b', '--branch', type='string',
help='Show detailed size delta for each board in the -S summary')
parser.add_option('-D', '--config-only', action='store_true', default=False,
help="Don't build, just configure each commit")
+ parser.add_option('--debug', action='store_true',
+ help='Enabling debugging (provides a full traceback on error)')
parser.add_option('-e', '--show_errors', action='store_true',
default=False, help='Show errors and warnings')
parser.add_option('-E', '--warnings-as-errors', action='store_true',
from buildman import board
from buildman import bsettings
+from buildman import cfgutil
from buildman import toolchain
from buildman.builder import Builder
from patman import command
from patman import patchstream
from patman import terminal
from patman import tools
-from patman.terminal import Print
+from patman.terminal import tprint
def GetPlural(count):
"""Returns a plural 's' if count is not 1"""
if commits:
for upto in range(0, len(series.commits), options.step):
commit = series.commits[upto]
- print(' ', col.Color(col.YELLOW, commit.hash[:8], bright=False), end=' ')
+ print(' ', col.build(col.YELLOW, commit.hash[:8], bright=False), end=' ')
print(commit.subject)
print()
for arg in why_selected:
len(why_selected['all'])))
if board_warnings:
for warning in board_warnings:
- print(col.Color(col.YELLOW, warning))
+ print(col.build(col.YELLOW, warning))
def ShowToolchainPrefix(boards, toolchains):
"""Show information about a the tool chain used by one or more boards
global builder
if options.full_help:
- tools.PrintFullHelp(
+ tools.print_full_help(
os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README')
)
return 0
- gitutil.Setup()
+ gitutil.setup()
col = terminal.Color()
options.git_dir = os.path.join(options.git, '.git')
if options.fetch_arch:
if options.fetch_arch == 'list':
sorted_list = toolchains.ListArchs()
- print(col.Color(col.BLUE, 'Available architectures: %s\n' %
+ print(col.build(col.BLUE, 'Available architectures: %s\n' %
' '.join(sorted_list)))
return 0
else:
fetch_arch = options.fetch_arch
if fetch_arch == 'all':
fetch_arch = ','.join(toolchains.ListArchs())
- print(col.Color(col.CYAN, '\nDownloading toolchains: %s' %
+ print(col.build(col.CYAN, '\nDownloading toolchains: %s' %
fetch_arch))
for arch in fetch_arch.split(','):
print()
return 0
if options.incremental:
- print(col.Color(col.RED,
+ print(col.build(col.RED,
'Warning: -I has been removed. See documentation'))
if not options.output_dir:
if options.work_in_output:
- sys.exit(col.Color(col.RED, '-w requires that you specify -o'))
+ sys.exit(col.build(col.RED, '-w requires that you specify -o'))
options.output_dir = '..'
# Work out what subset of the boards we are building
requested_boards)
selected = boards.GetSelected()
if not len(selected):
- sys.exit(col.Color(col.RED, 'No matching boards found'))
+ sys.exit(col.build(col.RED, 'No matching boards found'))
if options.print_prefix:
err = ShowToolchainPrefix(boards, toolchains)
if err:
- sys.exit(col.Color(col.RED, err))
+ sys.exit(col.build(col.RED, err))
return 0
# Work out how many commits to build. We want to build everything on the
count = 1
else:
if has_range:
- count, msg = gitutil.CountCommitsInRange(options.git_dir,
+ count, msg = gitutil.count_commits_in_range(options.git_dir,
options.branch)
else:
- count, msg = gitutil.CountCommitsInBranch(options.git_dir,
+ count, msg = gitutil.count_commits_in_branch(options.git_dir,
options.branch)
if count is None:
- sys.exit(col.Color(col.RED, msg))
+ sys.exit(col.build(col.RED, msg))
elif count == 0:
- sys.exit(col.Color(col.RED, "Range '%s' has no commits" %
+ sys.exit(col.build(col.RED, "Range '%s' has no commits" %
options.branch))
if msg:
- print(col.Color(col.YELLOW, msg))
+ print(col.build(col.YELLOW, msg))
count += 1 # Build upstream commit also
if not count:
str = ("No commits found to process in branch '%s': "
"set branch's upstream or use -c flag" % options.branch)
- sys.exit(col.Color(col.RED, str))
+ sys.exit(col.build(col.RED, str))
if options.work_in_output:
if len(selected) != 1:
- sys.exit(col.Color(col.RED,
+ sys.exit(col.build(col.RED,
'-w can only be used with a single board'))
if count != 1:
- sys.exit(col.Color(col.RED,
+ sys.exit(col.build(col.RED,
'-w can only be used with a single commit'))
# Read the metadata from the commits. First look at the upstream commit,
if has_range:
range_expr = options.branch
else:
- range_expr = gitutil.GetRangeInBranch(options.git_dir,
+ range_expr = gitutil.get_range_in_branch(options.git_dir,
options.branch)
- upstream_commit = gitutil.GetUpstream(options.git_dir,
+ upstream_commit = gitutil.get_upstream(options.git_dir,
options.branch)
series = patchstream.get_metadata_for_list(upstream_commit,
options.git_dir, 1, series=None, allow_overwrite=True)
if not options.step:
options.step = len(series.commits) - 1
- gnu_make = command.Output(os.path.join(options.git,
+ gnu_make = command.output(os.path.join(options.git,
'scripts/show-gnu-make'), raise_on_error=False).rstrip()
if not gnu_make:
sys.exit('GNU Make not found')
output_dir = os.path.join(options.output_dir, dirname)
if clean_dir and os.path.exists(output_dir):
shutil.rmtree(output_dir)
+ adjust_cfg = cfgutil.convert_list_to_dict(options.adjust_cfg)
+
builder = Builder(toolchains, output_dir, options.git_dir,
options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
show_unknown=options.show_unknown, step=options.step,
squash_config_y=not options.preserve_config_y,
warnings_as_errors=options.warnings_as_errors,
work_in_output=options.work_in_output,
- test_thread_exceptions=test_thread_exceptions)
+ test_thread_exceptions=test_thread_exceptions,
+ adjust_cfg=adjust_cfg)
builder.force_config_on_failure = not options.quick
if make_func:
builder.do_make = make_func
else:
commits = None
- Print(GetActionSummary(options.summary, commits, board_selected,
+ tprint(GetActionSummary(options.summary, commits, board_selected,
options))
# We can't show function sizes without board details at present
self._buildman_pathname = sys.argv[0]
self._buildman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
command.test_result = self._HandleCommand
+ bsettings.Setup(None)
+ bsettings.AddFile(settings_data)
self.setupToolchains()
self._toolchains.Add('arm-gcc', test=False)
self._toolchains.Add('powerpc-gcc', test=False)
- bsettings.Setup(None)
- bsettings.AddFile(settings_data)
self._boards = board.Boards()
for brd in boards:
self._boards.AddBoard(board.Board(*brd))
self._test_branch = TEST_BRANCH
# Avoid sending any output and clear all terminal output
- terminal.SetPrintTestMode()
- terminal.GetPrintTestLines()
+ terminal.set_print_test_mode()
+ terminal.get_print_test_lines()
def tearDown(self):
shutil.rmtree(self._base_dir)
self._toolchains.Add('gcc', test=False)
def _RunBuildman(self, *args):
- return command.RunPipe([[self._buildman_pathname] + list(args)],
+ return command.run_pipe([[self._buildman_pathname] + list(args)],
capture=True, capture_stderr=True)
def _RunControl(self, *args, boards=None, clean_dir=False,
def testGitSetup(self):
"""Test gitutils.Setup(), from outside the module itself"""
command.test_result = command.CommandResult(return_code=1)
- gitutil.Setup()
+ gitutil.setup()
self.assertEqual(gitutil.use_no_decorate, False)
command.test_result = command.CommandResult(return_code=0)
- gitutil.Setup()
+ gitutil.setup()
self.assertEqual(gitutil.use_no_decorate, True)
def _HandleCommandGitLog(self, args):
stage: Stage that we are at (mrproper, config, build)
cwd: Directory where make should be run
args: Arguments to pass to make
- kwargs: Arguments to pass to command.RunPipe()
+ kwargs: Arguments to pass to command.run_pipe()
"""
self._make_calls += 1
if stage == 'mrproper':
if arg.startswith('O='):
out_dir = arg[2:]
fname = os.path.join(cwd or '', out_dir, 'u-boot')
- tools.WriteFile(fname, b'U-Boot')
+ tools.write_file(fname, b'U-Boot')
if type(commit) is not str:
stderr = self._error.get((brd.target, commit.sequence))
if stderr:
print(len(lines))
for line in lines:
print(line)
- #self.print_lines(terminal.GetPrintTestLines())
+ #self.print_lines(terminal.get_print_test_lines())
def testNoBoards(self):
"""Test that buildman aborts when there are no boards"""
"""Very simple test to invoke buildman on the current source"""
self.setupToolchains();
self._RunControl('-o', self._output_dir)
- lines = terminal.GetPrintTestLines()
+ lines = terminal.get_print_test_lines()
self.assertIn('Building current source for %d boards' % len(boards),
lines[0].text)
"""Test that missing toolchains are detected"""
self.setupToolchains();
ret_code = self._RunControl('-b', TEST_BRANCH, '-o', self._output_dir)
- lines = terminal.GetPrintTestLines()
+ lines = terminal.get_print_test_lines()
# Buildman always builds the upstream commit as well
self.assertIn('Building %d commits for %d boards' %
with test_util.capture_sys_output() as (stdout, stderr):
self.assertEqual(102, self._RunControl('-o', self._output_dir,
test_thread_exceptions=True))
- self.assertIn('Thread exception: test exception', stdout.getvalue())
+ self.assertIn(
+ 'Thread exception (use -T0 to run without threads): test exception',
+ stdout.getvalue())
from patman import patchstream
from patman import gitutil
from patman import terminal
+from patman import test_util
-def RunTests(skip_net_tests):
+def RunTests(skip_net_tests, verboose, args):
import func_test
import test
import doctest
result = unittest.TestResult()
- for module in ['buildman.toolchain', 'patman.gitutil']:
- suite = doctest.DocTestSuite(module)
- suite.run(result)
-
- sys.argv = [sys.argv[0]]
+ test_name = args and args[0] or None
if skip_net_tests:
test.use_network = False
- for module in (test.TestBuild, func_test.TestFunctional):
- suite = unittest.TestLoader().loadTestsFromTestCase(module)
- suite.run(result)
- print(result)
- for test, err in result.errors:
- print(err)
- for test, err in result.failures:
- print(err)
+ # Run the entry tests first ,since these need to be the first to import the
+ # 'entry' module.
+ test_util.run_test_suites(
+ result, False, verboose, False, None, test_name, [],
+ [test.TestBuild, func_test.TestFunctional,
+ 'buildman.toolchain', 'patman.gitutil'])
+ return test_util.report_result('buildman', test_name, result)
options, args = cmdline.ParseArgs()
+if not options.debug:
+ sys.tracebacklimit = 0
+
# Run our meagre tests
if options.test:
- RunTests(options.skip_net_tests)
+ RunTests(options.skip_net_tests, options.verbose, args)
# Build selected commits for selected boards
else:
from buildman import board
from buildman import bsettings
from buildman import builder
+from buildman import cfgutil
from buildman import control
from buildman import toolchain
from patman import commit
self.toolchains.Add('gcc', test=False)
# Avoid sending any output
- terminal.SetPrintTestMode()
+ terminal.set_print_test_mode()
self._col = terminal.Color()
self.base_dir = tempfile.mkdtemp()
col.YELLOW if outcome == OUTCOME_WARN else col.RED)
expect = '%10s: ' % arch
# TODO(sjg@chromium.org): If plus is '', we shouldn't need this
- expect += ' ' + col.Color(expected_colour, plus)
+ expect += ' ' + col.build(expected_colour, plus)
expect += ' '
for board in boards:
- expect += col.Color(expected_colour, ' %s' % board)
+ expect += col.build(expected_colour, ' %s' % board)
self.assertEqual(text, expect)
def _SetupTest(self, echo_lines=False, threads=1, **kwdisplay_args):
# associated with each. This calls our Make() to inject the fake output.
build.BuildBoards(self.commits, board_selected, keep_outputs=False,
verbose=False)
- lines = terminal.GetPrintTestLines()
+ lines = terminal.get_print_test_lines()
count = 0
for line in lines:
if line.text.strip():
build.SetDisplayOptions(**kwdisplay_args);
build.ShowSummary(self.commits, board_selected)
if echo_lines:
- terminal.EchoPrintTestLines()
- return iter(terminal.GetPrintTestLines())
+ terminal.echo_print_test_lines()
+ return iter(terminal.get_print_test_lines())
def _CheckOutput(self, lines, list_error_boards=False,
filter_dtb_warnings=False,
new_lines = []
for line in lines:
if boards:
- expect = self._col.Color(colour, prefix + '(')
- expect += self._col.Color(self._col.MAGENTA, boards,
+ expect = self._col.build(colour, prefix + '(')
+ expect += self._col.build(self._col.MAGENTA, boards,
bright=False)
- expect += self._col.Color(colour, ') %s' % line)
+ expect += self._col.build(colour, ') %s' % line)
else:
- expect = self._col.Color(colour, prefix + line)
+ expect = self._col.build(colour, prefix + line)
new_lines.append(expect)
return '\n'.join(new_lines)
self.assertEqual(next(lines).text, '04: %s' % commits[3][1])
if filter_migration_warnings:
expect = '%10s: ' % 'powerpc'
- expect += ' ' + col.Color(col.GREEN, '')
+ expect += ' ' + col.build(col.GREEN, '')
expect += ' '
- expect += col.Color(col.GREEN, ' %s' % 'board2')
- expect += ' ' + col.Color(col.YELLOW, 'w+')
+ expect += col.build(col.GREEN, ' %s' % 'board2')
+ expect += ' ' + col.build(col.YELLOW, 'w+')
expect += ' '
- expect += col.Color(col.YELLOW, ' %s' % 'board3')
+ expect += col.build(col.YELLOW, ' %s' % 'board3')
self.assertEqual(next(lines).text, expect)
else:
self.assertSummary(next(lines).text, 'powerpc', 'w+',
def testPrepareOutputSpace(self):
def _Touch(fname):
- tools.WriteFile(os.path.join(base_dir, fname), b'')
+ tools.write_file(os.path.join(base_dir, fname), b'')
base_dir = tempfile.mkdtemp()
expected = set([os.path.join(base_dir, f) for f in to_remove])
self.assertEqual(expected, result)
+ def test_adjust_cfg_nop(self):
+ """check various adjustments of config that are nops"""
+ # enable an enabled CONFIG
+ self.assertEqual(
+ 'CONFIG_FRED=y',
+ cfgutil.adjust_cfg_line('CONFIG_FRED=y', {'FRED':'FRED'})[0])
+
+ # disable a disabled CONFIG
+ self.assertEqual(
+ '# CONFIG_FRED is not set',
+ cfgutil.adjust_cfg_line(
+ '# CONFIG_FRED is not set', {'FRED':'~FRED'})[0])
+
+ # use the adjust_cfg_lines() function
+ self.assertEqual(
+ ['CONFIG_FRED=y'],
+ cfgutil.adjust_cfg_lines(['CONFIG_FRED=y'], {'FRED':'FRED'}))
+ self.assertEqual(
+ ['# CONFIG_FRED is not set'],
+ cfgutil.adjust_cfg_lines(['CONFIG_FRED=y'], {'FRED':'~FRED'}))
+
+ # handling an empty line
+ self.assertEqual('#', cfgutil.adjust_cfg_line('#', {'FRED':'~FRED'})[0])
+
+ def test_adjust_cfg(self):
+ """check various adjustments of config"""
+ # disable a CONFIG
+ self.assertEqual(
+ '# CONFIG_FRED is not set',
+ cfgutil.adjust_cfg_line('CONFIG_FRED=1' , {'FRED':'~FRED'})[0])
+
+ # enable a disabled CONFIG
+ self.assertEqual(
+ 'CONFIG_FRED=y',
+ cfgutil.adjust_cfg_line(
+ '# CONFIG_FRED is not set', {'FRED':'FRED'})[0])
+
+ # enable a CONFIG that doesn't exist
+ self.assertEqual(
+ ['CONFIG_FRED=y'],
+ cfgutil.adjust_cfg_lines([], {'FRED':'FRED'}))
+
+ # disable a CONFIG that doesn't exist
+ self.assertEqual(
+ ['# CONFIG_FRED is not set'],
+ cfgutil.adjust_cfg_lines([], {'FRED':'~FRED'}))
+
+ # disable a value CONFIG
+ self.assertEqual(
+ '# CONFIG_FRED is not set',
+ cfgutil.adjust_cfg_line('CONFIG_FRED="fred"' , {'FRED':'~FRED'})[0])
+
+ # setting a value CONFIG
+ self.assertEqual(
+ 'CONFIG_FRED="fred"',
+ cfgutil.adjust_cfg_line('# CONFIG_FRED is not set' ,
+ {'FRED':'FRED="fred"'})[0])
+
+ # changing a value CONFIG
+ self.assertEqual(
+ 'CONFIG_FRED="fred"',
+ cfgutil.adjust_cfg_line('CONFIG_FRED="ernie"' ,
+ {'FRED':'FRED="fred"'})[0])
+
+ # setting a value for a CONFIG that doesn't exist
+ self.assertEqual(
+ ['CONFIG_FRED="fred"'],
+ cfgutil.adjust_cfg_lines([], {'FRED':'FRED="fred"'}))
+
+ def test_convert_adjust_cfg_list(self):
+ """Check conversion of the list of changes into a dict"""
+ self.assertEqual({}, cfgutil.convert_list_to_dict(None))
+
+ expect = {
+ 'FRED':'FRED',
+ 'MARY':'~MARY',
+ 'JOHN':'JOHN=0x123',
+ 'ALICE':'ALICE="alice"',
+ 'AMY':'AMY',
+ 'ABE':'~ABE',
+ 'MARK':'MARK=0x456',
+ 'ANNA':'ANNA="anna"',
+ }
+ actual = cfgutil.convert_list_to_dict(
+ ['FRED', '~MARY', 'JOHN=0x123', 'ALICE="alice"',
+ 'CONFIG_AMY', '~CONFIG_ABE', 'CONFIG_MARK=0x456',
+ 'CONFIG_ANNA="anna"'])
+ self.assertEqual(expect, actual)
+
+ def test_check_cfg_file(self):
+ """Test check_cfg_file detects conflicts as expected"""
+ # Check failure to disable CONFIG
+ result = cfgutil.check_cfg_lines(['CONFIG_FRED=1'], {'FRED':'~FRED'})
+ self.assertEqual([['~FRED', 'CONFIG_FRED=1']], result)
+
+ result = cfgutil.check_cfg_lines(
+ ['CONFIG_FRED=1', 'CONFIG_MARY="mary"'], {'FRED':'~FRED'})
+ self.assertEqual([['~FRED', 'CONFIG_FRED=1']], result)
+
+ result = cfgutil.check_cfg_lines(
+ ['CONFIG_FRED=1', 'CONFIG_MARY="mary"'], {'MARY':'~MARY'})
+ self.assertEqual([['~MARY', 'CONFIG_MARY="mary"']], result)
+
+ # Check failure to enable CONFIG
+ result = cfgutil.check_cfg_lines(
+ ['# CONFIG_FRED is not set'], {'FRED':'FRED'})
+ self.assertEqual([['FRED', '# CONFIG_FRED is not set']], result)
+
+ # Check failure to set CONFIG value
+ result = cfgutil.check_cfg_lines(
+ ['# CONFIG_FRED is not set', 'CONFIG_MARY="not"'],
+ {'MARY':'MARY="mary"', 'FRED':'FRED'})
+ self.assertEqual([
+ ['FRED', '# CONFIG_FRED is not set'],
+ ['MARY="mary"', 'CONFIG_MARY="not"']], result)
+
+ # Check failure to add CONFIG value
+ result = cfgutil.check_cfg_lines([], {'MARY':'MARY="mary"'})
+ self.assertEqual([
+ ['MARY="mary"', 'Missing expected line: CONFIG_MARY="mary"']], result)
+
+
if __name__ == "__main__":
unittest.main()
else:
self.priority = priority
if test:
- result = command.RunPipe([cmd], capture=True, env=env,
+ result = command.run_pipe([cmd], capture=True, env=env,
raise_on_error=False)
self.ok = result.return_code == 0
if verbose:
# We'll use MakeArgs() to provide this
pass
elif full_path:
- env[b'CROSS_COMPILE'] = tools.ToBytes(
+ env[b'CROSS_COMPILE'] = tools.to_bytes(
wrapper + os.path.join(self.path, self.cross))
else:
- env[b'CROSS_COMPILE'] = tools.ToBytes(wrapper + self.cross)
- env[b'PATH'] = tools.ToBytes(self.path) + b':' + env[b'PATH']
+ env[b'CROSS_COMPILE'] = tools.to_bytes(wrapper + self.cross)
+ env[b'PATH'] = tools.to_bytes(self.path) + b':' + env[b'PATH']
env[b'LC_ALL'] = b'C'
def List(self):
"""List out the selected toolchains for each architecture"""
col = terminal.Color()
- print(col.Color(col.BLUE, 'List of available toolchains (%d):' %
+ print(col.build(col.BLUE, 'List of available toolchains (%d):' %
len(self.toolchains)))
if len(self.toolchains):
for key, value in sorted(self.toolchains.items()):
else
URL containing this toolchain, if avaialble, else None
"""
- arch = command.OutputOneLine('uname', '-m')
+ arch = command.output_one_line('uname', '-m')
if arch == 'aarch64':
arch = 'arm64'
base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
url = '%s/%s/%s/' % (base, arch, version)
print('Checking: %s' % url)
response = urllib.request.urlopen(url)
- html = tools.ToString(response.read())
+ html = tools.to_string(response.read())
parser = MyHTMLParser(fetch_arch)
parser.feed(html)
if fetch_arch == 'list':
Directory name of the first entry in the archive, without the
trailing /
"""
- stdout = command.Output('tar', 'xvfJ', fname, '-C', dest)
+ stdout = command.output('tar', 'xvfJ', fname, '-C', dest)
dirs = stdout.splitlines()[1].split('/')[:2]
return '/'.join(dirs)
"""
# Fist get the URL for this architecture
col = terminal.Color()
- print(col.Color(col.BLUE, "Downloading toolchain for arch '%s'" % arch))
+ print(col.build(col.BLUE, "Downloading toolchain for arch '%s'" % arch))
url = self.LocateArchUrl(arch)
if not url:
print(("Cannot find toolchain for arch '%s' - use 'list' to list" %
os.mkdir(dest)
# Download the tar file for this toolchain and unpack it
- tarfile, tmpdir = tools.Download(url, '.buildman')
+ tarfile, tmpdir = tools.download(url, '.buildman')
if not tarfile:
return 1
- print(col.Color(col.GREEN, 'Unpacking to: %s' % dest), end=' ')
+ print(col.build(col.GREEN, 'Unpacking to: %s' % dest), end=' ')
sys.stdout.flush()
path = self.Unpack(tarfile, dest)
os.remove(tarfile)
print()
# Check that the toolchain works
- print(col.Color(col.GREEN, 'Testing'))
+ print(col.build(col.GREEN, 'Testing'))
dirpath = os.path.join(dest, path)
compiler_fname_list = self.ScanPath(dirpath, True)
if not compiler_fname_list:
print('Could not locate C compiler - fetch failed.')
return 1
if len(compiler_fname_list) != 1:
- print(col.Color(col.RED, 'Warning, ambiguous toolchains: %s' %
+ print(col.build(col.RED, 'Warning, ambiguous toolchains: %s' %
', '.join(compiler_fname_list)))
toolchain = Toolchain(compiler_fname_list[0], True, True)
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:focal-20220105
+FROM ubuntu:focal-20220113
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
libgit2-dev \
libjson-glib-dev \
libguestfs-tools \
+ libgnutls28-dev \
+ libgnutls30 \
liblz4-tool \
libpixman-1-dev \
libpython3-dev \
offset = fdt_obj.first_subnode(self._offset, QUIET_NOTFOUND)
for subnode in self.subnodes:
+ if subnode._offset is None:
+ continue
if subnode.name != fdt_obj.get_name(offset):
raise ValueError('Internal error, node name mismatch %s != %s' %
(subnode.name, fdt_obj.get_name(offset)))
prop_name: Name of property
"""
self.props[prop_name] = Prop(self, None, prop_name,
- tools.GetBytes(0, 4))
+ tools.get_bytes(0, 4))
def AddEmptyProp(self, prop_name, len):
"""Add a property with a fixed data size, for filling in later
prop_name: Name of property
len: Length of data in property
"""
- value = tools.GetBytes(0, len)
+ value = tools.get_bytes(0, len)
self.props[prop_name] = Prop(self, None, prop_name, value)
def _CheckProp(self, prop_name):
val = bytes(val, 'utf-8')
return self.AddData(prop_name, val + b'\0')
+ def AddStringList(self, prop_name, val):
+ """Add a new string-list property to a node
+
+ The device tree is marked dirty so that the value will be written to
+ the blob on the next sync.
+
+ Args:
+ prop_name: Name of property to add
+ val (list of str): List of strings to add
+
+ Returns:
+ Prop added
+ """
+ out = b''
+ for string in val:
+ out += bytes(string, 'utf-8') + b'\0'
+ return self.AddData(prop_name, out)
+
def AddInt(self, prop_name, val):
"""Add a new integer property to a node
self.subnodes.append(subnode)
return subnode
+ def Delete(self):
+ """Delete a node
+
+ The node is deleted and the offset cache is invalidated.
+
+ Args:
+ node (Node): Node to delete
+
+ Raises:
+ ValueError if the node does not exist
+ """
+ CheckErr(self._fdt._fdt_obj.del_node(self.Offset()),
+ "Node '%s': delete" % self.path)
+ parent = self.parent
+ self._fdt.Invalidate()
+ parent.subnodes.remove(self)
+
def Sync(self, auto_resize=False):
"""Sync node changes back to the device tree
dts_input = os.path.join(tmpdir, 'source.dts')
dtb_output = os.path.join(tmpdir, 'source.dtb')
else:
- dts_input = tools.GetOutputFilename('source.dts')
- dtb_output = tools.GetOutputFilename('source.dtb')
+ dts_input = tools.get_output_filename('source.dts')
+ dtb_output = tools.get_output_filename('source.dtb')
search_paths = [os.path.join(os.getcwd(), 'include')]
root, _ = os.path.splitext(fname)
- cc, args = tools.GetTargetCompileTool('cc')
+ cc, args = tools.get_target_compile_tool('cc')
args += ['-E', '-P', '-x', 'assembler-with-cpp', '-D__ASSEMBLY__']
args += ['-Ulinux']
for path in search_paths:
args.extend(['-I', path])
args += ['-o', dts_input, fname]
- command.Run(cc, *args)
+ command.run(cc, *args)
# If we don't have a directory, put it in the tools tempdir
search_list = []
for path in search_paths:
search_list.extend(['-i', path])
- dtc, args = tools.GetTargetCompileTool('dtc')
+ dtc, args = tools.get_target_compile_tool('dtc')
args += ['-I', 'dts', '-o', dtb_output, '-O', 'dtb',
'-W', 'no-unit_address_vs_reg']
args.extend(search_list)
args.append(dts_input)
- command.Run(dtc, *args, capture_stderr=capture_stderr)
+ command.run(dtc, *args, capture_stderr=capture_stderr)
return dtb_output
def GetInt(node, propname, default=None):
return [strval]
return value
+def GetArgs(node, propname):
+ prop = node.props.get(propname)
+ if not prop:
+ raise ValueError(f"Node '{node.path}': Expected property '{propname}'")
+ if prop.bytes:
+ value = GetStringList(node, propname)
+ else:
+ value = []
+ lists = [v.split() for v in value]
+ args = [x for l in lists for x in l]
+ return args
+
def GetBool(node, propname, default=False):
"""Get an boolean from a property
test_dtoc.setup()
- test_util.RunTestSuites(
+ test_util.run_test_suites(
result, debug=True, verbosity=1, test_preserve_dirs=False,
processes=processes, test_name=test_name, toolpath=[],
- test_class_list=[test_dtoc.TestDtoc,test_src_scan.TestSrcScan])
+ class_and_module_list=[test_dtoc.TestDtoc,test_src_scan.TestSrcScan])
- return test_util.ReportResult('binman', test_name, result)
+ return test_util.report_result('binman', test_name, result)
def RunTestCoverage():
"""Run the tests and check that we get 100% coverage"""
sys.argv = [sys.argv[0]]
- test_util.RunTestCoverage('tools/dtoc/dtoc', '/main.py',
+ test_util.run_test_coverage('tools/dtoc/dtoc', '/main.py',
['tools/patman/*.py', '*/fdt*', '*test*'], args.build_dir)
orig-node {
orig = <1 23 4>;
+ args = "-n first", "second", "-p", "123,456", "-x";
};
};
"""Tests for dtoc"""
@classmethod
def setUpClass(cls):
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
cls.maxDiff = None
@classmethod
def tearDownClass(cls):
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
@staticmethod
def _write_python_string(fname, data):
def test_empty_file(self):
"""Test output from a device tree file with no nodes"""
dtb_file = get_dtb_file('dtoc_test_empty.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
# Run this one without saved_scan to complete test coverage
dtb_platdata.run_steps(['struct'], dtb_file, False, output, [], None,
def test_simple(self):
"""Test output from some simple nodes with various types of data"""
dtb_file = get_dtb_file('dtoc_test_simple.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
# Try the 'all' command
self.run_test(['all'], dtb_file, output)
- data = tools.ReadFile(output, binary=False)
+ data = tools.read_file(output, binary=False)
self._check_strings(
self.decl_text + self.platdata_text + self.struct_text, data)
def test_driver_alias(self):
"""Test output from a device tree file with a driver alias"""
dtb_file = get_dtb_file('dtoc_test_driver_alias.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_invalid_driver(self):
"""Test output from a device tree file with an invalid driver"""
dtb_file = get_dtb_file('dtoc_test_invalid_driver.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with test_util.capture_sys_output() as _:
dtb_platdata.run_steps(
['struct'], dtb_file, False, output, [], None, False,
def test_phandle(self):
"""Test output from a node containing a phandle reference"""
dtb_file = get_dtb_file('dtoc_test_phandle.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_phandle_single(self):
"""Test output from a node containing a phandle reference"""
dtb_file = get_dtb_file('dtoc_test_phandle_single.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_phandle_reorder(self):
"""Test that phandle targets are generated before their references"""
dtb_file = get_dtb_file('dtoc_test_phandle_reorder.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['platdata'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_phandle_cd_gpio(self):
"""Test that phandle targets are generated when unsing cd-gpios"""
dtb_file = get_dtb_file('dtoc_test_phandle_cd_gpios.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
dtb_platdata.run_steps(
['platdata'], dtb_file, False, output, [], None, False,
warning_disabled=True, scan=copy_scan())
"""Test a node containing an invalid phandle fails"""
dtb_file = get_dtb_file('dtoc_test_phandle_bad.dts',
capture_stderr=True)
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
self.run_test(['struct'], dtb_file, output)
self.assertIn("Cannot parse 'clocks' in node 'phandle-source'",
"""Test a phandle target missing its #*-cells property"""
dtb_file = get_dtb_file('dtoc_test_phandle_bad2.dts',
capture_stderr=True)
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
self.run_test(['struct'], dtb_file, output)
self.assertIn("Node 'phandle-target' has no cells property",
def test_addresses64(self):
"""Test output from a node with a 'reg' property with na=2, ns=2"""
dtb_file = get_dtb_file('dtoc_test_addr64.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_addresses32(self):
"""Test output from a node with a 'reg' property with na=1, ns=1"""
dtb_file = get_dtb_file('dtoc_test_addr32.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_addresses64_32(self):
"""Test output from a node with a 'reg' property with na=2, ns=1"""
dtb_file = get_dtb_file('dtoc_test_addr64_32.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_addresses32_64(self):
"""Test output from a node with a 'reg' property with na=1, ns=2"""
dtb_file = get_dtb_file('dtoc_test_addr32_64.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
"""Test that a reg property with an invalid type generates an error"""
# Capture stderr since dtc will emit warnings for this file
dtb_file = get_dtb_file('dtoc_test_bad_reg.dts', capture_stderr=True)
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
self.run_test(['struct'], dtb_file, output)
self.assertIn("Node 'spl-test' reg property is not an int",
"""Test that a reg property with an invalid cell count is detected"""
# Capture stderr since dtc will emit warnings for this file
dtb_file = get_dtb_file('dtoc_test_bad_reg2.dts', capture_stderr=True)
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
self.run_test(['struct'], dtb_file, output)
self.assertIn(
def test_add_prop(self):
"""Test that a subequent node can add a new property to a struct"""
dtb_file = get_dtb_file('dtoc_test_add_prop.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
with open(output) as infile:
data = infile.read()
def test_multi_to_file(self):
"""Test output of multiple pieces to a single file"""
dtb_file = get_dtb_file('dtoc_test_simple.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['all'], dtb_file, output)
- data = tools.ReadFile(output, binary=False)
+ data = tools.read_file(output, binary=False)
self._check_strings(
self.decl_text + self.platdata_text + self.struct_text, data)
def test_bad_command(self):
"""Test running dtoc with an invalid command"""
dtb_file = get_dtb_file('dtoc_test_simple.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
self.run_test(['invalid-cmd'], dtb_file, output)
self.assertIn(
def check_output_dirs(self, instantiate):
# Remove the directory so that files from other tests are not there
- tools._RemoveOutputDir()
- tools.PrepareOutputDir(None)
+ tools._remove_output_dir()
+ tools.prepare_output_dir(None)
# This should create the .dts and .dtb in the output directory
dtb_file = get_dtb_file('dtoc_test_simple.dts')
- outdir = tools.GetOutputDir()
+ outdir = tools.get_output_dir()
fnames = glob.glob(outdir + '/*')
self.assertEqual(2, len(fnames))
Scanner: scanner to use
"""
dtb_file = get_dtb_file('dtoc_test_simple.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
# Take a copy before messing with it
scan = copy_scan()
def test_alias_read(self):
"""Test obtaining aliases"""
dtb_file = get_dtb_file('dtoc_test_inst.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
plat = self.run_test(['struct'], dtb_file, output)
scan = plat._scan
def test_alias_read_bad(self):
"""Test invalid alias property name"""
dtb_file = get_dtb_file('dtoc_test_alias_bad.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
plat = self.run_test(['struct'], dtb_file, output)
self.assertIn("Cannot decode alias 'i2c4-'", str(exc.exception))
# node (/does/not/exist)
dtb_file = get_dtb_file('dtoc_test_alias_bad_path.dts', True)
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
plat = self.run_test(['struct'], dtb_file, output)
self.assertIn("Alias 'i2c4' path '/does/not/exist' not found",
def test_alias_read_bad_uclass(self):
"""Test alias for a uclass that doesn't exist"""
dtb_file = get_dtb_file('dtoc_test_alias_bad_uc.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with test_util.capture_sys_output() as (stdout, _):
plat = self.run_test(['struct'], dtb_file, output)
self.assertEqual("Could not find uclass for alias 'other1'",
def test_sequence(self):
"""Test assignment of sequence numnbers"""
dtb_file = get_dtb_file('dtoc_test_inst.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
plat = self.run_test(['struct'], dtb_file, output)
scan = plat._scan
def test_process_root(self):
"""Test assignment of sequence numnbers"""
dtb_file = get_dtb_file('dtoc_test_simple.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
# Take a copy before messing with it
scan = copy_scan()
def test_simple_inst(self):
"""Test output from some simple nodes with instantiate enabled"""
dtb_file = get_dtb_file('dtoc_test_inst.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['decl'], dtb_file, output, True)
with open(output) as infile:
def test_inst_no_hdr(self):
"""Test dealing with a struct tsssshat has no header"""
dtb_file = get_dtb_file('dtoc_test_inst.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
# Run it once to set everything up
plat = self.run_test(['decl'], dtb_file, output, True)
def test_missing_props(self):
"""Test detection of a parent node with no properties"""
dtb_file = get_dtb_file('dtoc_test_noprops.dts', capture_stderr=True)
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
self.run_test(['struct'], dtb_file, output)
self.assertIn("Parent node '/i2c@0' has no properties - do you need",
def test_single_reg(self):
"""Test detection of a parent node with no properties"""
dtb_file = get_dtb_file('dtoc_test_single_reg.dts')
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
self.run_test(['struct'], dtb_file, output)
def test_missing_parent(self):
"""Test detection of a parent node with no properties"""
dtb_file = get_dtb_file('dtoc_test_noparent.dts', capture_stderr=True)
- output = tools.GetOutputFilename('output')
+ output = tools.get_output_filename('output')
with self.assertRaises(ValueError) as exc:
self.run_test(['device'], dtb_file, output, instantiate=True)
self.assertIn("Node '/i2c@0/spl-test/pmic@9' requires parent node "
"""
@classmethod
def setUpClass(cls):
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
@classmethod
def tearDownClass(cls):
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
def setUp(self):
self.dtb = fdt.FdtScan(find_dtb_file('dtoc_test_simple.dts'))
@classmethod
def setUpClass(cls):
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
@classmethod
def tearDownClass(cls):
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
def setUp(self):
self.dtb = fdt.FdtScan(find_dtb_file('dtoc_test_simple.dts'))
self.dtb.Sync(auto_resize=True)
+ def testAddOneNode(self):
+ """Testing deleting and adding a subnode before syncing"""
+ subnode = self.node.AddSubnode('subnode')
+ self.node.AddSubnode('subnode2')
+ self.dtb.Sync(auto_resize=True)
+
+ # Delete a node and add a new one
+ subnode.Delete()
+ self.node.AddSubnode('subnode3')
+ self.dtb.Sync()
+
def testRefreshNameMismatch(self):
"""Test name mismatch when syncing nodes and properties"""
prop = self.node.AddInt('integer-a', 12)
@classmethod
def setUpClass(cls):
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
@classmethod
def tearDownClass(cls):
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
def setUp(self):
self.dtb = fdt.FdtScan(find_dtb_file('dtoc_test_simple.dts'))
"""Tests the GetEmpty() function for the various supported types"""
self.assertEqual(True, fdt.Prop.GetEmpty(Type.BOOL))
self.assertEqual(chr(0), fdt.Prop.GetEmpty(Type.BYTE))
- self.assertEqual(tools.GetBytes(0, 4), fdt.Prop.GetEmpty(Type.INT))
+ self.assertEqual(tools.get_bytes(0, 4), fdt.Prop.GetEmpty(Type.INT))
self.assertEqual('', fdt.Prop.GetEmpty(Type.STRING))
def testGetOffset(self):
self.node.AddString('string', val)
self.dtb.Sync(auto_resize=True)
data = self.fdt.getprop(self.node.Offset(), 'string')
- self.assertEqual(tools.ToBytes(val) + b'\0', data)
+ self.assertEqual(tools.to_bytes(val) + b'\0', data)
self.fdt.pack()
self.node.SetString('string', val + 'x')
self.node.SetString('string', val[:-1])
prop = self.node.props['string']
- prop.SetData(tools.ToBytes(val))
+ prop.SetData(tools.to_bytes(val))
self.dtb.Sync(auto_resize=False)
data = self.fdt.getprop(self.node.Offset(), 'string')
- self.assertEqual(tools.ToBytes(val), data)
+ self.assertEqual(tools.to_bytes(val), data)
self.node.AddEmptyProp('empty', 5)
self.dtb.Sync(auto_resize=True)
prop = self.node.props['empty']
- prop.SetData(tools.ToBytes(val))
+ prop.SetData(tools.to_bytes(val))
self.dtb.Sync(auto_resize=False)
data = self.fdt.getprop(self.node.Offset(), 'empty')
- self.assertEqual(tools.ToBytes(val), data)
+ self.assertEqual(tools.to_bytes(val), data)
self.node.SetData('empty', b'123')
self.assertEqual(b'123', prop.bytes)
# Trying adding a lot of data at once
- self.node.AddData('data', tools.GetBytes(65, 20000))
+ self.node.AddData('data', tools.get_bytes(65, 20000))
+ self.dtb.Sync(auto_resize=True)
+
+ def test_string_list(self):
+ """Test adding string-list property to a node"""
+ val = ['123', '456']
+ self.node.AddStringList('stringlist', val)
self.dtb.Sync(auto_resize=True)
+ data = self.fdt.getprop(self.node.Offset(), 'stringlist')
+ self.assertEqual(b'123\x00456\0', data)
+
+ def test_delete_node(self):
+ """Test deleting a node"""
+ old_offset = self.fdt.path_offset('/spl-test')
+ self.assertGreater(old_offset, 0)
+ self.node.Delete()
+ self.dtb.Sync()
+ new_offset = self.fdt.path_offset('/spl-test', libfdt.QUIET_NOTFOUND)
+ self.assertEqual(-libfdt.NOTFOUND, new_offset)
def testFromData(self):
dtb2 = fdt.Fdt.FromData(self.dtb.GetContents())
def testGetFilename(self):
"""Test the dtb filename can be provided"""
- self.assertEqual(tools.GetOutputFilename('source.dtb'),
+ self.assertEqual(tools.get_output_filename('source.dtb'),
self.dtb.GetFilename())
"""
@classmethod
def setUpClass(cls):
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
@classmethod
def tearDownClass(cls):
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
def setUp(self):
self.dtb = fdt.FdtScan(find_dtb_file('dtoc_test_simple.dts'))
self.assertEqual(['test'],
fdt_util.GetStringList(self.node, 'missing', ['test']))
+ def testGetArgs(self):
+ node = self.dtb.GetNode('/orig-node')
+ self.assertEqual(['message'], fdt_util.GetArgs(self.node, 'stringval'))
+ self.assertEqual(
+ ['multi-word', 'message'],
+ fdt_util.GetArgs(self.node, 'stringarray'))
+ self.assertEqual([], fdt_util.GetArgs(self.node, 'boolval'))
+ self.assertEqual(['-n', 'first', 'second', '-p', '123,456', '-x'],
+ fdt_util.GetArgs(node, 'args'))
+ with self.assertRaises(ValueError) as exc:
+ fdt_util.GetArgs(self.node, 'missing')
+ self.assertIn(
+ "Node '/spl-test': Expected property 'missing'",
+ str(exc.exception))
+
def testGetBool(self):
self.assertEqual(True, fdt_util.GetBool(self.node, 'boolval'))
self.assertEqual(False, fdt_util.GetBool(self.node, 'missing'))
def RunTestCoverage():
"""Run the tests and check that we get 100% coverage"""
- test_util.RunTestCoverage('tools/dtoc/test_fdt.py', None,
+ test_util.run_test_coverage('tools/dtoc/test_fdt.py', None,
['tools/patman/*.py', '*test_fdt.py'], options.build_dir)
"""Tests for src_scan"""
@classmethod
def setUpClass(cls):
- tools.PrepareOutputDir(None)
+ tools.prepare_output_dir(None)
@classmethod
def tearDownClass(cls):
- tools.FinaliseOutputDir()
+ tools.finalise_output_dir()
def test_simple(self):
"""Simple test of scanning drivers"""
pathname = os.path.join(indir, fname)
dirname = os.path.dirname(pathname)
os.makedirs(dirname, exist_ok=True)
- tools.WriteFile(pathname, '', binary=False)
+ tools.write_file(pathname, '', binary=False)
fname_list.append(pathname)
try:
def test_scan(self):
"""Test scanning of a driver"""
fname = os.path.join(OUR_PATH, '..', '..', 'drivers/i2c/tegra_i2c.c')
- buff = tools.ReadFile(fname, False)
+ buff = tools.read_file(fname, False)
scan = src_scan.Scanner(None, None)
scan._parse_driver(fname, buff)
self.assertIn('i2c_tegra', scan._drivers)
def test_struct_scan_errors(self):
"""Test scanning a header file with an invalid unicode file"""
- output = tools.GetOutputFilename('output.h')
- tools.WriteFile(output, b'struct this is a test \x81 of bad unicode')
+ output = tools.get_output_filename('output.h')
+ tools.write_file(output, b'struct this is a test \x81 of bad unicode')
scan = src_scan.Scanner(None, None)
with test_util.capture_sys_output() as (stdout, _):
static void usage(void);
/* parameters initialized by core will be used by the image type code */
-static struct image_tool_params params = {
- .type = IH_TYPE_KERNEL,
-};
+static struct image_tool_params params;
/*
* dumpimage_extract_subimage -
}
}
- if (argc < 2)
+ if (argc < 2 || (params.iflag && params.lflag))
usage();
if (optind >= argc) {
/* set tparams as per input type_id */
tparams = imagetool_get_type(params.type);
- if (tparams == NULL) {
+ if (!params.lflag && tparams == NULL) {
fprintf(stderr, "%s: unsupported type: %s\n",
params.cmdname, genimg_get_type_name(params.type));
exit(EXIT_FAILURE);
* check the passed arguments parameters meets the requirements
* as per image type to be generated/listed
*/
- if (tparams->check_params) {
+ if (tparams && tparams->check_params) {
if (tparams->check_params(¶ms)) {
fprintf(stderr, "%s: Parameter check failed\n",
params.cmdname);
exit(EXIT_FAILURE);
}
- if ((uint32_t)sbuf.st_size < tparams->header_size) {
+ if (tparams && (uint32_t)sbuf.st_size < tparams->header_size) {
fprintf(stderr, "%s: Bad size: \"%s\" is not valid image\n",
params.cmdname, params.imagefile);
exit(EXIT_FAILURE);
static void usage(void)
{
- fprintf(stderr, "Usage: %s -l image\n"
- " -l ==> list image header information\n",
+ fprintf(stderr, "Usage: %s [-T type] -l image\n"
+ " -l ==> list image header information\n"
+ " -T ==> parse image file as 'type'\n",
params.cmdname);
fprintf(stderr,
" %s [-T type] [-p position] [-o outfile] image\n"
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2021 Linaro Limited
+ * Author: AKASHI Takahiro
+ *
+ * derived from efi.h and efi_api.h to make the file POSIX-compliant
+ */
+
+#ifndef _EFI_CAPSULE_H
+#define _EFI_CAPSULE_H
+
+#include <stdint.h>
+
+/*
+ * Gcc's predefined attributes are not recognized by clang.
+ */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif
+
+#ifndef __aligned
+#define __aligned(x) __attribute__((__aligned__(x)))
+#endif
+
+typedef struct {
+ uint8_t b[16];
+} efi_guid_t __aligned(8);
+
+#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
+ {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \
+ ((a) >> 24) & 0xff, \
+ (b) & 0xff, ((b) >> 8) & 0xff, \
+ (c) & 0xff, ((c) >> 8) & 0xff, \
+ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }
+
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
+ EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \
+ 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a)
+
+#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \
+ EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \
+ 0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47)
+
+#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \
+ EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \
+ 0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f)
+
+#define EFI_CERT_TYPE_PKCS7_GUID \
+ EFI_GUID(0x4aafd29d, 0x68df, 0x49ee, 0x8a, 0xa9, \
+ 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7)
+
+/* flags */
+#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000
+
+struct efi_capsule_header {
+ efi_guid_t capsule_guid;
+ uint32_t header_size;
+ uint32_t flags;
+ uint32_t capsule_image_size;
+} __packed;
+
+struct efi_firmware_management_capsule_header {
+ uint32_t version;
+ uint16_t embedded_driver_count;
+ uint16_t payload_item_count;
+ uint32_t item_offset_list[];
+} __packed;
+
+/* image_capsule_support */
+#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001
+
+struct efi_firmware_management_capsule_image_header {
+ uint32_t version;
+ efi_guid_t update_image_type_id;
+ uint8_t update_image_index;
+ uint8_t reserved[3];
+ uint32_t update_image_size;
+ uint32_t update_vendor_code_size;
+ uint64_t update_hardware_instance;
+ uint64_t image_capsule_support;
+} __packed;
+
+/**
+ * win_certificate_uefi_guid - A certificate that encapsulates
+ * a GUID-specific signature
+ *
+ * @hdr: Windows certificate header, cf. WIN_CERTIFICATE
+ * @cert_type: Certificate type
+ */
+struct win_certificate_uefi_guid {
+ struct {
+ uint32_t dwLength;
+ uint16_t wRevision;
+ uint16_t wCertificateType;
+ } hdr;
+ efi_guid_t cert_type;
+} __packed;
+
+/**
+ * efi_firmware_image_authentication - Capsule authentication method
+ * descriptor
+ *
+ * This structure describes an authentication information for
+ * a capsule with IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED set
+ * and should be included as part of the capsule.
+ * Only EFI_CERT_TYPE_PKCS7_GUID is accepted.
+ *
+ * @monotonic_count: Count to prevent replay
+ * @auth_info: Authentication info
+ */
+struct efi_firmware_image_authentication {
+ uint64_t monotonic_count;
+ struct win_certificate_uefi_guid auth_info;
+} __packed;
+
+#endif /* _EFI_CAPSULE_H */
return 0;
}
-static int flash_io(int mode);
+static int flash_io(int mode, void *buf, size_t count);
static int parse_config(struct env_opts *opts);
#if defined(CONFIG_FILE)
*environment.crc = crc32(0, (uint8_t *) environment.data, ENV_SIZE);
/* write environment back to flash */
- if (flash_io(O_RDWR)) {
+ if (flash_io(O_RDWR, environment.image, CUR_ENVSIZE)) {
fprintf(stderr, "Error: can't write fw_env to flash\n");
return -1;
}
return rc;
}
-static int flash_write(int fd_current, int fd_target, int dev_target)
+static int flash_write(int fd_current, int fd_target, int dev_target, void *buf,
+ size_t count)
{
int rc;
if (IS_UBI(dev_target)) {
if (ubi_update_start(fd_target, CUR_ENVSIZE) < 0)
return -1;
- return ubi_write(fd_target, environment.image, CUR_ENVSIZE);
+ return ubi_write(fd_target, buf, count);
}
- rc = flash_write_buf(dev_target, fd_target, environment.image,
- CUR_ENVSIZE);
+ rc = flash_write_buf(dev_target, fd_target, buf, count);
if (rc < 0)
return rc;
return 0;
}
-static int flash_read(int fd)
+static int flash_read(int fd, void *buf, size_t count)
{
int rc;
if (IS_UBI(dev_current)) {
DEVTYPE(dev_current) = MTD_ABSENT;
- return ubi_read(fd, environment.image, CUR_ENVSIZE);
+ return ubi_read(fd, buf, count);
}
- rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
+ rc = flash_read_buf(dev_current, fd, buf, count,
DEVOFFSET(dev_current));
if (rc != CUR_ENVSIZE)
return -1;
return rc;
}
-static int flash_io_write(int fd_current)
+static int flash_io_write(int fd_current, void *buf, size_t count)
{
int fd_target = -1, rc, dev_target;
const char *dname, *target_temp = NULL;
fd_target = fd_current;
}
- rc = flash_write(fd_current, fd_target, dev_target);
+ rc = flash_write(fd_current, fd_target, dev_target, buf, count);
if (fsync(fd_current) && !(errno == EINVAL || errno == EROFS)) {
fprintf(stderr,
return rc;
}
-static int flash_io(int mode)
+static int flash_io(int mode, void *buf, size_t count)
{
int fd_current, rc;
}
if (mode == O_RDWR) {
- rc = flash_io_write(fd_current);
+ rc = flash_io_write(fd_current, buf, count);
} else {
- rc = flash_read(fd_current);
+ rc = flash_read(fd_current, buf, count);
}
if (close(fd_current)) {
int ret;
- struct env_image_single *single;
- struct env_image_redundant *redundant;
-
if (!opts)
opts = &default_opts;
goto open_cleanup;
}
- /* read environment from FLASH to local buffer */
- environment.image = addr0;
-
- if (have_redund_env) {
- redundant = addr0;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
- } else {
- single = addr0;
- environment.crc = &single->crc;
- environment.flags = NULL;
- environment.data = single->data;
- }
-
dev_current = 0;
- if (flash_io(O_RDONLY)) {
+ if (flash_io(O_RDONLY, addr0, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
- crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE);
-
- crc0_ok = (crc0 == *environment.crc);
if (!have_redund_env) {
+ struct env_image_single *single = addr0;
+
+ crc0 = crc32(0, (uint8_t *)single->data, ENV_SIZE);
+ crc0_ok = (crc0 == single->crc);
if (!crc0_ok) {
fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy(environment.data, default_environment,
+ memcpy(single->data, default_environment,
sizeof(default_environment));
environment.dirty = 1;
}
+
+ environment.image = addr0;
+ environment.crc = &single->crc;
+ environment.flags = NULL;
+ environment.data = single->data;
} else {
- flag0 = *environment.flags;
+ struct env_image_redundant *redundant0 = addr0;
+ struct env_image_redundant *redundant1;
+
+ crc0 = crc32(0, (uint8_t *)redundant0->data, ENV_SIZE);
+ crc0_ok = (crc0 == redundant0->crc);
+
+ flag0 = redundant0->flags;
dev_current = 1;
addr1 = calloc(1, CUR_ENVSIZE);
ret = -ENOMEM;
goto open_cleanup;
}
- redundant = addr1;
+ redundant1 = addr1;
- /*
- * have to set environment.image for flash_read(), careful -
- * other pointers in environment still point inside addr0
- */
- environment.image = addr1;
- if (flash_io(O_RDONLY)) {
+ if (flash_io(O_RDONLY, addr1, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
goto open_cleanup;
}
- crc1 = crc32(0, (uint8_t *)redundant->data, ENV_SIZE);
+ crc1 = crc32(0, (uint8_t *)redundant1->data, ENV_SIZE);
- crc1_ok = (crc1 == redundant->crc);
- flag1 = redundant->flags;
+ crc1_ok = (crc1 == redundant1->crc);
+ flag1 = redundant1->flags;
- /*
- * environment.data still points to ((struct
- * env_image_redundant *)addr0)->data. If the two
- * environments differ, or one has bad crc, force a
- * write-out by marking the environment dirty.
- */
- if (memcmp(environment.data, redundant->data, ENV_SIZE) ||
+ if (memcmp(redundant0->data, redundant1->data, ENV_SIZE) ||
!crc0_ok || !crc1_ok)
environment.dirty = 1;
} else if (!crc0_ok && !crc1_ok) {
fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy(environment.data, default_environment,
+ memcpy(redundant0->data, default_environment,
sizeof(default_environment));
environment.dirty = 1;
dev_current = 0;
*/
if (dev_current) {
environment.image = addr1;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
+ environment.crc = &redundant1->crc;
+ environment.flags = &redundant1->flags;
+ environment.data = redundant1->data;
free(addr0);
} else {
environment.image = addr0;
- /* Other pointers are already set */
+ environment.crc = &redundant0->crc;
+ environment.flags = &redundant0->flags;
+ environment.data = redundant0->data;
free(addr1);
}
#ifdef DEBUG
return NULL;
}
+static int imagetool_verify_print_header_by_type(
+ void *ptr,
+ struct stat *sbuf,
+ struct image_type_params *tparams,
+ struct image_tool_params *params);
+
int imagetool_verify_print_header(
void *ptr,
struct stat *sbuf,
struct image_type_params **start = __start_image_type;
struct image_type_params **end = __stop_image_type;
+ if (tparams)
+ return imagetool_verify_print_header_by_type(ptr, sbuf, tparams, params);
+
for (curr = start; curr != end; curr++) {
if ((*curr)->verify_header) {
retval = (*curr)->verify_header((unsigned char *)ptr,
return retval;
}
-int imagetool_verify_print_header_by_type(
+static int imagetool_verify_print_header_by_type(
void *ptr,
struct stat *sbuf,
struct image_type_params *tparams,
const char *keydest; /* Destination .dtb for public key */
const char *keyfile; /* Filename of private or public key */
const char *comment; /* Comment to add to signature node */
- const char *algo_name; /* Algorithm name to use hashing/signing */
+ /* Algorithm name to use for hashing/signing or NULL to use the one
+ * specified in the its */
+ const char *algo_name;
int require_keys; /* 1 to mark signing keys as 'required' */
int file_size; /* Total size of output file */
int orig_file_size; /* Original size for file before padding */
/*
* imagetool_verify_print_header() - verifies the image header
*
- * Scan registered image types and verify the image_header for each
- * supported image type. If verification is successful, this prints
- * the respective header.
- *
- * Return: 0 on success, negative if input image format does not match with
- * any of supported image types
- */
-int imagetool_verify_print_header(
- void *ptr,
- struct stat *sbuf,
- struct image_type_params *tparams,
- struct image_tool_params *params);
-
-/*
- * imagetool_verify_print_header_by_type() - verifies the image header
- *
* Verify the image_header for the image type given by tparams.
+ * If tparams is NULL then scan registered image types and verify the
+ * image_header for each supported image type.
* If verification is successful, this prints the respective header.
* @ptr: pointer the the image header
* @sbuf: stat information about the file pointed to by ptr
- * @tparams: image type parameters
+ * @tparams: image type parameters or NULL
* @params: mkimage parameters
*
* Return: 0 on success, negative if input image format does not match with
* the given image type
*/
-int imagetool_verify_print_header_by_type(
+int imagetool_verify_print_header(
void *ptr,
struct stat *sbuf,
struct image_type_params *tparams,
*
* (C) Copyright 2013 Thomas Petazzoni
* <thomas.petazzoni@free-electrons.com>
+ *
+ * (C) Copyright 2022 Pali Rohár <pali@kernel.org>
*/
#define OPENSSL_API_COMPAT 0x10101000L
}
#endif
+/* fls - find last (most-significant) bit set in 4-bit integer */
+static inline int fls4(int num)
+{
+ if (num & 0x8)
+ return 4;
+ else if (num & 0x4)
+ return 3;
+ else if (num & 0x2)
+ return 2;
+ else if (num & 0x1)
+ return 1;
+ else
+ return 0;
+}
+
static struct image_cfg_element *image_cfg;
static int cfgn;
static int verbose_mode;
e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
if (e)
main_hdr->nandeccmode = e->nandeccmode;
+ e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
+ if (e)
+ main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
if (e)
main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
+ e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
+ if (e)
+ main_hdr->nandbadblklocation = e->nandbadblklocation;
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
fprintf(stderr,
"Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
"This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
- "image for your board. Use 'dumpimage -T kwbimage -p 0' to extract it from an existing image.\n",
+ "image for your board. Use 'dumpimage -T kwbimage -p 1' to extract it from an existing image.\n",
e->binary.file, dir);
return 0;
}
static void kwbimage_print_header(const void *ptr)
{
struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
+ struct bin_hdr_v0 *bhdr;
struct opt_hdr_v1 *ohdr;
printf("Image Type: MVEBU Boot from %s Image\n",
}
}
+ for_each_bin_hdr_v0(bhdr, mhdr) {
+ printf("BIN Img Size: ");
+ genimg_print_size(le32_to_cpu(bhdr->size));
+ printf("BIN Img Addr: %08x\n", le32_to_cpu(bhdr->destaddr));
+ printf("BIN Img Entr: %08x\n", le32_to_cpu(bhdr->execaddr));
+ }
+
printf("Data Size: ");
genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
printf("Load Address: %08x\n", mhdr->destaddr);
/* Only version 0 extended header has checksum */
if (kwbimage_version(ptr) == 0) {
struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
+ struct ext_hdr_v0 *ext_hdr;
+ struct bin_hdr_v0 *bhdr;
- if (mhdr->ext) {
- struct ext_hdr_v0 *ext_hdr = (void *)(mhdr + 1);
-
+ for_each_ext_hdr_v0(ext_hdr, ptr) {
csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1);
if (csum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
+ for_each_bin_hdr_v0(bhdr, ptr) {
+ csum = image_checksum8(bhdr, (uint8_t *)&bhdr->checksum - (uint8_t *)bhdr - 1);
+ if (csum != bhdr->checksum)
+ return -FDT_ERR_BADSTRUCTURE;
+
+ if (bhdr->offset > sizeof(*bhdr) || bhdr->offset % 4 != 0)
+ return -FDT_ERR_BADSTRUCTURE;
+
+ if (bhdr->offset + bhdr->size + 4 > sizeof(*bhdr) || bhdr->size % 4 != 0)
+ return -FDT_ERR_BADSTRUCTURE;
+
+ if (image_checksum32((uint8_t *)bhdr + bhdr->offset, bhdr->size) !=
+ *(uint32_t *)((uint8_t *)bhdr + bhdr->offset + bhdr->size))
+ return -FDT_ERR_BADSTRUCTURE;
+ }
+
blockid = mhdr->blockid;
offset = le32_to_cpu(mhdr->srcaddr);
size = le32_to_cpu(mhdr->blocksize);
struct register_set_hdr_v1 *regset_hdr;
struct ext_hdr_v0_reg *regdata;
struct ext_hdr_v0 *ehdr0;
+ struct bin_hdr_v0 *bhdr0;
struct opt_hdr_v1 *ohdr;
+ int params_count;
unsigned offset;
+ int is_v0_ext;
int cur_idx;
int version;
FILE *f;
version = kwbimage_version(ptr);
+ is_v0_ext = 0;
+ if (version == 0) {
+ if (mhdr0->ext > 1 || mhdr0->bin ||
+ ((ehdr0 = ext_hdr_v0_first(ptr)) &&
+ (ehdr0->match_addr || ehdr0->match_mask || ehdr0->match_value)))
+ is_v0_ext = 1;
+ }
+
if (version != 0)
fprintf(f, "VERSION %d\n", version);
if (mhdr->blockid == IBR_HDR_NAND_ID)
fprintf(f, "NAND_PAGE_SIZE 0x%x\n", (unsigned)mhdr->nandpagesize);
- if (version != 0 && mhdr->blockid == IBR_HDR_NAND_ID) {
+ if (version != 0 && mhdr->blockid == IBR_HDR_NAND_ID)
fprintf(f, "NAND_BLKSZ 0x%x\n", (unsigned)mhdr->nandblocksize);
+
+ if (mhdr->blockid == IBR_HDR_NAND_ID && (mhdr->nandbadblklocation != 0 || is_v0_ext))
fprintf(f, "NAND_BADBLK_LOCATION 0x%x\n", (unsigned)mhdr->nandbadblklocation);
- }
if (version == 0 && mhdr->blockid == IBR_HDR_SATA_ID)
fprintf(f, "SATA_PIO_MODE %u\n", (unsigned)mhdr0->satapiomode);
}
}
- if (version == 0 && mhdr0->ext) {
- ehdr0 = (struct ext_hdr_v0 *)(mhdr0 + 1);
+ if (version == 0 && !is_v0_ext && le16_to_cpu(mhdr0->ddrinitdelay))
+ fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)le16_to_cpu(mhdr0->ddrinitdelay));
+
+ for_each_ext_hdr_v0(ehdr0, ptr) {
+ if (is_v0_ext) {
+ fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
+ le32_to_cpu(ehdr0->match_addr),
+ le32_to_cpu(ehdr0->match_mask),
+ le32_to_cpu(ehdr0->match_value));
+ if (ehdr0->rsvd1[0] || ehdr0->rsvd1[1] || ehdr0->rsvd1[2] ||
+ ehdr0->rsvd1[3] || ehdr0->rsvd1[4] || ehdr0->rsvd1[5] ||
+ ehdr0->rsvd1[6] || ehdr0->rsvd1[7])
+ fprintf(f, "#DDR_RSVD1 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ ehdr0->rsvd1[0], ehdr0->rsvd1[1], ehdr0->rsvd1[2],
+ ehdr0->rsvd1[3], ehdr0->rsvd1[4], ehdr0->rsvd1[5],
+ ehdr0->rsvd1[6], ehdr0->rsvd1[7]);
+ if (ehdr0->rsvd2[0] || ehdr0->rsvd2[1] || ehdr0->rsvd2[2] ||
+ ehdr0->rsvd2[3] || ehdr0->rsvd2[4] || ehdr0->rsvd2[5] ||
+ ehdr0->rsvd2[6])
+ fprintf(f, "#DDR_RSVD2 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ ehdr0->rsvd2[0], ehdr0->rsvd2[1], ehdr0->rsvd2[2],
+ ehdr0->rsvd2[3], ehdr0->rsvd2[4], ehdr0->rsvd2[5],
+ ehdr0->rsvd2[6]);
+ if (ehdr0->ddrwritetype)
+ fprintf(f, "DDR_WRITE_TYPE %u\n", (unsigned)ehdr0->ddrwritetype);
+ if (ehdr0->ddrresetmpp)
+ fprintf(f, "DDR_RESET_MPP 0x%x\n", (unsigned)ehdr0->ddrresetmpp);
+ if (ehdr0->ddrclkenmpp)
+ fprintf(f, "DDR_CLKEN_MPP 0x%x\n", (unsigned)ehdr0->ddrclkenmpp);
+ if (ehdr0->ddrinitdelay)
+ fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)ehdr0->ddrinitdelay);
+ }
+
if (ehdr0->offset) {
for (regdata = (struct ext_hdr_v0_reg *)((uint8_t *)ptr + ehdr0->offset);
- (uint8_t *)regdata < (uint8_t *)ptr + header_size && regdata->raddr &&
- regdata->rdata;
+ (uint8_t *)regdata < (uint8_t *)ptr + header_size &&
+ (regdata->raddr || regdata->rdata);
regdata++)
fprintf(f, "DATA 0x%08x 0x%08x\n", le32_to_cpu(regdata->raddr),
le32_to_cpu(regdata->rdata));
+ if ((uint8_t *)regdata != (uint8_t *)ptr + ehdr0->offset)
+ fprintf(f, "DATA 0x0 0x0\n");
}
+
+ if (le32_to_cpu(ehdr0->enddelay))
+ fprintf(f, "DATA_DELAY %u\n", le32_to_cpu(ehdr0->enddelay));
+ else if (is_v0_ext)
+ fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
}
- if (version == 0 && le16_to_cpu(mhdr0->ddrinitdelay))
- fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)le16_to_cpu(mhdr0->ddrinitdelay));
+ cur_idx = 1;
+ for_each_bin_hdr_v0(bhdr0, ptr) {
+ fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
+ le32_to_cpu(bhdr0->match_addr),
+ le32_to_cpu(bhdr0->match_mask),
+ le32_to_cpu(bhdr0->match_value));
+
+ fprintf(f, "BINARY binary%d.bin", cur_idx);
+ params_count = fls4(bhdr0->params_flags & 0xF);
+ for (i = 0; i < params_count; i++)
+ fprintf(f, " 0x%x", (bhdr0->params[i] & (1 << i)) ? bhdr0->params[i] : 0);
+ fprintf(f, " LOAD_ADDRESS 0x%08x", le32_to_cpu(bhdr0->destaddr));
+ fprintf(f, " EXEC_ADDRESS 0x%08x", le32_to_cpu(bhdr0->execaddr));
+ fprintf(f, "\n");
+
+ fprintf(f, "#BINARY_OFFSET 0x%x\n", le32_to_cpu(bhdr0->offset));
+ fprintf(f, "#BINARY_SIZE 0x%x\n", le32_to_cpu(bhdr0->size));
+
+ if (bhdr0->rsvd1)
+ fprintf(f, "#BINARY_RSVD1 0x%x\n", (unsigned)bhdr0->rsvd1);
+ if (bhdr0->rsvd2)
+ fprintf(f, "#BINARY_RSVD2 0x%x\n", (unsigned)bhdr0->rsvd2);
+
+ cur_idx++;
+ }
/* Undocumented reserved fields */
fprintf(f, "#RSVD1 0x%x 0x%x 0x%x\n", (unsigned)mhdr0->rsvd1[0],
(unsigned)mhdr0->rsvd1[1], (unsigned)mhdr0->rsvd1[2]);
- if (version == 0 && mhdr0->rsvd3)
- fprintf(f, "#RSVD3 0x%x\n", (unsigned)mhdr0->rsvd3);
-
if (version == 0 && le16_to_cpu(mhdr0->rsvd2))
fprintf(f, "#RSVD2 0x%x\n", (unsigned)le16_to_cpu(mhdr0->rsvd2));
{
struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
size_t header_size = kwbheader_size(ptr);
+ struct bin_hdr_v0 *bhdr;
struct opt_hdr_v1 *ohdr;
int idx = params->pflag;
int cur_idx;
++cur_idx;
}
+ for_each_bin_hdr_v0(bhdr, ptr) {
+ if (idx == cur_idx) {
+ image = (ulong)bhdr + bhdr->offset;
+ size = bhdr->size;
+ break;
+ }
+ ++cur_idx;
+ }
if (!image) {
fprintf(stderr, "Argument -p %d is invalid\n", idx);
*/
static int kwbimage_check_params(struct image_tool_params *params)
{
- if (!params->lflag && !params->iflag &&
+ if (!params->lflag && !params->iflag && !params->pflag &&
(!params->imagename || !strlen(params->imagename))) {
char *msg = "Configuration file for kwbimage creation omitted";
uint32_t destaddr; /* 0x10-0x13 */
uint32_t execaddr; /* 0x14-0x17 */
uint8_t satapiomode; /* 0x18 */
- uint8_t rsvd3; /* 0x19 */
+ uint8_t nandblocksize; /* 0x19 */
+ union {
+ uint8_t nandbadblklocation; /* 0x1A */
uint16_t ddrinitdelay; /* 0x1A-0x1B */
- uint16_t rsvd2; /* 0x1C-0x1D */
+ };
+ uint8_t rsvd2; /* 0x1C */
+ uint8_t bin; /* 0x1D */
uint8_t ext; /* 0x1E */
uint8_t checksum; /* 0x1F */
} __packed;
uint32_t rdata;
} __packed;
-#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
-
+/* Structure of the extension header, version 0 (Kirkwood, Dove) */
struct ext_hdr_v0 {
- uint32_t offset;
- uint8_t reserved[0x20 - sizeof(uint32_t)];
- struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
- uint8_t reserved2[7];
- uint8_t checksum;
+ /*
+ * Beware that extension header offsets specified in 88AP510 Functional
+ * Specifications are relative to the start of the main header, not to
+ * the start of the extension header itself.
+ */
+ uint32_t offset; /* 0x0-0x3 */
+ uint8_t rsvd1[8]; /* 0x4-0xB */
+ uint32_t enddelay; /* 0xC-0xF */
+ uint32_t match_addr; /* 0x10-0x13 */
+ uint32_t match_mask; /* 0x14-0x17 */
+ uint32_t match_value; /* 0x18-0x1B */
+ uint8_t ddrwritetype; /* 0x1C */
+ uint8_t ddrresetmpp; /* 0x1D */
+ uint8_t ddrclkenmpp; /* 0x1E */
+ uint8_t ddrinitdelay; /* 0x1F */
+ struct ext_hdr_v0_reg rcfg[55]; /* 0x20-0x1D7 */
+ uint8_t rsvd2[7]; /* 0x1D8-0x1DE */
+ uint8_t checksum; /* 0x1DF */
+} __packed;
+
+/* Structure of the binary code header, version 0 (Dove) */
+struct bin_hdr_v0 {
+ uint32_t match_addr; /* 0x00-0x03 */
+ uint32_t match_mask; /* 0x04-0x07 */
+ uint32_t match_value; /* 0x08-0x0B */
+ uint32_t offset; /* 0x0C-0x0F */
+ uint32_t destaddr; /* 0x10-0x13 */
+ uint32_t size; /* 0x14-0x17 */
+ uint32_t execaddr; /* 0x18-0x1B */
+ uint32_t params[4]; /* 0x1C-0x2B */
+ uint8_t params_flags; /* 0x2C */
+ uint8_t rsvd1; /* 0x2D */
+ uint8_t rsvd2; /* 0x2E */
+ uint8_t checksum; /* 0x2F */
+ uint8_t code[2000]; /* 0x30-0x7FF */
} __packed;
/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
if (kwbimage_version(header) == 0) {
const struct main_hdr_v0 *hdr = header;
+ /*
+ * First extension header starts immediately after the main
+ * header without any padding. Between extension headers is
+ * 0x20 byte padding. There is no padding after the last
+ * extension header. First binary code header starts immediately
+ * after the last extension header (or immediately after the
+ * main header if there is no extension header) without any
+ * padding. There is no padding between binary code headers and
+ * neither after the last binary code header.
+ */
return sizeof(*hdr) +
- hdr->ext ? sizeof(struct ext_hdr_v0) : 0;
+ hdr->ext * sizeof(struct ext_hdr_v0) +
+ ((hdr->ext > 1) ? ((hdr->ext - 1) * 0x20) : 0) +
+ hdr->bin * sizeof(struct bin_hdr_v0);
} else {
const struct main_hdr_v1 *hdr = header;
return kwbheader_size(header);
}
+static inline struct ext_hdr_v0 *ext_hdr_v0_first(void *img)
+{
+ struct main_hdr_v0 *mhdr;
+
+ if (kwbimage_version(img) != 0)
+ return NULL;
+
+ mhdr = img;
+ if (mhdr->ext)
+ return (struct ext_hdr_v0 *)(mhdr + 1);
+ else
+ return NULL;
+}
+
+static inline void *_ext_hdr_v0_end(struct main_hdr_v0 *mhdr)
+{
+ return (uint8_t *)mhdr + kwbheader_size(mhdr) - mhdr->bin * sizeof(struct bin_hdr_v0);
+}
+
+static inline struct ext_hdr_v0 *ext_hdr_v0_next(void *img, struct ext_hdr_v0 *cur)
+{
+ if ((void *)(cur + 1) < _ext_hdr_v0_end(img))
+ return (struct ext_hdr_v0 *)((uint8_t *)(cur + 1) + 0x20);
+ else
+ return NULL;
+}
+
+#define for_each_ext_hdr_v0(ehdr, img) \
+ for ((ehdr) = ext_hdr_v0_first((img)); \
+ (ehdr) != NULL; \
+ (ehdr) = ext_hdr_v0_next((img), (ehdr)))
+
+static inline struct bin_hdr_v0 *bin_hdr_v0_first(void *img)
+{
+ struct main_hdr_v0 *mhdr;
+
+ if (kwbimage_version(img) != 0)
+ return NULL;
+
+ mhdr = img;
+ if (mhdr->bin)
+ return _ext_hdr_v0_end(mhdr);
+ else
+ return NULL;
+}
+
+#define for_each_bin_hdr_v0(bhdr, img) \
+ for ((bhdr) = bin_hdr_v0_first((img)); \
+ (bhdr) && (void *)(bhdr) < (void *)((uint8_t *)img + kwbheader_size(img)); \
+ (bhdr) = (struct bin_hdr_v0 *)((bhdr))+1)
+
static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr)
{
return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);
static int
kwboot_term_pipe(int in, int out, const char *quit, int *s)
{
+ char buf[128];
ssize_t nin;
- char _buf[128], *buf = _buf;
- nin = read(in, buf, sizeof(_buf));
+ nin = read(in, buf, sizeof(buf));
if (nin <= 0)
return -1;
int i;
for (i = 0; i < nin; i++) {
- if (*buf == quit[*s]) {
+ if (buf[i] == quit[*s]) {
(*s)++;
- if (!quit[*s])
- return 0;
- buf++;
- nin--;
+ if (!quit[*s]) {
+ nin = i - *s;
+ break;
+ }
} else {
- if (kwboot_write(out, quit, *s) < 0)
+ if (*s > i && kwboot_write(out, quit, *s - i) < 0)
return -1;
*s = 0;
}
}
+
+ if (i == nin)
+ nin -= *s;
}
if (kwboot_write(out, buf, nin) < 0)
bootmsg = kwboot_msg_boot;
if (prev_optind == optind)
goto usage;
- if (argv[optind] && argv[optind][0] != '-')
+ if (optind < argc - 1 && argv[optind] && argv[optind][0] != '-')
imgpath = argv[optind++];
break;
*/
#include <getopt.h>
-#include <malloc.h>
+#include <pe.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/types.h>
+#include <uuid/uuid.h>
+#include <linux/kconfig.h>
-typedef __u8 u8;
-typedef __u16 u16;
-typedef __u32 u32;
-typedef __u64 u64;
-typedef __s16 s16;
-typedef __s32 s32;
+#include <gnutls/gnutls.h>
+#include <gnutls/pkcs7.h>
+#include <gnutls/abstract.h>
-#define aligned_u64 __aligned_u64
-
-#ifndef __packed
-#define __packed __attribute__((packed))
-#endif
-
-#include <efi.h>
-#include <efi_api.h>
+#include "eficapsule.h"
static const char *tool_name = "mkeficapsule";
EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
efi_guid_t efi_guid_image_type_uboot_raw =
EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID;
+efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
+
+static const char *opts_short = "frg:i:I:v:p:c:m:dh";
static struct option options[] = {
- {"fit", required_argument, NULL, 'f'},
- {"raw", required_argument, NULL, 'r'},
+ {"fit", no_argument, NULL, 'f'},
+ {"raw", no_argument, NULL, 'r'},
+ {"guid", required_argument, NULL, 'g'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
+ {"private-key", required_argument, NULL, 'p'},
+ {"certificate", required_argument, NULL, 'c'},
+ {"monotonic-count", required_argument, NULL, 'm'},
+ {"dump-sig", no_argument, NULL, 'd'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
static void print_usage(void)
{
- printf("Usage: %s [options] <output file>\n"
+ fprintf(stderr, "Usage: %s [options] <image blob> <output file>\n"
"Options:\n"
- "\t-f, --fit <fit image> new FIT image file\n"
- "\t-r, --raw <raw image> new raw image file\n"
+ "\t-f, --fit FIT image type\n"
+ "\t-r, --raw raw image type\n"
+ "\t-g, --guid <guid string> guid for image blob type\n"
"\t-i, --index <index> update image index\n"
"\t-I, --instance <instance> update hardware instance\n"
+ "\t-p, --private-key <privkey file> private key file\n"
+ "\t-c, --certificate <cert file> signer's certificate file\n"
+ "\t-m, --monotonic-count <count> monotonic count\n"
+ "\t-d, --dump_sig dump signature (*.p7)\n"
"\t-h, --help print a help message\n",
tool_name);
}
/**
+ * auth_context - authentication context
+ * @key_file: Path to a private key file
+ * @cert_file: Path to a certificate file
+ * @image_data: Pointer to firmware data
+ * @image_size: Size of firmware data
+ * @auth: Authentication header
+ * @sig_data: Signature data
+ * @sig_size: Size of signature data
+ *
+ * Data structure used in create_auth_data(). @key_file through
+ * @image_size are input parameters. @auth, @sig_data and @sig_size
+ * are filled in by create_auth_data().
+ */
+struct auth_context {
+ char *key_file;
+ char *cert_file;
+ uint8_t *image_data;
+ size_t image_size;
+ struct efi_firmware_image_authentication auth;
+ uint8_t *sig_data;
+ size_t sig_size;
+};
+
+static int dump_sig;
+
+/**
* read_bin_file - read a firmware binary file
* @bin: Path to a firmware binary file
* @data: Pointer to pointer of allocated buffer
* * 0 - on success
* * -1 - on failure
*/
-static int read_bin_file(char *bin, void **data, off_t *bin_size)
+static int read_bin_file(char *bin, uint8_t **data, off_t *bin_size)
{
FILE *g;
struct stat bin_stat;
}
/**
+ * create_auth_data - compose authentication data in capsule
+ * @auth_context: Pointer to authentication context
+ *
+ * Fill up an authentication header (.auth) and signature data (.sig_data)
+ * in @auth_context, using library functions from openssl.
+ * All the parameters in @auth_context must be filled in by a caller.
+ *
+ * Return:
+ * * 0 - on success
+ * * -1 - on failure
+ */
+static int create_auth_data(struct auth_context *ctx)
+{
+ gnutls_datum_t cert;
+ gnutls_datum_t key;
+ off_t file_size;
+ gnutls_privkey_t pkey;
+ gnutls_x509_crt_t x509;
+ gnutls_pkcs7_t pkcs7;
+ gnutls_datum_t data;
+ gnutls_datum_t signature;
+ int ret;
+
+ ret = read_bin_file(ctx->cert_file, &cert.data, &file_size);
+ if (ret < 0)
+ return -1;
+ if (file_size > UINT_MAX)
+ return -1;
+ cert.size = file_size;
+
+ ret = read_bin_file(ctx->key_file, &key.data, &file_size);
+ if (ret < 0)
+ return -1;
+ if (file_size > UINT_MAX)
+ return -1;
+ key.size = file_size;
+
+ /*
+ * For debugging,
+ * gnutls_global_set_time_function(mytime);
+ * gnutls_global_set_log_function(tls_log_func);
+ * gnutls_global_set_log_level(6);
+ */
+
+ ret = gnutls_privkey_init(&pkey);
+ if (ret < 0) {
+ fprintf(stderr, "error in gnutls_privkey_init(): %s\n",
+ gnutls_strerror(ret));
+ return -1;
+ }
+
+ ret = gnutls_x509_crt_init(&x509);
+ if (ret < 0) {
+ fprintf(stderr, "error in gnutls_x509_crt_init(): %s\n",
+ gnutls_strerror(ret));
+ return -1;
+ }
+
+ /* load a private key */
+ ret = gnutls_privkey_import_x509_raw(pkey, &key, GNUTLS_X509_FMT_PEM,
+ 0, 0);
+ if (ret < 0) {
+ fprintf(stderr,
+ "error in gnutls_privkey_import_x509_raw(): %s\n",
+ gnutls_strerror(ret));
+ return -1;
+ }
+
+ /* load x509 certificate */
+ ret = gnutls_x509_crt_import(x509, &cert, GNUTLS_X509_FMT_PEM);
+ if (ret < 0) {
+ fprintf(stderr, "error in gnutls_x509_crt_import(): %s\n",
+ gnutls_strerror(ret));
+ return -1;
+ }
+
+ /* generate a PKCS #7 structure */
+ ret = gnutls_pkcs7_init(&pkcs7);
+ if (ret < 0) {
+ fprintf(stderr, "error in gnutls_pkcs7_init(): %s\n",
+ gnutls_strerror(ret));
+ return -1;
+ }
+
+ /* sign */
+ /*
+ * Data should have
+ * * firmware image
+ * * monotonic count
+ * in this order!
+ * See EDK2's FmpAuthenticatedHandlerRsa2048Sha256()
+ */
+ data.size = ctx->image_size + sizeof(ctx->auth.monotonic_count);
+ data.data = malloc(data.size);
+ if (!data.data) {
+ fprintf(stderr, "allocating memory (0x%x) failed\n", data.size);
+ return -1;
+ }
+ memcpy(data.data, ctx->image_data, ctx->image_size);
+ memcpy(data.data + ctx->image_size, &ctx->auth.monotonic_count,
+ sizeof(ctx->auth.monotonic_count));
+
+ ret = gnutls_pkcs7_sign(pkcs7, x509, pkey, &data, NULL, NULL,
+ GNUTLS_DIG_SHA256,
+ /* GNUTLS_PKCS7_EMBED_DATA? */
+ GNUTLS_PKCS7_INCLUDE_CERT |
+ GNUTLS_PKCS7_INCLUDE_TIME);
+ if (ret < 0) {
+ fprintf(stderr, "error in gnutls_pkcs7)sign(): %s\n",
+ gnutls_strerror(ret));
+ return -1;
+ }
+
+ /* export */
+ ret = gnutls_pkcs7_export2(pkcs7, GNUTLS_X509_FMT_DER, &signature);
+ if (ret < 0) {
+ fprintf(stderr, "error in gnutls_pkcs7_export2: %s\n",
+ gnutls_strerror(ret));
+ return -1;
+ }
+ ctx->sig_data = signature.data;
+ ctx->sig_size = signature.size;
+
+ /* fill auth_info */
+ ctx->auth.auth_info.hdr.dwLength = sizeof(ctx->auth.auth_info)
+ + ctx->sig_size;
+ ctx->auth.auth_info.hdr.wRevision = WIN_CERT_REVISION_2_0;
+ ctx->auth.auth_info.hdr.wCertificateType = WIN_CERT_TYPE_EFI_GUID;
+ memcpy(&ctx->auth.auth_info.cert_type, &efi_guid_cert_type_pkcs7,
+ sizeof(efi_guid_cert_type_pkcs7));
+
+ /*
+ * For better clean-ups,
+ * gnutls_pkcs7_deinit(pkcs7);
+ * gnutls_privkey_deinit(pkey);
+ * gnutls_x509_crt_deinit(x509);
+ * free(cert.data);
+ * free(key.data);
+ * if error
+ * gnutls_free(signature.data);
+ */
+
+ return 0;
+}
+
+/**
+ * dump_signature - dump out a signature
+ * @path: Path to a capsule file
+ * @signature: Signature data
+ * @sig_size: Size of signature data
+ *
+ * Signature data pointed to by @signature will be saved into
+ * a file whose file name is @path with ".p7" suffix.
+ *
+ * Return:
+ * * 0 - on success
+ * * -1 - on failure
+ */
+static int dump_signature(const char *path, uint8_t *signature, size_t sig_size)
+{
+ char *sig_path;
+ FILE *f;
+ size_t size;
+ int ret = -1;
+
+ sig_path = malloc(strlen(path) + 3 + 1);
+ if (!sig_path)
+ return ret;
+
+ sprintf(sig_path, "%s.p7", path);
+ f = fopen(sig_path, "w");
+ if (!f)
+ goto err;
+
+ size = fwrite(signature, 1, sig_size, f);
+ if (size == sig_size)
+ ret = 0;
+
+ fclose(f);
+err:
+ free(sig_path);
+ return ret;
+}
+
+/**
+ * free_sig_data - free out signature data
+ * @ctx: Pointer to authentication context
+ *
+ * Free signature data allocated in create_auth_data().
+ */
+static void free_sig_data(struct auth_context *ctx)
+{
+ if (ctx->sig_size)
+ gnutls_free(ctx->sig_data);
+}
+
+/**
* create_fwbin - create an uefi capsule file
* @path: Path to a created capsule file
* @bin: Path to a firmware binary to encapsulate
* * -1 - on failure
*/
static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
- unsigned long index, unsigned long instance)
+ unsigned long index, unsigned long instance,
+ uint64_t mcount, char *privkey_file, char *cert_file)
{
struct efi_capsule_header header;
struct efi_firmware_management_capsule_header capsule;
struct efi_firmware_management_capsule_image_header image;
+ struct auth_context auth_context;
FILE *f;
- void *data;
+ uint8_t *data;
off_t bin_size;
- u64 offset;
+ uint64_t offset;
int ret;
#ifdef DEBUG
- printf("For output: %s\n", path);
- printf("\tbin: %s\n\ttype: %pUl\n", bin, guid);
- printf("\tindex: %ld\n\tinstance: %ld\n", index, instance);
+ fprintf(stderr, "For output: %s\n", path);
+ fprintf(stderr, "\tbin: %s\n\ttype: %pUl\n", bin, guid);
+ fprintf(stderr, "\tindex: %lu\n\tinstance: %lu\n", index, instance);
#endif
-
+ auth_context.sig_size = 0;
f = NULL;
data = NULL;
ret = -1;
if (read_bin_file(bin, &data, &bin_size))
goto err;
+ /* first, calculate signature to determine its size */
+ if (privkey_file && cert_file) {
+ auth_context.key_file = privkey_file;
+ auth_context.cert_file = cert_file;
+ auth_context.auth.monotonic_count = mcount;
+ auth_context.image_data = data;
+ auth_context.image_size = bin_size;
+
+ if (create_auth_data(&auth_context)) {
+ fprintf(stderr, "Signing firmware image failed\n");
+ goto err;
+ }
+
+ if (dump_sig &&
+ dump_signature(path, auth_context.sig_data,
+ auth_context.sig_size)) {
+ fprintf(stderr, "Creating signature file failed\n");
+ goto err;
+ }
+ }
+
/*
* write a capsule file
*/
/* TODO: The current implementation ignores flags */
header.flags = CAPSULE_FLAGS_PERSIST_ACROSS_RESET;
header.capsule_image_size = sizeof(header)
- + sizeof(capsule) + sizeof(u64)
+ + sizeof(capsule) + sizeof(uint64_t)
+ sizeof(image)
+ bin_size;
+ if (auth_context.sig_size)
+ header.capsule_image_size += sizeof(auth_context.auth)
+ + auth_context.sig_size;
if (write_capsule_file(f, &header, sizeof(header),
"Capsule header"))
goto err;
"Firmware capsule header"))
goto err;
- offset = sizeof(capsule) + sizeof(u64);
+ offset = sizeof(capsule) + sizeof(uint64_t);
if (write_capsule_file(f, &offset, sizeof(offset),
"Offset to capsule image"))
goto err;
image.reserved[1] = 0;
image.reserved[2] = 0;
image.update_image_size = bin_size;
+ if (auth_context.sig_size)
+ image.update_image_size += sizeof(auth_context.auth)
+ + auth_context.sig_size;
image.update_vendor_code_size = 0; /* none */
image.update_hardware_instance = instance;
image.image_capsule_support = 0;
+ if (auth_context.sig_size)
+ image.image_capsule_support |= CAPSULE_SUPPORT_AUTHENTICATION;
if (write_capsule_file(f, &image, sizeof(image),
"Firmware capsule image header"))
goto err;
/*
+ * signature
+ */
+ if (auth_context.sig_size) {
+ if (write_capsule_file(f, &auth_context.auth,
+ sizeof(auth_context.auth),
+ "Authentication header"))
+ goto err;
+
+ if (write_capsule_file(f, auth_context.sig_data,
+ auth_context.sig_size, "Signature"))
+ goto err;
+ }
+
+ /*
* firmware binary
*/
if (write_capsule_file(f, data, bin_size, "Firmware binary"))
err:
if (f)
fclose(f);
+ free_sig_data(&auth_context);
free(data);
return ret;
}
-/*
- * Usage:
- * $ mkeficapsule -f <firmware binary> <output file>
+/**
+ * convert_uuid_to_guid() - convert UUID to GUID
+ * @buf: UUID binary
+ *
+ * UUID and GUID have the same data structure, but their binary
+ * formats are different due to the endianness. See lib/uuid.c.
+ * Since uuid_parse() can handle only UUID, this function must
+ * be called to get correct data for GUID when parsing a string.
+ *
+ * The correct data will be returned in @buf.
+ */
+void convert_uuid_to_guid(unsigned char *buf)
+{
+ unsigned char c;
+
+ c = buf[0];
+ buf[0] = buf[3];
+ buf[3] = c;
+ c = buf[1];
+ buf[1] = buf[2];
+ buf[2] = c;
+
+ c = buf[4];
+ buf[4] = buf[5];
+ buf[5] = c;
+
+ c = buf[6];
+ buf[6] = buf[7];
+ buf[7] = c;
+}
+
+/**
+ * main - main entry function of mkeficapsule
+ * @argc: Number of arguments
+ * @argv: Array of pointers to arguments
+ *
+ * Create an uefi capsule file, optionally signing it.
+ * Parse all the arguments and pass them on to create_fwbin().
+ *
+ * Return:
+ * * 0 - on success
+ * * -1 - on failure
*/
int main(int argc, char **argv)
{
- char *file;
efi_guid_t *guid;
+ unsigned char uuid_buf[16];
unsigned long index, instance;
+ uint64_t mcount;
+ char *privkey_file, *cert_file;
int c, idx;
- file = NULL;
guid = NULL;
index = 0;
instance = 0;
+ mcount = 0;
+ privkey_file = NULL;
+ cert_file = NULL;
+ dump_sig = 0;
for (;;) {
- c = getopt_long(argc, argv, "f:r:i:I:v:h", options, &idx);
+ c = getopt_long(argc, argv, opts_short, options, &idx);
if (c == -1)
break;
switch (c) {
case 'f':
- if (file) {
- fprintf(stderr, "Image already specified\n");
- return -1;
+ if (guid) {
+ fprintf(stderr,
+ "Image type already specified\n");
+ exit(EXIT_FAILURE);
}
- file = optarg;
guid = &efi_guid_image_type_uboot_fit;
break;
case 'r':
- if (file) {
- fprintf(stderr, "Image already specified\n");
- return -1;
+ if (guid) {
+ fprintf(stderr,
+ "Image type already specified\n");
+ exit(EXIT_FAILURE);
}
- file = optarg;
guid = &efi_guid_image_type_uboot_raw;
break;
+ case 'g':
+ if (guid) {
+ fprintf(stderr,
+ "Image type already specified\n");
+ exit(EXIT_FAILURE);
+ }
+ if (uuid_parse(optarg, uuid_buf)) {
+ fprintf(stderr, "Wrong guid format\n");
+ exit(EXIT_FAILURE);
+ }
+ convert_uuid_to_guid(uuid_buf);
+ guid = (efi_guid_t *)uuid_buf;
+ break;
case 'i':
index = strtoul(optarg, NULL, 0);
break;
case 'I':
instance = strtoul(optarg, NULL, 0);
break;
+ case 'p':
+ if (privkey_file) {
+ fprintf(stderr,
+ "Private Key already specified\n");
+ exit(EXIT_FAILURE);
+ }
+ privkey_file = optarg;
+ break;
+ case 'c':
+ if (cert_file) {
+ fprintf(stderr,
+ "Certificate file already specified\n");
+ exit(EXIT_FAILURE);
+ }
+ cert_file = optarg;
+ break;
+ case 'm':
+ mcount = strtoul(optarg, NULL, 0);
+ break;
+ case 'd':
+ dump_sig = 1;
+ break;
case 'h':
print_usage();
- return 0;
+ exit(EXIT_SUCCESS);
}
}
- /* need an output file */
- if (argc != optind + 1) {
+ /* check necessary parameters */
+ if ((argc != optind + 2) || !guid ||
+ ((privkey_file && !cert_file) ||
+ (!privkey_file && cert_file))) {
print_usage();
exit(EXIT_FAILURE);
}
- /* need a fit image file or raw image file */
- if (!file) {
- print_usage();
- exit(EXIT_SUCCESS);
- }
-
- if (create_fwbin(argv[optind], file, guid, index, instance)
- < 0) {
+ if (create_fwbin(argv[argc - 1], argv[argc - 2], guid, index, instance,
+ mcount, privkey_file, cert_file) < 0) {
fprintf(stderr, "Creating firmware capsule failed\n");
exit(EXIT_FAILURE);
}
static void usage(const char *msg)
{
fprintf(stderr, "Error: %s\n", msg);
- fprintf(stderr, "Usage: %s -l image\n"
- " -l ==> list image header information\n",
+ fprintf(stderr, "Usage: %s [-T type] -l image\n"
+ " -l ==> list image header information\n"
+ " -T ==> parse image file as 'type'\n",
params.cmdname);
fprintf(stderr,
" %s [-x] -A arch -O os -T type -C comp -a addr -e ep -n name -d data_file[:data_file...] image\n"
params.datafile = datafile;
else if (!params.datafile)
usage("Missing data file for auto-FIT (use -d)");
- } else if (type != IH_TYPE_INVALID) {
+ } else if (params.lflag || type != IH_TYPE_INVALID) {
if (type == IH_TYPE_SCRIPT && !params.datafile)
usage("Missing data file for script (use -d)");
params.type = type;
/* set tparams as per input type_id */
tparams = imagetool_get_type(params.type);
- if (tparams == NULL) {
+ if (tparams == NULL && !params.lflag) {
fprintf (stderr, "%s: unsupported type %s\n",
params.cmdname, genimg_get_type_name(params.type));
exit (EXIT_FAILURE);
* check the passed arguments parameters meets the requirements
* as per image type to be generated/listed
*/
- if (tparams->check_params)
+ if (tparams && tparams->check_params)
if (tparams->check_params (¶ms))
usage("Bad parameters for image type");
if (!params.eflag) {
params.ep = params.addr;
/* If XIP, entry point must be after the U-Boot header */
- if (params.xflag)
+ if (params.xflag && tparams)
params.ep += tparams->header_size;
}
params.cmdname, params.imagefile);
exit (EXIT_FAILURE);
#endif
- } else if (sbuf.st_size < (off_t)tparams->header_size) {
+ } else if (tparams && sbuf.st_size < (off_t)tparams->header_size) {
fprintf (stderr,
"%s: Bad size: \"%s\" is not valid image: size %llu < %u\n",
params.cmdname, params.imagefile,
exit (EXIT_FAILURE);
}
- if (params.fflag) {
- /*
- * Verifies the header format based on the expected header for image
- * type in tparams
- */
- retval = imagetool_verify_print_header_by_type(ptr, &sbuf,
- tparams, ¶ms);
- } else {
- /**
- * When listing the image, we are not given the image type. Simply check all
- * image types to find one that matches our header
- */
- retval = imagetool_verify_print_header(ptr, &sbuf,
- tparams, ¶ms);
- }
+ /*
+ * Verifies the header format based on the expected header for image
+ * type in tparams. If tparams is NULL simply check all image types
+ * to find one that matches our header.
+ */
+ retval = imagetool_verify_print_header(ptr, &sbuf, tparams, ¶ms);
(void) munmap((void *)ptr, sbuf.st_size);
(void) close (ifd);
'SZ_4G': 0x100000000
}
+RE_REMOVE_DEFCONFIG = re.compile(r'(.*)_defconfig')
+
### helper functions ###
+def remove_defconfig(defc):
+ """Drop the _defconfig suffix on a string
+
+ Args:
+ defc (str): String to convert
+
+ Returns:
+ str: string with the '_defconfig' suffix removed
+ """
+ return RE_REMOVE_DEFCONFIG.match(defc)[1]
+
def check_top_directory():
"""Exit if we are not at the top of source directory."""
for fname in 'README', 'Licenses':
for linenum in sorted(linenums, reverse=True):
add_imply_rule(config[CONFIG_LEN:], fname, linenum)
+def defconfig_matches(configs, re_match):
+ """Check if any CONFIG option matches a regex
+
+ The match must be complete, i.e. from the start to end of the CONFIG option.
+
+ Args:
+ configs (dict): Dict of CONFIG options:
+ key: CONFIG option
+ value: Value of option
+ re_match (re.Pattern): Match to check
+
+ Returns:
+ bool: True if any CONFIG matches the regex
+ """
+ for cfg in configs:
+ m_cfg = re_match.match(cfg)
+ if m_cfg and m_cfg.span()[1] == len(cfg):
+ return True
+ return False
def do_find_config(config_list):
"""Find boards with a given combination of CONFIGs
Params:
- config_list: List of CONFIG options to check (each a string consisting
+ config_list: List of CONFIG options to check (each a regex consisting
of a config option, with or without a CONFIG_ prefix. If an option
is preceded by a tilde (~) then it must be false, otherwise it must
be true)
# running for the next stage
in_list = out
out = set()
+ re_match = re.compile(cfg)
for defc in in_list:
- has_cfg = cfg in config_db[defc]
+ has_cfg = defconfig_matches(config_db[defc], re_match)
if has_cfg == want:
out.add(defc)
if adhoc:
print(f"Error: Not in Kconfig: %s" % ' '.join(adhoc))
else:
print(f'{len(out)} matches')
- print(' '.join(out))
+ print(' '.join([remove_defconfig(item) for item in out]))
def prefix_config(cfg):
size_t len;
fp = fopen(ictx->cfg_filename, "r");
- if (!fp)
- goto err_file;
+ if (!fp) {
+ fprintf(stderr, "ERR: Failed to load file \"%s\": \"%s\"\n",
+ ictx->cfg_filename, strerror(errno));
+ return -EINVAL;
+ }
while ((rlen = getline(&line, &len, fp)) > 0) {
memset(&cmd, 0, sizeof(cmd));
fclose(fp);
return 0;
-
-err_file:
- fclose(fp);
- fprintf(stderr, "ERR: Failed to load file \"%s\"\n",
- ictx->cfg_filename);
- return -EINVAL;
}
static int sb_build_tree_from_cfg(struct sb_image_ctx *ictx)
RE_NOTE = re.compile(r'NOTE: (.*)')
-def FindCheckPatch():
- top_level = gitutil.GetTopLevel()
+def find_check_patch():
+ top_level = gitutil.get_top_level()
try_list = [
os.getcwd(),
os.path.join(os.getcwd(), '..', '..'),
'~/bin directory or use --no-check')
-def CheckPatchParseOneMessage(message):
+def check_patch_parse_one_message(message):
"""Parse one checkpatch message
Args:
return item
-def CheckPatchParse(checkpatch_output, verbose=False):
+def check_patch_parse(checkpatch_output, verbose=False):
"""Parse checkpatch.pl output
Args:
elif re_bad.match(message):
result.ok = False
else:
- problem = CheckPatchParseOneMessage(message)
+ problem = check_patch_parse_one_message(message)
if problem:
result.problems.append(problem)
return result
-def CheckPatch(fname, verbose=False, show_types=False):
+def check_patch(fname, verbose=False, show_types=False):
"""Run checkpatch.pl on a file and parse the results.
Args:
lines: Number of lines
stdout: Full output of checkpatch
"""
- chk = FindCheckPatch()
+ chk = find_check_patch()
args = [chk, '--no-tree']
if show_types:
args.append('--show-types')
- output = command.Output(*args, fname, raise_on_error=False)
+ output = command.output(*args, fname, raise_on_error=False)
- return CheckPatchParse(output, verbose)
+ return check_patch_parse(output, verbose)
-def GetWarningMsg(col, msg_type, fname, line, msg):
+def get_warning_msg(col, msg_type, fname, line, msg):
'''Create a message for a given file/line
Args:
msg: Message to report
'''
if msg_type == 'warning':
- msg_type = col.Color(col.YELLOW, msg_type)
+ msg_type = col.build(col.YELLOW, msg_type)
elif msg_type == 'error':
- msg_type = col.Color(col.RED, msg_type)
+ msg_type = col.build(col.RED, msg_type)
elif msg_type == 'check':
- msg_type = col.Color(col.MAGENTA, msg_type)
+ msg_type = col.build(col.MAGENTA, msg_type)
line_str = '' if line is None else '%d' % line
return '%s:%s: %s: %s\n' % (fname, line_str, msg_type, msg)
-def CheckPatches(verbose, args):
+def check_patches(verbose, args):
'''Run the checkpatch.pl script on each patch'''
error_count, warning_count, check_count = 0, 0, 0
col = terminal.Color()
for fname in args:
- result = CheckPatch(fname, verbose)
+ result = check_patch(fname, verbose)
if not result.ok:
error_count += result.errors
warning_count += result.warnings
check_count += result.checks
print('%d errors, %d warnings, %d checks for %s:' % (result.errors,
- result.warnings, result.checks, col.Color(col.BLUE, fname)))
+ result.warnings, result.checks, col.build(col.BLUE, fname)))
if (len(result.problems) != result.errors + result.warnings +
result.checks):
print("Internal error: some problems lost")
for item in result.problems:
sys.stderr.write(
- GetWarningMsg(col, item.get('type', '<unknown>'),
+ get_warning_msg(col, item.get('type', '<unknown>'),
item.get('file', '<unknown>'),
item.get('line', 0), item.get('msg', 'message')))
print
color = col.YELLOW
if error_count:
color = col.RED
- print(col.Color(color, str % (error_count, warning_count, check_count)))
+ print(col.build(color, str % (error_count, warning_count, check_count)))
return False
return True
self.return_code = return_code
self.exception = exception
- def ToOutput(self, binary):
+ def to_output(self, binary):
if not binary:
self.stdout = self.stdout.decode('utf-8')
self.stderr = self.stderr.decode('utf-8')
# This permits interception of RunPipe for test purposes. If it is set to
# a function, then that function is called with the pipe list being
# executed. Otherwise, it is assumed to be a CommandResult object, and is
-# returned as the result for every RunPipe() call.
+# returned as the result for every run_pipe() call.
# When this value is None, commands are executed as normal.
test_result = None
-def RunPipe(pipe_list, infile=None, outfile=None,
+def run_pipe(pipe_list, infile=None, outfile=None,
capture=False, capture_stderr=False, oneline=False,
raise_on_error=True, cwd=None, binary=False,
output_func=None, **kwargs):
if raise_on_error:
raise Exception("Error running '%s': %s" % (user_pipestr, str))
result.return_code = 255
- return result.ToOutput(binary)
+ return result.to_output(binary)
if capture:
result.stdout, result.stderr, result.combined = (
- last_pipe.CommunicateFilter(output_func))
+ last_pipe.communicate_filter(output_func))
if result.stdout and oneline:
result.output = result.stdout.rstrip(b'\r\n')
result.return_code = last_pipe.wait()
result.return_code = os.waitpid(last_pipe.pid, 0)[1]
if raise_on_error and result.return_code:
raise Exception("Error running '%s'" % user_pipestr)
- return result.ToOutput(binary)
+ return result.to_output(binary)
-def Output(*cmd, **kwargs):
+def output(*cmd, **kwargs):
kwargs['raise_on_error'] = kwargs.get('raise_on_error', True)
- return RunPipe([cmd], capture=True, **kwargs).stdout
+ return run_pipe([cmd], capture=True, **kwargs).stdout
-def OutputOneLine(*cmd, **kwargs):
+def output_one_line(*cmd, **kwargs):
"""Run a command and output it as a single-line string
The command us expected to produce a single line of output
String containing output of command
"""
raise_on_error = kwargs.pop('raise_on_error', True)
- result = RunPipe([cmd], capture=True, oneline=True,
+ result = run_pipe([cmd], capture=True, oneline=True,
raise_on_error=raise_on_error, **kwargs).stdout.strip()
return result
-def Run(*cmd, **kwargs):
- return RunPipe([cmd], **kwargs).stdout
+def run(*cmd, **kwargs):
+ return run_pipe([cmd], **kwargs).stdout
-def RunList(cmd):
- return RunPipe([cmd], capture=True).stdout
+def run_list(cmd):
+ return run_pipe([cmd], capture=True).stdout
-def StopAll():
+def stop_all():
cros_subprocess.stay_alive = False
def __str__(self):
return self.subject
- def AddChange(self, version, info):
+ def add_change(self, version, info):
"""Add a new change line to the change list for a version.
Args:
self.changes[version] = []
self.changes[version].append(info)
- def CheckTags(self):
+ def check_tags(self):
"""Create a list of subject tags in the commit
Subject tags look like this:
str = m.group(2)
return None
- def AddCc(self, cc_list):
+ def add_cc(self, cc_list):
"""Add a list of people to Cc when we send this patch.
Args:
"""
self.cc_list += cc_list
- def CheckDuplicateSignoff(self, signoff):
+ def check_duplicate_signoff(self, signoff):
"""Check a list of signoffs we have send for this patch
Args:
self.signoff_set.add(signoff)
return True
- def AddRtag(self, rtag_type, who):
+ def add_rtag(self, rtag_type, who):
"""Add a response tag to a commit
Args:
def setup():
"""Do required setup before doing anything"""
- gitutil.Setup()
+ gitutil.setup()
def prepare_patches(col, branch, count, start, end, ignore_binary, signoff):
"""Figure out what patches to generate, then generate them
"""
if count == -1:
# Work out how many patches to send if we can
- count = (gitutil.CountCommitsToBranch(branch) - start)
+ count = (gitutil.count_commits_to_branch(branch) - start)
if not count:
str = 'No commits found to process - please use -c flag, or run:\n' \
' git branch --set-upstream-to remote/branch'
- sys.exit(col.Color(col.RED, str))
+ sys.exit(col.build(col.RED, str))
# Read the metadata from the commits
to_do = count - end
series = patchstream.get_metadata(branch, start, to_do)
- cover_fname, patch_files = gitutil.CreatePatches(
+ cover_fname, patch_files = gitutil.create_patches(
branch, start, to_do, ignore_binary, series, signoff)
# Fix up the patch files to our liking, and insert the cover letter
# Check the patches, and run them through 'git am' just to be sure
if run_checkpatch:
- ok = checkpatch.CheckPatches(verbose, patch_files)
+ ok = checkpatch.check_patches(verbose, patch_files)
else:
ok = True
return ok
# Email the patches out (giving the user time to check / cancel)
cmd = ''
if its_a_go:
- cmd = gitutil.EmailPatches(
+ cmd = gitutil.email_patches(
series, cover_fname, patch_files, dry_run, not ignore_bad_tags,
cc_file, in_reply_to=in_reply_to, thread=thread,
smtp_server=smtp_server)
else:
- print(col.Color(col.RED, "Not sending emails due to errors/warnings"))
+ print(col.build(col.RED, "Not sending emails due to errors/warnings"))
# For a dry run, just show our actions as a sanity check
if dry_run:
series.ShowActions(patch_files, cmd, process_tags)
if not its_a_go:
- print(col.Color(col.RED, "Email would not be sent"))
+ print(col.build(col.RED, "Email would not be sent"))
os.remove(cc_file)
ok = check_patches(series, patch_files, args.check_patch,
args.verbose)
- ok = ok and gitutil.CheckSuppressCCConfig()
+ ok = ok and gitutil.check_suppress_cc_config()
its_a_go = ok or args.ignore_errors
email_patches(
"""
if count == -1:
# Work out how many patches to send if we can
- count = (gitutil.CountCommitsToBranch(branch) - start)
+ count = (gitutil.count_commits_to_branch(branch) - start)
series = patchstream.get_metadata(branch, start, count - end)
warnings = 0
to us as soon as it is produced, rather than waiting for the end of a
line.
- Use CommunicateFilter() to handle output from the subprocess.
+ Use communicate_filter() to handle output from the subprocess.
"""
if kwargs:
raise ValueError("Unit tests do not test extra args - please add tests")
- def ConvertData(self, data):
+ def convert_data(self, data):
"""Convert stdout/stderr data to the correct format for output
Args:
return b''
return data
- def CommunicateFilter(self, output):
+ def communicate_filter(self, output):
"""Interact with process: Read data from stdout and stderr.
This method runs until end-of-file is reached, then waits for the
The output function is sent all output from the subprocess and must be
defined like this:
- def Output([self,] stream, data)
+ def output([self,] stream, data)
Args:
stream: the stream the output was received on, which will be
sys.stdout or sys.stderr.
self.terminate()
# All data exchanged. Translate lists into strings.
- stdout = self.ConvertData(stdout)
- stderr = self.ConvertData(stderr)
- combined = self.ConvertData(combined)
+ stdout = self.convert_data(stdout)
+ stderr = self.convert_data(stderr)
+ combined = self.convert_data(combined)
# Translate newlines, if requested. We cannot let the file
# object do the translation: It is based on stdio, which is
self.stdin_read_pipe = pipe[0]
self._stdin_write_pipe = os.fdopen(pipe[1], 'w')
- def Output(self, stream, data):
+ def output(self, stream, data):
"""Output handler for Popen. Stores the data for later comparison"""
if stream == sys.stdout:
self.stdout_data += data
self._stdin_write_pipe.write(self._input_to_send + '\r\n')
self._stdin_write_pipe.flush()
- def _BasicCheck(self, plist, oper):
+ def _basic_check(self, plist, oper):
"""Basic checks that the output looks sane."""
self.assertEqual(plist[0], oper.stdout_data)
self.assertEqual(plist[1], oper.stderr_data)
def test_simple(self):
"""Simple redirection: Get process list"""
oper = TestSubprocess.MyOperation()
- plist = Popen(['ps']).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen(['ps']).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
def test_stderr(self):
"""Check stdout and stderr"""
oper = TestSubprocess.MyOperation()
cmd = 'echo fred >/dev/stderr && false || echo bad'
- plist = Popen([cmd], shell=True).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen([cmd], shell=True).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(plist [0], 'bad\r\n')
self.assertEqual(plist [1], 'fred\r\n')
oper = TestSubprocess.MyOperation()
cmd = 'echo test >/dev/stderr'
self.assertRaises(OSError, Popen, [cmd], shell=False)
- plist = Popen([cmd], shell=True).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen([cmd], shell=True).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(len(plist [0]), 0)
self.assertEqual(plist [1], 'test\r\n')
"""Check with and without shell works using list arguments"""
oper = TestSubprocess.MyOperation()
cmd = ['echo', 'test', '>/dev/stderr']
- plist = Popen(cmd, shell=False).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen(cmd, shell=False).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(plist [0], ' '.join(cmd[1:]) + '\r\n')
self.assertEqual(len(plist [1]), 0)
# this should be interpreted as 'echo' with the other args dropped
cmd = ['echo', 'test', '>/dev/stderr']
- plist = Popen(cmd, shell=True).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen(cmd, shell=True).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(plist [0], '\r\n')
def test_cwd(self):
"""Check we can change directory"""
for shell in (False, True):
oper = TestSubprocess.MyOperation()
- plist = Popen('pwd', shell=shell, cwd='/tmp').CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen('pwd', shell=shell, cwd='/tmp').communicate_filter(
+ oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(plist [0], '/tmp\r\n')
def test_env(self):
if add:
env ['FRED'] = 'fred'
cmd = 'echo $FRED'
- plist = Popen(cmd, shell=True, env=env).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen(cmd, shell=True, env=env).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(plist [0], add and 'fred\r\n' or '\r\n')
def test_extra_args(self):
prompt = 'What is your name?: '
cmd = 'echo -n "%s"; read name; echo Hello $name' % prompt
plist = Popen([cmd], stdin=oper.stdin_read_pipe,
- shell=True).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ shell=True).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(len(plist [1]), 0)
self.assertEqual(plist [0], prompt + 'Hello Flash\r\r\n')
both_cmds = ''
for fd in (1, 2):
both_cmds += cmd % (fd, fd, fd, fd, fd)
- plist = Popen(both_cmds, shell=True).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ plist = Popen(both_cmds, shell=True).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(plist [0], 'terminal 1\r\n')
self.assertEqual(plist [1], 'terminal 2\r\n')
# Now try with PIPE and make sure it is not a terminal
oper = TestSubprocess.MyOperation()
plist = Popen(both_cmds, stdout=subprocess.PIPE, stderr=subprocess.PIPE,
- shell=True).CommunicateFilter(oper.Output)
- self._BasicCheck(plist, oper)
+ shell=True).communicate_filter(oper.output)
+ self._basic_check(plist, oper)
self.assertEqual(plist [0], 'not 1\n')
self.assertEqual(plist [1], 'not 2\n')
def tearDown(self):
shutil.rmtree(self.tmpdir)
- terminal.SetPrintTestMode(False)
+ terminal.set_print_test_mode(False)
@staticmethod
def _get_path(fname):
return cover_fname, fname_list
- def testBasic(self):
+ def test_basic(self):
"""Tests the basic flow of patman
This creates a series from some hard-coded patches build from a simple
cc_file = series.MakeCcFile(process_tags, cover_fname,
not ignore_bad_tags, add_maintainers,
None)
- cmd = gitutil.EmailPatches(
+ cmd = gitutil.email_patches(
series, cover_fname, args, dry_run, not ignore_bad_tags,
cc_file, in_reply_to=in_reply_to, thread=None)
series.ShowActions(args, cmd, process_tags)
text (str): Text to put into the file
"""
path = os.path.join(self.gitdir, fname)
- tools.WriteFile(path, text, binary=False)
+ tools.write_file(path, text, binary=False)
index = self.repo.index
index.add(fname)
author = pygit2.Signature('Test user', 'test@email.com')
repo.branches.local.create('base', base_target)
return repo
- def testBranch(self):
+ def test_branch(self):
"""Test creating patches from a branch"""
repo = self.make_git_tree()
target = repo.lookup_reference('refs/heads/first')
os.chdir(self.gitdir)
# Check that it can detect the current branch
- self.assertEqual(2, gitutil.CountCommitsToBranch(None))
+ self.assertEqual(2, gitutil.count_commits_to_branch(None))
col = terminal.Color()
with capture_sys_output() as _:
_, cover_fname, patch_files = control.prepare_patches(
self.assertEqual(2, len(patch_files))
# Check that it can detect a different branch
- self.assertEqual(3, gitutil.CountCommitsToBranch('second'))
+ self.assertEqual(3, gitutil.count_commits_to_branch('second'))
with capture_sys_output() as _:
_, cover_fname, patch_files = control.prepare_patches(
col, branch='second', count=-1, start=0, end=0,
finally:
os.chdir(orig_dir)
- def testTags(self):
+ def test_tags(self):
"""Test collection of tags in a patchstream"""
text = '''This is a patch
'Reviewed-by': {self.joe, self.mary},
'Tested-by': {self.leb}})
- def testInvalidTag(self):
+ def test_invalid_tag(self):
"""Test invalid tag in a patchstream"""
text = '''This is a patch
self.assertEqual("Line 3: Invalid tag = 'Serie-version: 2'",
str(exc.exception))
- def testMissingEnd(self):
+ def test_missing_end(self):
"""Test a missing END tag"""
text = '''This is a patch
self.assertEqual(["Missing 'END' in section 'cover'"],
pstrm.commit.warn)
- def testMissingBlankLine(self):
+ def test_missing_blank_line(self):
"""Test a missing blank line after a tag"""
text = '''This is a patch
self.assertEqual(["Missing 'blank line' in section 'Series-changes'"],
pstrm.commit.warn)
- def testInvalidCommitTag(self):
+ def test_invalid_commit_tag(self):
"""Test an invalid Commit-xxx tag"""
text = '''This is a patch
pstrm = PatchStream.process_text(text)
self.assertEqual(["Line 3: Ignoring Commit-fred"], pstrm.commit.warn)
- def testSelfTest(self):
+ def test_self_test(self):
"""Test a tested by tag by this user"""
test_line = 'Tested-by: %s@napier.com' % os.getenv('USER')
text = '''This is a patch
pstrm = PatchStream.process_text(text)
self.assertEqual(["Ignoring '%s'" % test_line], pstrm.commit.warn)
- def testSpaceBeforeTab(self):
+ def test_space_before_tab(self):
"""Test a space before a tab"""
text = '''This is a patch
pstrm = PatchStream.process_text(text)
self.assertEqual(["Line 3/0 has space before tab"], pstrm.commit.warn)
- def testLinesAfterTest(self):
+ def test_lines_after_test(self):
"""Test detecting lines after TEST= line"""
text = '''This is a patch
pstrm = PatchStream.process_text(text)
self.assertEqual(["Found 2 lines after TEST="], pstrm.commit.warn)
- def testBlankLineAtEnd(self):
+ def test_blank_line_at_end(self):
"""Test detecting a blank line at the end of a file"""
text = '''This is a patch
["Found possible blank line(s) at end of file 'lib/fdtdec.c'"],
pstrm.commit.warn)
- def testNoUpstream(self):
+ def test_no_upstream(self):
"""Test CountCommitsToBranch when there is no upstream"""
repo = self.make_git_tree()
target = repo.lookup_reference('refs/heads/base')
orig_dir = os.getcwd()
os.chdir(self.gitdir)
with self.assertRaises(ValueError) as exc:
- gitutil.CountCommitsToBranch(None)
+ gitutil.count_commits_to_branch(None)
self.assertIn(
"Failed to determine upstream: fatal: no upstream configured for branch 'base'",
str(exc.exception))
{'id': '1', 'name': 'Some patch'}]}
raise ValueError('Fake Patchwork does not understand: %s' % subpath)
- def testStatusMismatch(self):
+ def test_status_mismatch(self):
"""Test Patchwork patches not matching the series"""
series = Series()
self.assertIn('Warning: Patchwork reports 1 patches, series has 0',
err.getvalue())
- def testStatusReadPatch(self):
+ def test_status_read_patch(self):
"""Test handling a single patch in Patchwork"""
series = Series()
series.commits = [Commit('abcd')]
self.assertEqual('1', patch.id)
self.assertEqual('Some patch', patch.raw_subject)
- def testParseSubject(self):
+ def test_parse_subject(self):
"""Test parsing of the patch subject"""
patch = status.Patch('1')
self.assertEqual('RESEND', patch.prefix)
self.assertEqual(None, patch.version)
- def testCompareSeries(self):
+ def test_compare_series(self):
"""Test operation of compare_with_series()"""
commit1 = Commit('abcd')
commit1.subject = 'Subject 1'
return patch.comments
raise ValueError('Fake Patchwork does not understand: %s' % subpath)
- def testFindNewResponses(self):
+ def test_find_new_responses(self):
"""Test operation of find_new_responses()"""
commit1 = Commit('abcd')
commit1.subject = 'Subject 1'
series = Series()
series.commits = [commit1, commit2]
- terminal.SetPrintTestMode()
+ terminal.set_print_test_mode()
status.check_patchwork_status(series, '1234', None, None, False, False,
None, self._fake_patchwork2)
- lines = iter(terminal.GetPrintTestLines())
+ lines = iter(terminal.get_print_test_lines())
col = terminal.Color()
self.assertEqual(terminal.PrintLine(' 1 Subject 1', col.BLUE),
next(lines))
return patch.comments
raise ValueError('Fake Patchwork does not understand: %s' % subpath)
- def testCreateBranch(self):
+ def test_create_branch(self):
"""Test operation of create_branch()"""
repo = self.make_git_tree()
branch = 'first'
# 4 responses added from patchwork into new branch 'first2'
# <unittest.result.TestResult run=8 errors=0 failures=0>
- terminal.SetPrintTestMode()
+ terminal.set_print_test_mode()
status.check_patchwork_status(series, '1234', branch, dest_branch,
False, False, None, self._fake_patchwork3,
repo)
- lines = terminal.GetPrintTestLines()
+ lines = terminal.get_print_test_lines()
self.assertEqual(12, len(lines))
self.assertEqual(
"4 responses added from patchwork into new branch 'first2'",
self.assertEqual('Reviewed-by: %s' % self.mary, next(lines))
self.assertEqual('Tested-by: %s' % self.leb, next(lines))
- def testParseSnippets(self):
+ def test_parse_snippets(self):
"""Test parsing of review snippets"""
text = '''Hi Fred,
And another comment
-> @@ -153,8 +143,13 @@ def CheckPatch(fname, show_types=False):
+> @@ -153,8 +143,13 @@ def check_patch(fname, show_types=False):
> further down on the file
> and more code
> +Addition here
'> Code line 7', '> Code line 8', '> Code line 9',
'And another comment'],
['> File: file.c',
- '> Line: 153 / 143: def CheckPatch(fname, show_types=False):',
+ '> Line: 153 / 143: def check_patch(fname, show_types=False):',
'> and more code', '> +Addition here', '> +Another addition here',
'> codey', '> more codey', 'and another thing in same file'],
['> File: file.c', '> Line: 253 / 243',
'line2', 'line3', 'line4', 'line5', 'line6', 'line7', 'line8']],
pstrm.snippets)
- def testReviewSnippets(self):
+ def test_review_snippets(self):
"""Test showing of review snippets"""
def _to_submitter(who):
m_who = re.match('(.*) <(.*)>', who)
> + def __str__(self):
> + return self.subject
> +
-> def AddChange(self, version, info):
+> def add_change(self, version, info):
> """Add a new change line to the change list for a version.
>
A comment
series = Series()
series.commits = [commit1, commit2]
- terminal.SetPrintTestMode()
+ terminal.set_print_test_mode()
status.check_patchwork_status(series, '1234', None, None, False, True,
None, self._fake_patchwork2)
- lines = iter(terminal.GetPrintTestLines())
+ lines = iter(terminal.get_print_test_lines())
col = terminal.Color()
self.assertEqual(terminal.PrintLine(' 1 Subject 1', col.BLUE),
next(lines))
self.assertEqual(terminal.PrintLine(
' > +', col.MAGENTA), next(lines))
self.assertEqual(
- terminal.PrintLine(' > def AddChange(self, version, info):',
+ terminal.PrintLine(' > def add_change(self, version, info):',
col.MAGENTA),
next(lines))
self.assertEqual(terminal.PrintLine(
'4 new responses available in patchwork (use -d to write them to a new branch)',
None), next(lines))
- def testInsertTags(self):
+ def test_insert_tags(self):
"""Test inserting of review tags"""
msg = '''first line
second line.'''
from patman import command
-def FindGetMaintainer(try_list):
+def find_get_maintainer(try_list):
"""Look for the get_maintainer.pl script.
Args:
return None
-def GetMaintainer(dir_list, fname, verbose=False):
+def get_maintainer(dir_list, fname, verbose=False):
"""Run get_maintainer.pl on a file if we find it.
We look for get_maintainer.pl in the 'scripts' directory at the top of
Returns:
A list of email addresses to CC to.
"""
- get_maintainer = FindGetMaintainer(dir_list)
+ get_maintainer = find_get_maintainer(dir_list)
if not get_maintainer:
if verbose:
print("WARNING: Couldn't find get_maintainer.pl")
return []
- stdout = command.Output(get_maintainer, '--norolestats', fname)
+ stdout = command.output(get_maintainer, '--norolestats', fname)
lines = stdout.splitlines()
return [ x.replace('"', '') for x in lines ]
from patman import terminal
from patman import tools
-# True to use --no-decorate - we check this in Setup()
+# True to use --no-decorate - we check this in setup()
use_no_decorate = True
-def LogCmd(commit_range, git_dir=None, oneline=False, reverse=False,
+def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False,
count=None):
"""Create a command to perform a 'git log'
cmd.append('--')
return cmd
-def CountCommitsToBranch(branch):
+def count_commits_to_branch(branch):
"""Returns number of commits between HEAD and the tracking branch.
This looks back to the tracking branch and works out the number of commits
Number of patches that exist on top of the branch
"""
if branch:
- us, msg = GetUpstream('.git', branch)
+ us, msg = get_upstream('.git', branch)
rev_range = '%s..%s' % (us, branch)
else:
rev_range = '@{upstream}..'
- pipe = [LogCmd(rev_range, oneline=True)]
- result = command.RunPipe(pipe, capture=True, capture_stderr=True,
+ pipe = [log_cmd(rev_range, oneline=True)]
+ result = command.run_pipe(pipe, capture=True, capture_stderr=True,
oneline=True, raise_on_error=False)
if result.return_code:
raise ValueError('Failed to determine upstream: %s' %
patch_count = len(result.stdout.splitlines())
return patch_count
-def NameRevision(commit_hash):
+def name_revision(commit_hash):
"""Gets the revision name for a commit
Args:
Name of revision, if any, else None
"""
pipe = ['git', 'name-rev', commit_hash]
- stdout = command.RunPipe([pipe], capture=True, oneline=True).stdout
+ stdout = command.run_pipe([pipe], capture=True, oneline=True).stdout
# We expect a commit, a space, then a revision name
name = stdout.split(' ')[1].strip()
return name
-def GuessUpstream(git_dir, branch):
+def guess_upstream(git_dir, branch):
"""Tries to guess the upstream for a branch
This lists out top commits on a branch and tries to find a suitable
Name of upstream branch (e.g. 'upstream/master') or None if none
Warning/error message, or None if none
"""
- pipe = [LogCmd(branch, git_dir=git_dir, oneline=True, count=100)]
- result = command.RunPipe(pipe, capture=True, capture_stderr=True,
+ pipe = [log_cmd(branch, git_dir=git_dir, oneline=True, count=100)]
+ result = command.run_pipe(pipe, capture=True, capture_stderr=True,
raise_on_error=False)
if result.return_code:
return None, "Branch '%s' not found" % branch
for line in result.stdout.splitlines()[1:]:
commit_hash = line.split(' ')[0]
- name = NameRevision(commit_hash)
+ name = name_revision(commit_hash)
if '~' not in name and '^' not in name:
if name.startswith('remotes/'):
name = name[8:]
return name, "Guessing upstream as '%s'" % name
return None, "Cannot find a suitable upstream for branch '%s'" % branch
-def GetUpstream(git_dir, branch):
+def get_upstream(git_dir, branch):
"""Returns the name of the upstream for a branch
Args:
Warning/error message, or None if none
"""
try:
- remote = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
+ remote = command.output_one_line('git', '--git-dir', git_dir, 'config',
'branch.%s.remote' % branch)
- merge = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
+ merge = command.output_one_line('git', '--git-dir', git_dir, 'config',
'branch.%s.merge' % branch)
except:
- upstream, msg = GuessUpstream(git_dir, branch)
+ upstream, msg = guess_upstream(git_dir, branch)
return upstream, msg
if remote == '.':
"'%s' remote='%s', merge='%s'" % (branch, remote, merge))
-def GetRangeInBranch(git_dir, branch, include_upstream=False):
+def get_range_in_branch(git_dir, branch, include_upstream=False):
"""Returns an expression for the commits in the given branch.
Args:
Expression in the form 'upstream..branch' which can be used to
access the commits. If the branch does not exist, returns None.
"""
- upstream, msg = GetUpstream(git_dir, branch)
+ upstream, msg = get_upstream(git_dir, branch)
if not upstream:
return None, msg
rstr = '%s%s..%s' % (upstream, '~' if include_upstream else '', branch)
return rstr, msg
-def CountCommitsInRange(git_dir, range_expr):
+def count_commits_in_range(git_dir, range_expr):
"""Returns the number of commits in the given range.
Args:
Number of patches that exist in the supplied range or None if none
were found
"""
- pipe = [LogCmd(range_expr, git_dir=git_dir, oneline=True)]
- result = command.RunPipe(pipe, capture=True, capture_stderr=True,
+ pipe = [log_cmd(range_expr, git_dir=git_dir, oneline=True)]
+ result = command.run_pipe(pipe, capture=True, capture_stderr=True,
raise_on_error=False)
if result.return_code:
return None, "Range '%s' not found or is invalid" % range_expr
patch_count = len(result.stdout.splitlines())
return patch_count, None
-def CountCommitsInBranch(git_dir, branch, include_upstream=False):
+def count_commits_in_branch(git_dir, branch, include_upstream=False):
"""Returns the number of commits in the given branch.
Args:
Number of patches that exist on top of the branch, or None if the
branch does not exist.
"""
- range_expr, msg = GetRangeInBranch(git_dir, branch, include_upstream)
+ range_expr, msg = get_range_in_branch(git_dir, branch, include_upstream)
if not range_expr:
return None, msg
- return CountCommitsInRange(git_dir, range_expr)
+ return count_commits_in_range(git_dir, range_expr)
-def CountCommits(commit_range):
+def count_commits(commit_range):
"""Returns the number of commits in the given range.
Args:
Return:
Number of patches that exist on top of the branch
"""
- pipe = [LogCmd(commit_range, oneline=True),
+ pipe = [log_cmd(commit_range, oneline=True),
['wc', '-l']]
- stdout = command.RunPipe(pipe, capture=True, oneline=True).stdout
+ stdout = command.run_pipe(pipe, capture=True, oneline=True).stdout
patch_count = int(stdout)
return patch_count
-def Checkout(commit_hash, git_dir=None, work_tree=None, force=False):
+def checkout(commit_hash, git_dir=None, work_tree=None, force=False):
"""Checkout the selected commit for this build
Args:
if force:
pipe.append('-f')
pipe.append(commit_hash)
- result = command.RunPipe([pipe], capture=True, raise_on_error=False,
+ result = command.run_pipe([pipe], capture=True, raise_on_error=False,
capture_stderr=True)
if result.return_code != 0:
raise OSError('git checkout (%s): %s' % (pipe, result.stderr))
-def Clone(git_dir, output_dir):
+def clone(git_dir, output_dir):
"""Checkout the selected commit for this build
Args:
commit_hash: Commit hash to check out
"""
pipe = ['git', 'clone', git_dir, '.']
- result = command.RunPipe([pipe], capture=True, cwd=output_dir,
+ result = command.run_pipe([pipe], capture=True, cwd=output_dir,
capture_stderr=True)
if result.return_code != 0:
raise OSError('git clone: %s' % result.stderr)
-def Fetch(git_dir=None, work_tree=None):
+def fetch(git_dir=None, work_tree=None):
"""Fetch from the origin repo
Args:
if work_tree:
pipe.extend(['--work-tree', work_tree])
pipe.append('fetch')
- result = command.RunPipe([pipe], capture=True, capture_stderr=True)
+ result = command.run_pipe([pipe], capture=True, capture_stderr=True)
if result.return_code != 0:
raise OSError('git fetch: %s' % result.stderr)
-def CheckWorktreeIsAvailable(git_dir):
+def check_worktree_is_available(git_dir):
"""Check if git-worktree functionality is available
Args:
True if git-worktree commands will work, False otherwise.
"""
pipe = ['git', '--git-dir', git_dir, 'worktree', 'list']
- result = command.RunPipe([pipe], capture=True, capture_stderr=True,
+ result = command.run_pipe([pipe], capture=True, capture_stderr=True,
raise_on_error=False)
return result.return_code == 0
-def AddWorktree(git_dir, output_dir, commit_hash=None):
+def add_worktree(git_dir, output_dir, commit_hash=None):
"""Create and checkout a new git worktree for this build
Args:
pipe = ['git', '--git-dir', git_dir, 'worktree', 'add', '.', '--detach']
if commit_hash:
pipe.append(commit_hash)
- result = command.RunPipe([pipe], capture=True, cwd=output_dir,
+ result = command.run_pipe([pipe], capture=True, cwd=output_dir,
capture_stderr=True)
if result.return_code != 0:
raise OSError('git worktree add: %s' % result.stderr)
-def PruneWorktrees(git_dir):
+def prune_worktrees(git_dir):
"""Remove administrative files for deleted worktrees
Args:
git_dir: The repository whose deleted worktrees should be pruned
"""
pipe = ['git', '--git-dir', git_dir, 'worktree', 'prune']
- result = command.RunPipe([pipe], capture=True, capture_stderr=True)
+ result = command.run_pipe([pipe], capture=True, capture_stderr=True)
if result.return_code != 0:
raise OSError('git worktree prune: %s' % result.stderr)
-def CreatePatches(branch, start, count, ignore_binary, series, signoff = True):
+def create_patches(branch, start, count, ignore_binary, series, signoff = True):
"""Create a series of patches from the top of the current branch.
The patch files are written to the current directory using
brname = branch or 'HEAD'
cmd += ['%s~%d..%s~%d' % (brname, start + count, brname, start)]
- stdout = command.RunList(cmd)
+ stdout = command.run_list(cmd)
files = stdout.splitlines()
# We have an extra file if there is a cover letter
else:
return None, files
-def BuildEmailList(in_list, tag=None, alias=None, warn_on_error=True):
+def build_email_list(in_list, tag=None, alias=None, warn_on_error=True):
"""Build a list of email addresses based on an input list.
Takes a list of email addresses and aliases, and turns this into a list
>>> alias['mary'] = ['Mary Poppins <m.poppins@cloud.net>']
>>> alias['boys'] = ['fred', ' john']
>>> alias['all'] = ['fred ', 'john', ' mary ']
- >>> BuildEmailList(['john', 'mary'], None, alias)
+ >>> build_email_list(['john', 'mary'], None, alias)
['j.bloggs@napier.co.nz', 'Mary Poppins <m.poppins@cloud.net>']
- >>> BuildEmailList(['john', 'mary'], '--to', alias)
+ >>> build_email_list(['john', 'mary'], '--to', alias)
['--to "j.bloggs@napier.co.nz"', \
'--to "Mary Poppins <m.poppins@cloud.net>"']
- >>> BuildEmailList(['john', 'mary'], 'Cc', alias)
+ >>> build_email_list(['john', 'mary'], 'Cc', alias)
['Cc j.bloggs@napier.co.nz', 'Cc Mary Poppins <m.poppins@cloud.net>']
"""
quote = '"' if tag and tag[0] == '-' else ''
raw = []
for item in in_list:
- raw += LookupEmail(item, alias, warn_on_error=warn_on_error)
+ raw += lookup_email(item, alias, warn_on_error=warn_on_error)
result = []
for item in raw:
if not item in result:
return ['%s %s%s%s' % (tag, quote, email, quote) for email in result]
return result
-def CheckSuppressCCConfig():
+def check_suppress_cc_config():
"""Check if sendemail.suppresscc is configured correctly.
Returns:
True if the option is configured correctly, False otherwise.
"""
- suppresscc = command.OutputOneLine('git', 'config', 'sendemail.suppresscc',
+ suppresscc = command.output_one_line('git', 'config', 'sendemail.suppresscc',
raise_on_error=False)
# Other settings should be fine.
if suppresscc == 'all' or suppresscc == 'cccmd':
col = terminal.Color()
- print((col.Color(col.RED, "error") +
+ print((col.build(col.RED, "error") +
": git config sendemail.suppresscc set to %s\n" % (suppresscc)) +
" patman needs --cc-cmd to be run to set the cc list.\n" +
" Please run:\n" +
return True
-def EmailPatches(series, cover_fname, args, dry_run, warn_on_error, cc_fname,
+def email_patches(series, cover_fname, args, dry_run, warn_on_error, cc_fname,
self_only=False, alias=None, in_reply_to=None, thread=False,
smtp_server=None):
"""Email a patch series.
>>> series = {}
>>> series['to'] = ['fred']
>>> series['cc'] = ['mary']
- >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \
+ >>> email_patches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \
False, alias)
'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \
"m.poppins@cloud.net" --cc-cmd "./patman send --cc-cmd cc-fname" cover p1 p2'
- >>> EmailPatches(series, None, ['p1'], True, True, 'cc-fname', False, \
+ >>> email_patches(series, None, ['p1'], True, True, 'cc-fname', False, \
alias)
'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \
"m.poppins@cloud.net" --cc-cmd "./patman send --cc-cmd cc-fname" p1'
>>> series['cc'] = ['all']
- >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \
+ >>> email_patches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \
True, alias)
'git send-email --annotate --to "this-is-me@me.com" --cc-cmd "./patman \
send --cc-cmd cc-fname" cover p1 p2'
- >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \
+ >>> email_patches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \
False, alias)
'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \
"f.bloggs@napier.co.nz" --cc "j.bloggs@napier.co.nz" --cc \
# Restore argv[0] since we clobbered it.
>>> sys.argv[0] = _old_argv0
"""
- to = BuildEmailList(series.get('to'), '--to', alias, warn_on_error)
+ to = build_email_list(series.get('to'), '--to', alias, warn_on_error)
if not to:
- git_config_to = command.Output('git', 'config', 'sendemail.to',
+ git_config_to = command.output('git', 'config', 'sendemail.to',
raise_on_error=False)
if not git_config_to:
print("No recipient.\n"
"Or do something like this\n"
"git config sendemail.to u-boot@lists.denx.de")
return
- cc = BuildEmailList(list(set(series.get('cc')) - set(series.get('to'))),
+ cc = build_email_list(list(set(series.get('cc')) - set(series.get('to'))),
'--cc', alias, warn_on_error)
if self_only:
- to = BuildEmailList([os.getenv('USER')], '--to', alias, warn_on_error)
+ to = build_email_list([os.getenv('USER')], '--to', alias, warn_on_error)
cc = []
cmd = ['git', 'send-email', '--annotate']
if smtp_server:
return cmdstr
-def LookupEmail(lookup_name, alias=None, warn_on_error=True, level=0):
+def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0):
"""If an email address is an alias, look it up and return the full name
TODO: Why not just use git's own alias feature?
>>> alias['all'] = ['fred ', 'john', ' mary ']
>>> alias['loop'] = ['other', 'john', ' mary ']
>>> alias['other'] = ['loop', 'john', ' mary ']
- >>> LookupEmail('mary', alias)
+ >>> lookup_email('mary', alias)
['m.poppins@cloud.net']
- >>> LookupEmail('arthur.wellesley@howe.ro.uk', alias)
+ >>> lookup_email('arthur.wellesley@howe.ro.uk', alias)
['arthur.wellesley@howe.ro.uk']
- >>> LookupEmail('boys', alias)
+ >>> lookup_email('boys', alias)
['f.bloggs@napier.co.nz', 'j.bloggs@napier.co.nz']
- >>> LookupEmail('all', alias)
+ >>> lookup_email('all', alias)
['f.bloggs@napier.co.nz', 'j.bloggs@napier.co.nz', 'm.poppins@cloud.net']
- >>> LookupEmail('odd', alias)
+ >>> lookup_email('odd', alias)
Alias 'odd' not found
[]
- >>> LookupEmail('loop', alias)
+ >>> lookup_email('loop', alias)
Traceback (most recent call last):
...
OSError: Recursive email alias at 'other'
- >>> LookupEmail('odd', alias, warn_on_error=False)
+ >>> lookup_email('odd', alias, warn_on_error=False)
[]
>>> # In this case the loop part will effectively be ignored.
- >>> LookupEmail('loop', alias, warn_on_error=False)
+ >>> lookup_email('loop', alias, warn_on_error=False)
Recursive email alias at 'other'
Recursive email alias at 'john'
Recursive email alias at 'mary'
if warn_on_error:
raise OSError(msg)
else:
- print(col.Color(col.RED, msg))
+ print(col.build(col.RED, msg))
return out_list
if lookup_name:
if not lookup_name in alias:
msg = "Alias '%s' not found" % lookup_name
if warn_on_error:
- print(col.Color(col.RED, msg))
+ print(col.build(col.RED, msg))
return out_list
for item in alias[lookup_name]:
- todo = LookupEmail(item, alias, warn_on_error, level + 1)
+ todo = lookup_email(item, alias, warn_on_error, level + 1)
for new_item in todo:
if not new_item in out_list:
out_list.append(new_item)
return out_list
-def GetTopLevel():
+def get_top_level():
"""Return name of top-level directory for this git repo.
Returns:
This test makes sure that we are running tests in the right subdir
>>> os.path.realpath(os.path.dirname(__file__)) == \
- os.path.join(GetTopLevel(), 'tools', 'patman')
+ os.path.join(get_top_level(), 'tools', 'patman')
True
"""
- return command.OutputOneLine('git', 'rev-parse', '--show-toplevel')
+ return command.output_one_line('git', 'rev-parse', '--show-toplevel')
-def GetAliasFile():
+def get_alias_file():
"""Gets the name of the git alias file.
Returns:
Filename of git alias file, or None if none
"""
- fname = command.OutputOneLine('git', 'config', 'sendemail.aliasesfile',
+ fname = command.output_one_line('git', 'config', 'sendemail.aliasesfile',
raise_on_error=False)
if not fname:
return None
if os.path.isabs(fname):
return fname
- return os.path.join(GetTopLevel(), fname)
+ return os.path.join(get_top_level(), fname)
-def GetDefaultUserName():
+def get_default_user_name():
"""Gets the user.name from .gitconfig file.
Returns:
User name found in .gitconfig file, or None if none
"""
- uname = command.OutputOneLine('git', 'config', '--global', 'user.name')
+ uname = command.output_one_line('git', 'config', '--global', 'user.name')
return uname
-def GetDefaultUserEmail():
+def get_default_user_email():
"""Gets the user.email from the global .gitconfig file.
Returns:
User's email found in .gitconfig file, or None if none
"""
- uemail = command.OutputOneLine('git', 'config', '--global', 'user.email')
+ uemail = command.output_one_line('git', 'config', '--global', 'user.email')
return uemail
-def GetDefaultSubjectPrefix():
+def get_default_subject_prefix():
"""Gets the format.subjectprefix from local .git/config file.
Returns:
Subject prefix found in local .git/config file, or None if none
"""
- sub_prefix = command.OutputOneLine('git', 'config', 'format.subjectprefix',
+ sub_prefix = command.output_one_line('git', 'config', 'format.subjectprefix',
raise_on_error=False)
return sub_prefix
-def Setup():
+def setup():
"""Set up git utils, by reading the alias files."""
# Check for a git alias file also
global use_no_decorate
- alias_fname = GetAliasFile()
+ alias_fname = get_alias_file()
if alias_fname:
settings.ReadGitAliases(alias_fname)
- cmd = LogCmd(None, count=0)
- use_no_decorate = (command.RunPipe([cmd], raise_on_error=False)
+ cmd = log_cmd(None, count=0)
+ use_no_decorate = (command.run_pipe([cmd], raise_on_error=False)
.return_code == 0)
-def GetHead():
+def get_head():
"""Get the hash of the current HEAD
Returns:
Hash of HEAD
"""
- return command.OutputOneLine('git', 'show', '-s', '--pretty=format:%H')
+ return command.output_one_line('git', 'show', '-s', '--pretty=format:%H')
if __name__ == "__main__":
import doctest
help='Commits to skip at end of patch list')
parser.add_argument('-D', '--debug', action='store_true',
help='Enabling debugging (provides a full traceback on error)')
-parser.add_argument('-p', '--project', default=project.DetectProject(),
+parser.add_argument('-p', '--project', default=project.detect_project(),
help="Project name; affects default option values and "
"aliases [default: %(default)s]")
parser.add_argument('-P', '--patchwork-url',
import doctest
from patman import func_test
- sys.argv = [sys.argv[0]]
result = unittest.TestResult()
- suite = unittest.TestSuite()
- loader = unittest.TestLoader()
- for module in (test_checkpatch.TestPatch, func_test.TestFunctional):
- if args.testname:
- try:
- suite.addTests(loader.loadTestsFromName(args.testname, module))
- except AttributeError:
- continue
- else:
- suite.addTests(loader.loadTestsFromTestCase(module))
- suite.run(result)
-
- for module in ['gitutil', 'settings', 'terminal']:
- suite = doctest.DocTestSuite(module)
- suite.run(result)
-
- sys.exit(test_util.ReportResult('patman', args.testname, result))
+ test_util.run_test_suites(
+ result, False, False, False, None, None, None,
+ [test_checkpatch.TestPatch, func_test.TestFunctional,
+ 'gitutil', 'settings', 'terminal'])
+
+ sys.exit(test_util.report_result('patman', args.testname, result))
# Process commits, produce patches files, check them, email them
elif args.cmd == 'send':
fd.close()
elif args.full_help:
- tools.PrintFullHelp(
+ tools.print_full_help(
os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README')
)
args.dest_branch, args.force,
args.show_comments, args.patchwork_url)
except Exception as e:
- terminal.Print('patman: %s: %s' % (type(e).__name__, e),
+ terminal.tprint('patman: %s: %s' % (type(e).__name__, e),
colour=terminal.Color.RED)
if args.debug:
print()
who (str): Person who gave that rtag, e.g.
'Fred Bloggs <fred@bloggs.org>'
"""
- self.commit.AddRtag(rtag_type, who)
+ self.commit.add_rtag(rtag_type, who)
def _close_commit(self):
"""Save the current commit into our commit list, and reset our state"""
elif self.in_change == 'Cover':
self.series.AddChange(self.change_version, None, change)
elif self.in_change == 'Commit':
- self.commit.AddChange(self.change_version, change)
+ self.commit.add_change(self.change_version, change)
self.change_lines = []
def _finalise_snippet(self):
who.find(os.getenv('USER') + '@') != -1):
self._add_warn("Ignoring '%s'" % line)
elif rtag_type == 'Patch-cc':
- self.commit.AddCc(who.split(','))
+ self.commit.add_cc(who.split(','))
else:
out = [line]
# Suppress duplicate signoffs
elif signoff_match:
if (self.is_log or not self.commit or
- self.commit.CheckDuplicateSignoff(signoff_match.group(1))):
+ self.commit.check_duplicate_signoff(signoff_match.group(1))):
out = [line]
# Well that means this is an ordinary line
Returns
str: String containing the contents of the git log
"""
- params = gitutil.LogCmd(commit_range, reverse=True, count=count,
+ params = gitutil.log_cmd(commit_range, reverse=True, count=count,
git_dir=git_dir)
- return command.RunPipe([params], capture=True).stdout
+ return command.run_pipe([params], capture=True).stdout
def get_metadata_for_list(commit_range, git_dir=None, count=None,
series=None, allow_overwrite=False):
from patman import gitutil
-def DetectProject():
+def detect_project():
"""Autodetect the name of the current project.
This looks for signature files/directories that are unlikely to exist except
The name of the project, like "linux" or "u-boot". Returns "unknown"
if we can't detect the project.
"""
- top_level = gitutil.GetTopLevel()
+ top_level = gitutil.get_top_level()
if os.path.exists(os.path.join(top_level, "include", "u-boot")):
return "u-boot"
Args:
commit: Commit object to add
"""
- commit.CheckTags()
+ commit.check_tags()
self.commits.append(commit)
def ShowActions(self, args, cmd, process_tags):
cmd: The git command we would have run
process_tags: Process tags as if they were aliases
"""
- to_set = set(gitutil.BuildEmailList(self.to));
- cc_set = set(gitutil.BuildEmailList(self.cc));
+ to_set = set(gitutil.build_email_list(self.to));
+ cc_set = set(gitutil.build_email_list(self.cc));
col = terminal.Color()
print('Dry run, so not doing much. But I would do this:')
# TODO: Colour the patches according to whether they passed checks
for upto in range(len(args)):
commit = self.commits[upto]
- print(col.Color(col.GREEN, ' %s' % args[upto]))
+ print(col.build(col.GREEN, ' %s' % args[upto]))
cc_list = list(self._generated_cc[commit.patch])
for email in sorted(set(cc_list) - to_set - cc_set):
if email == None:
- email = col.
Color(col.YELLOW, "<alias '%s' not found>"
+ email = col.
build(col.YELLOW, "<alias '%s' not found>"
% tag)
if email:
print(' Cc: ', email)
print('Postfix:\t ', self.get('postfix'))
if self.cover:
print('Cover: %d lines' % len(self.cover))
- cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
+ cover_cc = gitutil.build_email_list(self.get('cover_cc', ''))
all_ccs = itertools.chain(cover_cc, *self._generated_cc.values())
for email in sorted(set(all_ccs) - to_set - cc_set):
print(' Cc: ', email)
else:
if version > 1:
str = 'Change log missing for v%d' % version
- print(col.Color(col.RED, str))
+ print(col.build(col.RED, str))
for version in changes_copy:
str = 'Change log for unknown version v%d' % version
- print(col.Color(col.RED, str))
+ print(col.build(col.RED, str))
elif self.changes:
str = 'Change log exists, but no version is set'
- print(col.Color(col.RED, str))
+ print(col.build(col.RED, str))
def MakeCcFile(self, process_tags, cover_fname, warn_on_error,
add_maintainers, limit):
for commit in self.commits:
cc = []
if process_tags:
- cc += gitutil.BuildEmailList(commit.tags,
+ cc += gitutil.build_email_list(commit.tags,
warn_on_error=warn_on_error)
- cc += gitutil.BuildEmailList(commit.cc_list,
+ cc += gitutil.build_email_list(commit.cc_list,
warn_on_error=warn_on_error)
if type(add_maintainers) == type(cc):
cc += add_maintainers
elif add_maintainers:
- dir_list = [os.path.join(gitutil.GetTopLevel(), 'scripts')]
- cc += get_maintainer.GetMaintainer(dir_list, commit.patch)
+ dir_list = [os.path.join(gitutil.get_top_level(), 'scripts')]
+ cc += get_maintainer.get_maintainer(dir_list, commit.patch)
for x in set(cc) & set(settings.bounces):
- print(col.Color(col.YELLOW, 'Skipping "%s"' % x))
+ print(col.build(col.YELLOW, 'Skipping "%s"' % x))
cc = list(set(cc) - set(settings.bounces))
if limit is not None:
cc = cc[:limit]
self._generated_cc[commit.patch] = cc
if cover_fname:
- cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
+ cover_cc = gitutil.build_email_list(self.get('cover_cc', ''))
cover_cc = list(set(cover_cc + all_ccs))
if limit is not None:
cover_cc = cover_cc[:limit]
Return:
Patch string, like 'RFC PATCH v5' or just 'PATCH'
"""
- git_prefix = gitutil.GetDefaultSubjectPrefix()
+ git_prefix = gitutil.get_default_subject_prefix()
if git_prefix:
git_prefix = '%s][' % git_prefix
else:
Returns:
None
"""
- name = gitutil.GetDefaultUserName()
+ name = gitutil.get_default_user_name()
if name == None:
name = raw_input("Enter name: ")
- email = gitutil.GetDefaultUserEmail()
+ email = gitutil.get_default_user_email()
if email == None:
email = raw_input("Enter email: ")
count = len(patch_dict)
num_commits = len(series.commits)
if count != num_commits:
- tout.Warning('Warning: Patchwork reports %d patches, series has %d' %
+ tout.warning('Warning: Patchwork reports %d patches, series has %d' %
(count, num_commits))
patches = []
patch.parse_subject(pw_patch['name'])
patches.append(patch)
if warn_count > 1:
- tout.Warning(' (total of %d warnings)' % warn_count)
+ tout.warning(' (total of %d warnings)' % warn_count)
# Sort patches by patch number
patches = sorted(patches, key=lambda x: x.seq)
for tag in sorted(rtags.keys()):
people = rtags[tag]
for who in sorted(people):
- terminal.Print(indent + '%s %s: ' % ('+' if is_new else ' ', tag),
+ terminal.tprint(indent + '%s %s: ' % ('+' if is_new else ' ', tag),
newline=False, colour=col.GREEN, bright=is_new)
- terminal.Print(who, colour=col.WHITE, bright=is_new)
+ terminal.tprint(who, colour=col.WHITE, bright=is_new)
count += 1
return count
patch_for_commit, _, warnings = compare_with_series(series, patches)
for warn in warnings:
- tout.Warning(warn)
+ tout.warning(warn)
patch_list = [patch_for_commit.get(c) for c in range(len(series.commits))]
patch = patch_for_commit.get(seq)
if not patch:
continue
- terminal.Print('%3d %s' % (patch.seq, patch.subject[:50]),
+ terminal.tprint('%3d %s' % (patch.seq, patch.subject[:50]),
colour=col.BLUE)
cmt = series.commits[seq]
base_rtags = cmt.rtags
num_to_add += show_responses(new_rtags, indent, True)
if show_comments:
for review in review_list[seq]:
- terminal.Print('Review: %s' % review.meta, colour=col.RED)
+ terminal.tprint('Review: %s' % review.meta, colour=col.RED)
for snippet in review.snippets:
for line in snippet:
quoted = line.startswith('>')
- terminal.Print(' %s' % line,
+ terminal.tprint(' %s' % line,
colour=col.MAGENTA if quoted else None)
- terminal.Print()
+ terminal.tprint()
- terminal.Print("%d new response%s available in patchwork%s" %
+ terminal.tprint("%d new response%s available in patchwork%s" %
(num_to_add, 's' if num_to_add != 1 else '',
'' if dest_branch
else ' (use -d to write them to a new branch)'))
if dest_branch:
num_added = create_branch(series, new_rtag_list, branch,
dest_branch, force, test_repo)
- terminal.Print(
+ terminal.tprint(
"%d response%s added from patchwork into new branch '%s'" %
(num_added, 's' if num_added != 1 else '', dest_branch))
(self.newline, self.colour, self.bright, self.text))
-def CalcAsciiLen(text):
+def calc_ascii_len(text):
"""Calculate the length of a string, ignoring any ANSI sequences
When displayed on a terminal, ANSI sequences don't take any space, so we
Length of text, after skipping ANSI sequences
>>> col = Color(COLOR_ALWAYS)
- >>> text = col.Color(Color.RED, 'abc')
+ >>> text = col.build(Color.RED, 'abc')
>>> len(text)
14
- >>> CalcAsciiLen(text)
+ >>> calc_ascii_len(text)
3
>>>
>>> text += 'def'
- >>> CalcAsciiLen(text)
+ >>> calc_ascii_len(text)
6
- >>> text += col.Color(Color.RED, 'abc')
- >>> CalcAsciiLen(text)
+ >>> text += col.build(Color.RED, 'abc')
+ >>> calc_ascii_len(text)
9
"""
result = ansi_escape.sub('', text)
return len(result)
-def TrimAsciiLen(text, size):
+def trim_ascii_len(text, size):
"""Trim a string containing ANSI sequences to the given ASCII length
The string is trimmed with ANSI sequences being ignored for the length
calculation.
>>> col = Color(COLOR_ALWAYS)
- >>> text = col.Color(Color.RED, 'abc')
+ >>> text = col.build(Color.RED, 'abc')
>>> len(text)
14
- >>> CalcAsciiLen(TrimAsciiLen(text, 4))
+ >>> calc_ascii_len(trim_ascii_len(text, 4))
3
- >>> CalcAsciiLen(TrimAsciiLen(text, 2))
+ >>> calc_ascii_len(trim_ascii_len(text, 2))
2
>>> text += 'def'
- >>> CalcAsciiLen(TrimAsciiLen(text, 4))
+ >>> calc_ascii_len(trim_ascii_len(text, 4))
4
- >>> text += col.Color(Color.RED, 'ghi')
- >>> CalcAsciiLen(TrimAsciiLen(text, 7))
+ >>> text += col.build(Color.RED, 'ghi')
+ >>> calc_ascii_len(trim_ascii_len(text, 7))
7
"""
- if CalcAsciiLen(text) < size:
+ if calc_ascii_len(text) < size:
return text
pos = 0
out = ''
return out
-def Print(text='', newline=True, colour=None, limit_to_line=False, bright=True):
+def tprint(text='', newline=True, colour=None, limit_to_line=False, bright=True):
"""Handle a line of output to the terminal.
In test mode this is recorded in a list. Otherwise it is output to the
else:
if colour:
col = Color()
- text = col.Color(colour, text, bright=bright)
+ text = col.build(colour, text, bright=bright)
if newline:
print(text)
last_print_len = None
else:
if limit_to_line:
cols = shutil.get_terminal_size().columns
- text = TrimAsciiLen(text, cols)
+ text = trim_ascii_len(text, cols)
print(text, end='', flush=True)
- last_print_len = CalcAsciiLen(text)
+ last_print_len = calc_ascii_len(text)
-def PrintClear():
+def print_clear():
"""Clear a previously line that was printed with no newline"""
global last_print_len
print('\r%s\r' % (' '* last_print_len), end='', flush=True)
last_print_len = None
-def SetPrintTestMode(enable=True):
+def set_print_test_mode(enable=True):
"""Go into test mode, where all printing is recorded"""
global print_test_mode
print_test_mode = enable
- GetPrintTestLines()
+ get_print_test_lines()
-def GetPrintTestLines():
- """Get a list of all lines output through Print()
+def get_print_test_lines():
+ """Get a list of all lines output through tprint()
Returns:
A list of PrintLine objects
print_test_list = []
return ret
-def EchoPrintTestLines():
+def echo_print_test_lines():
"""Print out the text lines collected"""
for line in print_test_list:
if line.colour:
col = Color()
- print(col.Color(line.colour, line.text), end='')
+ print(col.build(line.colour, line.text), end='')
else:
print(line.text, end='')
if line.newline:
except:
self._enabled = False
- def Start(self, color, bright=True):
+ def start(self, color, bright=True):
"""Returns a start color code.
Args:
return base % (color + 30)
return ''
- def Stop(self):
+ def stop(self):
"""Returns a stop color code.
Returns:
return self.RESET
return ''
- def Color(self, color, text, bright=True):
+ def build(self, color, text, bright=True):
"""Returns text with conditionally added color escape sequences.
Keyword arguments:
return inname
def run_checkpatch(self):
- return checkpatch.CheckPatch(self.get_patch(), show_types=True)
+ return checkpatch.check_patch(self.get_patch(), show_types=True)
class TestPatch(unittest.TestCase):
"""Test the u_boot_line() function in checkpatch.pl"""
- def testBasic(self):
+ def test_basic(self):
"""Test basic filter operation"""
data='''
os.remove(inname)
os.remove(expname)
- def GetData(self, data_type):
+ def get_data(self, data_type):
data='''From 4924887af52713cabea78420eff03badea8f0035 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 7 Apr 2011 10:14:41 -0700
print('not implemented')
return data % (signoff, license, tab, indent, tab)
- def SetupData(self, data_type):
+ def setup_data(self, data_type):
inhandle, inname = tempfile.mkstemp()
infd = os.fdopen(inhandle, 'w')
- data = self.GetData(data_type)
+ data = self.get_data(data_type)
infd.write(data)
infd.close()
return inname
- def testGood(self):
+ def test_good(self):
"""Test checkpatch operation"""
- inf = self.SetupData('good')
- result = checkpatch.CheckPatch(inf)
+ inf = self.setup_data('good')
+ result = checkpatch.check_patch(inf)
self.assertEqual(result.ok, True)
self.assertEqual(result.problems, [])
self.assertEqual(result.errors, 0)
self.assertEqual(result.lines, 62)
os.remove(inf)
- def testNoSignoff(self):
- inf = self.SetupData('no-signoff')
- result = checkpatch.CheckPatch(inf)
+ def test_no_signoff(self):
+ inf = self.setup_data('no-signoff')
+ result = checkpatch.check_patch(inf)
self.assertEqual(result.ok, False)
self.assertEqual(len(result.problems), 1)
self.assertEqual(result.errors, 1)
self.assertEqual(result.lines, 62)
os.remove(inf)
- def testNoLicense(self):
- inf = self.SetupData('no-license')
- result = checkpatch.CheckPatch(inf)
+ def test_no_license(self):
+ inf = self.setup_data('no-license')
+ result = checkpatch.check_patch(inf)
self.assertEqual(result.ok, False)
self.assertEqual(len(result.problems), 1)
self.assertEqual(result.errors, 0)
self.assertEqual(result.lines, 62)
os.remove(inf)
- def testSpaces(self):
- inf = self.SetupData('spaces')
- result = checkpatch.CheckPatch(inf)
+ def test_spaces(self):
+ inf = self.setup_data('spaces')
+ result = checkpatch.check_patch(inf)
self.assertEqual(result.ok, False)
self.assertEqual(len(result.problems), 3)
self.assertEqual(result.errors, 0)
self.assertEqual(result.lines, 62)
os.remove(inf)
- def testIndent(self):
- inf = self.SetupData('indent')
- result = checkpatch.CheckPatch(inf)
+ def test_indent(self):
+ inf = self.setup_data('indent')
+ result = checkpatch.check_patch(inf)
self.assertEqual(result.ok, False)
self.assertEqual(len(result.problems), 1)
self.assertEqual(result.errors, 0)
self.assertEqual(result.lines, 62)
os.remove(inf)
- def checkSingleMessage(self, pm, msg, pmtype = 'warning'):
+ def check_single_message(self, pm, msg, pmtype = 'warning'):
"""Helper function to run checkpatch and check the result
Args:
self.assertEqual(len(result.problems), 1)
self.assertIn(msg, result.problems[0]['cptype'])
- def testUclass(self):
+ def test_uclass(self):
"""Test for possible new uclass"""
pm = PatchMaker()
pm.add_line('include/dm/uclass-id.h', 'UCLASS_WIBBLE,')
- self.checkSingleMessage(pm, 'NEW_UCLASS')
+ self.check_single_message(pm, 'NEW_UCLASS')
- def testLivetree(self):
+ def test_livetree(self):
"""Test for using the livetree API"""
pm = PatchMaker()
pm.add_line('common/main.c', 'fdtdec_do_something()')
- self.checkSingleMessage(pm, 'LIVETREE')
+ self.check_single_message(pm, 'LIVETREE')
- def testNewCommand(self):
+ def test_new_command(self):
"""Test for adding a new command"""
pm = PatchMaker()
pm.add_line('common/main.c', 'do_wibble(struct cmd_tbl *cmd_tbl)')
- self.checkSingleMessage(pm, 'CMD_TEST')
+ self.check_single_message(pm, 'CMD_TEST')
- def testPreferIf(self):
+ def test_prefer_if(self):
"""Test for using #ifdef"""
pm = PatchMaker()
pm.add_line('common/main.c', '#ifdef CONFIG_YELLOW')
pm.add_line('common/init.h', '#ifdef CONFIG_YELLOW')
pm.add_line('fred.dtsi', '#ifdef CONFIG_YELLOW')
- self.checkSingleMessage(pm, "PREFER_IF")
+ self.check_single_message(pm, "PREFER_IF")
- def testCommandUseDefconfig(self):
+ def test_command_use_defconfig(self):
"""Test for enabling/disabling commands using preprocesor"""
pm = PatchMaker()
pm.add_line('common/main.c', '#undef CONFIG_CMD_WHICH')
- self.checkSingleMessage(pm, 'DEFINE_CONFIG_CMD', 'error')
+ self.check_single_message(pm, 'DEFINE_CONFIG_CMD', 'error')
- def testBarredIncludeInHdr(self):
+ def test_barred_include_in_hdr(self):
"""Test for using a barred include in a header file"""
pm = PatchMaker()
#pm.add_line('include/myfile.h', '#include <common.h>')
pm.add_line('include/myfile.h', '#include <dm.h>')
- self.checkSingleMessage(pm, 'BARRED_INCLUDE_IN_HDR', 'error')
+ self.check_single_message(pm, 'BARRED_INCLUDE_IN_HDR', 'error')
- def testConfigIsEnabledConfig(self):
+ def test_config_is_enabled_config(self):
"""Test for accidental CONFIG_IS_ENABLED(CONFIG_*) calls"""
pm = PatchMaker()
pm.add_line('common/main.c', 'if (CONFIG_IS_ENABLED(CONFIG_CLK))')
- self.checkSingleMessage(pm, 'CONFIG_IS_ENABLED_CONFIG', 'error')
+ self.check_single_message(pm, 'CONFIG_IS_ENABLED_CONFIG', 'error')
def check_struct(self, auto, suffix, warning):
"""Check one of the warnings for struct naming
pm.add_line('common/main.c', '.%s = sizeof(struct(fred)),' % auto)
pm.add_line('common/main.c', '.%s = sizeof(struct(mary%s)),' %
(auto, suffix))
- self.checkSingleMessage(
+ self.check_single_message(
pm, warning, "struct 'fred' should have a %s suffix" % suffix)
- def testDmDriverAuto(self):
+ def test_dm_driver_auto(self):
"""Check for the correct suffix on 'struct driver' auto members"""
self.check_struct('priv_auto', '_priv', 'PRIV_AUTO')
self.check_struct('plat_auto', '_plat', 'PLAT_AUTO')
self.check_struct('per_child_auto', '_priv', 'CHILD_PRIV_AUTO')
self.check_struct('per_child_plat_auto', '_plat', 'CHILD_PLAT_AUTO')
- def testDmUclassAuto(self):
+ def test_dm_uclass_auto(self):
"""Check for the correct suffix on 'struct uclass' auto members"""
# Some of these are omitted since they match those from struct driver
self.check_struct('per_device_auto', '_priv', 'DEVICE_PRIV_AUTO')
"""Check one of the checks for strn(cpy|cat)"""
pm = PatchMaker()
pm.add_line('common/main.c', "strn%s(foo, bar, sizeof(foo));" % func)
- self.checkSingleMessage(pm, "STRL",
+ self.check_single_message(pm, "STRL",
"strl%s is preferred over strn%s because it always produces a nul-terminated string\n"
% (func, func))
- def testStrl(self):
+ def test_strl(self):
"""Check for uses of strn(cat|cpy)"""
self.check_strl("cat");
self.check_strl("cpy");
#
from contextlib import contextmanager
+import doctest
import glob
import multiprocessing
import os
use_concurrent = False
-def RunTestCoverage(prog, filter_fname, exclude_list, build_dir, required=None,
+def run_test_coverage(prog, filter_fname, exclude_list, build_dir, required=None,
extra_args=None):
"""Run tests and check that we get 100% coverage
'--omit "%s" %s %s %s -P1' % (prefix, ','.join(glob_list),
prog, extra_args or '', test_cmd))
os.system(cmd)
- stdout = command.Output('python3-coverage', 'report')
+ stdout = command.output('python3-coverage', 'report')
lines = stdout.splitlines()
if required:
# Convert '/path/to/name.py' just the module name 'name'
sys.stdout, sys.stderr = old_out, old_err
-def ReportResult(toolname:str, test_name: str, result: unittest.TestResult):
+def report_result(toolname:str, test_name: str, result: unittest.TestResult):
"""Report the results from a suite of tests
Args:
return 0
-def RunTestSuites(result, debug, verbosity, test_preserve_dirs, processes,
- test_name, toolpath, test_class_list):
+def run_test_suites(result, debug, verbosity, test_preserve_dirs, processes,
+ test_name, toolpath, class_and_module_list):
"""Run a series of test suites and collect the results
Args:
processes: Number of processes to use to run tests (None=same as #CPUs)
test_name: Name of test to run, or None for all
toolpath: List of paths to use for tools
- test_class_list: List of test classes to run
+ class_and_module_list: List of test classes (type class) and module
+ names (type str) to run
"""
- for module in []:
- suite = doctest.DocTestSuite(module)
- suite.run(result)
+ for module in class_and_module_list:
+ if isinstance(module, str) and (not test_name or test_name == module):
+ suite = doctest.DocTestSuite(module)
+ suite.run(result)
sys.argv = [sys.argv[0]]
if debug:
suite = unittest.TestSuite()
loader = unittest.TestLoader()
- for module in test_class_list:
+ for module in class_and_module_list:
+ if isinstance(module, str):
+ continue
# Test the test module about our arguments, if it is interested
if hasattr(module, 'setup_test_args'):
setup_test_args = getattr(module, 'setup_test_args')
# Path to the Chrome OS chroot, if we know it
chroot_path = None
-# Search paths to use for Filename(), used to find files
+# Search paths to use for filename(), used to find files
search_paths = []
tool_search_paths = []
# List of paths to use when looking for an input file
indir = []
-def PrepareOutputDir(dirname, preserve=False):
+def prepare_output_dir(dirname, preserve=False):
"""Select an output directory, ensuring it exists.
This either creates a temporary directory or checks that the one supplied
except OSError as err:
raise CmdError("Cannot make output directory '%s': '%s'" %
(outdir, err.strerror))
- tout.Debug("Using output directory '%s'" % outdir)
+ tout.debug("Using output directory '%s'" % outdir)
else:
outdir = tempfile.mkdtemp(prefix='binman.')
- tout.Debug("Using temporary directory '%s'" % outdir)
+ tout.debug("Using temporary directory '%s'" % outdir)
-def _RemoveOutputDir():
+def _remove_output_dir():
global outdir
shutil.rmtree(outdir)
- tout.Debug("Deleted temporary directory '%s'" % outdir)
+ tout.debug("Deleted temporary directory '%s'" % outdir)
outdir = None
-def FinaliseOutputDir():
+def finalise_output_dir():
global outdir, preserve_outdir
"""Tidy up: delete output directory if temporary and not preserved."""
if outdir and not preserve_outdir:
- _RemoveOutputDir()
+ _remove_output_dir()
outdir = None
-def GetOutputFilename(fname):
+def get_output_filename(fname):
"""Return a filename within the output directory.
Args:
"""
return os.path.join(outdir, fname)
-def GetOutputDir():
+def get_output_dir():
"""Return the current output directory
Returns:
"""
return outdir
-def _FinaliseForTest():
+def _finalise_for_test():
"""Remove the output directory (for use by tests)"""
global outdir
if outdir:
- _RemoveOutputDir()
+ _remove_output_dir()
outdir = None
-def SetInputDirs(dirname):
+def set_input_dirs(dirname):
"""Add a list of input directories, where input files are kept.
Args:
global indir
indir = dirname
- tout.Debug("Using input directories %s" % indir)
+ tout.debug("Using input directories %s" % indir)
-def GetInputFilename(fname, allow_missing=False):
+def get_input_filename(fname, allow_missing=False):
"""Return a filename for use as input.
Args:
raise ValueError("Filename '%s' not found in input path (%s) (cwd='%s')" %
(fname, ','.join(indir), os.getcwd()))
-def GetInputFilenameGlob(pattern):
+def get_input_filename_glob(pattern):
"""Return a list of filenames for use as input.
Args:
files += glob.glob(pathname)
return sorted(files)
-def Align(pos, align):
+def align(pos, align):
if align:
mask = align - 1
pos = (pos + mask) & ~mask
return pos
-def NotPowerOfTwo(num):
+def not_power_of_two(num):
return num and (num & (num - 1))
-def SetToolPaths(toolpaths):
+def set_tool_paths(toolpaths):
"""Set the path to search for tools
Args:
- toolpaths: List of paths to search for tools executed by Run()
+ toolpaths: List of paths to search for tools executed by run()
"""
global tool_search_paths
tool_search_paths = toolpaths
-def PathHasFile(path_spec, fname):
+def path_has_file(path_spec, fname):
"""Check if a given filename is in the PATH
Args:
return True
return False
-def GetHostCompileTool(name):
+def get_host_compile_tool(name):
"""Get the host-specific version for a compile tool
This checks the environment variables that specify which version of
return host_name, extra_args
return name, []
-def GetTargetCompileTool(name, cross_compile=None):
+def get_target_compile_tool(name, cross_compile=None):
"""Get the target-specific version for a compile tool
This first checks the environment variables that specify which
target_name = cross_compile + name
elif name == 'ld':
try:
- if Run(cross_compile + 'ld.bfd', '-v'):
+ if run(cross_compile + 'ld.bfd', '-v'):
target_name = cross_compile + 'ld.bfd'
except:
target_name = cross_compile + 'ld'
raise_on_error = kwargs.get('raise_on_error', True)
env = get_env_with_path()
if for_target:
- name, extra_args = GetTargetCompileTool(name)
+ name, extra_args = get_target_compile_tool(name)
args = tuple(extra_args) + args
elif for_host:
- name, extra_args = GetHostCompileTool(name)
+ name, extra_args = get_host_compile_tool(name)
args = tuple(extra_args) + args
name = os.path.expanduser(name) # Expand paths containing ~
all_args = (name,) + args
- result = command.RunPipe([all_args], capture=True, capture_stderr=True,
+ result = command.run_pipe([all_args], capture=True, capture_stderr=True,
env=env, raise_on_error=False, binary=binary)
if result.return_code:
if raise_on_error:
result.stderr or result.stdout))
return result
except ValueError:
- if env and not PathHasFile(env['PATH'], name):
+ if env and not path_has_file(env['PATH'], name):
msg = "Please install tool '%s'" % name
package = packages.get(name)
if package:
def tool_find(name):
"""Search the current path for a tool
- This uses both PATH and any value from SetToolPaths() to search for a tool
+ This uses both PATH and any value from set_tool_paths() to search for a tool
Args:
name (str): Name of tool to locate
if os.path.isfile(fname) and os.access(fname, os.X_OK):
return fname
-def Run(name, *args, **kwargs):
+def run(name, *args, **kwargs):
"""Run a tool with some arguments
This runs a 'tool', which is a program used by binman to process files and
if result is not None:
return result.stdout
-def Filename(fname):
+def filename(fname):
"""Resolve a file path to an absolute path.
If fname starts with ##/ and chroot is available, ##/ gets replaced with
# If not found, just return the standard, unchanged path
return fname
-def ReadFile(fname, binary=True):
+def read_file(fname, binary=True):
"""Read and return the contents of a file.
Args:
Returns:
data read from file, as a string.
"""
- with open(Filename(fname), binary and 'rb' or 'r') as fd:
+ with open(filename(fname), binary and 'rb' or 'r') as fd:
data = fd.read()
#self._out.Info("Read file '%s' size %d (%#0x)" %
#(fname, len(data), len(data)))
return data
-def WriteFile(fname, data, binary=True):
+def write_file(fname, data, binary=True):
"""Write data into a file.
Args:
"""
#self._out.Info("Write file '%s' size %d (%#0x)" %
#(fname, len(data), len(data)))
- with open(Filename(fname), binary and 'wb' or 'w') as fd:
+ with open(filename(fname), binary and 'wb' or 'w') as fd:
fd.write(data)
-def GetBytes(byte, size):
+def get_bytes(byte, size):
"""Get a string of bytes of a given size
Args:
"""
return bytes([byte]) * size
-def ToBytes(string):
+def to_bytes(string):
"""Convert a str type into a bytes type
Args:
"""
return string.encode('utf-8')
-def ToString(bval):
+def to_string(bval):
"""Convert a bytes type into a str type
Args:
"""
return bval.decode('utf-8')
-def ToHex(val):
+def to_hex(val):
"""Convert an integer value (or None) to a string
Returns:
"""
return 'None' if val is None else '%#x' % val
-def ToHexSize(val):
+def to_hex_size(val):
"""Return the size of an object in hex
Returns:
"""
return 'None' if val is None else '%#x' % len(val)
-def PrintFullHelp(fname):
+def print_full_help(fname):
"""Print the full help message for a tool using an appropriate pager.
Args:
pager = [lesspath] if lesspath else None
if not pager:
pager = ['more']
- command.Run(*pager, fname)
+ command.run(*pager, fname)
-def Download(url, tmpdir_pattern='.patman'):
+def download(url, tmpdir_pattern='.patman'):
"""Download a file to a temporary directory
Args:
def __exit__(unused1, unused2, unused3):
"""Clean up and remove any progress message."""
- ClearProgress()
+ clear_progress()
return False
-def UserIsPresent():
+def user_is_present():
"""This returns True if it is likely that a user is present.
Sometimes we want to prompt the user, but if no one is there then this
"""
return stdout_is_tty and verbose > 0
-def ClearProgress():
+def clear_progress():
"""Clear any active progress message on the terminal."""
global in_progress
if verbose > 0 and stdout_is_tty and in_progress:
_stdout.flush()
in_progress = False
-def Progress(msg, warning=False, trailer='...'):
+def progress(msg, warning=False, trailer='...'):
"""Display progress information.
Args:
msg: Message to display.
warning: True if this is a warning."""
global in_progress
- ClearProgress()
+ clear_progress()
if verbose > 0:
_progress = msg + trailer
if stdout_is_tty:
col = _color.YELLOW if warning else _color.GREEN
- _stdout.write('\r' + _color.Color(col, _progress))
+ _stdout.write('\r' + _color.build(col, _progress))
_stdout.flush()
in_progress = True
else:
_stdout.write(_progress + '\n')
-def _Output(level, msg, color=None):
+def _output(level, msg, color=None):
"""Output a message to the terminal.
Args:
error: True if this is an error message, else False.
"""
if verbose >= level:
- ClearProgress()
+ clear_progress()
if color:
- msg = _color.Color(color, msg)
+ msg = _color.build(color, msg)
if level < NOTICE:
print(msg, file=sys.stderr)
else:
print(msg)
-def DoOutput(level, msg):
+def do_output(level, msg):
"""Output a message to the terminal.
Args:
this as high as the currently selected level.
msg; Message to display.
"""
- _Output(level, msg)
+ _output(level, msg)
-def Error(msg):
+def error(msg):
"""Display an error message
Args:
msg; Message to display.
"""
- _Output(ERROR, msg, _color.RED)
+ _output(ERROR, msg, _color.RED)
-def Warning(msg):
+def warning(msg):
"""Display a warning message
Args:
msg; Message to display.
"""
- _Output(WARNING, msg, _color.YELLOW)
+ _output(WARNING, msg, _color.YELLOW)
-def Notice(msg):
+def notice(msg):
"""Display an important infomation message
Args:
msg; Message to display.
"""
- _Output(NOTICE, msg)
+ _output(NOTICE, msg)
-def Info(msg):
+def info(msg):
"""Display an infomation message
Args:
msg; Message to display.
"""
- _Output(INFO, msg)
+ _output(INFO, msg)
-def Detail(msg):
+def detail(msg):
"""Display a detailed message
Args:
msg; Message to display.
"""
- _Output(DETAIL, msg)
+ _output(DETAIL, msg)
-def Debug(msg):
+def debug(msg):
"""Display a debug message
Args:
msg; Message to display.
"""
- _Output(DEBUG, msg)
+ _output(DEBUG, msg)
-def UserOutput(msg):
+def user_output(msg):
"""Display a message regardless of the current output level.
This is used when the output was specifically requested by the user.
Args:
msg; Message to display.
"""
- _Output(0, msg)
+ _output(0, msg)
-def Init(_verbose=WARNING, stdout=sys.stdout):
+def init(_verbose=WARNING, stdout=sys.stdout):
"""Initialize a new output object.
Args:
stdout_is_tty = hasattr(sys.stdout, 'isatty') and sys.stdout.isatty()
stderr_is_tty = hasattr(sys.stderr, 'isatty') and sys.stderr.isatty()
-def Uninit():
- ClearProgress()
+def uninit():
+ clear_progress()
-Init()
+init()
struct image_tool_params *params)
{
struct pbl_header *pbl_hdr = (struct pbl_header *) ptr;
+ uint32_t rcwheader;
+
+ if (params->arch == IH_ARCH_ARM)
+ rcwheader = RCW_ARM_HEADER;
+ else
+ rcwheader = RCW_PPC_HEADER;
/* Only a few checks can be done: search for magic numbers */
if (ENDIANNESS == 'l') {
if (pbl_hdr->preamble != reverse_byte(RCW_PREAMBLE))
return -FDT_ERR_BADSTRUCTURE;
- if (pbl_hdr->rcwheader != reverse_byte(RCW_HEADER))
+ if (pbl_hdr->rcwheader != reverse_byte(rcwheader))
return -FDT_ERR_BADSTRUCTURE;
} else {
if (pbl_hdr->preamble != RCW_PREAMBLE)
return -FDT_ERR_BADSTRUCTURE;
- if (pbl_hdr->rcwheader != RCW_HEADER)
+ if (pbl_hdr->rcwheader != rcwheader)
return -FDT_ERR_BADSTRUCTURE;
}
return 0;
#define RCW_BYTES 64
#define RCW_PREAMBLE 0xaa55aa55
-#define RCW_HEADER 0x010e0100
+#define RCW_ARM_HEADER 0x01ee0100
+#define RCW_PPC_HEADER 0x010e0100
struct pbl_header {
uint32_t preamble;
path: Path to search for and remove
"""
cmd = ['git', 'grep', path]
- stdout = command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
+ stdout = command.run_pipe([cmd], capture=True, raise_on_error=False).stdout
if not stdout:
return
fname = stdout.split(':')[0]
print("Fixing up '%s' to remove reference to '%s'" % (fname, path))
cmd = ['sed', '-i', '\|%s|d' % path, fname]
- stdout = command.RunPipe([cmd], capture=True).stdout
+ stdout = command.run_pipe([cmd], capture=True).stdout
cmd = ['git', 'add', fname]
- stdout = command.RunPipe([cmd], capture=True).stdout
+ stdout = command.run_pipe([cmd], capture=True).stdout
def rm_board(board):
"""Create a commit which removes a single board
# Find all MAINTAINERS and Kconfig files which mention the board
cmd = ['git', 'grep', '-l', board]
- stdout = command.RunPipe([cmd], capture=True).stdout
+ stdout = command.run_pipe([cmd], capture=True).stdout
maintain = []
kconfig = []
for line in stdout.splitlines():
# which reference Kconfig files we want to remove
for path in real:
cmd = ['find', path]
- stdout = (command.RunPipe([cmd], capture=True, raise_on_error=False).
+ stdout = (command.run_pipe([cmd], capture=True, raise_on_error=False).
stdout)
for fname in stdout.splitlines():
if fname.endswith('Kconfig'):
# Remove unwanted files
cmd = ['git', 'rm', '-r'] + real
- stdout = command.RunPipe([cmd], capture=True).stdout
+ stdout = command.run_pipe([cmd], capture=True).stdout
## Change the messages as needed
msg = '''arm: Remove %s board
# Create the commit
cmd = ['git', 'commit', '-s', '-m', msg]
- stdout = command.RunPipe([cmd], capture=True).stdout
+ stdout = command.run_pipe([cmd], capture=True).stdout
# Check if the board is mentioned anywhere else. The user will need to deal
# with this
cmd = ['git', 'grep', '-il', board]
- print(command.RunPipe([cmd], capture=True, raise_on_error=False).stdout)
+ print(command.run_pipe([cmd], capture=True, raise_on_error=False).stdout)
print(' '.join(cmd))
for board in sys.argv[1:]:
'SUSPEND_TIMEOUT' : 0xFFFFFFFF,
+ 'PM_CONFIG_OBJECT_TYPE_BASE' : 0x1,
+
'PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK' : 0x00000001,
'PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK' : 0x00000100,
'PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK' : 0x00000200,
projects / platform / kernel / u-boot.git / commitdiff