drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11  * to uboot.
  12  *
  13  * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14  */
  15
  16 #include <common.h>
  17 #include <cpu_func.h>
  18 #include <malloc.h>
  19 #include <dwc3-uboot.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/devres.h>
  22 #include <linux/bug.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/err.h>
  26 #include <linux/ioport.h>
  27 #include <dm.h>
  28 #include <generic-phy.h>
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31
  32 #include "core.h"
  33 #include "gadget.h"
  34 #include "io.h"
  35
  36 #include "linux-compat.h"
  37
  38 static LIST_HEAD(dwc3_list);
  39 /* -------------------------------------------------------------------------- */
  40
  41 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  42 {
  43         u32 reg;
  44
  45         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  46         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  47         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  48         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  49 }
  50
  51 /**
  52  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  53  * @dwc: pointer to our context structure
  54  */
  55 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  56 {
  57         u32             reg;
  58
  59         /* Before Resetting PHY, put Core in Reset */
  60         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  61         reg |= DWC3_GCTL_CORESOFTRESET;
  62         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  63
  64         /* Assert USB3 PHY reset */
  65         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  66         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  67         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  68
  69         /* Assert USB2 PHY reset */
  70         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  71         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  72         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  73
  74         mdelay(100);
  75
  76         /* Clear USB3 PHY reset */
  77         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  78         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  79         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  80
  81         /* Clear USB2 PHY reset */
  82         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  83         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  84         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  85
  86         mdelay(100);
  87
  88         /* After PHYs are stable we can take Core out of reset state */
  89         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  90         reg &= ~DWC3_GCTL_CORESOFTRESET;
  91         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  92
  93         return 0;
  94 }
  95
  96 /*
  97  * dwc3_frame_length_adjustment - Adjusts frame length if required
  98  * @dwc3: Pointer to our controller context structure
  99  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 100  */
 101 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 102 {
 103         u32 reg;
 104
 105         if (dwc->revision < DWC3_REVISION_250A)
 106                 return;
 107
 108         if (fladj == 0)
 109                 return;
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 112         reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 113         reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 114         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 115 }
 116
 117 /**
 118  * dwc3_free_one_event_buffer - Frees one event buffer
 119  * @dwc: Pointer to our controller context structure
 120  * @evt: Pointer to event buffer to be freed
 121  */
 122 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 123                 struct dwc3_event_buffer *evt)
 124 {
 125         dma_free_coherent(evt->buf);
 126 }
 127
 128 /**
 129  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 130  * @dwc: Pointer to our controller context structure
 131  * @length: size of the event buffer
 132  *
 133  * Returns a pointer to the allocated event buffer structure on success
 134  * otherwise ERR_PTR(errno).
 135  */
 136 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 137                 unsigned length)
 138 {
 139         struct dwc3_event_buffer        *evt;
 140
 141         evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
 142                            GFP_KERNEL);
 143         if (!evt)
 144                 return ERR_PTR(-ENOMEM);
 145
 146         evt->dwc        = dwc;
 147         evt->length     = length;
 148         evt->buf        = dma_alloc_coherent(length,
 149                                              (unsigned long *)&evt->dma);
 150         if (!evt->buf)
 151                 return ERR_PTR(-ENOMEM);
 152
 153         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
 154
 155         return evt;
 156 }
 157
 158 /**
 159  * dwc3_free_event_buffers - frees all allocated event buffers
 160  * @dwc: Pointer to our controller context structure
 161  */
 162 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 163 {
 164         struct dwc3_event_buffer        *evt;
 165         int i;
 166
 167         for (i = 0; i < dwc->num_event_buffers; i++) {
 168                 evt = dwc->ev_buffs[i];
 169                 if (evt)
 170                         dwc3_free_one_event_buffer(dwc, evt);
 171         }
 172 }
 173
 174 /**
 175  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 176  * @dwc: pointer to our controller context structure
 177  * @length: size of event buffer
 178  *
 179  * Returns 0 on success otherwise negative errno. In the error case, dwc
 180  * may contain some buffers allocated but not all which were requested.
 181  */
 182 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 183 {
 184         int                     num;
 185         int                     i;
 186
 187         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 188         dwc->num_event_buffers = num;
 189
 190         dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
 191                                  sizeof(*dwc->ev_buffs) * num);
 192         if (!dwc->ev_buffs)
 193                 return -ENOMEM;
 194
 195         for (i = 0; i < num; i++) {
 196                 struct dwc3_event_buffer        *evt;
 197
 198                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 199                 if (IS_ERR(evt)) {
 200                         dev_err(dwc->dev, "can't allocate event buffer\n");
 201                         return PTR_ERR(evt);
 202                 }
 203                 dwc->ev_buffs[i] = evt;
 204         }
 205
 206         return 0;
 207 }
 208
 209 /**
 210  * dwc3_event_buffers_setup - setup our allocated event buffers
 211  * @dwc: pointer to our controller context structure
 212  *
 213  * Returns 0 on success otherwise negative errno.
 214  */
 215 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 216 {
 217         struct dwc3_event_buffer        *evt;
 218         int                             n;
 219
 220         for (n = 0; n < dwc->num_event_buffers; n++) {
 221                 evt = dwc->ev_buffs[n];
 222                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 223                                 evt->buf, (unsigned long long) evt->dma,
 224                                 evt->length);
 225
 226                 evt->lpos = 0;
 227
 228                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 229                                 lower_32_bits(evt->dma));
 230                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 231                                 upper_32_bits(evt->dma));
 232                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 233                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 234                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 235         }
 236
 237         return 0;
 238 }
 239
 240 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 241 {
 242         struct dwc3_event_buffer        *evt;
 243         int                             n;
 244
 245         for (n = 0; n < dwc->num_event_buffers; n++) {
 246                 evt = dwc->ev_buffs[n];
 247
 248                 evt->lpos = 0;
 249
 250                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 251                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 252                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 253                                 | DWC3_GEVNTSIZ_SIZE(0));
 254                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 255         }
 256 }
 257
 258 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 259 {
 260         if (!dwc->has_hibernation)
 261                 return 0;
 262
 263         if (!dwc->nr_scratch)
 264                 return 0;
 265
 266         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 267                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 268         if (!dwc->scratchbuf)
 269                 return -ENOMEM;
 270
 271         return 0;
 272 }
 273
 274 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 275 {
 276         dma_addr_t scratch_addr;
 277         u32 param;
 278         int ret;
 279
 280         if (!dwc->has_hibernation)
 281                 return 0;
 282
 283         if (!dwc->nr_scratch)
 284                 return 0;
 285
 286         scratch_addr = dma_map_single(dwc->scratchbuf,
 287                                       dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 288                                       DMA_BIDIRECTIONAL);
 289         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 290                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 291                 ret = -EFAULT;
 292                 goto err0;
 293         }
 294
 295         dwc->scratch_addr = scratch_addr;
 296
 297         param = lower_32_bits(scratch_addr);
 298
 299         ret = dwc3_send_gadget_generic_command(dwc,
 300                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 301         if (ret < 0)
 302                 goto err1;
 303
 304         param = upper_32_bits(scratch_addr);
 305
 306         ret = dwc3_send_gadget_generic_command(dwc,
 307                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 308         if (ret < 0)
 309                 goto err1;
 310
 311         return 0;
 312
 313 err1:
 314         dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 315                          DMA_BIDIRECTIONAL);
 316
 317 err0:
 318         return ret;
 319 }
 320
 321 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 322 {
 323         if (!dwc->has_hibernation)
 324                 return;
 325
 326         if (!dwc->nr_scratch)
 327                 return;
 328
 329         dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
 330                          DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 331         kfree(dwc->scratchbuf);
 332 }
 333
 334 static void dwc3_core_num_eps(struct dwc3 *dwc)
 335 {
 336         struct dwc3_hwparams    *parms = &dwc->hwparams;
 337
 338         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 339         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 340
 341         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 342                         dwc->num_in_eps, dwc->num_out_eps);
 343 }
 344
 345 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 346 {
 347         struct dwc3_hwparams    *parms = &dwc->hwparams;
 348
 349         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 350         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 351         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 352         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 353         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 354         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 355         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 356         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 357         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 358 }
 359
 360 static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
 361 {
 362         enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
 363         u32 reg;
 364
 365         /* Set dwc3 usb2 phy config */
 366         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 367
 368         switch (hsphy_mode) {
 369         case USBPHY_INTERFACE_MODE_UTMI:
 370                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 371                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 372                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 373                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 374                 break;
 375         case USBPHY_INTERFACE_MODE_UTMIW:
 376                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 377                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 378                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 379                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 380                 break;
 381         default:
 382                 break;
 383         }
 384
 385         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 386 }
 387
 388 /**
 389  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 390  * @dwc: Pointer to our controller context structure
 391  */
 392 static void dwc3_phy_setup(struct dwc3 *dwc)
 393 {
 394         u32 reg;
 395
 396         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 397
 398         /*
 399          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 400          * to '0' during coreConsultant configuration. So default value
 401          * will be '0' when the core is reset. Application needs to set it
 402          * to '1' after the core initialization is completed.
 403          */
 404         if (dwc->revision > DWC3_REVISION_194A)
 405                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 406
 407         if (dwc->u2ss_inp3_quirk)
 408                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 409
 410         if (dwc->req_p1p2p3_quirk)
 411                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 412
 413         if (dwc->del_p1p2p3_quirk)
 414                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 415
 416         if (dwc->del_phy_power_chg_quirk)
 417                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 418
 419         if (dwc->lfps_filter_quirk)
 420                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 421
 422         if (dwc->rx_detect_poll_quirk)
 423                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 424
 425         if (dwc->tx_de_emphasis_quirk)
 426                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 427
 428         if (dwc->dis_u3_susphy_quirk)
 429                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 430
 431         if (dwc->dis_del_phy_power_chg_quirk)
 432                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 433
 434         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 435
 436         dwc3_hsphy_mode_setup(dwc);
 437
 438         mdelay(100);
 439
 440         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 441
 442         /*
 443          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 444          * '0' during coreConsultant configuration. So default value will
 445          * be '0' when the core is reset. Application needs to set it to
 446          * '1' after the core initialization is completed.
 447          */
 448         if (dwc->revision > DWC3_REVISION_194A)
 449                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 450
 451         if (dwc->dis_u2_susphy_quirk)
 452                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 453
 454         if (dwc->dis_enblslpm_quirk)
 455                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 456
 457         if (dwc->dis_u2_freeclk_exists_quirk)
 458                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 459
 460         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 461
 462         mdelay(100);
 463 }
 464
 465 /* set global incr burst type configuration registers */
 466 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 467 {
 468         struct udevice *dev = dwc->dev;
 469         u32 cfg;
 470
 471         if (!dwc->incrx_size)
 472                 return;
 473
 474         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 475
 476         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 477         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 478         if (dwc->incrx_mode)
 479                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 480         switch (dwc->incrx_size) {
 481         case 256:
 482                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 483                 break;
 484         case 128:
 485                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 486                 break;
 487         case 64:
 488                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 489                 break;
 490         case 32:
 491                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 492                 break;
 493         case 16:
 494                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 495                 break;
 496         case 8:
 497                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 498                 break;
 499         case 4:
 500                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 501                 break;
 502         case 1:
 503                 break;
 504         default:
 505                 dev_err(dev, "Invalid property\n");
 506                 break;
 507         }
 508
 509         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 510 }
 511
 512 /**
 513  * dwc3_core_init - Low-level initialization of DWC3 Core
 514  * @dwc: Pointer to our controller context structure
 515  *
 516  * Returns 0 on success otherwise negative errno.
 517  */
 518 static int dwc3_core_init(struct dwc3 *dwc)
 519 {
 520         unsigned long           timeout;
 521         u32                     hwparams4 = dwc->hwparams.hwparams4;
 522         u32                     reg;
 523         int                     ret;
 524
 525         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 526         /* This should read as U3 followed by revision number */
 527         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 528                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 529                 ret = -ENODEV;
 530                 goto err0;
 531         }
 532         dwc->revision = reg;
 533
 534         /* Handle USB2.0-only core configuration */
 535         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 536                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 537                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 538                         dwc->maximum_speed = USB_SPEED_HIGH;
 539         }
 540
 541         /* issue device SoftReset too */
 542         timeout = 5000;
 543         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 544         while (timeout--) {
 545                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 546                 if (!(reg & DWC3_DCTL_CSFTRST))
 547                         break;
 548         };
 549
 550         if (!timeout) {
 551                 dev_err(dwc->dev, "Reset Timed Out\n");
 552                 ret = -ETIMEDOUT;
 553                 goto err0;
 554         }
 555
 556         dwc3_phy_setup(dwc);
 557
 558         ret = dwc3_core_soft_reset(dwc);
 559         if (ret)
 560                 goto err0;
 561
 562         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 563         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 564
 565         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 566         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 567                 /**
 568                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 569                  * issue which would cause xHCI compliance tests to fail.
 570                  *
 571                  * Because of that we cannot enable clock gating on such
 572                  * configurations.
 573                  *
 574                  * Refers to:
 575                  *
 576                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 577                  * SOF/ITP Mode Used
 578                  */
 579                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 580                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 581                                 (dwc->revision >= DWC3_REVISION_210A &&
 582                                 dwc->revision <= DWC3_REVISION_250A))
 583                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 584                 else
 585                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 586                 break;
 587         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 588                 /* enable hibernation here */
 589                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 590
 591                 /*
 592                  * REVISIT Enabling this bit so that host-mode hibernation
 593                  * will work. Device-mode hibernation is not yet implemented.
 594                  */
 595                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 596                 break;
 597         default:
 598                 dev_dbg(dwc->dev, "No power optimization available\n");
 599         }
 600
 601         /* check if current dwc3 is on simulation board */
 602         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 603                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 604                 dwc->is_fpga = true;
 605         }
 606
 607         if(dwc->disable_scramble_quirk && !dwc->is_fpga)
 608                 WARN(true,
 609                      "disable_scramble cannot be used on non-FPGA builds\n");
 610
 611         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 612                 reg |= DWC3_GCTL_DISSCRAMBLE;
 613         else
 614                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 615
 616         if (dwc->u2exit_lfps_quirk)
 617                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 618
 619         /*
 620          * WORKAROUND: DWC3 revisions <1.90a have a bug
 621          * where the device can fail to connect at SuperSpeed
 622          * and falls back to high-speed mode which causes
 623          * the device to enter a Connect/Disconnect loop
 624          */
 625         if (dwc->revision < DWC3_REVISION_190A)
 626                 reg |= DWC3_GCTL_U2RSTECN;
 627
 628         dwc3_core_num_eps(dwc);
 629
 630         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 631
 632         ret = dwc3_alloc_scratch_buffers(dwc);
 633         if (ret)
 634                 goto err0;
 635
 636         ret = dwc3_setup_scratch_buffers(dwc);
 637         if (ret)
 638                 goto err1;
 639
 640         /* Adjust Frame Length */
 641         dwc3_frame_length_adjustment(dwc, dwc->fladj);
 642
 643         dwc3_set_incr_burst_type(dwc);
 644
 645         return 0;
 646
 647 err1:
 648         dwc3_free_scratch_buffers(dwc);
 649
 650 err0:
 651         return ret;
 652 }
 653
 654 static void dwc3_core_exit(struct dwc3 *dwc)
 655 {
 656         dwc3_free_scratch_buffers(dwc);
 657 }
 658
 659 static int dwc3_core_init_mode(struct dwc3 *dwc)
 660 {
 661         int ret;
 662
 663         switch (dwc->dr_mode) {
 664         case USB_DR_MODE_PERIPHERAL:
 665                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 666                 ret = dwc3_gadget_init(dwc);
 667                 if (ret) {
 668                         dev_err(dwc->dev, "failed to initialize gadget\n");
 669                         return ret;
 670                 }
 671                 break;
 672         case USB_DR_MODE_HOST:
 673                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 674                 ret = dwc3_host_init(dwc);
 675                 if (ret) {
 676                         dev_err(dwc->dev, "failed to initialize host\n");
 677                         return ret;
 678                 }
 679                 break;
 680         case USB_DR_MODE_OTG:
 681                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 682                 ret = dwc3_host_init(dwc);
 683                 if (ret) {
 684                         dev_err(dwc->dev, "failed to initialize host\n");
 685                         return ret;
 686                 }
 687
 688                 ret = dwc3_gadget_init(dwc);
 689                 if (ret) {
 690                         dev_err(dwc->dev, "failed to initialize gadget\n");
 691                         return ret;
 692                 }
 693                 break;
 694         default:
 695                 dev_err(dwc->dev,
 696                         "Unsupported mode of operation %d\n", dwc->dr_mode);
 697                 return -EINVAL;
 698         }
 699
 700         return 0;
 701 }
 702
 703 static void dwc3_gadget_run(struct dwc3 *dwc)
 704 {
 705         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
 706         mdelay(100);
 707 }
 708
 709 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 710 {
 711         switch (dwc->dr_mode) {
 712         case USB_DR_MODE_PERIPHERAL:
 713                 dwc3_gadget_exit(dwc);
 714                 break;
 715         case USB_DR_MODE_HOST:
 716                 dwc3_host_exit(dwc);
 717                 break;
 718         case USB_DR_MODE_OTG:
 719                 dwc3_host_exit(dwc);
 720                 dwc3_gadget_exit(dwc);
 721                 break;
 722         default:
 723                 /* do nothing */
 724                 break;
 725         }
 726
 727         /*
 728          * switch back to peripheral mode
 729          * This enables the phy to enter idle and then, if enabled, suspend.
 730          */
 731         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 732         dwc3_gadget_run(dwc);
 733 }
 734
 735 #define DWC3_ALIGN_MASK         (16 - 1)
 736
 737 /**
 738  * dwc3_uboot_init - dwc3 core uboot initialization code
 739  * @dwc3_dev: struct dwc3_device containing initialization data
 740  *
 741  * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
 742  * kernel driver). Pointer to dwc3_device should be passed containing
 743  * base address and other initialization data. Returns '0' on success and
 744  * a negative value on failure.
 745  *
 746  * Generally called from board_usb_init() implemented in board file.
 747  */
 748 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 749 {
 750         struct dwc3             *dwc;
 751         struct device           *dev = NULL;
 752         u8                      lpm_nyet_threshold;
 753         u8                      tx_de_emphasis;
 754         u8                      hird_threshold;
 755
 756         int                     ret;
 757
 758         void                    *mem;
 759
 760         mem = devm_kzalloc((struct udevice *)dev,
 761                            sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 762         if (!mem)
 763                 return -ENOMEM;
 764
 765         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 766         dwc->mem = mem;
 767
 768         dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
 769                                         DWC3_GLOBALS_REGS_START);
 770
 771         /* default to highest possible threshold */
 772         lpm_nyet_threshold = 0xff;
 773
 774         /* default to -3.5dB de-emphasis */
 775         tx_de_emphasis = 1;
 776
 777         /*
 778          * default to assert utmi_sleep_n and use maximum allowed HIRD
 779          * threshold value of 0b1100
 780          */
 781         hird_threshold = 12;
 782
 783         dwc->maximum_speed = dwc3_dev->maximum_speed;
 784         dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
 785         if (dwc3_dev->lpm_nyet_threshold)
 786                 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
 787         dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
 788         if (dwc3_dev->hird_threshold)
 789                 hird_threshold = dwc3_dev->hird_threshold;
 790
 791         dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
 792         dwc->dr_mode = dwc3_dev->dr_mode;
 793
 794         dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
 795         dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
 796         dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
 797         dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
 798         dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
 799         dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
 800         dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
 801         dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
 802         dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 803         dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 804         dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
 805         dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
 806         dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
 807         dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
 808
 809         dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 810         if (dwc3_dev->tx_de_emphasis)
 811                 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
 812
 813         /* default to superspeed if no maximum_speed passed */
 814         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 815                 dwc->maximum_speed = USB_SPEED_SUPER;
 816
 817         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 818         dwc->tx_de_emphasis = tx_de_emphasis;
 819
 820         dwc->hird_threshold = hird_threshold
 821                 | (dwc->is_utmi_l1_suspend << 4);
 822
 823         dwc->hsphy_mode = dwc3_dev->hsphy_mode;
 824
 825         dwc->index = dwc3_dev->index;
 826
 827         dwc3_cache_hwparams(dwc);
 828
 829         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 830         if (ret) {
 831                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 832                 return -ENOMEM;
 833         }
 834
 835         if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 836                 dwc->dr_mode = USB_DR_MODE_HOST;
 837         else if (!IS_ENABLED(CONFIG_USB_HOST))
 838                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 839
 840         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 841                 dwc->dr_mode = USB_DR_MODE_OTG;
 842
 843         ret = dwc3_core_init(dwc);
 844         if (ret) {
 845                 dev_err(dwc->dev, "failed to initialize core\n");
 846                 goto err0;
 847         }
 848
 849         ret = dwc3_event_buffers_setup(dwc);
 850         if (ret) {
 851                 dev_err(dwc->dev, "failed to setup event buffers\n");
 852                 goto err1;
 853         }
 854
 855         ret = dwc3_core_init_mode(dwc);
 856         if (ret)
 857                 goto err2;
 858
 859         list_add_tail(&dwc->list, &dwc3_list);
 860
 861         return 0;
 862
 863 err2:
 864         dwc3_event_buffers_cleanup(dwc);
 865
 866 err1:
 867         dwc3_core_exit(dwc);
 868
 869 err0:
 870         dwc3_free_event_buffers(dwc);
 871
 872         return ret;
 873 }
 874
 875 /**
 876  * dwc3_uboot_exit - dwc3 core uboot cleanup code
 877  * @index: index of this controller
 878  *
 879  * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
 880  * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
 881  * should be passed and should match with the index passed in
 882  * dwc3_device during init.
 883  *
 884  * Generally called from board file.
 885  */
 886 void dwc3_uboot_exit(int index)
 887 {
 888         struct dwc3 *dwc;
 889
 890         list_for_each_entry(dwc, &dwc3_list, list) {
 891                 if (dwc->index != index)
 892                         continue;
 893
 894                 dwc3_core_exit_mode(dwc);
 895                 dwc3_event_buffers_cleanup(dwc);
 896                 dwc3_free_event_buffers(dwc);
 897                 dwc3_core_exit(dwc);
 898                 list_del(&dwc->list);
 899                 kfree(dwc->mem);
 900                 break;
 901         }
 902 }
 903
 904 /**
 905  * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
 906  * @index: index of this controller
 907  *
 908  * Invokes dwc3 gadget interrupts.
 909  *
 910  * Generally called from board file.
 911  */
 912 void dwc3_uboot_handle_interrupt(int index)
 913 {
 914         struct dwc3 *dwc = NULL;
 915
 916         list_for_each_entry(dwc, &dwc3_list, list) {
 917                 if (dwc->index != index)
 918                         continue;
 919
 920                 dwc3_gadget_uboot_handle_interrupt(dwc);
 921                 break;
 922         }
 923 }
 924
 925 MODULE_ALIAS("platform:dwc3");
 926 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 927 MODULE_LICENSE("GPL v2");
 928 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
 929
 930 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
 931 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
 932 {
 933         int ret;
 934
 935         ret = generic_phy_get_bulk(dev, phys);
 936         if (ret)
 937                 return ret;
 938
 939         ret = generic_phy_init_bulk(phys);
 940         if (ret)
 941                 return ret;
 942
 943         ret = generic_phy_power_on_bulk(phys);
 944         if (ret)
 945                 generic_phy_exit_bulk(phys);
 946
 947         return ret;
 948 }
 949
 950 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
 951 {
 952         int ret;
 953
 954         ret = generic_phy_power_off_bulk(phys);
 955         ret |= generic_phy_exit_bulk(phys);
 956         return ret;
 957 }
 958 #endif
 959
 960 #if CONFIG_IS_ENABLED(DM_USB)
 961 void dwc3_of_parse(struct dwc3 *dwc)
 962 {
 963         const u8 *tmp;
 964         struct udevice *dev = dwc->dev;
 965         u8 lpm_nyet_threshold;
 966         u8 tx_de_emphasis;
 967         u8 hird_threshold;
 968         u32 val;
 969         int i;
 970
 971         /* default to highest possible threshold */
 972         lpm_nyet_threshold = 0xff;
 973
 974         /* default to -3.5dB de-emphasis */
 975         tx_de_emphasis = 1;
 976
 977         /*
 978          * default to assert utmi_sleep_n and use maximum allowed HIRD
 979          * threshold value of 0b1100
 980          */
 981         hird_threshold = 12;
 982
 983         dwc->hsphy_mode = usb_get_phy_mode(dev_ofnode(dev));
 984
 985         dwc->has_lpm_erratum = dev_read_bool(dev,
 986                                 "snps,has-lpm-erratum");
 987         tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
 988         if (tmp)
 989                 lpm_nyet_threshold = *tmp;
 990
 991         dwc->is_utmi_l1_suspend = dev_read_bool(dev,
 992                                 "snps,is-utmi-l1-suspend");
 993         tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
 994         if (tmp)
 995                 hird_threshold = *tmp;
 996
 997         dwc->disable_scramble_quirk = dev_read_bool(dev,
 998                                 "snps,disable_scramble_quirk");
 999         dwc->u2exit_lfps_quirk = dev_read_bool(dev,
1000                                 "snps,u2exit_lfps_quirk");
1001         dwc->u2ss_inp3_quirk = dev_read_bool(dev,
1002                                 "snps,u2ss_inp3_quirk");
1003         dwc->req_p1p2p3_quirk = dev_read_bool(dev,
1004                                 "snps,req_p1p2p3_quirk");
1005         dwc->del_p1p2p3_quirk = dev_read_bool(dev,
1006                                 "snps,del_p1p2p3_quirk");
1007         dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
1008                                 "snps,del_phy_power_chg_quirk");
1009         dwc->lfps_filter_quirk = dev_read_bool(dev,
1010                                 "snps,lfps_filter_quirk");
1011         dwc->rx_detect_poll_quirk = dev_read_bool(dev,
1012                                 "snps,rx_detect_poll_quirk");
1013         dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
1014                                 "snps,dis_u3_susphy_quirk");
1015         dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
1016                                 "snps,dis_u2_susphy_quirk");
1017         dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
1018                                 "snps,dis-del-phy-power-chg-quirk");
1019         dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
1020                                 "snps,dis-tx-ipgap-linecheck-quirk");
1021         dwc->dis_enblslpm_quirk = dev_read_bool(dev,
1022                                 "snps,dis_enblslpm_quirk");
1023         dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
1024                                 "snps,dis-u2-freeclk-exists-quirk");
1025         dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
1026                                 "snps,tx_de_emphasis_quirk");
1027         tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
1028         if (tmp)
1029                 tx_de_emphasis = *tmp;
1030
1031         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1032         dwc->tx_de_emphasis = tx_de_emphasis;
1033
1034         dwc->hird_threshold = hird_threshold
1035                 | (dwc->is_utmi_l1_suspend << 4);
1036
1037         dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj);
1038
1039         /*
1040          * Handle property "snps,incr-burst-type-adjustment".
1041          * Get the number of value from this property:
1042          * result <= 0, means this property is not supported.
1043          * result = 1, means INCRx burst mode supported.
1044          * result > 1, means undefined length burst mode supported.
1045          */
1046         dwc->incrx_mode = INCRX_BURST_MODE;
1047         dwc->incrx_size = 0;
1048         for (i = 0; i < 8; i++) {
1049                 if (dev_read_u32_index(dev, "snps,incr-burst-type-adjustment",
1050                                        i, &val))
1051                         break;
1052
1053                 dwc->incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1054                 dwc->incrx_size = max(dwc->incrx_size, val);
1055         }
1056 }
1057
1058 int dwc3_init(struct dwc3 *dwc)
1059 {
1060         int ret;
1061         u32 reg;
1062
1063         dwc3_cache_hwparams(dwc);
1064
1065         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1066         if (ret) {
1067                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1068                 return -ENOMEM;
1069         }
1070
1071         ret = dwc3_core_init(dwc);
1072         if (ret) {
1073                 dev_err(dwc->dev, "failed to initialize core\n");
1074                 goto core_fail;
1075         }
1076
1077         ret = dwc3_event_buffers_setup(dwc);
1078         if (ret) {
1079                 dev_err(dwc->dev, "failed to setup event buffers\n");
1080                 goto event_fail;
1081         }
1082
1083         if (dwc->revision >= DWC3_REVISION_250A) {
1084                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1085
1086                 /*
1087                  * Enable hardware control of sending remote wakeup
1088                  * in HS when the device is in the L1 state.
1089                  */
1090                 if (dwc->revision >= DWC3_REVISION_290A)
1091                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1092
1093                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1094                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1095
1096                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1097         }
1098
1099         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1100             dwc->dr_mode == USB_DR_MODE_OTG) {
1101                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1102
1103                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1104
1105                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1106         }
1107
1108         ret = dwc3_core_init_mode(dwc);
1109         if (ret)
1110                 goto mode_fail;
1111
1112         return 0;
1113
1114 mode_fail:
1115         dwc3_event_buffers_cleanup(dwc);
1116
1117 event_fail:
1118         dwc3_core_exit(dwc);
1119
1120 core_fail:
1121         dwc3_free_event_buffers(dwc);
1122
1123         return ret;
1124 }
1125
1126 void dwc3_remove(struct dwc3 *dwc)
1127 {
1128         dwc3_core_exit_mode(dwc);
1129         dwc3_event_buffers_cleanup(dwc);
1130         dwc3_free_event_buffers(dwc);
1131         dwc3_core_exit(dwc);
1132         kfree(dwc->mem);
1133 }
1134 #endif