VERSION = 2021
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
# Generate some files
# ---------------------------------------------------------------------------
+# Use sed to remove leading zeros from PATCHLEVEL to avoid using octal numbers
define filechk_version.h
(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
+ echo \#define U_BOOT_VERSION_NUM $(VERSION); \
+ echo \#define U_BOOT_VERSION_NUM_PATCH $$(echo $(PATCHLEVEL) | \
+ sed -e "s/^0*//"); \
echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
endef
* The bootm command automatically updates the fdt
OF_TBCLK - The timebase frequency.
- OF_STDOUT_PATH - The path to the console device
boards with QUICC Engines require OF_QE to set UCC MAC
addresses
#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <config.h>
#include <common.h>
#include <cpu_func.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <vsprintf.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
#include <elf.h>
#include <log.h>
#include <asm-generic/sections.h>
+#include <asm/global_data.h>
extern ulong __image_copy_start;
extern ulong __ivt_start;
bool "Support flea3"
select CPU_ARM1136
-config TARGET_MX35PDK
- bool "Support mx35pdk"
- select BOARD_LATE_INIT
- select CPU_ARM1136
-
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
-config TARGET_LS2080A_SIMU
- bool "Support ls2080a_simu"
- select ARCH_LS2080A
- select ARM64
- select ARMV8_MULTIENTRY
- select BOARD_LATE_INIT
- help
- Support for Freescale LS2080A_SIMU platform.
- The LS2080A Development System (QDS) is a pre silicon
- development platform that supports the QorIQ LS2080A
- Layerscape Architecture processor.
-
config TARGET_LS1088AQDS
bool "Support ls1088aqds"
select ARCH_LS1088A
source "board/cirrus/edb93xx/Kconfig"
source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
-source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
-source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/hisilicon/hikey/Kconfig"
#include <div64.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/armada100.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
/*
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <div64.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
#include <hang.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <init.h>
#include <log.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_gpt.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <div64.h>
#include <bootstage.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <net.h>
#include <vsprintf.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/cache.h>
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 state;
+ icache_enable();
+
/*
* The RCPM FSM state may not be reset after power-on.
* So, reset them.
#include <common.h>
#include <clock_legacy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/immap_ls102xa.h>
#include <common.h>
#include <fdtdec.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <div64.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <asm/arch/clk.h>
#include <command.h>
#include <asm/system.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/arch/nexell.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-stv0991/hardware.h>
#include <asm/arch-stv0991/stv0991_cgu.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
#include <linux/delay.h>
#include <init.h>
#include <net.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
-#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/armv7.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
default y
select ARM_SMCCC if OF_CONTROL
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
- !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
+ !TARGET_LS2080AQDS && \
!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
#include <hang.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <net.h>
#include <vsprintf.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <linux/errno.h>
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <image.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/mp.h>
#include <config.h>
#include <errno.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/types.h>
#include <asm/arch/soc.h>
#include <log.h>
#include <spl.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <fsl_ifc.h>
#include <i2c.h>
#include <bootstage.h>
#include <command.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <linux/bitops.h>
#include <cpu_func.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <image.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/kernel.h>
#include <asm/io.h>
return false;
}
- if (!fit_check_format(sec_firmware_img)) {
+ if (fit_check_format(sec_firmware_img, IMAGE_SIZE_INVAL)) {
printf("SEC Firmware: Bad firmware image (bad FIT header)\n");
return false;
}
kirkwood-atl-sbx81lifxcat.dtb \
kirkwood-blackarmor-nas220.dtb \
kirkwood-d2net.dtb \
- kirkwood-db-88f6281.dtb \
- kirkwood-db-88f6281-spi.dtb \
kirkwood-dns325.dtb \
kirkwood-dockstar.dtb \
kirkwood-dreamplug.dtb \
fsl-ls1012a-frdm.dtb \
fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
+ fsl-ls1028a-kontron-sl28-var1.dtb \
+ fsl-ls1028a-kontron-sl28-var2.dtb \
fsl-ls1028a-kontron-sl28-var3.dtb \
fsl-ls1028a-kontron-sl28-var4.dtb \
dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
+ r8a774b1-beacon-rzg2n-kit.dtb \
+ r8a774e1-beacon-rzg2h-kit.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
};
&prcm {
- l4_per_cm: l4_per-cm@0 {
+ per_cm: per-cm@0 {
compatible = "ti,omap4-cm";
reg = <0x0 0x400>;
#address-cells = <1>;
l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
compatible = "ti,clkctrl";
- reg = <0x4 0x10>, <0xb4 0x24>;
+ reg = <0x0 0x10>, <0xb4 0x24>;
#clock-cells = <2>;
};
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- l4_cefuse_clkctrl: clk@20 {
+ l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
+ reg = <0x0 0x24>;
#clock-cells = <2>;
};
};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x7000 0x1000>;
+
+ gpio0: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 82 8>,
+ <&am33xx_pinmux 8 52 4>,
+ <&am33xx_pinmux 12 94 4>,
+ <&am33xx_pinmux 16 71 2>,
+ <&am33xx_pinmux 18 135 1>,
+ <&am33xx_pinmux 19 108 2>,
+ <&am33xx_pinmux 21 73 1>,
+ <&am33xx_pinmux 22 8 2>,
+ <&am33xx_pinmux 26 10 2>,
+ <&am33xx_pinmux 28 74 1>,
+ <&am33xx_pinmux 29 81 1>,
+ <&am33xx_pinmux 30 28 2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <96>;
+ };
};
target-module@9000 { /* 0x44e09000, ap 16 04.0 */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4c000 0x1000>;
+
+ gpio1: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 0 8>,
+ <&am33xx_pinmux 8 90 4>,
+ <&am33xx_pinmux 12 12 16>,
+ <&am33xx_pinmux 28 30 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <98>;
+ };
};
target-module@50000 { /* 0x48050000, ap 34 2c.0 */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xac000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 34 18>,
+ <&am33xx_pinmux 18 77 4>,
+ <&am33xx_pinmux 22 56 10>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <32>;
+ };
};
target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xae000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 66 5>,
+ <&am33xx_pinmux 5 98 2>,
+ <&am33xx_pinmux 7 75 2>,
+ <&am33xx_pinmux 13 141 1>,
+ <&am33xx_pinmux 14 100 8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <62>;
+ };
};
target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
};
};
- gpio0: gpio@44e07000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio1";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x44e07000 0x1000>;
- interrupts = <96>;
- };
-
- gpio1: gpio@4804c000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio2";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4804c000 0x1000>;
- interrupts = <98>;
- };
-
- gpio2: gpio@481ac000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio3";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x481ac000 0x1000>;
- interrupts = <32>;
- };
-
- gpio3: gpio@481ae000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio4";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x481ae000 0x1000>;
- interrupts = <62>;
- };
-
i2c0: i2c@44e0b000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/clk/versaclock.h>
/ {
- aliases {
- serial0 = &scif2;
- serial1 = &hscif0;
- serial2 = &hscif1;
- serial3 = &scif0;
- serial4 = &hscif2;
- serial5 = &scif5;
- spi0 = &msiof0;
- spi1 = &msiof1;
- spi2 = &msiof2;
- spi3 = &msiof3;
- ethernet0 = &avb;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- backlight: backlight {
+ backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
power-supply = <®_lcd>;
enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>;
- pwms = <&pwm0 0 50000>;
+ pwms = <&pwm2 0 25000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
+ backlight_dpi: backlight-dpi {
+ compatible = "pwm-backlight";
+ power-supply = <®_lcd>;
+ enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>;
+ pwms = <&pwm0 0 25000>;
+ brightness-levels = <0 25 33 50 63 75 88 100>;
+ default-brightness-level = <6>;
+ };
+
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
keys {
compatible = "gpio-keys";
- key-1 {
+ key-1 { /* S19 */
gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "Switch-1";
+ linux,code = <KEY_UP>;
+ label = "Up";
wakeup-source;
debounce-interval = <20>;
};
- key-2 {
+ key-2 { /*S20 */
gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "Switch-2";
+ linux,code = <KEY_LEFT>;
+ label = "Left";
wakeup-source;
debounce-interval = <20>;
};
- key-3 {
+ key-3 { /* S21 */
gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "Switch-3";
+ linux,code = <KEY_DOWN>;
+ label = "Down";
wakeup-source;
debounce-interval = <20>;
};
- key-4 {
+ key-4 { /* S22 */
gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "Switch-4";
+ linux,code = <KEY_RIGHT>;
+ label = "Right";
wakeup-source;
debounce-interval = <20>;
};
- key-5 {
+ key-5 { /* S23 */
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_5>;
- label = "Switch-4";
+ linux,code = <KEY_ENTER>;
+ label = "Center";
wakeup-source;
debounce-interval = <20>;
};
led1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
label = "LED1";
- linux,default-trigger = "heartbeat";
};
led2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
label = "LED2";
- linux,default-trigger = "heartbeat";
};
led3 {
gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
label = "LED3";
- linux,default-trigger = "heartbeat";
+ };
+ };
+
+ lvds {
+ compatible = "panel-lvds";
+ power-supply = <®_lcd_reset>;
+ width-mm = <223>;
+ height-mm = <125>;
+ backlight = <&backlight_lvds>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ /* 800x480@60Hz */
+ clock-frequency = <30000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hsync-len = <48>;
+ hfront-porch = <40>;
+ hback-porch = <40>;
+ vfront-porch = <13>;
+ vback-porch = <29>;
+ vsync-len = <1>;
+ hsync-active = <1>;
+ vsync-active = <3>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ rgb {
+ /* Different LCD with compatible timings */
+ compatible = "rocktech,rk070er9427";
+ backlight = <&backlight_dpi>;
+ enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_lcd>;
+ port {
+ rgb_panel: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
};
};
regulator-name = "audio-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
-
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
-
gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
- regulator-always-on;
};
/* External DU dot clocks */
#clock-cells = <0>;
clock-frequency = <25000000>;
};
-};
-&audio_clk_a {
- clock-frequency = <22579200>;
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ hs_ep: endpoint {
+ remote-endpoint = <&usb3_hs_ep>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ss_ep: endpoint {
+ remote-endpoint = <&hd3ss3220_in_ep>;
+ };
+ };
+ };
+ };
};
&audio_clk_b {
status = "okay";
};
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&versaclock5 1>,
- <&x302_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2",
- "dclkin.0", "dclkin.1", "dclkin.2";
+&du_out_rgb {
+ remote-endpoint = <&rgb_panel>;
};
&ehci0 {
dr_mode = "otg";
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>, <&versaclock6_bb 4>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
};
&ehci1 {
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 4>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
};
&hdmi0 {
};
};
port@2 {
- /* HDMI sound */
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
&i2c2 {
status = "okay";
- clock-frequency = <100000>;
+ clock-frequency = <400000>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
#gpio-cells = <2>;
};
- versaclock6_bb: versaclock6_bb@6a {
+ gpio_exp4: gpio@23 {
+ compatible = "onnn,pca9654";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ versaclock6_bb: clock-controller@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
- /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
+
assigned-clocks = <&versaclock6_bb 1>,
<&versaclock6_bb 2>,
<&versaclock6_bb 3>,
<&versaclock6_bb 4>;
- assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24000000>;
+ assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
+
+ OUT1 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <1800000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT2 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <1800000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT3 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <3300000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT4 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <3300000>;
+ idt,slew-percent = <100>;
+ };
};
};
&i2c5 {
status = "okay";
- clock-frequency = <100000>;
+ clock-frequency = <400000>;
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
+ clocks = <&versaclock6_bb 3>;
DCVDD-supply = <®_audio>;
DBVDD-supply = <®_audio>;
AVDD-supply = <®_audio>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
wakeup-source;
};
+
+ hd3ss3220@47 {
+ compatible = "ti,hd3ss3220";
+ reg = <0x47>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ hd3ss3220_in_ep: endpoint {
+ remote-endpoint = <&ss_ep>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ hd3ss3220_out_ep: endpoint {
+ remote-endpoint = <&usb3_role_switch>;
+ };
+ };
+ };
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&msiof1 {
+ pinctrl-0 = <&msiof1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
};
&ohci0 {
function = "pwm0";
};
+ pwm2_pins: pwm2 {
+ groups = "pwm2_a";
+ function = "pwm2";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sound_clk_pins: sound_clk {
- groups = "audio_clk_a_a";
+ groups = "audio_clk_a_a", "audio_clk_b_a";
function = "audio_clk";
};
status = "okay";
};
+&pwm2 {
+ pinctrl-0 = <&pwm2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
status = "okay";
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
+&rwdt {
+ status = "okay";
+ timeout-sec = <60>;
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
shared-pin;
};
+&tmu0 {
+ status = "okay";
+};
+
+&tmu1 {
+ status = "okay";
+};
+
+&tmu2 {
+ status = "okay";
+};
+
+&tmu3 {
+ status = "okay";
+};
+
+&tmu4 {
+ status = "okay";
+};
+
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
pinctrl-names = "default";
status = "okay";
};
+
+&usb3_peri0 {
+ companion = <&xhci0>;
+ status = "okay";
+ usb-role-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ usb3_hs_ep: endpoint {
+ remote-endpoint = <&hs_ep>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ usb3_role_switch: endpoint {
+ remote-endpoint = <&hd3ss3220_out_ep>;
+ };
+ };
+ };
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&vin0 {
+ status = "okay";
+};
+&vin1 {
+ status = "okay";
+};
+&vin2 {
+ status = "okay";
+};
+&vin3 {
+ status = "okay";
+};
+&vin4 {
+ status = "okay";
+};
+&vin5 {
+ status = "okay";
+};
+&vin6 {
+ status = "okay";
+};
+&vin7 {
+ status = "okay";
+};
+
+&xhci0
+{
+ pinctrl-0 = <&usb30_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/versaclock.h>
/ {
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
+ reg = <0x0 0x48000000 0x0 0xc000000>;
};
- memory@600000000 {
+ memory@57000000 {
device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x80000000>;
+ reg = <0x0 0x57000000 0x0 0x29000000>;
};
osc_32k: osc_32k {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <1800>;
+ tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
- max-speed = <4000000>;
bluetooth {
compatible = "brcm,bcm43438-bt";
device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
clocks = <&osc_32k>;
clock-names = "extclk";
+ max-speed = <4000000>;
};
};
&i2c4 {
status = "okay";
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
pca9654: gpio@20 {
compatible = "onnn,pca9654";
};
eeprom@50 {
- compatible = "microchip, at24c64", "atmel,24c64";
+ compatible = "microchip,at24c64", "atmel,24c64";
pagesize = <32>;
read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x50>;
<&versaclock5 2>,
<&versaclock5 3>,
<&versaclock5 4>;
+
assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
+
+ OUT1 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <1800000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT2 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <1800000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT3 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <1800000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT4 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <3300000>;
+ idt,slew-percent = <100>;
+ };
};
};
status = "okay";
};
-&usb_extal_clk {
- clock-frequency = <50000000>;
+&usb2_clksel {
+ status = "okay";
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&versaclock5 3>, <&usb3s0_clk>;
+ clock-names = "ehci_ohci", "hs-usb-if",
+ "usb_extal", "usb_xtal";
};
&usb3s0_clk {
clock-frequency = <100000000>;
};
-
-&vspb {
- status = "okay";
-};
-
-&vspi0 {
- status = "okay";
-};
bus-width = <4>;
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
i2c1 = &i2c3;
i2c2 = &i2c4;
rtc0 = &rtc;
- ethernet0 = &enetc0;
- ethernet1 = &enetc1;
ethernet2 = &enetc2;
ethernet3 = &enetc6;
};
};
fdt-2 {
+ description = "fsl-ls1028a-kontron-sl28-var1";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ blob {
+ filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dtb";
+ };
+ };
+
+ fdt-3 {
+ description = "fsl-ls1028a-kontron-sl28-var2";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ blob {
+ filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dtb";
+ };
+ };
+
+ fdt-4 {
description = "fsl-ls1028a-kontron-sl28-var3";
type = "flat_dt";
arch = "arm";
};
};
- fdt-3 {
+ fdt-5 {
description = "fsl-ls1028a-kontron-sl28-var4";
type = "flat_dt";
arch = "arm";
};
conf-2 {
- description = "fsl-ls1028a-kontron-sl28-var3";
+ description = "fsl-ls1028a-kontron-sl28-var1";
firmware = "uboot";
fdt = "fdt-2";
};
conf-3 {
- description = "fsl-ls1028a-kontron-sl28-var4";
+ description = "fsl-ls1028a-kontron-sl28-var2";
firmware = "uboot";
fdt = "fdt-3";
};
+
+ conf-4 {
+ description = "fsl-ls1028a-kontron-sl28-var3";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-4";
+ };
+
+ conf-5 {
+ description = "fsl-ls1028a-kontron-sl28-var4";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-5";
+ };
};
};
};
firmware = "bl31";
loadables = "uboot";
};
+
+ conf-4 {
+ firmware = "bl31";
+ loadables = "uboot";
+ };
+
+ conf-5 {
+ firmware = "bl31";
+ loadables = "uboot";
+ };
};
};
};
conf-3 {
loadables = "uboot", "bl32";
};
+
+ conf-4 {
+ loadables = "uboot", "bl32";
+ };
+
+ conf-5 {
+ loadables = "uboot", "bl32";
+ };
};
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &enetc1;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * This is for the network variant 1 which has one ethernet port. It is
+ * different than the base variant, which also has one port, but here the
+ * port is connected via RGMII. This port is not TSN aware.
+ * None of the four SerDes lanes are used by the module, instead they are
+ * all led out to the carrier for customer use.
+ *
+ * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-kontron-sl28.dts"
+#include <dt-bindings/net/qca-ar803x.h>
+
+/ {
+ model = "Kontron SMARC-sAL28 (4 Lanes)";
+ compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
+};
+
+&enetc0 {
+ status = "disabled";
+ /delete-property/ phy-handle;
+};
+
+&enetc1 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+/delete-node/ &phy0;
+&mdio0 {
+ phy0: ethernet-phy@4 {
+ reg = <0x4>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+
+ qca,clk-out-frequency = <125000000>;
+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+
+ vddio-supply = <&vddh>;
+
+ vddio: vddio-regulator {
+ regulator-name = "VDDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddh: vddh-regulator {
+ regulator-name = "VDDH";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * This is for the network variant 2 which has no ethernet support in the
+ * bootloader.
+ *
+ * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-kontron-sl28.dts"
+
+/ {
+ model = "Kontron SMARC-sAL28 (TSN-on-module)";
+ compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
+};
+
+&enetc0 {
+ status = "disabled";
+ /delete-property/ phy-handle;
+};
+
+/delete-node/ &phy0;
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &enetc0;
+ };
+};
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &enetc0;
+ ethernet1 = &enetc1;
+ };
+};
};
};
+&sata {
+ status = "okay";
+};
+
&serial0 {
status = "okay";
};
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
spi0 = &fspi;
+ eth0 = &enetc0;
+ eth1 = &enetc2;
+ eth2 = &mscc_felix_port0;
+ eth3 = &mscc_felix_port1;
+ eth4 = &mscc_felix_port2;
+ eth5 = &mscc_felix_port3;
};
};
phy-handle = <&rdb_phy0>;
};
+&enetc2 {
+ status = "okay";
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ label = "swp0";
+ phy-handle = <&sw_phy0>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port1 {
+ label = "swp1";
+ phy-handle = <&sw_phy1>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port2 {
+ label = "swp2";
+ phy-handle = <&sw_phy2>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port3 {
+ label = "swp3";
+ phy-handle = <&sw_phy3>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
+
&mdio0 {
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
};
+
+ /* VSC8514 QSGMII PHY */
+ sw_phy0: phy@10 {
+ reg = <0x10>;
+ };
+
+ sw_phy1: phy@11 {
+ reg = <0x11>;
+ };
+
+ sw_phy2: phy@12 {
+ reg = <0x12>;
+ };
+
+ sw_phy3: phy@13 {
+ reg = <0x13>;
+ };
};
reg = <0x000300 0 0 0 0>;
status = "disabled";
};
+
+ mscc_felix: pci@0,5 {
+ reg = <0x000500 0 0 0 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mscc_felix_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ mscc_felix_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ mscc_felix_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ mscc_felix_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ mscc_felix_port4: port@4 {
+ reg = <4>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+
+ mscc_felix_port5: port@5 {
+ reg = <5>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ };
+ };
+ };
+
enetc6: pci@0,6 {
reg = <0x000600 0 0 0 0>;
- status = "okay";
+ status = "disabled";
phy-mode = "internal";
};
};
status = "disabled";
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
bus-width = <4>;
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
bus-width = <4>;
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
/*
* NXP ls1088a SOC common device tree source
*
- * Copyright 2017, 2020 NXP
+ * Copyright 2017, 2020-2021 NXP
*/
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1088a";
interrupt-parent = <&gic>;
bus-width = <4>;
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;
/*
* NXP ls2080a SOC common device tree source
*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
bus-width = <4>;
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
aliases {
- pcie@3500000 {
- status = "disabled";
- };
-
- pcie@3800000 {
- status = "disabled";
- };
-
- pcie@3900000 {
- status = "disabled";
- };
+ spi1 = &dspi0;
+ spi2 = &dspi1;
+ spi3 = &dspi2;
};
};
&usb1 {
status = "disabled";
};
+
+&pcie2 {
+ status = "disabled";
+};
+
+&pcie5 {
+ status = "disabled";
+};
+
+&pcie6 {
+ status = "disabled";
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash3: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash4: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash5: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&dspi2 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash6: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash7: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash8: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
/*
* Device Tree Source for AM6 SoC Family Main Domain peripherals
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
-
#include <dt-bindings/phy/phy-am654-serdes.h>
-#include <dt-bindings/phy/phy.h>
&cbass_main {
+ msmc_ram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x70000000 0x0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x70000000 0x200000>;
+
+ atf-sram@0 {
+ reg = <0x0 0x20000>;
+ };
+
+ sysfw-sram@f0000 {
+ reg = <0xf0000 0x10000>;
+ };
+
+ l3cache-sram@100000 {
+ reg = <0x100000 0x100000>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- gic_its: gic-its@18200000 {
+ gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
- secure_proxy_main: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x32c00000 0x00 0x100000>,
- <0x00 0x32400000 0x00 0x100000>,
- <0x00 0x32800000 0x00 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ serdes0: serdes@900000 {
+ compatible = "ti,phy-am654-serdes";
+ reg = <0x0 0x900000 0x0 0x2000>;
+ reg-names = "serdes";
+ #phy-cells = <2>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
+ clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
+ ti,serdes-clk = <&serdes0_clk>;
+ #clock-cells = <1>;
+ mux-controls = <&serdes_mux 0>;
+ };
+
+ serdes1: serdes@910000 {
+ compatible = "ti,phy-am654-serdes";
+ reg = <0x0 0x910000 0x0 0x2000>;
+ reg-names = "serdes";
+ #phy-cells = <2>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
+ clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
+ assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
+ ti,serdes-clk = <&serdes1_clk>;
+ #clock-cells = <1>;
+ mux-controls = <&serdes_mux 1>;
};
main_uart0: serial@2800000 {
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
};
main_uart1: serial@2810000 {
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
};
main_uart2: serial@2820000 {
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ crypto: crypto@4e00000 {
+ compatible = "ti,am654-sa2ul";
+ reg = <0x0 0x4e00000 0x0 0x1200>;
+ power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
+
+ dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
+ <&main_udmap 0x4001>;
+ dma-names = "tx", "rx1", "rx2";
+ dma-coherent;
+
+ rng: rng@4e10000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x0 0x4e10000 0x0 0x7d>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 136 1>;
+ };
};
- main_pmx0: pinmux@11c000 {
+ main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
#pinctrl-cells = <1>;
pinctrl-single,function-mask = <0xffffffff>;
};
- main_pmx1: pinmux@11c2e8 {
+ main_pmx1: pinctrl@11c2e8 {
compatible = "pinctrl-single";
reg = <0x0 0x11c2e8 0x0 0x24>;
#pinctrl-cells = <1>;
pinctrl-single,function-mask = <0xffffffff>;
};
- sdhci0: sdhci@4f80000 {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
- power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
- clock-names = "clk_ahb", "clk_xin";
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0x5>;
- ti,otap-del-sel-ddr52 = <0x5>;
- ti,otap-del-sel-hs200 = <0x5>;
- ti,otap-del-sel-hs400 = <0x0>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- };
-
main_i2c0: i2c@2000000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x2000000 0x0 0x100>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
- scm_conf: scm_conf@100000 {
+ ecap0: pwm@3100000 {
+ compatible = "ti,am654-ecap", "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x0 0x03100000 0x0 0x60>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 39 0>;
+ clock-names = "fck";
+ };
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x2100000 0x0 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 137 1>;
+ power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
+ dma-names = "tx0", "rx0";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x2110000 0x0 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 138 1>;
+ power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ assigned-clocks = <&k3_clks 137 1>;
+ assigned-clock-rates = <48000000>;
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x2120000 0x0 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 139 1>;
+ power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x2130000 0x0 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 140 1>;
+ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x2140000 0x0 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 141 1>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sdhci0: sdhci@4f80000 {
+ compatible = "ti,am654-sdhci-5.1";
+ reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0x0>;
+ ti,otap-del-sel-sdr25 = <0x0>;
+ ti,otap-del-sel-sdr50 = <0x8>;
+ ti,otap-del-sel-sdr104 = <0x5>;
+ ti,otap-del-sel-ddr50 = <0x5>;
+ ti,otap-del-sel-ddr52 = <0x5>;
+ ti,otap-del-sel-hs200 = <0x5>;
+ ti,otap-del-sel-hs400 = <0x0>;
+ ti,itap-del-sel-legacy = <0xa>;
+ ti,itap-del-sel-mmc-hs = <0x1>;
+ ti,itap-del-sel-sdr12 = <0xa>;
+ ti,itap-del-sel-sdr25 = <0x1>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
+
+ sdhci1: sdhci@4fa0000 {
+ compatible = "ti,am654-sdhci-5.1";
+ reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0x0>;
+ ti,otap-del-sel-sdr25 = <0x0>;
+ ti,otap-del-sel-sdr50 = <0x8>;
+ ti,otap-del-sel-sdr104 = <0x7>;
+ ti,otap-del-sel-ddr50 = <0x4>;
+ ti,otap-del-sel-ddr52 = <0x4>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,itap-del-sel-legacy = <0xa>;
+ ti,itap-del-sel-mmc-hs = <0x1>;
+ ti,itap-del-sel-sdr12 = <0xa>;
+ ti,itap-del-sel-sdr25 = <0x1>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
+
+ scm_conf: scm-conf@100000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x00100000 0 0x1c000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
- serdes_mux: mux-controller {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
- <0x4090 0x3>; /* SERDES1 lane select */
- };
-
pcie0_mode: pcie-mode@4060 {
compatible = "syscon";
reg = <0x00004060 0x4>;
reg = <0x00004070 0x4>;
};
- serdes0_clk: serdes_clk@4080 {
+ pcie_devid: pcie-devid@210 {
compatible = "syscon";
- reg = <0x00004080 0x4>;
+ reg = <0x00000210 0x4>;
};
- serdes1_clk: serdes_clk@4090 {
+ serdes0_clk: clock@4080 {
compatible = "syscon";
- reg = <0x00004090 0x4>;
+ reg = <0x00004080 0x4>;
};
- pcie_devid: pcie-devid@210 {
+ serdes1_clk: clock@4090 {
compatible = "syscon";
- reg = <0x00000210 0x4>;
+ reg = <0x00004090 0x4>;
};
- };
- serdes0: serdes@900000 {
- compatible = "ti,phy-am654-serdes";
- reg = <0x0 0x900000 0x0 0x2000>;
- reg-names = "serdes";
- #phy-cells = <2>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
- clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
- ti,serdes-clk = <&serdes0_clk>;
- mux-controls = <&serdes_mux 0>;
- #clock-cells = <1>;
- };
-
- serdes1: serdes@910000 {
- compatible = "ti,phy-am654-serdes";
- reg = <0x0 0x910000 0x0 0x2000>;
- reg-names = "serdes";
- #phy-cells = <2>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
- clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
- assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
- ti,serdes-clk = <&serdes1_clk>;
- mux-controls = <&serdes_mux 1>;
- #clock-cells = <1>;
- };
+ serdes_mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
+ <0x4090 0x3>; /* SERDES1 lane select */
+ };
- pcie0_rc: pcie@5500000 {
- compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
- reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
- 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&pcie_devid>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
- bus-range = <0x0 0xff>;
- status = "disabled";
- device_type = "pci";
- num-lanes = <1>;
- num-ob-windows = <16>;
- num-viewport = <16>;
- max-link-speed = <3>;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
- <0 0 0 2 &pcie0_intc 0>, /* INT B */
- <0 0 0 3 &pcie0_intc 0>, /* INT C */
- <0 0 0 4 &pcie0_intc 0>; /* INT D */
- msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
+ compatible = "syscon";
+ reg = <0x0000041e0 0x14>;
+ };
- pcie0_intc: legacy-interrupt-controller@1 {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+ ehrpwm_tbclk: clock@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
};
};
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
- ti,dis-chg-det-quirk;
};
dwc3_1: dwc3@4020000 {
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 2>;
assigned-clocks = <&k3_clks 152 2>;
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
- ti,dis-chg-det-quirk;
+ };
+
+ intr_main_gpio: interrupt-controller0 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <100>;
+ ti,interrupt-ranges = <0 392 32>;
+ };
+
+ main-navss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+ dma-ranges;
+
+ ti,sci-dev-id = <118>;
+
+ intr_main_navss: interrupt-controller1 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <4>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <182>;
+ ti,interrupt-ranges = <0 64 64>,
+ <64 448 64>;
+ };
+
+ inta_main_udmass: interrupt-controller@33d00000 {
+ compatible = "ti,sci-inta";
+ reg = <0x0 0x33d00000 0x0 0x100000>;
+ interrupt-controller;
+ interrupt-parent = <&intr_main_navss>;
+ msi-controller;
+ #interrupt-cells = <0>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <179>;
+ ti,interrupt-ranges = <0 0 256>;
+ };
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ hwspinlock: spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f80000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster1: mailbox@31f81000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f81000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster2: mailbox@31f82000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f82000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster3: mailbox@31f83000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f83000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster4: mailbox@31f84000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f84000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster5: mailbox@31f85000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f85000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster6: mailbox@31f86000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f86000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster7: mailbox@31f87000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f87000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster8: mailbox@31f88000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f88000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster9: mailbox@31f89000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f89000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster10: mailbox@31f8a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ mailbox0_cluster11: mailbox@31f8b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ };
+
+ ringacc: ringacc@3c000000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <818>;
+ ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <187>;
+ msi-parent = <&inta_main_udmass>;
+ };
+
+ main_udmap: dma-controller@31150000 {
+ compatible = "ti,am654-navss-main-udmap";
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&inta_main_udmass>;
+ #dma-cells = <1>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <188>;
+ ti,ringacc = <&ringacc>;
+
+ ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
+ <0xd>; /* TX_CHAN */
+ ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
+ <0xa>; /* RX_CHAN */
+ ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
+ };
+
+ cpts@310d0000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x0 0x310d0000 0x0 0x400>;
+ reg-names = "cpts";
+ clocks = <&main_cpts_mux>;
+ clock-names = "cpts";
+ interrupts-extended = <&intr_main_navss 391>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+
+ main_cpts_mux: refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
+ <&k3_clks 118 6>, <&k3_clks 118 3>,
+ <&k3_clks 118 8>, <&k3_clks 118 14>,
+ <&k3_clks 120 3>, <&k3_clks 121 3>;
+ assigned-clocks = <&main_cpts_mux>;
+ assigned-clock-parents = <&k3_clks 118 5>;
+ };
+ };
+ };
+
+ main_gpio0: gpio@600000 {
+ compatible = "ti,am654-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x600000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&intr_main_gpio>;
+ interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <96>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k3_clks 57 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio1: gpio@601000 {
+ compatible = "ti,am654-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x601000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&intr_main_gpio>;
+ interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <90>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k3_clks 58 0>;
+ clock-names = "gpio";
+ };
+
+ pcie0_rc: pcie@5500000 {
+ compatible = "ti,am654-pcie-rc";
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+ reg-names = "app", "dbics", "config", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
+ 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&pcie_devid>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ bus-range = <0x0 0xff>;
+ num-viewport = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ };
+
+ pcie0_ep: pcie-ep@5500000 {
+ compatible = "ti,am654-pcie-ep";
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
+ reg-names = "app", "dbics", "addr_space", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pcie1_rc: pcie@5600000 {
+ compatible = "ti,am654-pcie-rc";
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
+ reg-names = "app", "dbics", "config", "atu";
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
+ 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&pcie_devid>;
+ ti,syscon-pcie-mode = <&pcie1_mode>;
+ bus-range = <0x0 0xff>;
+ num-viewport = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ msi-map = <0x0 &gic_its 0x10000 0x10000>;
+ };
+
+ pcie1_ep: pcie-ep@5600000 {
+ compatible = "ti,am654-pcie-ep";
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
+ reg-names = "app", "dbics", "addr_space", "atu";
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
+ ti,syscon-pcie-mode = <&pcie1_mode>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ mcasp0: mcasp@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b00000 0x0 0x2000>,
+ <0x0 0x02b08000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 104 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp1: mcasp@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b10000 0x0 0x2000>,
+ <0x0 0x02b18000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 105 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp2: mcasp@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b20000 0x0 0x2000>,
+ <0x0 0x02b28000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 106 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ cal: cal@6f03000 {
+ compatible = "ti,am654-cal";
+ reg = <0x0 0x06f03000 0x0 0x400>,
+ <0x0 0x06f03800 0x0 0x40>;
+ reg-names = "cal_top",
+ "cal_rx_core0";
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ ti,camerrx-control = <&scm_conf 0x40c0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 2 0>;
+ power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_0: port@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,am65x-dss";
+ reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
+ <0x0 0x04a06000 0x0 0x1000>, /* vid */
+ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
+ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
+ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
+ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+ reg-names = "common", "vidl1", "vid",
+ "ovr1", "ovr2", "vp1", "vp2";
+
+ ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
+
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+
+ clocks = <&k3_clks 67 1>,
+ <&k3_clks 216 1>,
+ <&k3_clks 67 2>;
+ clock-names = "fck", "vp1", "vp2";
+
+ /*
+ * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
+ * DIV1. See "Figure 12-3365. DSS Integration"
+ * in AM65x TRM for details.
+ */
+ assigned-clocks = <&k3_clks 67 2>;
+ assigned-clock-parents = <&k3_clks 67 5>;
+
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+
+ dma-coherent;
+
+ dss_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3000000 0x0 0x100>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3010000 0x0 0x100>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3020000 0x0 0x100>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3030000 0x0 0x100>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3040000 0x0 0x100>;
+ power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3050000 0x0 0x100>;
+ power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
+ clock-names = "tbclk", "fck";
};
};
/*
* Device Tree Source for AM6 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
- mcu_conf: scm_conf@40f00000 {
+ mcu_conf: scm-conf@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x40f00000 0x0 0x20000>;
#address-cells = <1>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcu_ram: sram@41c00000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x41c00000 0x00 0x80000>;
+ ranges = <0x0 0x00 0x41c00000 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
mcu_i2c0: i2c@40b00000 {
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
};
- mcu_r5fss0: r5fss@41000000 {
- compatible = "ti,am654-r5fss";
- lockstep-mode = <0>;
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x40300000 0x0 0x400>;
+ interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 142 1>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x41000000 0x00 0x41000000 0x20000>,
- <0x41400000 0x00 0x41400000 0x20000>;
- power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
+ #size-cells = <0>;
+ };
- mcu_r5fss0_core0: r5f@41000000 {
- compatible = "ti,am654-r5f";
- reg = <0x41000000 0x00008000>,
- <0x41010000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <159>;
- ti,sci-proc-ids = <0x01 0xFF>;
- resets = <&k3_reset 159 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x40310000 0x0 0x400>;
+ interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 143 1>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
- mcu_r5fss0_core1: r5f@41400000 {
- compatible = "ti,am654-r5f";
- reg = <0x41400000 0x00008000>,
- <0x41410000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <245>;
- ti,sci-proc-ids = <0x02 0xFF>;
- resets = <&k3_reset 245 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x40320000 0x0 0x400>;
+ interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 144 1>;
+ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- fss: fss@47000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ tscadc0: tscadc@40200000 {
+ compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
+ reg = <0x0 0x40200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 0 2>;
+ assigned-clocks = <&k3_clks 0 2>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "adc_tsc_fck";
+ dmas = <&mcu_udmap 0x7100>,
+ <&mcu_udmap 0x7101 >;
+ dma-names = "fifo0", "fifo1";
- ospi0: spi@47040000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 248 0>;
- assigned-clocks = <&k3_clks 248 0>;
- assigned-clock-parents = <&k3_clks 248 2>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am654-adc", "ti,am3359-adc";
};
+ };
- ospi1: spi@47050000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x7 0x00000000 0x1 0x00000000>;
- interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 249 6>;
- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
+ tscadc1: tscadc@40210000 {
+ compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
+ reg = <0x0 0x40210000 0x0 0x1000>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 1 2>;
+ assigned-clocks = <&k3_clks 1 2>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "adc_tsc_fck";
+ dmas = <&mcu_udmap 0x7102>,
+ <&mcu_udmap 0x7103>;
+ dma-names = "fifo0", "fifo1";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am654-adc", "ti,am3359-adc";
};
};
- mcu_navss {
+ mcu-navss {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,dma-ring-reset-quirk;
ti,sci = <&dmsc>;
ti,sci-dev-id = <195>;
+ msi-parent = <&inta_main_udmass>;
};
mcu_udmap: dma-controller@285c0000 {
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
ti,sci = <&dmsc>;
};
};
+ fss: fss@47000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x5 0x00000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 248 0>;
+ assigned-clocks = <&k3_clks 248 0>;
+ assigned-clock-parents = <&k3_clks 248 2>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x0 0x47050000 0x0 0x100>,
+ <0x7 0x00000000 0x1 0x00000000>;
+ interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 249 6>;
+ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
mcu_cpsw: ethernet@46000000 {
compatible = "ti,am654-cpsw-nuss";
#address-cells = <2>;
};
};
- mcu_rti1: rti@40610000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x0 0x40610000 0x0 0x100>;
- clocks = <&k3_clks 135 0>;
- power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
- assigned-clocks = <&k3_clks 135 0>;
- assigned-clock-parents = <&k3_clks 135 4>;
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,am654-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,am654-r5f";
+ reg = <0x41000000 0x00008000>,
+ <0x41010000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <159>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 159 1>;
+ firmware-name = "am65x-mcu-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,am654-r5f";
+ reg = <0x41400000 0x00008000>,
+ <0x41410000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <245>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 245 1>;
+ firmware-name = "am65x-mcu-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
};
};
/*
* Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
};
};
- wkup_pmx0: pinmux@4301c000 {
+ chipid@43000014 {
+ compatible = "ti,am654-chipid";
+ reg = <0x43000014 0x4>;
+ };
+
+ wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
reg = <0x4301c000 0x118>;
#pinctrl-cells = <1>;
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
+ power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
};
wkup_i2c0: i2c@42120000 {
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
- chipid: chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x43000014 0x4>;
+ intr_wkup_gpio: interrupt-controller2 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <156>;
+ ti,interrupt-ranges = <0 712 16>;
+ };
+
+ wkup_gpio0: gpio@42110000 {
+ compatible = "ti,am654-gpio", "ti,keystone-gpio";
+ reg = <0x42110000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&intr_wkup_gpio>;
+ interrupts = <60>, <61>, <62>, <63>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <56>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k3_clks 59 0>;
+ clock-names = "gpio";
+ };
+
+ wkup_vtm0: temperature-sensor@42050000 {
+ compatible = "ti,am654-vtm";
+ reg = <0x42050000 0x25c>;
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal_zones: thermal-zones {
+ #include "k3-am654-industrial-thermal.dtsi"
};
};
/*
* Device Tree Source for AM6 SoC Family
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
i2c5 = &main_i2c3;
- spi0 = &ospi0;
- spi1 = &ospi1;
+ ethernet0 = &cpsw_port1;
};
chosen { };
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
/* MCUSS Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
ethernet0 = &cpsw_port1;
usb0 = &usb0;
usb1 = &usb1;
+ spi0 = &ospi0;
+ spi1 = &ospi1;
};
};
&cbass_main{
u-boot,dm-spl;
-
- sdhci1: sdhci@04FA0000 {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4FA0000 0x0 0x1000>,
- <0x0 0x4FB0000 0x0 0x400>;
- clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
- clock-names = "clk_ahb", "clk_xin";
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- max-frequency = <25000000>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x4>;
- ti,otap-del-sel-ddr52 = <0x4>;
- ti,otap-del-sel-hs200 = <0x7>;
- ti,trm-icp = <0x8>;
+ main-navss {
+ u-boot,dm-spl;
};
-
};
&cbass_mcu {
u-boot,dm-spl;
- mcu_navss {
+ mcu-navss {
u-boot,dm-spl;
ringacc@2b800000 {
u-boot,dm-spl;
+ ti,dma-ring-reset-quirk;
};
dma-controller@285c0000 {
&cbass_wakeup {
u-boot,dm-spl;
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
};
&secure_proxy_main {
&main_pmx0 {
u-boot,dm-spl;
- main_uart0_pins_default: main_uart0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- >;
- u-boot,dm-spl;
- };
-
- main_mmc0_pins_default: main_mmc0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- u-boot,dm-spl;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
- >;
- u-boot,dm-spl;
- };
-
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
};
};
+&main_uart0_pins_default {
+ u-boot,dm-spl;
+};
+
&main_pmx1 {
u-boot,dm-spl;
};
&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu_cpsw_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
- AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
- AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
- AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
- AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
- AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
- AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
- AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
- AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
- AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
- AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
- AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
- >;
- };
-
- mcu_mdio_pins_default: mcu_mdio1_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
- AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
- >;
- };
-
mcu-fss0-ospi0-pins-default {
u-boot,dm-spl;
};
&main_uart0 {
u-boot,dm-spl;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
};
-&sdhci0 {
+&main_mmc0_pins_default {
u-boot,dm-spl;
};
-&sdhci1 {
+&main_mmc1_pins_default {
u-boot,dm-spl;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- sdhci-caps-mask = <0x7 0x0>;
- ti,driver-strength-ohm = <50>;
};
-&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+&sdhci0 {
+ u-boot,dm-spl;
+};
+
+&sdhci1 {
+ u-boot,dm-spl;
};
&davinci_mdio {
};
};
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x2>;
};
};
-&chipid {
- u-boot,dm-spl;
-};
-
&dwc3_0 {
status = "okay";
u-boot,dm-spl;
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am654.dtsi"
-#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
/ {
compatible = "ti,am654-evm", "ti,am654";
bootargs = "earlycon=ns16550a,mmio32,0x02800000";
};
- aliases {
- remoteproc0 = &mcu_r5fss0_core0;
- remoteproc1 = &mcu_r5fss0_core1;
- };
-
memory@80000000 {
device_type = "memory";
/* 4G RAM */
#address-cells = <2>;
#size-cells = <2>;
ranges;
- secure_ddr: secure_ddr@9e800000 {
+
+ secure_ddr: secure-ddr@9e800000 {
reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa0000000 0 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa0100000 0 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa1000000 0 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa1100000 0 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a2000000 {
+ reg = <0x00 0xa2000000 0x00 0x00100000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&push_button_pins_default>;
+
+ sw5 {
+ label = "GPIO Key USER1";
+ linux,code = <BTN_0>;
+ gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
+ };
+
+ sw6 {
+ label = "GPIO Key USER2";
+ linux,code = <BTN_1>;
+ gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ clk_ov5640_fixed: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
};
};
-&main_pmx0 {
- main_mmc0_pins_default: main_mmc0_pins_default {
+&wkup_pmx0 {
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
- usb1_pins_default: usb1_pins_default {
+ push_button_pins_default: push-button-pins-default {
pinctrl-single,pins = <
- AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
+ AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
+ AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
+ >;
+ };
+
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
+ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
+ AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
+ AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
+ AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
+ AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
+ AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
+ AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
+ AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
+ AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
+ AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
+ >;
+ };
+
+ wkup_pca554_default: wkup-pca554-default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
+ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
+ AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
+ AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
+ AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
+ AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
+ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
+ AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
+ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
+ >;
+ };
+};
+
+&main_pmx0 {
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
+ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
+ AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
+ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
>;
};
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
>;
};
+
+ main_spi0_pins_default: main-spi0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
+ AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
+ AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
+ AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
+ >;
+ };
+
+ main_mmc0_pins_default: main-mmc0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
+ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
+ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
+ AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
+ AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
+ AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
+ AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
+ AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
+ AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
+ >;
+ };
+
+ usb1_pins_default: usb1-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
+ >;
+ };
};
&main_pmx1 {
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
-};
-&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ ecap0_pins_default: ecap0-pins-default {
pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
+ AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
};
+};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
- AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
- AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
- AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
- AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
- AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
- AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
- >;
- };
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "reserved";
};
-&sdhci0 {
+&main_uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- bus-width = <8>;
- non-removable;
- ti,driver-strength-ohm = <50>;
+ pinctrl-0 = <&main_uart0_pins_default>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
- tca9554: gpio@38 {
+ pca9554: gpio@39 {
compatible = "nxp,pca9554";
- reg = <0x38>;
+ reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_pca554_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
};
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2_phy0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
};
&main_i2c2 {
clock-frequency = <400000>;
};
-&dwc3_1 {
- status = "okay";
+&ecap0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins_default>;
};
-&usb1_phy {
- status = "okay";
+&main_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_spi0_pins_default>;
+ #address-cells = <1>;
+ #size-cells= <0>;
+ ti,pindir-d0-out-d1-in = <1>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ spi-max-frequency = <48000000>;
+ #address-cells = <1>;
+ #size-cells= <1>;
+ };
+};
+
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+/*
+ * Because of erratas i2025 and i2026 for silicon revision 1.0, the
+ * SD card interface might fail. Boards with sr1.0 are recommended to
+ * disable sdhci1
+ */
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ sdhci-caps-mask = <0x7 0x0>;
+ disable-wp;
};
&usb1 {
status = "disabled";
};
+&tscadc0 {
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&tscadc1 {
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&serdes0 {
+ status = "disabled";
+};
+
+&serdes1 {
+ status = "disabled";
+};
+
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+};
+
+&pcie1_rc {
+ status = "disabled";
+};
+
+&pcie1_ep {
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+};
+
+&mcu_r5fss0_core1 {
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+};
+
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <8>;
- spi-max-frequency = <50000000>;
+ spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
#size-cells = <1>;
};
};
+
+&csi2_0 {
+ csi2_phy0: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&mcasp0 {
+ status = "disabled";
+};
+
+&mcasp1 {
+ status = "disabled";
+};
+
+&mcasp2 {
+ status = "disabled";
+};
+
+&dss {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+mpu0_thermal: mpu0-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ mpu0_crit: mpu0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+mpu1_thermal: mpu1-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ mpu1_crit: mpu1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+mcu_thermal: mcu-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ mcu_crit: mcu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
/dts-v1/;
#include "k3-am654.dtsi"
-#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
};
};
+&wkup_gpio0 {
+ u-boot,dm-spl;
+};
+
&cbass_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
u-boot,dm-spl;
};
- wkup_gpio0: wkup_gpio0@42110000 {
- compatible = "ti,k2g-gpio", "ti,keystone-gpio";
- reg = <0x42110000 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- ti,ngpio = <56>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k3_clks 59 0>;
- clock-names = "gpio";
- u-boot,dm-spl;
- };
-
- wkup_vtm0: wkup_vtm@42050000 {
- compatible = "ti,am654-vtm", "ti,am654-avs";
- reg = <0x42050000 0x25c>;
- power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <48000000>;
+ /delete-property/ power-domains;
status = "okay";
};
&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ status = "okay";
};
&wkup_vtm0 {
+ compatible = "ti,am654-vtm", "ti,am654-avs";
vdd-supply-3 = <&vdd_mpu>;
vdd-supply-4 = <&vdd_mpu>;
u-boot,dm-spl;
&main_pmx0 {
u-boot,dm-spl;
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
+ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
+ AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
+ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
+ >;
+ u-boot,dm-spl;
+ };
+
main_mmc0_pins_default: main_mmc0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
+ u-boot,dm-spl;
+ };
+
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
+ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
+ AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
+ AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
+ AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
+ AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
+ AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
+ AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
+ >;
+ u-boot,dm-spl;
};
};
&sdhci0 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
+ pinctrl-0 = <&main_mmc0_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
};
&sdhci1 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
+ pinctrl-0 = <&main_mmc1_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
};
&scm_conf {
u-boot,dm-spl;
};
+
+#include "k3-am654-base-board-u-boot.dtsi"
/*
* Device Tree Source for AM6 SoC family in Quad core configuration
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am65.dtsi"
};
cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
};
cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
};
cpu2: cpu@100 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
enable-method = "psci";
};
cpu3: cpu@101 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
enable-method = "psci";
aliases {
ethernet0 = &cpsw_port1;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &mcu_i2c1;
+ i2c3 = &main_i2c0;
};
};
-&chipid {
- u-boot,dm-spl;
-};
-
&cbass_main {
u-boot,dm-spl;
};
clock-frequency = <25000000>;
u-boot,dm-spl;
};
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
};
&secure_proxy_main {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
cpsw-phy-sel@40f04040 {
compatible = "ti,am654-cpsw-phy-sel";
u-boot,dm-spl;
};
-&wkup_gpio0 {
- u-boot,dm-spl;
-};
-
&mcu_fss0_hpb0_pins_default {
u-boot,dm-spl;
};
/dts-v1/;
-#include <dt-bindings/net/ti-dp83867.h>
#include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
chosen {
remoteproc2 = &main_r5fss0_core0;
remoteproc3 = &main_r5fss0_core1;
};
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: gpio-regulator-vdd-sd-dv {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_sd_dv";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0
+ 3300000 0x1>;
+ };
};
&wkup_pmx0 {
>;
};
- mcu_cpsw_pins_default: mcu_cpsw_pins_default {
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
>;
};
- mcu_mdio_pins_default: mcu_mdio1_pins_default {
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
- main_usbss0_pins_default: main_usbss0_pins_default {
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
+ J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
- status = "disabled";
+ status = "reserved";
};
&main_uart0 {
+ /* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&main_uart2 {
/* MAIN UART 2 is used by R5F firmware */
- status = "disabled";
+ status = "reserved";
};
&main_uart3 {
status = "disabled";
};
-&wkup_i2c0 {
+&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};
-&main_sdhci0 {
- /* eMMC */
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
};
-&main_sdhci1 {
- /* SD card */
- ti,driver-strength-ohm = <50>;
- disable-wp;
- no-1-8-v;
- sdhci-caps-mask = <0x8000000F 0x0>;
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
};
&main_i2c0 {
};
};
-&usbss0 {
+/*
+ * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
+ * swapped on the CPB.
+ *
+ * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
+ * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
+ */
+&main_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&main_usbss0_pins_default>;
- ti,vbus-divider;
- ti,usb2-only;
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ exp3: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
+ "UB926_LOCK", "UB926_PWR_SW_CNTRL",
+ "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
+ };
};
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
};
-&wkup_gpio0 {
+&main_sdhci1 {
+ /* SD card */
+ pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
- pinctrl-0 = <&wkup_gpio_pins_default>;
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
};
-&mcu_cpsw {
+&serdes_ln_ctrl {
+ idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
+ <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
+};
+
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+ ti,usb2-only;
};
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
};
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
+&tscadc0 {
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
};
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
- reg = <0x0 0x70000000 0x0 0x100000>;
+ reg = <0x00 0x70000000 0x00 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x70000000 0x100000>;
+ ranges = <0x00 0x00 0x70000000 0x100000>;
atf-sram@0 {
- reg = <0x0 0x20000>;
+ reg = <0x00 0x20000>;
+ };
+ };
+
+ scm_conf: scm-conf@100000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00100000 0x00 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
+ };
+
+ usb_serdes_mux: mux-controller@4000 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
};
};
};
- main_navss: navss@30000000 {
+ main_gpio_intr: interrupt-controller0 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <131>;
+ ti,interrupt-ranges = <8 392 56>;
+ };
+
+ main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+ ti,sci-dev-id = <199>;
+
+ main_navss_intr: interrupt-controller1 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <4>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <213>;
+ ti,interrupt-ranges = <0 64 64>,
+ <64 448 64>,
+ <128 672 64>;
+ };
+
+ main_udmass_inta: msi-controller@33d00000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x33d00000 0x00 0x100000>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ interrupt-parent = <&main_navss_intr>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <209>;
+ ti,interrupt-ranges = <0 0 256>;
+ };
secure_proxy_main: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ hwspinlock: spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f80000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster1: mailbox@31f81000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f81000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster2: mailbox@31f82000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f82000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster3: mailbox@31f83000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f83000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster4: mailbox@31f84000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f84000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster5: mailbox@31f85000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f85000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster6: mailbox@31f86000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f86000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster7: mailbox@31f87000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f87000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster8: mailbox@31f88000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f88000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster9: mailbox@31f89000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f89000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster10: mailbox@31f8a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster11: mailbox@31f8b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ main_ringacc: ringacc@3c000000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x00 0x3c000000 0x00 0x400000>,
+ <0x00 0x38000000 0x00 0x400000>,
+ <0x00 0x31120000 0x00 0x100>,
+ <0x00 0x33000000 0x00 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <1024>;
+ ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <211>;
+ msi-parent = <&main_udmass_inta>;
+ };
+
+ main_udmap: dma-controller@31150000 {
+ compatible = "ti,j721e-navss-main-udmap";
+ reg = <0x00 0x31150000 0x00 0x100>,
+ <0x00 0x34000000 0x00 0x100000>,
+ <0x00 0x35000000 0x00 0x100000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <1>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <212>;
+ ti,ringacc = <&main_ringacc>;
+
+ ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+ <0x0f>, /* TX_HCHAN */
+ <0x10>; /* TX_UHCHAN */
+ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+ <0x0b>, /* RX_HCHAN */
+ <0x0c>; /* RX_UHCHAN */
+ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ };
+
+ cpts@310d0000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x00 0x310d0000 0x00 0x400>;
+ reg-names = "cpts";
+ clocks = <&k3_clks 201 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&main_navss_intr 391>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+ };
};
- main_pmx0: pinmux@11c000 {
+ main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x0 0x11c000 0x0 0x2b4>;
+ reg = <0x00 0x11c000 0x00 0x2b4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,clkbuf-sel = <0x7>;
dma-coherent;
};
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2000000 0x0 0x100>;
+ reg = <0x00 0x2000000 0x00 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 187 1>;
- power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
};
main_i2c1: i2c@2010000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2010000 0x0 0x100>;
+ reg = <0x00 0x2010000 0x00 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
main_i2c2: i2c@2020000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2020000 0x0 0x100>;
+ reg = <0x00 0x2020000 0x00 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
main_i2c3: i2c@2030000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2030000 0x0 0x100>;
+ reg = <0x00 0x2030000 0x00 0x100>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
main_i2c4: i2c@2040000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2040000 0x0 0x100>;
+ reg = <0x00 0x2040000 0x00 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
main_i2c5: i2c@2050000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2050000 0x0 0x100>;
+ reg = <0x00 0x2050000 0x00 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
main_i2c6: i2c@2060000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2060000 0x0 0x100>;
+ reg = <0x00 0x2060000 0x00 0x100>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
- usbss0: cdns_usb@4104000 {
+ main_gpio0: gpio@600000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00600000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+ <105 1 IRQ_TYPE_EDGE_RISING>,
+ <105 2 IRQ_TYPE_EDGE_RISING>,
+ <105 3 IRQ_TYPE_EDGE_RISING>,
+ <105 4 IRQ_TYPE_EDGE_RISING>,
+ <105 5 IRQ_TYPE_EDGE_RISING>,
+ <105 6 IRQ_TYPE_EDGE_RISING>,
+ <105 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 0>;
+ clock-names = "gpio";
+ };
+
+ usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
dma-coherent;
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
- clock-names = "usb2_refclk", "lpm_clk";
+ clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
#address-cells = <2>;
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j7200-r5fss";
- lockstep-mode = <0>;
+ ti,cluster-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
ti,sci-proc-ids = <0x06 0xFF>;
resets = <&k3_reset 245 1>;
firmware-name = "j7200-main-r5f0_0-fw";
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
ti,sci-proc-ids = <0x07 0xFF>;
resets = <&k3_reset 246 1>;
firmware-name = "j7200-main-r5f0_1-fw";
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
};
};
};
<&secure_proxy_main 13>;
reg-names = "debug_messages";
- reg = <0x00 0x44083000 0x0 0x1000>;
+ reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
};
};
- chipid: chipid@43000014 {
+ mcu_conf: syscon@40f00000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x40f00000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x40f00000 0x20000>;
+
+ phy_gmii_sel: phy@4040 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4040 0x4>;
+ #phy-cells = <1>;
+ };
+ };
+
+ chipid@43000014 {
compatible = "ti,am654-chipid";
- reg = <0x0 0x43000014 0x0 0x4>;
+ reg = <0x00 0x43000014 0x00 0x4>;
};
- wkup_pmx0: pinmux@4301c000 {
+ wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
- ranges = <0x0 0x00 0x41c00000 0x100000>;
+ ranges = <0x00 0x00 0x41c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
clock-names = "fclk";
};
- wkup_i2c0: i2c@42120000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x42120000 0x0 0x100>;
- interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 197 1>;
- power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
- };
-
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
clock-names = "fclk";
};
- fss: system-controller@47000000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x47000000 0x0 0x100>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hbmc_mux: hbmc-mux {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4 0x2>; /* HBMC select */
- };
-
- hbmc: hyperbus@47034000 {
- compatible = "ti,am654-hbmc";
- reg = <0x0 0x47034000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <1>;
- mux-controls = <&hbmc_mux 0>;
- clocks = <&k3_clks 102 5>;
- assigned-clocks = <&k3_clks 102 5>;
- assigned-clock-rates = <333333333>;
- };
- };
-
- mcu_i2c0: i2c@40b00000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b00000 0x0 0x100>;
- interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 194 1>;
- power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
- };
-
- mcu_i2c1: i2c@40b10000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b10000 0x0 0x100>;
- interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 195 1>;
- power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ wkup_gpio_intr: interrupt-controller2 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <137>;
+ ti,interrupt-ranges = <16 960 16>;
};
- cbass_mcu_navss: mcu-navss {
+ mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
- ranges;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
-
ti,sci-dev-id = <232>;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>;
+ reg = <0x00 0x2b800000 0x00 0x400000>,
+ <0x00 0x2b000000 0x00 0x400000>,
+ <0x00 0x28590000 0x00 0x100>,
+ <0x00 0x2a500000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
+ msi-parent = <&main_udmass_inta>;
};
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
+ reg = <0x00 0x285c0000 0x00 0x100>,
+ <0x00 0x2a800000 0x00 0x40000>,
+ <0x00 0x2aa00000 0x00 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&dmsc>;
};
};
- wkup_gpio0: gpio@42110000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x42110000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- ti,ngpio = <84>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 113 0>;
- clock-names = "gpio";
- };
-
- mcu_conf: scm_conf@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x40f00000 0x20000>;
-
- phy_gmii_sel: phy@4040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg = <0x4040 0x4>;
- reg-names = "gmii-sel";
- #phy-cells = <1>;
- };
- };
-
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
- reg = <0x0 0x46000000 0x0 0x200000>;
+ reg = <0x00 0x46000000 0x00 0x200000>;
reg-names = "cpsw_nuss";
- ranges;
+ ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
dma-coherent;
clocks = <&k3_clks 18 21>;
clock-names = "fck";
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
- ti,label = "port1";
+ label = "port1";
ti,syscon-efuse = <&mcu_conf 0x200>;
phys = <&phy_gmii_sel 1>;
};
davinci_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
+ reg = <0x00 0xf00 0x00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 18 21>;
bus_freq = <1000000>;
};
- cpts {
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
clocks = <&k3_clks 18 2>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
};
};
+ mcu_i2c0: i2c@40b00000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x40b00000 0x00 0x100>;
+ interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 194 1>;
+ power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcu_i2c1: i2c@40b10000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x40b10000 0x00 0x100>;
+ interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 195 1>;
+ power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ wkup_i2c0: i2c@42120000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x42120000 0x00 0x100>;
+ interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 197 1>;
+ power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+ };
+
+ fss: syscon@47000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x47000000 0x00 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hbmc_mux: hbmc-mux {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4 0x2>; /* HBMC select */
+ };
+
+ hbmc: hyperbus@47034000 {
+ compatible = "ti,am654-hbmc";
+ reg = <0x00 0x47034000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x0000000>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 0>;
+ assigned-clocks = <&k3_clks 102 5>;
+ assigned-clock-rates = <333333333>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ mux-controls = <&hbmc_mux 0>;
+ };
+ };
+
+ tscadc0: tscadc@40200000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x00 0x40200000 0x00 0x1000>;
+ interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 0 1>;
+ assigned-clocks = <&k3_clks 0 3>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "adc_tsc_fck";
+ dmas = <&main_udmap 0x7400>,
+ <&main_udmap 0x7401>;
+ dma-names = "fifo0", "fifo1";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j7200-r5fss";
- lockstep-mode = <1>;
+ ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 250 1>;
firmware-name = "j7200-mcu-r5f0_0-fw";
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 251 1>;
firmware-name = "j7200-mcu-r5f0_1-fw";
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
};
};
};
>;
};
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
memory@80000000 {
device_type = "memory";
/* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
+ reg = <0x00 0x80000000 0x00 0x80000000>,
+ <0x08 0x80000000 0x00 0x80000000>;
};
reserved_memory: reserved-memory {
};
};
+&main_pmx0 {
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
+ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
+ >;
+ };
+};
+
&hbmc {
+ /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
+ * appropriate node based on board detection
+ */
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
- ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
- <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
+ ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
+ <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x0 0x4000000>;
+ reg = <0x00 0x00 0x4000000>;
+ };
+};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ exp_som: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+ "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+ "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
+ "GPIO_LIN_EN", "CAN_STB";
};
};
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
- i2c4 = &main_i2c1;
- i2c5 = &main_i2c2;
- i2c6 = &main_i2c3;
- i2c7 = &main_i2c4;
- i2c8 = &main_i2c5;
- i2c9 = &main_i2c6;
};
+ chosen { };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
- <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
- <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
+ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
+ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
/* MCUSS_WKUP Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>;
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
compatible = "simple-bus";
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>; /* FSS OSPI0 data region 3 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
};
};
};
aliases {
ethernet0 = &cpsw_port1;
+ spi0 = &ospi0;
+ spi1 = &ospi1;
+ remoteproc0 = &mcu_r5fss0_core0;
+ remoteproc1 = &mcu_r5fss0_core1;
+ remoteproc2 = &main_r5fss0_core0;
+ remoteproc3 = &main_r5fss0_core1;
+ remoteproc4 = &main_r5fss1_core0;
+ remoteproc5 = &main_r5fss1_core1;
+ remoteproc6 = &c66_0;
+ remoteproc7 = &c66_1;
+ remoteproc8 = &c71_0;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &mcu_i2c1;
+ i2c3 = &main_i2c0;
};
};
&cbass_main{
u-boot,dm-spl;
+
+ main-navss {
+ u-boot,dm-spl;
+ };
};
&cbass_mcu_wakeup {
u-boot,dm-spl;
};
- mcu_navss {
+ mcu-navss {
u-boot,dm-spl;
ringacc@2b800000 {
u-boot,dm-spl;
};
};
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
};
&secure_proxy_main {
&wkup_pmx0 {
u-boot,dm-spl;
- mcu_cpsw_pins_default: mcu_cpsw_pins_default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
- J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
- J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
- J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
- J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
- J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
- J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
- J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
- J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
- J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
- J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
- >;
- };
-
- mcu_mdio_pins_default: mcu_mdio1_pins_default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
- J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
- >;
- };
};
&main_pmx0 {
};
&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
-&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x2>;
reg-names = "cpsw_nuss", "mac_efuse";
&mcu_fss0_ospi1_pins_default {
u-boot,dm-spl;
};
-
-&chipid {
- u-boot,dm-spl;
-};
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
/ {
chosen {
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
- aliases {
- remoteproc0 = &mcu_r5fss0_core0;
- remoteproc1 = &mcu_r5fss0_core1;
- remoteproc2 = &main_r5fss0_core0;
- remoteproc3 = &main_r5fss0_core1;
- remoteproc4 = &main_r5fss1_core0;
- remoteproc5 = &main_r5fss1_core1;
- remoteproc6 = &c66_0;
- remoteproc7 = &c66_1;
- remoteproc8 = &c71_0;
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+
+ sw10: sw10 {
+ label = "GPIO Key USER1";
+ linux,code = <BTN_0>;
+ gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ sw11: sw11 {
+ label = "GPIO Key USER2";
+ linux,code = <BTN_1>;
+ gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
+ };
};
-};
-&wkup_uart0 {
- /* Wakeup UART is used by System firmware */
- status = "disabled";
-};
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
-&main_uart0 {
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of LMS140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
-&main_uart3 {
- /* UART not brought out */
- status = "disabled";
-};
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
-&main_uart5 {
- /* UART not brought out */
- status = "disabled";
-};
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+ };
-&main_uart6 {
- /* UART not brought out */
- status = "disabled";
-};
+ vdd_sd_dv_alt: gpio-regulator-TLV71033 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
-&main_uart7 {
- /* UART not brought out */
- status = "disabled";
-};
+ sound0: sound@0 {
+ compatible = "ti,j721e-cpb-audio";
+ model = "j721e-cpb";
-&main_uart8 {
- /* UART not brought out */
- status = "disabled";
-};
+ ti,cpb-mcasp = <&mcasp10>;
+ ti,cpb-codec = <&pcm3168a_1>;
-&main_uart9 {
- /* UART not brought out */
- status = "disabled";
+ clocks = <&k3_clks 184 1>,
+ <&k3_clks 184 2>, <&k3_clks 184 4>,
+ <&k3_clks 157 371>,
+ <&k3_clks 157 400>, <&k3_clks 157 401>;
+ clock-names = "cpb-mcasp-auxclk",
+ "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
+ "cpb-codec-scki",
+ "cpb-codec-scki-48000", "cpb-codec-scki-44100";
+ };
};
&main_pmx0 {
- main_mmc1_pins_default: main_mmc1_pins_default {
+ sw10_button_pins_default: sw10-button-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
};
-};
-&main_sdhci0 {
- /* eMMC */
- non-removable;
- ti,driver-strength-ohm = <50>;
-};
-
-&main_sdhci1 {
- /* SD card */
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
-};
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+ >;
+ };
-&main_pmx0 {
- main_usbss0_pins_default: main_usbss0_pins_default {
+ main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
- main_usbss1_pins_default: main_usbss1_pins_default {
+ main_usbss1_pins_default: main-usbss1-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
+ main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
+ >;
+ };
+
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_i2c6_pins_default: main-i2c6-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
+ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
+ >;
+ };
+
+ mcasp10_pins_default: mcasp10-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
+ J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
+ J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
+ J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
+ J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
+ J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
+ J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
+ J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
+ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
+ >;
+ };
+
+ audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
+ >;
+ };
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ sw11_button_pins_default: sw11-button-pins-default {
pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
>;
};
J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
>;
};
+
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
+ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "reserved";
+};
+
+&main_uart0 {
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart5 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio3 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio5 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&main_gpio7 {
+ status = "disabled";
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
};
&usbss0 {
&usb0 {
dr_mode = "otg";
maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
};
&usbss1 {
maximum-speed = "high-speed";
};
-&wkup_i2c0 {
+&ospi1 {
pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
+ pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&tscadc0 {
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&tscadc1 {
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
};
&main_i2c0 {
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+
+ p09-hog {
+ /* P11 - MCASP/TRACE_MUX_S0 */
+ gpio-hog;
+ gpios = <9 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "MCASP/TRACE_MUX_S0";
+ };
+
+ p10-hog {
+ /* P12 - MCASP/TRACE_MUX_S1 */
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MCASP/TRACE_MUX_S1";
+ };
};
};
-&ospi1 {
+&main_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
- flash@0{
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <40000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
+ exp4: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_exp4_pins_default>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
};
+
+&k3_clks {
+ /* Confiure AUDIO_EXT_REFCLK2 pin as output */
+ pinctrl-names = "default";
+ pinctrl-0 = <&audi_ext_refclk2_pins_default>;
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+
+ exp3: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pcm3168a_1: audio-codec@44 {
+ compatible = "ti,pcm3168a";
+ reg = <0x44>;
+
+ #sound-dai-cells = <1>;
+
+ reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
+
+ /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
+ clocks = <&k3_clks 157 371>;
+ clock-names = "scki";
+
+ /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
+ assigned-clocks = <&k3_clks 157 371>;
+ assigned-clock-parents = <&k3_clks 157 400>;
+ assigned-clock-rates = <24576000>; /* for 48KHz */
+
+ VDD1-supply = <&vsys_3v3>;
+ VDD2-supply = <&vsys_3v3>;
+ VCCAD1-supply = <&vsys_5v0>;
+ VCCAD2-supply = <&vsys_5v0>;
+ VCCDA1-supply = <&vsys_5v0>;
+ VCCDA2-supply = <&vsys_5v0>;
+ };
+};
+
+&main_i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c6_pins_default>;
+ clock-frequency = <400000>;
+
+ exp5: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ /*
+ * These clock assignments are chosen to enable the following outputs:
+ *
+ * VP0 - DisplayPort SST
+ * VP1 - DPI0
+ * VP2 - DSI
+ * VP3 - DPI1
+ */
+
+ assigned-clocks = <&k3_clks 152 1>,
+ <&k3_clks 152 4>,
+ <&k3_clks 152 9>,
+ <&k3_clks 152 13>;
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* PLL19_HSDIV0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* PLL23_HSDIV0 */
+};
+
+&mcasp0 {
+ status = "disabled";
+};
+
+&mcasp1 {
+ status = "disabled";
+};
+
+&mcasp2 {
+ status = "disabled";
+};
+
+&mcasp3 {
+ status = "disabled";
+};
+
+&mcasp4 {
+ status = "disabled";
+};
+
+&mcasp5 {
+ status = "disabled";
+};
+
+&mcasp6 {
+ status = "disabled";
+};
+
+&mcasp7 {
+ status = "disabled";
+};
+
+&mcasp8 {
+ status = "disabled";
+};
+
+&mcasp9 {
+ status = "disabled";
+};
+
+&mcasp10 {
+ #sound-dai-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcasp10_pins_default>;
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ auxclk-fs-ratio = <256>;
+
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 1 1 1
+ 2 2 2 0
+ >;
+ tx-num-evt = <0>;
+ rx-num-evt = <0>;
+};
+
+&mcasp11 {
+ status = "disabled";
+};
+
+&serdes0 {
+ serdes0_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&serdes2 {
+ serdes2_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie2_rc {
+ reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes2_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie0_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
+
+&pcie1_ep {
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ status = "disabled";
+};
+
+&pcie2_ep {
+ phys = <&serdes2_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ status = "disabled";
+};
+
+&pcie3_rc {
+ status = "disabled";
+};
+
+&pcie3_ep {
+ status = "disabled";
+};
+
+&dss {
+ status = "disabled";
+};
/*
* Device Tree Source for J721E SoC Family Main Domain peripherals
*
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/mux/ti-serdes.h>
&cbass_main {
msmc_ram: sram@70000000 {
};
};
+ scm_conf: scm-conf@100000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x00100000 0x1c000>;
+
+ pcie0_ctrl: syscon@4070 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00004070 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x4070 0x4070 0x4>;
+ };
+
+ pcie1_ctrl: syscon@4074 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00004074 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x4074 0x4074 0x4>;
+ };
+
+ pcie2_ctrl: syscon@4078 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00004078 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x4078 0x4078 0x4>;
+ };
+
+ pcie3_ctrl: syscon@407c {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x0000407c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x407c 0x407c 0x4>;
+ };
+
+ serdes_ln_ctrl: mux@4080 {
+ compatible = "mmio-mux";
+ reg = <0x00004080 0x50>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+ <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+ /* SERDES4 lane0/1/2/3 select */
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
+ <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+ };
+
+ usb_serdes_mux: mux-controller@4000 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
+ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- gic_its: gic-its@18200000 {
+ gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
};
};
- smmu0: smmu@36600000 {
- compatible = "arm,smmu-v3";
- reg = <0x0 0x36600000 0x0 0x100000>;
+ main_gpio_intr: interrupt-controller0 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "eventq", "gerror";
- #iommu-cells = <1>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <131>;
+ ti,interrupt-ranges = <8 392 56>;
+ };
+
+ main-navss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+ dma-ranges;
+
+ ti,sci-dev-id = <199>;
+
+ main_navss_intr: interrupt-controller1 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <4>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <213>;
+ ti,interrupt-ranges = <0 64 64>,
+ <64 448 64>,
+ <128 672 64>;
+ };
+
+ main_udmass_inta: interrupt-controller@33d00000 {
+ compatible = "ti,sci-inta";
+ reg = <0x0 0x33d00000 0x0 0x100000>;
+ interrupt-controller;
+ interrupt-parent = <&main_navss_intr>;
+ msi-controller;
+ #interrupt-cells = <0>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <209>;
+ ti,interrupt-ranges = <0 0 256>;
+ };
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ smmu0: iommu@36600000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x36600000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror";
+ #iommu-cells = <1>;
+ };
+
+ hwspinlock: spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f80000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster1: mailbox@31f81000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f81000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster2: mailbox@31f82000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f82000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster3: mailbox@31f83000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f83000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster4: mailbox@31f84000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f84000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster5: mailbox@31f85000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f85000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster6: mailbox@31f86000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f86000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster7: mailbox@31f87000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f87000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster8: mailbox@31f88000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f88000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster9: mailbox@31f89000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f89000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster10: mailbox@31f8a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ mailbox0_cluster11: mailbox@31f8b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ };
+
+ main_ringacc: ringacc@3c000000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <1024>;
+ ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <211>;
+ msi-parent = <&main_udmass_inta>;
+ };
+
+ main_udmap: dma-controller@31150000 {
+ compatible = "ti,j721e-navss-main-udmap";
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <1>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <212>;
+ ti,ringacc = <&main_ringacc>;
+
+ ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+ <0x0f>, /* TX_HCHAN */
+ <0x10>; /* TX_UHCHAN */
+ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+ <0x0b>, /* RX_HCHAN */
+ <0x0c>; /* RX_UHCHAN */
+ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ };
+
+ cpts@310d0000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x310d0000 0x0 0x400>;
+ reg-names = "cpts";
+ clocks = <&k3_clks 201 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&main_navss_intr 391>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+ };
};
- secure_proxy_main: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x32c00000 0x00 0x100000>,
- <0x00 0x32400000 0x00 0x100000>,
- <0x00 0x32800000 0x00 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ main_crypto: crypto@4e00000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x0 0x4e00000 0x0 0x1200>;
+ power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
+
+ dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
+ <&main_udmap 0x4001>;
+ dma-names = "tx", "rx1", "rx2";
+ dma-coherent;
+
+ rng: rng@4e10000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x0 0x4e10000 0x0 0x7d>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 264 1>;
+ };
};
- main_pmx0: pinmux@11c000 {
+ main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x0 0x11c000 0x0 0x2b4>;
pinctrl-single,function-mask = <0xffffffff>;
};
+ dummy_cmn_refclk: dummy-cmn-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ dummy_cmn_refclk1: dummy-cmn-refclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ serdes_wiz0: wiz@5000000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
+ assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5000000 0x0 0x5000000 0x10000>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 292 11>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 292 0>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 11>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz0_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5000000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz0 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz1: wiz@5010000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
+ assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5010000 0x0 0x5010000 0x10000>;
+
+ wiz1_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 293 13>;
+ };
+
+ wiz1_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 293 0>;
+ };
+
+ wiz1_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 293 13>;
+ };
+
+ wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
+ clocks = <&wiz1_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz1_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes1: serdes@5010000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz1 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz2: wiz@5020000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
+ assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5020000 0x0 0x5020000 0x10000>;
+
+ wiz2_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 294 11>;
+ };
+
+ wiz2_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 294 0>;
+ };
+
+ wiz2_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 294 11>;
+ };
+
+ wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz2_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz2_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes2: serdes@5020000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz2 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz3: wiz@5030000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
+ assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5030000 0x0 0x5030000 0x10000>;
+
+ wiz3_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 295 9>;
+ };
+
+ wiz3_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 295 0>;
+ };
+
+ wiz3_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 295 9>;
+ };
+
+ wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz3_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz3_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes3: serdes@5030000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz3 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ pcie0_rc: pcie@2900000 {
+ compatible = "ti,j721e-pcie-host";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 239 1>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ vendor-id = <0x104c>;
+ device-id = <0xb00d>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie0_ep: pcie-ep@2900000 {
+ compatible = "ti,j721e-pcie-ep";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 239 1>;
+ clock-names = "fck";
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ dma-coherent;
+ };
+
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 1>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ vendor-id = <0x104c>;
+ device-id = <0xb00d>;
+ msi-map = <0x0 &gic_its 0x10000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 1>;
+ clock-names = "fck";
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ dma-coherent;
+ };
+
+ pcie2_rc: pcie@2920000 {
+ compatible = "ti,j721e-pcie-host";
+ reg = <0x00 0x02920000 0x00 0x1000>,
+ <0x00 0x02927000 0x00 0x400>,
+ <0x00 0x0e000000 0x00 0x00800000>,
+ <0x44 0x00000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 241 1>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ vendor-id = <0x104c>;
+ device-id = <0xb00d>;
+ msi-map = <0x0 &gic_its 0x20000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie2_ep: pcie-ep@2920000 {
+ compatible = "ti,j721e-pcie-ep";
+ reg = <0x00 0x02920000 0x00 0x1000>,
+ <0x00 0x02927000 0x00 0x400>,
+ <0x00 0x0e000000 0x00 0x00800000>,
+ <0x44 0x00000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 241 1>;
+ clock-names = "fck";
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ dma-coherent;
+ };
+
+ pcie3_rc: pcie@2930000 {
+ compatible = "ti,j721e-pcie-host";
+ reg = <0x00 0x02930000 0x00 0x1000>,
+ <0x00 0x02937000 0x00 0x400>,
+ <0x00 0x0e800000 0x00 0x00800000>,
+ <0x44 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 242 1>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ vendor-id = <0x104c>;
+ device-id = <0xb00d>;
+ msi-map = <0x0 &gic_its 0x30000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie3_ep: pcie-ep@2930000 {
+ compatible = "ti,j721e-pcie-ep";
+ reg = <0x00 0x02930000 0x00 0x1000>,
+ <0x00 0x02937000 0x00 0x400>,
+ <0x00 0x0e800000 0x00 0x00800000>,
+ <0x44 0x10000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 242 1>;
+ clock-names = "fck";
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ dma-coherent;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg = <0x0 0x00600000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
- <105 1 IRQ_TYPE_EDGE_RISING>,
- <105 2 IRQ_TYPE_EDGE_RISING>,
- <105 3 IRQ_TYPE_EDGE_RISING>,
- <105 4 IRQ_TYPE_EDGE_RISING>,
- <105 5 IRQ_TYPE_EDGE_RISING>,
- <105 6 IRQ_TYPE_EDGE_RISING>,
- <105 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <256>, <257>, <258>, <259>,
+ <260>, <261>, <262>, <263>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <128>;
clock-names = "gpio";
};
+ main_gpio1: gpio@601000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00601000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <288>, <289>, <290>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <36>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 106 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio2: gpio@610000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00610000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <264>, <265>, <266>, <267>,
+ <268>, <269>, <270>, <271>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <128>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio3: gpio@611000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00611000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <292>, <293>, <294>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <36>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 108 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio4: gpio@620000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00620000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <272>, <273>, <274>, <275>,
+ <276>, <277>, <278>, <279>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <128>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 109 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio5: gpio@621000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00621000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <296>, <297>, <298>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <36>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 110 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio6: gpio@630000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00630000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <280>, <281>, <282>, <283>,
+ <284>, <285>, <286>, <287>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <128>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 111 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio7: gpio@631000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00631000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <300>, <301>, <302>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <36>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 112 0>;
+ clock-names = "gpio";
+ };
+
main_sdhci0: sdhci@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
assigned-clocks = <&k3_clks 91 1>;
assigned-clock-parents = <&k3_clks 91 2>;
bus-width = <8>;
- ti,trm-icp = <0x8>;
- dma-coherent;
+ mmc-hs400-1_8v;
mmc-ddr-1_8v;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-legacy = <0xf>;
+ ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
ti,otap-del-sel-hs400 = <0x0>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,itap-del-sel-ddr52 = <0x3>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
};
main_sdhci1: sdhci@4fb0000 {
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,trm-icp = <0x8>;
+ ti,clkbuf-sel = <0x7>;
dma-coherent;
};
- main_r5fss0: r5fss@5c00000 {
- compatible = "ti,j721e-r5fss";
- lockstep-mode = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
- <0x5d00000 0x00 0x5d00000 0x20000>;
- power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss0_core0: r5f@5c00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5c00000 0x00008000>,
- <0x5c10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <245>;
- ti,sci-proc-ids = <0x06 0xFF>;
- resets = <&k3_reset 245 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
-
- main_r5fss0_core1: r5f@5d00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5d00000 0x00008000>,
- <0x5d10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <246>;
- ti,sci-proc-ids = <0x07 0xFF>;
- resets = <&k3_reset 246 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
- };
-
- main_r5fss1: r5fss@5e00000 {
- compatible = "ti,j721e-r5fss";
- lockstep-mode = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
- <0x5f00000 0x00 0x5f00000 0x20000>;
- power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss1_core0: r5f@5e00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5e00000 0x00008000>,
- <0x5e10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <247>;
- ti,sci-proc-ids = <0x08 0xFF>;
- resets = <&k3_reset 247 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
-
- main_r5fss1_core1: r5f@5f00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5f00000 0x00008000>,
- <0x5f10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <248>;
- ti,sci-proc-ids = <0x09 0xFF>;
- resets = <&k3_reset 248 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
- };
-
- c66_0: dsp@4d80800000 {
- compatible = "ti,j721e-c66-dsp";
- reg = <0x4d 0x80800000 0x00 0x00048000>,
- <0x4d 0x80e00000 0x00 0x00008000>,
- <0x4d 0x80f00000 0x00 0x00008000>;
- reg-names = "l2sram", "l1pram", "l1dram";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <142>;
- ti,sci-proc-ids = <0x03 0xFF>;
- resets = <&k3_reset 142 1>;
- };
-
- c66_1: dsp@4d81800000 {
- compatible = "ti,j721e-c66-dsp";
- reg = <0x4d 0x81800000 0x00 0x00048000>,
- <0x4d 0x81e00000 0x00 0x00008000>,
- <0x4d 0x81f00000 0x00 0x00008000>;
- reg-names = "l2sram", "l1pram", "l1dram";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <143>;
- ti,sci-proc-ids = <0x04 0xFF>;
- resets = <&k3_reset 143 1>;
- };
-
- c71_0: dsp@64800000 {
- compatible = "ti,j721e-c71-dsp";
- reg = <0x00 0x64800000 0x00 0x00080000>,
- <0x00 0x64e00000 0x00 0x0000c000>;
- reg-names = "l2sram", "l1dram";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <15>;
- ti,sci-proc-ids = <0x30 0xFF>;
- resets = <&k3_reset 15 1>;
+ main_sdhci2: sdhci@4f98000 {
+ compatible = "ti,j721e-sdhci-4bit";
+ reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
+ assigned-clocks = <&k3_clks 93 0>;
+ assigned-clock-parents = <&k3_clks 93 1>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-ddr50 = <0xc>;
+ ti,trm-icp = <0x8>;
+ ti,clkbuf-sel = <0x7>;
+ dma-coherent;
};
- usbss0: cdns_usb@4104000 {
+ usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
dma-coherent;
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
- clock-names = "usb2_refclk", "lpm_clk";
+ clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
- phy@4108000 {
- compatible = "ti,j721e-usb2-phy";
- reg = <0x00 0x4108000 0x00 0x400>;
- };
-
usb0: usb@6000000 {
compatible = "cdns,usb3";
reg = <0x00 0x6000000 0x00 0x10000>,
};
};
- usbss1: cdns_usb@4114000 {
+ usbss1: cdns-usb@4114000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4114000 0x00 0x100>;
dma-coherent;
power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
- clock-names = "usb2_refclk", "lpm_clk";
+ clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
- phy@4118000 {
- compatible = "ti,j721e-usb2-phy";
- reg = <0x00 0x4118000 0x00 0x400>;
- };
-
usb1: usb@6400000 {
compatible = "cdns,usb3";
reg = <0x00 0x6400000 0x00 0x10000>,
};
};
- ufs_wrapper: ufs-wrapper@4e80000 {
- compatible = "ti,j721e-ufs";
- reg = <0x0 0x4e80000 0x0 0x100>;
- power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 277 1>;
- assigned-clocks = <&k3_clks 277 1>;
- assigned-clock-parents = <&k3_clks 277 4>;
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- ufs@4e84000 {
- compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
- reg = <0x0 0x4e84000 0x0 0x10000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- freq-table-hz = <0 0>, <0 0>;
- clocks = <&k3_clks 277 0>, <&k3_clks 277 1>;
- clock-names = "core_clk", "phy_clk";
- assigned-clocks = <&k3_clks 277 1>;
- assigned-clock-parents = <&k3_clks 277 4>;
- dma-coherent;
- };
- };
-
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2000000 0x0 0x100>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 187 0>;
- power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
};
main_i2c1: i2c@2010000 {
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
+ ufs_wrapper: ufs-wrapper@4e80000 {
+ compatible = "ti,j721e-ufs";
+ reg = <0x0 0x4e80000 0x0 0x100>;
+ power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 277 1>;
+ assigned-clocks = <&k3_clks 277 1>;
+ assigned-clock-parents = <&k3_clks 277 4>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ufs@4e84000 {
+ compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
+ reg = <0x0 0x4e84000 0x0 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
+ clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
+ clock-names = "core_clk", "phy_clk", "ref_clk";
+ dma-coherent;
+ };
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg =
+ <0x00 0x04a00000 0x00 0x10000>, /* common_m */
+ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
+ <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
+ <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
+
+ <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
+ <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
+ <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
+ <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
+
+ <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
+ <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
+ <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
+ <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
+
+ <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
+ <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
+ <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
+ <0x00 0x04af0000 0x00 0x10000>; /* wb */
+
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+
+ clocks = <&k3_clks 152 0>,
+ <&k3_clks 152 1>,
+ <&k3_clks 152 4>,
+ <&k3_clks 152 9>,
+ <&k3_clks 152 13>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+
+ dss_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mcasp0: mcasp@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b00000 0x0 0x2000>,
+ <0x0 0x02b08000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 174 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp1: mcasp@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b10000 0x0 0x2000>,
+ <0x0 0x02b18000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 175 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp2: mcasp@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b20000 0x0 0x2000>,
+ <0x0 0x02b28000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 176 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp3: mcasp@2b30000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b30000 0x0 0x2000>,
+ <0x0 0x02b38000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 177 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp4: mcasp@2b40000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b40000 0x0 0x2000>,
+ <0x0 0x02b48000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 178 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp5: mcasp@2b50000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b50000 0x0 0x2000>,
+ <0x0 0x02b58000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 179 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp6: mcasp@2b60000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b60000 0x0 0x2000>,
+ <0x0 0x02b68000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 180 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp7: mcasp@2b70000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b70000 0x0 0x2000>,
+ <0x0 0x02b78000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 181 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp8: mcasp@2b80000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b80000 0x0 0x2000>,
+ <0x0 0x02b88000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 182 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp9: mcasp@2b90000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02b90000 0x0 0x2000>,
+ <0x0 0x02b98000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 183 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp10: mcasp@2ba0000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02ba0000 0x0 0x2000>,
+ <0x0 0x02ba8000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 184 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcasp11: mcasp@2bb0000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x02bb0000 0x0 0x2000>,
+ <0x0 0x02bb8000 0x0 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 185 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ };
+
watchdog0: watchdog@2200000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x2200000 0x0 0x100>;
assigned-clocks = <&k3_clks 253 1>;
assigned-clock-parents = <&k3_clks 253 5>;
};
+
+ main_r5fss0: r5fss@5c00000 {
+ compatible = "ti,j721e-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+ <0x5d00000 0x00 0x5d00000 0x20000>;
+ power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@5c00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5c00000 0x00008000>,
+ <0x5c10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <245>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 245 1>;
+ firmware-name = "j7-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@5d00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5d00000 0x00008000>,
+ <0x5d10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <246>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 246 1>;
+ firmware-name = "j7-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@5e00000 {
+ compatible = "ti,j721e-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
+ <0x5f00000 0x00 0x5f00000 0x20000>;
+ power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@5e00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5e00000 0x00008000>,
+ <0x5e10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <247>;
+ ti,sci-proc-ids = <0x08 0xff>;
+ resets = <&k3_reset 247 1>;
+ firmware-name = "j7-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@5f00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5f00000 0x00008000>,
+ <0x5f10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <248>;
+ ti,sci-proc-ids = <0x09 0xff>;
+ resets = <&k3_reset 248 1>;
+ firmware-name = "j7-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ c66_0: dsp@4d80800000 {
+ compatible = "ti,j721e-c66-dsp";
+ reg = <0x4d 0x80800000 0x00 0x00048000>,
+ <0x4d 0x80e00000 0x00 0x00008000>,
+ <0x4d 0x80f00000 0x00 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <142>;
+ ti,sci-proc-ids = <0x03 0xff>;
+ resets = <&k3_reset 142 1>;
+ firmware-name = "j7-c66_0-fw";
+ };
+
+ c66_1: dsp@4d81800000 {
+ compatible = "ti,j721e-c66-dsp";
+ reg = <0x4d 0x81800000 0x00 0x00048000>,
+ <0x4d 0x81e00000 0x00 0x00008000>,
+ <0x4d 0x81f00000 0x00 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <143>;
+ ti,sci-proc-ids = <0x04 0xff>;
+ resets = <&k3_reset 143 1>;
+ firmware-name = "j7-c66_1-fw";
+ };
+
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721e-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <15>;
+ ti,sci-proc-ids = <0x30 0xff>;
+ resets = <&k3_reset 15 1>;
+ firmware-name = "j7-c71_0-fw";
+ };
};
/*
* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
*
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
k3_clks: clocks {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
- ti,scan-clocks-from-dt;
};
k3_reset: reset-controller {
};
};
- wkup_pmx0: pinmux@4301c000 {
+ chipid@43000014 {
+ compatible = "ti,am654-chipid";
+ reg = <0x0 0x43000014 0x0 0x4>;
+ };
+
+ wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
pinctrl-single,function-mask = <0xffffffff>;
};
+ mcu_ram: sram@41c00000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x41c00000 0x00 0x100000>;
+ ranges = <0x0 0x00 0x41c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
clock-names = "fclk";
};
- wkup_i2c0: i2c@42120000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x42120000 0x0 0x100>;
- interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 197 0>;
- power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
- };
-
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
clock-names = "fclk";
};
- mcu_r5fss0: r5fss@41000000 {
- compatible = "ti,j721e-r5fss";
- lockstep-mode = <1>;
+ wkup_gpio_intr: interrupt-controller2 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <137>;
+ ti,interrupt-ranges = <16 960 16>;
+ };
+
+ wkup_gpio0: gpio@42110000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x42110000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <84>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 113 0>;
+ clock-names = "gpio";
+ };
+
+ wkup_gpio1: gpio@42100000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x42100000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <84>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "gpio";
+ };
+
+ mcu_i2c0: i2c@40b00000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x40b00000 0x0 0x100>;
+ interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x41000000 0x00 0x41000000 0x20000>,
- <0x41400000 0x00 0x41400000 0x20000>;
- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 194 0>;
+ power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ };
- mcu_r5fss0_core0: r5f@41000000 {
- compatible = "ti,j721e-r5f";
- reg = <0x41000000 0x00008000>,
- <0x41010000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <250>;
- ti,sci-proc-ids = <0x01 0xFF>;
- resets = <&k3_reset 250 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
+ mcu_i2c1: i2c@40b10000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x40b10000 0x0 0x100>;
+ interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 195 0>;
+ power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ };
- mcu_r5fss0_core1: r5f@41400000 {
- compatible = "ti,j721e-r5f";
- reg = <0x41400000 0x00008000>,
- <0x41410000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <251>;
- ti,sci-proc-ids = <0x02 0xFF>;
- resets = <&k3_reset 251 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
- };
+ wkup_i2c0: i2c@42120000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x42120000 0x0 0x100>;
+ interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 197 0>;
+ power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
};
fss: fss@47000000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "simple-bus";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 104 0>;
- assigned-clocks = <&k3_clks 104 0>;
- assigned-clock-rates = <133333333>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
};
- mcu_i2c0: i2c@40b00000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b00000 0x0 0x100>;
- interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 194 0>;
- power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ tscadc0: tscadc@40200000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x0 0x40200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 0 1>;
+ assigned-clocks = <&k3_clks 0 3>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "adc_tsc_fck";
+ dmas = <&main_udmap 0x7400>,
+ <&main_udmap 0x7401>;
+ dma-names = "fifo0", "fifo1";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
};
- mcu_i2c1: i2c@40b10000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b10000 0x0 0x100>;
- interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 195 0>;
- power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ tscadc1: tscadc@40210000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x0 0x40210000 0x0 0x1000>;
+ interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 1 1>;
+ assigned-clocks = <&k3_clks 1 3>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "adc_tsc_fck";
+ dmas = <&main_udmap 0x7402>,
+ <&main_udmap 0x7403>;
+ dma-names = "fifo0", "fifo1";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
};
- mcu_navss {
+ mcu-navss {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
+ msi-parent = <&main_udmass_inta>;
};
mcu_udmap: dma-controller@285c0000 {
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&dmsc>;
};
};
- chipid: chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x0 0x43000014 0x0 0x4>;
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,j721e-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x41000000 0x00008000>,
+ <0x41010000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <250>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 250 1>;
+ firmware-name = "j7-mcu-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x41400000 0x00008000>,
+ <0x41410000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <251>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 251 1>;
+ firmware-name = "j7-mcu-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
};
};
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include "k3-j721e-common-proc-board-u-boot.dtsi"
+
/ {
chosen {
firmware-loader = &fs_loader0;
};
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ remoteproc2 = &main_r5fss0_core0;
+ remoteproc3 = &main_r5fss0_core1;
+ };
+
fs_loader0: fs_loader@0 {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
u-boot,dm-spl;
};
};
-
-#include "k3-j721e-common-proc-board-u-boot.dtsi"
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
alignment = <0x1000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_0_memory_region: c66-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_1_memory_region: c66-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@aa000000 {
+ reg = <0x00 0xaa000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
};
&wkup_pmx0 {
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <8>;
- spi-max-frequency = <50000000>;
+ spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
#size-cells = <1>;
};
};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ interrupts = <428>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster3 {
+ interrupts = <424>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ interrupts = <420>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+ memory-region = <&c66_0_dma_memory_region>,
+ <&c66_0_memory_region>;
+};
+
+&c66_1 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+ memory-region = <&c66_1_dma_memory_region>,
+ <&c66_1_memory_region>;
+};
+
+&c71_0 {
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
/*
* Device Tree Source for J721E SoC Family
*
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/irq.h>
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
- i2c4 = &main_i2c1;
- i2c5 = &main_i2c2;
- i2c6 = &main_i2c3;
- i2c7 = &main_i2c4;
- i2c8 = &main_i2c5;
- i2c9 = &main_i2c6;
- spi0 = &ospi0;
- spi1 = &ospi1;
+ ethernet0 = &cpsw_port1;
};
chosen { };
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
- <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
+ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
+ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
- <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
+ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
+ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
+
/* MCUSS_WKUP Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * Saeed Bishara <saeed@marvell.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- */
-
-/dts-v1/;
-
-#include "kirkwood-db-88f6281.dts"
-
-/ {
- aliases {
- spi0 = &spi0;
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
- reg = <0>;
- spi-max-frequency = <50000000>;
- mode = <0>;
-
- partition@u-boot {
- reg = <0x00000000 0x00c00000>;
- label = "u-boot";
- };
- partition@u-boot-env {
- reg = <0x00c00000 0x00040000>;
- label = "u-boot-env";
- };
- partition@unused {
- reg = <0x00100000 0x00f00000>;
- label = "unused";
- };
- };
-};
-
-&nand {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * Saeed Bishara <saeed@marvell.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- */
-
-/dts-v1/;
-
-#include "kirkwood-db.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Marvell DB-88F6281-BP Development Board";
- compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell DB-{88F6281,88F6282}-BP Development Board Setup
- *
- * Saeed Bishara <saeed@marvell.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file contains the definitions that are common between the 6281
- * and 6282 variants of the Marvell Kirkwood Development Board.
- */
-
-#include "kirkwood.dtsi"
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>; /* 512 MB */
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- aliases {
- ethernet0 = ð0;
- spi0 = &spi0;
- };
-
- ocp@f1000000 {
- pin-controller@10000 {
- pmx_sdio_gpios: pmx-sdio-gpios {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "gpio";
- };
- };
-
- serial@12000 {
- status = "okay";
- };
-
- sata@80000 {
- nr-ports = <2>;
- status = "okay";
- };
-
- ehci@50000 {
- status = "okay";
- };
-
- mvsdio@90000 {
- pinctrl-0 = <&pmx_sdio_gpios>;
- pinctrl-names = "default";
- wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
- };
-};
-
-&nand {
- chip-delay = <25>;
- status = "okay";
-
- partition@0 {
- label = "uboot";
- reg = <0x0 0x100000>;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x100000 0x400000>;
- };
-
- partition@500000 {
- label = "root";
- reg = <0x500000 0x1fb00000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
bus-width = <4>;
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
scfg: scfg@1570000 {
compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x1570000 0x10000>;
*/
#include "meson-g12-common-u-boot.dtsi"
+
+/* SARADC is needed for proper board variant detection */
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
snps,reset-active-low;
};
+/* SARADC is needed for proper board variant detection */
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
&tflash_vdd {
gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
};
#include "beacon-renesom-baseboard.dtsi"
/ {
- model = "Beacon Embedded Works RZ/G2M Development Kit";
- compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
+ model = "Beacon EmbeddedWorks RZ/G2M Development Kit";
+ compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
+
+ aliases {
+ serial0 = &scif2;
+ serial1 = &hscif0;
+ serial2 = &hscif1;
+ serial3 = &scif0;
+ serial4 = &hscif2;
+ serial5 = &scif5;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&versaclock5 1>,
+ <&x302_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2",
+ "dclkin.0", "dclkin.1", "dclkin.2";
+};
+
+/* Reference versaclock instead of audio_clk_a */
+&rcar_sound {
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&versaclock6_bb 4>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
};
resets = <&cpg 905>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774a1";
reg = <0 0xe6060000 0 0x50c>;
};
status = "disabled";
};
+ usb2_clksel: clock-controller@e6590630 {
+ compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
+ "renesas,rcar-gen3-usb2-clock-sel";
+ reg = <0 0xe6590630 0 0x02>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&usb_extal_clk>, <&usb3s0_clk>;
+ clock-names = "ehci_ohci", "hs-usb-if",
+ "usb_extal", "usb_xtal";
+ #clock-cells = <0>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ reset-names = "ehci_ohci", "hs-usb-if";
+ status = "disabled";
+ };
+
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a774a1-usb-dmac",
"renesas,usb-dmac";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a774a1-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
status = "disabled";
};
+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774a1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774a1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cpg {
+ u-boot,dm-pre-reloc;
+};
+
+&extal_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&prr {
+ u-boot,dm-pre-reloc;
+};
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&sdhi0 {
+ /delete-property/ cd-gpios;
+};
+
+&sdhi2 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020, Compass Electronics Group, LLC
+ */
+
+/dts-v1/;
+
+#include "r8a774b1.dtsi"
+#include "beacon-renesom-som.dtsi"
+#include "beacon-renesom-baseboard.dtsi"
+
+/ {
+ model = "Beacon Embedded Works RZ/G2N Development Kit";
+ compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
+
+ aliases {
+ serial0 = &scif2;
+ serial1 = &hscif0;
+ serial2 = &hscif1;
+ serial3 = &scif0;
+ serial4 = &hscif2;
+ serial5 = &scif5;
+ serial6 = &scif4;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 721>,
+ <&versaclock5 1>,
+ <&x302_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+/* Reference versaclock instead of audio_clk_a */
+&rcar_sound {
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&versaclock6_bb 4>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
+};
/*
* Device Tree Source for the r8a774b1 SoC
*
- * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright (C) 2019 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/irq.h>
resets = <&cpg 905>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774b1";
reg = <0 0xe6060000 0 0x50c>;
};
status = "disabled";
};
+ usb2_clksel: clock-controller@e6590630 {
+ compatible = "renesas,r8a774b1-rcar-usb2-clock-sel",
+ "renesas,rcar-gen3-usb2-clock-sel";
+ reg = <0 0xe6590630 0 0x02>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&usb_extal_clk>, <&usb3s0_clk>;
+ clock-names = "ehci_ohci", "hs-usb-if",
+ "usb_extal", "usb_xtal";
+ #clock-cells = <0>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ reset-names = "ehci_ohci", "hs-usb-if";
+ status = "disabled";
+ };
+
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a774b1-usb-dmac",
"renesas,usb-dmac";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a774b1-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sata: sata@ee300000 {
compatible = "renesas,sata-r8a774b1",
"renesas,rcar-gen3-sata";
status = "disabled";
};
+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774b1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774b1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cpg {
+ u-boot,dm-pre-reloc;
+};
+
+&extal_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&prr {
+ u-boot,dm-pre-reloc;
+};
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&sdhi0 {
+ /delete-property/ cd-gpios;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ max-frequency = <208000000>;
+};
+
+&sdhi2 {
+ status = "disabled";
+};
+
+&sdhi3 {
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020, Compass Electronics Group, LLC
+ */
+
+/dts-v1/;
+
+#include "r8a774e1.dtsi"
+#include "beacon-renesom-som.dtsi"
+#include "beacon-renesom-baseboard.dtsi"
+
+/ {
+ model = "Beacon Embedded Works RZ/G2H Development Kit";
+ compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
+
+ aliases {
+ serial0 = &scif2;
+ serial1 = &hscif0;
+ serial2 = &hscif1;
+ serial3 = &scif0;
+ serial4 = &hscif2;
+ serial5 = &scif5;
+ serial6 = &scif4;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 721>,
+ <&versaclock5 1>,
+ <&x302_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+/* Reference versaclock instead of audio_clk_a */
+&rcar_sound {
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&versaclock6_bb 4>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
+};
clock-frequency = <0>;
};
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
cache-unified;
cache-level = <2>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <4000>;
+ };
+
+ CPU_SLEEP_1: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <700>;
+ exit-latency-us = <700>;
+ min-residency-us = <5000>;
+ };
+ };
};
extal_clk: extal {
resets = <&cpg 905>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774e1";
reg = <0 0xe6060000 0 0x50c>;
};
};
hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a774e1",
+ "renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ renesas,buswait = <11>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 704>, <&cpg 703>;
status = "disabled";
+ };
- /* placeholder */
+ usb2_clksel: clock-controller@e6590630 {
+ compatible = "renesas,r8a774e1-rcar-usb2-clock-sel",
+ "renesas,rcar-gen3-usb2-clock-sel";
+ reg = <0 0xe6590630 0 0x02>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&usb_extal_clk>, <&usb3s0_clk>;
+ clock-names = "ehci_ohci", "hs-usb-if",
+ "usb_extal", "usb_xtal";
+ #clock-cells = <0>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ reset-names = "ehci_ohci", "hs-usb-if";
+ status = "disabled";
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a774e1-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a774e1-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
};
usb3_phy0: usb-phy@e65ee000 {
+ compatible = "renesas,r8a774e1-usb3-phy",
+ "renesas,rcar-gen3-usb3-phy";
reg = <0 0xe65ee000 0 0x90>;
+ clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+ <&usb_extal_clk>;
+ clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
#phy-cells = <0>;
status = "disabled";
-
- /* placeholder */
};
dmac0: dma-controller@e6700000 {
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
};
pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
+ };
- /* placeholder */
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
};
scif0: serial@e6e60000 {
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin0>;
+ };
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin1>;
+ };
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin2>;
+ };
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin3>;
+ };
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ renesas,id = <6>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a774e1";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ renesas,id = <7>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi20vin7>;
+ };
+ };
+ };
+ };
+
rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ /*
+ * #clock-cells is required for audio_clkout0/1/2/3
+ *
+ * clkout : #clock-cells = <0>; <&rcar_sound>;
+ * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
status = "disabled";
- /* placeholder */
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = <&audma0 0x35>, <&audma1 0x36>;
+ dma-names = "rx", "tx";
+ };
+ ssiu02: ssiu-2 {
+ dmas = <&audma0 0x37>, <&audma1 0x38>;
+ dma-names = "rx", "tx";
+ };
+ ssiu03: ssiu-3 {
+ dmas = <&audma0 0x47>, <&audma1 0x48>;
+ dma-names = "rx", "tx";
+ };
+ ssiu04: ssiu-4 {
+ dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dma-names = "rx", "tx";
+ };
+ ssiu05: ssiu-5 {
+ dmas = <&audma0 0x43>, <&audma1 0x44>;
+ dma-names = "rx", "tx";
+ };
+ ssiu06: ssiu-6 {
+ dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dma-names = "rx", "tx";
+ };
+ ssiu07: ssiu-7 {
+ dmas = <&audma0 0x53>, <&audma1 0x54>;
+ dma-names = "rx", "tx";
+ };
+ ssiu10: ssiu-8 {
+ dmas = <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu11: ssiu-9 {
+ dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu12: ssiu-10 {
+ dmas = <&audma0 0x57>, <&audma1 0x58>;
+ dma-names = "rx", "tx";
+ };
+ ssiu13: ssiu-11 {
+ dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu14: ssiu-12 {
+ dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dma-names = "rx", "tx";
+ };
+ ssiu15: ssiu-13 {
+ dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu16: ssiu-14 {
+ dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu17: ssiu-15 {
+ dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu20: ssiu-16 {
+ dmas = <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx";
+ };
+ ssiu21: ssiu-17 {
+ dmas = <&audma0 0x67>, <&audma1 0x68>;
+ dma-names = "rx", "tx";
+ };
+ ssiu22: ssiu-18 {
+ dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu23: ssiu-19 {
+ dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu24: ssiu-20 {
+ dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu25: ssiu-21 {
+ dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu26: ssiu-22 {
+ dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu27: ssiu-23 {
+ dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dma-names = "rx", "tx";
+ };
+ ssiu30: ssiu-24 {
+ dmas = <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx";
+ };
+ ssiu31: ssiu-25 {
+ dmas = <&audma0 0x21>, <&audma1 0x22>;
+ dma-names = "rx", "tx";
+ };
+ ssiu32: ssiu-26 {
+ dmas = <&audma0 0x23>, <&audma1 0x24>;
+ dma-names = "rx", "tx";
+ };
+ ssiu33: ssiu-27 {
+ dmas = <&audma0 0x25>, <&audma1 0x26>;
+ dma-names = "rx", "tx";
+ };
+ ssiu34: ssiu-28 {
+ dmas = <&audma0 0x27>, <&audma1 0x28>;
+ dma-names = "rx", "tx";
+ };
+ ssiu35: ssiu-29 {
+ dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu36: ssiu-30 {
+ dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu37: ssiu-31 {
+ dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu40: ssiu-32 {
+ dmas = <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx";
+ };
+ ssiu41: ssiu-33 {
+ dmas = <&audma0 0x17>, <&audma1 0x18>;
+ dma-names = "rx", "tx";
+ };
+ ssiu42: ssiu-34 {
+ dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu43: ssiu-35 {
+ dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu44: ssiu-36 {
+ dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu45: ssiu-37 {
+ dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dma-names = "rx", "tx";
+ };
+ ssiu46: ssiu-38 {
+ dmas = <&audma0 0x31>, <&audma1 0x32>;
+ dma-names = "rx", "tx";
+ };
+ ssiu47: ssiu-39 {
+ dmas = <&audma0 0x33>, <&audma1 0x34>;
+ dma-names = "rx", "tx";
+ };
+ ssiu50: ssiu-40 {
+ dmas = <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx";
+ };
+ ssiu60: ssiu-41 {
+ dmas = <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx";
+ };
+ ssiu70: ssiu-42 {
+ dmas = <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu80: ssiu-43 {
+ dmas = <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx";
+ };
+ ssiu90: ssiu-44 {
+ dmas = <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx";
+ };
+ ssiu91: ssiu-45 {
+ dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dma-names = "rx", "tx";
+ };
+ ssiu92: ssiu-46 {
+ dmas = <&audma0 0x81>, <&audma1 0x82>;
+ dma-names = "rx", "tx";
+ };
+ ssiu93: ssiu-47 {
+ dmas = <&audma0 0x83>, <&audma1 0x84>;
+ dma-names = "rx", "tx";
+ };
+ ssiu94: ssiu-48 {
+ dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu95: ssiu-49 {
+ dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dma-names = "rx", "tx";
+ };
+ ssiu96: ssiu-50 {
+ dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu97: ssiu-51 {
+ dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dma-names = "rx", "tx";
+ };
+ };
rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>;
+ dma-names = "rx", "tx";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>;
+ dma-names = "rx", "tx";
+ };
ssi2: ssi-2 {
- /* placeholder */
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>;
+ dma-names = "rx", "tx";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>;
+ dma-names = "rx", "tx";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>;
+ dma-names = "rx", "tx";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+ dma-names = "rx", "tx";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+ dma-names = "rx", "tx";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>;
+ dma-names = "rx", "tx";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>;
+ dma-names = "rx", "tx";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>;
+ dma-names = "rx", "tx";
};
};
};
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a774e1",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
+ <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
+ <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
+ <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
+ <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
+ <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
+ <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
+ <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a774e1",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
+ <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
+ <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
+ <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
+ <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
+ <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
+ <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
+ <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
+ };
+
xhci0: usb@ee000000 {
+ compatible = "renesas,xhci-r8a774e1",
+ "renesas,rcar-gen3-xhci";
reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
status = "disabled";
-
- /* placeholder */
};
usb3_peri0: usb@ee020000 {
+ compatible = "renesas,r8a774e1-usb3-peri",
+ "renesas,rcar-gen3-usb3-peri";
reg = <0 0xee020000 0 0x400>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
status = "disabled";
-
- /* placeholder */
};
ohci0: usb@ee080000 {
+ compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
-
- /* placeholder */
};
ohci1: usb@ee0a0000 {
+ compatible = "generic-ohci";
reg = <0 0xee0a0000 0 0x100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 702>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
status = "disabled";
-
- /* placeholder */
};
ehci0: usb@ee080100 {
+ compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
-
- /* placeholder */
};
ehci1: usb@ee0a0100 {
+ compatible = "generic-ehci";
reg = <0 0xee0a0100 0 0x100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 702>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
status = "disabled";
-
- /* placeholder */
};
usb2_phy0: usb-phy@ee080200 {
+ compatible = "renesas,usb2-phy-r8a774e1",
+ "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ #phy-cells = <1>;
status = "disabled";
-
- /* placeholder */
};
usb2_phy1: usb-phy@ee0a0200 {
+ compatible = "renesas,usb2-phy-r8a774e1",
+ "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>;
+ clocks = <&cpg CPG_MOD 702>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
+ #phy-cells = <1>;
status = "disabled";
-
- /* placeholder */
};
sdhi0: mmc@ee100000 {
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a774e1-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sata: sata@ee300000 {
+ compatible = "renesas,sata-r8a774e1",
+ "renesas,rcar-gen3-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ iommus = <&ipmmu_hc 2>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
};
pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a774e1",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
status = "disabled";
+ };
- /* placeholder */
+ pciec1: pcie@ee800000 {
+ compatible = "renesas,pcie-r8a774e1",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xee800000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
+ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
+ <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
+ <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
+
+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774e1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774e1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ vspbc: vsp@fe920000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe920000 0 0x8000>;
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 624>;
+
+ renesas,fcp = <&fcpvb1>;
+ };
+
+ vspbd: vsp@fe960000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe960000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 626>;
+
+ renesas,fcp = <&fcpvb0>;
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x5000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x5000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+
+ renesas,fcp = <&fcpvd1>;
+ };
+
+ vspi0: vsp@fe9a0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe9a0000 0 0x8000>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 631>;
+
+ renesas,fcp = <&fcpvi0>;
+ };
+
+ vspi1: vsp@fe9b0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe9b0000 0 0x8000>;
+ interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 630>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 630>;
+
+ renesas,fcp = <&fcpvi1>;
+ };
+
+ fdp1@fe940000 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe940000 0 0x2400>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 119>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 119>;
+ renesas,fcp = <&fcpf0>;
+ };
+
+ fdp1@fe944000 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe944000 0 0x2400>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 118>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 118>;
+ renesas,fcp = <&fcpf1>;
+ };
+
+ fcpf0: fcp@fe950000 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe950000 0 0x200>;
+ clocks = <&cpg CPG_MOD 615>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 615>;
+ };
+
+ fcpf1: fcp@fe951000 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe951000 0 0x200>;
+ clocks = <&cpg CPG_MOD 614>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 614>;
+ };
+
+ fcpvb0: fcp@fe96f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 607>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 607>;
+ };
+
+ fcpvb1: fcp@fe92f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe92f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 606>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 606>;
+ };
+
+ fcpvi0: fcp@fe9af000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9af000 0 0x200>;
+ clocks = <&cpg CPG_MOD 611>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 611>;
+ };
+
+ fcpvi1: fcp@fe9bf000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9bf000 0 0x200>;
+ clocks = <&cpg CPG_MOD 610>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 610>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ };
+
+ csi20: csi2@fea80000 {
+ compatible = "renesas,r8a774e1-csi2";
+ reg = <0 0xfea80000 0 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi20vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi20>;
+ };
+ csi20vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi20>;
+ };
+ csi20vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi20>;
+ };
+ csi20vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi20>;
+ };
+ csi20vin4: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi20>;
+ };
+ csi20vin5: endpoint@5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi20>;
+ };
+ csi20vin6: endpoint@6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi20>;
+ };
+ csi20vin7: endpoint@7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi20>;
+ };
+ };
+ };
+ };
+
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a774e1-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
};
hdmi0: hdmi@fead0000 {
+ compatible = "renesas,r8a774e1-hdmi",
+ "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 729>,
+ <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 729>;
status = "disabled";
- /* placeholder */
-
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
};
port@1 {
reg = <1>;
};
port@2 {
+ /* HDMI sound */
reg = <2>;
};
};
};
du: display@feb00000 {
+ compatible = "renesas,du-r8a774e1";
reg = <0 0xfeb00000 0 0x80000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 721>;
+ clock-names = "du.0", "du.1", "du.3";
+ resets = <&cpg 724>, <&cpg 722>;
+ reset-names = "du.0", "du.3";
status = "disabled";
- /* placeholder */
+ renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
+ du_out_rgb: endpoint {
+ };
};
port@1 {
reg = <1>;
+ du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
+ };
};
port@2 {
reg = <2>;
+ du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a774e1-lvds";
+ reg = <0 0xfeb90000 0 0x14>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
};
};
};
pinctrl_flx3_default: flx3_default {
pinmux = <PIN_PD16__FLEXCOM3_IO0>,
<PIN_PD17__FLEXCOM3_IO1>;
- bias-disable;
+ bias-pull-up;
};
pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default {
* Save Date: 2020.02.20, save Time: 18:45:20
*/
#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz
-#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
+#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
* Save Date: 2020.02.20, save Time: 18:49:33
*/
#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz
-#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz"
+#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
};
};
+ fmc_pins_b: fmc-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
+ <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
+ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
+ <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
+ <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
+ <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
+ <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
+ <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
+ <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
+ <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
+ <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
+ <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
+ <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ fmc_sleep_pins_b: fmc-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
+ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
+ <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
+ <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
+ <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
+ <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
+ <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
};
};
+ sdmmc2_d47_pins_d: sdmmc2-d47-3 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
};
stusb1600_pins_a: stusb1600-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
- bias-pull-up;
+ pins {
+ pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
+ bias-pull-up;
};
};
};
};
+ uart8_rtscts_pins_a: uart8rtscts-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
+ <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
+ bias-disable;
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
resets = <&rcc UART8_R>;
};
-&usbotg_hs {
- compatible = "st,stm32mp1-hsotg", "snps,dwc2";
-};
};
};
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x40009000 0x400>;
+ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
+ wakeup-source;
status = "disabled";
pwm {
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
- reg = <0x48002000 0x1c>;
+ reg = <0x48002000 0x40>;
#dma-cells = <3>;
dma-requests = <128>;
dma-masters = <&dma1 &dma2>;
sdmmc3: sdmmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
+ arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- g-rx-fifo-size = <256>;
+ g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
usb33d-supply = <&usb33>;
status = "disabled";
resets = <&rcc CAMITF_R>;
clocks = <&rcc DCMI>;
clock-names = "mclk";
- dmas = <&dmamux1 75 0x400 0x0d>;
+ dmas = <&dmamux1 75 0x400 0x01>;
dma-names = "tx";
status = "disabled";
};
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50021000 0x400>;
+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
+ wakeup-source;
status = "disabled";
pwm {
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50022000 0x400>;
+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
+ wakeup-source;
status = "disabled";
pwm {
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
+ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
+ wakeup-source;
status = "disabled";
pwm {
lptimer5: timer@50024000 {
compatible = "st,stm32-lptimer";
reg = <0x50024000 0x400>;
+ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
+ wakeup-source;
status = "disabled";
pwm {
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
- dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
status = "disabled";
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
- <&mdma1 22 0x10 0x100008 0x0 0x0>;
+ dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
+ <&mdma1 22 0x2 0x100008 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
sdmmc1: sdmmc@58005000 {
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
+ arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
sdmmc2: sdmmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
+ arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
status = "disabled";
};
- usbh_ohci: usbh-ohci@5800c000 {
+ usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&rcc USBH>;
status = "disabled";
};
- usbh_ehci: usbh-ehci@5800d000 {
+ usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>;
status = "disabled";
};
+ tamp: tamp@5c00a000 {
+ compatible = "st,stm32-tamp", "syscon", "simple-mfd";
+ reg = <0x5c00a000 0x400>;
+ };
+
/*
* Break node order to solve dependency probe issue between
* pinctrl and exti.
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
+ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
+ st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
status = "disabled";
};
};
};
};
+ arm-pmu {
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";
};
};
+&cryp1 {
+ status = "okay";
+};
+
&dsi {
status = "okay";
phy-dsi-supply = <®18>;
states = <1800000 0x1>,
<2900000 0x0>;
};
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
};
&adc {
cpu-supply = <&vddcore>;
};
+&crc1 {
+ status = "okay";
+};
+
+&cryp1 {
+ status = "okay";
+};
+
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
contiguous-area = <&gpu_reserved>;
};
+&hash1 {
+ status = "okay";
+};
+
&i2c4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_pins_a>;
regulators {
compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin>;
+ buck2-supply = <&vin>;
+ buck3-supply = <&vin>;
+ buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
+ ldo4-supply = <&vin>;
ldo5-supply = <&v3v3>;
ldo6-supply = <&v3v3>;
+ vref_ddr-supply = <&vin>;
+ boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
+ bus-type = <5>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
- fmc_pins_b: fmc-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
- <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
- <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
- <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
- <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
- <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
- <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
- <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
- <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
- <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
- <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
- <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- fmc_sleep_pins_b: fmc-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
- <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
- <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
- <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
- <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
- <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
- <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
- <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
- };
- };
-
mco2_pins_a: mco2-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
dais = <&sai2a_port &sai2b_port &i2s2_port>;
status = "okay";
};
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
};
&adc {
status = "okay";
};
+&crc1 {
+ status = "okay";
+};
+
&dts {
status = "okay";
};
contiguous-area = <&gpu_reserved>;
};
+&hash1 {
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
- typec: stusb1600@28 {
+ stusb1600@28 {
compatible = "st,stusb1600";
reg = <0x28>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpioi>;
pinctrl-names = "default";
pinctrl-0 = <&stusb1600_pins_a>;
-
status = "okay";
+ vdd-supply = <&vin>;
- typec_con: connector {
+ connector {
compatible = "usb-c-connector";
label = "USB-C";
- power-role = "sink";
- power-opmode = "default";
+ power-role = "dual";
+ typec-power-opmode = "default";
+
+ port {
+ con_usbotg_hs_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
};
};
regulators {
compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin>;
+ buck2-supply = <&vin>;
+ buck3-supply = <&vin>;
+ buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
+ ldo2-supply = <&vin>;
ldo3-supply = <&vdd_ddr>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&vin>;
ldo6-supply = <&v3v3>;
+ vref_ddr-supply = <&vin>;
+ boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
+
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usbotg_hs_ep>;
+ };
+ };
};
&usbphyc {
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define TZPC_BASE 0x02200000
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
-#if !defined(CONFIG_DM_I2C)
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
u8 res5[0x19fc - 0xa00];
};
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+ u32 gpibe;
+};
+
#endif /*__ASSEMBLY__ */
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
#include <asm/arch/immap_lsch3.h>
#endif
#endif
+#include <asm/arch/svr.h>
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
#define gur_in32(a) in_le32(a)
#endif
#endif
#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1012A 0x870400
-#define SVR_LS1043A 0x879200
-#define SVR_LS1023A 0x879208
-/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
-#define SVR_LS1043A_P23 0x879202
-#define SVR_LS1023A_P23 0x87920A
-#define SVR_LS1017A 0x870B24
-#define SVR_LS1018A 0x870B20
-#define SVR_LS1027A 0x870B04
-#define SVR_LS1028A 0x870B00
-#define SVR_LS1046A 0x870700
-#define SVR_LS1026A 0x870708
-#define SVR_LS1048A 0x870320
-#define SVR_LS1084A 0x870302
-#define SVR_LS1088A 0x870300
-#define SVR_LS1044A 0x870322
-#define SVR_LS2045A 0x870120
-#define SVR_LS2080A 0x870110
-#define SVR_LS2085A 0x870100
-#define SVR_LS2040A 0x870130
-#define SVR_LS2088A 0x870900
-#define SVR_LS2084A 0x870910
-#define SVR_LS2048A 0x870920
-#define SVR_LS2044A 0x870930
-#define SVR_LS2081A 0x870918
-#define SVR_LS2041A 0x870914
-#define SVR_LX2160A 0x873600
-#define SVR_LX2120A 0x873620
-#define SVR_LX2080A 0x873602
-#define SVR_LX2162A 0x873608
-#define SVR_LX2122A 0x873628
-#define SVR_LX2082A 0x87360A
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
-#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
+#define SVR_WO_CE 0xFFFFEE
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE)
+#else
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#endif
#ifdef CONFIG_ARCH_LS1028A
#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2015-2020 NXP
+ * Copyright 2015-2021 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*
*/
#define FSL_DPAA2_STREAM_ID_END 63
/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */
-#define FSL_ECAM_STREAM_ID_START 32
+#define FSL_ECAM_STREAM_ID_START 41
#define FSL_ECAM_STREAM_ID_END 63
#define FSL_SEC_STREAM_ID 64
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_
+
+#define SVR_LS1012A 0x870400
+#define SVR_LS1043A 0x879200
+#define SVR_LS1023A 0x879208
+/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
+#define SVR_LS1043A_P23 0x879202
+#define SVR_LS1023A_P23 0x87920A
+#define SVR_LS1017A 0x870B24
+#define SVR_LS1018A 0x870B20
+#define SVR_LS1027A 0x870B04
+#define SVR_LS1028A 0x870B00
+#define SVR_LS1046A 0x870700
+#define SVR_LS1026A 0x870708
+#define SVR_LS1048A 0x870320
+#define SVR_LS1084A 0x870302
+#define SVR_LS1088A 0x870300
+#define SVR_LS1044A 0x870322
+#define SVR_LS2045A 0x870120
+#define SVR_LS2080A 0x870110
+#define SVR_LS2085A 0x870100
+#define SVR_LS2040A 0x870130
+#define SVR_LS2088A 0x870900
+#define SVR_LS2084A 0x870910
+#define SVR_LS2048A 0x870920
+#define SVR_LS2044A 0x870930
+#define SVR_LS2081A 0x870918
+#define SVR_LS2041A 0x870914
+#define SVR_LX2160A 0x873600
+#define SVR_LX2120A 0x873620
+#define SVR_LX2080A 0x873602
+#define SVR_LX2162A 0x873608
+#define SVR_LX2122A 0x873628
+#define SVR_LX2082A 0x87360A
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */
u32 stxfl;
};
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
enum {
I2C_0, I2C_1, I2C_2,
};
#ifndef __ASM_ARCH_LS102XA_GPIO_H_
#define __ASM_ARCH_LS102XA_GPIO_H_
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+ u32 gpibe;
+};
+
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ ulong size;
+ uint ngpios;
+};
+
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef _ASM_LS102X_SVR_H_
+#define _ASM_LS102X_SVR_H_
+
+#define SVR_LS102XA 0
+#define SVR_VAR_PER_SHIFT 8
+#define SVR_LS102XA_MASK 0x700
+
+#endif /* _ASM_LS102X_SVR_H_ */
#ifndef _ASM_ARCH_CLOCK_H
#define _ASM_ARCH_CLOCK_H
+struct udevice;
+
/* define pll mode */
#define RKCLK_PLL_MODE_SLOW 0
#define RKCLK_PLL_MODE_NORMAL 1
#define SUN5I_GPG_SDC1 2
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
+#define SUN8I_GPG_UART1 2
#define SUN6I_GPG_TWI3 2
#define SUN5I_GPG_UART1 4
#ifndef _TEGRA_CLOCK_H_
#define _TEGRA_CLOCK_H_
+struct udevice;
+
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
/* All in MHz, so 13_0 is 13.0MHz */
#include <asm/types.h>
+struct udevice;
+
enum {
I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#include <asm/types.h>
+#include <linux/types.h>
+
/* Architecture-specific global data */
struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
#if CONFIG_IS_ENABLED(CLK)
struct clk per_clk;
#endif
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
int (*idle_bus_fn)(void *p);
void *idle_bus_data;
#else
#ifndef _OMAP_I2C_H
#define _OMAP_I2C_H
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
/* Information about a GPIO bank */
struct omap_i2c_plat {
#define __ASM_SECURE_H
#include <config.h>
+#include <asm/global_data.h>
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
#ifndef _TI_COMMON_SYS_PROTO_H_
#define _TI_COMMON_SYS_PROTO_H_
+#include <asm/global_data.h>
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ARCH_OMAP2PLUS
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
{
struct bd_info *bd = gd->bd;
- bdinfo_print_num("arch_number", bd->bi_arch_number);
+ bdinfo_print_num_l("arch_number", bd->bi_arch_number);
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
- bdinfo_print_num("Secure ram",
- gd->arch.secure_ram &
- MEM_RESERVE_SECURE_ADDR_MASK);
+ bdinfo_print_num_ll("Secure ram",
+ gd->arch.secure_ram &
+ MEM_RESERVE_SECURE_ADDR_MASK);
}
#endif
#ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram)
- bdinfo_print_num("Reserved ram", gd->arch.resv_ram);
+ bdinfo_print_num_ll("Reserved ram", gd->arch.resv_ram);
#endif
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
- bdinfo_print_num("TLB addr", gd->arch.tlb_addr);
+ bdinfo_print_num_l("TLB addr", gd->arch.tlb_addr);
#endif
- bdinfo_print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
- bdinfo_print_num("sp start ", gd->start_addr_sp);
+ bdinfo_print_num_l("irq_sp", gd->irq_sp); /* irq stack pointer */
+ bdinfo_print_num_l("sp start ", gd->start_addr_sp);
/*
* TODO: Currently only support for davinci SOC's is added.
* Remove this check once all the board implement this.
#ifdef CONFIG_ARMV7_NONSEC
#include <asm/armv7.h>
#endif
+#include <asm/global_data.h>
#include <asm/psci.h>
#include <asm/spin_table.h>
#include <hang.h>
#include <lmb.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/root.h>
#include <env.h>
#include <image.h>
* This may be useful for last-stage operations, like cancelling
* of DMA operation or releasing device internal buffers.
*/
+ dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
+
+ /* Remove all active vital devices next */
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
cleanup_before_linux();
#include <common.h>
#include <cpu_func.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/cache.h>
#include <linux/compiler.h>
#include <log.h>
#include <malloc.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <image.h>
#include <mapmem.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/sizes.h>
#include <cpu_func.h>
#include <efi_loader.h>
#include <irq_func.h>
+#include <asm/global_data.h>
#include <asm/proc-armv/ptrace.h>
#include <asm/ptrace.h>
#include <asm/u-boot-arm.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <irq_func.h>
#include <linux/compiler.h>
#include <spl.h>
#include <image.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mach-types.h>
*/
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <log.h>
#include <ram.h>
#include <timer.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
#include <asm/arch/wdt.h>
#include <linux/err.h>
#include <dm/uclass.h>
#include <asm/arch/scu_ast2600.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <asm/io.h>
#include <asm/arch/scu_ast2600.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/io.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pit.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pit.h>
#include <hang.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91sam9_matrix.h>
#include <init.h>
#include <dm/device.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL
#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
#include <common.h>
#include <init.h>
#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#include <log.h>
#include <net.h>
#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/timer_defs.h>
#include <div64.h>
#include <config.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/cache.h>
#include <asm/arch/clock.h>
if (ret)
goto err_idle;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
bus_i2c_init(i2c_index, speed, slave_addr, force_idle_bus, p);
#endif
#include <command.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sci/sci.h>
#include <asm/mach-imx/sys_proto.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/arch/clock.h>
#include <init.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass.h>
#include <log.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <dm/ofnode.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch-imx8/imx8-pins.h>
#include <asm/arch-imx8/snvs_security_sc.h>
+#include <asm/global_data.h>
/* Access to gd */
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <div64.h>
#include <errno.h>
#include <init.h>
#include <log.h>
#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <lmb.h>
#include <log.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <env.h>
#include <command.h>
#include <div64.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <clock_legacy.h>
#include <command.h>
#include <div64.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/arch/clock.h>
prompt "MX28 board select"
optional
-config TARGET_APX4DEVKIT
- bool "Support apx4devkit"
-
config TARGET_BG0900
bool "Support bg0900"
config SYS_SOC
default "mxs"
-source "board/bluegiga/apx4devkit/Kconfig"
source "board/freescale/mx28evk/Kconfig"
source "board/liebherr/xea/Kconfig"
source "board/ppcag/bg0900/Kconfig"
#include <clock_legacy.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#include <hang.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/boot_mode.h>
#include <g_dnl.h>
+#include <linux/libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
return size;
}
-void board_spl_fit_post_load(ulong load_addr, size_t length)
+void board_spl_fit_post_load(const void *fit)
{
- u32 offset = length - CONFIG_CSF_SIZE;
+ u32 offset = ALIGN(fdt_totalsize(fit), 0x1000);
- if (imx_hab_authenticate_image(load_addr,
+ if (imx_hab_authenticate_image((uintptr_t)fit,
offset + IVT_SIZE + CSF_PAD_SIZE,
offset)) {
panic("spl: ERROR: image authentication unsuccessful\n");
#include <errno.h>
#include <image.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <spl.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <time.h>
#include <asm/io.h>
#include <div64.h>
+#include <asm/global_data.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <fdt_support.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/hardware.h>
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include "common.h"
#include <dm.h>
#include <remoteproc.h>
#include <malloc.h>
#include <remoteproc.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <g_dnl.h>
#include <usb.h>
static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
{
int ret;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
int old_bus;
i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
config TARGET_SBx81LIFXCAT
bool "Allied Telesis SBx81GP24/SBx81GT24"
-config TARGET_DB_88F6281_BP
- bool "Marvell DB-88F6281-BP"
-
endchoice
config SYS_SOC
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
-source "board/Marvell/db-88f6281-bp/Kconfig"
endif
/*
* I2C related stuff
*/
-#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
+#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
#ifndef CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/arch/misc.h>
#include <log.h>
#include <ram.h>
#include <asm/arch/misc.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <linux/bitops.h>
#include <asm/arch/misc.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8512-clk.h>
#include <asm/arch/misc.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8516-clk.h>
#include <asm/arch/misc.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8518-clk.h>
select SYSCON
select REGMAP
select PWRSEQ
+ select MMC_PWRSEQ
select BOARD_LATE_INIT
imply CMD_DM
#include <asm/arch/eth.h>
#include <asm/arch/axg.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <asm/arch/boot.h>
#include <env.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <asm/arch/g12a.h>
#include <asm/arch/mem.h>
#include <asm/arch/meson-vpu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <asm/arch/gx.h>
#include <asm/arch/mem.h>
#include <asm/arch/meson-vpu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <linux/bitfield.h>
#include <log.h>
#include <asm/arch/sm.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <fdtdec.h>
#include <init.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/libfdt.h>
#include <linux/sizes.h>
#include <dm.h>
#include <fdtdec.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <asm/io.h>
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <linux/sizes.h>
#include <config.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <errno.h>
#include <image.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_CLI_FRAMEWORK)
#include <common.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/board.h>
#include <common.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/board.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
# endif
};
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static const struct omap_i2c_plat am33xx_i2c[] = {
{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
/* Enable Bye read */
addr = addr | CLK_SYNTHESIZER_BYTE_MODE;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/* Send the command byte */
rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
if (rc)
cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE;
cmd[1] = val;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2);
#else
rc = dm_i2c_write(dev, addr, cmd, 2);
int rc;
u8 val = 0;
struct udevice *dev = NULL;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR);
if (rc) {
printf("i2c probe failed at address 0x%x\n",
#include <ahci.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/omap_common.h>
#include <asm/arch/omap.h>
#include <asm/arch/mmc_host_def.h>
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
-#if defined(CONFIG_SPL_I2C_SUPPORT) && !defined(CONFIG_DM_I2C)
+#if defined(CONFIG_SPL_I2C_SUPPORT) && !CONFIG_IS_ENABLED(DM_I2C)
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
enable_basic_uboot_clocks();
}
-#if !defined(CONFIG_DM_I2C)
+#if !CONFIG_IS_ENABLED(DM_I2C)
void gpi2c_init(void)
{
static int gpi2c = 1;
#include <init.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <log.h>
+#include <dm/device.h>
#include <asm/io.h>
#include <asm/arch/am35x_def.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <config.h>
#include <init.h>
#include <asm/arch/cpu.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/arm-smccc.h>
#include <linux/psci.h>
#include <common.h>
prompt "Renesas ARM64 SoCs board select"
optional
+config TARGET_BEACON_RZG2H
+ bool "Beacon EmbeddedWorks RZ/G2H Dev Kit"
+ select R8A774E1
+ select PINCTRL_PFC_R8A774E1
+
config TARGET_BEACON_RZG2M
bool "Beacon EmbeddedWorks RZ/G2M Dev Kit"
select R8A774A1
select PINCTRL_PFC_R8A774A1
+config TARGET_BEACON_RZG2N
+ bool "Beacon EmbeddedWorks RZ/G2N Dev Kit"
+ select R8A774B1
+ select PINCTRL_PFC_R8A774B1
+
config TARGET_CONDOR
bool "Condor board"
imply R8A77980
#include <common.h>
#include <cpu_func.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
#define GEN3_NR_REGIONS 16
#include <ram.h>
#include <syscon.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/clock.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/grf_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
*/
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <led.h>
#include <log.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <init.h>
#include <malloc.h>
#include <asm/armv7.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <common.h>
#include <init.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/arch-rockchip/uart.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <spl_gpio.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <init.h>
#include <log.h>
#include <ram.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/sdram.h>
#include <dm/uclass-internal.h>
int dram_init_banksize(void)
{
size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
- gd->ram_top);
+ (unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64
/* Reserve 0x200000 for ATF bl31 */
#include <log.h>
#include <mmc.h>
#include <spl.h>
+#include <asm/global_data.h>
#if CONFIG_IS_ENABLED(OF_LIBFDT)
/**
#include <ram.h>
#include <spl.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#ifndef _PINCTRL_SNAPDRAGON_H
#define _PINCTRL_SNAPDRAGON_H
-#include <common.h>
+struct udevice;
struct msm_pinctrl_data {
int pin_count;
#include <asm/arch/reset_manager.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/misc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <log.h>
#include <usb.h>
#include <command.h>
#include <init.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
#include <malloc.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dt-bindings/clock/agilex-clock.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/handoff_s10.h>
#include <common.h>
#include <hang.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/system_manager.h>
#include <hang.h>
#include <asm/cache.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <fdtdec.h>
#include <common.h>
#include <cpu_func.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <env.h>
#include <errno.h>
#include <errno.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/misc.h>
#include <common.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
* Copyright (C) 2016-2017 Intel Corporation
*/
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/misc.h>
#include <common.h>
#include <hang.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/smc_api.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/pl310.h>
#include <asm/u-boot.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <hang.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <hang.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/system_manager.h>
#include <common.h>
#include <log.h>
+#include <linux/libfdt.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <mmc.h>
#include <part.h>
#include <asm/arch/stm32mp1_smc.h>
+#include <asm/global_data.h>
#include <dm/uclass.h>
#include <jffs2/load_kernel.h>
#include <linux/list.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
#include <linux/delay.h>
+#include <asm/global_data.h>
#include "stm32prog.h"
/* - configuration part -----------------------------*/
#include <asm/arch/bsec.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <linux/bitops.h>
#include <lmb.h>
#include <log.h>
#include <ram.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#define LOG_CATEGORY LOGC_ARCH
#include <common.h>
+#include <fdtdec.h>
#include <fdt_support.h>
#include <log.h>
#include <tee.h>
#include <log.h>
#include <spl.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <linux/libfdt.h>
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
+ !defined(CONFIG_MACH_SUN8I_R40)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
+ sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
clock_init();
timer_init();
gpio_init();
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_init_board();
#endif
eth_init_board();
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* this seems to enable PLLs on H616 */
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
+ setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
+
clock_set_pll1(408000000);
writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
#include <ns16550.h>
#include <spl.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
#include <log.h>
#include <ns16550.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <net.h>
#include <stdlib.h>
#include <string.h>
+#include <asm/global_data.h>
#include <linux/ctype.h>
#include <linux/sizes.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include "emc.h"
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <common.h>
#include <cpu_func.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/arm-smccc.h>
#include <dm/of_access.h>
#include <dm/ofnode.h>
#include <linux/delay.h>
+#include <asm/global_data.h>
#include "../xusb-padctl-common.h"
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/clock.h>
#include <common.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/of_access.h>
#include <dm/ofnode.h>
#include <linux/delay.h>
#include <env.h>
#include <init.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <stdio.h>
#include <linux/printk.h>
#include <common.h>
#include <init.h>
#include <time.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <init.h>
#include <malloc.h>
#include <asm/arch/clk.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <time.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/armv7_mpu.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/sys_proto.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <zynqmp_firmware.h>
#include <asm/cache.h>
#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/immap.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <netdev.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/immap.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/immap.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
#include <irq_func.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/timer.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
#if defined(CONFIG_SYS_MBAR)
- bdinfo_print_num("mbar", bd->bi_mbar_base);
+ bdinfo_print_num_l("mbar", bd->bi_mbar_base);
#endif
bdinfo_print_mhz("cpufreq", bd->bi_intfreq);
if (IS_ENABLED(CONFIG_PCI))
#include <image.h>
#include <lmb.h>
#include <log.h>
+#include <asm/global_data.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
#include <watchdog.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <init.h>
#include <irq_func.h>
#include <time.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/timer.h>
#include <irq_func.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
#include <init.h>
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/microblaze_timer.h>
#include <asm/microblaze_intc.h>
#include <linux/delay.h>
#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
#include <asm/cpu-features.h>
+#include <asm/global_data.h>
#include <asm/pgtable-bits.h>
#include <asm/processor.h>
#include <asm/string.h>
#include <common.h>
#include <command.h>
#include <cpu_func.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <lmb.h>
#include <log.h>
#include <asm/addrspace.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/cache.h>
#include <asm/cacheops.h>
#include <asm/cm.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <common.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <cpu_func.h>
#include <hang.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <clock_legacy.h>
#include <command.h>
#include <hang.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <init.h>
#include <asm/io.h>
#include <asm/addrspace.h>
+#include <asm/global_data.h>
#include <asm/types.h>
#include <mach/ath79.h>
#include <mach/ar71xx_regs.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/addrspace.h>
#include <mach/ddr.h>
#ifndef __ASM_MACH_ATH79_H
#define __ASM_MACH_ATH79_H
+#include <asm/global_data.h>
#include <linux/types.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <common.h>
#include <clock_legacy.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <log.h>
#include <ram.h>
#include <dm.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <hang.h>
#include <image.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/sections.h>
#include <mach/jz4780.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/types.h>
#include <init.h>
#include <malloc.h>
#include <asm/addrspace.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <mach/mc.h>
#include <common.h>
#include <asm/addrspace.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/sizes.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt7628-clk.h>
#include <linux/io.h>
*/
#include <common.h>
-#include <fdt.h>
#include <init.h>
#include <spl.h>
#include <asm/sections.h>
+#include <linux/libfdt.h>
#include <linux/sizes.h>
#include <mach/serial.h>
#include <dm.h>
#include <elf.h>
#include <env.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/compat.h>
#include <dm.h>
#include <init.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <mach/pic32.h>
#include <mach/ddr.h>
#include <dt-bindings/clock/microchip,clock.h>
#include <hang.h>
#include <image.h>
#include <log.h>
+#include <asm/global_data.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <asm/bootm.h>
#include <init.h>
#include <irq_func.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef __ASM_NIOS2_IO_H_
#define __ASM_NIOS2_IO_H_
+#include <asm/global_data.h>
+
static inline void sync(void)
{
__asm__ __volatile__ ("sync" : : : "memory");
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
#include <asm-generic/io.h>
+#include <asm/global_data.h>
#endif /* __ASM_NIOS2_IO_H_ */
#include <common.h>
#include <cpu_func.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <watchdog.h>
#include <command.h>
#include <mpc83xx.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <asm-offsets.h>
#include <mpc83xx.h>
#include <ioports.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <fsl_qe.h>
#include <common.h>
#include <clock_legacy.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <command.h>
#include <irq_func.h>
#include <mpc83xx.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <init.h>
#include <pci.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#if defined(CONFIG_OF_LIBFDT)
#include <common.h>
#include <pci.h>
#include <mpc83xx.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#include <mpc83xx.h>
#include <command.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#include <clock_legacy.h>
#include <mpc83xx.h>
#include <time.h>
+#include <asm/global_data.h>
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <command.h>
#include <kgdb.h>
bool "Support MPC8541CDS"
select ARCH_MPC8541
-config TARGET_MPC8544DS
- bool "Support MPC8544DS"
- select ARCH_MPC8544
- imply PANIC_HANG
-
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
bool "Support MPC8569MDS"
select ARCH_MPC8569
-config TARGET_MPC8572DS
- bool "Support MPC8572DS"
- select ARCH_MPC8572
-# Use DDR3 controller with DDR2 DIMMs on this board
- select SYS_FSL_DDRC_GEN3
- imply SCSI
- imply PANIC_HANG
-
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
bool "Support kmp204x"
select VENDOR_KM
+config TARGET_KMCENT2
+ bool "Support kmcent2"
+ select VENDOR_KM
+
config TARGET_XPEDITE520X
bool "Support xpedite520x"
select ARCH_MPC8548
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
-source "board/freescale/mpc8544ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
-source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
#include <common.h>
#include <asm-offsets.h>
#include <asm/cpm_85xx.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <command.h>
#include <fsl_esdhc.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <fsl_ifc.h>
#include <common.h>
#include <asm-offsets.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <env.h>
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <cpu_func.h>
#include <env.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <env.h>
#include <ioports.h>
#include <common.h>
#include <asm/cpm_85xx.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <cpu_func.h>
#include <ppc_asm.tmpl>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <common.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#ifdef CONFIG_ADDR_MAP
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <command.h>
#include <init.h>
select ARCH_MPC8641
select BOARD_EARLY_INIT_F
-config TARGET_MPC8610HPCD
- bool "Support MPC8610HPCD"
- select ARCH_MPC8610
- select BOARD_EARLY_INIT_F
-
-config TARGET_MPC8641HPCN
- bool "Support MPC8641HPCN"
- select ARCH_MPC8641
- select FSL_DDR_INTERACTIVE
- imply SCSI
-
config TARGET_XPEDITE517X
bool "Support xpedite517x"
select ARCH_MPC8641
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
-source "board/freescale/mpc8610hpcd/Kconfig"
-source "board/freescale/mpc8641hpcn/Kconfig"
source "board/sbc8641d/Kconfig"
source "board/xes/xpedite517x/Kconfig"
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <mpc86xx.h>
#include <asm/fsl_law.h>
#include <common.h>
#include <init.h>
#include <mpc86xx.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/mp.h>
#include <common.h>
#include <cpu_func.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <ioports.h>
#include <common.h>
#include <clock_legacy.h>
#include <mpc86xx.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/io.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <command.h>
#include <init.h>
#include <netdev.h>
#include <asm/cache.h>
#include <asm/cpm_8xx.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <common.h>
#include <time.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <common.h>
#include <command.h>
+#include <asm/global_data.h>
#include <asm/immap_8xx.h>
#include <asm/cpm_8xx.h>
#include <common.h>
#include <clock_legacy.h>
#include <mpc8xx.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <fm_eth.h>
#include <netdev.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <vsc9953.h>
return -1;
sizebit = __ilog2_roundup_64(size);
- size = 1 << sizebit;
+ size = 1ull << sizebit;
debug("min start_addr is %llx\n", min_addr);
debug("max end_addr is %llx\n", max_addr);
debug("size found is %llx\n", size);
#include <common.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/io.h>
#include <common.h>
#include <log.h>
#include <asm/fsl_pamu.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb
dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
+dtb-$(CONFIG_TARGET_MPC837XERDB) += mpc8379erdb.dtb
dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma0: dma@100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elo3-dma";
+ reg = <0x100300 0x4>,
+ <0x100600 0x4>;
+ ranges = <0x0 0x100100 0x500>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ interrupts = <31 2 0 0>;
+ };
+ dma-channel@300 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x300 0x80>;
+ interrupts = <76 2 0 0>;
+ };
+ dma-channel@380 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x380 0x80>;
+ interrupts = <77 2 0 0>;
+ };
+ dma-channel@400 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x400 0x80>;
+ interrupts = <78 2 0 0>;
+ };
+ dma-channel@480 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x480 0x80>;
+ interrupts = <79 2 0 0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma1: dma@101300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elo3-dma";
+ reg = <0x101300 0x4>,
+ <0x101600 0x4>;
+ ranges = <0x0 0x101100 0x500>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ interrupts = <32 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ interrupts = <33 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ interrupts = <34 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ interrupts = <35 2 0 0>;
+ };
+ dma-channel@300 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x300 0x80>;
+ interrupts = <80 2 0 0>;
+ };
+ dma-channel@380 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x380 0x80>;
+ interrupts = <81 2 0 0>;
+ };
+ dma-channel@400 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x400 0x80>;
+ interrupts = <82 2 0 0>;
+ };
+ dma-channel@480 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x480 0x80>;
+ interrupts = <83 2 0 0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2021 Niel Fourie <lusus@denx.de>
+ */
+
+#include <config.h>
+
+/ {
+
+ aliases {
+ spi0 = "/soc@ffe000000/spi@110000";
+ i2c0 = "/soc@ffe000000/i2c@118000";
+ i2c1 = "/soc@ffe000000/i2c@118000/mux@70/i2c@0";
+ i2c2 = "/soc@ffe000000/i2c@118000/mux@70/i2c@1";
+ i2c3 = "/soc@ffe000000/i2c@118000/mux@70/i2c@7";
+ i2c4 = "/soc@ffe000000/i2c@118100";
+ /delete-property/ pci1;
+ /delete-property/ pci2;
+ /delete-property/ pci3;
+ };
+
+ chosen {
+ stdout-path = "/soc@ffe000000/serial@11c500";
+ };
+
+ soc@ffe000000 {
+ u-boot,dm-pre-reloc;
+ spi@110000 {
+ /* This documents where km_fpgacfg should be appear */
+ fpga@0 {
+ compatible = "keymile,fpga-conf";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ sdhc@114000 {
+ status = "okay";
+ };
+
+ i2c@118000 {
+ u-boot,dm-pre-reloc;
+ mux@70 {
+ i2c@1 { /* IVM bus */
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ serial@11c500 {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <200000000>;
+ };
+
+ fman@400000 {
+ ethernet@e0000 {
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e8000 {
+ phy-connection-type = "rgmii-id";
+ };
+ };
+
+ };
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t104x";
+ law_trgt_if = <0>;
+ };
+
+ binman {
+ filename = "u-boot-with-dtb.bin";
+ skip-at-start = <CONFIG_SYS_TEXT_BASE>;
+ sort-by-offset;
+ pad-byte = <0xff>;
+ size = <CONFIG_SYS_MONITOR_LEN>;
+
+ u-boot-with-ucode-ptr {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ optional-ucode;
+ };
+
+ u-boot-dtb-with-ucode {
+ align = <256>;
+ };
+ powerpc-mpc85xx-bootpg-resetvec {
+ offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
+ *
+ * (C) Copyright 2016
+ * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * Copyright 2014 - 2015 Freescale Semiconductor Inc.
+ */
+
+/include/ "t104xsi-pre.dtsi"
+
+/ {
+ model = "keymile,kmcent2";
+ compatible = "keymile,kmcent2";
+
+ aliases {
+ front_phy = &front_phy;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ size = <0 0x1000000>;
+ alignment = <0 0x1000000>;
+ };
+ qman_fqd: qman-fqd {
+ size = <0 0x400000>;
+ alignment = <0 0x400000>;
+ };
+ qman_pfdr: qman-pfdr {
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ };
+ };
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe8000000 0x04000000
+ 1 0 0xf 0xfa000000 0x00010000
+ 2 0 0xf 0xfb000000 0x00010000
+ 4 0 0xf 0xc0000000 0x08000000
+ 6 0 0xf 0xd0000000 0x08000000
+ 7 0 0xf 0xd8000000 0x08000000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x04000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ board-control@2,0 {
+ compatible = "keymile,qriox";
+ reg = <0x2 0x0 0x80>;
+ };
+
+ chassis-mgmt@6,0 {
+ compatible = "keymile,bfticu";
+ reg = <6 0 0x100>;
+ interrupt-controller;
+ interrupt-parent = <&mpic>;
+ interrupts = <11 1 0 0>;
+ #interrupt-cells = <1>;
+ };
+
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ dcsr: dcsr@f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01072000>;
+ };
+
+ bportals: bman-portals@ff4000000 {
+ ranges = <0x0 0xf 0xf4000000 0x2000000>;
+ };
+
+ qportals: qman-portals@ff6000000 {
+ ranges = <0x0 0xf 0xf6000000 0x2000000>;
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ spi@110000 {
+ network-clock@1 {
+ compatible = "zarlink,zl30364";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ sdhc@114000 {
+ status = "disabled";
+ };
+
+ i2c@118000 {
+ clock-frequency = <100000>;
+
+ mux@70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@54 {
+ compatible = "atmel,24c02";
+ reg = <0x54>;
+ pagesize = <2>;
+ read-only;
+ label = "ddr3-spd";
+ };
+ };
+
+ i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temp-sensor@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ label = "SENSOR_0";
+ };
+ temp-sensor@4a {
+ compatible = "national,lm75";
+ reg = <0x4a>;
+ label = "SENSOR_2";
+ };
+ temp-sensor@4b {
+ compatible = "national,lm75";
+ reg = <0x4b>;
+ label = "SENSOR_3";
+ };
+ };
+ };
+ };
+
+ i2c@118100 {
+ clock-frequency = <100000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+ };
+
+ i2c@119000 {
+ status = "disabled";
+ };
+
+ i2c@119100 {
+ status = "disabled";
+ };
+
+ serial2: serial@11d500 {
+ status = "disabled";
+ };
+
+ serial3: serial@11d600 {
+ status = "disabled";
+ };
+
+ usb0: usb@210000 {
+ status = "disabled";
+ };
+ usb1: usb@211000 {
+ status = "disabled";
+ };
+
+ display@180000 {
+ status = "disabled";
+ };
+
+ sata@220000 {
+ status = "disabled";
+ };
+ sata@221000 {
+ status = "disabled";
+ };
+
+ fman@400000 {
+ ethernet@e0000 {
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet@e2000 {
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet@e4000 {
+ status = "disabled";
+ };
+
+ ethernet@e6000 {
+ status = "disabled";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&front_phy>;
+ phy-mode = "rgmii-id";
+ };
+
+ mdio0: mdio@fc000 {
+ front_phy: ethernet-phy@11 {
+ reg = <0x11>;
+ };
+ };
+ };
+ };
+
+ pci0: pcie@ffe240000 {
+ reg = <0xf 0xfe240000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie@ffe250000 {
+ status = "disabled";
+ reg = <0xf 0xfe250000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
+ 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie@ffe260000 {
+ status = "disabled";
+ reg = <0xf 0xfe260000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci3: pcie@ffe270000 {
+ status = "disabled";
+ reg = <0xf 0xfe270000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ qe: qe@ffe140000 {
+ ranges = <0x0 0xf 0xfe140000 0x40000>;
+ reg = <0xf 0xfe140000 0 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <0>;
+
+ si1: si@700 {
+ compatible = "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ compatible = "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc_hdlc: ucc@2000 {
+ device_type = "hdlc";
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk9";
+ tx-clock-name = "clk9";
+ fsl,hdlc-bus;
+ };
+ };
+};
+
+#include "t1040si-post.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8379E RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "fsl,mpc8379erdb";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8379@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; // 256MB at 0
+ };
+
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ immr@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>;
+
+ sdhc@2e000 {
+ compatible = "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ bus-width = <0x4>;
+ clock-frequency = <0>;
+ };
+
+ ipic: interrupt-controller@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x700 0x100>;
+ device_type = "ipic";
+ };
+
+ };
+
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ BMan device tree stub [ controller @ offset 0x31a000 ]
+ *
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
+ */
+
+bman: bman@31a000 {
+ compatible = "fsl,bman";
+ reg = <0x31a000 0x1000>;
+ interrupts = <16 2 1 2>;
+ fsl,bman-portals = <&bportals>;
+ memory-region = <&bman_fbpr>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+serial0: serial@11c500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11c500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+};
+
+serial1: serial@11c600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11c600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+serial2: serial@11d500 {
+ cell-index = <2>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11d500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+};
+
+serial3: serial@11d600 {
+ cell-index = <3>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11d600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sdhc: sdhc@114000 {
+ compatible = "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ clock-frequency = <0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+spi@110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+};
+
+timer@41100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x41100 0x100 0x41300 4>;
+ interrupts = <0 0 3 0
+ 1 0 3 0
+ 2 0 3 0
+ 3 0 3 0>;
+};
+
+msi0: msi@41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200 0x44140 4>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+};
+
+msi1: msi@41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200 0x45140 4>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+};
+
+msi2: msi@41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200 0x46140 4>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+};
+
+timer@42100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x42100 0x100 0x42300 4>;
+ interrupts = <4 0 3 0
+ 5 0 3 0
+ 6 0 3 0
+ 7 0 3 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ QMan rev3 device tree stub [ controller @ offset 0x318000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ */
+
+qman: qman@318000 {
+ compatible = "fsl,qman";
+ reg = <0x318000 0x2000>;
+ interrupts = <16 2 1 3>;
+ fsl,qman-portals = <&qportals>;
+ memory-region = <&qman_fqd &qman_pfdr>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sata@220000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sata@221000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v5.0-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+usb@211000 {
+ compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+usb@210000 {
+ compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+&bman_fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&qman_fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&qman_pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc", "simple-bus";
+ interrupts = <25 2 0 0>;
+};
+
+&pci0 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ interrupts = <20 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <20 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+};
+
+&pci1 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0 0xff>;
+ interrupts = <21 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <21 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ };
+};
+
+&pci2 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ interrupts = <22 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <22 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ };
+};
+
+&pci3 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ interrupts = <23 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <23 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 43 1 0 0
+ 0000 0 0 2 &mpic 0 1 0 0
+ 0000 0 0 3 &mpic 4 1 0 0
+ 0000 0 0 4 &mpic 8 1 0 0
+ >;
+ };
+};
+
+&dcsr {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+
+ dcsr-epu@0 {
+ compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
+ interrupts = <52 2 0 0
+ 84 2 0 0
+ 85 2 0 0>;
+ reg = <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
+ reg = <0x1000 0x1000 0x1002000 0x10000>;
+ };
+ dcsr-nxc@2000 {
+ compatible = "fsl,dcsr-nxc";
+ reg = <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible = "fsl,dcsr-corenet";
+ reg = <0x8000 0x1000 0x1A000 0x1000>;
+ };
+ dcsr-dpaa@9000 {
+ compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg = <0x9000 0x1000>;
+ };
+ dcsr-ocn@11000 {
+ compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
+ reg = <0x11000 0x1000>;
+ };
+ dcsr-ddr@12000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr1>;
+ reg = <0x12000 0x1000>;
+ };
+ dcsr-nal@18000 {
+ compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
+ reg = <0x18000 0x1000>;
+ };
+ dcsr-rcpm@22000 {
+ compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg = <0x22000 0x1000>;
+ };
+ dcsr-snpc@30000 {
+ compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+ reg = <0x30000 0x1000 0x1022000 0x10000>;
+ };
+ dcsr-snpc@31000 {
+ compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+ reg = <0x31000 0x1000 0x1042000 0x10000>;
+ };
+ dcsr-cpu-sb-proxy@100000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu0>;
+ reg = <0x100000 0x1000 0x101000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@108000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x108000 0x1000 0x109000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@110000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu2>;
+ reg = <0x110000 0x1000 0x111000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@118000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu3>;
+ reg = <0x118000 0x1000 0x119000 0x1000>;
+ };
+};
+
+&bportals {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "simple-bus";
+
+ bman-portal@0 {
+ compatible = "fsl,bman-portal";
+ reg = <0x0 0x4000>, <0x1000000 0x1000>;
+ interrupts = <105 2 0 0>;
+ };
+ bman-portal@4000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+ interrupts = <107 2 0 0>;
+ };
+ bman-portal@8000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+ interrupts = <109 2 0 0>;
+ };
+ bman-portal@c000 {
+ compatible = "fsl,bman-portal";
+ reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+ interrupts = <111 2 0 0>;
+ };
+ bman-portal@10000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+ interrupts = <113 2 0 0>;
+ };
+ bman-portal@14000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+ interrupts = <115 2 0 0>;
+ };
+ bman-portal@18000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+ interrupts = <117 2 0 0>;
+ };
+ bman-portal@1c000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+ interrupts = <119 2 0 0>;
+ };
+ bman-portal@20000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+ interrupts = <121 2 0 0>;
+ };
+ bman-portal@24000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+ interrupts = <123 2 0 0>;
+ };
+};
+
+&qportals {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "simple-bus";
+
+ qportal0: qman-portal@0 {
+ compatible = "fsl,qman-portal";
+ reg = <0x0 0x4000>, <0x1000000 0x1000>;
+ interrupts = <104 0x2 0 0>;
+ cell-index = <0x0>;
+ };
+ qportal1: qman-portal@4000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+ interrupts = <106 0x2 0 0>;
+ cell-index = <0x1>;
+ };
+ qportal2: qman-portal@8000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+ interrupts = <108 0x2 0 0>;
+ cell-index = <0x2>;
+ };
+ qportal3: qman-portal@c000 {
+ compatible = "fsl,qman-portal";
+ reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+ interrupts = <110 0x2 0 0>;
+ cell-index = <0x3>;
+ };
+ qportal4: qman-portal@10000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+ interrupts = <112 0x2 0 0>;
+ cell-index = <0x4>;
+ };
+ qportal5: qman-portal@14000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+ interrupts = <114 0x2 0 0>;
+ cell-index = <0x5>;
+ };
+ qportal6: qman-portal@18000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+ interrupts = <116 0x2 0 0>;
+ cell-index = <0x6>;
+ };
+ qportal7: qman-portal@1c000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+ interrupts = <118 0x2 0 0>;
+ cell-index = <0x7>;
+ };
+ qportal8: qman-portal@20000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+ interrupts = <120 0x2 0 0>;
+ cell-index = <0x8>;
+ };
+ qportal9: qman-portal@24000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+ interrupts = <122 0x2 0 0>;
+ cell-index = <0x9>;
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <16>;
+ };
+
+ ddr1: memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v5.0",
+ "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,t1040-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000>;
+ interrupts = <16 2 1 27>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x1000>;
+ ranges = <0 0x20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ pamu0: pamu@0 {
+ reg = <0 0x1000>;
+ fsl,primary-cache-geometry = <128 1>;
+ fsl,secondary-cache-geometry = <16 2>;
+ };
+ };
+
+/include/ "qoriq-mpic.dtsi"
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ fsl,liodn-bits = <12>;
+ };
+
+/include/ "qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
+ compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1";
+ reg = <0xe2000 0x1000>;
+ };
+
+ sfp: sfp@e8000 {
+ compatible = "fsl,t1040-sfp";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes@ea000 {
+ compatible = "fsl,t1040-serdes";
+ reg = <0xea000 0x4000>;
+ };
+
+ tmu: tmu@f0000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0xf0000 0x1000>;
+ interrupts = <18 2 0 0>;
+ fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
+ fsl,tmu-calibration = <0x00000000 0x00000025
+ 0x00000001 0x00000028
+ 0x00000002 0x0000002d
+ 0x00000003 0x00000031
+ 0x00000004 0x00000036
+ 0x00000005 0x0000003a
+ 0x00000006 0x00000040
+ 0x00000007 0x00000044
+ 0x00000008 0x0000004a
+ 0x00000009 0x0000004f
+ 0x0000000a 0x00000054
+
+ 0x00010000 0x0000000d
+ 0x00010001 0x00000013
+ 0x00010002 0x00000019
+ 0x00010003 0x0000001f
+ 0x00010004 0x00000025
+ 0x00010005 0x0000002d
+ 0x00010006 0x00000033
+ 0x00010007 0x00000043
+ 0x00010008 0x0000004b
+ 0x00010009 0x00000053
+
+ 0x00020000 0x00000010
+ 0x00020001 0x00000017
+ 0x00020002 0x0000001f
+ 0x00020003 0x00000029
+ 0x00020004 0x00000031
+ 0x00020005 0x0000003c
+ 0x00020006 0x00000042
+ 0x00020007 0x0000004d
+ 0x00020008 0x00000056
+
+ 0x00030000 0x00000012
+ 0x00030001 0x0000001d>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map2 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map3 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ scfg: global-utilities@fc000 {
+ compatible = "fsl,t1040-scfg";
+ reg = <0xfc000 0x1000>;
+ };
+
+/include/ "elo3-dma-0.dtsi"
+/include/ "elo3-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+ spi@110000 {
+ fsl,espi-num-chipselects = <4>;
+ };
+
+/include/ "qoriq-esdhc-0.dtsi"
+ sdhc@114000 {
+ compatible = "fsl,t1040-esdhc", "fsl,esdhc";
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
+ sdhci,auto-cmd12;
+ };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+ usb0: usb@210000 {
+ compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
+ phy_type = "utmi";
+ port0;
+ };
+/include/ "qoriq-usb2-dr-0.dtsi"
+ usb1: usb@211000 {
+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ display@180000 {
+ compatible = "fsl,t1040-diu", "fsl,diu";
+ reg = <0x180000 1000>;
+ interrupts = <74 2 0 0>;
+ };
+
+/include/ "qoriq-sata2-0.dtsi"
+ sata@220000 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
+ };
+/include/ "qoriq-sata2-1.dtsi"
+ sata@221000 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
+ };
+/include/ "qoriq-sec5.0-0.dtsi"
+/include/ "qoriq-qman3.dtsi"
+/include/ "qoriq-bman1.dtsi"
+
+/include/ "qoriq-fman3l-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+ fman@400000 {
+ enet0: ethernet@e0000 {
+ };
+
+ enet1: ethernet@e2000 {
+ };
+
+ enet2: ethernet@e4000 {
+ };
+
+ enet3: ethernet@e6000 {
+ };
+
+ enet4: ethernet@e8000 {
+ };
+
+ mdio@fc000 {
+ interrupts = <100 1 0 0>;
+ };
+
+ mdio@fd000 {
+ status = "disabled";
+ };
+ };
+
+ seville_switch: ethernet-switch@800000 {
+ compatible = "mscc,vsc9953-switch";
+ reg = <0x800000 0x290000>;
+ interrupts = <26 2 0 0>;
+ interrupt-names = "xtr";
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ seville_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ seville_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ seville_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ seville_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ seville_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+
+ seville_port5: port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+
+ seville_port6: port@6 {
+ reg = <6>;
+ status = "disabled";
+ };
+
+ seville_port7: port@7 {
+ reg = <7>;
+ status = "disabled";
+ };
+
+ seville_port8: port@8 {
+ reg = <8>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+
+ seville_port9: port@9 {
+ reg = <9>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&qe {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013-2014 Freescale Semiconductor Inc.
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+ dcsr = &dcsr;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ pci3 = &pci3;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ sdhc = &sdhc;
+
+ crypto = &crypto;
+
+ fman0 = &fman0;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&clockgen 1 1>;
+ next-level-cache = <&L2_2>;
+ #cooling-cells = <2>;
+ L2_2: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type = "cpu";
+ reg = <2>;
+ clocks = <&clockgen 1 2>;
+ next-level-cache = <&L2_3>;
+ #cooling-cells = <2>;
+ L2_3: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type = "cpu";
+ reg = <3>;
+ clocks = <&clockgen 1 3>;
+ next-level-cache = <&L2_4>;
+ #cooling-cells = <2>;
+ L2_4: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+};
u8 res6[0xE8];
} fsl_i2c_t;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct fsl_i2c_dev {
struct fsl_i2c_base __iomem *base; /* register base */
u32 i2c_clk;
} immap_t;
#endif
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+ union {
+ u32 gpibe;
+ u8 res0[0xE8];
+ };
+};
+
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
- bdinfo_print_num("immr_base", bd->bi_immr_base);
+ bdinfo_print_num_l("immr_base", bd->bi_immr_base);
#endif
- bdinfo_print_num("bootflags", bd->bi_bootflags);
+ bdinfo_print_num_l("bootflags", bd->bi_bootflags);
bdinfo_print_mhz("intfreq", bd->bi_intfreq);
#ifdef CONFIG_ENABLE_36BIT_PHYS
if (IS_ENABLED(CONFIG_PHYS_64BIT))
#include <command.h>
#include <image.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
#include <asm/byteorder.h>
*/
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <common.h>
#include <fdtdec.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
ulong board_get_usable_ram_top(ulong total_size)
{
-#ifdef CONFIG_64BIT
/*
* Ensure that we run from first 4GB so that all
* addresses used by U-Boot are 32bit addresses.
* devices work fine because DMA mapping APIs will
* provide 32bit DMA addresses only.
*/
- if (gd->ram_top > SZ_4G)
- return SZ_4G;
-#endif
+ if (gd->ram_top >= SZ_4G)
+ return SZ_4G - 1;
+
return gd->ram_top;
}
#include <common.h>
#include <fdtdec.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
ulong board_get_usable_ram_top(ulong total_size)
{
-#ifdef CONFIG_64BIT
/*
* Ensure that we run from first 4GB so that all
* addresses used by U-Boot are 32bit addresses.
* devices work fine because DMA mapping APIs will
* provide 32bit DMA addresses only.
*/
- if (gd->ram_top > SZ_4G)
- return SZ_4G;
-#endif
+ if (gd->ram_top >= SZ_4G)
+ return SZ_4G - 1;
+
return gd->ram_top;
}
typedef u32 dma_addr_t;
#endif
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
#endif /* __KERNEL__ */
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass-internal.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/kbuild.h>
int main(void)
#include <fdt_support.h>
#include <hang.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/root.h>
#include <image.h>
#include <asm/byteorder.h>
#include <fdt_support.h>
#include <log.h>
#include <mapmem.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <image.h>
#include <mapmem.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <linux/stddef.h>
#include <efi_loader.h>
#include <hang.h>
#include <irq_func.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/encoding.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <linux/err.h>
#include <cpu_func.h>
#include <dm.h>
#include <asm/barrier.h>
+#include <asm/global_data.h>
#include <asm/smp.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/smp.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <os.h>
#include <log.h>
#include <os.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/spl.h>
#include <asm/state.h>
#include <test/test.h>
#include <cli.h>
#include <sort.h>
#include <asm/getopt.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/malloc.h>
#include <asm/sections.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/sandbox-gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sandbox-pinmux.h>
#include <dt-bindings/mux/mux.h>
};
};
+ buttons2 {
+ compatible = "adc-keys";
+ io-channels = <&adc 3>;
+ keyup-threshold-microvolt = <3000000>;
+
+ button-up {
+ label = "button3";
+ linux,code = <KEY_F3>;
+ press-threshold-microvolt = <1500000>;
+ };
+
+ button-down {
+ label = "button4";
+ linux,code = <KEY_F4>;
+ press-threshold-microvolt = <1000000>;
+ };
+
+ button-enter {
+ label = "button5";
+ linux,code = <KEY_F5>;
+ press-threshold-microvolt = <500000>;
+ };
+ };
+
cros_ec: cros-ec {
reg = <0 0>;
compatible = "google,cros-ec-sandbox";
test5-gpios = <&gpio_a 19>;
};
+ mmio-bus@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "denx,u-boot-test-bus";
+ dma-ranges = <0x10000000 0x00000000 0x00040000>;
+
+ subnode@0 {
+ compatible = "denx,u-boot-fdt-test";
+ };
+ };
+
+ mmio-bus@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "denx,u-boot-test-bus";
+
+ subnode@0 {
+ compatible = "denx,u-boot-fdt-test";
+ };
+ };
+
acpi_test1: acpi-test {
compatible = "denx,u-boot-acpi-test";
acpi-ssdt-test-data = "ab";
i2c-eeprom = <&bootcount_i2c>;
};
- adc@0 {
+ adc: adc@0 {
compatible = "sandbox,adc";
+ #io-channel-cells = <1>;
vdd-supply = <&buck2>;
vss-microvolts = <0>;
};
* sandbox_clk_test_get - Ask the sandbox clock test device to request its
* clocks.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_get(struct udevice *dev);
* sandbox_clk_test_devm_get - Ask the sandbox clock test device to request its
* clocks using the managed API.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_devm_get(struct udevice *dev);
* sandbox_clk_test_get_bulk - Ask the sandbox clock test device to request its
* clocks with the bulk clk API.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_get_bulk(struct udevice *dev);
* sandbox_clk_test_get_rate - Ask the sandbox clock test device to query a
* clock's rate.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @id: The test device's clock ID to query.
* @return: The rate of the clock.
*/
* sandbox_clk_test_set_rate - Ask the sandbox clock test device to set a
* clock's rate.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @id: The test device's clock ID to configure.
* @return: The new rate of the clock.
*/
* sandbox_clk_test_enable - Ask the sandbox clock test device to enable a
* clock.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @id: The test device's clock ID to configure.
* @return: 0 if OK, or a negative error code.
*/
* sandbox_clk_test_enable_bulk - Ask the sandbox clock test device to enable
* all clocks in it's clock bulk struct.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_enable_bulk(struct udevice *dev);
* sandbox_clk_test_disable - Ask the sandbox clock test device to disable a
* clock.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @id: The test device's clock ID to configure.
* @return: 0 if OK, or a negative error code.
*/
* sandbox_clk_test_disable_bulk - Ask the sandbox clock test device to disable
* all clocks in it's clock bulk struct.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_disable_bulk(struct udevice *dev);
* sandbox_clk_test_free - Ask the sandbox clock test device to free its
* clocks.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_free(struct udevice *dev);
* sandbox_clk_test_release_bulk - Ask the sandbox clock test device to release
* all clocks in it's clock bulk struct.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_release_bulk(struct udevice *dev);
* sandbox_clk_test_valid - Ask the sandbox clock test device to check its
* clocks are valid.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_valid(struct udevice *dev);
* sandbox_clk_test_valid - Ask the sandbox clock test device to check its
* clocks are valid.
*
- * @dev: The sandbox clock test (client) devivce.
+ * @dev: The sandbox clock test (client) device.
* @return: 0 if OK, or a negative error code.
*/
struct clk *sandbox_clk_test_get_devm_clk(struct udevice *dev, int id);
#include <efi_loader.h>
#include <irq_func.h>
#include <os.h>
+#include <asm/global_data.h>
#include <asm-generic/signal.h>
#include <asm/u-boot-sandbox.h>
config CPU_SH4
bool
-config CPU_SH4A
- bool
- select CPU_SH4
-
-config SH_32BIT
- bool "32bit mode"
- depends on CPU_SH4A
- default n
- help
- SH4A has 2 physical memory maps. This use 32bit mode.
- And this is board specific. Please check your board if you
- want to use this.
-
choice
prompt "Target select"
optional
-config TARGET_MIGOR
- bool "Migo-R"
- select CPU_SH4
-
config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
select CPU_SH4
-config TARGET_R7780MP
- bool "R7780MP board"
- select CPU_SH4A
-
-config TARGET_SH7752EVB
- bool "SH7752EVB"
- select CPU_SH4A
-
-config TARGET_SH7753EVB
- bool "SH7753EVB"
- select CPU_SH4
-
-config TARGET_SH7757LCR
- bool "SH7757LCR"
- select CPU_SH4A
-
-config TARGET_SH7763RDP
- bool "SH7763RDP"
- select CPU_SH4
-
endchoice
config SYS_ARCH
source "arch/sh/lib/Kconfig"
-source "board/renesas/MigoR/Kconfig"
source "board/renesas/r2dplus/Kconfig"
-source "board/renesas/r7780mp/Kconfig"
-source "board/renesas/sh7752evb/Kconfig"
-source "board/renesas/sh7753evb/Kconfig"
-source "board/renesas/sh7757lcr/Kconfig"
-source "board/renesas/sh7763rdp/Kconfig"
endmenu
# error "Unknown SH4 variant"
#endif
-#if defined(CONFIG_SH_32BIT)
-#define PMB_ADDR_ARRAY 0xf6100000
-#define PMB_ADDR_ENTRY 8
-#define PMB_VPN 24
-
-#define PMB_DATA_ARRAY 0xf7100000
-#define PMB_DATA_ENTRY 8
-#define PMB_PPN 24
-#define PMB_UB 9 /* Buffered write */
-#define PMB_V 8 /* Valid */
-#define PMB_SZ1 7 /* Page size (upper bit) */
-#define PMB_SZ0 4 /* Page size (lower bit) */
-#define PMB_C 3 /* Cacheability */
-#define PMB_WT 0 /* Write-through */
-
-#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
-#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
-#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
-#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
- ((ppn << PMB_PPN) | (ub << PMB_UB) | \
- (v << PMB_V) | (sz1 << PMB_SZ1) | \
- (sz0 << PMB_SZ0) | (c << PMB_C) | \
- (wt << PMB_WT))
-#endif
-
#endif /* _ASM_CPU_SH4_H_ */
{
}
-#ifdef CONFIG_CPU_SH4A
-#define __icbi() \
-{ \
- unsigned long __addr; \
- __addr = 0xa8000000; \
- __asm__ __volatile__( \
- "icbi %0\n\t" \
- : /* no output */ \
- : "m" (__m(__addr))); \
-}
-#endif
-
static inline unsigned long tas(volatile int *m)
{
unsigned long retval;
* effect. On newer cores (like the sh4a and sh5) this is accomplished
* with icbi.
*
- * Also note that on sh4a in the icbi case we can forego a synco for the
- * write barrier, as it's not necessary for control registers.
- *
* Historically we have only done this type of barrier for the MMUCR, but
* it's also necessary for the CCR, so we make it generic here instead.
*/
-#ifdef CONFIG_CPU_SH4A
-#define mb() __asm__ __volatile__ ("synco": : :"memory")
-#define rmb() mb()
-#define wmb() __asm__ __volatile__ ("synco": : :"memory")
-#define ctrl_barrier() __icbi()
-#define read_barrier_depends() do { } while(0)
-#else
#define mb() __asm__ __volatile__ ("": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
#define read_barrier_depends() do { } while(0)
-#endif
#ifdef CONFIG_SMP
#define smp_mb() mb()
+++ /dev/null
-#ifndef __ASM_SH_UNALIGNED_SH4A_H
-#define __ASM_SH_UNALIGNED_SH4A_H
-
-/*
- * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
- * Support for 64-bit accesses are done through shifting and masking
- * relative to the endianness. Unaligned stores are not supported by the
- * instruction encoding, so these continue to use the packed
- * struct.
- *
- * The same note as with the movli.l/movco.l pair applies here, as long
- * as the load is gauranteed to be inlined, nothing else will hook in to
- * r0 and we get the return value for free.
- *
- * NOTE: Due to the fact we require r0 encoding, care should be taken to
- * avoid mixing these heavily with other r0 consumers, such as the atomic
- * ops. Failure to adhere to this can result in the compiler running out
- * of spill registers and blowing up when building at low optimization
- * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
- */
-#include <linux/types.h>
-#include <asm/byteorder.h>
-
-static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
-{
- unsigned long unaligned;
-
- __asm__ __volatile__ (
- "movua.l @%1, %0\n\t"
- : "=z" (unaligned)
- : "r" (p)
- );
-
- return unaligned;
-}
-
-struct __una_u16 { u16 x __attribute__((packed)); };
-struct __una_u32 { u32 x __attribute__((packed)); };
-struct __una_u64 { u64 x __attribute__((packed)); };
-
-static inline u16 __get_unaligned_cpu16(const u8 *p)
-{
-#ifdef __LITTLE_ENDIAN
- return p[0] | p[1] << 8;
-#else
- return p[0] << 8 | p[1];
-#endif
-}
-
-/*
- * Even though movua.l supports auto-increment on the read side, it can
- * only store to r0 due to instruction encoding constraints, so just let
- * the compiler sort it out on its own.
- */
-static inline u64 __get_unaligned_cpu64(const u8 *p)
-{
-#ifdef __LITTLE_ENDIAN
- return (u64)__get_unaligned_cpu32(p + 4) << 32 |
- __get_unaligned_cpu32(p);
-#else
- return (u64)__get_unaligned_cpu32(p) << 32 |
- __get_unaligned_cpu32(p + 4);
-#endif
-}
-
-static inline u16 get_unaligned_le16(const void *p)
-{
- return le16_to_cpu(__get_unaligned_cpu16(p));
-}
-
-static inline u32 get_unaligned_le32(const void *p)
-{
- return le32_to_cpu(__get_unaligned_cpu32(p));
-}
-
-static inline u64 get_unaligned_le64(const void *p)
-{
- return le64_to_cpu(__get_unaligned_cpu64(p));
-}
-
-static inline u16 get_unaligned_be16(const void *p)
-{
- return be16_to_cpu(__get_unaligned_cpu16(p));
-}
-
-static inline u32 get_unaligned_be32(const void *p)
-{
- return be32_to_cpu(__get_unaligned_cpu32(p));
-}
-
-static inline u64 get_unaligned_be64(const void *p)
-{
- return be64_to_cpu(__get_unaligned_cpu64(p));
-}
-
-static inline void __put_le16_noalign(u8 *p, u16 val)
-{
- *p++ = val;
- *p++ = val >> 8;
-}
-
-static inline void __put_le32_noalign(u8 *p, u32 val)
-{
- __put_le16_noalign(p, val);
- __put_le16_noalign(p + 2, val >> 16);
-}
-
-static inline void __put_le64_noalign(u8 *p, u64 val)
-{
- __put_le32_noalign(p, val);
- __put_le32_noalign(p + 4, val >> 32);
-}
-
-static inline void __put_be16_noalign(u8 *p, u16 val)
-{
- *p++ = val >> 8;
- *p++ = val;
-}
-
-static inline void __put_be32_noalign(u8 *p, u32 val)
-{
- __put_be16_noalign(p, val >> 16);
- __put_be16_noalign(p + 2, val);
-}
-
-static inline void __put_be64_noalign(u8 *p, u64 val)
-{
- __put_be32_noalign(p, val >> 32);
- __put_be32_noalign(p + 4, val);
-}
-
-static inline void put_unaligned_le16(u16 val, void *p)
-{
-#ifdef __LITTLE_ENDIAN
- ((struct __una_u16 *)p)->x = val;
-#else
- __put_le16_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_le32(u32 val, void *p)
-{
-#ifdef __LITTLE_ENDIAN
- ((struct __una_u32 *)p)->x = val;
-#else
- __put_le32_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_le64(u64 val, void *p)
-{
-#ifdef __LITTLE_ENDIAN
- ((struct __una_u64 *)p)->x = val;
-#else
- __put_le64_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_be16(u16 val, void *p)
-{
-#ifdef __BIG_ENDIAN
- ((struct __una_u16 *)p)->x = val;
-#else
- __put_be16_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_be32(u32 val, void *p)
-{
-#ifdef __BIG_ENDIAN
- ((struct __una_u32 *)p)->x = val;
-#else
- __put_be32_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_be64(u64 val, void *p)
-{
-#ifdef __BIG_ENDIAN
- ((struct __una_u64 *)p)->x = val;
-#else
- __put_be64_noalign(p, val);
-#endif
-}
-
-/*
- * Cause a link-time error if we try an unaligned access other than
- * 1,2,4 or 8 bytes long
- */
-extern void __bad_unaligned_access_size(void);
-
-#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \
- __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
- __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \
- __bad_unaligned_access_size())))); \
- }))
-
-#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \
- __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
- __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \
- __bad_unaligned_access_size())))); \
- }))
-
-#define __put_unaligned_le(val, ptr) ({ \
- void *__gu_p = (ptr); \
- switch (sizeof(*(ptr))) { \
- case 1: \
- *(u8 *)__gu_p = (__force u8)(val); \
- break; \
- case 2: \
- put_unaligned_le16((__force u16)(val), __gu_p); \
- break; \
- case 4: \
- put_unaligned_le32((__force u32)(val), __gu_p); \
- break; \
- case 8: \
- put_unaligned_le64((__force u64)(val), __gu_p); \
- break; \
- default: \
- __bad_unaligned_access_size(); \
- break; \
- } \
- (void)0; })
-
-#define __put_unaligned_be(val, ptr) ({ \
- void *__gu_p = (ptr); \
- switch (sizeof(*(ptr))) { \
- case 1: \
- *(u8 *)__gu_p = (__force u8)(val); \
- break; \
- case 2: \
- put_unaligned_be16((__force u16)(val), __gu_p); \
- break; \
- case 4: \
- put_unaligned_be32((__force u32)(val), __gu_p); \
- break; \
- case 8: \
- put_unaligned_be64((__force u64)(val), __gu_p); \
- break; \
- default: \
- __bad_unaligned_access_size(); \
- break; \
- } \
- (void)0; })
-
-#ifdef __LITTLE_ENDIAN
-# define get_unaligned __get_unaligned_le
-# define put_unaligned __put_unaligned_le
-#else
-# define get_unaligned __get_unaligned_be
-# define put_unaligned __put_unaligned_be
-#endif
-
-#endif /* __ASM_SH_UNALIGNED_SH4A_H */
/* Copy from linux-kernel. */
-#ifdef CONFIG_CPU_SH4A
-/* SH-4A can handle unaligned loads in a relatively neutered fashion. */
-#include <asm/unaligned-sh4a.h>
-#else
-/* Otherwise, SH can't handle unaligned accesses. */
+/* Other than SH4A, SH can't handle unaligned accesses. */
#include <linux/compiler.h>
#if defined(__BIG_ENDIAN__)
#define get_unaligned __get_unaligned_be
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
-#endif
#endif /* _ASM_SH_UNALIGNED_H */
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <acpi/acpi_table.h>
#include <asm/cpu_common.h>
#include <asm/cpu_x86.h>
+#include <asm/global_data.h>
#include <asm/intel_acpi.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/cpu_common.h>
#include <asm/cpu_x86.h>
#include <asm/fast_spi.h>
+#include <asm/global_data.h>
#include <asm/intel_pinctrl.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <malloc.h>
#include <p2sb.h>
#include <acpi/acpi_s3.h>
+#include <asm/global_data.h>
#include <asm/intel_pinctrl.h>
#include <asm/io.h>
#include <asm/intel_regs.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/fsp1/fsp_support.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <fdtdec.h>
#include <log.h>
#include <asm/fsp1/fsp_support.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
#include <asm/cpu_common.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/lpc_common.h>
#include <asm/msr.h>
#include <handoff.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mtrr.h>
int misc_init_r(void)
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
#include <asm/cpu_common.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/msr.h>
#include <asm/post.h>
#include <dm.h>
#include <log.h>
#include <pch.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lpc_common.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mrc_common.h>
#include <asm/arch/iomap.h>
#include <log.h>
#include <pch.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/i8259.h>
#include <asm/intel_regs.h>
#include <pch.h>
#include <pci.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/intel_regs.h>
#include <pci.h>
#include <syscon.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/lpc_common.h>
#include <asm/mrccache.h>
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor-flags.h>
#include <fdtdec.h>
#include <init.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <init.h>
#include <asm/e820.h>
#include <asm/arch/sysinfo.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <net.h>
#include <asm/arch/sysinfo.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/control_regs.h>
#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/lapic.h>
#include <asm/microcode.h>
#include <asm/mp.h>
#include <dm.h>
#include <errno.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <usb.h>
#include <asm/bootparam.h>
#include <asm/e820.h>
+#include <asm/global_data.h>
#include <asm/post.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <efi.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/u-boot-x86.h>
DECLARE_GLOBAL_DATA_PTR;
* Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
*/
-#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor-flags.h>
#include <asm/control_regs.h>
#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <irq.h>
#include <irq_func.h>
#include <asm/control_regs.h>
+#include <asm/global_data.h>
#include <asm/i8259.h>
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/acpi_table.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
+#include <asm/global_data.h>
#include <asm/intel_acpi.h>
#include <asm/ioapic.h>
#include <asm/mpspec.h>
#include <acpi/acpigen.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/lapic.h>
#include <asm/lpc_common.h>
#include <handoff.h>
#include <init.h>
#include <asm/cpu_common.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/lapic.h>
#include <asm/lpc_common.h>
#include <malloc.h>
#include <p2sb.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/itss.h>
static int set_polarity(struct udevice *dev, uint irq, bool active_low)
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lpc_common.h>
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <asm/cpu.h>
#include <asm/microcode.h>
#include <log.h>
#include <syscon.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/intel_regs.h>
#include <asm/mrc_common.h>
#include <irq.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <malloc.h>
#include <pch.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <pch.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/fsp1/fsp_support.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <log.h>
#include <rtc.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
#include <asm/cpu_x86.h>
+#include <asm/global_data.h>
#include <asm/msr.h>
#include <asm/msr-index.h>
#include <asm/mtrr.h>
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/msr.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/pch_common.h>
#include <asm/pci.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <qfw.h>
#include <asm/atomic.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <log.h>
#include <sort.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mp.h>
#include <asm/msr.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/post.h>
#include <asm/arch/qemu.h>
#include <malloc.h>
#include <asm/e820.h>
#include <asm/arch/qemu.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
int ret;
int cpu_num;
int cpu_online;
+ struct uclass *uc;
struct udevice *dev, *pdev;
struct cpu_plat *plat;
char *cpu;
+ /* This will cause the CPUs devices to be bound */
+ ret = uclass_get(UCLASS_CPU, &uc);
+ if (ret)
+ return ret;
+
/* first we need to find '/cpus' */
for (device_find_first_child(dm_root(), &pdev);
pdev;
#include <common.h>
#include <acpi/acpi_table.h>
+#include <asm/processor.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
#include <log.h>
#include <malloc.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/post.h>
* C code
*/
-#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/e820.h>
#include <asm/arch/slimbootloader.h>
#include <ns16550.h>
#include <serial.h>
#include <asm/arch/slimbootloader.h>
+#include <asm/global_data.h>
/**
* The serial port info hob is generated by Slim Bootloader, so eligible for
#include <init.h>
#include <log.h>
#include <asm/arch/slimbootloader.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <config.h>
-#include <asm/global_data.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*/
-#include <asm/global_data.h>
#include <asm/processor-flags.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */
#include <common.h>
#include <log.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/msr.h>
#include <asm/processor.h>
#include <asm/turbo.h>
#ifndef __ACPI__
+#include <pci.h>
+
struct acpi_facs;
struct acpi_fadt;
struct acpi_global_nvs;
/* Device 0:0.0 PCI configuration space */
#include <linux/bitops.h>
+
+struct udevice;
+
#define MCHBAR 0x48
/* RAPL Package Power Limit register under MCHBAR */
};
struct cpu_info;
+struct udevice;
/**
* cpu_common_init() - Set up common CPU init
#ifndef ASM_FAST_SPI_H
#define ASM_FAST_SPI_H
-/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
+#include <pci.h>
#include <linux/bitops.h>
+
+/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
struct fast_spi_regs {
u32 bfp;
u32 hsfsts_ctl;
#ifndef _ASM_IO_H
#define _ASM_IO_H
-#include <linux/compiler.h>
+#include <compiler.h>
/*
* This file contains the definitions for the x86 IO instructions
#include <asm/atomic.h>
#include <asm/cache.h>
+struct udevice;
+
enum {
/* Indicates that the function should run on all CPUs */
MP_SELECT_ALL = -1,
#ifndef _ASM_MRCCACHE_H
#define _ASM_MRCCACHE_H
+#include <compiler.h>
+
#define MRC_DATA_ALIGN 0x100
#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \
('C' << 16) | ('D'<<24))
#include <acpi/acpi_s3.h>
#include <acpi/acpi_table.h>
#include <asm/acpi.h>
+#include <asm/global_data.h>
#include <asm/post.h>
#include <linux/linkage.h>
#include <acpi/acpi_table.h>
#include <asm/acpi/global_nvs.h>
#include <asm/ioapic.h>
+#include <asm/global_data.h>
#include <asm/lapic.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/kbuild.h>
int main(void)
* Copyright (C) 2009-2010 coresystems GmbH
*/
#include <common.h>
+#include <compiler.h>
#include <bios_emul.h>
#include <irq_func.h>
#include <log.h>
#include <command.h>
#include <hang.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/root.h>
#include <errno.h>
#include <common.h>
#include <command.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/u-boot-x86.h>
DECLARE_GLOBAL_DATA_PTR;
#include <acpi/acpi_s3.h>
#include <asm/coreboot_tables.h>
#include <asm/e820.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <efi_loader.h>
#include <asm/e820.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <acpi/acpi_s3.h>
#include <asm/cmos_layout.h>
#include <asm/early_cmos.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mrccache.h>
#include <asm/post.h>
#include <log.h>
#include <asm/fsp/fsp_support.h>
#include <asm/e820.h>
+#include <asm/global_data.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/post.h>
#include <video.h>
#include <acpi/acpi_table.h>
#include <asm/fsp/fsp_support.h>
+#include <asm/global_data.h>
#include <asm/intel_opregion.h>
#include <asm/mtrr.h>
#include <dm/acpi.h>
#include <acpi/acpi_s3.h>
#include <asm/cmos_layout.h>
#include <asm/early_cmos.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mrccache.h>
#include <asm/post.h>
#include <common.h>
#include <init.h>
#include <asm/fsp/fsp_support.h>
+#include <asm/global_data.h>
int dram_init(void)
{
#include <asm/fsp/fsp_support.h>
#include <asm/fsp2/fsp_api.h>
#include <asm/fsp2/fsp_internal.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
int dram_init(void)
#include <bootstage.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mrccache.h>
#include <asm/fsp/fsp_infoheader.h>
#include <asm/fsp2/fsp_api.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#include <asm/fsp/fsp_infoheader.h>
#include <asm/fsp2/fsp_internal.h>
+#include <asm/global_data.h>
int fsp_silicon_init(bool s3wake, bool use_spi_flash)
{
#include <spi_flash.h>
#include <asm/fsp/fsp_support.h>
#include <asm/fsp2/fsp_internal.h>
+#include <asm/global_data.h>
/* The amount of the FSP header to probe to obtain what we need */
#define PROBE_BUF_SIZE 0x180
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/mtrr.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/irq.h>
#include <asm/ioapic.h>
#include <asm/lapic.h>
#include <net.h>
#include <spi.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include <asm/mrccache.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <log.h>
#include <physmem.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#include <pch.h>
#include <pci.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <common.h>
#include <log.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/pci.h>
#include <asm/pirq_routing.h>
#include <common.h>
#include <log.h>
#include <relocate.h>
+#include <asm/global_data.h>
#include <asm/u-boot-x86.h>
#include <asm/sections.h>
#include <elf.h>
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
+#include <asm/global_data.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
#include <malloc.h>
#include <smbios.h>
#include <acpi/acpi_table.h>
+#include <asm/global_data.h>
#include <asm/sfi.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <log.h>
#include <spl.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm-generic/sections.h>
#include <command.h>
#include <cpu_func.h>
#include <env.h>
+#include <asm/global_data.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <asm/addrspace.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <common.h>
#include <flash.h>
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
#include <netdev.h>
#endif
+#include <asm/global_data.h>
#include <linux/io.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
#include <netdev.h>
#endif
+#include <asm/global_data.h>
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- regs = (struct ftsmc020_bank *)addr;
+ regs = (struct ftsmc020_bank *)(uintptr_t)addr;
regs->cr &= ~FTSMC020_BANK_WPROT;
return 0;
#include <i2c.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
# include <asm/arch/mx6-ddr.h>
#endif
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <fdtdec.h>
#include <i2c.h>
#include <lcd.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include "bur_common.h"
#include <common.h>
#include <command.h>
+#include <asm/global_data.h>
#include "asm/m5282.h"
#include <bmp_layout.h>
#include <env.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <clk.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <env.h>
#include <linux/delay.h>
#include <miiphy.h>
#include <net.h>
#include <asm/arch/orion5x.h>
+#include <asm/global_data.h>
#include "../common/common.h"
#include <spl.h>
#include <ns16550.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <env.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <common.h>
#include <init.h>
#include <mvmfp.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mfp.h>
+++ /dev/null
-kwbimage.cfg
+++ /dev/null
-if TARGET_DB_88F6281_BP
-
-config SYS_BOARD
- default "db-88f6281-bp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-88f6281-bp"
-
-endif
+++ /dev/null
-DB_88F6820_AMC BOARD
-M: Chris Packham <judge.packham@gmail.com>
-S: Maintained
-F: arch/arm/dts/kirkwood-db-88f6281.dts
-F: arch/arm/dts/kirkwood-db-88f6281-spi.dts
-F: arch/arm/dts/kirkwood-db.dtsi
-F: board/Marvell/db-88f6281-bp/
-F: include/configs/db-88f6281-bp.h
-F: configs/db-88f6281-bp-nand_defconfig
-F: configs/db-88f6281-bp-spi_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := db-88f6281-bp.o
-extra-y := kwbimage.cfg
-
-quiet_cmd_sed = SED $@
- cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
-
-SEDFLAGS_kwbimage.cfg = -e "s/^\#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/"
-$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
- include/config/auto.conf
- $(call if_changed,sed)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#define DB_88F6281_OE_LOW ~(BIT(7))
-#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4))
-#define DB_88F6281_OE_VAL_LOW BIT(7)
-#define DB_88F6281_OE_VAL_HIGH 0
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- mvebu_config_gpio(DB_88F6281_OE_VAL_LOW,
- DB_88F6281_OE_VAL_HIGH,
- DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
-#ifdef CONFIG_CMD_NAND
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
-#else
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
-#endif
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_SATA1_ACTn,
- MPP21_SATA0_ACTn,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* automatically defined by kirkwood config.h */
-void reset_phy(void)
-{
-}
-#endif
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-# Boot Media configurations
-#@BOOT_FROM
-
-DATA 0xd00100e0 0x1b1b1b9b
-DATA 0xd0020134 0xbbbbbbbb
-DATA 0xd0020138 0x00bbbbbb
-DATA 0xd0020154 0x00000200
-DATA 0xd002014c 0x00001c00
-DATA 0xd0020148 0x00000001
-
-DATA 0xd0001400 0x43000c30
-DATA 0xd0001404 0x39543000
-DATA 0xd0001408 0x22125451
-DATA 0xd000140c 0x00000833
-DATA 0xd0001410 0x000000cc
-DATA 0xd0001414 0x00000000
-DATA 0xd0001418 0x00000000
-DATA 0xd000141c 0x00000c52
-DATA 0xd0001420 0x00000044
-DATA 0xd0001424 0x0000f1ff
-DATA 0xd0001428 0x00085520
-DATA 0xd000147c 0x00008552
-DATA 0xd0001504 0x0ffffff1
-DATA 0xd0001508 0x10000000
-DATA 0xd000150c 0x0ffffff5
-DATA 0xd0001514 0x00000000
-DATA 0xd000151c 0x00000000
-DATA 0xd0001494 0x84210000
-DATA 0xd0001498 0x00000000
-DATA 0xd000149c 0x0000f40f
-DATA 0xd0001480 0x00000001
-
-# End of Header extension
-DATA 0x0 0x0
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <common.h>
#include <i2c.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
#include <linux/mbus.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
#include "dreamplug.h"
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/cpu.h>
#include <asm/arch/mfp.h>
#include <asm/arch/armada100.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <miiphy.h>
#include <asm/mach-types.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <env.h>
+#include <env_internal.h>
#include <i2c.h>
#include <init.h>
#include <mmc.h>
#include <phy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+ char *ptr = (char *)&default_environment[0];
struct udevice *dev;
struct mmc *mmc_dev;
bool ddr4, emmc;
+ const char *mac;
+ char eth[10];
+ int i;
if (!of_machine_is_compatible("globalscale,espressobin"))
return 0;
+ /* Find free buffer in default_environment[] for new variables */
+ while (*ptr != '\0' && *(ptr+1) != '\0') ptr++;
+ ptr += 2;
+
+ /*
+ * Ensure that 'env default -a' does not erase permanent MAC addresses
+ * stored in env variables: $ethaddr, $eth1addr, $eth2addr and $eth3addr
+ */
+
+ mac = env_get("ethaddr");
+ if (mac && strlen(mac) <= 17)
+ ptr += sprintf(ptr, "ethaddr=%s", mac) + 1;
+
+ for (i = 1; i <= 3; i++) {
+ sprintf(eth, "eth%daddr", i);
+ mac = env_get(eth);
+ if (mac && strlen(mac) <= 17)
+ ptr += sprintf(ptr, "%s=%s", eth, mac) + 1;
+ }
+
/* If the memory controller has been configured for DDR4, we're running on v7 */
ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
& A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
if (env_get("fdtfile"))
return 0;
+ /* Ensure that 'env default -a' set correct value to $fdtfile */
if (ddr4 && emmc)
- env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
+ strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7-emmc.dtb");
else if (ddr4)
- env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
+ strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7.dtb");
else if (emmc)
- env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
+ strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb");
else
- env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
+ strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb");
+
+ /* If $fdtfile was not set explicitly by user then set default value */
+ if (!env_get("fdtfile"))
+ env_set("fdtfile", ptr + sizeof("fdtfile="));
return 0;
}
#include <dm.h>
#include <i2c.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <log.h>
#include <netdev.h>
#include <pci_ids.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <linux/libfdt.h>
#include <console.h>
#include <cpu_func.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/uclass-internal.h>
#include <env.h>
#include <init.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/arch/cpu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include "dockstar.h"
#include <init.h>
#include <miiphy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/setup.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <common.h>
#include <init.h>
#include <miiphy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <env.h>
#include <errno.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <asm/io.h>
#include <log.h>
#include <spl.h>
#include <fsl_esdhc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <net.h>
#include <netdev.h>
#include <led.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <asm/arch/cpu.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#include <i2c.h>
#include <init.h>
#include <wdt.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
#include <linux/mbus.h>
#include <env.h>
#include <fastboot.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/ctype.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
#include <common.h>
#include <dm.h>
+#include <adc.h>
#include <env.h>
#include <init.h>
#include <net.h>
#define EFUSE_MAC_SIZE 12
#define MAC_ADDR_LEN 6
+#define ODROID_HW_VS_ADC_CHANNEL 1
+
+#define MESON_SOC_ID_G12B 0x29
+#define MESON_SOC_ID_SM1 0x2b
+
int mmc_get_env_dev(void)
{
if (meson_get_boot_device() == BOOT_DEVICE_EMMC)
return 0;
}
+/* Variant detection is based on the ADC RAW values for the channel #1 */
+static struct meson_odroid_boards {
+ unsigned int soc_id;
+ unsigned int adc_min;
+ unsigned int adc_max;
+ char *variant;
+} boards[] = {
+ /* OdroidN2 rev 2018,7,23 */
+ { MESON_SOC_ID_G12B, 80 * 4, 90 * 4, "n2" },
+ /* OdroidN2 rev 2018,12,6 */
+ { MESON_SOC_ID_G12B, 160 * 4, 170 * 4, "n2" },
+ /* OdroidN2 rev 2019,1,17 */
+ { MESON_SOC_ID_G12B, 245 * 4, 255 * 4, "n2" },
+ /* OdroidN2 rev 2019,2,7 */
+ { MESON_SOC_ID_G12B, 330 * 4, 350 * 4, "n2" },
+ /* OdroidN2plus rev 2019,11,20 */
+ { MESON_SOC_ID_G12B, 410 * 4, 430 * 4, "n2_plus" },
+ /* OdroidC4 rev 2020,01,29 */
+ { MESON_SOC_ID_SM1, 80 * 4, 100 * 4, "c4" },
+ /* OdroidHC4 rev 2019,12,10 */
+ { MESON_SOC_ID_SM1, 300 * 4, 320 * 4, "hc4" },
+ /* OdroidC4 rev 2019,11,29 */
+ { MESON_SOC_ID_SM1, 335 * 4, 345 * 4, "c4" },
+ /* OdroidHC4 rev 2020,8,7 */
+ { MESON_SOC_ID_SM1, 590 * 4, 610 * 4, "hc4" },
+};
+
+static void odroid_set_fdtfile(char *soc, char *variant)
+{
+ char s[128];
+
+ snprintf(s, sizeof(s), "amlogic/meson-%s-odroid-%s.dtb", soc, variant);
+ env_set("fdtfile", s);
+}
+
+static int odroid_detect_variant(void)
+{
+ char *variant = "", *soc = "";
+ unsigned int adcval = 0;
+ int ret, i, soc_id = 0;
+
+ if (of_machine_is_compatible("amlogic,sm1")) {
+ soc_id = MESON_SOC_ID_SM1;
+ soc = "sm1";
+ } else if (of_machine_is_compatible("amlogic,g12b")) {
+ soc_id = MESON_SOC_ID_G12B;
+ soc = "g12b";
+ } else {
+ return -1;
+ }
+
+ ret = adc_channel_single_shot("adc@9000", ODROID_HW_VS_ADC_CHANNEL,
+ &adcval);
+ if (ret)
+ return ret;
+
+ for (i = 0 ; i < ARRAY_SIZE(boards) ; ++i) {
+ if (soc_id == boards[i].soc_id &&
+ adcval >= boards[i].adc_min &&
+ adcval < boards[i].adc_max) {
+ variant = boards[i].variant;
+ break;
+ }
+ }
+
+ printf("Board variant: %s\n", variant);
+ env_set("variant", variant);
+
+ odroid_set_fdtfile(soc, variant);
+
+ return 0;
+}
+
int misc_init_r(void)
{
u8 mac_addr[MAC_ADDR_LEN];
meson_generate_serial_ethaddr();
}
+ odroid_detect_variant();
return 0;
}
#include <asm/arch/boot.h>
#include <asm/arch/eth.h>
#include <asm/arch/sm.h>
+#include <asm/global_data.h>
#include <i2c.h>
#include "khadas-mcu.h"
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <common.h>
#include <hang.h>
#include <init.h>
+#include <asm/global_data.h>
#include <jffs2/jffs2.h>
#include <nand.h>
#include <netdev.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/platform_data/serial_pl01x.h>
#include "arm-ebi.h"
#include <dm.h>
#include <dm/platform_data/serial_pl01x.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
static const struct pl01x_serial_plat serial_plat = {
.base = UART0_BASE,
#include <errno.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/systimer.h>
#include <errno.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <dm/platform_data/serial_pl01x.h>
#include <serial.h>
#include <watchdog.h>
#include <command.h>
+#include <asm/global_data.h>
#include <asm/m5329.h>
#include <asm/immap_5329.h>
#include <asm/io.h>
#include <cpu_func.h>
#include <init.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <debug_uart.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <debug_uart.h>
#include <init.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9_smc.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9x5_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <debug_uart.h>
#include <init.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/at91sam9rl.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9x5_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <video.h>
#include <video_console.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <common.h>
#include <debug_uart.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <common.h>
#include <debug_uart.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <common.h>
#include <debug_uart.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <init.h>
#include <nand.h>
#include <version.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <common.h>
#include <debug_uart.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <common.h>
#include <debug_uart.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-if TARGET_BEACON_RZG2M
+if TARGET_BEACON_RZG2H || TARGET_BEACON_RZG2M || TARGET_BEACON_RZG2N
config SYS_SOC
default "rmobile"
F: board/beacon/beacon-rzg2m/
F: include/configs/beacon-rzg2m.h
F: configs/r8a774a1_beacon_defconfig
+F: configs/r8a774b1_beacon_defconfig
+F: configs/r8a774e1_beacon_defconfig
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/rcar-mstp.h>
#include <common.h>
#include <miiphy.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#include <log.h>
#include <asm/io.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mn_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/mx5_video.h>
#include <ACEX1K.h>
#include <asm/gpio.h>
+++ /dev/null
-if TARGET_APX4DEVKIT
-
-config SYS_BOARD
- default "apx4devkit"
-
-config SYS_VENDOR
- default "bluegiga"
-
-config SYS_SOC
- default "mxs"
-
-config SYS_CONFIG_NAME
- default "apx4devkit"
-
-endif
+++ /dev/null
-APX4DEVKIT BOARD
-M: Lauri Hintsala <lauri.hintsala@bluegiga.com>
-S: Maintained
-F: board/bluegiga/apx4devkit/
-F: include/configs/apx4devkit.h
-F: configs/apx4devkit_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifndef CONFIG_SPL_BUILD
-obj-y := apx4devkit.o
-else
-obj-y := spl_boot.o
-endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bluegiga APX4 Development Kit
- *
- * Copyright (C) 2012 Bluegiga Technologies Oy
- *
- * Authors:
- * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
- * Lauri Hintsala <lauri.hintsala@bluegiga.com>
- *
- * Based on m28evk.c:
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <env.h>
-#include <linux/mii.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Functions */
-int board_early_init_f(void)
-{
- /* IO0 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK0, 480000);
- /* IO1 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK1, 480000);
-
- /* SSP0 clock at 96MHz */
- mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
-
- return 0;
-}
-
-int dram_init(void)
-{
- return mxs_dram_init();
-}
-
-int board_init(void)
-{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(struct bd_info *bis)
-{
- return mxsmmc_initialize(bis, 0, NULL, NULL);
-}
-#endif
-
-
-#ifdef CONFIG_CMD_NET
-
-#define MII_PHY_CTRL2 0x1f
-int fecmxc_mii_postcall(int phy)
-{
- /* change PHY RMII clock to 50MHz */
- miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int ret;
- struct eth_device *dev;
-
- ret = cpu_eth_init(bis);
- if (ret) {
- printf("FEC MXS: Unable to init FEC clocks\n");
- return ret;
- }
-
- ret = fecmxc_initialize(bis);
- if (ret) {
- printf("FEC MXS: Unable to init FEC\n");
- return ret;
- }
-
- dev = eth_get_dev_by_name("FEC");
- if (!dev) {
- printf("FEC MXS: Unable to get FEC device entry\n");
- return -EINVAL;
- }
-
- ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
- if (ret) {
- printf("FEC MXS: Unable to register FEC MII postcall\n");
- return ret;
- }
-
- return ret;
-}
-#endif
-
-#ifdef CONFIG_SERIAL_TAG
-#define MXS_OCOTP_MAX_TIMEOUT 1000000
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- struct mxs_ocotp_regs *ocotp_regs =
- (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
-
- serialnr->high = 0;
- serialnr->low = 0;
-
- writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
-
- if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
- MXS_OCOTP_MAX_TIMEOUT)) {
- printf("MXS: Can't get serial number from OCOTP\n");
- return;
- }
-
- serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
-{
- if (env_get("revision#") != NULL)
- return simple_strtoul(env_get("revision#"), NULL, 10);
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bluegiga APX4 Development Kit
- *
- * Copyright (C) 2012 Bluegiga Technologies Oy
- *
- * Authors:
- * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
- * Lauri Hintsala <lauri.hintsala@bluegiga.com>
- *
- * Based on spl_boot.c:
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-
-const iomux_cfg_t iomux_setup[] = {
- /* DUART */
- MX28_PAD_PWM0__DUART_RX,
- MX28_PAD_PWM1__DUART_TX,
-
- /* LED */
- MX28_PAD_PWM3__GPIO_3_28,
-
- /* MMC0 */
- MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
- MX28_PAD_SSP0_SCK__SSP0_SCK |
- (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
- /* GPMI NAND */
- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDN__GPMI_RDN |
- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
-
- /* FEC0 */
- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
-
- /* I2C */
- MX28_PAD_I2C0_SCL__I2C0_SCL,
- MX28_PAD_I2C0_SDA__I2C0_SDA,
-
- /* EMI */
- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
-
- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
-};
-
-void board_init_ll(const uint32_t arg, const uint32_t *resptr)
-{
- mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
-
- /* switch LED on */
- gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
-}
-
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-{
- /*
- * All address lines are routed from CPU to memory chip.
- * ADDR_PINS field is set to zero.
- */
- dram_vals[0x74 >> 2] = 0x0f02000a;
-
- /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */
- dram_vals[0x7c >> 2] = 0x00000101;
-}
#ifndef CONFIG_DM_ETH
#include <netdev.h>
#endif
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <common.h>
#include <dm.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <led.h>
#include <miiphy.h>
#include <panel.h>
+#include <asm/global_data.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <spl.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <env.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <common.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <env.h>
#include <common.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <env.h>
#include <init.h>
#include <net.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <config.h>
#include <netdev.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/gic-v3.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-bcmns3/bl33_info.h>
#include <init.h>
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <linux/types.h>
#include <common.h>
#include <env.h>
#include <common.h>
#include <init.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <serial.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mpp.h>
#include <asm/arch/gpio.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include "lsxl.h"
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <errno.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <cavium/atf.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <net.h>
#include <netdev.h>
#include <status_led.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/ep93xx.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
#include "pogo_e02.h"
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#include <phy.h>
#include <netdev.h>
#include <fsl_esdhc_imx.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
#include <net.h>
#include <status_led.h>
#include <cpsw.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/arch/sys_proto.h>
#include <miiphy.h>
#include <cpsw.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/emif.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <common.h>
#include <asm/arch/sysinfo.h>
+#include <asm/global_data.h>
#include <init.h>
#include <smbios.h>
#include <malloc.h>
#include <twl4030.h>
#include <status_led.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <errno.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <mpc8xx.h>
#include <fdt_support.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/uclass.h>
#include <wdt.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/arch/gpio.h>
+#include <asm/global_data.h>
#include "dns325.h"
DECLARE_GLOBAL_DATA_PTR;
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <init.h>
#include <net.h>
#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/io.h>
#include <ns16550.h>
#include <image.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <net.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <bootm.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mx7ulp-pins.h>
#include <i2c.h>
#include <watchdog.h>
#include <debug_uart.h>
+#include <asm/global_data.h>
#include <dm/ofnode.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <i2c.h>
#include <mmc.h>
#include <atmel_mci.h>
+#include <asm/global_data.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <env.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <common.h>
#include <init.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rv1108.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <efi_loader.h>
#include <env.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include "board.h"
#include <net.h>
#include <serial.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mpc8349_pci.h>
#if defined(CONFIG_OF_LIBFDT)
#include <linux/libfdt.h>
#include <hang.h>
#include <led.h>
#include <log.h>
+#include <asm/global_data.h>
#ifdef CONFIG_SPL_BUILD
DECLARE_GLOBAL_DATA_PTR;
obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
-obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
obj-$(CONFIG_P2020DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#ifndef CONFIG_ARMV7_NONSEC
#error " Deep sleep needs non-secure mode support. "
u8 temp;
u16 temp1, temp2;
u32 temp3;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
u8 temp;
temp = I2C_DVI_TEST_PATTERN_VAL;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
#include <common.h>
#include <command.h>
#include <i2c.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include "emc2305.h"
I2C_EMC2305_FAN5};
for (index = 0; index < NUM_OF_FANS; index++) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
if (i2c_write(chip_addr, Fan[index], 1, &data, 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
u8 data;
data = I2C_EMC2305_CMD;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
if (i2c_write(chip_addr, I2C_EMC2305_CONF, 1, &data, 1) != 0)
printf("Error: failed to configure EMC2305\n");
#else
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/immap_85xx.h>
#include "sleep.h"
#ifdef CONFIG_U_QE
u8 vtempmax[2];
u8 res2[4];
} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8544DS)
-typedef struct pixis {
- u8 id;
- u8 ver;
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr;
- u8 aux1;
- u8 spd;
- u8 res[8];
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[2];
- u8 vclkh;
- u8 vclkl;
- u8 watch;
- u8 led;
- u8 vspeed2;
- u8 res2[34];
-} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8572DS)
-typedef struct pixis {
- u8 id;
- u8 ver;
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr1;
- u8 aux1;
- u8 spd;
- u8 aux2;
- u8 res[7];
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[3];
- u8 res2[2];
- u8 sclk[3];
- u8 dclk[3];
- u8 res3[2];
- u8 watch;
- u8 led;
- u8 res4[25];
-} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8610HPCD)
-typedef struct pixis {
- u8 id;
- u8 ver; /* also called arch */
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr;
- u8 aux;
- u8 spd;
- u8 brdcfg0;
- u8 brdcfg1;
- u8 res[4];
- u8 led;
- u8 serno;
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[2];
- u8 res2;
- u8 sclk[3];
- u8 res3;
- u8 watch;
- u8 res4[33];
-} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8641HPCN)
-typedef struct pixis {
- u8 id;
- u8 ver;
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr;
- u8 aux;
- u8 spd;
- u8 res[8];
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[2];
- u8 vclkh;
- u8 vclkl;
- u8 watch;
- u8 res3[36];
-} __attribute__ ((packed)) pixis_t;
#else
#error Need to define pixis_t for this board
#endif
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
#else
struct udevice *dev;
void qixis_write_i2c(unsigned int reg, u8 value)
{
u8 val = value;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
#else
struct udevice *dev;
{
int ret;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
unsigned int bus;
#endif
#endif
return 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
#endif
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e, sizeof(e));
#endif
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_set_bus_num(bus);
#endif
#endif
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
unsigned int bus;
#endif
#endif
#endif
update_crc();
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
* complete a given write.
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((int)(sizeof(e) - i), 8));
/* Verify the write by reading back the EEPROM and comparing */
struct eeprom e2;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e2, sizeof(e2));
ret = -1;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
u8 minor; /* 0x05 Board revision, minor */
} be;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&be, sizeof(be));
#else
u8 byte;
int i;
const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
/* Check all the address */
for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
i2caddress = ir_i2c_addr[i];
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(i2caddress,
IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
sizeof(byte));
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf[2];
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
for (i = 0; i < NUM_READINGS; i++) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
(void *)&buf, 2);
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
for (i = 0; i < NUM_READINGS; i++) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(i2caddress,
IR36021_LOOP1_VOUT_OFFSET,
1, (void *)&buf, 1);
int ret, vcode = 0;
u8 chan = PWM_CHANNEL0;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/* select the PAGE 0 using PMBus commands PAGE for VDD*/
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
return ret;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/*read the output voltage using PMBus command READ_VOUT*/
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
vid = DIV_ROUND_UP(vdd - 245, 5);
#endif
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
#else
vdd & 0xFF, (vdd & 0xFF00) >> 8};
/* Write the desired voltage code to the regulator */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/* Check write protect state */
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_WRITE_PROTECT, 1,
}
/* check IR chip work on Intel mode*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
}
/* check IR chip work on Intel mode*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
/* enable 2-wire Serial InterFace (I2C) */
data = 0x02;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int ret, bus_num = 0;
struct udevice *dev;
debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
" for Tx\n", vsc_addr);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int bus_num = 0;
struct udevice *dev;
debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
vsc_addr);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int bus_num = 0;
struct udevice *dev;
debug("VSC:Initializing VSC3308 at I2C address 0x%x"
" for Tx\n", vsc_addr);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int bus_num = 0;
struct udevice *dev;
/* For new crosspoint configuration to occur, WP bit of
* CORE_CONFIG_REG should be set 1 and then reset to 0 */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int ret, bus_num = 0;
struct udevice *dev;
#include <image.h>
#include <init.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <init.h>
#include <log.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/clock.h>
#include <common.h>
#include <env.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/clock.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/delay.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <asm/arch/imx8mp_pins.h>
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <image.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <env.h>
#include <errno.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <env.h>
#include <errno.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fsl_esdhc_imx.h>
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <log.h>
#include <ram.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <log.h>
#include <ram.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <i2c.h>
#include <asm/cache.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <fdt_support.h>
#include <asm/cache.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
u8 mux_sdhc_cd = 0x80;
int bus_num = 0;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
{
#ifdef CONFIG_TARGET_LS1012ARDB
/* Through reset IO expander reset both RGMII and SGMII PHYs */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
#include <i2c.h>
#include <asm/cache.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
puts("Board: LS1012ARDB ");
/* Initialize i2c early for Serial flash bank information */
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
u8 io = 0;
int ret, bus_num = 0;
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
* 10 - eMMC Memory
* 11 - SPI
*/
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
#else
ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
int ret, bus_num = 0;
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
u8 chip_addr = 0x24;
int ret, i, bus_num = 0;
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
* CS routed to SPI memory bank2
*/
for (i = 0; i < sizeof(data); i++) {
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
#else /* Non DM I2C support - will be removed */
ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
#include <common.h>
#include <fsl_dcu_fb.h>
+#include <asm/global_data.h>
#include "div64.h"
#include "../common/dcu_sii9022a.h"
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/arch/ls102xa_devdis.h>
* FSL DCU Framebuffer driver
*/
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_dcu_fb.h>
static int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
u8 ch;
/* Mux I2C3+I2C4 as HSYNC+VSYNC */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
/* QIXIS device mount on I2C1 bus*/
pixval = 1000000000 / dcu_fb_videomode->pixclock;
pixval *= 1000;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
#include <fsl_ddr_dimm_params.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <linux/delay.h>
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include "../common/sleep.h"
#include <fsl_validate.h>
#include <common.h>
#include <fsl_dcu_fb.h>
+#include <asm/global_data.h>
#include "div64.h"
#include "../common/dcu_sii9022a.h"
#include <i2c.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#define MC34VR500_ADDR 0x8
#define MC34VR500_DEVICEID 0x4
#define MC34VR500_DEVICEID_MASK 0x0f
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <errno.h>
#include <fsl_ddr.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <hwconfig.h>
#include <fdt_support.h>
#if defined(CONFIG_TARGET_LS1028ARDB)
u8 val = I2C_MUX_CH_DEFAULT;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
#else
struct udevice *dev;
#endif
#include <log.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
#include <fsl_ddr_sdram.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
/* Retimer is connected to I2C1_CH7_CH5 */
select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
reg = I2C_MUX_CH5;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
#include "ddr.h"
#include <log.h>
#include <vsprintf.h>
#include <common.h>
#include <i2c.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <common.h>
#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <i2c.h>
#include <fdt_support.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
#endif
#include <log.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
#include "ddr.h"
#ifdef CONFIG_FSL_DEEP_SLEEP
#include <fsl_sleep.h>
#include <i2c.h>
#include <fdt_support.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <log.h>
#include <asm/arch/soc.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
{0x18, NULL}, {0x23, ®_val[3]},
{0x2d, ®_val[4]}, {4, ®_val[5]},
};
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
return;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
#endif
reg_pair[5].val = &ch_b_eq[i];
reg_pair[6].val = &ch_b_ctl2[j];
for (k = 0; k < 10; k++) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(i2c_phy_addr,
reg_pair[k].addr,
1, reg_pair[k].val, 1);
const char *dev = mdio_names[EMI1_SLOT1];
int ret = 0;
unsigned short value;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
return;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
#endif
reg_pair[6].val = &ch_b_ctl2[j];
for (k = 0; k < 10; k++) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(i2c_phy_addr,
reg_pair[k].addr,
1, reg_pair[k].val, 1);
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <fsl_sec.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/delay.h>
{
int ret;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
/* Access to Control/Shared register */
reg = 0x0;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
#else
struct udevice *dev;
#endif
/* Read device revision and ID */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
#else
dm_i2c_read(dev, 1, ®, 1);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
#else
dm_i2c_write(dev, 0xff, ®, 1);
#endif
/* Reset Channel Registers */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
#else
dm_i2c_read(dev, 0, ®, 1);
#endif
reg |= 0x4;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
#else
dm_i2c_write(dev, 0, ®, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
#else
dm_i2c_write(dev, 0x60, ®, 1);
#endif
reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
#else
dm_i2c_write(dev, 0x61, ®, 1);
#endif
reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
#else
dm_i2c_write(dev, 0x62, ®, 1);
#endif
reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
#else
dm_i2c_write(dev, 0x63, ®, 1);
#endif
reg = 0xcd;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
#else
dm_i2c_write(dev, 0x64, ®, 1);
#endif
/* Select VCO Divider to full rate (000) */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
#else
dm_i2c_read(dev, 0x2F, ®, 1);
#endif
reg &= 0x0f;
reg |= 0x70;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
#else
dm_i2c_write(dev, 0x2F, ®, 1);
/* Access to Control/Shared register */
reg = 0x0;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
#else
i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
#endif
/* Read device revision and ID */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
#else
dm_i2c_read(dev, 1, ®, 1);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
#else
dm_i2c_write(dev, 0xff, ®, 1);
#endif
/* Reset Channel Registers */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
#else
dm_i2c_read(dev, 0, ®, 1);
#endif
reg |= 0x4;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
#else
dm_i2c_write(dev, 0, ®, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
#else
dm_i2c_write(dev, 0x60, ®, 1);
#endif
reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
#else
dm_i2c_write(dev, 0x61, ®, 1);
#endif
reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
#else
dm_i2c_write(dev, 0x62, ®, 1);
#endif
reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
#else
dm_i2c_write(dev, 0x63, ®, 1);
#endif
reg = 0xcd;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
#else
dm_i2c_write(dev, 0x64, ®, 1);
#endif
/* Select VCO Divider to full rate (000) */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
#else
dm_i2c_read(dev, 0x2F, ®, 1);
#endif
reg &= 0x0f;
reg |= 0x70;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
#else
dm_i2c_write(dev, 0x2F, ®, 1);
u8 chan = PWM_CHANNEL0;
/* Select the PAGE 0 using PMBus commands PAGE for VDD */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
#else
}
/* Read the output voltage using PMBus command READ_VOUT */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
#else
svdd & 0xFF, (svdd & 0xFF00) >> 8};
/* Write the desired voltage code to the SVDD regulator */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
#else
printf("SVDD changing of RDB\n");
/* Read the BRDCFG54 via CLPD */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
brdcfg4 = brdcfg4 | 0x08;
/* Write to the BRDCFG4 */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
+++ /dev/null
-if TARGET_LS2080A_EMU
-
-config SYS_BOARD
- default "ls2080a"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2080a_emu"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
-if TARGET_LS2080A_SIMU
-
-config SYS_BOARD
- default "ls2080a"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2080a_simu"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/ls2080a/
-F: include/configs/ls2080a_emu.h
-F: configs/ls2080a_emu_defconfig
-F: include/configs/ls2080a_simu.h
-F: configs/ls2080a_simu_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2014-15 Freescale Semiconductor
-
-obj-y += ls2080a.o
-obj-y += ddr.o
+++ /dev/null
-Freescale ls2080a_emu
-
-This is a emulator target with limited peripherals.
-
-Memory map from core's view
-
-0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
-0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
-0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
-0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
-0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
-0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
-0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
-
-Other addresses are either reserved, or not used directly by U-Boot.
-This list should be updated when more addresses are used.
-
-Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
--------------------------------------------------------------------
-One needs to use appropriate bootargs to boot Linux flavors which do
-not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
-below:
-
-=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
- earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
- hugepages=16 mem=2048M'
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <log.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/clock.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 3) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (ctrl_num == CONFIG_DP_DDR_CTRL) {
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
- popts->bstopre = 0; /* enable auto precharge */
- }
-#endif
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-#else
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 1073741824u,
- .capacity = 2147483648,
- .primary_sdram_width = 64,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 937,
- .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
- .taa_ps = 13090,
- .twr_ps = 15000,
- .trcd_ps = 13090,
- .trrd_ps = 5000,
- .trp_ps = 13090,
- .tras_ps = 33000,
- .trc_ps = 46090,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 25000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if (((controller_number == 0) && (dimm_number == 0)) ||
- ((controller_number == 1) && (dimm_number == 0))) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif
-
-int fsl_initdram(void)
-{
- puts("Initializing DDR....");
-
- puts("using SPD\n");
- gd->ram_size = fsl_ddr_sdram();
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 2140, 0, 4, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters udimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 2140, 0, 4, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 2140, 0, 5, 4, 0x0, 0x0},
- {2, 2140, 0, 5, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters rdimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 2140, 0, 5, 4, 0x0, 0x0},
- {2, 2140, 0, 5, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
- udimm2,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
- rdimm2,
-};
-
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor
- */
-#include <common.h>
-#include <init.h>
-#include <malloc.h>
-#include <errno.h>
-#include <net.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <fsl_ddr.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <fsl-mc/fsl_mc.h>
-#include <env_internal.h>
-#include <asm/arch/soc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- init_final_memctl_regs();
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
-
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
- print_ddr_info(0);
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
- puts("\nDP-DDR ");
- print_size(gd->bd->bi_dram[2].size, "");
- print_ddr_info(CONFIG_DP_DDR_CTRL);
- }
-#endif
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int error = 0;
-
-#ifdef CONFIG_SMC91111
- error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- error = cpu_eth_init(bis);
-#endif
- return error;
-}
-
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-void fdt_fixup_board_enet(void *fdt)
-{
- int offset;
-
- offset = fdt_path_offset(fdt, "/soc/fsl-mc");
-
- /*
- * TODO: Remove this when backward compatibility
- * with old DT node (/fsl-mc) is no longer needed.
- */
- if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl-mc");
-
- if (offset < 0) {
- printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
- __func__, offset);
- return;
- }
-
- if (get_mc_boot_status() == 0 &&
- (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
- fdt_status_okay(fdt, offset);
- else
- fdt_status_fail(fdt, offset);
-}
-
-void board_quiesce_devices(void)
-{
- fsl_mc_ldpaa_exit(gd->bd);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- ft_cpu_setup(blob, bd);
-
- /* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
-#ifdef CONFIG_RESV_RAM
- /* reduce size if reserved memory is within this bank */
- if (gd->arch.resv_ram >= base[0] &&
- gd->arch.resv_ram < base[0] + size[0])
- size[0] = gd->arch.resv_ram - base[0];
- else if (gd->arch.resv_ram >= base[1] &&
- gd->arch.resv_ram < base[1] + size[1])
- size[1] = gd->arch.resv_ram - base[1];
-#endif
-
- fdt_fixup_memory_banks(blob, base, size, 2);
-
- fdt_fsl_mc_fixup_iommu_map_entry(blob);
-
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_RESET_PHY_R)
-void reset_phy(void)
-{
-}
-#endif
-
-#ifdef CONFIG_TFABOOT
-void *env_sf_get_env_addr(void)
-{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
-}
-#endif
#include <log.h>
#include <asm/arch/soc.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
};
int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
mii_bus = 1;
dpmac_id = dpmac + 9;
a = 0xb;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(0x76, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
reg_pair[6].val = &ch_b_ctl2[j];
for (k = 0; k < 10; k++) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(i2c_addr[dpmac],
reg_pair[k].addr,
1, reg_pair[k].val, 1);
const char *dev = "LS2080A_QDS_MDIO0";
int ret = 0;
unsigned short value;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
reg_pair[6].val = &ch_b_ctl2[j];
for (k = 0; k < 10; k++) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(i2c_phy_addr,
reg_pair[k].addr,
1, reg_pair[k].val, 1);
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
#else
rtc_enable_32khz_output();
#include <log.h>
#include <asm/arch/soc.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <hwconfig.h>
#include <fdt_support.h>
{
int ret;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <exports.h>
+#include <asm/global_data.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <clock_legacy.h>
#include <dm.h>
#include <init.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_pl01x.h>
#include <i2c.h>
#include <malloc.h>
{
int ret;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
#include <config.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <config.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <command.h>
#include <init.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <linux/delay.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <netdev.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#include <config.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <config.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <config.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <common.h>
#include <init.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/immap.h>
#include <mmc.h>
#include <common.h>
#include <init.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <common.h>
#include <init.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <common.h>
#include <init.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <common.h>
#include <init.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <common.h>
#include <init.h>
#include <mpc83xx.h>
+#include <asm/global_data.h>
#include <asm/bitops.h>
#include <asm/io.h>
#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
#include <asm/gpio.h>
#endif
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/bitops.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <init.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/bitops.h>
#include <i2c.h>
#include <miiphy.h>
#include <command.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <u-boot/crc.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
+#include <asm/global_data.h>
#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <linux/libfdt.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spi.h>
#endif
#include <spd_sdram.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <linux/libfdt.h>
#include <init.h>
#include <net.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <init.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <fdt_support.h>
int board_early_init_f(void)
{
-#ifdef CONFIG_FSL_SERDES
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_SERDES
u32 spridr = in_be32(&immr->sysconf.spridr);
/* we check only part num, and don't look for CPU revisions */
break;
}
#endif /* CONFIG_FSL_SERDES */
+
+#ifdef CONFIG_FSL_ESDHC
+ clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+ clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
+#endif
return 0;
}
#ifdef CONFIG_FSL_ESDHC
+#if !(CONFIG_IS_ENABLED(DM_MMC))
int board_mmc_init(struct bd_info *bd)
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
return fsl_esdhc_mmc_init(bd);
}
#endif
+#endif
/*
* Miscellaneous late-boot configurations
+++ /dev/null
-if TARGET_MPC8544DS
-
-config SYS_BOARD
- default "mpc8544ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8544DS"
-
-endif
+++ /dev/null
-MPC8544DS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8544ds/
-F: include/configs/MPC8544DS.h
-F: configs/MPC8544DS_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8544ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
-The MPC8544DS system is similar to the 85xx CDS systems such
-as the MPC8548CDS due to the similar E500 core. However, it
-is placed on the same board as the 8641 HPCN system.
-
-
-Flash Banks
------------
-Like the 85xx CDS systems, the 8544 DS board has two flash banks.
-They are both present on boot, but there locations can be swapped
-using the dip-switch SW10, bit 2.
-
-However, unlike the CDS systems, but similar to the 8641 HPCN
-board, a runtime reset through the FPGA can also affect a swap
-on the flash bank mappings for the next reset cycle.
-
-Irrespective of the switch SW10[2], booting is always from the
-boot bank at 0xfff8_0000.
-
-
-Memory Map
-----------
-
-0xff80_0000 - 0xffbf_ffff Alternate bank 4MB
-0xffc0_0000 - 0xffff_ffff Boot bank 4MB
-
-0xffb8_0000 Alternate image start 512KB
-0xfff8_0000 Boot image start 512KB
-
-
-Flashing Images
----------------
-
-For example, to place a new image in the alternate flash bank
-and then reset with that new image temporarily, use this:
-
- tftp 1000000 u-boot.bin.8544ds
- erase ffb80000 ffbfffff
- cp.b 1000000 ffb80000 80000
- pixis_reset altbank
-
-
-To overwrite the image in the boot flash bank:
-
- tftp 1000000 u-boot.bin.8544ds
- protect off all
- erase fff80000 ffffffff
- cp.b 1000000 fff80000 80000
-
-Other example U-Boot image and flash manipulations examples
-can be found in the README.mpc85xxcds file as well.
-
-
-The pixis_reset command
------------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
- /* reset board, use alternate flash bank with watchdog timer enabled*/
- pixis_reset altbank wd
-
- /* reset board to alternate bank with frequency changed.
- * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
- */
- pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
-
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
-
-After placing the DTB file in your TFTP disk area,
-you can download that dtb file using a command like:
-
- tftp 900000 mpc8544ds.dtb
-
-Burn it to flash if you want.
-
-
-Booting Linux
--------------
-
-Place a linux uImage in the TFTP disk area too.
-
- tftp 1000000 uImage.8544
- tftp 900000 mpc8544ds.dtb
- bootm 1000000 - 900000
-
-Watch your ethact, netdev and bootargs U-Boot environment variables.
-You may want to do something like this too:
-
- setenv ethact eTSEC3
- setenv netdev eth1
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /* 2T timing enable */
- popts->twot_en = 1;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-
-#include "../common/sgmii_riser.h"
-
-int checkboard (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- if ((uint)&gur->porpllsr != 0xe00e0000) {
- printf("immap size error %lx\n",(ulong)&gur->porpllsr);
- }
- printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- if (vboot & PIXIS_VBOOT_FMAP)
- printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
- else
- puts ("Promjet\n");
-
- lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
- lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
- ecm->eedr = 0xffffffff; /* Clear ecm errors */
- ecm->eeer = 0xffffffff; /* Enable ecm errors */
-
- return 0;
-}
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
-void pci_init_board(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr, io_sel;
- u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
- int first_free_busno = 0;
-
- int pcie_ep, pcie_configured;
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- porpllsr = in_be32(&gur->porpllsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
- puts("\n");
-
-#ifdef CONFIG_PCIE3
- pcie_configured = is_serdes_configured(PCIE3);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
- /* contains both PCIE3 MEM & IO space */
- set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
- LAW_TRGT_IF_PCIE_3);
- SET_STD_PCIE_INFO(pci_info, 3);
- pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
-
- /* outbound memory */
- pci_set_region(&pcie3_hose.regions[0],
- CONFIG_SYS_PCIE3_MEM_BUS2,
- CONFIG_SYS_PCIE3_MEM_PHYS2,
- CONFIG_SYS_PCIE3_MEM_SIZE2,
- PCI_REGION_MEM);
-
- pcie3_hose.region_count = 1;
-
- printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info.regs);
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pcie3_hose, first_free_busno);
-
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- */
- in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
- } else {
- printf("PCIE3: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
- SET_STD_PCIE_INFO(pci_info, 1);
- first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
-#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
- SET_STD_PCIE_INFO(pci_info, 2);
- first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
-#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCI1
- pci_speed = 66666000;
- pci_32 = 1;
- pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33333000) ? "33" :
- (pci_speed == 66666000) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter",
- pci_info.regs);
-
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-
-int last_stage_init(void)
-{
- return 0;
-}
-
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 i, go_bit, rd_clks;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- go_bit = in_8(pixis_base + PIXIS_VCTL);
- go_bit &= 0x01;
-
- rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
- rd_clks &= 0x1C;
-
- /*
- * Only if both go bit and the SCLK bit in VCFGEN0 are set
- * should we be using the AUX register. Remember, we also set the
- * GO bit to boot from the alternate bank on the on-board flash
- */
-
- if (go_bit) {
- if (rd_clks == 0x1c)
- i = in_8(pixis_base + PIXIS_AUX);
- else
- i = in_8(pixis_base + PIXIS_SPD);
- } else {
- i = in_8(pixis_base + PIXIS_SPD);
- }
-
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83000000;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
-
- return val;
-}
-
-
-#define MIIM_CIS8204_SLED_CON 0x1b
-#define MIIM_CIS8204_SLEDCON_INIT 0x1115
-/*
- * Hack to write all 4 PHYs with the LED values
- */
-int board_phy_config(struct phy_device *phydev)
-{
- static int do_once;
- uint phyid;
- struct mii_dev *bus = phydev->bus;
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- if (do_once)
- return 0;
-
- for (phyid = 0; phyid < 4; phyid++)
- bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
- MIIM_CIS8204_SLEDCON_INIT);
-
- do_once = 1;
-
- return 0;
-}
-
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
- if (is_serdes_configured(SGMII_TSEC1) ||
- is_serdes_configured(SGMII_TSEC3)) {
- fsl_sgmii_riser_init(tsec_info, num);
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- /*
- * TLB 0: 64M Non-cacheable, guarded
- * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
- /*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 1G PCIE 8,9,a,b
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1G, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe100_0000 255M PCI IO range
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_MPC8572DS
-
-config SYS_BOARD
- default "mpc8572ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8572DS"
-
-endif
+++ /dev/null
-MPC8572DS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8572ds/
-F: include/configs/MPC8572DS.h
-F: configs/MPC8572DS_defconfig
-F: configs/MPC8572DS_36BIT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8572ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
-MPC8572DS is a high-performance computing, evaluation and development platform
-supporting the mpc8572 PowerTM processor.
-
-Building U-Boot
------------
- make MPC8572DS_config
- make
-
-Flash Banks
------------
-MPC8572DS board has two flash banks. They are both present on boot, but their
-locations can be swapped using the dip-switch SW9[1:2].
-
-Booting is always from the boot bank at 0xec00_0000.
-
-
-Memory Map
-----------
-
-0xe800_0000 - 0xebff_ffff Alternate bank 64MB
-0xec00_0000 - 0xefff_ffff Boot bank 64MB
-
-0xebf8_0000 - 0xebff_ffff Alternate U-Boot address 512KB
-0xeff8_0000 - 0xefff_ffff Boot U-Boot address 512KB
-
-
-Flashing Images
----------------
-
-To place a new U-Boot image in the alternate flash bank and then reset with that
- new image temporarily, use this:
-
- tftp 1000000 u-boot.bin
- erase ebf80000 ebffffff
- cp.b 1000000 ebf80000 80000
- pixis_reset altbank
-
-
-To program the image in the boot flash bank:
-
- tftp 1000000 u-boot.bin
- protect off all
- erase eff80000 ffffffff
- cp.b 1000000 eff80000 80000
-
-
-The pixis_reset command
------------------------
-The command - "pixis_reset", is introduced to reset mpc8572ds board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples:
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
-
-
-Booting Linux
--------------
-
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage.8572
- tftp c00000 mpc8572ds.dtb
- bootm 1000000 - c00000
-
-
-Implementing AMP(Asymmetric MultiProcessing)
--------------
-1. Build kernel image for core0:
-
- a. $ make 85xx/mpc8572_ds_defconfig
-
- b. $ make menuconfig
- - un-select "Processor support"->"Symetric multi-processing support"
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
-
-2. Build kernel image for core1:
-
- a. $ make 85xx/mpc8572_ds_defconfig
-
- b. $ make menuconfig
- - Un-select "Processor support"->"Symetric multi-processing support"
- - Select "Advanced setup" -> " Prompt for advanced kernel
- configuration options"
- - Select "Set physical address where the kernel is loaded" and
- set it to 0x20000000, assuming core1 will start from 512MB.
- - Select "Set custom page offset address"
- - Select "Set custom kernel base address"
- - Select "Set maximum low memory"
- - "Exit" and save the selection.
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
-
-3. Create dtb for core0:
-
- $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
-
-4. Create dtb for core1:
-
- $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
-
-5. Bring up two cores separately:
-
- a. Power on the board, under U-Boot prompt:
- => setenv <serverip>
- => setenv <ipaddr>
- => setenv bootargs root=/dev/ram rw console=ttyS0,115200
- b. Bring up core1's kernel first:
- => setenv bootm_low 0x20000000
- => setenv bootm_size 0x10000000
- => tftp 21000000 8572/uImage.core1
- => tftp 22000000 8572/ramdiskfile
- => tftp 20c00000 8572/mpc8572ds_core1.dtb
- => interrupts off
- => bootm start 21000000 22000000 20c00000
- => bootm loados
- => bootm ramdisk
- => bootm fdt
- => fdt boardsetup
- => fdt chosen $initrd_start $initrd_end
- => bootm prep
- => cpu 1 release $bootm_low - $fdtaddr -
- c. Bring up core0's kernel(on the same U-Boot console):
- => setenv bootm_low 0
- => setenv bootm_size 0x20000000
- => tftp 1000000 8572/uImage.core0
- => tftp 2000000 8572/ramdiskfile
- => tftp c00000 8572/mpc8572ds_core0.dtb
- => bootm 1000000 2000000 c00000
-
-Please note only core0 will run U-Boot, core1 starts kernel directly after
-"cpu release" command is issued.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
- * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
- * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
- * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
- * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
- *
- * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 8, 7, 5, 0},
- {2, 400, 8, 9, 5, 0},
- {2, 549, 8, 11, 5, 0},
- {2, 680, 8, 10, 5, 0},
- {2, 850, 8, 12, 5, 1},
- {1, 333, 6, 7, 3, 0},
- {1, 400, 6, 9, 3, 0},
- {1, 549, 6, 11, 3, 0},
- {1, 680, 1, 10, 5, 0},
- {1, 850, 1, 12, 5, 0},
- {}
-};
-
-static const struct board_specific_parameters udimm1[] = {
- /*
- * memory controller 1
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 8, 7, 5, 0},
- {2, 400, 8, 9, 5, 0},
- {2, 549, 8, 11, 5, 0},
- {2, 680, 8, 11, 5, 0},
- {2, 850, 8, 13, 5, 1},
- {1, 333, 6, 7, 3, 0},
- {1, 400, 6, 9, 3, 0},
- {1, 549, 6, 11, 3, 0},
- {1, 680, 1, 11, 6, 0},
- {1, 850, 1, 13, 6, 0},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm1,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 4, 7, 3, 0},
- {2, 400, 4, 9, 3, 0},
- {2, 549, 4, 11, 3, 0},
- {2, 680, 4, 10, 3, 0},
- {2, 850, 4, 12, 3, 1},
- {}
-};
-
-static const struct board_specific_parameters rdimm1[] = {
- /*
- * memory controller 1
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 4, 7, 3, 0},
- {2, 400, 4, 9, 3, 0},
- {2, 549, 4, 11, 3, 0},
- {2, 680, 4, 11, 3, 0},
- {2, 850, 4, 13, 3, 1},
- {}
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm1,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <tsec.h>
-#include <fsl_mdio.h>
-#include <netdev.h>
-
-#include "../common/sgmii_riser.h"
-
-int checkboard (void)
-{
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf("Board: MPC8572DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
- case PIXIS_VBOOT_LBMAP_NOR0:
- puts ("vBank: 0\n");
- break;
- case PIXIS_VBOOT_LBMAP_PJET:
- puts ("Promjet\n");
- break;
- case PIXIS_VBOOT_LBMAP_NAND:
- puts ("NAND\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR1:
- puts ("vBank: 1\n");
- break;
- }
-
- return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
- uint d_init;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-
-#if defined (CONFIG_DDR_ECC)
- ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
- ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
- ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
- udelay(1000);
- }
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- return 512 * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- struct pci_controller *hose;
-
- fsl_pcie_init_board(0);
-
- hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
-
- if (hose) {
- u32 temp32;
- u8 uli_busno = hose->first_busno + 2;
-
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- * Device 1d has the first on-board memory BAR.
- */
- pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
- PCI_BASE_ADDRESS_1, &temp32);
-
- if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
- void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
- temp32, 4, 0);
- debug(" uli1572 read to %p\n", p);
- in_be32(p);
- }
- }
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC4
- SET_STD_TSEC_INFO(tsec_info[num], 4);
- if (is_serdes_configured(SGMII_TSEC4)) {
- puts("eTSEC4 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_init(tsec_info, num);
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_NAND_SPL
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
- CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_MPC8610HPCD
-
-config SYS_BOARD
- default "mpc8610hpcd"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8610HPCD"
-
-endif
+++ /dev/null
-MPC8610HPCD BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8610hpcd/
-F: include/configs/MPC8610HPCD.h
-F: configs/MPC8610HPCD_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright 2007 Freescale Semiconductor, Inc.
-
-obj-y += mpc8610hpcd.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
-obj-y += law.o
-obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o
+++ /dev/null
-Freescale MPC8610HPCD board
-===========================
-
-
-Building U-Boot
----------------
-
- $ make MPC8610HPCD_config
- Configuring for MPC8610HPCD board...
-
- $ make
-
-
-Flashing U-Boot
----------------
-The flash is 128M starting at 0xF800_0000.
-
-The alternate image is at 0xFBF0_0000
-The boot image is at 0xFFF0_0000.
-
-
-To Flash U-Boot into the booting bank:
-
- tftp 1000000 u-boot.bin
- protect off all
- erase fff00000 +$filesize
- cp.b 1000000 fff00000 $filesize
-
-
-To Flash U-Boot into the alternate bank
-
- tftp 1000000 u-boot.bin
- erase fbf00000 +$filesize
- cp.b 1000000 fbf00000 $filesize
-
-
-pixis_reset command
--------------------
-A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
- /* reset board, use alternate flash bank with watchdog timer enabled*/
- pixis_reset altbank wd
-
- /* reset board to alternate bank with frequency changed.
- * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
- */
- pixis-reset altbank cf 40 2.5 10
-
-
-DIP Switch Settings
--------------------
-To manually switch the flash banks using the DIP switch
-settings, toggle both SW6:1 and SW6:2.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /* 2T timing enable */
- popts->twot_en = 1;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
-#endif
- SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void sdram_init(void);
-phys_size_t fixed_sdram(void);
-int mpc8610hpcd_diu_init(void);
-
-
-/* called before any console output */
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
-
- gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u8 tmp_val, version;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- /*Do not use 8259PIC*/
- tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
- out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
-
- /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
- version = in_8(pixis_base + PIXIS_PVER);
- if(version >= 0x07) {
- tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
- out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
- }
-
- /* Using this for DIU init before the driver in linux takes over
- * Enable the TFP410 Encoder (I2C address 0x38)
- */
-
- tmp_val = 0xBF;
- i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- /* Verify if enabled */
- tmp_val = 0;
- i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
- tmp_val = 0x10;
- i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- /* Verify if enabled */
- tmp_val = 0;
- i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
- return 0;
-}
-
-int checkboard(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- /*
- * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
- * bank and LBMAP=00 is the alternate bank. However, the pixis
- * altbank code can only set bits, not clear them, so we treat 00 as
- * the normal bank and 11 as the alternate.
- */
- switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
- case 0:
- puts("vBank: Standard\n");
- break;
- case 0x40:
- puts("Promjet\n");
- break;
- case 0x80:
- puts("NAND\n");
- break;
- case 0xC0:
- puts("vBank: Alternate\n");
- break;
- }
-
- mcm->abcr |= 0x00010000; /* 0 */
- mcm->hpmr3 = 0x80000008; /* 4c */
- mcm->hpmr0 = 0;
- mcm->hpmr1 = 0;
- mcm->hpmr2 = 0;
- mcm->hpmr4 = 0;
- mcm->hpmr5 = 0;
-
- return 0;
-}
-
-
-int dram_init(void)
-{
- phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
-
- setup_ddr_bat(dram_size);
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
- uint d_init;
-
- ddr->cs0_bnds = 0x0000001f;
- ddr->cs0_config = 0x80010202;
-
- ddr->timing_cfg_3 = 0x00000000;
- ddr->timing_cfg_0 = 0x00260802;
- ddr->timing_cfg_1 = 0x3935d322;
- ddr->timing_cfg_2 = 0x14904cc8;
- ddr->sdram_mode = 0x00480432;
- ddr->sdram_mode_2 = 0x00000000;
- ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
- ddr->sdram_data_init = 0xDEADBEEF;
- ddr->sdram_clk_cntl = 0x03800000;
- ddr->sdram_cfg_2 = 0x04400010;
-
-#if defined(CONFIG_DDR_ECC)
- ddr->err_int_en = 0x0000000d;
- ddr->err_disable = 0x00000000;
- ddr->err_sbe = 0x00010000;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
-
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
- udelay(1000);
-
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- return 512 * 1024 * 1024;
-#endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-
-#endif
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
- {}
-};
-#endif
-
-
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI */
-
-void pci_init_board(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- struct fsl_pci_info pci_info;
- u32 devdisr;
- int first_free_busno;
- int pci_agent;
-
- devdisr = in_be32(&gur->devdisr);
-
- first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
- if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI: connected to PCI slots as %s" \
- " (base address %lx)\n",
- pci_agent ? "Agent" : "Host",
- pci_info.regs);
-#ifndef CONFIG_PCI_PNP
- pci1_hose.config_table = pci_mpc86xxcts_config_table;
-#endif
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
-#endif
-
- fsl_pcie_init_board(first_free_busno);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
- return 0;
-}
-#endif
-
-/*
- * get_board_sys_clk
- * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333000;
- break;
- case 1:
- val = 39999600;
- break;
- case 2:
- val = 49999500;
- break;
- case 3:
- val = 66666000;
- break;
- case 4:
- val = 83332500;
- break;
- case 5:
- val = 99999000;
- break;
- case 6:
- val = 133332000;
- break;
- case 7:
- val = 166665000;
- break;
- }
-
- return val;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- out_8(pixis_base + PIXIS_RST, 0);
-
- while (1)
- ;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- * Authors: York Sun <yorksun@freescale.com>
- * Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_diu_fb.h>
-#include "../common/pixis.h"
-
-#define PX_BRDCFG0_DLINK 0x10
-#define PX_BRDCFG0_DVISEL 0x08
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
- unsigned long speed_ccb, temp, pixval;
-
- speed_ccb = get_bus_freq(0);
- temp = 1000000000/pixclock;
- temp *= 1000;
- pixval = speed_ccb / temp;
- debug("DIU pixval = %lu\n", pixval);
-
- /* Modify PXCLK in GUTS CLKDVDR */
- debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
- temp = *guts_clkdvdr & 0x2000FFFF;
- *guts_clkdvdr = temp; /* turn off clock */
- *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
- debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
- const char *name;
- int gamma_fix = 0;
- u32 pixel_format = 0x88883316;
- u8 temp;
-
- temp = in_8(&pixis->brdcfg0);
-
- if (strncmp(port, "dlvds", 5) == 0) {
- /* Dual link LVDS */
- gamma_fix = 1;
- temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL);
- name = "Dual-Link LVDS";
- } else if (strncmp(port, "lvds", 4) == 0) {
- /* Single link LVDS */
- temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK;
- name = "Single-Link LVDS";
- } else {
- /* DVI */
- if (in_8(&pixis->ver) == 1) /* Board version */
- pixel_format = 0x88882317;
- temp |= PX_BRDCFG0_DVISEL;
- name = "DVI";
- }
-
- printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
- out_8(&pixis->brdcfg0, temp);
-
- return fsl_diu_init(xres, yres, pixel_format, gamma_fix);
-}
+++ /dev/null
-if TARGET_MPC8641HPCN
-
-config SYS_BOARD
- default "mpc8641hpcn"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8641HPCN"
-
-endif
+++ /dev/null
-MPC8641HPCN BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8641hpcn/
-F: include/configs/MPC8641HPCN.h
-F: configs/MPC8641HPCN_defconfig
-F: configs/MPC8641HPCN_36BIT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8641hpcn.o
-obj-y += law.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
+++ /dev/null
-Freescale MPC8641HPCN board
-===========================
-
-Created 05/24/2006 Haiying Wang
--------------------------------
-
-1. Building U-Boot
-------------------
-The 86xx HPCN code base is known to compile using:
- Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
-
- $ make MPC8641HPCN_config
- Configuring for MPC8641HPCN board...
-
- $ make
-
-
-2. Switch and Jumper Setting
-----------------------------
-Jumpers:
- J14 Pins 1-2 (near plcc32 socket)
-
-Switches:
- SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
- 01100 :: CORE = 2.5:1
- 10000 :: CORE = 3:1
- 11100 :: CORE = 3.5:1
- 10100 :: CORE = 4:1
- 01110 :: CORE = 4.5:1
- SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
- 001 :: SYSCLK = 40MHz
-
- SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
- 0100 :: 4X
- 0110 :: 6X
- 1000 :: 8X
- 1010 :: 10X
- 1100 :: 12X
- 1110 :: 14X
- 0000 :: 16X
- SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
-
- SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
- 0100000 :: VCORE = 1.11V
- SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
- 1 :: VCC_PLAT = 1.0V
-
- SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
- SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
- SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
-
- SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
- 0 :: boot from PromJet
- SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
- halves (virtual banks)
- 0 :: normal
- SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
- SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
- 1:1 for PD6
- SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
- SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
-
- SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
- SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
- SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
- SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
- SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
- SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
-
- SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
- SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
- SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
- SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
- SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
- SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
- SW8(7) = 1 ACPWR = 1 :: non-battery
- SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
-
-
-3. Flash U-Boot
----------------
-The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
-It is possible to use either half to boot using U-Boot. Switch 5 bit 2
-is used for this purpose.
-
-0xEF800000 to 0xEFBFFFFF - 4MB
-0xEFC00000 to 0xEFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xEFF00000.
-When this bit is 1, U-Boot is at 0xEFB00000.
-
-Use the above mentioned flash commands to program the other half, and
-use switch 5, bit 2 to alternate between the halves. Note: The booting
-version of U-Boot will always be at 0xEFF00000.
-
-To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
-
- tftp 1000000 u-boot.bin
- protect off all
- erase eff00000 +$filesize
- cp.b 1000000 eff00000 $filesize
-
-or use tftpflash command:
- run tftpflash
-
-To Flash U-Boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
-
- tftp 1000000 u-boot.bin
- erase efb00000 +$filesize
- cp.b 1000000 efb00000 $filesize
-
-
-4. Memory Map
--------------
-NOTE: RIO and PCI are mutually exclusive, so they share an address
-
-For 32-bit U-Boot, devices are mapped so that the virtual address ==
-the physical address, and the map looks liks this:
-
- Memory Range Device Size
- ------------ ------ ----
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x9fff_ffff RIO MEM 512M
- 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
- 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
- 0xffe0_0000 0xffef_ffff CCSR 1M
- 0xffdf_0000 0xffdf_7fff PIXIS 8K
- 0xffdf_8000 0xffdf_ffff CF 8K
- 0xf840_0000 0xf840_3fff Stack space 32K
- 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
- 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
- 0xef80_0000 0xefff_ffff Flash 8M
-
-For 36-bit-enabled U-Boot, the virtual map is the same as for 32-bit.
-However, the physical map is altered to reside in 36-bit space, as follows.
-Addresses are no longer mapped with VA == PA. All accesses from
-software use the VA; the PA is only used for setting up windows
-and mappings. Note that with the exception of PCI MEM and RIO, the low
- 32 bits are the same as the VA above; only the top 4 bits vary:
-
- Memory Range Device Size
- ------------ ------ ----
- 0x0_0000_0000 0x0_7fff_ffff DDR 2G
- 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M
- 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M
- 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M
- 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
- 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
- 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
- 0x0_f840_0000 0xf_f840_3fff Stack space 32K
- 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
- 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
- 0xf_ef80_0000 0xf_efff_ffff Flash 8M
-
-5. pixis_reset command
---------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
- /* reset board, use alternate flash bank with watchdog timer enabled*/
- pixis_reset altbank wd
-
- /* reset board to alternate bank with frequency changed.
- * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
- */
- pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008,2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {4, 333, 7, 7, 3},
- {4, 549, 7, 9, 3},
- {4, 650, 7, 10, 4},
- {2, 333, 7, 7, 3},
- {2, 549, 7, 9, 3},
- {2, 650, 7, 10, 4},
- {1, 333, 7, 7, 3},
- {1, 549, 7, 9, 3},
- {1, 650, 7, 10, 4},
- {}
-};
-
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-const struct board_specific_parameters *dimms[] = {
- dimm0,
- dimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- unsigned int i;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (pdimm[i].n_ranks)
- break;
- }
- if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
- return;
-
- pbsp = dimms[ctrl_num];
-
- /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[i].n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /* 2T timing enable */
- popts->twot_en = 1;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M
- * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000 0x9fff_ffff RapidIO 512M
- * endif
- * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
- * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K
- * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K
- * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
- * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
- * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR doesn't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-#endif
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t fixed_sdram(void);
-
-int checkboard(void)
-{
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- if (vboot & PIXIS_VBOOT_FMAP)
- printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
- else
- puts ("Promjet\n");
-
- return 0;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
-
- setup_ddr_bat(dram_size);
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t
-fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
- ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
-
-#if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000008D;
- ddr->err_sbe = 0x00ff0000;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
-#if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-#else
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-#endif
- asm("sync; isync");
-
- udelay(500);
-#endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCIE1
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- */
- in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
- + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
-#endif /* CONFIG_PCIE1 */
-}
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- int off;
- u64 *tmp;
- int addrcells;
-
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
- /*
- * Warn if it looks like the device tree doesn't match u-boot.
- * This is just an estimation, based on the location of CCSR,
- * which is defined by the "reg" property in the soc node.
- */
- off = fdt_path_offset(blob, "/soc8641");
- addrcells = fdt_address_cells(blob, 0);
- tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
-
- if (tmp) {
- u64 addr;
-
- if (addrcells == 1)
- addr = *(u32 *)tmp;
- else
- addr = *tmp;
-
- if (addr != CONFIG_SYS_CCSRBAR_PHYS)
- printf("WARNING: The CCSRBAR address in your .dts "
- "does not match the address of the CCSR "
- "in u-boot. This means your .dts might "
- "be old.\n");
- }
-
- return 0;
-}
-#endif
-
-
-/*
- * get_board_sys_clk
- * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 i, go_bit, rd_clks;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- go_bit = in_8(pixis_base + PIXIS_VCTL);
- go_bit &= 0x01;
-
- rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
- rd_clks &= 0x1C;
-
- /*
- * Only if both go bit and the SCLK bit in VCFGEN0 are set
- * should we be using the AUX register. Remember, we also set the
- * GO bit to boot from the alternate bank on the on-board flash
- */
-
- if (go_bit) {
- if (rd_clks == 0x1c)
- i = in_8(pixis_base + PIXIS_AUX);
- else
- i = in_8(pixis_base + PIXIS_SPD);
- } else {
- i = in_8(pixis_base + PIXIS_SPD);
- }
-
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33000000;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66000000;
- break;
- case 4:
- val = 83000000;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 134000000;
- break;
- case 7:
- val = 166000000;
- break;
- }
-
- return val;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- /* Initialize TSECs */
- cpu_eth_init(bis);
- return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- out_8(pixis_base + PIXIS_RST, 0);
-
- while (1)
- ;
-}
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+++ /dev/null
-if TARGET_MX35PDK
-
-config SYS_BOARD
- default "mx35pdk"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx35"
-
-config SYS_CONFIG_NAME
- default "mx35pdk"
-
-endif
+++ /dev/null
-MX35PDK BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/freescale/mx35pdk/
-F: include/configs/mx35pdk.h
-F: configs/mx35pdk_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y := mx35pdk.o
-obj-y += lowlevel_init.o
+++ /dev/null
-Overview
---------------
-
-mx35pdk (known als as mx35_3stack) is a development board by Freescale.
-It consists of three pluggable board:
- - CPU module, with CPU, RAM, flash
- - Personality board, with most interfaces (USB, Network,..)
- - Debug board with JTAG header.
-
-The board is usually delivered with redboot. This howto explains how to boot
-a linux kernel and how to replace the original bootloader with U-Boot.
-
-The board is delivered with Redboot on the NAND flash. It is possible to
-switch the boot device with the switches SW1-SW2 on the Personality board,
-and with SW5-SW10 on the Debug board.
-
-Delivered Redboot script to start the kernel
----------------------------------------------------
-
-In redboot the following script is stored:
-
-fis load kernel
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
-
-Kernel is taken from flash. The image is in zImage format.
-
-Booting from NET, rootfs on NFS:
------------------------------------
-
-To change the script in redboot:
-
-load -r -b 0x100000 <path_to_zImage>
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
-
-If the ip address is not set, you can set it with :
-
-ip_address -l <board_ip/netmask> -h <server_ip>
-
-Linux partitions:
----------------------------
-
-As default, the board is shipped with these partition tables for NAND
-and for NOR:
-
-Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit":
-0x00000000-0x00100000 : "nand.bootloader"
-0x00100000-0x00600000 : "nand.kernel"
-0x00600000-0x06600000 : "nand.rootfs"
-0x06600000-0x06e00000 : "nand.configure"
-0x06e00000-0x80000000 : "nand.userfs"
-
-Creating 6 MTD partitions on "mxc_nor_flash.0":
-0x00000000-0x00080000 : "Bootloader"
-0x00080000-0x00480000 : "nor.Kernel"
-0x00480000-0x02280000 : "nor.userfs"
-0x02280000-0x03e80000 : "nor.rootfs"
-0x01fe0000-0x01fe3000 : "FIS directory"
-0x01fff000-0x04000000 : "Redboot config"
-
-NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS.
-For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
-
-However, the setup in redboot is not correct and does not use the whole flash.
-
-Better solution is to use the kernel parameter mtdparts.
-Here the resulting script to be defined in RedBoot with fconfig:
-
-load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
-
-Flashing U-Boot
---------------------------------
-
-U-Boot should be stored on the NOR flash.
-
-The boot storage can be select using the switches on the personality board
-(SW1-SW2) and on the DEBUG board (SW4-SW10).
-
-If something goes wrong flashing the bootloader, it is always possible to
-recover the board booting from the other device.
-
-Saving U-Boot in the NOR flash
----------------------------------
-
-Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
-the boot partition should be /dev/mtd0.
-
-Creating 6 MTD partitions on "mxc_nor_flash.0":
-0x00000000-0x00080000 : "Bootloader"
-0x00080000-0x00480000 : "nor.Kernel"
-0x00480000-0x02280000 : "nor.userfs"
-0x02280000-0x03e80000 : "nor.rootfs"
-0x01fe0000-0x01fe3000 : "FIS directory"
-0x01fff000-0x04000000 : "Redboot config"
-
-To erase the whole partition:
-$ flash_eraseall /dev/mtd0
-
-Writing U-Boot:
-dd if=u-boot.bin of=/dev/mtd0
-
-To boot from NOR, you have to select the switches as follows:
-
-Personality board
- SW2 all off
- SW1 all off
-
-Debug Board:
- SW5 0
- SW6 0
- SW7 0
- SW8 1
- SW9 1
- SW10 0
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include "mx35pdk.h"
-#include <asm/arch/lowlevel_macro.S>
-
-/*
- * return soc version
- * 0x10: TO1
- * 0x20: TO2
- * 0x30: TO3
- */
-.macro check_soc_version ret, tmp
- ldr \tmp, =IIM_BASE_ADDR
- ldr \ret, [\tmp, #IIM_SREV]
- cmp \ret, #0x00
- moveq \tmp, #ROMPATCH_REV
- ldreq \ret, [\tmp]
- moveq \ret, \ret, lsl #4
- addne \ret, \ret, #0x10
-.endm
-
-/* CPLD on CS5 setup */
-.macro init_debug_board
- ldr r0, =DBG_BASE_ADDR
- ldr r1, =DBG_CSCR_U_CONFIG
- str r1, [r0, #0x00]
- ldr r1, =DBG_CSCR_L_CONFIG
- str r1, [r0, #0x04]
- ldr r1, =DBG_CSCR_A_CONFIG
- str r1, [r0, #0x08]
-.endm
-
-/* clock setup */
-.macro init_clock
- ldr r0, =CCM_BASE_ADDR
-
- /* default CLKO to 1/32 of the ARM core*/
- ldr r1, [r0, #CLKCTL_COSR]
- bic r1, r1, #0x00000FF00
- bic r1, r1, #0x0000000FF
- mov r2, #0x00006C00
- add r2, r2, #0x67
- orr r1, r1, r2
- str r1, [r0, #CLKCTL_COSR]
-
- ldr r2, =CCM_CCMR_CONFIG
- str r2, [r0, #CLKCTL_CCMR]
-
- check_soc_version r1, r2
- cmp r1, #CHIP_REV_2_0
- ldrhs r3, =CCM_MPLL_532_HZ
- bhs 1f
- ldr r2, [r0, #CLKCTL_PDR0]
- tst r2, #CLKMODE_CONSUMER
- ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
- ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
-1:
- str r3, [r0, #CLKCTL_MPCTL]
-
- ldr r1, =CCM_PPLL_300_HZ
- str r1, [r0, #CLKCTL_PPCTL]
-
- ldr r1, =CCM_PDR0_CONFIG
- bic r1, r1, #0x800000
- str r1, [r0, #CLKCTL_PDR0]
-
- ldr r1, [r0, #CLKCTL_CGR0]
- orr r1, r1, #0x0C300000
- str r1, [r0, #CLKCTL_CGR0]
-
- ldr r1, [r0, #CLKCTL_CGR1]
- orr r1, r1, #0x00000C00
- orr r1, r1, #0x00000003
- str r1, [r0, #CLKCTL_CGR1]
-
- ldr r1, [r0, #CLKCTL_CGR2]
- orr r1, r1, #0x00C00000
- str r1, [r0, #CLKCTL_CGR2]
-.endm
-
-.macro setup_sdram
- ldr r0, =ESDCTL_BASE_ADDR
- mov r3, #0x2000
- str r3, [r0, #0x0]
- str r3, [r0, #0x8]
-
- /*ip(r12) has used to save lr register in upper calling*/
- mov fp, lr
-
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD0_BASE_ADDR
- bl setup_sdram_bank
-
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD1_BASE_ADDR
- bl setup_sdram_bank
-
- mov lr, fp
-
-1:
- ldr r3, =ESDCTL_DELAY_LINE5
- str r3, [r0, #0x30]
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- mov r10, lr
-
- core_init
-
- init_aips
-
- init_max
-
- init_m3if
-
- init_clock
- init_debug_board
-
- cmp pc, #PHYS_SDRAM_1
- blo init_sdram_start
- cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
- blo skip_sdram_setup
-
-init_sdram_start:
- /*init_sdram*/
- setup_sdram
-
-skip_sdram_setup:
- mov lr, r10
- mov pc, lr
-
-
-/*
- * r0: ESDCTL control base, r1: sdram slot base
- * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
- */
-setup_sdram_bank:
- mov r3, #0xE
- tst r2, #0x1
- orreq r3, r3, #0x300 /*DDR2*/
- str r3, [r0, #0x10]
- bic r3, r3, #0x00A
- str r3, [r0, #0x10]
- beq 2f
-
- mov r3, #0x20000
-1: subs r3, r3, #1
- bne 1b
-
-2: tst r2, #0x1
- ldreq r3, =ESDCTL_DDR2_CONFIG
- ldrne r3, =ESDCTL_MDDR_CONFIG
- cmp r1, #CSD1_BASE_ADDR
- strlo r3, [r0, #0x4]
- strhs r3, [r0, #0xC]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
- tst r2, #0x1
- bne skip_set_mode
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_DDR2_EMR2
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EMR3
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EN_DLL
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_RESET_DLL
- strb r3, [r1, r4]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
-skip_set_mode:
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xA2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- strb r3, [r1]
- strb r3, [r1]
-
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- tst r2, #0x1
- ldreq r4, =ESDCTL_DDR2_MR
- ldrne r4, =ESDCTL_MDDR_MR
- mov r3, #0xDA
- strb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
- streqb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_EN_DLL
- ldrne r4, =ESDCTL_MDDR_EMR
- strb r3, [r1, r4]
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0x82228080
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
-
- tst r2, #0x1
- moveq r4, #0x20000
- movne r4, #0x200
-1: subs r4, r4, #1
- bne 1b
-
- str r3, [r1, #0x100]
- ldr r4, [r1, #0x100]
- cmp r3, r4
- movne r3, #1
- moveq r3, #0
-
- mov pc, lr
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx35.h>
-#include <i2c.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <mc9sdz60.h>
-#include <mc13892.h>
-#include <linux/types.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <netdev.h>
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_BOARD_LATE_INIT
-#error "CONFIG_BOARD_LATE_INIT must be set for this board"
-#endif
-
-#ifndef CONFIG_BOARD_EARLY_INIT_F
-#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- u32 size1, size2;
-
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
- gd->ram_size = size1 + size2;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return 0;
-}
-
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
- static const iomux_v3_cfg_t i2c1_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
- };
-
- /* setup pins for I2C1 */
- imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
-}
-
-
-static void setup_iomux_spi(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
- MX35_PAD_CSPI1_MISO__CSPI1_MISO,
- MX35_PAD_CSPI1_SS0__CSPI1_SS0,
- MX35_PAD_CSPI1_SS1__CSPI1_SS1,
- MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-
-#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-
-static void setup_iomux_usbotg(void)
-{
- static const iomux_v3_cfg_t usbotg_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
- USBOTG_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
- USBOTG_IN_PAD_CTRL),
- };
-
- /* Set up pins for USBOTG. */
- imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
-}
-
-#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
- };
-
- /* setup pins for FEC */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-int board_early_init_f(void)
-{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- /* enable clocks */
- writel(readl(&ccm->cgr0) |
- MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDIO_MASK |
- MXC_CCM_CGR0_EPIT1_MASK,
- &ccm->cgr0);
-
- writel(readl(&ccm->cgr1) |
- MXC_CCM_CGR1_FEC_MASK |
- MXC_CCM_CGR1_GPIO1_MASK |
- MXC_CCM_CGR1_GPIO2_MASK |
- MXC_CCM_CGR1_GPIO3_MASK |
- MXC_CCM_CGR1_I2C1_MASK |
- MXC_CCM_CGR1_I2C2_MASK |
- MXC_CCM_CGR1_IPU_MASK,
- &ccm->cgr1);
-
- /* Setup NAND */
- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
-
- setup_iomux_i2c();
- setup_iomux_usbotg();
- setup_iomux_fec();
- setup_iomux_spi();
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-static inline int pmic_detect(void)
-{
- unsigned int id;
- struct pmic *p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
-
- pmic_reg_read(p, REG_IDENTIFICATION, &id);
-
- id = (id >> 6) & 0x7;
- if (id == 0x7)
- return 1;
- return 0;
-}
-
-u32 get_board_rev(void)
-{
- int rev;
-
- rev = pmic_detect();
-
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
-int board_late_init(void)
-{
- u8 val;
- u32 pmic_val;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(I2C_0);
- if (ret)
- return ret;
-
- if (pmic_detect()) {
- p = pmic_get("FSL_PMIC");
- imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
-
- pmic_reg_read(p, REG_SETTING_0, &pmic_val);
- pmic_reg_write(p, REG_SETTING_0,
- pmic_val | VO_1_30V | VO_1_50V);
- pmic_reg_read(p, REG_MODE_0, &pmic_val);
- pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
-
- imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
-
- gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
- }
-
- val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
- mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
- mdelay(200);
-
- val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
- mdelay(200);
-
- val |= 0x80;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
-
- /* Print board revision */
- printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_SMC911X)
- int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- if (rc)
- return rc;
-#endif
- return cpu_eth_init(bis);
-}
-
-#if defined(CONFIG_FSL_ESDHC_IMX)
-
-struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- };
-
- /* configure pins for SDHC1 only */
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __BOARD_MX35_3STACK_H
-#define __BOARD_MX35_3STACK_H
-
-#define DBG_BASE_ADDR WEIM_CTRL_CS5
-#define DBG_CSCR_U_CONFIG 0x0000D843
-#define DBG_CSCR_L_CONFIG 0x22252521
-#define DBG_CSCR_A_CONFIG 0x22220A00
-
-#define CCM_CCMR_CONFIG 0x003F4208
-#define CCM_PDR0_CONFIG 0x00801000
-
-/* MEMORY SETTING */
-#define ESDCTL_0x92220000 0x92220000
-#define ESDCTL_0xA2220000 0xA2220000
-#define ESDCTL_0xB2220000 0xB2220000
-#define ESDCTL_0x82228080 0x82228080
-
-#define ESDCTL_PRECHARGE 0x00000400
-
-#define ESDCTL_MDDR_CONFIG 0x007FFC3F
-#define ESDCTL_MDDR_MR 0x00000033
-#define ESDCTL_MDDR_EMR 0x02000000
-
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-#define ESDCTL_DDR2_EMR2 0x04000000
-#define ESDCTL_DDR2_EMR3 0x06000000
-#define ESDCTL_DDR2_EN_DLL 0x02000400
-#define ESDCTL_DDR2_RESET_DLL 0x00000333
-#define ESDCTL_DDR2_MR 0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-#define ESDCTL_DELAY_LINE5 0x00F49F00
-#endif /* __BOARD_MX35_3STACK_H */
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <init.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <cpu_func.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/clock.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <image.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/spi.h>
#include <env.h>
#include <linux/errno.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <fdt_support.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mx7ulp-pins.h>
#include <common.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <image.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 tmp;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
#if defined(CONFIG_TARGET_P1010RDB_PA)
u8 val;
int bus_num = I2C_PCA9557_BUS_NUM;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
printf("Board: %sRDB-PA, ", cpu->name);
#elif defined(CONFIG_TARGET_P1010RDB_PB)
printf("Board: %sRDB-PB, ", cpu->name);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
case 0xe:
puts("SDHC\n");
val = 0x60; /* set pca9557 pin input/output */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
dm_i2c_write(dev, 3, &val, 1);
#else
i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
#include <i2c.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
in_8(&cpld_data->pcba_rev) & 0x0F);
/* Initialize i2c early for rom_loc and flash bank information */
- #if defined(CONFIG_DM_I2C)
+ #if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
#include <i2c.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <image.h>
#include <init.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <net.h>
#include <pci.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/fsl_pci.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/siul.h>
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include "../common/sleep.h"
#include "../common/spl.h"
#include <image.h>
#include <init.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
u8 tmp;
int bus_num = I2C_PCA6408_BUS_NUM;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include "../common/sleep.h"
#include "../common/spl.h"
#include <init.h>
#include <log.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include "../common/qixis.h"
#include "t208xqds_qixis.h"
#include "../common/spl.h"
#include <init.h>
#include <log.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
#include <image.h>
#include <init.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <console.h>
#include <env_internal.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
#include <image.h>
#include <init.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-vf610.h>
#ifdef CONFIG_PWM_NX
#include <pwm.h>
#endif
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/nexell.h>
static int lcd_id = -1;
static unsigned short lcd_fwrev;
static int current_brightness = -1;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static struct udevice *i2c_dev;
#endif
tx[0] = req;
tx[1] = crc8_ow(req << 24, 8);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
if (dm_i2c_write(i2c_dev, 0, tx, 2))
return -EIO;
unsigned char buf[4];
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_chip_for_busnum(ONEWIRE_I2C_BUS,
ONEWIRE_I2C_ADDR, 0, &i2c_dev);
#else
#include <led.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sata.h>
#include <miiphy.h>
#include <net.h>
#include <tpm-v1.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm-generic/gpio.h>
#include <common.h>
#include <command.h>
#include <console.h> /* ctrlc */
+#include <pci.h>
#include <asm/io.h>
#include "hydra.h"
#include <sysinfo.h>
#include <tpm-v1.h>
#include <video_osd.h>
+#include <asm/global_data.h>
#include "../common/ihs_mdio.h"
#include "../../../drivers/sysinfo/gazerbeam.h"
#include <spd_sdram.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/video.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <env.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/libfdt.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <command.h>
#include <dm.h>
#include <log.h>
+#include <sysinfo.h>
#include <acpi/acpigen.h>
#include <asm-generic/gpio.h>
#include <asm/acpi_nhlt.h>
.inject_dsdt = chromeos_acpi_gpio_generate,
};
+struct sysinfo_ops coral_sysinfo_ops = {
+};
+
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id coral_ids[] = {
{ .compatible = "google,coral" },
.name = "coral",
.id = UCLASS_SYSINFO,
.of_match = of_match_ptr(coral_ids),
+ .ops = &coral_sysinfo_ops,
ACPI_OPS_PTR(&coral_acpi_ops)
};
#include <init.h>
#include <malloc.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <common.h>
#include <hang.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <init.h>
#include <init.h>
#include <log.h>
#include <asm/arch-rockchip/clock.h>
+#include <asm/global_data.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/emif.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <cpsw.h>
#include <env.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <net.h>
#include <netdev.h>
#include <scsi.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_pl01x.h>
#include <errno.h>
#include <malloc.h>
#include <errno.h>
#include <asm/cache.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hi3660.h>
#include <asm/armv8/mmu.h>
#include <dm.h>
#include <init.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/platform_data/serial_pl01x.h>
#include <asm/arch/hi3798cv200.h>
#include <mpc83xx.h>
#include <spi.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
int ft_board_setup(void *blob, struct bd_info *bd)
{
#include <init.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
#include <pci_gt64120.h>
#include <pci_msc01.h>
#include <rtc.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/addrspace.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <command.h>
#include <fs.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
#include "iconnect.h"
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <common.h>
#include <twl4030.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/omap_mmc.h>
#include <asm/arch/mux.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
#include <errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <spl.h>
Page size of inventory in EEPROM.
source "board/keymile/km83xx/Kconfig"
+source "board/keymile/kmcent2/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/keymile/km_arm/Kconfig"
#include <cli_hush.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/ctype.h>
#include <linux/delay.h>
*/
int set_km_env(void)
{
- uchar buf[32];
unsigned int pnvramaddr;
unsigned int pram;
unsigned int varaddr;
char *p;
unsigned long rootfssize = 0;
- pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM
- - CONFIG_KM_PNVRAM;
- sprintf((char *)buf, "0x%x", pnvramaddr);
- env_set("pnvramaddr", (char *)buf);
+ pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+ CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
+ env_set_hex("pnvramaddr", pnvramaddr);
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
strict_strtoul(p, 16, &rootfssize);
pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
CONFIG_KM_PNVRAM) / 0x400;
- sprintf((char *)buf, "0x%x", pram);
- env_set("pram", (char *)buf);
+ env_set_ulong("pram", pram);
- varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
- sprintf((char *)buf, "0x%x", varaddr);
- env_set("varaddr", (char *)buf);
+ varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+ CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
+ env_set_hex("varaddr", varaddr);
kernelmem = gd->ram_size - 0x400 * pram;
- sprintf((char *)buf, "0x%x", kernelmem);
- env_set("kernelmem", (char *)buf);
+ env_set_hex("kernelmem", kernelmem);
return 0;
}
p = env_get("hwkey");
if (p)
rc = strict_strtoul(p, 16, &envhwkey);
-
if (rc != 0) {
printf("strict_strtoul returns error: %d", rc);
return rc;
* set the values in environment variables.
*/
if (bid == ivmbid && hwkey == ivmhwkey) {
- char buf[10];
-
found = 1;
envbid = bid;
envhwkey = hwkey;
- sprintf(buf, "%lx", bid);
- env_set("boardid", buf);
- sprintf(buf, "%lx", hwkey);
- env_set("hwkey", buf);
+ env_set_hex("boardid", bid);
+ env_set_hex("hwkey", hwkey);
}
} /* end while( ! found ) */
}
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+
int i2c_soft_read_pin(void);
int i2c_make_abort(void);
#endif /* __KEYMILE_COMMON_H */
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth1addr", (char *)valbuf);
}
+ if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) {
+ /* 3rd ethernet interface */
+ process_mac(valbuf, page2, 2, true);
+ env_set((char *)"eth4addr", (char *)valbuf);
+ }
return 0;
}
int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *eedev = NULL;
ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS,
*/
#include <common.h>
+#include <asm/io.h>
#include <linux/bitops.h>
#include "common.h"
#include "qrio.h"
+/* QRIO ID register offset */
+#define ID_REV_OFF 0x00
+
/* QRIO GPIO register offsets */
#define DIRECT_OFF 0x18
#define GPRT_OFF 0x1c
+void show_qrio(void)
+{
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
+
+ printf("QRIO: id = %u, revision = %u\n",
+ (id_rev >> 8) & 0xff, id_rev & 0xff);
+}
+
int qrio_get_gpio(u8 port_off, u8 gpio_nr)
{
u32 gprt;
void qrio_prstcfg(u8 bit, u8 mode)
{
- u32 prstcfg;
+ unsigned long prstcfg;
u8 i;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
for (i = 0; i < 2; i++) {
if (mode & (1 << i))
- set_bit(2 * bit + i, &prstcfg);
+ __set_bit(2 * bit + i, &prstcfg);
else
- clear_bit(2 * bit + i, &prstcfg);
+ __clear_bit(2 * bit + i, &prstcfg);
}
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
#define QRIO_GPIO_A 0x40
#define QRIO_GPIO_B 0x60
+void show_qrio(void);
int qrio_get_gpio(u8 port_off, u8 gpio_nr);
void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <netdev.h>
#include <miiphy.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
--- /dev/null
+if TARGET_KMCENT2
+
+config SYS_BOARD
+ default "kmcent2"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmcent2"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_T1040
+ select PHYS_64BIT
+
+endif
--- /dev/null
+KMCENT2 BOARD
+M: Niel Fourie <lusus@denx.de>
+S: Maintained
+F: board/keymile/kmcent2/
+F: include/configs/kmcent2.h
+F: configs/kmcent2_defconfig
+F: arch/powerpc/dts/kmcent2.dts
+F: arch/powerpc/dts/kmcent2-u-boot.dtsi
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Keymile AG
+# Rainer Boschung <rainer.boschung@keymile.com>
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+
+obj-y += kmcent2.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += ../common/common.o
+obj-y += ../common/ivm.o
+obj-y += ../common/qrio.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+#include <asm/mpc85xx_gpio.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8
+#define DQSn_START(n, start) ((start) << DQSn_POS(n))
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+
+ /* 1/2 clk delay between wr command and data strobe */
+ popts->write_data_delay = 4;
+ /* clk lauched 1/2 applied cylcle after address command */
+ popts->clk_adjust = 4;
+ /* 1T timing: command/address held for only 1 cycle */
+ popts->twot_en = 0;
+ popts->threet_en = 0;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x3b;
+
+ /* we have only one module, half str should be OK */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ /* set for DDR3-1600 */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x7;
+ /* DQS write leveling start time according layout */
+ popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
+ DQSn_START(2, 0x06) |
+ DQSn_START(3, 0x07) |
+ DQSn_START(4, 0x07));
+ popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
+ DQSn_START(6, 0x08) |
+ DQSn_START(7, 0x08) |
+ DQSn_START(8, 0x08));
+
+ /*
+ * rtt and wtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+int dram_init(void)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ gd->ram_size = dram_size;
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/cache.h>
+#include <asm/fsl_fdt.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_liodn.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <net.h>
+#include <netdev.h>
+#include <vsc9953.h>
+
+#include "../common/common.h"
+#include "../common/qrio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+int checkboard(void)
+{
+ printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
+
+ return 0;
+}
+
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* board specific IFC configuration: increased bus turnaround time */
+ setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
+
+ /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
+ setbits_be32(&gur->ddrclkdr, 0x40000000);
+
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+ RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
+ /* configure PRST lines for the application: */
+ /*
+ * ETHSW_DDR_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_ETHSW_DDR_RST, true);
+ /*
+ * XES_PHY_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_XES_PHY_RST, true);
+ /*
+ * ES_PHY_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_ES_PHY_RST, true);
+ /*
+ * EFE_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_EFE_RST, true);
+ /*
+ * BFTIC4_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_BFTIC4_RST, true);
+ /*
+ * DPAXE_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_DPAXE_RST, true);
+ /*
+ * PEXSW_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_PEXSW_RST, false, false);
+ /*
+ * PEXSW_NT_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_PEXSW_NT_RST, false, false);
+ /*
+ * BOBCAT_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_BOBCAT_RST, false, false);
+ /*
+ * FEMT_RST:
+ * reset at power-up and unit reset only and enable WD
+ */
+ qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_FEMT_RST, true);
+ /*
+ * FOAM_RST:
+ * reset at power-up and unit reset only and enable WD
+ */
+ qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_FOAM_RST, true);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ int ret = 0;
+
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+ setup_qbman_portals();
+
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
+ return ret;
+}
+
+unsigned long get_serial_clock(unsigned long dummy)
+{
+ return (gd->bus_clk / 2);
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+ return 66666666;
+}
+
+int misc_init_f(void)
+{
+ /* configure QRIO pis for i2c deblocking */
+ i2c_deblock_gpio_cfg();
+
+ /*
+ * CFE_RST (front phy):
+ * reset at power-up, unit and core reset, deasset reset w/o WD
+ */
+ qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(KM_CFE_RST, false, false);
+
+ /*
+ * ZL30158_RST (PTP clock generator):
+ * reset at power-up only, deassert reset and enable WD on it
+ */
+ qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
+ qrio_prst(KM_ZL30158_RST, false, false);
+
+ /*
+ * ZL30364_RST (EEC generator):
+ * reset at power-up only, deassert reset and enable WD on it
+ */
+ qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
+ qrio_prst(KM_ZL30364_RST, false, false);
+
+ return 0;
+}
+
+#define USED_SRDS_BANK 0
+#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
+
+#define BRG01_IOCLK12 0x02000000
+#define EC2_GTX_CLK125 0x08000000
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
+ ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* check SERDES bank 0 reference clock */
+ u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0);
+
+ if (actual & SRDS_PLLCR0_POFF)
+ printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
+ if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
+ printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
+ USED_SRDS_BANK,
+ serdes_clock_to_string(EXPECTED_SRDS_RFCK),
+ serdes_clock_to_string(actual));
+ }
+
+ /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
+ out_be32(&scfg->qeioclkcr,
+ in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
+
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+
+ /* Fix polarity of Card Detect and Write Protect */
+ out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
+
+ /*
+ * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
+ * to EC2
+ */
+ out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
+
+ return 0;
+}
+
+int hush_init_var(void)
+{
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ const char *kmem;
+ /* DIP switch support on BFTIC */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)SYS_BFTIC_BASE;
+ u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ env_set("actual_bank", "0");
+ }
+
+ set_km_env();
+
+ /*
+ * bootm_size is used to fixup the FDT memory node
+ * set it to kernelmem that has the same value
+ */
+ kmem = env_get("kernelmem");
+ if (kmem)
+ env_set("bootm_size", kmem);
+
+ return 0;
+}
+
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+ int node, ret;
+ char path[24];
+ unsigned char mac_addr[6];
+
+ /*
+ * Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
+ * get the mac addr from env
+ */
+ if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
+ printf("eth4addr env variable not defined\n");
+ return;
+ }
+
+ /* local management port */
+ strcpy(path, "/soc/fman/ethernet@e8000");
+ node = fdt_path_offset(blob, path);
+ if (node < 0) {
+ printf("no %s\n", path);
+ return;
+ }
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("%s\n\terror setting local-mac-address property\n",
+ path);
+ }
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = env_get_bootm_low();
+ size = env_get_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_liodn(blob);
+
+ fdt_fixup_fman_mac_addresses(blob);
+
+ if (hwconfig("qe-tdm"))
+ fdt_del_diu(blob);
+ return 0;
+}
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT QRIO_GPIO_A
+#define SELFTEST_PIN 0
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <config.h>
+#include <asm/fsl_law.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
+/* other application LAW are not used in u-boot */
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/mmu.h>
+#include <asm/u-boot.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+ 0, 2, BOOKE_PAGESZ_128M, 1),
+
+ /* *I*G* - PCI1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI1 I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+ /* QRIO */
+ SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 11, BOOKE_PAGESZ_64K, 1),
+ /* MRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 12, BOOKE_PAGESZ_128M, 1),
+ /* BFTIC */
+ SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 13, BOOKE_PAGESZ_128M, 1),
+ /*
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so do not use them here!!.
+ */
+ /* PAXE */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 16, BOOKE_PAGESZ_128M, 1)
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <cpu_func.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
obj-y += sl28.o cmds.o
endif
-obj-y += common.o ddr.o
+obj-y += ddr.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <common.h>
-#include <asm/arch-fsl-layerscape/soc.h>
-
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <errno.h>
#include <fsl_ddr.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
int board_init(void)
{
if (CONFIG_IS_ENABLED(FSL_CAAM))
#include <common.h>
#include <asm/io.h>
#include <asm/spl.h>
+#include <asm/arch-fsl-layerscape/fsl_serdes.h>
+#include <asm/arch-fsl-layerscape/soc.h>
#define DCFG_RCWSR25 0x160
#define GPINFO_HW_VARIANT_MASK 0xff
+#define SERDES_LNDGCR0 0x1ea08c0
+#define LNDGCR0_PROTS_MASK GENMASK(11, 7)
+#define LNDGCR0_PROTS_SATA (0x2 << 7)
+#define SERDES_LNDGCR1 0x1ea08c4
+#define LNDGCR1_RDAT_INV BIT(31)
+
+/*
+ * On this board the SMARC PCIe lane D might be switched to SATA mode. This
+ * makes sense if this lane is connected to a Mini PCI slot and a mSATA card
+ * is plugged in. In this case, the RX pair is swapped and we need to invert
+ * the received data.
+ */
+static void fixup_sata_rx_polarity(void)
+{
+ u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
+ u32 tmp;
+
+ if (prot == LNDGCR0_PROTS_SATA) {
+ tmp = in_le32(SERDES_LNDGCR1);
+ tmp |= LNDGCR1_RDAT_INV;
+ out_le32(SERDES_LNDGCR1, tmp);
+ }
+}
+
int sl28_variant(void)
{
return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
int variant = sl28_variant();
switch (variant) {
+ case 1:
+ return strcmp(name, "fsl-ls1028a-kontron-sl28-var1");
+ case 2:
+ return strcmp(name, "fsl-ls1028a-kontron-sl28-var2");
case 3:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
case 4:
{
spl_boot_list[0] = BOOT_DEVICE_SPI;
}
+
+int board_early_init_f(void)
+{
+ fixup_sata_rx_polarity();
+ fsl_lsch3_early_init_f();
+
+ return 0;
+}
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <atf_common.h>
#include <spl.h>
#include <eeprom.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <ahci.h>
#include <env.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9x5_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_sfr.h>
#include <asm/arch/sama5d3_smc.h>
*/
#include <common.h>
+#include <env.h>
#include <i2c.h>
#include <init.h>
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pinmux_defs.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
-u8 board_rev;
-
#define EEPROM_I2C_ADDR 0x50
#define EEPROM_REV_OFFSET 0x3F00
-#define EEPROM_MAC_OFFSET 0x3F06
+#define EEPROM_BDADDR_OFFSET 0x3F06
const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(spi0_pins_base),
const int lpsc_size = ARRAY_SIZE(lpsc);
-u32 get_board_rev(void)
-{
- u8 buf[2];
-
- if (!board_rev) {
- if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
- printf("\nBoard revision read failed!\n");
- } else {
- /*
- * Board rev 3 has MAC address at EEPROM_REV_OFFSET.
- * Other revisions have checksum at EEPROM_REV_OFFSET+1
- * to detect this.
- */
- if ((buf[0] ^ buf[1]) == 0xFF)
- board_rev = buf[0];
- else
- board_rev = 3;
- }
- }
-
- return board_rev;
-}
-
/*
- * The Bluetooth MAC address serves as the board serial number.
+ * The Bluetooth address serves as the board serial number.
*/
-void get_board_serial(struct tag_serialnr *serialnr)
+static void setup_serial_number(void)
{
u32 offset;
+ char serial_number[13];
u8 buf[6];
+ u8 eeprom_rev;
+
+ if (env_get("serial#"))
+ return;
- if (!board_rev)
- board_rev = get_board_rev();
+ if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
+ printf("\nEEPROM revision read failed!\n");
+ return;
+ }
- /* Board rev 3 has MAC address where rev should be */
- offset = (board_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_MAC_OFFSET;
+ /*
+ * EEPROM rev 3 has Bluetooth address at EEPROM_REV_OFFSET.
+ * Other revisions have checksum at EEPROM_REV_OFFSET+1
+ * to detect this.
+ */
+ if ((buf[0] ^ buf[1]) == 0xFF)
+ eeprom_rev = buf[0];
+ else
+ eeprom_rev = 3;
+
+ /* EEPROM rev 3 has Bluetooth address where rev should be */
+ offset = (eeprom_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_BDADDR_OFFSET;
if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) {
- printf("\nBoard serial read failed!\n");
- } else {
- u8 *nr;
-
- nr = (u8 *)&serialnr->low;
- nr[0] = buf[5];
- nr[1] = buf[4];
- nr[2] = buf[3];
- nr[3] = buf[2];
- nr = (u8 *)&serialnr->high;
- nr[0] = buf[1];
- nr[1] = buf[0];
- nr[2] = 0;
- nr[3] = 0;
+ printf("\nEEPROM serial read failed!\n");
+ return;
}
+
+ sprintf(serial_number, "%02X%02X%02X%02X%02X%02X",
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+
+ env_set("serial#", serial_number);
}
int board_early_init_f(void)
{
irq_init();
- /* arch number of the board */
- /* LEGO didn't register for a unique number and uses da850evm */
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
-
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
return 0;
}
+
+int board_late_init(void)
+{
+ setup_serial_number();
+
+ return 0;
+}
#include <env.h>
#include <fastboot.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/ctype.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
#include <fdt_support.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <log.h>
#include <serial.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <log.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <net.h>
#include <ns16550.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/omap_musb.h>
#include <asm/arch/am35x_def.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
#include <i2c.h>
#include <serial.h>
#include <twl4030.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <common.h>
#include <init.h>
#include <miiphy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <config.h>
#include <env.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <mmc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <common.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <log.h>
#include <wdt.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <init.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <env.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <i2c.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
#include <linux/mbus.h>
#include <common.h>
#include <init.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <common.h>
#include <init.h>
#include <mpc83xx.h>
+#include <asm/global_data.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <miiphy.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <asm/global_data.h>
enum {
BOARD_TYPE_PCB110 = 0xAABBCE00,
#include <common.h>
#include <image.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <led.h>
#include <miiphy.h>
#include <image.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <common.h>
#include <image.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <led.h>
#include <miiphy.h>
#include <common.h>
#include <image.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <led.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
#include <twl4030.h>
#include <i2c.h>
#include <video_fb.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/bitops.h>
/* initialize twl4030 power managment */
twl4030_power_init();
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
/* set VSIM to 1.8V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
return keybuf[keybuf_head++];
}
-/*
- * Routine: board_mmc_init
- * Description: Initialize mmc devices.
- */
-int board_mmc_init(struct bd_info *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
+static const struct mmc_config rx51_mmc_cfg = {
+ .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
+ .f_min = 400000,
+ .f_max = 52000000,
+ .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
+};
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
- twl4030_power_mmc_init(1);
-}
+static const struct omap_hsmmc_plat rx51_mmc[] = {
+ { rx51_mmc_cfg, (struct hsmmc *)OMAP_HSMMC1_BASE },
+ { rx51_mmc_cfg, (struct hsmmc *)OMAP_HSMMC2_BASE },
+};
+
+U_BOOT_DRVINFOS(rx51_mmc) = {
+ { "omap_hsmmc", &rx51_mmc[0] },
+ { "omap_hsmmc", &rx51_mmc[1] },
+};
static const struct omap_i2c_plat rx51_i2c[] = {
{ I2C_BASE1, 100000, OMAP_I2C_REV_V1 },
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-vf610.h>
#include <net.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <init.h>
#include <log.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <power/tps65910.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <common.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <dm/device.h>
#include <common.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <init.h>
#include <log.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/arm-smccc.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <command.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <netdev.h>
#include <net.h>
#include <usb.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <fdt_support.h>
#include <asm/arch/dram.h>
#include <asm/arch/sysmap-apq8096.h>
#include <env.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/arm-smccc.h>
#include <linux/psci.h>
#include <common.h>
#include <common.h>
#include <init.h>
#include <miiphy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
DTB_DIR "bcm2711-rpi-4-b.dtb",
true,
},
+ [0x13] = {
+ "400",
+ DTB_DIR "bcm2711-rpi-400.dtb",
+ true,
+ },
+ [0x14] = {
+ "Compute Module 4",
+ DTB_DIR "bcm2711-rpi-cm4.dtb",
+ true,
+ },
};
static const struct rpi_model rpi_models_old_scheme[] = {
gd->ram_size = msg->get_arm_mem.body.resp.mem_size;
+ /*
+ * In some configurations the memory size returned by VideoCore
+ * is not aligned to the section size, what is mandatory for
+ * the u-boot's memory setup.
+ */
+ gd->ram_size &= ~MMU_SECTION_SIZE;
+
return 0;
}
+++ /dev/null
-if TARGET_MIGOR
-
-config SYS_BOARD
- default "MigoR"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "MigoR"
-
-endif
+++ /dev/null
-MIGOR BOARD
-#M: -
-S: Maintained
-F: board/renesas/MigoR/
-F: include/configs/MigoR.h
-F: configs/MigoR_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/MigoR/Makefile
-#
-
-obj-y := migo_r.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007-2008
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/MigoR/lowlevel_init.S
- */
-
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
- *
- * (Note: As no stack is available, no subroutines can be called...).
- */
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- write32 CCR_A, CCR_D ! Address of Cache Control Register
- ! Instruction Cache Invalidate
-
- write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
- ! TI == TLB Invalidate bit
-
- write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
-
- write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
-
- write16 PFC_PULCR_A, PFC_PULCR_D
-
- write16 PFC_DRVCR_A, PFC_DRVCR_D
-
- write16 SBSCR_A, SBSCR_D
-
- write16 PSCR_A, PSCR_D
-
- write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
- ! 0xA507 -> timer_STOP / WDT_CLK = max
-
- write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
- ! 0x5A00 -> Clear
-
- write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
- ! 0xA504 -> timer_STOP / CLK = 500ms
-
- write32 DLLFRQ_A, DLLFRQ_D ! 20080115
- ! 20080115
-
- write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
- ! 20080115
-
- write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
- ! ??
-
-bsc_init:
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5ABCR_A, CS5ABCR_D
-
- write32 CS5BBCR_A, CS5BBCR_D
-
- write32 CS6ABCR_A, CS6ABCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5AWCR_A, CS5AWCR_D
-
- write32 CS5BWCR_A, CS5BWCR_D
-
- write32 CS6AWCR_A, CS6AWCR_D
-
- ! SDRAM initialization
- write32 SDCR_A, SDCR_D
-
- write32 SDWCR_A, SDWCR_D
-
- write32 SDPCR_A, SDPCR_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 RTCNT_A, RTCNT_D
-
- write32 RTCSR_A, RTCSR_D
-
- write32 RFCR_A, RFCR_D
-
- write8 SDMR3_A, SDMR3_D
-
- ! BL bit off (init = ON) (?!?)
-
- stc sr, r0 ! BL bit off(init=ON)
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
- mov #0, r0
-
- .align 4
-
-CCR_A: .long CCR
-MMUCR_A: .long MMUCR
-MSTPCR0_A: .long MSTPCR0
-MSTPCR2_A: .long MSTPCR2
-PFC_PULCR_A: .long PULCR
-PFC_DRVCR_A: .long DRVCR
-SBSCR_A: .long SBSCR
-PSCR_A: .long PSCR
-RWTCSR_A: .long RWTCSR
-RWTCNT_A: .long RWTCNT
-FRQCR_A: .long FRQCR
-PLLCR_A: .long PLLCR
-DLLFRQ_A: .long DLLFRQ
-
-CCR_D: .long 0x00000800
-CCR_D_2: .long 0x00000103
-MMUCR_D: .long 0x00000004
-MSTPCR0_D: .long 0x00001001
-MSTPCR2_D: .long 0xffffffff
-PFC_PULCR_D: .long 0x6000
-PFC_DRVCR_D: .long 0x0464
-FRQCR_D: .long 0x07033639
-PLLCR_D: .long 0x00005000
-DLLFRQ_D: .long 0x000004F6
-
-CMNCR_A: .long CMNCR
-CMNCR_D: .long 0x0000001B
-CS0BCR_A: .long CS0BCR
-CS0BCR_D: .long 0x24920400
-CS4BCR_A: .long CS4BCR
-CS4BCR_D: .long 0x00003400
-CS5ABCR_A: .long CS5ABCR
-CS5ABCR_D: .long 0x24920400
-CS5BBCR_A: .long CS5BBCR
-CS5BBCR_D: .long 0x24920400
-CS6ABCR_A: .long CS6ABCR
-CS6ABCR_D: .long 0x24920400
-
-CS0WCR_A: .long CS0WCR
-CS0WCR_D: .long 0x00000380
-CS4WCR_A: .long CS4WCR
-CS4WCR_D: .long 0x00110080
-CS5AWCR_A: .long CS5AWCR
-CS5AWCR_D: .long 0x00000300
-CS5BWCR_A: .long CS5BWCR
-CS5BWCR_D: .long 0x00000300
-CS6AWCR_A: .long CS6AWCR
-CS6AWCR_D: .long 0x00000300
-
-SDCR_A: .long SBSC_SDCR
-SDCR_D: .long 0x80160809
-SDWCR_A: .long SBSC_SDWCR
-SDWCR_D: .long 0x0014450C
-SDPCR_A: .long SBSC_SDPCR
-SDPCR_D: .long 0x00000087
-RTCOR_A: .long SBSC_RTCOR
-RTCNT_A: .long SBSC_RTCNT
-RTCNT_D: .long 0xA55A0012
-RTCOR_D: .long 0xA55A001C
-RTCSR_A: .long SBSC_RTCSR
-RFCR_A: .long SBSC_RFCR
-RFCR_D: .long 0xA55A0221
-RTCSR_D: .long 0xA55A009a
-SDMR3_A: .long 0xFE581180
-SDMR3_D: .long 0x0
-
-SR_MASK_D: .long 0xEFFFFF0F
-
- .align 2
-
-SBSCR_D: .word 0x0044
-PSCR_D: .word 0x0000
-RWTCSR_D_1: .word 0xA507
-RWTCSR_D_2: .word 0xA504
-RWTCNT_D: .word 0x5A00
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/MigoR/migo_r.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas MigoR\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state (unsigned short value)
-{
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(struct bd_info *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
#include <init.h>
#include <malloc.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/sh_sdhi.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <init.h>
#include <malloc.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <common.h>
#include <cpu_func.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <init.h>
#include <malloc.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <init.h>
#include <malloc.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
+++ /dev/null
-if TARGET_R7780MP
-
-config SYS_BOARD
- default "r7780mp"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "r7780mp"
-
-endif
+++ /dev/null
-R7780MP BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/r7780mp/
-F: include/configs/r7780mp.h
-F: configs/r7780mp_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
-#
-# board/r7780mp/Makefile
-#
-
-obj-y := r7780mp.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
- *
- * u-boot/board/r7780mp/lowlevel_init.S
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
- *
- * (Note: As no stack is available, no subroutines can be called...).
- */
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- write32 CCR_A, CCR_D /* Address of Cache Control Register */
- /* Instruction Cache Invalidate */
-
- write32 FRQCR_A, FRQCR_D /* Frequency control register */
-
- /* pin_multi_setting */
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
-
- write32 BBG_PMSR1_A, BBG_PMSR1_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
-
- write32 BBG_PMSR2_A, BBG_PMSR2_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
-
- write32 BBG_PMSR3_A, BBG_PMSR3_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
-
- write32 BBG_PMSR4_A, BBG_PMSR4_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
-
- write32 BBG_PMSRG_A, BBG_PMSRG_D
-
- /* cpg_setting */
- write32 FRQCR_A, FRQCR_D
-
- write32 DLLCSR_A, DLLCSR_D
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* wait 200us */
- mov.l REPEAT0_R3, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- /* bsc_setting */
- write32 MMSELR_A, MMSELR_D
-
- write32 BCR_A, BCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS1BCR_A, CS1BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5BCR_A, CS5BCR_D
-
- write32 CS6BCR_A, CS6BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS1WCR_A, CS1WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5WCR_A, CS5WCR_D
-
- write32 CS6WCR_A, CS6WCR_D
-
- write32 CS5PCR_A, CS5PCR_D
-
- write32 CS6PCR_A, CS6PCR_D
-
- /* ddr_setting */
- /* wait 200us */
- mov.l REPEAT0_R3, r3
- mov #0, r2
-repeat1:
- add #1, r2
- cmp/hs r3, r2
- bf repeat1
- nop
-
- mov.l MIM_U_A, r0
- mov.l MIM_U_D, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l MIM_L_A, r0
- mov.l MIM_L_D0, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l STR_L_A, r0
- mov.l STR_L_D, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l SDR_L_A, r0
- mov.l SDR_L_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D0, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D1, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l EMRS_A, r0
- mov.l EMRS_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l MRS1_A, r0
- mov.l MRS1_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D2, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D3, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D4, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l MRS2_A, r0
- mov.l MRS2_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D5, r1
- synco
- mov.l r1, @r0
- synco
-
- /* wait 200us */
- mov.l REPEAT0_R1, r3
- mov #0, r2
-repeat2:
- add #1, r2
- cmp/hs r3, r2
- bf repeat2
-
- synco
-
- mov.l MIM_L_A, r0
- mov.l MIM_L_D1, r1
- synco
- mov.l r1, @r0
- synco
-
- rts
- nop
- .align 4
-
-RWTCSR_D_1: .word 0xA507
-RWTCSR_D_2: .word 0xA507
-RWTCNT_D: .word 0x5A00
- .align 2
-
-BBG_PMMR_A: .long 0xFF800010
-BBG_PMSR1_A: .long 0xFF800014
-BBG_PMSR2_A: .long 0xFF800018
-BBG_PMSR3_A: .long 0xFF80001C
-BBG_PMSR4_A: .long 0xFF800020
-BBG_PMSRG_A: .long 0xFF800024
-
-BBG_PMMR_D_PMSR1: .long 0xffffbffd
-BBG_PMSR1_D: .long 0x00004002
-BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
-BBG_PMSR2_D: .long 0x03de5800
-BBG_PMMR_D_PMSR3: .long 0xfffffff8
-BBG_PMSR3_D: .long 0x00000007
-BBG_PMMR_D_PMSR4: .long 0xdffdfff9
-BBG_PMSR4_D: .long 0x20020006
-BBG_PMMR_D_PMSRG: .long 0xffffffff
-BBG_PMSRG_D: .long 0x00000000
-
-FRQCR_A: .long FRQCR
-DLLCSR_A: .long 0xffc40010
-FRQCR_D: .long 0x40233035
-DLLCSR_D: .long 0x00000000
-
-/* for DDR-SDRAM */
-MIM_U_A: .long MIM_1
-MIM_L_A: .long MIM_2
-SCR_U_A: .long SCR_1
-SCR_L_A: .long SCR_2
-STR_U_A: .long STR_1
-STR_L_A: .long STR_2
-SDR_U_A: .long SDR_1
-SDR_L_A: .long SDR_2
-
-EMRS_A: .long 0xFEC02000
-MRS1_A: .long 0xFEC00B08
-MRS2_A: .long 0xFEC00308
-
-MIM_U_D: .long 0x00004000
-MIM_L_D0: .long 0x03e80009
-MIM_L_D1: .long 0x03e80209
-SCR_L_D0: .long 0x3
-SCR_L_D1: .long 0x2
-SCR_L_D2: .long 0x2
-SCR_L_D3: .long 0x4
-SCR_L_D4: .long 0x4
-SCR_L_D5: .long 0x0
-STR_L_D: .long 0x000f0000
-SDR_L_D: .long 0x00000400
-EMRS_D: .long 0x0
-MRS1_D: .long 0x0
-MRS2_D: .long 0x0
-
-/* Cache Controller */
-CCR_A: .long CCR
-MMUCR_A: .long MMUCR
-RWTCNT_A: .long WTCNT
-
-CCR_D: .long 0x0000090b
-CCR_D_2: .long 0x00000103
-MMUCR_D: .long 0x00000004
-MSTPCR0_D: .long 0x00001001
-MSTPCR2_D: .long 0xffffffff
-
-/* local Bus State Controller */
-MMSELR_A: .long MMSELR
-BCR_A: .long BCR
-CS0BCR_A: .long CS0BCR
-CS1BCR_A: .long CS1BCR
-CS2BCR_A: .long CS2BCR
-CS4BCR_A: .long CS4BCR
-CS5BCR_A: .long CS5BCR
-CS6BCR_A: .long CS6BCR
-CS0WCR_A: .long CS0WCR
-CS1WCR_A: .long CS1WCR
-CS2WCR_A: .long CS2WCR
-CS4WCR_A: .long CS4WCR
-CS5WCR_A: .long CS5WCR
-CS6WCR_A: .long CS6WCR
-CS5PCR_A: .long CS5PCR
-CS6PCR_A: .long CS6PCR
-
-MMSELR_D: .long 0xA5A50003
-BCR_D: .long 0x00000000
-CS0BCR_D: .long 0x77777770
-CS1BCR_D: .long 0x77777670
-CS2BCR_D: .long 0x77777770
-CS4BCR_D: .long 0x77777770
-CS5BCR_D: .long 0x77777670
-CS6BCR_D: .long 0x77777770
-CS0WCR_D: .long 0x00020006
-CS1WCR_D: .long 0x00232304
-CS2WCR_D: .long 0x7777770F
-CS4WCR_D: .long 0x7777770F
-CS5WCR_D: .long 0x00101006
-CS6WCR_D: .long 0x77777703
-CS5PCR_D: .long 0x77000000
-CS6PCR_D: .long 0x77000000
-
-REPEAT0_R3: .long 0x00002000
-REPEAT0_R1: .long 0x0000200
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- */
-
-#include <common.h>
-#include <ide.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <netdev.h>
-#include "r7780mp.h"
-
-int checkboard(void)
-{
-#if defined(CONFIG_R7780MP)
- puts("BOARD: Renesas Solutions R7780MP\n");
-#else
- puts("BOARD: Renesas Solutions R7780RP\n");
-#endif
- return 0;
-}
-
-int board_init(void)
-{
- /* SCIF Enable */
- writew(0x0, PHCR);
-
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-
-}
-
-void ide_set_reset(int idereset)
-{
- /* if reset = 1 IDE reset will be asserted */
- if (idereset) {
- writew(0x432, FPGA_CFCTL);
-#if defined(CONFIG_R7780MP)
- writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
-#else
- writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
-#endif
- writew(0x01, FPGA_CFCDINTCLR);
- }
-}
-
-static struct pci_controller hose;
-void pci_init_board(void)
-{
- pci_sh7780_init(&hose);
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- /* return >= 0 if a chip is found, the board's AX88796L is n2k-based */
- return ne2k_register() + pci_eth_init(bis);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- *
- * u-boot/board/r7780mp/r7780mp.h
- */
-
-#ifndef _BOARD_R7780MP_R7780MP_H_
-#define _BOARD_R7780MP_R7780MP_H_
-
-/* R7780MP's FPGA register map */
-#define FPGA_BASE 0xa4000000
-#define FPGA_IRLMSK (FPGA_BASE + 0x00)
-#define FPGA_IRLMON (FPGA_BASE + 0x02)
-#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
-#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
-#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
-#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
-#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
-#define FPGA_PCIBD (FPGA_BASE + 0x0E)
-#define FPGA_PCICD (FPGA_BASE + 0x10)
-#define FPGA_EXTGIO (FPGA_BASE + 0x16)
-#define FPGA_IVDRMON (FPGA_BASE + 0x18)
-#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
-#define FPGA_OBLED (FPGA_BASE + 0x1C)
-#define FPGA_OBSW (FPGA_BASE + 0x1E)
-#define FPGA_TPCTL (FPGA_BASE + 0x100)
-#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
-#define FPGA_TPCLR (FPGA_BASE + 0x104)
-#define FPGA_TPXPOS (FPGA_BASE + 0x106)
-#define FPGA_TPYPOS (FPGA_BASE + 0x108)
-#define FPGA_DBSW (FPGA_BASE + 0x200)
-#define FPGA_VERSION (FPGA_BASE + 0x700)
-#define FPGA_CFCTL (FPGA_BASE + 0x300)
-#define FPGA_CFPOW (FPGA_BASE + 0x302)
-#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
-#define FPGA_PMR (FPGA_BASE + 0x900)
-
-#endif /* _BOARD_R7780RP_R7780RP_H_ */
#include <common.h>
#include <dm.h>
#include <init.h>
+#include <asm/global_data.h>
#include <dm/uclass-internal.h>
#include <asm/arch/rmobile.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
+++ /dev/null
-if TARGET_SH7752EVB
-
-config SYS_BOARD
- default "sh7752evb"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7752evb"
-
-endif
+++ /dev/null
-SH7752EVB BOARD
-#M: -
-S: Maintained
-F: board/renesas/sh7752evb/
-F: include/configs/sh7752evb.h
-F: configs/sh7752evb_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-#
-
-obj-y := sh7752evb.o spi-boot.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-.macro or32, addr, data
- mov.l \addr, r1
- mov.l \data, r0
- mov.l @r1, r2
- or r2, r0
- mov.l r0, @r1
-.endm
-
-.macro wait_DBCMD
- mov.l DBWAIT_A, r0
- mov.l @r0, r1
-.endm
-
- .global lowlevel_init
- .section .spiboot1.text
- .align 2
-
-lowlevel_init:
- /*------- GPIO -------*/
- write16 PDCR_A, PDCR_D ! SPI0
- write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
- write16 PJCR_A, PJCR_D ! SCIF4
- write16 PTCR_A, PTCR_D ! STATUS
- write16 PSEL1_A, PSEL1_D ! SPI0
- write16 PSEL2_A, PSEL2_D ! SPI0
- write16 PSEL5_A, PSEL5_D ! STATUS
-
- bra exit_gpio
- nop
-
- .align 2
-
-/*------- GPIO -------*/
-PDCR_A: .long 0xffec0006
-PGCR_A: .long 0xffec000c
-PJCR_A: .long 0xffec0012
-PTCR_A: .long 0xffec0026
-PSEL1_A: .long 0xffec0072
-PSEL2_A: .long 0xffec0074
-PSEL5_A: .long 0xffec007a
-
-PDCR_D: .long 0x0000
-PGCR_D: .long 0x0004
-PJCR_D: .long 0x0000
-PTCR_D: .long 0x0000
-PSEL1_D: .long 0x0000
-PSEL2_D: .long 0x3000
-PSEL5_D: .long 0x0ffc
-
- .align 2
-
-exit_gpio:
- mov #0, r14
- mova 2f, r0
- mov.l PC_MASK, r1
- tst r0, r1
- bf 2f
-
- bra exit_pmb
- nop
-
- .align 2
-
-/* If CPU runs on SDRAM (PC=0x5???????) or not. */
-PC_MASK: .long 0x20000000
-
-2:
- mov #1, r14
-
- mov.l EXPEVT_A, r0
- mov.l @r0, r0
- mov.l EXPEVT_POWER_ON_RESET, r1
- cmp/eq r0, r1
- bt 1f
-
- /*
- * If EXPEVT value is manual reset or tlb multipul-hit,
- * initialization of DDR3IF is not necessary.
- */
- bra exit_ddr
- nop
-
-1:
- /*------- Reset -------*/
- write32 MRSTCR0_A, MRSTCR0_D
- write32 MRSTCR1_A, MRSTCR1_D
-
- /* For Core Reset */
- mov.l DBACEN_A, r0
- mov.l @r0, r0
- cmp/eq #0, r0
- bt 3f
-
- /*
- * If DBACEN == 1(DBSC was already enabled), we have to avoid the
- * initialization of DDR3-SDRAM.
- */
- bra exit_ddr
- nop
-
-3:
- /*------- DDR3IF -------*/
- /* oscillation stabilization time */
- wait_timer WAIT_OSC_TIME
-
- /* step 3 */
- write32 DBCMD_A, DBCMD_RSTL_VAL
- wait_timer WAIT_30US
-
- /* step 4 */
- write32 DBCMD_A, DBCMD_PDEN_VAL
-
- /* step 5 */
- write32 DBKIND_A, DBKIND_D
-
- /* step 6 */
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBTR4_A, DBTR4_D
- write32 DBTR5_A, DBTR5_D
- write32 DBTR6_A, DBTR6_D
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D
- write32 DBTR13_A, DBTR13_D
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D
- write32 DBTR17_A, DBTR17_D
- write32 DBTR18_A, DBTR18_D
- write32 DBTR19_A, DBTR19_D
- write32 DBRNK0_A, DBRNK0_D
-
- /* step 7 */
- write32 DBPDCNT3_A, DBPDCNT3_D
-
- /* step 8 */
- write32 DBPDCNT1_A, DBPDCNT1_D
- write32 DBPDCNT2_A, DBPDCNT2_D
- write32 DBPDLCK_A, DBPDLCK_D
- write32 DBPDRGA_A, DBPDRGA_D
- write32 DBPDRGD_A, DBPDRGD_D
-
- /* step 9 */
- wait_timer WAIT_30US
-
- /* step 10 */
- write32 DBPDCNT0_A, DBPDCNT0_D
-
- /* step 11 */
- wait_timer WAIT_30US
- wait_timer WAIT_30US
-
- /* step 12 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- wait_DBCMD
-
- /* step 13 */
- write32 DBCMD_A, DBCMD_RSTH_VAL
- wait_DBCMD
-
- /* step 14 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
-
- /* step 15 */
- write32 DBCMD_A, DBCMD_PDXT_VAL
-
- /* step 16 */
- write32 DBCMD_A, DBCMD_MRS2_VAL
-
- /* step 17 */
- write32 DBCMD_A, DBCMD_MRS3_VAL
-
- /* step 18 */
- write32 DBCMD_A, DBCMD_MRS1_VAL
-
- /* step 19 */
- write32 DBCMD_A, DBCMD_MRS0_VAL
-
- /* step 20 */
- write32 DBCMD_A, DBCMD_ZQCL_VAL
-
- write32 DBCMD_A, DBCMD_REF_VAL
- write32 DBCMD_A, DBCMD_REF_VAL
- wait_DBCMD
-
- /* step 21 */
- write32 DBADJ0_A, DBADJ0_D
- write32 DBADJ1_A, DBADJ1_D
- write32 DBADJ2_A, DBADJ2_D
-
- /* step 22 */
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D
- write32 DBRFCNF2_A, DBRFCNF2_D
-
- /* step 23 */
- write32 DBCALCNF_A, DBCALCNF_D
-
- /* step 24 */
- write32 DBRFEN_A, DBRFEN_D
- write32 DBCMD_A, DBCMD_SRXT_VAL
-
- /* step 25 */
- write32 DBACEN_A, DBACEN_D
-
- /* step 26 */
- wait_DBCMD
-
- bra exit_ddr
- nop
-
- .align 2
-
-EXPEVT_A: .long 0xff000024
-EXPEVT_POWER_ON_RESET: .long 0x00000000
-
-/*------- Reset -------*/
-MRSTCR0_A: .long 0xffd50030
-MRSTCR0_D: .long 0xfe1ffe7f
-MRSTCR1_A: .long 0xffd50034
-MRSTCR1_D: .long 0xfff3ffff
-
-/*------- DDR3IF -------*/
-DBCMD_A: .long 0xfe800018
-DBKIND_A: .long 0xfe800020
-DBCONF_A: .long 0xfe800024
-DBTR0_A: .long 0xfe800040
-DBTR1_A: .long 0xfe800044
-DBTR2_A: .long 0xfe800048
-DBTR3_A: .long 0xfe800050
-DBTR4_A: .long 0xfe800054
-DBTR5_A: .long 0xfe800058
-DBTR6_A: .long 0xfe80005c
-DBTR7_A: .long 0xfe800060
-DBTR8_A: .long 0xfe800064
-DBTR9_A: .long 0xfe800068
-DBTR10_A: .long 0xfe80006c
-DBTR11_A: .long 0xfe800070
-DBTR12_A: .long 0xfe800074
-DBTR13_A: .long 0xfe800078
-DBTR14_A: .long 0xfe80007c
-DBTR15_A: .long 0xfe800080
-DBTR16_A: .long 0xfe800084
-DBTR17_A: .long 0xfe800088
-DBTR18_A: .long 0xfe80008c
-DBTR19_A: .long 0xfe800090
-DBRNK0_A: .long 0xfe800100
-DBPDCNT0_A: .long 0xfe800200
-DBPDCNT1_A: .long 0xfe800204
-DBPDCNT2_A: .long 0xfe800208
-DBPDCNT3_A: .long 0xfe80020c
-DBPDLCK_A: .long 0xfe800280
-DBPDRGA_A: .long 0xfe800290
-DBPDRGD_A: .long 0xfe8002a0
-DBADJ0_A: .long 0xfe8000c0
-DBADJ1_A: .long 0xfe8000c4
-DBADJ2_A: .long 0xfe8000c8
-DBRFCNF0_A: .long 0xfe8000e0
-DBRFCNF1_A: .long 0xfe8000e4
-DBRFCNF2_A: .long 0xfe8000e8
-DBCALCNF_A: .long 0xfe8000f4
-DBRFEN_A: .long 0xfe800014
-DBACEN_A: .long 0xfe800010
-DBWAIT_A: .long 0xfe80001c
-
-WAIT_OSC_TIME: .long 6000
-WAIT_30US: .long 13333
-
-DBCMD_RSTL_VAL: .long 0x20000000
-DBCMD_PDEN_VAL: .long 0x1000d73c
-DBCMD_WAIT_VAL: .long 0x0000d73c
-DBCMD_RSTH_VAL: .long 0x2100d73c
-DBCMD_PDXT_VAL: .long 0x110000c8
-DBCMD_MRS0_VAL: .long 0x28000930
-DBCMD_MRS1_VAL: .long 0x29000004
-DBCMD_MRS2_VAL: .long 0x2a000008
-DBCMD_MRS3_VAL: .long 0x2b000000
-DBCMD_ZQCL_VAL: .long 0x03000200
-DBCMD_REF_VAL: .long 0x0c000000
-DBCMD_SRXT_VAL: .long 0x19000000
-DBKIND_D: .long 0x00000007
-DBCONF_D: .long 0x0f030a01
-DBTR0_D: .long 0x00000007
-DBTR1_D: .long 0x00000006
-DBTR2_D: .long 0x00000000
-DBTR3_D: .long 0x00000007
-DBTR4_D: .long 0x00070007
-DBTR5_D: .long 0x0000001b
-DBTR6_D: .long 0x00000014
-DBTR7_D: .long 0x00000005
-DBTR8_D: .long 0x00000015
-DBTR9_D: .long 0x00000006
-DBTR10_D: .long 0x00000008
-DBTR11_D: .long 0x00000007
-DBTR12_D: .long 0x0000000e
-DBTR13_D: .long 0x00000056
-DBTR14_D: .long 0x00000006
-DBTR15_D: .long 0x00000004
-DBTR16_D: .long 0x00150002
-DBTR17_D: .long 0x000c0017
-DBTR18_D: .long 0x00000200
-DBTR19_D: .long 0x00000040
-DBRNK0_D: .long 0x00000001
-DBPDCNT0_D: .long 0x00000001
-DBPDCNT1_D: .long 0x00000001
-DBPDCNT2_D: .long 0x00000000
-DBPDCNT3_D: .long 0x00004010
-DBPDLCK_D: .long 0x0000a55a
-DBPDRGA_D: .long 0x00000028
-DBPDRGD_D: .long 0x00017100
-
-DBADJ0_D: .long 0x00000000
-DBADJ1_D: .long 0x00000000
-DBADJ2_D: .long 0x18061806
-DBRFCNF0_D: .long 0x000001ff
-DBRFCNF1_D: .long 0x08001000
-DBRFCNF2_D: .long 0x00000000
-DBCALCNF_D: .long 0x0000ffff
-DBRFEN_D: .long 0x00000001
-DBACEN_D: .long 0x00000001
-
- .align 2
-exit_ddr:
-#if defined(CONFIG_SH_32BIT)
- /*------- set PMB -------*/
- write32 PASCR_A, PASCR_29BIT_D
- write32 MMUCR_A, MMUCR_D
-
- /*****************************************************************
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x00000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- */
- write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
- write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
- write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
- write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
- write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
- write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
-
- write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
-
- write32 PASCR_A, PASCR_INIT
- mov.l DUMMY_ADDR, r0
- icbi @r0
-#endif /* if defined(CONFIG_SH_32BIT) */
-
-exit_pmb:
- /* CPU is running on ILRAM? */
- mov r14, r0
- tst #1, r0
- bt 1f
-
- mov.l _stack_ilram, r15
- mov.l _spiboot_main, r0
-100: bsrf r0
- nop
-
- .align 2
-_spiboot_main: .long (spiboot_main - (100b + 4))
-_stack_ilram: .long 0xe5204000
-
-1:
- write32 CCR_A, CCR_D
-
- rts
- nop
-
- .align 2
-
-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
-PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
-PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
-PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
-PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
-PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
-PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
-PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
-PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
-PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
-PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
-PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
-PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
-PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
-PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
-PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
-
-PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
-PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
-PMB_ADDR_NOT_USE_D: .long 0x00000000
-
-PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
-PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
-PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
-
-/* ppn ub v s1 s0 c wt */
-PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
-
-PASCR_A: .long 0xff000070
-DUMMY_ADDR: .long 0xa0000000
-PASCR_29BIT_D: .long 0x00000000
-PASCR_INIT: .long 0x80000080
-MMUCR_A: .long 0xff000010
-MMUCR_D: .long 0x00000004 /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */
-
-CCR_A: .long CCR
-CCR_D: .long CCR_CACHE_INIT
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <flash.h>
-#include <init.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmc.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <linux/delay.h>
-
-int checkboard(void)
-{
- puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
-
- return 0;
-}
-
-static void init_gpio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
- struct sermux_regs *sermux = SERMUX_BASE;
-
- /* GPIO */
- writew(0x0000, &gpio->pacr); /* GETHER */
- writew(0x0001, &gpio->pbcr); /* INTC */
- writew(0x0000, &gpio->pccr); /* PWMU, INTC */
- writew(0xeaff, &gpio->pecr); /* GPIO */
- writew(0x0000, &gpio->pfcr); /* WDT */
- writew(0x0000, &gpio->phcr); /* SPI1 */
- writew(0x0000, &gpio->picr); /* SDHI */
- writew(0x0003, &gpio->pkcr); /* SerMux */
- writew(0x0000, &gpio->plcr); /* SerMux */
- writew(0x0000, &gpio->pmcr); /* RIIC */
- writew(0x0000, &gpio->pncr); /* USB, SGPIO */
- writew(0x0000, &gpio->pocr); /* SGPIO */
- writew(0xd555, &gpio->pqcr); /* GPIO */
- writew(0x0000, &gpio->prcr); /* RIIC */
- writew(0x0000, &gpio->pscr); /* RIIC */
- writeb(0x00, &gpio->pudr);
- writew(0x5555, &gpio->pucr); /* Debug LED */
- writew(0x0000, &gpio->pvcr); /* RSPI */
- writew(0x0000, &gpio->pwcr); /* EVC */
- writew(0x0000, &gpio->pxcr); /* LBSC */
- writew(0x0000, &gpio->pycr); /* LBSC */
- writew(0x0000, &gpio->pzcr); /* eMMC */
- writew(0xfe00, &gpio->psel0);
- writew(0xff00, &gpio->psel3);
- writew(0x771f, &gpio->psel4);
- writew(0x00ff, &gpio->psel6);
- writew(0xfc00, &gpio->psel7);
-
- writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
-}
-
-static void init_usb_phy(void)
-{
- struct usb_common_regs *common0 = USB0_COMMON_BASE;
- struct usb_common_regs *common1 = USB1_COMMON_BASE;
- struct usb0_phy_regs *phy = USB0_PHY_BASE;
- struct usb1_port_regs *port = USB1_PORT_BASE;
- struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
-
- writew(0x0100, &phy->reset); /* set reset */
- /* port0 = USB0, port1 = USB1 */
- writew(0x0002, &phy->portsel);
- writel(0x0001, &port->port1sel); /* port1 = Host */
- writew(0x0111, &phy->reset); /* clear reset */
-
- writew(0x4000, &common0->suspmode);
- writew(0x4000, &common1->suspmode);
-
-#if defined(__LITTLE_ENDIAN)
- writel(0x00000000, &align->ehcidatac);
- writel(0x00000000, &align->ohcidatac);
-#endif
-}
-
-static void init_gether_mdio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
-}
-
-static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = GETHER0_MAC_BASE;
- else
- ether = GETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-/*****************************************************************
- * This PMB must be set on this timing. The lowlevel_init is run on
- * Area 0(phys 0x00000000), so we have to map it.
- *
- * The new PMB table is following:
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x40000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 2 0xb0000000 0x50000000 1 128M 0 1
- * 3 0xb8000000 0x58000000 1 128M 0 1
- * 4 0x80000000 0x40000000 1 128M 1 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- * 6 0x90000000 0x50000000 1 128M 1 1
- * 7 0x98000000 0x58000000 1 128M 1 1
- */
-static void set_pmb_on_board_init(void)
-{
- struct mmu_regs *mmu = MMU_BASE;
-
- /* clear ITLB */
- writel(0x00000004, &mmu->mmucr);
-
- /* delete PMB for SPIBOOT */
- writel(0, PMB_ADDR_BASE(0));
- writel(0, PMB_DATA_BASE(0));
-
- /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
- /* ppn ub v s1 s0 c wt */
- writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
- writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
- writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
- writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
- writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
- writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
- writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
- writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
- writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
- writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
- writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
- writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
-}
-
-int board_init(void)
-{
- init_gpio();
- set_pmb_on_board_init();
-
- init_usb_phy();
- init_gether_mdio();
-
- return 0;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
- udelay(1);
- writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
- udelay(200);
-
- return mmcif_mmc_init();
-}
-
-static int get_sh_eth_mac_raw(unsigned char *buf, int size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (spi == NULL) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
- if (ret) {
- printf("%s: spi_flash read failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-#endif
-
- return 0;
-}
-
-static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
-{
- memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
- SH7752EVB_ETHERNET_MAC_SIZE);
- mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
-
- return 0;
-}
-
-static void init_ethernet_mac(void)
-{
- char mac_string[64];
- char env_string[64];
- int i;
- unsigned char *buf;
-
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return;
- }
- get_sh_eth_mac_raw(buf, 256);
-
- /* Gigabit Ethernet */
- for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i == 0)
- env_set("ethaddr", mac_string);
- else {
- sprintf(env_string, "eth%daddr", i);
- env_set(env_string, mac_string);
- }
- set_mac_to_sh_giga_eth_register(i, mac_string);
- }
-
- free(buf);
-}
-
-int board_late_init(void)
-{
- init_ethernet_mac();
-
- return 0;
-}
-
-#ifdef CONFIG_DEPRECATED
-int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int i, ret;
- char mac_string[256];
- struct spi_flash *spi;
- unsigned char *buf;
-
- if (argc != 3) {
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return 1;
- }
-
- get_sh_eth_mac_raw(buf, 256);
-
- /* print current MAC address */
- for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- printf("GETHERC ch%d = %s\n", i, mac_string);
- }
- free(buf);
- return 0;
- }
-
- /* new setting */
- memset(mac_string, 0xff, sizeof(mac_string));
- sprintf(mac_string, "%s\t%s",
- argv[1], argv[2]);
-
- /* write MAC data to SPI rom */
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
- SH7752EVB_SPI_SECTOR_SIZE);
- if (ret) {
- printf("%s: spi_flash erase failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
- sizeof(mac_string), mac_string);
- if (ret) {
- printf("%s: spi_flash write failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- puts("The writing of the MAC address to SPI ROM was completed.\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- write_mac, 3, 1, do_write_mac,
- "write MAC address for GETHERC",
- "[GETHERC ch0] [GETHERC ch1]\n"
-);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is subject to the terms and conditions of the GNU Lesser
- * General Public License. See the file "COPYING.LIB" in the main
- * directory of this archive for more details.
- */
-
-#include <common.h>
-
-#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
-#define CONFIG_SPI_ADDR 0x00000000
-#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
-#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
-
-#define SPIWDMADR 0xFE001018
-#define SPIWDMCNTR 0xFE001020
-#define SPIDMCOR 0xFE001028
-#define SPIDMINTSR 0xFE001188
-#define SPIDMINTMR 0xFE001190
-
-#define SPIDMINTSR_DMEND 0x00000004
-
-#define TBR 0xFE002000
-#define RBR 0xFE002000
-
-#define CR1 0xFE002008
-#define CR2 0xFE002010
-#define CR3 0xFE002018
-#define CR4 0xFE002020
-
-/* CR1 */
-#define SPI_TBE 0x80
-#define SPI_TBF 0x40
-#define SPI_RBE 0x20
-#define SPI_RBF 0x10
-#define SPI_PFONRD 0x08
-#define SPI_SSDB 0x04
-#define SPI_SSD 0x02
-#define SPI_SSA 0x01
-
-/* CR2 */
-#define SPI_RSTF 0x80
-#define SPI_LOOPBK 0x40
-#define SPI_CPOL 0x20
-#define SPI_CPHA 0x10
-#define SPI_L1M0 0x08
-
-/* CR4 */
-#define SPI_TBEI 0x80
-#define SPI_TBFI 0x40
-#define SPI_RBEI 0x20
-#define SPI_RBFI 0x10
-#define SPI_SpiS0 0x02
-#define SPI_SSS 0x01
-
-#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
-#define spi_read(addr) (*(volatile unsigned long *)(addr))
-
-/* M25P80 */
-#define M25_READ 0x03
-
-#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
-static void __uses_spiboot2 spi_reset(void)
-{
- int timeout = 0x00100000;
-
- /* Make sure the last transaction is finalized */
- spi_write(0x00, CR3);
- spi_write(0x02, CR1);
- while (!(spi_read(CR4) & SPI_SpiS0)) {
- if (timeout-- < 0)
- break;
- }
- spi_write(0x00, CR1);
-
- spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
- spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
-
- spi_write(0, SPIDMCOR);
-}
-
-static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
- unsigned long len)
-{
- spi_write(M25_READ, TBR);
- spi_write((addr >> 16) & 0xFF, TBR);
- spi_write((addr >> 8) & 0xFF, TBR);
- spi_write(addr & 0xFF, TBR);
-
- spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
- spi_write((unsigned long)buf, SPIWDMADR);
- spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
- spi_write(1, SPIDMCOR);
-
- spi_write(0xff, CR3);
- spi_write(spi_read(CR1) | SPI_SSDB, CR1);
- spi_write(spi_read(CR1) | SPI_SSA, CR1);
-
- while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
- ;
-
- /* Nagate SP0-SS0 */
- spi_write(0, CR1);
-}
-
-void __uses_spiboot2 spiboot_main(void)
-{
- void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
-
- spi_reset();
- spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
- CONFIG_SPI_LENGTH);
-
- _start();
-}
+++ /dev/null
-if TARGET_SH7753EVB
-
-config SYS_BOARD
- default "sh7753evb"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7753evb"
-
-endif
+++ /dev/null
-SH7753EVB BOARD
-#M: -
-S: Maintained
-F: board/renesas/sh7753evb/
-F: include/configs/sh7753evb.h
-F: configs/sh7753evb_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-#
-
-obj-y := sh7753evb.o spi-boot.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Renesas Solutions Corp.
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-.macro or32, addr, data
- mov.l \addr, r1
- mov.l \data, r0
- mov.l @r1, r2
- or r2, r0
- mov.l r0, @r1
-.endm
-
-.macro wait_DBCMD
- mov.l DBWAIT_A, r0
- mov.l @r0, r1
-.endm
-
- .global lowlevel_init
- .section .spiboot1.text
- .align 2
-
-lowlevel_init:
- mov #0, r14
- mova 2f, r0
- mov.l PC_MASK, r1
- tst r0, r1
- bf 2f
-
- bra exit_pmb
- nop
-
- .align 2
-
-/* If CPU runs on SDRAM (PC=0x5???????) or not. */
-PC_MASK: .long 0x20000000
-
-2:
- mov #1, r14
-
- mov.l EXPEVT_A, r0
- mov.l @r0, r0
- mov.l EXPEVT_POWER_ON_RESET, r1
- cmp/eq r0, r1
- bt 1f
-
- /*
- * If EXPEVT value is manual reset or tlb multipul-hit,
- * initialization of DBSC3 is not necessary.
- */
- bra exit_ddr
- nop
-
-1:
- /*------- Reset -------*/
- write32 MRSTCR0_A, MRSTCR0_D
- write32 MRSTCR1_A, MRSTCR1_D
-
- /* For Core Reset */
- mov.l DBACEN_A, r0
- mov.l @r0, r0
- cmp/eq #0, r0
- bt 3f
-
- /*
- * If DBACEN == 1(DBSC was already enabled), we have to avoid the
- * initialization of DDR3-SDRAM.
- */
- bra exit_ddr
- nop
-
-3:
- /*------- DBSC3 -------*/
- /* oscillation stabilization time */
- wait_timer WAIT_OSC_TIME
-
- /* step 3 */
- write32 DBKIND_A, DBKIND_D
-
- /* step 4 */
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBTR4_A, DBTR4_D
- write32 DBTR5_A, DBTR5_D
- write32 DBTR6_A, DBTR6_D
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D
- write32 DBTR13_A, DBTR13_D
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D
- write32 DBTR17_A, DBTR17_D
- write32 DBTR18_A, DBTR18_D
- write32 DBTR19_A, DBTR19_D
- write32 DBRNK0_A, DBRNK0_D
- write32 DBADJ0_A, DBADJ0_D
- write32 DBADJ2_A, DBADJ2_D
-
- /* step 5 */
- write32 DBCMD_A, DBCMD_RSTL_VAL
- wait_timer WAIT_30US
-
- /* step 6 */
- write32 DBCMD_A, DBCMD_PDEN_VAL
-
- /* step 7 */
- write32 DBPDCNT3_A, DBPDCNT3_D
-
- /* step 8 */
- write32 DBPDCNT1_A, DBPDCNT1_D
- write32 DBPDCNT2_A, DBPDCNT2_D
- write32 DBPDLCK_A, DBPDLCK_D
- write32 DBPDRGA_A, DBPDRGA_D
- write32 DBPDRGD_A, DBPDRGD_D
-
- /* step 9 */
- wait_timer WAIT_30US
-
- /* step 10 */
- write32 DBPDCNT0_A, DBPDCNT0_D
-
- /* step 11 */
- wait_timer WAIT_30US
- wait_timer WAIT_30US
-
- /* step 12 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- wait_DBCMD
-
- /* step 13 */
- write32 DBCMD_A, DBCMD_RSTH_VAL
- wait_DBCMD
-
- /* step 14 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
-
- /* step 15 */
- write32 DBCMD_A, DBCMD_PDXT_VAL
-
- /* step 16 */
- write32 DBCMD_A, DBCMD_MRS2_VAL
-
- /* step 17 */
- write32 DBCMD_A, DBCMD_MRS3_VAL
-
- /* step 18 */
- write32 DBCMD_A, DBCMD_MRS1_VAL
-
- /* step 19 */
- write32 DBCMD_A, DBCMD_MRS0_VAL
- write32 DBPDNCNF_A, DBPDNCNF_D
-
- /* step 20 */
- write32 DBCMD_A, DBCMD_ZQCL_VAL
-
- write32 DBCMD_A, DBCMD_REF_VAL
- write32 DBCMD_A, DBCMD_REF_VAL
- wait_DBCMD
-
- /* step 21 */
- write32 DBCALTR_A, DBCALTR_D
-
- /* step 22 */
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D
- write32 DBRFCNF2_A, DBRFCNF2_D
-
- /* step 23 */
- write32 DBCALCNF_A, DBCALCNF_D
-
- /* step 24 */
- write32 DBRFEN_A, DBRFEN_D
- write32 DBCMD_A, DBCMD_SRXT_VAL
-
- /* step 25 */
- write32 DBACEN_A, DBACEN_D
-
- /* step 26 */
- wait_DBCMD
-
- bra exit_ddr
- nop
-
- .align 2
-
-EXPEVT_A: .long 0xff000024
-EXPEVT_POWER_ON_RESET: .long 0x00000000
-
-/*------- Reset -------*/
-MRSTCR0_A: .long 0xffd50030
-MRSTCR0_D: .long 0xfe1ffe7f
-MRSTCR1_A: .long 0xffd50034
-MRSTCR1_D: .long 0xfff3ffff
-
-/*------- DBSC3 -------*/
-DBCMD_A: .long 0xfe800018
-DBKIND_A: .long 0xfe800020
-DBCONF_A: .long 0xfe800024
-DBTR0_A: .long 0xfe800040
-DBTR1_A: .long 0xfe800044
-DBTR2_A: .long 0xfe800048
-DBTR3_A: .long 0xfe800050
-DBTR4_A: .long 0xfe800054
-DBTR5_A: .long 0xfe800058
-DBTR6_A: .long 0xfe80005c
-DBTR7_A: .long 0xfe800060
-DBTR8_A: .long 0xfe800064
-DBTR9_A: .long 0xfe800068
-DBTR10_A: .long 0xfe80006c
-DBTR11_A: .long 0xfe800070
-DBTR12_A: .long 0xfe800074
-DBTR13_A: .long 0xfe800078
-DBTR14_A: .long 0xfe80007c
-DBTR15_A: .long 0xfe800080
-DBTR16_A: .long 0xfe800084
-DBTR17_A: .long 0xfe800088
-DBTR18_A: .long 0xfe80008c
-DBTR19_A: .long 0xfe800090
-DBRNK0_A: .long 0xfe800100
-DBPDCNT0_A: .long 0xfe800200
-DBPDCNT1_A: .long 0xfe800204
-DBPDCNT2_A: .long 0xfe800208
-DBPDCNT3_A: .long 0xfe80020c
-DBPDLCK_A: .long 0xfe800280
-DBPDRGA_A: .long 0xfe800290
-DBPDRGD_A: .long 0xfe8002a0
-DBADJ0_A: .long 0xfe8000c0
-DBADJ2_A: .long 0xfe8000c8
-DBRFCNF0_A: .long 0xfe8000e0
-DBRFCNF1_A: .long 0xfe8000e4
-DBRFCNF2_A: .long 0xfe8000e8
-DBCALCNF_A: .long 0xfe8000f4
-DBRFEN_A: .long 0xfe800014
-DBACEN_A: .long 0xfe800010
-DBWAIT_A: .long 0xfe80001c
-DBCALTR_A: .long 0xfe8000f8
-DBPDNCNF_A: .long 0xfe800180
-
-WAIT_OSC_TIME: .long 6000
-WAIT_30US: .long 13333
-
-DBCMD_RSTL_VAL: .long 0x20000000
-DBCMD_PDEN_VAL: .long 0x1000d73c
-DBCMD_WAIT_VAL: .long 0x0000d73c
-DBCMD_RSTH_VAL: .long 0x2100d73c
-DBCMD_PDXT_VAL: .long 0x110000c8
-DBCMD_MRS0_VAL: .long 0x28000930
-DBCMD_MRS1_VAL: .long 0x29000004
-DBCMD_MRS2_VAL: .long 0x2a000008
-DBCMD_MRS3_VAL: .long 0x2b000000
-DBCMD_ZQCL_VAL: .long 0x03000200
-DBCMD_REF_VAL: .long 0x0c000000
-DBCMD_SRXT_VAL: .long 0x19000000
-DBKIND_D: .long 0x00000007
-DBCONF_D: .long 0x0f030a01
-DBTR0_D: .long 0x00000007
-DBTR1_D: .long 0x00000006
-DBTR2_D: .long 0x00000000
-DBTR3_D: .long 0x00000007
-DBTR4_D: .long 0x00070007
-DBTR5_D: .long 0x0000001b
-DBTR6_D: .long 0x00000014
-DBTR7_D: .long 0x00000004
-DBTR8_D: .long 0x00000014
-DBTR9_D: .long 0x00000004
-DBTR10_D: .long 0x00000008
-DBTR11_D: .long 0x00000007
-DBTR12_D: .long 0x0000000e
-DBTR13_D: .long 0x000000a0
-DBTR14_D: .long 0x00060006
-DBTR15_D: .long 0x00000003
-DBTR16_D: .long 0x00160002
-DBTR17_D: .long 0x000c0000
-DBTR18_D: .long 0x00000200
-DBTR19_D: .long 0x00000040
-DBRNK0_D: .long 0x00000001
-DBPDCNT0_D: .long 0x00000001
-DBPDCNT1_D: .long 0x00000001
-DBPDCNT2_D: .long 0x00000000
-DBPDCNT3_D: .long 0x00004010
-DBPDLCK_D: .long 0x0000a55a
-DBPDRGA_D: .long 0x00000028
-DBPDRGD_D: .long 0x00017100
-
-DBADJ0_D: .long 0x00010000
-DBADJ2_D: .long 0x18061806
-DBRFCNF0_D: .long 0x000001ff
-DBRFCNF1_D: .long 0x00081040
-DBRFCNF2_D: .long 0x00000000
-DBCALCNF_D: .long 0x0000ffff
-DBRFEN_D: .long 0x00000001
-DBACEN_D: .long 0x00000001
-DBCALTR_D: .long 0x08200820
-DBPDNCNF_D: .long 0x00000001
-
- .align 2
-exit_ddr:
-#if defined(CONFIG_SH_32BIT)
- /*------- set PMB -------*/
- write32 PASCR_A, PASCR_29BIT_D
- write32 MMUCR_A, MMUCR_D
-
- /*****************************************************************
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x00000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- */
- write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
- write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
- write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
- write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
- write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
- write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
-
- write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
-
- write32 PASCR_A, PASCR_INIT
- mov.l DUMMY_ADDR, r0
- icbi @r0
-#endif /* if defined(CONFIG_SH_32BIT) */
-
-exit_pmb:
- /* CPU is running on ILRAM? */
- mov r14, r0
- tst #1, r0
- bt 1f
-
- mov.l _stack_ilram, r15
- mov.l _spiboot_main, r0
-100: bsrf r0
- nop
-
- .align 2
-_spiboot_main: .long (spiboot_main - (100b + 4))
-_stack_ilram: .long 0xe5204000
-
-1:
- write32 CCR_A, CCR_D
-
- rts
- nop
-
- .align 2
-
-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
-PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
-PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
-PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
-PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
-PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
-PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
-PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
-PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
-PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
-PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
-PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
-PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
-PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
-PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
-PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
-
-PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
-PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
-PMB_ADDR_NOT_USE_D: .long 0x00000000
-
-PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
-PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
-PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
-
-/* ppn ub v s1 s0 c wt */
-PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
-
-PASCR_A: .long 0xff000070
-DUMMY_ADDR: .long 0xa0000000
-PASCR_29BIT_D: .long 0x00000000
-PASCR_INIT: .long 0x80000080
-MMUCR_A: .long 0xff000010
-MMUCR_D: .long 0x00000004 /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */
-
-CCR_A: .long CCR
-CCR_D: .long CCR_CACHE_INIT
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <flash.h>
-#include <init.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmc.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <linux/delay.h>
-
-int checkboard(void)
-{
- puts("BOARD: SH7753 EVB\n");
-
- return 0;
-}
-
-static void init_gpio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
- struct sermux_regs *sermux = SERMUX_BASE;
-
- /* GPIO */
- writew(0x0000, &gpio->pacr); /* GETHER */
- writew(0x0001, &gpio->pbcr); /* INTC */
- writew(0x0000, &gpio->pccr); /* PWMU, INTC */
- writew(0x0000, &gpio->pdcr); /* SPI0 */
- writew(0xeaff, &gpio->pecr); /* GPIO */
- writew(0x0000, &gpio->pfcr); /* WDT */
- writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
- writew(0x0000, &gpio->phcr); /* SPI1 */
- writew(0x0000, &gpio->picr); /* SDHI */
- writew(0x0000, &gpio->pjcr); /* SCIF4 */
- writew(0x0003, &gpio->pkcr); /* SerMux */
- writew(0x0000, &gpio->plcr); /* SerMux */
- writew(0x0000, &gpio->pmcr); /* RIIC */
- writew(0x0000, &gpio->pncr); /* USB, SGPIO */
- writew(0x0000, &gpio->pocr); /* SGPIO */
- writew(0xd555, &gpio->pqcr); /* GPIO */
- writew(0x0000, &gpio->prcr); /* RIIC */
- writew(0x0000, &gpio->pscr); /* RIIC */
- writew(0x0000, &gpio->ptcr); /* STATUS */
- writeb(0x00, &gpio->pudr);
- writew(0x5555, &gpio->pucr); /* Debug LED */
- writew(0x0000, &gpio->pvcr); /* RSPI */
- writew(0x0000, &gpio->pwcr); /* EVC */
- writew(0x0000, &gpio->pxcr); /* LBSC */
- writew(0x0000, &gpio->pycr); /* LBSC */
- writew(0x0000, &gpio->pzcr); /* eMMC */
- writew(0xfe00, &gpio->psel0);
- writew(0x0000, &gpio->psel1);
- writew(0x3000, &gpio->psel2);
- writew(0xff00, &gpio->psel3);
- writew(0x771f, &gpio->psel4);
- writew(0x0ffc, &gpio->psel5);
- writew(0x00ff, &gpio->psel6);
- writew(0xfc00, &gpio->psel7);
-
- writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
-}
-
-static void init_usb_phy(void)
-{
- struct usb_common_regs *common0 = USB0_COMMON_BASE;
- struct usb_common_regs *common1 = USB1_COMMON_BASE;
- struct usb0_phy_regs *phy = USB0_PHY_BASE;
- struct usb1_port_regs *port = USB1_PORT_BASE;
- struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
-
- writew(0x0100, &phy->reset); /* set reset */
- /* port0 = USB0, port1 = USB1 */
- writew(0x0002, &phy->portsel);
- writel(0x0001, &port->port1sel); /* port1 = Host */
- writew(0x0111, &phy->reset); /* clear reset */
-
- writew(0x4000, &common0->suspmode);
- writew(0x4000, &common1->suspmode);
-
-#if defined(__LITTLE_ENDIAN)
- writel(0x00000000, &align->ehcidatac);
- writel(0x00000000, &align->ohcidatac);
-#endif
-}
-
-static void init_gether_mdio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
-}
-
-static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = GETHER0_MAC_BASE;
- else
- ether = GETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-#if defined(CONFIG_SH_32BIT)
-/*****************************************************************
- * This PMB must be set on this timing. The lowlevel_init is run on
- * Area 0(phys 0x00000000), so we have to map it.
- *
- * The new PMB table is following:
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x40000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 2 0xb0000000 0x50000000 1 128M 0 1
- * 3 0xb8000000 0x58000000 1 128M 0 1
- * 4 0x80000000 0x40000000 1 128M 1 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- * 6 0x90000000 0x50000000 1 128M 1 1
- * 7 0x98000000 0x58000000 1 128M 1 1
- */
-static void set_pmb_on_board_init(void)
-{
- struct mmu_regs *mmu = MMU_BASE;
-
- /* clear ITLB */
- writel(0x00000004, &mmu->mmucr);
-
- /* delete PMB for SPIBOOT */
- writel(0, PMB_ADDR_BASE(0));
- writel(0, PMB_DATA_BASE(0));
-
- /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
- /* ppn ub v s1 s0 c wt */
- writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
- writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
- writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
- writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
- writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
- writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
- writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
- writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
- writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
- writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
- writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
- writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
-}
-#endif
-
-int board_init(void)
-{
- struct gether_control_regs *gether = GETHER_CONTROL_BASE;
-
- init_gpio();
-#if defined(CONFIG_SH_32BIT)
- set_pmb_on_board_init();
-#endif
-
- /* Sets TXnDLY to B'010 */
- writel(0x00000202, &gether->gbecont);
-
- init_usb_phy();
- init_gether_mdio();
-
- return 0;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
- udelay(1);
- writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
- udelay(200);
-
- return mmcif_mmc_init();
-}
-
-static int get_sh_eth_mac_raw(unsigned char *buf, int size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (spi == NULL) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
- if (ret) {
- printf("%s: spi_flash read failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-#endif
-
- return 0;
-}
-
-static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
-{
- memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
- SH7753EVB_ETHERNET_MAC_SIZE);
- mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
-
- return 0;
-}
-
-static void init_ethernet_mac(void)
-{
- char mac_string[64];
- char env_string[64];
- int i;
- unsigned char *buf;
-
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return;
- }
- get_sh_eth_mac_raw(buf, 256);
-
- /* Gigabit Ethernet */
- for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i == 0)
- env_set("ethaddr", mac_string);
- else {
- sprintf(env_string, "eth%daddr", i);
- env_set(env_string, mac_string);
- }
- set_mac_to_sh_giga_eth_register(i, mac_string);
- }
-
- free(buf);
-}
-
-int board_late_init(void)
-{
- init_ethernet_mac();
-
- return 0;
-}
-
-#ifdef CONFIG_DEPRECATED
-int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int i, ret;
- char mac_string[256];
- struct spi_flash *spi;
- unsigned char *buf;
-
- if (argc != 3) {
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return 1;
- }
-
- get_sh_eth_mac_raw(buf, 256);
-
- /* print current MAC address */
- for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- printf("GETHERC ch%d = %s\n", i, mac_string);
- }
- free(buf);
- return 0;
- }
-
- /* new setting */
- memset(mac_string, 0xff, sizeof(mac_string));
- sprintf(mac_string, "%s\t%s",
- argv[1], argv[2]);
-
- /* write MAC data to SPI rom */
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
- SH7753EVB_SPI_SECTOR_SIZE);
- if (ret) {
- printf("%s: spi_flash erase failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
- sizeof(mac_string), mac_string);
- if (ret) {
- printf("%s: spi_flash write failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- puts("The writing of the MAC address to SPI ROM was completed.\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- write_mac, 3, 1, do_write_mac,
- "write MAC address for GETHERC",
- "[GETHERC ch0] [GETHERC ch1]\n"
-);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Renesas Solutions Corp.
- */
-
-#include <common.h>
-
-#define CONFIG_SPI_ADDR 0x00000000
-#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000)
-#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE)
-
-#define SPIWDMADR 0xFE001018
-#define SPIWDMCNTR 0xFE001020
-#define SPIDMCOR 0xFE001028
-#define SPIDMINTSR 0xFE001188
-#define SPIDMINTMR 0xFE001190
-
-#define SPIDMINTSR_DMEND 0x00000004
-
-#define TBR 0xFE002000
-#define RBR 0xFE002000
-
-#define CR1 0xFE002008
-#define CR2 0xFE002010
-#define CR3 0xFE002018
-#define CR4 0xFE002020
-#define CR7 0xFE002038
-#define CR8 0xFE002040
-
-/* CR1 */
-#define SPI_TBE 0x80
-#define SPI_TBF 0x40
-#define SPI_RBE 0x20
-#define SPI_RBF 0x10
-#define SPI_PFONRD 0x08
-#define SPI_SSDB 0x04
-#define SPI_SSD 0x02
-#define SPI_SSA 0x01
-
-/* CR2 */
-#define SPI_RSTF 0x80
-#define SPI_LOOPBK 0x40
-#define SPI_CPOL 0x20
-#define SPI_CPHA 0x10
-#define SPI_L1M0 0x08
-
-/* CR4 */
-#define SPI_TBEI 0x80
-#define SPI_TBFI 0x40
-#define SPI_RBEI 0x20
-#define SPI_RBFI 0x10
-#define SPI_SpiS0 0x02
-#define SPI_SSS 0x01
-
-/* CR7 */
-#define CR7_IDX_OR12 0x12
-#define OR12_ADDR32 0x00000001
-
-#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
-#define spi_read(addr) (*(volatile unsigned long *)(addr))
-
-/* M25P80 */
-#define M25_READ 0x03
-#define M25_READ_4BYTE 0x13
-
-extern void bss_start(void);
-
-#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
-static void __uses_spiboot2 spi_reset(void)
-{
- int timeout = 0x00100000;
-
- /* Make sure the last transaction is finalized */
- spi_write(0x00, CR3);
- spi_write(0x02, CR1);
- while (!(spi_read(CR4) & SPI_SpiS0)) {
- if (timeout-- < 0)
- break;
- }
- spi_write(0x00, CR1);
-
- spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
- spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
-
- spi_write(0, SPIDMCOR);
-}
-
-static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
- unsigned long len)
-{
- spi_write(CR7_IDX_OR12, CR7);
- if (spi_read(CR8) & OR12_ADDR32) {
- /* 4-bytes address mode */
- spi_write(M25_READ_4BYTE, TBR);
- spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */
- } else {
- /* 3-bytes address mode */
- spi_write(M25_READ, TBR);
- }
- spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */
- spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */
- spi_write(addr & 0xFF, TBR); /* ADDR7-0 */
-
- spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
- spi_write((unsigned long)buf, SPIWDMADR);
- spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
- spi_write(1, SPIDMCOR);
-
- spi_write(0xff, CR3);
- spi_write(spi_read(CR1) | SPI_SSDB, CR1);
- spi_write(spi_read(CR1) | SPI_SSA, CR1);
-
- while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
- ;
-
- /* Nagate SP0-SS0 */
- spi_write(0, CR1);
-}
-
-void __uses_spiboot2 spiboot_main(void)
-{
- /*
- * This code rounds len up for SPIWDMCNTR. We should set it to 0 in
- * lower 5-bits.
- */
- void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
- volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;
-
- spi_reset();
- spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);
-
- _start();
-}
+++ /dev/null
-if TARGET_SH7757LCR
-
-config SYS_BOARD
- default "sh7757lcr"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7757lcr"
-
-endif
+++ /dev/null
-SH7757LCR BOARD
-#M: -
-S: Maintained
-F: board/renesas/sh7757lcr/
-F: include/configs/sh7757lcr.h
-F: configs/sh7757lcr_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-#
-
-obj-y := sh7757lcr.o spi-boot.o
-extra-y += lowlevel_init.o
+++ /dev/null
-========================================
-Renesas R0P7757LC0030RL board
-========================================
-
-This board specification:
-=========================
-
-The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:
-
- - SH7757 (SH-4A)
- - DDR3-SDRAM 256MB (with ECC)
- - SPI ROM 8MB
- - 2D Graphic controller
- - Ethernet controller
- - eMMC 2GB
-
-
-configuration for This board:
-=============================
-
-You can select the configuration as follows:
-
- - make sh7757lcr_config
-
-
-This board specific command:
-============================
-
-This board has the following its specific command:
-
- - sh_g200
- - write_mac
-
-
-1. sh_g200
-
-If we run this command, SH4 can control the G200.
-The default setting is that SH4 cannot control the G200.
-
-
-2. write_mac
-
-You can write MAC address to SPI ROM.
-
- Usage 1) Write MAC address
-
- write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]
-
- For example)
- => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
- *) We have to input the command as a single line
- (without carriage return)
- *) We have to reset after input the command.
-
- Usage 2) Show current data
-
- write_mac
-
- For example)
- => write_mac
- ETHERC ch0 = 00:00:87:6c:21:80
- ETHERC ch1 = 00:00:87:6c:21:81
- GETHERC ch0 = 00:00:87:6c:21:82
- GETHERC ch1 = 00:00:87:6c:21:83
-
-
-Update SPI ROM:
-============================
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
- => sf probe 0
- 8192 KiB M25P64 at 0:0 is now current device
-3. Erase SPI ROM.
- => sf erase 0 80000
-4. Write u-boot image to SPI ROM.
- => sf write 0x89000000 0 80000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-.macro or32, addr, data
- mov.l \addr, r1
- mov.l \data, r0
- mov.l @r1, r2
- or r2, r0
- mov.l r0, @r1
-.endm
-
-.macro wait_DBCMD
- mov.l DBWAIT_A, r0
- mov.l @r0, r1
-.endm
-
- .global lowlevel_init
- .section .spiboot1.text
- .align 2
-
-lowlevel_init:
-
- /*------- GPIO -------*/
- write8 PGDR_A, PGDR_D /* eMMC power off */
-
- write16 PACR_A, PACR_D
- write16 PBCR_A, PBCR_D
- write16 PCCR_A, PCCR_D
- write16 PDCR_A, PDCR_D
- write16 PECR_A, PECR_D
- write16 PFCR_A, PFCR_D
- write16 PGCR_A, PGCR_D
- write16 PHCR_A, PHCR_D
- write16 PICR_A, PICR_D
- write16 PJCR_A, PJCR_D
- write16 PKCR_A, PKCR_D
- write16 PLCR_A, PLCR_D
- write16 PMCR_A, PMCR_D
- write16 PNCR_A, PNCR_D
- write16 POCR_A, POCR_D
- write16 PQCR_A, PQCR_D
- write16 PRCR_A, PRCR_D
- write16 PSCR_A, PSCR_D
- write16 PTCR_A, PTCR_D
- write16 PUCR_A, PUCR_D
- write16 PVCR_A, PVCR_D
- write16 PWCR_A, PWCR_D
- write16 PXCR_A, PXCR_D
- write16 PYCR_A, PYCR_D
- write16 PZCR_A, PZCR_D
- write16 PSEL0_A, PSEL0_D
- write16 PSEL1_A, PSEL1_D
- write16 PSEL2_A, PSEL2_D
- write16 PSEL3_A, PSEL3_D
- write16 PSEL4_A, PSEL4_D
- write16 PSEL5_A, PSEL5_D
- write16 PSEL6_A, PSEL6_D
- write16 PSEL7_A, PSEL7_D
- write16 PSEL8_A, PSEL8_D
-
- bra exit_gpio
- nop
-
- .align 4
-
-/*------- GPIO -------*/
-PGDR_A: .long 0xffec0040
-PACR_A: .long 0xffec0000
-PBCR_A: .long 0xffec0002
-PCCR_A: .long 0xffec0004
-PDCR_A: .long 0xffec0006
-PECR_A: .long 0xffec0008
-PFCR_A: .long 0xffec000a
-PGCR_A: .long 0xffec000c
-PHCR_A: .long 0xffec000e
-PICR_A: .long 0xffec0010
-PJCR_A: .long 0xffec0012
-PKCR_A: .long 0xffec0014
-PLCR_A: .long 0xffec0016
-PMCR_A: .long 0xffec0018
-PNCR_A: .long 0xffec001a
-POCR_A: .long 0xffec001c
-PQCR_A: .long 0xffec0020
-PRCR_A: .long 0xffec0022
-PSCR_A: .long 0xffec0024
-PTCR_A: .long 0xffec0026
-PUCR_A: .long 0xffec0028
-PVCR_A: .long 0xffec002a
-PWCR_A: .long 0xffec002c
-PXCR_A: .long 0xffec002e
-PYCR_A: .long 0xffec0030
-PZCR_A: .long 0xffec0032
-PSEL0_A: .long 0xffec0070
-PSEL1_A: .long 0xffec0072
-PSEL2_A: .long 0xffec0074
-PSEL3_A: .long 0xffec0076
-PSEL4_A: .long 0xffec0078
-PSEL5_A: .long 0xffec007a
-PSEL6_A: .long 0xffec007c
-PSEL7_A: .long 0xffec0082
-PSEL8_A: .long 0xffec0084
-
-PGDR_D: .long 0x80
-PACR_D: .long 0x0000
-PBCR_D: .long 0x0001
-PCCR_D: .long 0x0000
-PDCR_D: .long 0x0000
-PECR_D: .long 0x0000
-PFCR_D: .long 0x0000
-PGCR_D: .long 0x0000
-PHCR_D: .long 0x0000
-PICR_D: .long 0x0000
-PJCR_D: .long 0x0000
-PKCR_D: .long 0x0003
-PLCR_D: .long 0x0000
-PMCR_D: .long 0x0000
-PNCR_D: .long 0x0000
-POCR_D: .long 0x0000
-PQCR_D: .long 0xc000
-PRCR_D: .long 0x0000
-PSCR_D: .long 0x0000
-PTCR_D: .long 0x0000
-#if defined(CONFIG_SH7757_OFFSET_SPI)
-PUCR_D: .long 0x0055
-#else
-PUCR_D: .long 0x0000
-#endif
-PVCR_D: .long 0x0000
-PWCR_D: .long 0x0000
-PXCR_D: .long 0x0000
-PYCR_D: .long 0x0000
-PZCR_D: .long 0x0000
-PSEL0_D: .long 0xfe00
-PSEL1_D: .long 0x0000
-PSEL2_D: .long 0x3000
-PSEL3_D: .long 0xff00
-PSEL4_D: .long 0x771f
-PSEL5_D: .long 0x0ffc
-PSEL6_D: .long 0x00ff
-PSEL7_D: .long 0xfc00
-PSEL8_D: .long 0x0000
-
- .align 2
-
-exit_gpio:
- mov #0, r14
- mova 2f, r0
- mov.l PC_MASK, r1
- tst r0, r1
- bf 2f
-
- bra exit_pmb
- nop
-
- .align 2
-
-/* If CPU runs on SDRAM, PC is 0x8???????. */
-PC_MASK: .long 0x20000000
-
-2:
- mov #1, r14
-
- mov.l EXPEVT_A, r0
- mov.l @r0, r0
- mov.l EXPEVT_POWER_ON_RESET, r1
- cmp/eq r0, r1
- bt 1f
-
- /*
- * If EXPEVT value is manual reset or tlb multipul-hit,
- * initialization of DDR3IF is not necessary.
- */
- bra exit_ddr
- nop
-
-1:
- /* For Core Reset */
- mov.l DBACEN_A, r0
- mov.l @r0, r0
- cmp/eq #0, r0
- bt 3f
-
- /*
- * If DBACEN == 1(DBSC was already enabled), we have to avoid the
- * initialization of DDR3-SDRAM.
- */
- bra exit_ddr
- nop
-
-3:
- /*------- DDR3IF -------*/
- /* oscillation stabilization time */
- wait_timer WAIT_OSC_TIME
-
- /* step 3 */
- write32 DBCMD_A, DBCMD_RSTL_VAL
- wait_timer WAIT_30US
-
- /* step 4 */
- write32 DBCMD_A, DBCMD_PDEN_VAL
-
- /* step 5 */
- write32 DBKIND_A, DBKIND_D
-
- /* step 6 */
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBTR4_A, DBTR4_D
- write32 DBTR5_A, DBTR5_D
- write32 DBTR6_A, DBTR6_D
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D
- write32 DBTR13_A, DBTR13_D
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D
- write32 DBTR17_A, DBTR17_D
- write32 DBTR18_A, DBTR18_D
- write32 DBTR19_A, DBTR19_D
- write32 DBRNK0_A, DBRNK0_D
-
- /* step 7 */
- write32 DBPDCNT3_A, DBPDCNT3_D
-
- /* step 8 */
- write32 DBPDCNT1_A, DBPDCNT1_D
- write32 DBPDCNT2_A, DBPDCNT2_D
- write32 DBPDLCK_A, DBPDLCK_D
- write32 DBPDRGA_A, DBPDRGA_D
- write32 DBPDRGD_A, DBPDRGD_D
-
- /* step 9 */
- wait_timer WAIT_30US
-
- /* step 10 */
- write32 DBPDCNT0_A, DBPDCNT0_D
-
- /* step 11 */
- wait_timer WAIT_30US
- wait_timer WAIT_30US
-
- /* step 12 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- wait_DBCMD
-
- /* step 13 */
- write32 DBCMD_A, DBCMD_RSTH_VAL
- wait_DBCMD
-
- /* step 14 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
-
- /* step 15 */
- write32 DBCMD_A, DBCMD_PDXT_VAL
-
- /* step 16 */
- write32 DBCMD_A, DBCMD_MRS2_VAL
-
- /* step 17 */
- write32 DBCMD_A, DBCMD_MRS3_VAL
-
- /* step 18 */
- write32 DBCMD_A, DBCMD_MRS1_VAL
-
- /* step 19 */
- write32 DBCMD_A, DBCMD_MRS0_VAL
-
- /* step 20 */
- write32 DBCMD_A, DBCMD_ZQCL_VAL
-
- write32 DBCMD_A, DBCMD_REF_VAL
- write32 DBCMD_A, DBCMD_REF_VAL
- wait_DBCMD
-
- /* step 21 */
- write32 DBADJ0_A, DBADJ0_D
- write32 DBADJ1_A, DBADJ1_D
- write32 DBADJ2_A, DBADJ2_D
-
- /* step 22 */
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D
- write32 DBRFCNF2_A, DBRFCNF2_D
-
- /* step 23 */
- write32 DBCALCNF_A, DBCALCNF_D
-
- /* step 24 */
- write32 DBRFEN_A, DBRFEN_D
- write32 DBCMD_A, DBCMD_SRXT_VAL
-
- /* step 25 */
- write32 DBACEN_A, DBACEN_D
-
- /* step 26 */
- wait_DBCMD
-
-#if defined(CONFIG_SH7757LCR_DDR_ECC)
- /* enable DDR-ECC */
- write32 ECD_ECDEN_A, ECD_ECDEN_D
- write32 ECD_INTSR_A, ECD_INTSR_D
- write32 ECD_SPACER_A, ECD_SPACER_D
- write32 ECD_MCR_A, ECD_MCR_D
-#endif
- bra exit_ddr
- nop
-
- .align 4
-
-EXPEVT_A: .long 0xff000024
-EXPEVT_POWER_ON_RESET: .long 0x00000000
-
-/*------- DDR3IF -------*/
-DBCMD_A: .long 0xfe800018
-DBKIND_A: .long 0xfe800020
-DBCONF_A: .long 0xfe800024
-DBTR0_A: .long 0xfe800040
-DBTR1_A: .long 0xfe800044
-DBTR2_A: .long 0xfe800048
-DBTR3_A: .long 0xfe800050
-DBTR4_A: .long 0xfe800054
-DBTR5_A: .long 0xfe800058
-DBTR6_A: .long 0xfe80005c
-DBTR7_A: .long 0xfe800060
-DBTR8_A: .long 0xfe800064
-DBTR9_A: .long 0xfe800068
-DBTR10_A: .long 0xfe80006c
-DBTR11_A: .long 0xfe800070
-DBTR12_A: .long 0xfe800074
-DBTR13_A: .long 0xfe800078
-DBTR14_A: .long 0xfe80007c
-DBTR15_A: .long 0xfe800080
-DBTR16_A: .long 0xfe800084
-DBTR17_A: .long 0xfe800088
-DBTR18_A: .long 0xfe80008c
-DBTR19_A: .long 0xfe800090
-DBRNK0_A: .long 0xfe800100
-DBPDCNT0_A: .long 0xfe800200
-DBPDCNT1_A: .long 0xfe800204
-DBPDCNT2_A: .long 0xfe800208
-DBPDCNT3_A: .long 0xfe80020c
-DBPDLCK_A: .long 0xfe800280
-DBPDRGA_A: .long 0xfe800290
-DBPDRGD_A: .long 0xfe8002a0
-DBADJ0_A: .long 0xfe8000c0
-DBADJ1_A: .long 0xfe8000c4
-DBADJ2_A: .long 0xfe8000c8
-DBRFCNF0_A: .long 0xfe8000e0
-DBRFCNF1_A: .long 0xfe8000e4
-DBRFCNF2_A: .long 0xfe8000e8
-DBCALCNF_A: .long 0xfe8000f4
-DBRFEN_A: .long 0xfe800014
-DBACEN_A: .long 0xfe800010
-DBWAIT_A: .long 0xfe80001c
-
-WAIT_OSC_TIME: .long 6000
-WAIT_30US: .long 13333
-
-DBCMD_RSTL_VAL: .long 0x20000000
-DBCMD_PDEN_VAL: .long 0x1000d73c
-DBCMD_WAIT_VAL: .long 0x0000d73c
-DBCMD_RSTH_VAL: .long 0x2100d73c
-DBCMD_PDXT_VAL: .long 0x110000c8
-DBCMD_MRS0_VAL: .long 0x28000930
-DBCMD_MRS1_VAL: .long 0x29000004
-DBCMD_MRS2_VAL: .long 0x2a000008
-DBCMD_MRS3_VAL: .long 0x2b000000
-DBCMD_ZQCL_VAL: .long 0x03000200
-DBCMD_REF_VAL: .long 0x0c000000
-DBCMD_SRXT_VAL: .long 0x19000000
-DBKIND_D: .long 0x00000007
-DBCONF_D: .long 0x0f030a01
-DBTR0_D: .long 0x00000007
-DBTR1_D: .long 0x00000006
-DBTR2_D: .long 0x00000000
-DBTR3_D: .long 0x00000007
-DBTR4_D: .long 0x00070007
-DBTR5_D: .long 0x0000001b
-DBTR6_D: .long 0x00000014
-DBTR7_D: .long 0x00000005
-DBTR8_D: .long 0x00000015
-DBTR9_D: .long 0x00000006
-DBTR10_D: .long 0x00000008
-DBTR11_D: .long 0x00000007
-DBTR12_D: .long 0x0000000e
-DBTR13_D: .long 0x00000056
-DBTR14_D: .long 0x00000006
-DBTR15_D: .long 0x00000004
-DBTR16_D: .long 0x00150002
-DBTR17_D: .long 0x000c0017
-DBTR18_D: .long 0x00000200
-DBTR19_D: .long 0x00000040
-DBRNK0_D: .long 0x00000001
-DBPDCNT0_D: .long 0x00000001
-DBPDCNT1_D: .long 0x00000001
-DBPDCNT2_D: .long 0x00000000
-DBPDCNT3_D: .long 0x00004010
-DBPDLCK_D: .long 0x0000a55a
-DBPDRGA_D: .long 0x00000028
-DBPDRGD_D: .long 0x00017100
-
-DBADJ0_D: .long 0x00000000
-DBADJ1_D: .long 0x00000000
-DBADJ2_D: .long 0x18061806
-DBRFCNF0_D: .long 0x000001ff
-DBRFCNF1_D: .long 0x08001000
-DBRFCNF2_D: .long 0x00000000
-DBCALCNF_D: .long 0x0000ffff
-DBRFEN_D: .long 0x00000001
-DBACEN_D: .long 0x00000001
-
-/*------- DDR-ECC -------*/
-ECD_ECDEN_A: .long 0xffc1012c
-ECD_ECDEN_D: .long 0x00000001
-ECD_INTSR_A: .long 0xfe900024
-ECD_INTSR_D: .long 0xffffffff
-ECD_SPACER_A: .long 0xfe900018
-ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
-ECD_MCR_A: .long 0xfe900010
-ECD_MCR_D: .long 0x00000001
-
- .align 2
-exit_ddr:
-
-#if defined(CONFIG_SH_32BIT)
- /*------- set PMB -------*/
- write32 PASCR_A, PASCR_29BIT_D
- write32 MMUCR_A, MMUCR_D
-
- /*****************************************************************
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x00000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- */
- write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
- write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
- write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
- write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
- write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
- write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
-
- write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
-
- write32 PASCR_A, PASCR_INIT
- mov.l DUMMY_ADDR, r0
- icbi @r0
-#endif /* if defined(CONFIG_SH_32BIT) */
-
-exit_pmb:
- /* CPU is running on ILRAM? */
- mov r14, r0
- tst #1, r0
- bt 1f
-
- mov.l _bss_start, r15
- mov.l _spiboot_main, r0
-100: bsrf r0
- nop
-
- .align 2
-_spiboot_main: .long (spiboot_main - (100b + 4))
-_bss_start: .long bss_start
-
-1:
-
- write32 CCR_A, CCR_D
-
- rts
- nop
-
- .align 4
-
-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
-PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
-PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
-PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
-PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
-PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
-PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
-PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
-PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
-PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
-PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
-PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
-PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
-PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
-PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
-PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
-
-PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
-PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
-PMB_ADDR_NOT_USE_D: .long 0x00000000
-
-PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
-PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
-PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
-
-/* ppn ub v s1 s0 c wt */
-PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
-
-PASCR_A: .long 0xff000070
-DUMMY_ADDR: .long 0xa0000000
-PASCR_29BIT_D: .long 0x00000000
-PASCR_INIT: .long 0x80000080
-MMUCR_A: .long 0xff000010
-MMUCR_D: .long 0x00000004 /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */
-
-CCR_A: .long CCR
-CCR_D: .long CCR_CACHE_INIT
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <flash.h>
-#include <init.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmc.h>
-#include <spi.h>
-#include <spi_flash.h>
-
-int checkboard(void)
-{
- puts("BOARD: R0P7757LC0030RL board\n");
-
- return 0;
-}
-
-static void init_gctrl(void)
-{
- struct gctrl_regs *gctrl = GCTRL_BASE;
- unsigned long graofst;
-
- graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
- writel(graofst | 0x20000f00, &gctrl->gracr3);
-}
-
-static int init_pcie_bridge_from_spi(void *buf, size_t size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
- unsigned long pcie_addr;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe error.\n", __func__);
- return 1;
- }
-
- if (is_sh7757_b0())
- pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
- else
- pcie_addr = SH7757LCR_PCIEBRG_ADDR;
-
- ret = spi_flash_read(spi, pcie_addr, size, buf);
- if (ret) {
- printf("%s: spi_flash read error.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- return 0;
-#else
- printf("No SPI support so no PCIe support\n");
- return 1;
-#endif
-}
-
-static void init_pcie_bridge(void)
-{
- struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
- struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
- int i;
- unsigned char *data;
- unsigned short tmp;
- unsigned long pcie_size;
-
- if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
- return;
-
- if (is_sh7757_b0())
- pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
- else
- pcie_size = SH7757LCR_PCIEBRG_SIZE;
-
- data = malloc(pcie_size);
- if (!data) {
- printf("%s: malloc error.\n", __func__);
- return;
- }
- if (init_pcie_bridge_from_spi(data, pcie_size)) {
- free(data);
- return;
- }
-
- if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
- data[3] == 0xff) {
- free(data);
- printf("%s: skipped initialization\n", __func__);
- return;
- }
-
- writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
- writew(0x0000, &pciebrg->cp_ctrl);
- writew(0x0000, &pciebrg->cp_addr);
-
- for (i = 0; i < pcie_size; i += 2) {
- tmp = (data[i] << 8) | data[i + 1];
- writew(tmp, &pciebrg->cp_data);
- }
-
- writew(0xa500, &pciebrg->ctrl_h8s); /* start */
- if (!is_sh7757_b0())
- writel(0x00000001, &pcie_setup->pbictl3);
-
- free(data);
-}
-
-static void init_usb_phy(void)
-{
- struct usb_common_regs *common0 = USB0_COMMON_BASE;
- struct usb_common_regs *common1 = USB1_COMMON_BASE;
- struct usb0_phy_regs *phy = USB0_PHY_BASE;
- struct usb1_port_regs *port = USB1_PORT_BASE;
- struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
-
- writew(0x0100, &phy->reset); /* set reset */
- /* port0 = USB0, port1 = USB1 */
- writew(0x0002, &phy->portsel);
- writel(0x0001, &port->port1sel); /* port1 = Host */
- writew(0x0111, &phy->reset); /* clear reset */
-
- writew(0x4000, &common0->suspmode);
- writew(0x4000, &common1->suspmode);
-
-#if defined(__LITTLE_ENDIAN)
- writel(0x00000000, &align->ehcidatac);
- writel(0x00000000, &align->ohcidatac);
-#endif
-}
-
-static void set_mac_to_sh_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = ETHER0_MAC_BASE;
- else
- ether = ETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = GETHER0_MAC_BASE;
- else
- ether = GETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-/*****************************************************************
- * This PMB must be set on this timing. The lowlevel_init is run on
- * Area 0(phys 0x00000000), so we have to map it.
- *
- * The new PMB table is following:
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x40000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 2 0xb0000000 0x50000000 1 128M 0 1
- * 3 0xb8000000 0x58000000 1 128M 0 1
- * 4 0x80000000 0x40000000 1 128M 1 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- * 6 0x90000000 0x50000000 1 128M 1 1
- * 7 0x98000000 0x58000000 1 128M 1 1
- */
-static void set_pmb_on_board_init(void)
-{
- struct mmu_regs *mmu = MMU_BASE;
-
- /* clear ITLB */
- writel(0x00000004, &mmu->mmucr);
-
- /* delete PMB for SPIBOOT */
- writel(0, PMB_ADDR_BASE(0));
- writel(0, PMB_DATA_BASE(0));
-
- /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
- /* ppn ub v s1 s0 c wt */
- writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
- writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
- writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
- writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
- writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
- writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
- writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
- writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
- writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
- writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
- writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
- writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
-}
-
-int board_init(void)
-{
- struct gether_control_regs *gether = GETHER_CONTROL_BASE;
-
- set_pmb_on_board_init();
-
- /* enable RMII's MDIO (disable GRMII's MDIO) */
- writel(0x00030000, &gether->gbecont);
-
- init_gctrl();
- init_usb_phy();
-
- return 0;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- return mmcif_mmc_init();
-}
-
-static int get_sh_eth_mac_raw(unsigned char *buf, int size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (spi == NULL) {
- printf("%s: spi_flash probe error.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
- if (ret) {
- printf("%s: spi_flash read error.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-#endif
-
- return 0;
-}
-
-static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
-{
- memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
- SH7757LCR_ETHERNET_MAC_SIZE);
- mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
-
- return 0;
-}
-
-static void init_ethernet_mac(void)
-{
- char mac_string[64];
- char env_string[64];
- int i;
- unsigned char *buf;
-
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc error.\n", __func__);
- return;
- }
- get_sh_eth_mac_raw(buf, 256);
-
- /* Fast Ethernet */
- for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i == 0)
- env_set("ethaddr", mac_string);
- else {
- sprintf(env_string, "eth%daddr", i);
- env_set(env_string, mac_string);
- }
-
- set_mac_to_sh_eth_register(i, mac_string);
- }
-
- /* Gigabit Ethernet */
- for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
- sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
- env_set(env_string, mac_string);
-
- set_mac_to_sh_giga_eth_register(i, mac_string);
- }
-
- free(buf);
-}
-
-static void init_pcie(void)
-{
- struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
- struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
-
- writel(0x00000ff2, &pcie_setup->ladmsk0);
- writel(0x00000001, &pcie_setup->barmap);
- writel(0xffcaa000, &pcie_setup->lad0);
- writel(0x00030000, &pcie_sysbus->endictl0);
- writel(0x00000003, &pcie_sysbus->endictl1);
- writel(0x00000004, &pcie_setup->pbictl2);
-}
-
-static void finish_spiboot(void)
-{
- struct gctrl_regs *gctrl = GCTRL_BASE;
- /*
- * SH7757 B0 does not use LBSC.
- * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
- * This setting is not cleared by manual reset, So we have to set it
- * to 0.
- */
- writel(0x00000000, &gctrl->spibootcan);
-}
-
-int board_late_init(void)
-{
- init_ethernet_mac();
- init_pcie_bridge();
- init_pcie();
- finish_spiboot();
-
- return 0;
-}
-
-int do_sh_g200(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- struct gctrl_regs *gctrl = GCTRL_BASE;
- unsigned long graofst;
-
- writel(0xfedcba98, &gctrl->wprotect);
- graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
- writel(graofst | 0xa0000f00, &gctrl->gracr3);
-
- return 0;
-}
-
-U_BOOT_CMD(
- sh_g200, 1, 1, do_sh_g200,
- "enable sh-g200",
- "enable SH-G200 bus (disable PCIe-G200)"
-);
-
-#ifdef CONFIG_DEPRECATED
-int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int i, ret;
- char mac_string[256];
- struct spi_flash *spi;
- unsigned char *buf;
-
- if (argc != 5) {
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc error.\n", __func__);
- return 1;
- }
-
- get_sh_eth_mac_raw(buf, 256);
-
- /* print current MAC address */
- for (i = 0; i < 4; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i < 2)
- printf(" ETHERC ch%d = %s\n", i, mac_string);
- else
- printf("GETHERC ch%d = %s\n", i-2, mac_string);
- }
- free(buf);
- return 0;
- }
-
- /* new setting */
- memset(mac_string, 0xff, sizeof(mac_string));
- sprintf(mac_string, "%s\t%s\t%s\t%s",
- argv[1], argv[2], argv[3], argv[4]);
-
- /* write MAC data to SPI rom */
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe error.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
- SH7757LCR_SPI_SECTOR_SIZE);
- if (ret) {
- printf("%s: spi_flash erase error.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
- sizeof(mac_string), mac_string);
- if (ret) {
- printf("%s: spi_flash write error.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- puts("The writing of the MAC address to SPI ROM was completed.\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- write_mac, 5, 1, do_write_mac,
- "write MAC address for ETHERC/GETHERC",
- "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
-);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- *
- * This file is subject to the terms and conditions of the GNU Lesser
- * General Public License. See the file "COPYING.LIB" in the main
- * directory of this archive for more details.
- */
-
-#include <common.h>
-
-#define CONFIG_RAM_BOOT_PHYS 0x4ef80000
-#if defined(CONFIG_SH7757_OFFSET_SPI)
-#define CONFIG_SPI_ADDR 0x00010000
-#else
-#define CONFIG_SPI_ADDR 0x00000000
-#endif
-#define CONFIG_SPI_LENGTH 0x00030000
-#define CONFIG_RAM_BOOT 0x8ef80000
-
-#define SPIWDMADR 0xFE001018
-#define SPIWDMCNTR 0xFE001020
-#define SPIDMCOR 0xFE001028
-#define SPIDMINTSR 0xFE001188
-#define SPIDMINTMR 0xFE001190
-
-#define SPIDMINTSR_DMEND 0x00000004
-
-#define TBR 0xFE002000
-#define RBR 0xFE002000
-
-#define CR1 0xFE002008
-#define CR2 0xFE002010
-#define CR3 0xFE002018
-#define CR4 0xFE002020
-
-/* CR1 */
-#define SPI_TBE 0x80
-#define SPI_TBF 0x40
-#define SPI_RBE 0x20
-#define SPI_RBF 0x10
-#define SPI_PFONRD 0x08
-#define SPI_SSDB 0x04
-#define SPI_SSD 0x02
-#define SPI_SSA 0x01
-
-/* CR2 */
-#define SPI_RSTF 0x80
-#define SPI_LOOPBK 0x40
-#define SPI_CPOL 0x20
-#define SPI_CPHA 0x10
-#define SPI_L1M0 0x08
-
-/* CR4 */
-#define SPI_TBEI 0x80
-#define SPI_TBFI 0x40
-#define SPI_RBEI 0x20
-#define SPI_RBFI 0x10
-#define SPI_SSS 0x01
-
-#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
-#define spi_read(addr) (*(volatile unsigned long *)(addr))
-
-/* M25P80 */
-#define M25_READ 0x03
-
-#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
-static void __uses_spiboot2 spi_reset(void)
-{
- spi_write(0xfe, CR1);
-
- spi_write(0, SPIDMCOR);
- spi_write(0x00, CR1);
-
- spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
- spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
-}
-
-static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
- unsigned long len)
-{
- spi_write(M25_READ, TBR);
- spi_write((addr >> 16) & 0xFF, TBR);
- spi_write((addr >> 8) & 0xFF, TBR);
- spi_write(addr & 0xFF, TBR);
-
- spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
- spi_write((unsigned long)buf, SPIWDMADR);
- spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
- spi_write(1, SPIDMCOR);
-
- spi_write(0xff, CR3);
- spi_write(spi_read(CR1) | SPI_SSDB, CR1);
- spi_write(spi_read(CR1) | SPI_SSA, CR1);
-
- while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
- ;
-}
-
-void __uses_spiboot2 spiboot_main(void)
-{
- void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
-
- spi_reset();
- spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
- CONFIG_SPI_LENGTH);
-
- _start();
-}
+++ /dev/null
-if TARGET_SH7763RDP
-
-config SYS_BOARD
- default "sh7763rdp"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7763rdp"
-
-endif
+++ /dev/null
-SH7763RDP BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/sh7763rdp/
-F: include/configs/sh7763rdp.h
-F: configs/sh7763rdp_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2008 Renesas Solutions Corp.
-# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-# Copyright (C) 2007 Kenati Technologies, Inc.
-#
-# board/sh7763rdp/Makefile
-
-obj-y := sh7763rdp.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2007 Kenati Technologies, Inc.
- *
- * board/sh7763rdp/lowlevel_init.S
- */
-
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
-
- write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
-
- write32 WDTBST_A, WDTBST_D /*
- * 0xFFCC0008
- * Watchdog Base Stop Time Register
- */
-
- write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
- /* Instruction Cache Invalidate */
-
- write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
- /* TI == TLB Invalidate bit */
-
- write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
-
- write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
-
- write32 RAMCR_A, RAMCR_D
-
- mov.l MMSELR_A, r1
- mov.l MMSELR_D, r0
- synco
- mov.l r0, @r1
-
- mov.l @r1, r2 /* execute two reads after setting MMSELR */
- mov.l @r1, r2
- synco
-
- /* issue memory read */
- mov.l DDRSD_START_A, r1 /* memory address to read*/
- mov.l @r1, r0
- synco
-
- write32 MIM8_A, MIM8_D
-
- write32 MIMC_A, MIMC_D1
-
- write32 STRC_A, STRC_D
-
- write32 SDR4_A, SDR4_D
-
- write32 MIMC_A, MIMC_D2
-
- nop
- nop
- nop
-
- write32 SCR4_A, SCR4_D3
-
- write32 SCR4_A, SCR4_D2
-
- write32 SDMR02000_A, SDMR02000_D
-
- write32 SDMR00B08_A, SDMR00B08_D
-
- write32 SCR4_A, SCR4_D2
-
- write32 SCR4_A, SCR4_D4
-
- nop
- nop
- nop
- nop
-
- write32 SCR4_A, SCR4_D4
-
- nop
- nop
- nop
- nop
-
- write32 SDMR00308_A, SDMR00308_D
-
- write32 MIMC_A, MIMC_D3
-
- mov.l SCR4_A, r1
- mov.l SCR4_D1, r0
- mov.l DELAY60_D, r3
-
-delay_loop_60:
- mov.l r0, @r1
- dt r3
- bf delay_loop_60
- nop
-
- write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
-
-bsc_init:
- write32 BCR_A, BCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS1BCR_A, CS1BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5BCR_A, CS5BCR_D
-
- write32 CS6BCR_A, CS6BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS1WCR_A, CS1WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5WCR_A, CS5WCR_D
-
- write32 CS6WCR_A, CS6WCR_D
-
- write32 CS5PCR_A, CS5PCR_D
-
- write32 CS6PCR_A, CS6PCR_D
-
- mov.l DELAY200_D, r3
-
-delay_loop_200:
- dt r3
- bf delay_loop_200
- nop
-
- write16 PSEL0_A, PSEL0_D
-
- write16 PSEL1_A, PSEL1_D
-
- write32 ICR0_A, ICR0_D
-
- stc sr, r0 /* BL bit off(init=ON) */
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
- nop
-
- .align 2
-
-DELAY60_D: .long 60
-DELAY200_D: .long 17800
-
-CCR_A: .long 0xFF00001C
-MMUCR_A: .long 0xFF000010
-RAMCR_A: .long 0xFF000074
-
-/* Low power mode control */
-MSTPCR0_A: .long 0xFFC80030
-MSTPCR1_A: .long 0xFFC80038
-
-/* RWBT */
-WDTST_A: .long 0xFFCC0000
-WDTCSR_A: .long 0xFFCC0004
-WDTBST_A: .long 0xFFCC0008
-
-/* BSC */
-MMSELR_A: .long 0xFE600020
-BCR_A: .long 0xFF801000
-CS0BCR_A: .long 0xFF802000
-CS1BCR_A: .long 0xFF802010
-CS2BCR_A: .long 0xFF802020
-CS4BCR_A: .long 0xFF802040
-CS5BCR_A: .long 0xFF802050
-CS6BCR_A: .long 0xFF802060
-CS0WCR_A: .long 0xFF802008
-CS1WCR_A: .long 0xFF802018
-CS2WCR_A: .long 0xFF802028
-CS4WCR_A: .long 0xFF802048
-CS5WCR_A: .long 0xFF802058
-CS6WCR_A: .long 0xFF802068
-CS5PCR_A: .long 0xFF802070
-CS6PCR_A: .long 0xFF802080
-DDRSD_START_A: .long 0xAC000000
-
-/* INTC */
-ICR0_A: .long 0xFFD00000
-
-/* DDR I/F */
-MIM8_A: .long 0xFE800008
-MIMC_A: .long 0xFE80000C
-SCR4_A: .long 0xFE800014
-STRC_A: .long 0xFE80001C
-SDR4_A: .long 0xFE800034
-SDMR00308_A: .long 0xFE900308
-SDMR00B08_A: .long 0xFE900B08
-SDMR02000_A: .long 0xFE902000
-
-/* GPIO */
-PSEL0_A: .long 0xFFEF0070
-PSEL1_A: .long 0xFFEF0072
-
-CCR_CACHE_ICI_D:.long 0x00000800
-CCR_CACHE_D_2: .long 0x00000103
-MMU_CONTROL_TI_D:.long 0x00000004
-RAMCR_D: .long 0x00000200
-MSTPCR0_D: .long 0x00000000
-MSTPCR1_D: .long 0x00000000
-
-MMSELR_D: .long 0xa5a50000
-BCR_D: .long 0x00000000
-CS0BCR_D: .long 0x77777770
-CS1BCR_D: .long 0x77777670
-CS2BCR_D: .long 0x77777670
-CS4BCR_D: .long 0x77777670
-CS5BCR_D: .long 0x77777670
-CS6BCR_D: .long 0x77777670
-CS0WCR_D: .long 0x7777770F
-CS1WCR_D: .long 0x22000002
-CS2WCR_D: .long 0x7777770F
-CS4WCR_D: .long 0x7777770F
-CS5WCR_D: .long 0x7777770F
-CS6WCR_D: .long 0x7777770F
-CS5PCR_D: .long 0x77000000
-CS6PCR_D: .long 0x77000000
-ICR0_D: .long 0x00E00000
-MIM8_D: .long 0x00000000
-MIMC_D1: .long 0x01d10008
-MIMC_D2: .long 0x01d10009
-MIMC_D3: .long 0x01d10209
-SCR4_D1: .long 0x00000001
-SCR4_D2: .long 0x00000002
-SCR4_D3: .long 0x00000003
-SCR4_D4: .long 0x00000004
-STRC_D: .long 0x000f3980
-SDR4_D: .long 0x00000300
-SDMR00308_D: .long 0x00000000
-SDMR00B08_D: .long 0x00000000
-SDMR02000_D: .long 0x00000000
-PSEL0_D: .word 0x00000001
-PSEL1_D: .word 0x00000244
-SR_MASK_D: .long 0xEFFFFF0F
-WDTST_D: .long 0x5A000FFF
-WDTCSR_D: .long 0xA5000000
-WDTBST_D: .long 0x55000000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2007 Kenati Technologies, Inc.
- *
- * board/sh7763rdp/sh7763rdp.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-#define CPU_CMDREG 0xB1000006
-#define PDCR 0xffef0006
-#define PECR 0xffef0008
-#define PFCR 0xffef000a
-#define PGCR 0xffef000c
-#define PHCR 0xffef000e
-#define PJCR 0xffef0012
-#define PKCR 0xffef0014
-#define PLCR 0xffef0016
-#define PMCR 0xffef0018
-#define PSEL1 0xffef0072
-#define PSEL2 0xffef0074
-#define PSEL3 0xffef0076
-
-int checkboard(void)
-{
- puts("BOARD: Renesas SH7763 RDP\n");
- return 0;
-}
-
-int board_init(void)
-{
- vu_short dat;
-
- /* Enable mode */
- writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
-
- /* GPIO Setting (eth1) */
- dat = inw(PSEL1);
- writew(((dat & ~0xff00) | 0x2400), PSEL1);
- writew(0, PFCR);
- writew(0, PGCR);
- writew(0, PHCR);
-
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
#include <init.h>
#include <malloc.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <common.h>
#include <adc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <init.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rv1108.h>
#include <common.h>
#include <init.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <init.h>
#include <log.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/dwmmc.h>
#include <spi.h>
#include <tmu.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/board.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <env.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <i2c.h>
#include <env.h>
#include <lcd.h>
#include <libtizen.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <samsung/misc.h>
#include <errno.h>
#ifdef CONFIG_LCD_MENU
static int power_key_pressed(u32 reg)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
struct pmic *pmic;
u32 status;
u32 mask;
#include <common.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/arch/mmc.h>
#include <dm.h>
#include <asm/arch/power.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/arch/cpu.h>
#include <dm.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/sromc.h>
#include <init.h>
#include <log.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <netdev.h>
return 0;
}
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
static void trats_low_power_mode(void)
{
struct exynos4_clock *clk =
int exynos_power_init(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
int chrg, ret;
struct power_battery *pb;
struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
int g_dnl_board_usb_cable_connected(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
struct pmic *muic = pmic_get("MAX8997_MUIC");
if (!muic)
return 0;
int lcd_power(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
if (!p)
int mipi_power(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
if (!p)
int exynos_power_init(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
int chrg;
struct power_battery *pb;
struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
int ret = 0;
unsigned int val;
struct pmic *p, *p_pmic, *p_muic;
int g_dnl_board_usb_cable_connected(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
struct pmic *muic = pmic_get("MAX77693_MUIC");
if (!muic)
return 0;
#ifdef CONFIG_LCD
int mipi_power(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
struct pmic *p = pmic_get("MAX77686_PMIC");
/* LDO8 VMIPI_1.0V_AP */
void exynos_lcd_power_on(void)
{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
struct pmic *p = pmic_get("MAX77686_PMIC");
/* LCD_2.2V_EN: GPC0[1] */
#include <log.h>
#include <spi.h>
#include <lcd.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/adc.h>
#include <init.h>
#include <led.h>
#include <os.h>
+#include <asm/global_data.h>
#include <asm/test.h>
#include <asm/u-boot-sandbox.h>
#include <errno.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd_sdram.h>
#include <init.h>
#include <log.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <common.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <init.h>
#include <spl.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <dm.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <env.h>
#include <flash.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <init.h>
#include <pci.h>
#include <uuid.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <i2c.h>
-#include <mb862xx.h>
#include <video_fb.h>
#include "upm_table.h"
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
-extern GraphicDevice mb862xx;
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
val[i++] = gd->bd->bi_flashstart;
val[i++] = gd->bd->bi_flashsize;
-#if defined(CONFIG_VIDEO_MB862xx)
- if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
- /* Fixup LIME mapping */
- val[i++] = 2; /* chip select number */
- val[i++] = 0; /* always 0 */
- val[i++] = CONFIG_SYS_LIME_BASE;
- val[i++] = CONFIG_SYS_LIME_SIZE;
- }
-#endif
-
/* Fixup FPGA mapping */
val[i++] = 3; /* chip select number */
val[i++] = 0; /* always 0 */
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <net.h>
#include <status_led.h>
#include <asm/arch/reset_manager.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
*/
#include <common.h>
+#include <compiler.h>
#include <tlv_eeprom.h>
#include "tlv_data.h"
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
#include <env.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <tee.h>
#include <asm/arch/stm32prog.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#define MTDPARTS_LEN 256
#define MTDIDS_LEN 128
#include <cpu_func.h>
#include <init.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/usb/otg.h>
#include <dwc3-sti-glue.h>
#include <dwc3-uboot.h>
#include <env.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <env.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <env.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <splash.h>
#include <st_logo_data.h>
#include <video.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <syscon.h>
#include <usb.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/platform_data/serial_pl01x.h>
*/
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/mmc.h>
#include <asm/arch/prcm.h>
#include <asm/arch/spl.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <u-boot/crc.h>
#ifndef CONFIG_ARM64
}
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
/*
* Temporary workaround for enabling I2C clocks until proper sunxi DM
* clk, reset and pinctrl drivers land.
#include <init.h>
#include <malloc.h>
#include <asm/arcregs.h>
+#include <asm/global_data.h>
#include "axs10x.h"
#include <asm/cache.h>
#include <dwmmc.h>
#include <init.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <asm/arcregs.h>
#include <irq_func.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/printk.h>
#include <init.h>
#include <malloc.h>
#include <dwmmc.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <fdtdec.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <dm.h>
#include <common.h>
#include <init.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/immap.h>
#include <mmc.h>
#include <cpu_func.h>
#include <env.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
* Author: Fabio Estevam <festevam@gmail.com>
*/
+#include <common.h>
#include <env.h>
#include <init.h>
#include <net.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/mach-imx/video.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/sizes.h>
-#include <common.h>
#include <miiphy.h>
#include <netdev.h>
#include <phy.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <malloc.h>
#include <netdev.h>
#include <twl4030.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mem.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <init.h>
#include <log.h>
#include <net.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <common.h>
#include <command.h>
#include <console.h>
+#include <dm.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
#if !defined(CONFIG_SPL_BUILD)
#include <bootcount.h>
#endif
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
}
+#define PCIE_LNK_CTRL_STAT_2_OFF 0x0090
+#define PCIE_LNK_CTRL_STAT_2_DEEM_BIT BIT(6)
+
+static void pcie_set_deemphasis(u32 base)
+{
+ u32 reg;
+
+ reg = readl((void *)base + PCIE_LNK_CTRL_STAT_2_OFF);
+ reg |= PCIE_LNK_CTRL_STAT_2_DEEM_BIT;
+ writel(reg, (void *)base + PCIE_LNK_CTRL_STAT_2_OFF);
+}
+
int board_early_init_f(void)
{
/* Configure MPP */
writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+ /*
+ * Set deephasis bit in the PCIe configuration of both PCIe ports
+ * used on this board.
+ *
+ * This needs to be done very early, even before the SERDES setup
+ * code is run. This way, the first link will already be established
+ * with this setup. Testing has shown, that this results in a more
+ * stable PCIe link with better signal quality.
+ */
+ pcie_set_deemphasis(MVEBU_REG_PCIE_BASE); /* Port 0 */
+ pcie_set_deemphasis(MVEBU_REG_PCIE_BASE + 0x2000); /* Port 2 */
+
return 0;
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
-int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width)
{
- pci_dev_t bdf;
+ struct udevice *dev;
u16 ven_id, dev_id;
+ u16 lnksta;
+ int ret;
+ int pos;
- if (argc != 3)
- return cmd_usage(cmdtp);
+ /*
+ * Check if the PCIe device is detected (sometimes its not available
+ * on the PCIe bus)
+ */
+ ret = dm_pci_bus_find_bdf(bdf, &dev);
+ if (ret)
+ return -ENODEV;
+
+ /* PCIe device found */
+ dm_pci_read_config16(dev, PCI_VENDOR_ID, &ven_id);
+ dm_pci_read_config16(dev, PCI_DEVICE_ID, &dev_id);
+ printf("Detected PCIe device: VendorID 0x%04x DeviceId 0x%04x @ BDF %d.%d.%d\n",
+ ven_id, dev_id, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+
+ /* Now read EXP_LNKSTA register */
+ pos = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
+ dm_pci_read_config16(dev, pos + PCI_EXP_LNKSTA, &lnksta);
+ *speed = lnksta & PCI_EXP_LNKSTA_CLS;
+ *width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
+
+ return 0;
+}
- ven_id = simple_strtoul(argv[1], NULL, 16);
- dev_id = simple_strtoul(argv[2], NULL, 16);
+/*
+ * U-Boot cmd to test for the presence of the directly connected PCIe devices
+ * the theadorable board. This cmd can be used by U-Boot scripts for automated
+ * testing, if the PCIe setup is correct. Meaning, that all PCIe devices are
+ * correctly detected and the link speed and width is corrent.
+ *
+ * Here a short script that may be used for an automated test. It results in
+ * an endless reboot loop, if the PCIe devices are detected correctly. If at
+ * any time a problem is detected (PCIe device not available or link is
+ * incorrect), then booting will halt. So just use this "bootcmd" and let the
+ * board run over a longer time (e.g. one night) and if the board still reboots
+ * after this time, then everything is okay.
+ *
+ * bootcmd=echo bootcount=$bootcount; pcie ;if test $? -eq 0;
+ * then echo PCIe status okay, resetting...; reset; else;
+ * echo PCIe status NOT okay, hanging (bootcount=$bootcount); fi;
+ */
+int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ pci_dev_t bdf;
+ int speed;
+ int width;
+ int ret;
- printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
- ven_id, dev_id);
+ if (argc != 1)
+ return cmd_usage(cmdtp);
/*
- * Check if the PCIe device is detected (somtimes its not available
+ * Check if the PCIe device is detected (sometimes its not available
* on the PCIe bus)
*/
- bdf = pci_find_device(ven_id, dev_id, 0);
- if (bdf == -1) {
+
+ /* Check for PCIe device on PCIe port/bus 0 */
+ bdf = PCI_BDF(0, 1, 0);
+ ret = pcie_get_link_speed_width(bdf, &speed, &width);
+ if (ret) {
/* PCIe device not found! */
- printf("Failed to find PCIe device\n");
- } else {
- /* PCIe device found! */
- printf("PCIe device found, resetting board...\n");
+ printf("Failed to find PCIe device @ BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return CMD_RET_FAILURE;
+ }
- /* default handling: SOFT reset */
- do_reset(NULL, 0, 0, NULL);
+ printf("Established speed=%d width=%d\n", speed, width);
+ if ((speed != 1 || width != 1)) {
+ printf("Detected incorrect speed/width!!!\n");
+ return CMD_RET_FAILURE;
}
- return 0;
+ /* Check for PCIe device on PCIe port/bus 1 */
+ bdf = PCI_BDF(1, 1, 0);
+ ret = pcie_get_link_speed_width(bdf, &speed, &width);
+ if (ret) {
+ /* PCIe device not found! */
+ printf("Failed to find PCIe device @ BDF %d.%d.%d\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Established speed=%d width=%d\n", speed, width);
+ if ((speed != 2 || width != 4)) {
+ printf("Detected incorrect speed/width!!!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
- pcie, 3, 0, do_pcie_test,
- "Test for presence of a PCIe device",
- "<VendorID> <DeviceID>"
+ pcie, 1, 0, do_pcie_test,
+ "Test for presence of a PCIe devices with correct link",
+ ""
);
#endif
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
void do_board_detect(void)
{
enable_i2c0_pin_mux();
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
return;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
if (i2c_probe(TPS65217_CHIP_PM))
return;
#else
* 1.10V. For MPU voltage we need to switch based on
* the frequency we are running at.
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
return;
#else
if (first_time) {
enable_i2c0_pin_mux();
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
{
unsigned short val;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
if (i2c_probe(I2C_CPLD_ADDR))
return PROFILE_NONE;
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mem.h>
#include <common.h>
#include <eeprom.h>
#include <image.h>
+#include <asm/global_data.h>
#include <dm/uclass.h>
#include <env.h>
#include <fdt_support.h>
{
int mpu_vdd, ddr_volt;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
if (i2c_probe(TPS65218_CHIP_PM))
return;
#else
{
int mpu_vdd;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
if (i2c_probe(TPS62362_I2C_ADDR))
return;
#else
if (first_time) {
enable_i2c0_pin_mux();
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
int power_init_board(void)
{
int rc;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
struct pmic *p = NULL;
#endif
if (board_is_idk()) {
rc = power_tps62362_init(0);
if (rc)
goto done;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
p = pmic_get("TPS62362");
if (!p || pmic_probe(p))
goto done;
rc = power_tps65218_init(0);
if (rc)
goto done;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
p = pmic_get("TPS65218_PMIC");
if (!p || pmic_probe(p))
goto done;
#include <serial.h>
#include <usb.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/emif.h>
#include <net.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/omap_common.h>
#include <status_led.h>
#endif
#include <twl4030.h>
+#include <asm/global_data.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include "board_detect.h"
-#if !defined(CONFIG_DM_I2C)
+#if !CONFIG_IS_ENABLED(DM_I2C)
/**
* ti_i2c_eeprom_init - Initialize an i2c bus and probe for a device
* @i2c_bus: i2c bus number to initialize
u32 hdr_read;
int rc;
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
struct udevice *bus;
#include <palmas.h>
#include <sata.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <linux/string.h>
#include <asm/gpio.h>
#include <usb.h>
#include <net.h>
#include <ns16550.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <net.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <spl.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include "board.h"
#include <env.h>
#include <hang.h>
#if defined(CONFIG_DTB_RESELECT)
static int k2g_alt_board_detect(void)
{
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
int rc;
rc = i2c_set_bus_num(1);
#include <serial.h>
#include <tca642x.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <log.h>
#include <net.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <serial.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
+#include <asm/global_data.h>
#include "sdp4430_mux_data.h"
#include <net.h>
#include <spl.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/cpu.h>
#include <asm/arch/emc.h>
#include <asm/arch/wdt.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <malloc.h>
#include <ns16550.h>
#include <twl4030.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <common.h>
#include <cpu_func.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <env.h>
#include <image.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/tegra.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm.h>
*/
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/arch/clock.h>
#include <common.h>
#include <cpu_func.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8-pins.h>
#include <env.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/arch/pxa.h>
#include <asm/arch/regs-mmc.h>
#include <asm/arch/regs-uart.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/platdata.h>
#include <dm/platform_data/pxa_mmc_gen.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/tegra.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <i2c.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include "tdx-cfg-block.h"
#include "tdx-eeprom.h"
#include <dm.h>
#include <i2c_eeprom.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <i2c.h>
#include <miiphy.h>
#include <ioports.h>
#include <log.h>
#include <mpc83xx.h>
+#include <asm/global_data.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/arch/sys_proto.h>
#include <env.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <env.h>
#include <env.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <dm.h>
#include <hwconfig.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <common.h>
#include <fdt_support.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <pci.h>
#include <init.h>
#include <net.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#define REV_DETECTION IMX_GPIO_NR(2, 28)
/* Speed defined in Kconfig is only applicable when not using DM_I2C. */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
#define I2C1_SPEED_NON_DM 0
#define I2C2_SPEED_NON_DM 0
#else
static int detect_i2c(struct display_info_t const *dev)
{
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus, *udev;
int rc;
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/iomux-v3.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <errno.h>
#include <malloc.h>
#include <xen.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <asm/mmu.h>
#include <common.h>
#include <env.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <i2c.h>
#include <env.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <fdtdec.h>
#include <linux/sizes.h>
#include <malloc.h>
#include <time.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
#include <wdt.h>
#include <zynqpl.h>
+#include <asm/global_data.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include "../common/board.h"
#include <common.h>
#include <log.h>
#include <part.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <command.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/psu_init_gpl.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <dm/device.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include "nsa310s.h"
#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/acpi_table.h>
+#include <asm/global_data.h>
#include <dm/acpi.h>
DECLARE_GLOBAL_DATA_PTR;
#include <video.h>
#include <vsprintf.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
-void bdinfo_print_num(const char *name, ulong value)
+void bdinfo_print_num_l(const char *name, ulong value)
{
printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value);
}
+void bdinfo_print_num_ll(const char *name, unsigned long long value)
+{
+ printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong), value);
+}
+
static void print_eth(int idx)
{
char name[10], *val;
printf("%-12s= %s\n", name, val);
}
-static void print_phys_addr(const char *name, phys_addr_t value)
-{
- printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong),
- (unsigned long long)value);
-}
-
void bdinfo_print_mhz(const char *name, unsigned long hz)
{
char buf[32];
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
- bdinfo_print_num("DRAM bank", i);
- bdinfo_print_num("-> start", bd->bi_dram[i].start);
- bdinfo_print_num("-> size", bd->bi_dram[i].size);
+ bdinfo_print_num_l("DRAM bank", i);
+ bdinfo_print_num_ll("-> start", bd->bi_dram[i].start);
+ bdinfo_print_num_ll("-> size", bd->bi_dram[i].size);
}
}
}
if (device_active(dev)) {
struct video_priv *upriv = dev_get_uclass_priv(dev);
- print_phys_addr("FB base", (ulong)upriv->fb);
+ bdinfo_print_num_ll("FB base", (ulong)upriv->fb);
if (upriv->copy_fb)
- print_phys_addr("FB copy", (ulong)upriv->copy_fb);
+ bdinfo_print_num_ll("FB copy",
+ (ulong)upriv->copy_fb);
printf("%-12s= %dx%dx%d\n", "FB size", upriv->xsize,
upriv->ysize, 1 << upriv->bpix);
}
struct bd_info *bd = gd->bd;
#ifdef DEBUG
- bdinfo_print_num("bd address", (ulong)bd);
+ bdinfo_print_num_l("bd address", (ulong)bd);
#endif
- bdinfo_print_num("boot_params", (ulong)bd->bi_boot_params);
+ bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params);
print_bi_dram(bd);
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
- bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
- bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
+ bdinfo_print_num_l("sramstart", (ulong)bd->bi_sramstart);
+ bdinfo_print_num_l("sramsize", (ulong)bd->bi_sramsize);
}
- bdinfo_print_num("flashstart", (ulong)bd->bi_flashstart);
- bdinfo_print_num("flashsize", (ulong)bd->bi_flashsize);
- bdinfo_print_num("flashoffset", (ulong)bd->bi_flashoffset);
+ bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart);
+ bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize);
+ bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset);
printf("baudrate = %u bps\n", gd->baudrate);
- bdinfo_print_num("relocaddr", gd->relocaddr);
- bdinfo_print_num("reloc off", gd->reloc_off);
+ bdinfo_print_num_l("relocaddr", gd->relocaddr);
+ bdinfo_print_num_l("reloc off", gd->reloc_off);
printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
if (IS_ENABLED(CONFIG_CMD_NET)) {
printf("current eth = %s\n", eth_get_name());
print_eth(0);
printf("IP addr = %s\n", env_get("ipaddr"));
}
- bdinfo_print_num("fdt_blob", (ulong)gd->fdt_blob);
- bdinfo_print_num("new_fdt", (ulong)gd->new_fdt);
- bdinfo_print_num("fdt_size", (ulong)gd->fdt_size);
+ bdinfo_print_num_l("fdt_blob", (ulong)gd->fdt_blob);
+ bdinfo_print_num_l("new_fdt", (ulong)gd->new_fdt);
+ bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
if (IS_ENABLED(CONFIG_DM_VIDEO))
show_video_info();
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
- bdinfo_print_num("FB base ", gd->fb_base);
+ bdinfo_print_num_l("FB base ", gd->fb_base);
#endif
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
- bdinfo_print_num("multi_dtb_fit", (ulong)gd->multi_dtb_fit);
+ bdinfo_print_num_l("multi_dtb_fit", (ulong)gd->multi_dtb_fit);
#endif
if (gd->fdt_blob) {
struct lmb lmb;
#include <cli.h>
#include <command.h>
#include <console.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/ctype.h>
#include <net.h>
#include <common.h>
#include <bloblist.h>
#include <command.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <image.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <linux/libfdt_env.h>
#include <mapmem.h>
/* Remember only PE-COFF and FIT images */
if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) {
#ifdef CONFIG_FIT
- if (!fit_check_format(buffer))
+ if (fit_check_format(buffer, IMAGE_SIZE_INVAL))
return;
/*
* FIT images of type EFI_OS are started via command bootm.
#include <lmb.h>
#include <log.h>
#include <mapmem.h>
+#include <asm/global_data.h>
#include <linux/kernel.h>
#include <linux/sizes.h>
#include <malloc.h>
#include <nand.h>
#include <asm/byteorder.h>
+#include <asm/global_data.h>
#include <linux/ctype.h>
#include <linux/err.h>
#include <u-boot/zlib.h>
case IMAGE_FORMAT_FIT:
puts(" FIT image found\n");
- if (!fit_check_format(hdr)) {
+ if (fit_check_format(hdr, IMAGE_SIZE_INVAL)) {
puts("Bad FIT image format!\n");
unmap_sysmem(hdr);
return 1;
#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
- if (!fit_check_format(hdr))
+ if (fit_check_format(hdr, IMAGE_SIZE_INVAL))
goto next_sector;
printf("FIT Image at %08lX:\n", (ulong)hdr);
return ret;
}
- if (!fit_check_format(imgdata)) {
+ if (fit_check_format(imgdata, IMAGE_SIZE_INVAL)) {
free(imgdata);
return 0;
}
#include <dm.h>
#include <rtc.h>
#include <i2c.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
/* This cannot be done earlier,
* we need complete FIT image in RAM first */
if (genimg_get_format((void *) addr) == IMAGE_FORMAT_FIT) {
- if (!fit_check_format(fit_hdr)) {
+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
bootstage_error(BOOTSTAGE_ID_IDE_FIT_READ);
puts("** Bad FIT image format\n");
return 1;
#endif
#endif
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
static int eeprom_i2c_bus;
#endif
void eeprom_init(int bus)
{
/* I2C EEPROM */
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
eeprom_i2c_bus = bus;
#elif defined(CONFIG_SYS_I2C)
if (bus >= 0)
{
int ret = 0;
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(eeprom_i2c_bus, addr[0],
#include <log.h>
#include <malloc.h>
#include <sort.h>
+#include <asm/global_data.h>
static const char *const type_name[] = {
"reserved",
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
+#include <part.h>
#include <search.h>
#include <linux/ctype.h>
"Device-Tree Fixup",
EFI_DT_FIXUP_PROTOCOL_GUID,
},
+ {
+ "System Partition",
+ PARTITION_SYSTEM_GUID
+ },
/* Configuration table GUIDs */
{
"ACPI table",
return CMD_RET_FAILURE;
}
- if (!fit_check_format(fit_hdr)) {
+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
puts("Bad FIT image format\n");
return CMD_RET_FAILURE;
}
* For legacy code, this is not stored, so we need to use a suitable
* default.
*/
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
#define DEFAULT_ADDR_LEN (-1)
#else
#define DEFAULT_ADDR_LEN 1
#endif
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static struct udevice *i2c_cur_bus;
static int cmd_i2c_set_bus_num(unsigned int busnum)
*
* Returns I2C bus speed in Hz.
*/
-#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
+#if !defined(CONFIG_SYS_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
/*
* TODO: Implement architecture-specific get/set functions
* Should go away, if we switched completely to new multibus support
int alen;
u_char *memaddr;
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
*/
memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
int alen;
u_char *memaddr;
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
struct dm_i2c_chip *i2c_chip;
#endif
*/
length = simple_strtoul(argv[4], NULL, 16);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
* a page boundary. No write delay upon completion, take this
* into account if linking commands.
*/
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
ret = dm_i2c_write(dev, devaddr, memaddr, length);
#else
* write transactions of one byte each
*/
while (length-- > 0) {
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
i2c_chip->flags |= DM_I2C_CHIP_WR_ADDRESS;
ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
#else
return 0;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static int do_i2c_flags(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int alen;
int j, nbytes, linebytes;
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
length = simple_strtoul(argv[3], NULL, 16);
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, addr, linebuf, linebytes);
#else
ret = i2c_read(chip, addr, alen, linebuf, linebytes);
uchar byte;
int count;
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
if (alen > 3)
return CMD_RET_USAGE;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
count = 1;
while (count-- > 0) {
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_write(dev, addr++, &byte, 1);
#else
ret = i2c_write(chip, addr++, alen, &byte, 1);
ulong crc;
ulong err;
int ret = 0;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
if (alen > 3)
return CMD_RET_USAGE;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
crc = 0;
err = 0;
while (count-- > 0) {
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, addr, &byte, 1);
#else
ret = i2c_read(chip, addr, alen, &byte, 1);
int size = 1;
int nbytes;
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
return CMD_RET_USAGE;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
*/
do {
printf("%08lx:", addr);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
#else
ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
* good enough to not time out
*/
bootretry_reset_cmd_timeout();
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_write(dev, addr, (uchar *)&data,
size);
#else
unsigned int bus = GET_BUS_NUM;
#endif /* NOPROBES */
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus, *dev;
if (i2c_get_cur_bus(&bus))
if (skip)
continue;
#endif
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_probe(bus, j, 0, &dev);
#else
ret = i2c_probe(j);
u_char bytes[16];
int delay;
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen > 3)
return CMD_RET_USAGE;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
* Run the loop...
*/
while (1) {
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, addr, bytes, length);
#else
ret = i2c_read(chip, addr, alen, bytes, length);
u_char data[128];
u_char cksum;
int j, ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
*/
chip = simple_strtoul (argv[1], NULL, 16);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret)
ret = dm_i2c_read(dev, 0, data, sizeof(data));
uint chip;
struct edid1_info edid;
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
#endif
}
chip = simple_strtoul(argv[1], NULL, 16);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret)
ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
}
#endif /* CONFIG_I2C_EDID */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static void show_bus(struct udevice *bus)
{
struct udevice *dev;
*
* Returns zero always.
*/
-#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
+#if defined(CONFIG_SYS_I2C) || CONFIG_IS_ENABLED(DM_I2C)
static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
if (argc == 1) {
/* show all busses */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus;
struct uclass *uc;
int ret;
/* show specific bus */
i = simple_strtoul(argv[1], NULL, 10);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus;
int ret;
* on error.
*/
#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
- defined(CONFIG_DM_I2C)
+ CONFIG_IS_ENABLED(DM_I2C)
static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
if (argc == 1) {
/* querying current setting */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus;
if (!i2c_get_cur_bus(&bus))
}
#endif
printf("Setting bus to %d\n", bus_no);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = cmd_i2c_set_bus_num(bus_no);
#else
ret = i2c_set_bus_num(bus_no);
{
int speed, ret=0;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus;
if (i2c_get_cur_bus(&bus))
return 1;
#endif
if (argc == 1) {
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
speed = dm_i2c_get_bus_speed(bus);
#else
speed = i2c_get_bus_speed();
} else {
speed = simple_strtoul(argv[1], NULL, 10);
printf("Setting bus speed to %d Hz\n", speed);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_set_bus_speed(bus, speed);
#else
ret = i2c_set_bus_speed(speed);
static int do_i2c_reset(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus;
if (i2c_get_cur_bus(&bus))
}
static struct cmd_tbl cmd_i2c_sub[] = {
-#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
+#if defined(CONFIG_SYS_I2C) || CONFIG_IS_ENABLED(DM_I2C)
U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
#endif
U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
#if defined(CONFIG_SYS_I2C) || \
- defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
+ defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
#endif /* CONFIG_I2C_MULTI_BUS */
#if defined(CONFIG_I2C_EDID)
U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
U_BOOT_CMD_MKENT(olen, 2, 1, do_i2c_olen, "", ""),
#endif
/***************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char i2c_help_text[] =
-#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
+#if defined(CONFIG_SYS_I2C) || CONFIG_IS_ENABLED(DM_I2C)
"bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
"i2c " /* That's the prefix for the crc32 command below. */
#endif
"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
#if defined(CONFIG_SYS_I2C) || \
- defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
+ defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
"i2c dev [dev] - show or set current I2C bus\n"
#endif /* CONFIG_I2C_MULTI_BUS */
#if defined(CONFIG_I2C_EDID)
"i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
"i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
" to I2C; the -s option selects bulk write in a single transaction\n"
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
"i2c flags chip [flags] - set or get chip flags\n"
"i2c olen chip [offset_length] - set or get chip offset length\n"
#endif
#include <serial.h>
#include <xyzModem.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#include <getopt.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
static char log_fmt_chars[LOGF_COUNT] = "clFLfm";
#include <mapmem.h>
#include <rand.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
" Power cycling is required to initialize partitions after set to complete.\n"
#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT
- "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n"
+ "mmc bootbus <dev> <boot_bus_width> <reset_boot_bus_width> <boot_mode>\n"
" - Set the BOOT_BUS_WIDTH field of the specified device\n"
"mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>\n"
" - Change sizes of boot and RPMB partitions of specified device\n"
- "mmc partconf dev [boot_ack boot_partition partition_access]\n"
+ "mmc partconf <dev> [boot_ack boot_partition partition_access]\n"
" - Show or change the bits of the PARTITION_CONFIG field of the specified device\n"
- "mmc rst-function dev value\n"
+ "mmc rst-function <dev> <value>\n"
" - Change the RST_n_FUNCTION field of the specified device\n"
" WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n"
#endif
#include <env.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <jffs2/load_kernel.h>
#include <linux/list.h>
#include <linux/ctype.h>
bubt, 4, 0, do_bubt_cmd,
"Burn a u-boot image to flash",
"[file-name] [destination [source]]\n"
- "\t-file-name The image file name to burn. Default = flash-image.bin\n"
- "\t-destination Flash to burn to [spi, nand, mmc]. Default = active boot device\n"
- "\t-source The source to load image from [tftp, usb, mmc]. Default = tftp\n"
+ "\t-file-name The image file name to burn. Default = " CONFIG_MVEBU_UBOOT_DFLT_NAME "\n"
+ "\t-destination Flash to burn to [spi, nand, mmc]. Default = " DEFAULT_BUBT_DST "\n"
+ "\t-source The source to load image from [tftp, usb, mmc]. Default = " DEFAULT_BUBT_SRC "\n"
"Examples:\n"
"\tbubt - Burn flash-image.bin from tftp to active boot device\n"
"\tbubt flash-image-new.bin nand - Burn flash-image-new.bin from tftp to NAND flash\n"
#if defined(CONFIG_FIT)
/* This cannot be done earlier, we need complete FIT image in RAM first */
if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) {
- if (!fit_check_format (fit_hdr)) {
+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
bootstage_error(BOOTSTAGE_ID_NAND_FIT_READ);
puts ("** Bad FIT image format\n");
return 1;
#include <errno.h>
#include <malloc.h>
#include <mapmem.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <u-boot/crc.h>
#include <watchdog.h>
#include <config.h>
#include <command.h>
+#include <fdtdec.h>
#include <fs.h>
#include <log.h>
#include <mapmem.h>
env_get("gatewayip"), env_get("netmask"));
}
-#ifdef CONFIG_CMD_NET
- if (label->ipappend & 0x2) {
- int err;
-
- strcpy(mac_str, " BOOTIF=");
- err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8);
- if (err < 0)
- mac_str[0] = '\0';
+ if (IS_ENABLED(CONFIG_CMD_NET)) {
+ if (label->ipappend & 0x2) {
+ int err;
+
+ strcpy(mac_str, " BOOTIF=");
+ err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8);
+ if (err < 0)
+ mac_str[0] = '\0';
+ }
}
-#endif
if ((label->ipappend & 0x3) || label->append) {
char bootargs[CONFIG_SYS_CBSIZE] = "";
/* Try bootm for legacy and FIT format image */
if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID)
do_bootm(cmdtp, 0, bootm_argc, bootm_argv);
-#ifdef CONFIG_CMD_BOOTI
/* Try booting an AArch64 Linux kernel image */
- else
+ else if (IS_ENABLED(CONFIG_CMD_BOOTI))
do_booti(cmdtp, 0, bootm_argc, bootm_argv);
-#elif defined(CONFIG_CMD_BOOTZ)
/* Try booting a Image */
- else
+ else if (IS_ENABLED(CONFIG_CMD_BOOTZ))
do_bootz(cmdtp, 0, bootm_argc, bootm_argv);
-#endif
+ /* Try booting an x86_64 Linux kernel image */
+ else if (IS_ENABLED(CONFIG_CMD_ZBOOT))
+ do_zboot_parent(cmdtp, 0, bootm_argc, bootm_argv, NULL);
+
unmap_sysmem(buf);
cleanup:
struct menu *m;
int err;
-#ifdef CONFIG_CMD_BMP
- /* display BMP if available */
- if (cfg->bmp) {
- if (get_relfile(cmdtp, cfg->bmp, image_load_addr)) {
- if (CONFIG_IS_ENABLED(CMD_CLS))
- run_command("cls", 0);
- bmp_display(image_load_addr,
- BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
- } else {
- printf("Skipping background bmp %s for failure\n",
- cfg->bmp);
+ if (IS_ENABLED(CONFIG_CMD_BMP)) {
+ /* display BMP if available */
+ if (cfg->bmp) {
+ if (get_relfile(cmdtp, cfg->bmp, image_load_addr)) {
+ if (CONFIG_IS_ENABLED(CMD_CLS))
+ run_command("cls", 0);
+ bmp_display(image_load_addr,
+ BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
+ } else {
+ printf("Skipping background bmp %s for failure\n",
+ cfg->bmp);
+ }
}
}
-#endif
m = pxe_menu_to_menu(cfg);
if (!m)
#ifndef __PXE_UTILS_H
#define __PXE_UTILS_H
+#include <linux/list.h>
+
/*
* A note on the pxe file parser.
*
#include <command.h>
#include <dm.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/state.h>
static int do_sb_handoff(struct cmd_tbl *cmdtp, int flag, int argc,
#include <dm.h>
#include <fdtdec.h>
#include <sound.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = buf;
- if (!fit_check_format (fit_hdr)) {
+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
puts ("Bad FIT image format\n");
return 1;
}
#include <env.h>
#include <image.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/emif.h>
#include <common.h>
#include <command.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <env.h>
#include <init.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/ctype.h>
#include <u-boot/crc.h>
#include <common.h>
#include <command.h>
#include <asm/fsp/fsp_support.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <command.h>
#include <efi.h>
#include <uuid.h>
+#include <asm/global_data.h>
#include <asm/hob.h>
#include <asm/fsp/fsp_hob.h>
"at %08lx ...\n", uname, addr);
fit_hdr = (const void *)addr;
- if (!fit_check_format(fit_hdr)) {
+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
puts("Bad FIT image format\n");
return 1;
}
SHA512 checksum is a 512-bit (64-byte) hash value used to check that
the image contents have not been corrupted.
+config FIT_FULL_CHECK
+ bool "Do a full check of the FIT before using it"
+ default y
+ help
+ Enable this do a full check of the FIT to make sure it is valid. This
+ helps to protect against carefully crafted FITs which take advantage
+ of bugs or omissions in the code. This includes a bad structure,
+ multiple root nodes and the like.
+
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
select RSA
select RSA_VERIFY
select IMAGE_SIGN_INFO
+ select FIT_FULL_CHECK
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA. If
help
Support printing the content of the fitImage in a verbose manner in SPL.
+config SPL_FIT_FULL_CHECK
+ bool "Do a full check of the FIT before using it"
+ help
+ Enable this do a full check of the FIT to make sure it is valid. This
+ helps to protect against carefully crafted FITs which take advantage
+ of bugs or omissions in the code. This includes a bad structure,
+ multiple root nodes and the like.
+
+
config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
depends on SPL_DM
select SPL_RSA
select SPL_RSA_VERIFY
select SPL_IMAGE_SIGN_INFO
+ select SPL_FIT_FULL_CHECK
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
#include <menu.h>
#include <post.h>
#include <time.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <u-boot/sha256.h>
#include <bootcount.h>
#include <log.h>
#include <mapmem.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <u-boot/crc.h>
/*
#if defined(CONFIG_MP) && defined(CONFIG_PPC)
#include <asm/mp.h>
#endif
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/sections.h>
#include <dm/root.h>
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <linux/compiler.h>
#include <log.h>
#include <net.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <u-boot/crc.h>
/* TODO: can we just include all these headers whether needed or not? */
#if defined(CONFIG_CMD_BEDBUG)
#include <mapmem.h>
#include <net.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/sizes.h>
#if defined(CONFIG_CMD_USB)
#include <image.h>
#include <lmb.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <mapmem.h>
#include <malloc.h>
#include <sort.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <linux/libfdt.h>
#include <fdtdec.h>
#include <hang.h>
#include <malloc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <cli.h>
#include <cli_hush.h>
#include <command.h> /* find_cmd */
+#include <asm/global_data.h>
#endif
#ifndef __U_BOOT__
#include <ctype.h> /* isalpha, isdigit */
#include <command.h>
#include <time.h>
#include <watchdog.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <console.h>
#include <env.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/ctype.h>
DECLARE_GLOBAL_DATA_PTR;
#include <exports.h>
#include <env_internal.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
struct stdio_dev **console_devices[MAX_FILES];
int cd_count[MAX_FILES];
-static void __maybe_unused console_devices_set(int file, struct stdio_dev *dev)
+static void console_devices_set(int file, struct stdio_dev *dev)
{
console_devices[file][0] = dev;
+ cd_count[file] = 1;
}
/**
*/
static bool console_needs_start_stop(int file, struct stdio_dev *sdev)
{
- int i, j;
+ int i;
for (i = 0; i < ARRAY_SIZE(cd_count); i++) {
if (i == file)
continue;
- for (j = 0; j < cd_count[i]; j++)
- if (console_devices[i][j] == sdev)
- return false;
+ if (iomux_match_device(console_devices[i], cd_count[i], sdev) >= 0)
+ return false;
}
return true;
}
int prev;
prev = disable_ctrlc(1);
- for (i = 0; i < cd_count[file]; i++) {
- dev = console_devices[file][i];
+ for_each_console_dev(i, file, dev) {
if (dev->tstc != NULL) {
ret = dev->tstc(dev);
if (ret > 0) {
int i;
struct stdio_dev *dev;
- for (i = 0; i < cd_count[file]; i++) {
- dev = console_devices[file][i];
+ for_each_console_dev(i, file, dev) {
if (dev->putc != NULL)
dev->putc(dev, c);
}
int i;
struct stdio_dev *dev;
- for (i = 0; i < cd_count[file]; i++) {
- bool is_serial;
+ for_each_console_dev(i, file, dev) {
+ bool is_serial = console_dev_is_serial(dev);
- dev = console_devices[file][i];
- is_serial = console_dev_is_serial(dev);
if (dev->puts && serial_only == is_serial)
dev->puts(dev, s);
}
int i;
struct stdio_dev *dev;
- for (i = 0; i < cd_count[file]; i++) {
- dev = console_devices[file][i];
+ for_each_console_dev(i, file, dev) {
if (dev->puts != NULL)
dev->puts(dev, s);
}
#endif
#else
-static void __maybe_unused console_devices_set(int file, struct stdio_dev *dev)
+static void console_devices_set(int file, struct stdio_dev *dev)
{
}
#endif
#endif /* CONIFIG_IS_ENABLED(CONSOLE_MUX) */
+static void __maybe_unused console_setfile_and_devices(int file, struct stdio_dev *dev)
+{
+ console_setfile(file, dev);
+ console_devices_set(file, dev);
+}
+
int console_start(int file, struct stdio_dev *sdev)
{
int error;
struct stdio_dev *dev;
/* Check for valid file */
- switch (file) {
- case stdin:
- flag = DEV_FLAGS_INPUT;
- break;
- case stdout:
- case stderr:
- flag = DEV_FLAGS_OUTPUT;
- break;
- default:
- return -1;
- }
+ flag = stdio_file_to_flags(file);
+ if (flag < 0)
+ return flag;
/* Check for valid device name */
/* Initializes output console first */
if (outputdev != NULL) {
- console_setfile(stdout, outputdev);
- console_setfile(stderr, outputdev);
- console_devices_set(stdout, outputdev);
- console_devices_set(stderr, outputdev);
+ console_setfile_and_devices(stdout, outputdev);
+ console_setfile_and_devices(stderr, outputdev);
}
/* Initializes input console */
- if (inputdev != NULL) {
- console_setfile(stdin, inputdev);
- console_devices_set(stdin, inputdev);
- }
+ if (inputdev != NULL)
+ console_setfile_and_devices(stdin, inputdev);
if (!IS_ENABLED(CONFIG_SYS_CONSOLE_INFO_QUIET))
stdio_print_current_devices();
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#if CONFIG_IS_ENABLED(UNIT_TEST)
#define DEBUG
#include <malloc.h>
#include <spi.h>
#include <i2c.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
int depth = -1;
int want = 0;
int base = fdt_off_dt_struct(fdt);
+ bool expect_end = false;
end = path;
*end = '\0';
tag = fdt_next_tag(fdt, offset, &nextoffset);
stop_at = nextoffset;
+ /* If we see two root nodes, something is wrong */
+ if (expect_end && tag != FDT_END)
+ return -FDT_ERR_BADLAYOUT;
+
switch (tag) {
case FDT_PROP:
include = want >= 2;
if (depth == FDT_MAX_DEPTH)
return -FDT_ERR_BADSTRUCTURE;
name = fdt_get_name(fdt, offset, &len);
+
+ /* The root node must have an empty name */
+ if (!depth && *name)
+ return -FDT_ERR_BADLAYOUT;
if (end - path + 2 + len >= path_len)
return -FDT_ERR_NOSPACE;
if (end != path + 1)
while (end > path && *--end != '/')
;
*end = '\0';
+ if (depth == -1)
+ expect_end = true;
break;
case FDT_END:
return offset;
}
-/* rename to CONFIG_OF_STDOUT_PATH ? */
-#if defined(OF_STDOUT_PATH)
-static int fdt_fixup_stdout(void *fdt, int chosenoff)
-{
- return fdt_setprop(fdt, chosenoff, "linux,stdout-path",
- OF_STDOUT_PATH, strlen(OF_STDOUT_PATH) + 1);
-}
-#elif defined(CONFIG_OF_STDOUT_VIA_ALIAS) && defined(CONFIG_CONS_INDEX)
+#if defined(CONFIG_OF_STDOUT_VIA_ALIAS) && defined(CONFIG_CONS_INDEX)
static int fdt_fixup_stdout(void *fdt, int chosenoff)
{
int err;
return __of_translate_address(blob, node_offset, in_addr, "dma-ranges");
}
+int fdt_get_dma_range(const void *blob, int node, phys_addr_t *cpu,
+ dma_addr_t *bus, u64 *size)
+{
+ bool found_dma_ranges = false;
+ struct of_bus *bus_node;
+ const fdt32_t *ranges;
+ int na, ns, pna, pns;
+ int parent = node;
+ int ret = 0;
+ int len;
+
+ /* Find the closest dma-ranges property */
+ while (parent >= 0) {
+ ranges = fdt_getprop(blob, parent, "dma-ranges", &len);
+
+ /* Ignore empty ranges, they imply no translation required */
+ if (ranges && len > 0)
+ break;
+
+ /* Once we find 'dma-ranges', then a missing one is an error */
+ if (found_dma_ranges && !ranges) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (ranges)
+ found_dma_ranges = true;
+
+ parent = fdt_parent_offset(blob, parent);
+ }
+
+ if (!ranges || parent < 0) {
+ debug("no dma-ranges found for node %s\n",
+ fdt_get_name(blob, node, NULL));
+ ret = -ENOENT;
+ goto out;
+ }
+
+ /* switch to that node */
+ node = parent;
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0) {
+ printf("Found dma-ranges in root node, shoudln't happen\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Get the address sizes both for the bus and its parent */
+ bus_node = of_match_bus(blob, node);
+ bus_node->count_cells(blob, node, &na, &ns);
+ if (!OF_CHECK_COUNTS(na, ns)) {
+ printf("%s: Bad cell count for %s\n", __FUNCTION__,
+ fdt_get_name(blob, node, NULL));
+ return -EINVAL;
+ goto out;
+ }
+
+ bus_node = of_match_bus(blob, parent);
+ bus_node->count_cells(blob, parent, &pna, &pns);
+ if (!OF_CHECK_COUNTS(pna, pns)) {
+ printf("%s: Bad cell count for %s\n", __FUNCTION__,
+ fdt_get_name(blob, parent, NULL));
+ return -EINVAL;
+ goto out;
+ }
+
+ *bus = fdt_read_number(ranges, na);
+ *cpu = fdt_translate_dma_address(blob, node, ranges + na);
+ *size = fdt_read_number(ranges + na + pna, ns);
+out:
+ return ret;
+}
+
/**
* fdt_node_offset_by_compat_reg: Find a node that matches compatiable and
* who's reg property matches a physical cpu address
#include <mapmem.h>
#include <hw_sha.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <u-boot/crc.h>
#include <exports.h>
#include <hwconfig.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/types.h>
#include <linux/string.h>
#else
#include <errno.h>
#include <asm/unaligned.h>
#include <mapmem.h>
+#include <linux/libfdt.h>
#define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
#else
#include <common.h>
#include <malloc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSdTCC*/
#include <image.h>
#include <lmb.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <mapmem.h>
#include <asm/io.h>
*/
#if CONFIG_IS_ENABLED(FIT)
/* check FDT blob vs FIT blob */
- if (fit_check_format(buf)) {
+ if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) {
ulong load, len;
fdt_noffset = boot_get_fdt_fit(images,
#include <common.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
#include <fdt_region.h>
fdt_for_each_subnode(noffset, fit, image_noffset) {
const char *name = fit_get_name(fit, noffset, NULL);
+ /*
+ * We don't support this since libfdt considers names with the
+ * name root but different @ suffix to be equal
+ */
+ if (strchr(name, '@')) {
+ err_msg = "Node name contains @";
+ goto error;
+ }
if (!strncmp(name, FIT_SIG_NODENAME,
strlen(FIT_SIG_NODENAME))) {
ret = fit_image_check_sig(fit, noffset, data,
return -EPERM;
}
-int fit_config_verify_required_sigs(const void *fit, int conf_noffset,
- const void *sig_blob)
+static int fit_config_verify_required_sigs(const void *fit, int conf_noffset,
+ const void *sig_blob)
{
+ const char *name = fit_get_name(fit, conf_noffset, NULL);
int noffset;
int sig_node;
int verified = 0;
bool reqd_policy_all = true;
const char *reqd_mode;
+ /*
+ * We don't support this since libfdt considers names with the
+ * name root but different @ suffix to be equal
+ */
+ if (strchr(name, '@')) {
+ printf("Configuration node '%s' contains '@'\n", name);
+ return -EPERM;
+ }
+
/* Work out what we need to verify */
sig_node = fdt_subnode_offset(sig_blob, 0, FIT_SIG_NODENAME);
if (sig_node < 0) {
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#ifdef USE_HOSTCC
#include "mkimage.h"
#include <time.h>
#include <mapmem.h>
#include <asm/io.h>
#include <malloc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
*/
int fit_image_verify(const void *fit, int image_noffset)
{
+ const char *name = fit_get_name(fit, image_noffset, NULL);
const void *data;
size_t size;
- int noffset = 0;
char *err_msg = "";
+ if (strchr(name, '@')) {
+ /*
+ * We don't support this since libfdt considers names with the
+ * name root but different @ suffix to be equal
+ */
+ err_msg = "Node name contains @";
+ goto err;
+ }
/* Get image data and data length */
if (fit_image_get_data_and_size(fit, image_noffset, &data, &size)) {
err_msg = "Can't get image data/size";
- printf("error!\n%s for '%s' hash node in '%s' image node\n",
- err_msg, fit_get_name(fit, noffset, NULL),
- fit_get_name(fit, image_noffset, NULL));
- return 0;
+ goto err;
}
return fit_image_verify_with_data(fit, image_noffset, data, size);
+
+err:
+ printf("error!\n%s in '%s' image node\n", err_msg,
+ fit_get_name(fit, image_noffset, NULL));
+ return 0;
}
/**
}
/**
- * fit_check_format - sanity check FIT image format
- * @fit: pointer to the FIT format image header
+ * fdt_check_no_at() - Check for nodes whose names contain '@'
*
- * fit_check_format() runs a basic sanity FIT image verification.
- * Routine checks for mandatory properties, nodes, etc.
+ * This checks the parent node and all subnodes recursively
*
- * returns:
- * 1, on success
- * 0, on failure
+ * @fit: FIT to check
+ * @parent: Parent node to check
+ * @return 0 if OK, -EADDRNOTAVAIL is a node has a name containing '@'
*/
-int fit_check_format(const void *fit)
+static int fdt_check_no_at(const void *fit, int parent)
{
+ const char *name;
+ int node;
+ int ret;
+
+ name = fdt_get_name(fit, parent, NULL);
+ if (!name || strchr(name, '@'))
+ return -EADDRNOTAVAIL;
+
+ fdt_for_each_subnode(node, fit, parent) {
+ ret = fdt_check_no_at(fit, node);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int fit_check_format(const void *fit, ulong size)
+{
+ int ret;
+
/* A FIT image must be a valid FDT */
- if (fdt_check_header(fit)) {
- debug("Wrong FIT format: not a flattened device tree\n");
- return 0;
+ ret = fdt_check_header(fit);
+ if (ret) {
+ log_debug("Wrong FIT format: not a flattened device tree (err=%d)\n",
+ ret);
+ return -ENOEXEC;
+ }
+
+ if (CONFIG_IS_ENABLED(FIT_FULL_CHECK)) {
+ /*
+ * If we are not given the size, make do wtih calculating it.
+ * This is not as secure, so we should consider a flag to
+ * control this.
+ */
+ if (size == IMAGE_SIZE_INVAL)
+ size = fdt_totalsize(fit);
+ ret = fdt_check_full(fit, size);
+ if (ret)
+ ret = -EINVAL;
+
+ /*
+ * U-Boot stopped using unit addressed in 2017. Since libfdt
+ * can match nodes ignoring any unit address, signature
+ * verification can see the wrong node if one is inserted with
+ * the same name as a valid node but with a unit address
+ * attached. Protect against this by disallowing unit addresses.
+ */
+ if (!ret && CONFIG_IS_ENABLED(FIT_SIGNATURE)) {
+ ret = fdt_check_no_at(fit, 0);
+
+ if (ret) {
+ log_debug("FIT check error %d\n", ret);
+ return ret;
+ }
+ }
+ if (ret) {
+ log_debug("FIT check error %d\n", ret);
+ return ret;
+ }
}
/* mandatory / node 'description' property */
- if (fdt_getprop(fit, 0, FIT_DESC_PROP, NULL) == NULL) {
- debug("Wrong FIT format: no description\n");
- return 0;
+ if (!fdt_getprop(fit, 0, FIT_DESC_PROP, NULL)) {
+ log_debug("Wrong FIT format: no description\n");
+ return -ENOMSG;
}
if (IMAGE_ENABLE_TIMESTAMP) {
/* mandatory / node 'timestamp' property */
- if (fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL) == NULL) {
- debug("Wrong FIT format: no timestamp\n");
- return 0;
+ if (!fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL)) {
+ log_debug("Wrong FIT format: no timestamp\n");
+ return -ENODATA;
}
}
/* mandatory subimages parent '/images' node */
if (fdt_path_offset(fit, FIT_IMAGES_PATH) < 0) {
- debug("Wrong FIT format: no images parent node\n");
- return 0;
+ log_debug("Wrong FIT format: no images parent node\n");
+ return -ENOENT;
}
- return 1;
+ return 0;
}
-
/**
* fit_conf_find_compat
* @fit: pointer to the FIT format image header
printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr);
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT);
- if (!fit_check_format(fit)) {
- printf("Bad FIT %s image format!\n", prop_name);
+ ret = fit_check_format(fit, IMAGE_SIZE_INVAL);
+ if (ret) {
+ printf("Bad FIT %s image format! (err=%d)\n", prop_name, ret);
+ if (CONFIG_IS_ENABLED(FIT_SIGNATURE) && ret == -EADDRNOTAVAIL)
+ printf("Signature checking prevents use of unit addresses (@) in nodes\n");
bootstage_error(bootstage_id + BOOTSTAGE_SUB_FORMAT);
- return -ENOEXEC;
+ return ret;
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK);
if (fit_uname) {
#include <common.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
#include <image.h>
#include <xilinx.h>
#endif
+#include <asm/global_data.h>
#include <u-boot/md5.h>
#include <u-boot/sha1.h>
#include <linux/errno.h>
#include <common.h>
#include <bootstage.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <handoff.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
int i;
struct stdio_dev *dev;
- for (i = 0; i < cd_count[console]; i++) {
- dev = console_devices[console][i];
+ for_each_console_dev(i, console, dev)
printf("%s ", dev->name);
- }
printf("\n");
}
+int iomux_match_device(struct stdio_dev **set, const int n, struct stdio_dev *sdev)
+{
+ int i;
+
+ for (i = 0; i < n; i++)
+ if (sdev == set[i])
+ return i;
+ return -ENOENT;
+}
+
/* This tries to preserve the old list if an error occurs. */
int iomux_doenv(const int console, const char *arg)
{
char *console_args, *temp, **start;
- int i, j, k, io_flag, cs_idx, repeat;
+ int i, j, io_flag, cs_idx, repeat;
struct stdio_dev **cons_set, **old_set;
struct stdio_dev *dev;
return 1;
}
- switch (console) {
- case stdin:
- io_flag = DEV_FLAGS_INPUT;
- break;
- case stdout:
- case stderr:
- io_flag = DEV_FLAGS_OUTPUT;
- break;
- default:
+ io_flag = stdio_file_to_flags(console);
+ if (io_flag < 0) {
free(start);
free(console_args);
free(cons_set);
/*
* Prevent multiple entries for a device.
*/
- repeat = 0;
- for (k = 0; k < cs_idx; k++) {
- if (dev == cons_set[k]) {
- repeat++;
- break;
- }
- }
- if (repeat)
+ repeat = iomux_match_device(cons_set, cs_idx, dev);
+ if (repeat >= 0)
continue;
/*
* Try assigning the specified device.
/* Stop dropped consoles */
for (i = 0; i < repeat; i++) {
- for (j = 0; j < cs_idx; j++) {
- if (old_set[i] == cons_set[j])
- break;
- }
+ j = iomux_match_device(cons_set, cs_idx, old_set[i]);
if (j == cs_idx)
console_stop(console, old_set[i]);
}
free(old_set);
return 0;
}
+
+int iomux_replace_device(const int console, const char *old, const char *new)
+{
+ struct stdio_dev *dev;
+ char *arg = NULL; /* Initial empty list */
+ int size = 1; /* For NUL terminator */
+ int i, ret;
+
+ for_each_console_dev(i, console, dev) {
+ const char *name = strcmp(dev->name, old) ? dev->name : new;
+ char *tmp;
+
+ /* Append name with a ',' (comma) separator */
+ tmp = realloc(arg, size + strlen(name) + 1);
+ if (!tmp) {
+ free(arg);
+ return -ENOMEM;
+ }
+
+ strcat(tmp, ",");
+ strcat(tmp, name);
+
+ arg = tmp;
+ size = strlen(tmp) + 1;
+ }
+
+ ret = iomux_doenv(console, arg);
+ if (ret)
+ ret = -EINVAL;
+
+ free(arg);
+ return ret;
+}
#endif /* CONSOLE_MUX */
#include <common.h>
#include <mapmem.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bug.h>
#include <u-boot/crc.h>
#include <log.h>
#include <asm/cache.h>
#include <init.h>
+#include <asm/global_data.h>
#include <linux/types.h>
#include <stdio_dev.h>
#include <lcd.h>
#include <dm.h>
#include <lcd.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <video.h>
#include <common.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <log.h>
#include <net.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <init.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <log.h>
#include <serial.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/u-boot.h>
#include <nand.h>
#include <fat.h>
#include <spl.h>
#include <sysinfo.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#endif
-__weak void board_spl_fit_post_load(ulong load_addr, size_t length)
+struct spl_fit_info {
+ const void *fit; /* Pointer to a valid FIT blob */
+ size_t ext_data_offset; /* Offset to FIT external data (end of FIT) */
+ int images_node; /* FDT offset to "/images" node */
+ int conf_node; /* FDT offset to selected configuration node */
+};
+
+__weak void board_spl_fit_post_load(const void *fit)
{
}
*
* Return: 0 on success, or a negative error number
*/
-static int spl_fit_get_image_name(const void *fit, int images,
+static int spl_fit_get_image_name(const struct spl_fit_info *ctx,
const char *type, int index,
const char **outname)
{
struct udevice *sysinfo;
const char *name, *str;
__maybe_unused int node;
- int conf_node;
int len, i;
bool found = true;
- conf_node = fit_find_config_node(fit);
- if (conf_node < 0) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("No matching DT out of these options:\n");
- for (node = fdt_first_subnode(fit, conf_node);
- node >= 0;
- node = fdt_next_subnode(fit, node)) {
- name = fdt_getprop(fit, node, "description", &len);
- printf(" %s\n", name);
- }
-#endif
- return conf_node;
- }
-
- name = fdt_getprop(fit, conf_node, type, &len);
+ name = fdt_getprop(ctx->fit, ctx->conf_node, type, &len);
if (!name) {
debug("cannot find property '%s': %d\n", type, len);
return -EINVAL;
* node name.
*/
int node;
- int images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+ int images = fdt_path_offset(ctx->fit, FIT_IMAGES_PATH);
- node = find_node_from_desc(fit, images, str);
+ node = find_node_from_desc(ctx->fit, images, str);
if (node > 0)
- str = fdt_get_name(fit, node, NULL);
+ str = fdt_get_name(ctx->fit, node, NULL);
found = true;
}
* Return: the node offset of the respective image node or a negative
* error number.
*/
-static int spl_fit_get_image_node(const void *fit, int images,
+static int spl_fit_get_image_node(const struct spl_fit_info *ctx,
const char *type, int index)
{
const char *str;
int err;
int node;
- err = spl_fit_get_image_name(fit, images, type, index, &str);
+ err = spl_fit_get_image_name(ctx, type, index, &str);
if (err)
return err;
debug("%s: '%s'\n", type, str);
- node = fdt_subnode_offset(fit, images, str);
+ node = fdt_subnode_offset(ctx->fit, ctx->images_node, str);
if (node < 0) {
pr_err("cannot find image node '%s': %d\n", str, node);
return -EINVAL;
* spl_load_fit_image(): load the image described in a certain FIT node
* @info: points to information about the device to load data from
* @sector: the start sector of the FIT image on the device
- * @fit: points to the flattened device tree blob describing the FIT
- * image
- * @base_offset: the beginning of the data area containing the actual
- * image data, relative to the beginning of the FIT
+ * @ctx: points to the FIT context structure
* @node: offset of the DT node describing the image to load (relative
* to @fit)
* @image_info: will be filled with information about the loaded image
* Return: 0 on success or a negative error number.
*/
static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
- void *fit, ulong base_offset, int node,
+ const struct spl_fit_info *ctx, int node,
struct spl_image_info *image_info)
{
int offset;
int align_len = ARCH_DMA_MINALIGN - 1;
uint8_t image_comp = -1, type = -1;
const void *data;
+ const void *fit = ctx->fit;
bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
if (!fit_image_get_data_position(fit, node, &offset)) {
external_data = true;
} else if (!fit_image_get_data_offset(fit, node, &offset)) {
- offset += base_offset;
+ offset += ctx->ext_data_offset;
external_data = true;
}
src = (void *)data;
}
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- printf("## Checking hash(es) for Image %s ... ",
- fit_get_name(fit, node, NULL));
- if (!fit_image_verify_with_data(fit, node,
- src, length))
- return -EPERM;
- puts("OK\n");
-#endif
+ if (CONFIG_IS_ENABLED(FIT_SIGNATURE)) {
+ printf("## Checking hash(es) for Image %s ... ",
+ fit_get_name(fit, node, NULL));
+ if (!fit_image_verify_with_data(fit, node, src, length))
+ return -EPERM;
+ puts("OK\n");
+ }
-#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
- board_fit_image_post_process(&src, &length);
-#endif
+ if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS))
+ board_fit_image_post_process(&src, &length);
if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
size = length;
return 0;
}
+static bool os_takes_devicetree(uint8_t os)
+{
+ switch (os) {
+ case IH_OS_U_BOOT:
+ return true;
+ case IH_OS_LINUX:
+ return IS_ENABLED(CONFIG_SPL_OS_BOOT);
+ default:
+ return false;
+ }
+}
+
static int spl_fit_append_fdt(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector,
- void *fit, int images, ulong base_offset)
+ const struct spl_fit_info *ctx)
{
struct spl_image_info image_info;
int node, ret = 0, index = 0;
image_info.load_addr = spl_image->load_addr + spl_image->size;
/* Figure out which device tree the board wants to use */
- node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, index++);
+ node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index++);
if (node < 0) {
debug("%s: cannot find FDT node\n", __func__);
else
return node;
} else {
- ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ ret = spl_load_fit_image(info, sector, ctx, node,
&image_info);
if (ret < 0)
return ret;
/* Make the load-address of the FDT available for the SPL framework */
spl_image->fdt_addr = (void *)image_info.load_addr;
-#if !CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
+ if (CONFIG_IS_ENABLED(FIT_IMAGE_TINY))
+ return 0;
+
if (CONFIG_IS_ENABLED(LOAD_FIT_APPLY_OVERLAY)) {
void *tmpbuffer = NULL;
for (; ; index++) {
- node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP,
- index);
+ node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index);
if (node == -E2BIG) {
debug("%s: No additional FDT node\n", __func__);
break;
__func__);
}
image_info.load_addr = (ulong)tmpbuffer;
- ret = spl_load_fit_image(info, sector, fit, base_offset,
+ ret = spl_load_fit_image(info, sector, ctx,
node, &image_info);
if (ret < 0)
break;
(void *)image_info.load_addr);
if (ret) {
pr_err("failed to apply DT overlay %s\n",
- fit_get_name(fit, node, NULL));
+ fit_get_name(ctx->fit, node, NULL));
break;
}
debug("%s: DT overlay %s applied\n", __func__,
- fit_get_name(fit, node, NULL));
+ fit_get_name(ctx->fit, node, NULL));
}
free(tmpbuffer);
if (ret)
ret = fdt_shrink_to_minimum(spl_image->fdt_addr, 8192);
if (ret < 0)
return ret;
-#endif
return ret;
}
-static int spl_fit_record_loadable(const void *fit, int images, int index,
+static int spl_fit_record_loadable(const struct spl_fit_info *ctx, int index,
void *blob, struct spl_image_info *image)
{
int ret = 0;
-#if !CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
const char *name;
int node;
- ret = spl_fit_get_image_name(fit, images, "loadables",
- index, &name);
+ if (CONFIG_IS_ENABLED(FIT_IMAGE_TINY))
+ return 0;
+
+ ret = spl_fit_get_image_name(ctx, "loadables", index, &name);
if (ret < 0)
return ret;
- node = spl_fit_get_image_node(fit, images, "loadables", index);
+ node = spl_fit_get_image_node(ctx, "loadables", index);
ret = fdt_record_loadable(blob, index, name, image->load_addr,
image->size, image->entry_point,
- fdt_getprop(fit, node, "type", NULL),
- fdt_getprop(fit, node, "os", NULL));
-#endif
+ fdt_getprop(ctx->fit, node, "type", NULL),
+ fdt_getprop(ctx->fit, node, "os", NULL));
return ret;
}
static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os)
{
-#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY) && !defined(CONFIG_SPL_OS_BOOT)
- const char *name = fdt_getprop(fit, noffset, FIT_OS_PROP, NULL);
+ if (!CONFIG_IS_ENABLED(FIT_IMAGE_TINY) || CONFIG_IS_ENABLED(OS_BOOT))
+ return fit_image_get_os(fit, noffset, os);
+ const char *name = fdt_getprop(fit, noffset, FIT_OS_PROP, NULL);
if (!name)
return -ENOENT;
*os = IH_OS_INVALID;
return 0;
-#else
- return fit_image_get_os(fit, noffset, os);
-#endif
}
/*
return false;
}
-int spl_load_simple_fit(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector, void *fit)
+static int spl_simple_fit_read(struct spl_fit_info *ctx,
+ struct spl_load_info *info, ulong sector,
+ const void *fit_header)
{
+ unsigned long count, size;
int sectors;
- ulong size, hsize;
- unsigned long count;
- struct spl_image_info image_info;
- int node = -1;
- int images, ret;
- int base_offset;
- int index = 0;
- int firmware_node;
+ void *buf;
/*
* For FIT with external data, figure out where the external images
* start. This is the base for the data-offset properties in each
* image.
*/
- size = fdt_totalsize(fit);
- size = (size + 3) & ~3;
+ size = ALIGN(fdt_totalsize(fit_header), 4);
size = board_spl_fit_size_align(size);
- base_offset = (size + 3) & ~3;
+ ctx->ext_data_offset = ALIGN(size, 4);
/*
* So far we only have one block of data from the FIT. Read the entire
* For FIT with external data, data is not loaded in this step.
*/
sectors = get_aligned_image_size(info, size, 0);
- hsize = sectors * info->bl_len;
- fit = spl_get_fit_load_buffer(hsize);
- count = info->read(info, sector, sectors, fit);
+ buf = spl_get_fit_load_buffer(sectors * info->bl_len);
+
+ count = info->read(info, sector, sectors, buf);
+ ctx->fit = buf;
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
- sector, sectors, fit, count, size);
+ sector, sectors, buf, count, size);
- if (count == 0)
- return -EIO;
+ return (count == 0) ? -EIO : 0;
+}
- /* skip further processing if requested to enable load-only use cases */
- if (spl_load_simple_fit_skip_processing())
- return 0;
+static int spl_simple_fit_parse(struct spl_fit_info *ctx)
+{
+ /* Find the correct subnode under "/configurations" */
+ ctx->conf_node = fit_find_config_node(ctx->fit);
+ if (ctx->conf_node < 0)
+ return -EINVAL;
if (IS_ENABLED(CONFIG_SPL_FIT_SIGNATURE)) {
- int conf_offset = fit_find_config_node(fit);
-
printf("## Checking hash(es) for config %s ... ",
- fit_get_name(fit, conf_offset, NULL));
- if (fit_config_verify(fit, conf_offset))
+ fit_get_name(ctx->fit, ctx->conf_node, NULL));
+ if (fit_config_verify(ctx->fit, ctx->conf_node))
return -EPERM;
puts("OK\n");
}
/* find the node holding the images information */
- images = fdt_path_offset(fit, FIT_IMAGES_PATH);
- if (images < 0) {
- debug("%s: Cannot find /images node: %d\n", __func__, images);
- return -1;
+ ctx->images_node = fdt_path_offset(ctx->fit, FIT_IMAGES_PATH);
+ if (ctx->images_node < 0) {
+ debug("%s: Cannot find /images node: %d\n", __func__,
+ ctx->images_node);
+ return -EINVAL;
}
+ return 0;
+}
+
+int spl_load_simple_fit(struct spl_image_info *spl_image,
+ struct spl_load_info *info, ulong sector, void *fit)
+{
+ struct spl_image_info image_info;
+ struct spl_fit_info ctx;
+ int node = -1;
+ int ret;
+ int index = 0;
+ int firmware_node;
+
+ ret = spl_simple_fit_read(&ctx, info, sector, fit);
+ if (ret < 0)
+ return ret;
+
+ /* skip further processing if requested to enable load-only use cases */
+ if (spl_load_simple_fit_skip_processing())
+ return 0;
+
+ ret = spl_simple_fit_parse(&ctx);
+ if (ret < 0)
+ return ret;
+
#ifdef CONFIG_SPL_FPGA
- node = spl_fit_get_image_node(fit, images, "fpga", 0);
+ node = spl_fit_get_image_node(&ctx, "fpga", 0);
if (node >= 0) {
/* Load the image and set up the spl_image structure */
- ret = spl_load_fit_image(info, sector, fit, base_offset, node,
- spl_image);
+ ret = spl_load_fit_image(info, sector, &ctx, node, spl_image);
if (ret) {
printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
return ret;
* - fall back to using the first 'loadables' entry
*/
if (node < 0)
- node = spl_fit_get_image_node(fit, images, FIT_FIRMWARE_PROP,
- 0);
-#ifdef CONFIG_SPL_OS_BOOT
- if (node < 0)
- node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
-#endif
+ node = spl_fit_get_image_node(&ctx, FIT_FIRMWARE_PROP, 0);
+
+ if (node < 0 && IS_ENABLED(CONFIG_SPL_OS_BOOT))
+ node = spl_fit_get_image_node(&ctx, FIT_KERNEL_PROP, 0);
+
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
- node = spl_fit_get_image_node(fit, images, "loadables", 0);
+ node = spl_fit_get_image_node(&ctx, "loadables", 0);
/*
* If we pick the U-Boot image from "loadables", start at
* the second image when later loading additional images.
}
/* Load the image and set up the spl_image structure */
- ret = spl_load_fit_image(info, sector, fit, base_offset, node,
- spl_image);
+ ret = spl_load_fit_image(info, sector, &ctx, node, spl_image);
if (ret)
return ret;
* For backward compatibility, we treat the first node that is
* as a U-Boot image, if no OS-type has been declared.
*/
- if (!spl_fit_image_get_os(fit, node, &spl_image->os))
+ if (!spl_fit_image_get_os(ctx.fit, node, &spl_image->os))
debug("Image OS is %s\n", genimg_get_os_name(spl_image->os));
-#if !defined(CONFIG_SPL_OS_BOOT)
- else
+ else if (!IS_ENABLED(CONFIG_SPL_OS_BOOT))
spl_image->os = IH_OS_U_BOOT;
-#endif
/*
* Booting a next-stage U-Boot may require us to append the FDT.
* We allow this to fail, as the U-Boot image might embed its FDT.
*/
- if (spl_image->os == IH_OS_U_BOOT) {
- ret = spl_fit_append_fdt(spl_image, info, sector, fit,
- images, base_offset);
- if (!IS_ENABLED(CONFIG_OF_EMBED) && ret < 0)
+ if (os_takes_devicetree(spl_image->os)) {
+ ret = spl_fit_append_fdt(spl_image, info, sector, &ctx);
+ if (ret < 0 && spl_image->os != IH_OS_U_BOOT)
return ret;
}
for (; ; index++) {
uint8_t os_type = IH_OS_INVALID;
- node = spl_fit_get_image_node(fit, images, "loadables", index);
+ node = spl_fit_get_image_node(&ctx, "loadables", index);
if (node < 0)
break;
if (firmware_node == node)
continue;
- ret = spl_load_fit_image(info, sector, fit, base_offset, node,
- &image_info);
+ ret = spl_load_fit_image(info, sector, &ctx, node, &image_info);
if (ret < 0) {
printf("%s: can't load image loadables index %d (ret = %d)\n",
__func__, index, ret);
return ret;
}
- if (!spl_fit_image_get_os(fit, node, &os_type))
+ if (!spl_fit_image_get_os(ctx.fit, node, &os_type))
debug("Loadable is %s\n", genimg_get_os_name(os_type));
- if (os_type == IH_OS_U_BOOT) {
- spl_fit_append_fdt(&image_info, info, sector,
- fit, images, base_offset);
+ if (os_takes_devicetree(os_type)) {
+ spl_fit_append_fdt(&image_info, info, sector, &ctx);
spl_image->fdt_addr = image_info.fdt_addr;
}
/* Record our loadables into the FDT */
if (spl_image->fdt_addr)
- spl_fit_record_loadable(fit, images, index,
+ spl_fit_record_loadable(&ctx, index,
spl_image->fdt_addr,
&image_info);
}
spl_image->flags |= SPL_FIT_FOUND;
-#ifdef CONFIG_IMX_HAB
- board_spl_fit_post_load((ulong)fit, size);
-#endif
+ if (IS_ENABLED(CONFIG_IMX_HAB))
+ board_spl_fit_post_load(ctx.fit);
return 0;
}
#include <hang.h>
#include <image.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/smp.h>
#include <opensbi.h>
#include <linux/libfdt.h>
#include <spi_flash.h>
#include <errno.h>
#include <spl.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <spi_flash.h>
#include <splash.h>
#include <usb.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
return -ENODEV;
}
- return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr);
+ return spi_flash_read(sf, offset, read_size, (void *)(uintptr_t)bmp_load_addr);
}
#else
static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
if (res < 0)
return res;
- bmp_hdr = (struct bmp_header *)bmp_load_addr;
+ bmp_hdr = (struct bmp_header *)(uintptr_t)bmp_load_addr;
bmp_size = le32_to_cpu(bmp_hdr->file_size);
if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
if (res < 0)
return res;
- res = fit_check_format(fit_header);
- if (!res) {
+ res = fit_check_format(fit_header, IMAGE_SIZE_INVAL);
+ if (res) {
debug("Could not find valid FIT image\n");
- return -EINVAL;
+ return res;
}
/* Get the splash image node */
#include <serial.h>
#include <splash.h>
#include <i2c.h>
-
+#include <asm/global_data.h>
#include <dm/device-internal.h>
DECLARE_GLOBAL_DATA_PTR;
struct stdio_dev *stdio_devices[] = { NULL, NULL, NULL };
char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
+int stdio_file_to_flags(const int file)
+{
+ switch (file) {
+ case stdin:
+ return DEV_FLAGS_INPUT;
+ case stdout:
+ case stderr:
+ return DEV_FLAGS_OUTPUT;
+ default:
+ return -EINVAL;
+ }
+}
+
+#if CONFIG_IS_ENABLED(SYS_DEVICE_NULLDEV)
static void nulldev_putc(struct stdio_dev *dev, const char c)
{
/* nulldev is empty! */
return 0;
}
+static void nulldev_register(void)
+{
+ struct stdio_dev dev;
+
+ memset(&dev, '\0', sizeof(dev));
+
+ strcpy(dev.name, "nulldev");
+ dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
+ dev.putc = nulldev_putc;
+ dev.puts = nulldev_puts;
+ dev.getc = nulldev_input;
+ dev.tstc = nulldev_input;
+
+ stdio_register(&dev);
+}
+#else
+static inline void nulldev_register(void) {}
+#endif /* SYS_DEVICE_NULLDEV */
+
static void stdio_serial_putc(struct stdio_dev *dev, const char c)
{
serial_putc(c);
dev.tstc = stdio_serial_tstc;
stdio_register (&dev);
- if (CONFIG_IS_ENABLED(SYS_DEVICE_NULLDEV)) {
- memset(&dev, '\0', sizeof(dev));
-
- strcpy(dev.name, "nulldev");
- dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
- dev.putc = nulldev_putc;
- dev.puts = nulldev_puts;
- dev.getc = nulldev_input;
- dev.tstc = nulldev_input;
-
- stdio_register(&dev);
- }
+ nulldev_register();
}
/**************************************************************************
return 0;
}
-int stdio_deregister(const char *devname, int force)
-{
- struct stdio_dev *dev;
-
- dev = stdio_get_by_name(devname);
- if (!dev) /* device not found */
- return -ENODEV;
-
- return stdio_deregister_dev(dev, force);
-}
-
int stdio_init_tables(void)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
got_update_file:
fit = map_sysmem(addr, 0);
- if (!fit_check_format((void *)fit)) {
+ if (fit_check_format((void *)fit, IMAGE_SIZE_INVAL)) {
printf("Bad FIT format of the update file, aborting "
"auto-update\n");
return 1;
if (!fit)
return -EINVAL;
- if (!fit_check_format((void *)fit)) {
+ if (fit_check_format((void *)fit, IMAGE_SIZE_INVAL)) {
printf("Bad FIT format of the update file, aborting auto-update\n");
return -EINVAL;
}
if (dev) {
usb_kbd_dev = (struct usb_device *)dev->priv;
data = usb_kbd_dev->privptr;
- if (stdio_deregister_dev(dev, force) != 0)
- return 1;
#if CONFIG_IS_ENABLED(CONSOLE_MUX)
- if (iomux_doenv(stdin, env_get("stdin")) != 0)
+ if (iomux_replace_device(stdin, DEVNAME, force ? "nulldev" : ""))
return 1;
#endif
+ if (stdio_deregister_dev(dev, force) != 0)
+ return 1;
#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
destroy_int_queue(usb_kbd_dev, data->intq);
#endif
goto err;
}
data = udev->privptr;
- if (stdio_deregister_dev(sdev, true)) {
- ret = -EPERM;
- goto err;
- }
#if CONFIG_IS_ENABLED(CONSOLE_MUX)
- if (iomux_doenv(stdin, env_get("stdin"))) {
+ if (iomux_replace_device(stdin, DEVNAME, "nulldev")) {
ret = -ENOLINK;
goto err;
}
#endif
+ if (stdio_deregister_dev(sdev, true)) {
+ ret = -EPERM;
+ goto err;
+ }
#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
destroy_int_queue(udev, data->intq);
#endif
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_ENV_ADDR=0xFE080000
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_SATA=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8544DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF70000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_RTL8139=y
-CONFIG_TSEC_ENET=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8572DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SCSI_AHCI=y
-CONFIG_SYS_FSL_DDR2=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8572DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SCSI_AHCI=y
-CONFIG_SYS_FSL_DDR2=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8610HPCD=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xeff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8641HPCN=y
-CONFIG_PHYS_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=8
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xeff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8641HPCN=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=8
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MIGOR=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 root=1f01"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xA0020000
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_ETH_SUPPORT=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PHANDLE_CHECK_SEQ=y
CONFIG_K3_AVS0=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX28=y
-CONFIG_SYS_TEXT_BASE=0x40002000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x120000
-CONFIG_SPL_TEXT_BASE=0x00001000
-CONFIG_TARGET_APX4DEVKIT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x180000
-CONFIG_BOOTDELAY=1
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MXS_GPIO=y
-CONFIG_MMC_MXS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+CONFIG_MMC_PWRSEQ=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+CONFIG_MMC_PWRSEQ=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+CONFIG_MMC_PWRSEQ=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+CONFIG_MMC_PWRSEQ=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+CONFIG_MMC_PWRSEQ=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_TARGET_DB_88F6281_BP=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP"
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281"
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_DM_ETH=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
-CONFIG_LZO=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_TARGET_DB_88F6281_BP=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP"
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281-spi"
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_DM_ETH=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
-CONFIG_LZO=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_I2C is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_FS_LOADER=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_REMOTEPROC_TI_K3_DSP=y
CONFIG_ESM_PMIC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xebf40000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_KM_DEF_NETDEV="eth2"
+CONFIG_KM_IVM_BUS=2
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
+CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
+CONFIG_MPC85xx=y
+CONFIG_TARGET_KMCENT2=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND_TRIMFFS=y
+# CONFIG_CMD_SATA is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
+CONFIG_MP=y
+CONFIG_CMD_CRAMFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=ffa000000.flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:128k(RCW),128k(fman),128k(QE),128k(zarlink),512k(res),62m(ubi0),128k(envred),128k(env),768k(u-boot);ffa000000.flash:-(ubi1);"
+CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_ADDR=0xebf20000
+CONFIG_ENV_ADDR_REDUND=0xebf00000
+CONFIG_DM=y
+# CONFIG_FSL_SATA is not set
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_FSL_CAAM=y
+CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_FMAN_ENET=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_FSL_ESPI=y
+CONFIG_WATCHDOG=y
+CONFIG_FS_CRAMFS=y
+CONFIG_BCH=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZO=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BAT3_DCACHE_GUARDED=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="PAXE"
CONFIG_BAT5_BASE=0xA0000000
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
CONFIG_DM_SPI_FLASH=y
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_DSA=y
+CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
CONFIG_DM=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
+CONFIG_REGEX=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_I2C is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_DSA=y
+CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_DSA=y
+CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_DSA=y
+CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_DSA=y
+CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_SPL=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_SPL=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_I2C is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_AHCI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_EMU=y
-CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
-CONFIG_IDENT_STRING=" LS2080A-EMU"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU"
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_MP=y
-# CONFIG_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_SIMU=y
-CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
-CONFIG_IDENT_STRING=" LS2080A-SIMU"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SIMU"
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_MP=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
+CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_FASTBOOT_BUF_SIZE=0x1e00000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_FASTBOOT_BUF_SIZE=0x1E00000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_MX35PDK=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0080000
-CONFIG_ENV_ADDR_REDUND=0xA00A0000
-CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_MII=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0xB6000000
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NOKIA_RX51=y
+# CONFIG_SYS_MALLOC_F is not set
# CONFIG_FIT is not set
CONFIG_BOOTDELAY=30
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_MTD=y
CONFIG_CMD_ONENAND=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_DM=y
+# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_I2C=y
CONFIG_TWL4030_LED=y
+CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
+# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_CONS_INDEX=3
CONFIG_MESON_G12A=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_IDENT_STRING=" odroid-c4"
+CONFIG_IDENT_STRING=" odroid-c4/hc4"
CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-c4"
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_MESON_G12A=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_IDENT_STRING=" odroid-n2"
+CONFIG_IDENT_STRING=" odroid-n2/n2_plus"
CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2"
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_CLK_IMX8MP=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_I2C is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_FASTBOOT_BUF_SIZE=0x4000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
# CONFIG_INPUT is not set
CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x0FFC0000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_TARGET_R7780MP=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xA0040000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_BEACON_RZG2N=y
+# CONFIG_SPL is not set
+CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit"
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_DEFAULT_FDT_FILE="r8a774b1-beacon-rzg2n-kit.dtb"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_BEACON_RZG2H=y
+# CONFIG_SPL is not set
+CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit"
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_DEFAULT_FDT_FILE="r8a774e1-beacon-rzg2h-kit.dtb"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_RENESAS_RAVB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_RCAR_GEN3=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_DMA=y
CONFIG_DFU_MMC=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_DMA=y
CONFIG_DFU_MMC=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_IPROC200=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_DMA=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_IPROC200=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
+CONFIG_DM_DMA=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_DEVRES=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
+CONFIG_DM_DMA=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_DEVRES=y
CONFIG_DM_BOOTCOUNT_RTC=y
CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y
CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
+CONFIG_DM_DMA=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_DEVRES=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_SPL_DM=y
+CONFIG_DM_DMA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x5ff80000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_SH_32BIT=y
-CONFIG_TARGET_SH7752EVB=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_MD5SUM=y
-# CONFIG_CMD_LOADB is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MMC=y
-CONFIG_SH_MMCIF=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_VITESSE=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x5ff80000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_TARGET_SH7753EVB=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_MD5SUM=y
-# CONFIG_CMD_LOADB is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MMC=y
-CONFIG_SH_MMCIF=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_VITESSE=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8ef80000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_SH_32BIT=y
-CONFIG_TARGET_SH7757LCR=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_MD5SUM=y
-# CONFIG_CMD_LOADB is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MMC=y
-CONFIG_SH_MMCIF=y
-CONFIG_BITBANGMII=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_SH7763RDP=y
-CONFIG_BOOTDELAY=-1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=1f01"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0020000
-CONFIG_ENV_ADDR_REDUND=0xA0040000
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_BITBANGMII=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_FASTBOOT_USB_DEV=1
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
+CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_FASTBOOT_USB_DEV=1
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
+CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
#include <part.h>
#include <uuid.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/unaligned.h>
#include <command.h>
#include <fdtdec.h>
kernel_comp_addr_r:
Optional. This is only required if user wants to boot Linux from a compressed
- Image(.gz, .bz2, .lzma, .lzo) using booti command. It represents the location
- in RAM where the compressed Image will be decompressed temporarily. Once the
- decompression is complete, decompressed data will be moved kernel_addr_r for
- booting.
+ Image(.gz, .bz2, .lzma, .lzo) using the booti command. It represents the
+ location in RAM where the compressed Image will be decompressed temporarily.
+ Once the decompression is complete, the decompressed data will be moved to
+ kernel_addr_r for booting.
kernel_comp_size:
Optional. This is only required if user wants to boot Linux from a compressed
The following OEM commands are supported (if enabled):
- ``oem format`` - this executes ``gpt write mmc %x $partitions``
+- ``oem partconf`` - this executes ``mmc partconf %x <arg> 0`` to configure eMMC
+ with <arg> = boot_ack boot_partition
+- ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC
Support for both eMMC and NAND devices is included.
^^^^^^^^^^^^^^
This CPU has the SH4AL-DSP core.
-Renesas SH7780
-^^^^^^^^^^^^^^
-This CPU has the SH4A core.
-
Supported Boards
----------------
- NOR Flash
- Marubun PCMCIA
-Renesas R7780MP
-^^^^^^^^^^^^^^^
-Board specific code is in board/r7780mp
-To use this board, type "make r7780mp_config".
-Support devices are:
-
- - SCIF
- - DDR-SDRAM
- - NOR Flash
- - Compact Flash
- - ASIX ethernet
- - SH7780 PCI bridge
- - RTL8110 ethernet
-
In SuperH, S-record and binary of made u-boot work on the memory.
When u-boot is written in the flash, it is necessary to change the
address by using 'objcopy'::
intel/index
kontron/index
microchip/index
- renesas/index
rockchip/index
sifive/index
sipeed/index
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0+
-
-Renesas
-=======
-
-.. toctree::
- :maxdepth: 2
-
- sh7752evb
- sh7753evb
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0+
-
-R0P7752C00000RZ board
-=====================
-
-This board specification
-------------------------
-
-The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
-
- - SH7752 (SH-4A)
- - DDR3-SDRAM 512MB
- - SPI ROM 8MB
- - Gigabit Ethernet controllers
- - eMMC 4GB
-
-
-Configuration for This board
-----------------------------
-
-You can select the configuration as follows:
-
- - make sh7752evb_config
-
-
-This board specific command
----------------------------
-
-This board has the following its specific command:
-
-write_mac:
- You can write MAC address to SPI ROM.
-
-Usage 1: Write MAC address
-
-.. code-block:: none
-
- write_mac [GETHERC ch0] [GETHERC ch1]
-
- For example:
- => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
-
-* We have to input the command as a single line (without carriage return)
-* We have to reset after input the command.
-
-Usage 2: Show current data
-
-.. code-block:: none
-
- write_mac
-
- For example:
- => write_mac
- GETHERC ch0 = 74:90:50:00:33:9e
- GETHERC ch1 = 74:90:50:00:33:9f
-
-
-Update SPI ROM
---------------
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
-
-.. code-block:: none
-
- => sf probe 0
- SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
-
-3. Erase SPI ROM.
-
-.. code-block:: none
-
- => sf erase 0 80000
-
-4. Write u-boot image to SPI ROM.
-
-.. code-block:: none
-
- => sf write 0x48000000 0 80000
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0+
-
-SH7753 EVB board
-================
-
-This board specification
-------------------------
-
-The SH7753 EVB (board config name:sh7753evb) has the following device:
-
- - SH7753 (SH-4A)
- - DDR3-SDRAM 512MB
- - SPI ROM 8MB
- - Gigabit Ethernet controllers
- - eMMC 4GB
-
-
-Configuration for This board
-----------------------------
-
-You can select the configuration as follows:
-
- - make sh7753evb_config
-
-
-This board specific command
----------------------------
-
-This board has the following its specific command:
-
-write_mac:
- You can write MAC address to SPI ROM.
-
-Usage 1: Write MAC address
-
-.. code-block:: none
-
- write_mac [GETHERC ch0] [GETHERC ch1]
-
- For example:
- => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
-
-* We have to input the command as a single line (without carriage return)
-* We have to reset after input the command.
-
-Usage 2: Show current data
-
-.. code-block:: none
-
- write_mac
-
- For example:
- => write_mac
- GETHERC ch0 = 74:90:50:00:33:9e
- GETHERC ch1 = 74:90:50:00:33:9f
-
-
-Update SPI ROM
---------------
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
-
-.. code-block:: none
-
- => sf probe 0
- SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
-
-3. Erase SPI ROM.
-
-.. code-block:: none
-
- => sf erase 0 80000
-
-4. Write u-boot image to SPI ROM.
-
-.. code-block:: none
-
- => sf write 0x48000000 0 80000
master_doc = 'index'
# General information about the project.
-project = 'The Linux Kernel'
-copyright = 'The kernel development community'
-author = 'The kernel development community'
+project = 'Das U-Boot'
+copyright = 'The U-Boot development community'
+author = 'The U-Boot development community'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# The name of an image file (relative to this directory) to place at the top
# of the sidebar.
-#html_logo = None
+html_logo = '../tools/logos/u-boot_logo.svg'
# The name of an image file (within the static path) to use as favicon of the
# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
#html_search_scorer = 'scorer.js'
# Output file base name for HTML help builder.
-htmlhelp_basename = 'TheLinuxKerneldoc'
+htmlhelp_basename = 'TheUBootdoc'
# -- Options for LaTeX output ---------------------------------------------
# author, documentclass [howto, manual, or own class]).
# Sorted in alphabetical order
latex_documents = [
+ ('index', 'u-boot-hacker-manual.tex', 'U-Boot Hacker Manual',
+ 'The U-Boot development community', 'manual'),
]
# Add all other index files from Documentation/ subdirectories
break
if not has:
latex_documents.append((doc, fn + '.tex',
- 'Linux %s Documentation' % fn.capitalize(),
- 'The kernel development community',
+ 'U-Boot %s Documentation' % fn.capitalize(),
+ 'The U-Boot development community',
'manual'))
# The name of an image file (relative to this directory) to place at the top of
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
- (master_doc, 'thelinuxkernel', 'The Linux Kernel Documentation',
+ (master_doc, 'dasuboot', 'The U-Boot Documentation',
[author], 1)
]
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
- (master_doc, 'TheLinuxKernel', 'The Linux Kernel Documentation',
- author, 'TheLinuxKernel', 'One line description of project.',
+ (master_doc, 'DasUBoot', 'The U-Boot Documentation',
+ author, 'DasUBoot', 'One line description of project.',
'Miscellaneous'),
]
# multiple PDF files here actually tries to get the cross-referencing right
# *between* PDF files.
pdf_documents = [
- ('kernel-documentation', u'Kernel', u'Kernel', u'J. Random Bozo'),
+ ('uboot-documentation', u'U-Boot', u'U-Boot', u'J. Random Bozo'),
]
# kernel-doc extension configuration for running Sphinx directly (e.g. by Read
global_data
logging
menus
+ version
Debugging
---------
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2013 The Chromium OS Authors.
+
+Version information
+===================
+
+U-Boot releases are named by year and patch level, for example 2020.10 means the
+release that came out in October 2020. Release candidates are tagged every few
+weeks as the project heads to the next release. So 2020.10-rc1 was the first
+release candidate (RC), tagged soon after 2020.07 was released.
+
+See https://www.denx.de/wiki/view/U-Boot/ReleaseCycle for full details.
+
+Within the build system, various Makefile variables are created, making use of
+VERSION, PATCHLEVEL and EXTRAVERSION defined at the top of 'Makefile'. There is
+also SUBLEVEL available for downstream use. See also CONFIG_IDENT_STRING.
+
+Some variables end up in a generated header file at
+include/generated/version_autogenerated.h and can be accessed from C source by
+including <version.h>
+
+The following are available:
+
+ UBOOTRELEASE (Makefile)
+ Full release version as a string. If this is not a tagged release, it also
+ includes the number of commits since the last tag as well as the the git
+ hash. If there are uncommitted changes a '-dirty' suffix is added too.
+
+ This is written by scripts/setlocalversion (maintained by Linux) to
+ include/config/uboot.release and ends up in the UBOOTRELEASE Makefile
+ variable.
+
+ Examples::
+
+ 2020.10-rc3
+ 2021.01-rc5-00248-g60dd854f3ba-dirty
+
+ PLAIN_VERSION (string #define)
+ This is UBOOTRELEASE but available in C source.
+
+ Examples::
+
+ 2020.10
+ 2021.01-rc5-00248-g60dd854f3ba-dirty
+
+ UBOOTVERSION (Makefile)
+ This holds just the first three components of UBOOTRELEASE (i.e. not the
+ git hash, etc.)
+
+ Examples::
+
+ 2020.10
+ 2021.01-rc5
+
+ U_BOOT_VERSION (string #define)
+ "U-Boot " followed by UBOOTRELEASE, for example::
+
+ U-Boot 2020.10
+ U-Boot 2021.01-rc5
+
+ This is used as part of the banner string when U-Boot starts.
+
+ U_BOOT_VERSION_STRING (string #define)
+ U_BOOT_VERSION followed by build-time information
+ and CONFIG_IDENT_STRING.
+
+ Examples::
+
+ U-Boot 2020.10 (Jan 06 2021 - 08:50:36 -0700)
+ U-Boot 2021.01-rc5-00248-g60dd854f3ba-dirty (Jan 06 2021 - 08:50:36 -0700) for spring
+
+ U_BOOT_VERSION_NUM (integer #define)
+ Release year, e.g. 2021 for release 2021.01. Note
+ this is an integer, not a string.
+
+ U_BOOT_VERSION_NUM_PATCH (integer #define)
+ Patch number, e.g. 1 for release 2020.01. Note
+ this is an integer, not a string.
+
+Build date/time is also included. See the generated file
+include/generated/timestamp_autogenerated.h for the available
+fields. For example::
+
+ #define U_BOOT_DATE "Jan 06 2021" (US format only)
+ #define U_BOOT_TIME "08:50:36" (24-hour clock)
+ #define U_BOOT_TZ "-0700" (Time zone in hours)
+ #define U_BOOT_DMI_DATE "01/06/2021" (US format only)
+ #define U_BOOT_BUILD_DATE 0x20210106 (hex yyyymmdd format)
+ #define U_BOOT_EPOCH 1609948236
+
+The Epoch is the number of seconds since midnight on 1/1/70. You can convert
+this to a time with::
+
+ $ date -u -d @1609948236
+ Wed 06 Jan 2021 03:50:36 PM UTC
+ $ date -d 'Wed 06 Jan 2021 03:50:36 PM UTC' +%s
+ 1609948236
+
+Every time you build U-Boot this will update based on the time
+on your build machine. See 'Reproducible builds' if you want to
+avoid that.
--- /dev/null
+ADC attached resistor ladder buttons
+------------------------------------
+
+Required properties:
+ - compatible: "adc-keys"
+ - io-channels: Phandle to an ADC channel
+ - io-channel-names = "buttons";
+ - keyup-threshold-microvolt: Voltage above or equal to which all the keys are
+ considered up.
+
+Optional properties:
+ - poll-interval: Poll interval time in milliseconds
+ - autorepeat: Boolean, Enable auto repeat feature of Linux input
+ subsystem.
+
+Each button (key) is represented as a sub-node of "adc-keys":
+
+Required subnode-properties:
+ - label: Descriptive name of the key.
+ - linux,code: Keycode to emit.
+ - press-threshold-microvolt: voltage above or equal to which this key is
+ considered pressed.
+
+No two values of press-threshold-microvolt may be the same.
+All values of press-threshold-microvolt must be less than
+keyup-threshold-microvolt.
+
+Example:
+
+#include <dt-bindings/input/input.h>
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&lradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <2000000>;
+
+ button-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <1500000>;
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <1000000>;
+ };
+
+ button-enter {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ press-threshold-microvolt = <500000>;
+ };
+ };
+
++--------------------------------+------------------------+
+| 2.000.000 <= value | no key pressed |
++--------------------------------+------------------------+
+| 1.500.000 <= value < 2.000.000 | KEY_VOLUMEUP pressed |
++--------------------------------+------------------------+
+| 1.000.000 <= value < 1.500.000 | KEY_VOLUMEDOWN pressed |
++--------------------------------+------------------------+
+| 500.000 <= value < 1.000.000 | KEY_ENTER pressed |
++--------------------------------+------------------------+
+| value < 500.000 | no key pressed |
++--------------------------------+------------------------+
Optional properties:
--------------------
-- lockstep-mode: Configuration Mode for the Dual R5F cores within the R5F
+- ti,cluster-mode: Configuration Mode for the Dual R5F cores within the R5F
cluster. Should be either a value of 1 (LockStep mode) or
0 (Split mode), default is LockStep mode if omitted.
--------------------
The following properties are optional properties for each of the R5F cores:
-- atcm-enable: R5F core configuration mode dictating if ATCM should be
+- ti,atcm-enable: R5F core configuration mode dictating if ATCM should be
enabled. Should be either a value of 1 (enabled) or
0 (disabled), default is disabled if omitted. R5F view
- of ATCM dictated by loczrama property.
-- btcm-enable: R5F core configuration mode dictating if BTCM should be
+ of ATCM dictated by ti,loczrama property.
+- ti,btcm-enable: R5F core configuration mode dictating if BTCM should be
enabled. Should be either a value of 1 (enabled) or
0 (disabled), default is enabled if omitted. R5F view
- of BTCM dictated by loczrama property.
-- loczrama: R5F core configuration mode dictating which TCM should
+ of BTCM dictated by ti,loczrama property.
+- ti,loczrama: R5F core configuration mode dictating which TCM should
appear at address 0 (from core's view). Should be either
a value of 1 (ATCM at 0x0) or 0 (BTCM at 0x0), default
value is 1 if omitted.
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,am654-r5fss";
power-domains = <&k3_pds 129>;
- lockstep-mode = <1>;
+ ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
ti,sci-dev-id = <159>;
ti,sci-proc-ids = <0x01 0xFF>;
resets = <&k3_reset 159 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
};
mcu_r5f1: r5f@41400000 {
ti,sci-dev-id = <245>;
ti,sci-proc-ids = <0x02 0xFF>;
resets = <&k3_reset 245 1>;
- atcm-enable = <1>;
- btcm-enable = <1>;
- loczrama = <1>;
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
};
};
};
Optional properties:
- vbus-supply : reference to the VBUS regulator;
+ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
+ bit1 for u3port1, ... etc;
+ - mediatek,u2p-dis-msk : mask to disable u2ports, bit0 for u2port0,
+ bit1 for u2port1, ... etc;
Example:
xhci: usb@1a0c0000 {
2. If plat_auto is non-zero, then the platform data space
is allocated. This is only useful for device tree operation, since
- otherwise you would have to specific the platform data in the
+ otherwise you would have to specify the platform data in the
U_BOOT_DRVINFO() declaration. The space is allocated for the device and
zeroed. It will be accessible as dev->plat.
be dynamically allocated, and thus needs to be deallocated during the
remove() method, either:
- - if the plat_auto is non-zero, the deallocation
- happens automatically within the driver model core; or
+ - if the plat_auto is non-zero, the deallocation happens automatically
+ within the driver model core in the unbind stage; or
- when plat_auto is 0, both the allocation (in probe()
or preferably of_to_plat()) and the deallocation in remove()
the device does not exist and its memory has be deallocated.
+Special cases for removal
+-------------------------
+
+Some devices need to do clean-up before the OS is called. For example, a USB
+driver may want to stop the bus. This can be done in the remove() method.
+Some special flags are used to determine whether to remove the device:
+
+ DM_FLAG_OS_PREPARE - indicates that the device needs to get ready for OS
+ boot. The device will be removed just before the OS is booted
+ DM_REMOVE_ACTIVE_DMA - indicates that the device uses DMA. This is
+ effectively the same as DM_FLAG_OS_PREPARE, so the device is removed
+ before the OS is booted
+ DM_FLAG_VITAL - indicates that the device is 'vital' to the operation of
+ other devices. It is possible to remove this device after all regular
+ devices are removed. This is useful e.g. for a clock, which need to
+ be active during the device-removal phase.
+
+The dm_remove_devices_flags() function can be used to remove devices based on
+their driver flags.
+
Data Structures
---------------
Here is a suggested approach for converting your I2C driver over to driver
model. Please feel free to update this file with your ideas and suggestions.
-- #ifdef out all your own I2C driver code (#ifndef CONFIG_DM_I2C)
+- #ifdef out all your own I2C driver code (#if !CONFIG_IS_ENABLED(DM_I2C))
- Define CONFIG_DM_I2C for your board, vendor or architecture
- If the board does not already use driver model, you need CONFIG_DM also
- Your board should then build, but will not work fully since there will be
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+:
+
+booti command
+=============
+
+Synopsis
+--------
+
+::
+
+ booti [<addr> [<initrd>[:<size>]] [<fdt>]]
+
+Description
+-----------
+
+The booti command is used to boot a Linux kernel in flat or compressed
+'Image' format. Which compressed formats are supported is configurable.
+
+addr
+ address of kernel image, defaults to CONFIG_SYS_LOAD_ADDR.
+
+initrd
+ address of the initial RAM disk. Use '-' to boot a kernel with a device
+ tree but without an initial RAM disk.
+
+size
+ size of the initial RAM disk. This parameter must be specified for raw
+ initial RAM disks.
+
+fdt
+ address of the device tree.
+
+To support compressed Image files the following environment variables must be
+set:
+
+kernel_comp_addr_r
+ start of memory area used for decompression
+
+kernel_comp_size
+ size of the compressed file. The value has to be at least the size of
+ loaded image for decompression to succeed. For the booti command the
+ maximum decompressed size is 10 times this value.
+
+Example
+-------
+
+This is the boot log of an Odroid C2 board:
+
+::
+
+ => load mmc 0:1 $fdt_addr_r dtb-5.10.0-3-arm64
+ 27530 bytes read in 7 ms (3.7 MiB/s)
+ => load mmc 0:1 $kernel_addr_r vmlinuz-5.10.0-3-arm64
+ 26990448 bytes read in 1175 ms (21.9 MiB/s)
+ => load mmc 0:1 $ramdisk_addr_r initrd.img-5.10.0-3-arm64
+ 27421776 bytes read in 1209 ms (21.6 MiB/s)
+ => booti $kernel_addr_r $ramdisk_addr_r:$filesize $fdt_addr_r
+ Moving Image from 0x8080000 to 0x8200000, end=9c60000
+ ## Flattened Device Tree blob at 08008000
+ Booting using the fdt blob at 0x8008000
+ Loading Ramdisk to 7a52a000, end 7bf50c50 ... OK
+ Loading Device Tree to 000000007a520000, end 000000007a529b89 ... OK
+
+ Starting kernel ...
+
+The kernel can be compressed with gzip:
+
+.. code-block:: bash
+
+ cd /boot
+ gzip -k vmlinuz-5.10.0-3-arm64
+
+Here is the boot log for the compressed kernel:
+
+::
+
+ => setenv kernel_comp_addr_r 0x50000000
+ => setenv kernel_comp_size 0x04000000
+ => load mmc 0:1 $fdt_addr_r dtb-5.10.0-3-arm64
+ 27530 bytes read in 6 ms (4.4 MiB/s)
+ => load mmc 0:1 $kernel_addr_r vmlinuz-5.10.0-3-arm64.gz
+ 9267730 bytes read in 402 ms (22 MiB/s)
+ => load mmc 0:1 $ramdisk_addr_r initrd.img-5.10.0-3-arm64
+ 27421776 bytes read in 1181 ms (22.1 MiB/s)
+ => booti $kernel_addr_r $ramdisk_addr_r:$filesize $fdt_addr_r
+ Uncompressing Kernel Image
+ Moving Image from 0x8080000 to 0x8200000, end=9c60000
+ ## Flattened Device Tree blob at 08008000
+ Booting using the fdt blob at 0x8008000
+ Loading Ramdisk to 7a52a000, end 7bf50c50 ... OK
+ Loading Device Tree to 000000007a520000, end 000000007a529b89 ... OK
+
+ Starting kernel ...
+
+Configuration
+-------------
+
+The booti command is only available if CONFIG_CMD_BOOTI=y.
+
+Which compression types are supported depends on:
+
+* CONFIG_BZIP2
+* CONFIG_GZIP
+* CONFIG_LZ4
+* CONFIG_LZMA
+* CONFIG_LZO
+* CONFIG_ZSTD
+
+Return value
+------------
+
+Normally this command does not return. If an error occurs, the return value $?
+is set to 1 (false). If the operating system returns to U-Boot, the system is
+reset.
pc = 0x56076dd1a0f9, pc_reloc = 0x540f9
resetting ...
-
-Return value
-------------
-
-The return value $? is always set to 0 (true).
base
bootefi
+ booti
bootmenu
button
conitrace
exit
false
for
+ load
loady
mbr
pstore
+ qfw
sbi
true
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+:
+
+load command
+============
+
+Synopsis
+--------
+
+::
+
+ load <interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]]
+
+Description
+-----------
+
+The load command is used to read a file from a filesystem into memory.
+
+The number of transferred bytes is saved in the environment variable filesize.
+The load address is saved in the environment variable fileaddr.
+
+interface
+ interface for accessing the block device (mmc, sata, scsi, usb, ....)
+
+dev
+ device number
+
+part
+ partition number, defaults to 0 (whole device)
+
+addr
+ load address, defaults to environment variable loadaddr or if loadaddr is
+ not set to configuration variable CONFIG_SYS_LOAD_ADDR
+
+filename
+ path to file, defaults to environment variable bootfile
+
+bytes
+ maximum number of bytes to load
+
+pos
+ number of bytes to skip
+
+addr, bytes, pos are hexadecimal numbers.
+
+Example
+-------
+
+::
+
+ => load mmc 0:1 ${kernel_addr_r} snp.efi
+ 149280 bytes read in 11 ms (12.9 MiB/s)
+ =>
+ => load mmc 0:1 ${kernel_addr_r} snp.efi 1000000
+ 149280 bytes read in 9 ms (15.8 MiB/s)
+ =>
+ => load mmc 0:1 ${kernel_addr_r} snp.efi 1000000 100
+ 149024 bytes read in 10 ms (14.2 MiB/s)
+ =>
+ => load mmc 0:1 ${kernel_addr_r} snp.efi 10
+ 16 bytes read in 1 ms (15.6 KiB/s)
+ =>
+
+Configuration
+-------------
+
+The load command is only available if CONFIG_CMD_FS_GENERIC=y.
+
+Return value
+------------
+
+The return value $? is set to 0 (true) if the file was successfully loaded
+even if the number of bytes is less then the specified length.
+
+If an error occurs, the return value $? is set to 1 (false).
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+qfw command
+===========
+
+Synopsis
+--------
+
+::
+
+ qfw list
+ qfw cpus
+ qfw load [kernel_addr [initrd_addr]]
+
+Description
+-----------
+
+The *qfw* command is used to retrieve information form the QEMU firmware.
+
+The *qfw list* sub-command displays the QEMU firmware files.
+
+The *qfw cpus* sub-command displays the available CPUs.
+
+The *qfw load* command is used to load a kernel and an initial RAM disk.
+
+kernel_addr
+ address to which the file specified by the -kernel parameter of QEMU shall
+ be loaded. Defaults to environment variable *loadaddr* and further to
+ the value of *CONFIG_LOADADDR*.
+
+initrd_addr
+ address to which the file specified by the -initrd parameter of QEMU shall
+ be loaded. Defaults to environment variable *ramdiskaddr* and further to
+ the value of *CONFIG_RAMDISK_ADDR*.
+
+Examples
+--------
+
+QEMU firmware files are listed via the *qfw list* command:
+
+::
+
+ => qfw list
+ etc/boot-fail-wait
+ etc/smbios/smbios-tables
+ etc/smbios/smbios-anchor
+ etc/e820
+ genroms/kvmvapic.bin
+ genroms/linuxboot.bin
+ etc/system-states
+ etc/acpi/tables
+ etc/table-loader
+ etc/tpm/log
+ etc/acpi/rsdp
+ bootorder
+
+The available CPUs can be shown via the *qfw cpus* command:
+
+::
+
+ => qfw cpu
+ 2 cpu(s) online
+
+The *-kernel* and *-initrd* parameters allow to specify a kernel and an
+initial RAM disk for QEMU:
+
+.. code-block:: bash
+
+ $ qemu-system-x86_64 -machine pc-i440fx-2.5 -bios u-boot.rom -m 1G \
+ -nographic -kernel vmlinuz -initrd initrd
+
+Now the kernel and the initial RAM disk can be loaded to the U-Boot memory via
+the *qfw load* command and booted thereafter.
+
+::
+
+ => qfw load ${kernel_addr_r} ${ramdisk_addr_r}
+ loading kernel to address 0000000001000000 size 5048f0 initrd 0000000004000000 size 3c94891
+ => zboot 1000000 5048f0 4000000 3c94891
+ Valid Boot Flag
+ Magic signature found
+ Linux kernel version 4.19.0-14-amd64 (debian-kernel@lists.debian.org) #1 SMP Debian 4.19.171-2 (2021-01-30)
+ Building boot_params at 0x00090000
+ Loading bzImage at address 100000 (5260160 bytes)
+
+Configuration
+-------------
+
+The qfw command is only available if CONFIG_CMD_QFW=y.
#include <linux/delay.h>
#include <linux/math64.h>
#include <linux/bitfield.h>
+#include <power/regulator.h>
#define MESON_SAR_ADC_REG0 0x00
#define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
static int meson_saradc_probe(struct udevice *dev)
{
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct meson_saradc_priv *priv = dev_get_priv(dev);
+ struct udevice *vref;
+ int vref_uv;
int ret;
ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
priv->active_channel = -1;
+ ret = device_get_supply_regulator(dev, "vref-supply", &vref);
+ if (ret) {
+ printf("can't get vref-supply: %d\n", ret);
+ return ret;
+ }
+
+ vref_uv = regulator_get_value(vref);
+ if (vref_uv < 0) {
+ printf("can't get vref-supply value: %d\n", vref_uv);
+ return vref_uv;
+ }
+
+ /* VDD supplied by common vref pin */
+ uc_pdata->vdd_supply = vref;
+ uc_pdata->vdd_microvolts = vref_uv;
+ uc_pdata->vss_microvolts = 0;
+
return 0;
}
* port from the libata of linux kernel
*/
+#include <common.h>
+#include <compiler.h>
#include <libata.h>
u64 ata_id_n_sectors(u16 *id)
#include <common.h>
#include <ahci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/of_access.h>
#include <dm.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <fis.h>
* BIOS in u-boot.
****************************************************************************/
#include <common.h>
+#include <compiler.h>
#include <bios_emul.h>
#include <errno.h>
#include <log.h>
#include <log.h>
#include <malloc.h>
#include <part.h>
+#include <asm/global_data.h>
#include <linux/ctype.h>
#include <linux/list.h>
#include <os.h>
#include <malloc.h>
#include <sandboxblockdev.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/errno.h>
#include <dm/device-internal.h>
#include <common.h>
#include <cpu_func.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
can provide access to board-specific buttons. Use of the device tree
for configuration is encouraged.
+config BUTTON_ADC
+ bool "Button adc"
+ depends on BUTTON
+ help
+ Enable support for buttons which are connected to Analog to Digital
+ Converter device. The ADC driver must use driver model. Buttons are
+ configured using the device tree.
+
config BUTTON_GPIO
bool "Button gpio"
depends on BUTTON
# Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
obj-$(CONFIG_BUTTON) += button-uclass.o
+obj-$(CONFIG_BUTTON_ADC) += button-adc.o
obj-$(CONFIG_BUTTON_GPIO) += button-gpio.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Author: Marek Szyprowski <m.szyprowski@samsung.com>
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <button.h>
+#include <log.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/of_access.h>
+#include <dm/uclass-internal.h>
+
+/**
+ * struct button_adc_priv - private data for button-adc driver.
+ *
+ * @adc: Analog to Digital Converter device to which button is connected.
+ * @channel: channel of the ADC device to probe the button state.
+ * @min: minimal uV value to consider button as pressed.
+ * @max: maximal uV value to consider button as pressed.
+ */
+struct button_adc_priv {
+ struct udevice *adc;
+ int channel;
+ int min;
+ int max;
+};
+
+static enum button_state_t button_adc_get_state(struct udevice *dev)
+{
+ struct button_adc_priv *priv = dev_get_priv(dev);
+ unsigned int val;
+ int ret, uV;
+
+ ret = adc_start_channel(priv->adc, priv->channel);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_data(priv->adc, priv->channel, &val);
+ if (ret)
+ return ret;
+
+ ret = adc_raw_to_uV(priv->adc, val, &uV);
+ if (ret)
+ return ret;
+
+ return (uV >= priv->min && uV < priv->max) ? BUTTON_ON : BUTTON_OFF;
+}
+
+static int button_adc_of_to_plat(struct udevice *dev)
+{
+ struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct button_adc_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ u32 treshold, up_treshold, t;
+ ofnode node;
+ int ret;
+
+ /* Ignore the top-level button node */
+ if (!uc_plat->label)
+ return 0;
+
+ ret = dev_read_phandle_with_args(dev->parent, "io-channels",
+ "#io-channel-cells", 0, 0, &args);
+ if (ret)
+ return ret;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_ADC, args.node, &priv->adc);
+ if (ret)
+ return ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev->parent),
+ "keyup-threshold-microvolt", &up_treshold);
+ if (ret)
+ return ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "press-threshold-microvolt",
+ &treshold);
+ if (ret)
+ return ret;
+
+ dev_for_each_subnode(node, dev->parent) {
+ ret = ofnode_read_u32(node, "press-threshold-microvolt", &t);
+ if (ret)
+ return ret;
+
+ if (t > treshold)
+ up_treshold = t;
+ }
+
+ priv->channel = args.args[0];
+ priv->min = treshold;
+ priv->max = up_treshold;
+
+ return ret;
+}
+
+static int button_adc_bind(struct udevice *parent)
+{
+ struct udevice *dev;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ struct button_uc_plat *uc_plat;
+ const char *label;
+
+ label = ofnode_read_string(node, "label");
+ if (!label) {
+ debug("%s: node %s has no label\n", __func__,
+ ofnode_get_name(node));
+ return -EINVAL;
+ }
+ ret = device_bind_driver_to_node(parent, "button_adc",
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret)
+ return ret;
+ uc_plat = dev_get_uclass_plat(dev);
+ uc_plat->label = label;
+ }
+
+ return 0;
+}
+
+static const struct button_ops button_adc_ops = {
+ .get_state = button_adc_get_state,
+};
+
+static const struct udevice_id button_adc_ids[] = {
+ { .compatible = "adc-keys" },
+ { }
+};
+
+U_BOOT_DRIVER(button_adc) = {
+ .name = "button_adc",
+ .id = UCLASS_BUTTON,
+ .of_match = button_adc_ids,
+ .ops = &button_adc_ops,
+ .priv_auto = sizeof(struct button_adc_priv),
+ .bind = button_adc_bind,
+ .of_to_plat = button_adc_of_to_plat,
+};
#include <cache.h>
#include <dm.h>
#include <hang.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/ofnode.h>
#include <linux/bitops.h>
#include <cache.h>
#include <dm.h>
#include <errno.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/util.h>
#include <linux/bitops.h>
+#include <asm/global_data.h>
#include <asm/arch/clock_manager.h>
#include <clk-uclass.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/scu_ast2500.h>
#include <dm/lists.h>
#include <dm/lists.h>
#include <linux/delay.h>
#include <asm/arch/scu_ast2600.h>
+#include <asm/global_data.h>
#include <dt-bindings/clock/ast2600-clock.h>
#include <dt-bindings/reset/ast2600-reset.h>
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/util.h>
*/
int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
{
- ofnode parent = dev_ofnode(dev);
- ofnode node;
+ const void *fdt = gd->fdt_blob;
+ int offset = dev_of_offset(dev);
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
- ofnode_for_each_subnode(node, parent) {
- if (pre_reloc_only && !ofnode_pre_reloc(node))
+ for (offset = fdt_first_subnode(fdt, offset);
+ offset > 0;
+ offset = fdt_next_subnode(fdt, offset)) {
+ if (pre_reloc_only &&
+ !ofnode_pre_reloc(offset_to_ofnode(offset)))
continue;
/*
* If this node has "compatible" property, this is not
* a clock sub-node, but a normal device. skip.
*/
- if (ofnode_read_prop(node, "compatible", NULL))
+ fdt_get_property(fdt, offset, "compatible", &ret);
+ if (ret >= 0)
continue;
if (ret != -FDT_ERR_NOTFOUND)
return ret;
- name = ofnode_get_name(node);
+ name = fdt_get_name(fdt, offset, NULL);
if (!name)
return -EINVAL;
- ret = device_bind_driver_to_node(dev, drv_name, name, node,
- NULL);
+ ret = device_bind_driver_to_node(dev, drv_name, name,
+ offset_to_ofnode(offset), NULL);
if (ret)
return ret;
}
* Wenyou.Yang <wenyou.yang@atmel.com>
*/
+#include <common.h>
#include <asm/io.h>
#include <clk-uclass.h>
-#include <common.h>
-
#include "pmc.h"
static int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
#include <linux/bug.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
+#include <asm/global_data.h>
static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
#include <clk-uclass.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dt-bindings/clock/octeon-clock.h>
DECLARE_GLOBAL_DATA_PTR;
#include <div64.h>
#include <time.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <time.h>
#include <vsprintf.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
#include <clk-uclass.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <errno.h>
#include <dm.h>
#include <log.h>
#include <vsprintf.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <dt-bindings/clk/mpc83xx-clk.h>
#include <asm/arch/soc.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <errno.h>
#include <log.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_px30.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <malloc.h>
#include <mapmem.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <log.h>
#include <malloc.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cru_rk3308.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
#include <log.h>
#include <malloc.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rv1108.h>
}
clk_modules[0] = (u32 *)(offs);
- dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ dev_dbg(clk->dev, "disable module @ %p\n", clk_modules[0]);
do_disable_clocks(NULL, clk_modules, 1);
return 0;
}
}
clk_modules[0] = (u32 *)(offs);
- dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ dev_dbg(clk->dev, "enable module @ %p\n", clk_modules[0]);
do_enable_clocks(NULL, clk_modules, 1);
return 0;
}
*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/io.h>
#include "clk.h"
This applies to several ofnode functions (see ofnode.h) which are
seldom used. Inlining them can help reduce code size.
+config DM_DMA
+ bool "Support per-device DMA constraints"
+ depends on DM
+ default n
+ help
+ Enable this to extract per-device DMA constraints, only supported on
+ device-tree systems for now. This is needed in order translate
+ addresses on systems where different buses have different views of
+ the physical address space.
+
config REGMAP
bool "Support register maps"
depends on DM
* Pavel Herrmann <morpheus.ibis@gmail.com>
*/
+#define LOG_CATEGORY LOGC_DM
+
#include <common.h>
#include <errno.h>
#include <log.h>
#include <dm/uclass-internal.h>
#include <dm/util.h>
#include <power-domain.h>
+#include <asm/global_data.h>
int device_chld_unbind(struct udevice *dev, struct driver *drv)
{
uint flags)
{
struct udevice *pos, *n;
- int ret;
+ int result = 0;
assert(dev);
list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+ int ret;
+
if (drv && (pos->driver != drv))
continue;
ret = device_remove(pos, flags);
- if (ret)
+ if (ret == -EPROBE_DEFER)
+ result = ret;
+ else if (ret && ret != -EKEYREJECTED)
return ret;
}
- return 0;
+ return result;
}
int device_unbind(struct udevice *dev)
devres_release_probe(dev);
}
-static bool flags_remove(uint flags, uint drv_flags)
+/**
+ * flags_remove() - Figure out whether to remove a device
+ *
+ * If this is called with @flags == DM_REMOVE_NON_VITAL | DM_REMOVE_ACTIVE_DMA,
+ * then it returns 0 (=go head and remove) if the device is not matked vital
+ * but is marked DM_REMOVE_ACTIVE_DMA.
+ *
+ * If this is called with @flags == DM_REMOVE_ACTIVE_DMA,
+ * then it returns 0 (=go head and remove) if the device is marked
+ * DM_REMOVE_ACTIVE_DMA, regardless of whether it is marked vital.
+ *
+ * @flags: Flags passed to device_remove()
+ * @drv_flags: Driver flags
+ * @return 0 if the device should be removed,
+ * -EKEYREJECTED if @flags includes a flag in DM_REMOVE_ACTIVE_ALL but
+ * @drv_flags does not (indicates that this device has nothing to do for
+ * DMA shutdown or OS prepare)
+ * -EPROBE_DEFER if @flags is DM_REMOVE_NON_VITAL but @drv_flags contains
+ * DM_FLAG_VITAL (indicates the device is vital and should not be removed)
+ */
+static int flags_remove(uint flags, uint drv_flags)
{
- if ((flags & DM_REMOVE_NORMAL) ||
- (flags && (drv_flags & (DM_FLAG_ACTIVE_DMA | DM_FLAG_OS_PREPARE))))
- return true;
+ if (!(flags & DM_REMOVE_NORMAL)) {
+ bool vital_match;
+ bool active_match;
+
+ active_match = !(flags & DM_REMOVE_ACTIVE_ALL) ||
+ (drv_flags & flags);
+ vital_match = !(flags & DM_REMOVE_NON_VITAL) ||
+ !(drv_flags & DM_FLAG_VITAL);
+ if (!vital_match)
+ return -EPROBE_DEFER;
+ if (!active_match)
+ return -EKEYREJECTED;
+ }
- return false;
+ return 0;
}
int device_remove(struct udevice *dev, uint flags)
if (!(dev_get_flags(dev) & DM_FLAG_ACTIVATED))
return 0;
+ /*
+ * If the child returns EKEYREJECTED, continue. It just means that it
+ * didn't match the flags.
+ */
+ ret = device_chld_remove(dev, NULL, flags);
+ if (ret && ret != -EKEYREJECTED)
+ return ret;
+
+ /*
+ * Remove the device if called with the "normal" remove flag set,
+ * or if the remove flag matches any of the drivers remove flags
+ */
drv = dev->driver;
assert(drv);
+ ret = flags_remove(flags, drv->flags);
+ if (ret) {
+ log_debug("%s: When removing: flags=%x, drv->flags=%x, err=%d\n",
+ dev->name, flags, drv->flags, ret);
+ return ret;
+ }
ret = uclass_pre_remove_device(dev);
if (ret)
return ret;
- ret = device_chld_remove(dev, NULL, flags);
- if (ret)
- goto err;
-
- /*
- * Remove the device if called with the "normal" remove flag set,
- * or if the remove flag matches any of the drivers remove flags
- */
- if (drv->remove && flags_remove(flags, drv->flags)) {
+ if (drv->remove) {
ret = drv->remove(dev);
if (ret)
goto err_remove;
if (!(flags & DM_REMOVE_NO_PD) &&
!(drv->flags &
- (DM_FLAG_DEFAULT_PD_CTRL_OFF | DM_FLAG_REMOVE_WITH_PD_ON)) &&
+ (DM_FLAG_DEFAULT_PD_CTRL_OFF | DM_FLAG_LEAVE_PD_ON)) &&
dev != gd->cur_serial_dev)
dev_power_domain_off(dev);
- if (flags_remove(flags, drv->flags)) {
- device_free(dev);
+ device_free(dev);
- dev_bic_flags(dev, DM_FLAG_ACTIVATED);
- }
+ dev_bic_flags(dev, DM_FLAG_ACTIVATED);
- return ret;
+ return 0;
err_remove:
/* We can't put the children back */
dm_warn("%s: Device '%s' failed to remove, but children are gone\n",
__func__, dev->name);
-err:
- ret = uclass_post_probe_device(dev);
- if (ret) {
- dm_warn("%s: Device '%s' failed to post_probe on error path\n",
- __func__, dev->name);
- }
return ret;
}
#include <common.h>
#include <cpu_func.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <fdtdec.h>
return ret;
}
+/**
+ * device_get_dma_constraints() - Populate device's DMA constraints
+ *
+ * Gets a device's DMA constraints from firmware. This information is later
+ * used by drivers to translate physcal addresses to the device's bus address
+ * space. For now only device-tree is supported.
+ *
+ * @dev: Pointer to target device
+ * Return: 0 if OK or if no DMA constraints were found, error otherwise
+ */
+static int device_get_dma_constraints(struct udevice *dev)
+{
+ struct udevice *parent = dev->parent;
+ phys_addr_t cpu = 0;
+ dma_addr_t bus = 0;
+ u64 size = 0;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(DM_DMA) || !parent || !dev_has_ofnode(parent))
+ return 0;
+
+ /*
+ * We start parsing for dma-ranges from the device's bus node. This is
+ * specially important on nested buses.
+ */
+ ret = dev_get_dma_range(parent, &cpu, &bus, &size);
+ /* Don't return an error if no 'dma-ranges' were found */
+ if (ret && ret != -ENOENT) {
+ dm_warn("%s: failed to get DMA range, %d\n", dev->name, ret);
+ return ret;
+ }
+
+ dev_set_dma_offset(dev, cpu - bus);
+
+ return 0;
+}
+
int device_probe(struct udevice *dev)
{
const struct driver *drv;
goto fail;
}
+ ret = device_get_dma_constraints(dev);
+ if (ret)
+ goto fail;
+
ret = uclass_pre_probe_device(dev);
if (ret)
goto fail;
#include <dm.h>
#include <fdt_support.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <common.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/bug.h>
#include <linux/libfdt.h>
#include <dm/of_access.h>
return __of_translate_address(dev, in_addr, "dma-ranges");
}
+int of_get_dma_range(const struct device_node *dev, phys_addr_t *cpu,
+ dma_addr_t *bus, u64 *size)
+{
+ bool found_dma_ranges = false;
+ struct device_node *parent;
+ struct of_bus *bus_node;
+ int na, ns, pna, pns;
+ const __be32 *ranges;
+ int ret = 0;
+ int len;
+
+ /* Find the closest dma-ranges property */
+ dev = of_node_get(dev);
+ while (dev) {
+ ranges = of_get_property(dev, "dma-ranges", &len);
+
+ /* Ignore empty ranges, they imply no translation required */
+ if (ranges && len > 0)
+ break;
+
+ /* Once we find 'dma-ranges', then a missing one is an error */
+ if (found_dma_ranges && !ranges) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (ranges)
+ found_dma_ranges = true;
+
+ parent = of_get_parent(dev);
+ of_node_put(dev);
+ dev = parent;
+ }
+
+ if (!dev || !ranges) {
+ debug("no dma-ranges found for node %s\n",
+ of_node_full_name(dev));
+ ret = -ENOENT;
+ goto out;
+ }
+
+ /* switch to that node */
+ parent = of_get_parent(dev);
+ if (!parent) {
+ printf("Found dma-ranges in root node, shoudln't happen\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Get the address sizes both for the bus and its parent */
+ bus_node = of_match_bus((struct device_node*)dev);
+ bus_node->count_cells(dev, &na, &ns);
+ if (!OF_CHECK_COUNTS(na, ns)) {
+ printf("Bad cell count for %s\n", of_node_full_name(dev));
+ return -EINVAL;
+ goto out_parent;
+ }
+
+ bus_node = of_match_bus(parent);
+ bus_node->count_cells(parent, &pna, &pns);
+ if (!OF_CHECK_COUNTS(pna, pns)) {
+ printf("Bad cell count for %s\n", of_node_full_name(parent));
+ return -EINVAL;
+ goto out_parent;
+ }
+
+ *bus = of_read_number(ranges, na);
+ *cpu = of_translate_dma_address(dev, ranges + na);
+ *size = of_read_number(ranges + na + pna, ns);
+
+out_parent:
+ of_node_put(parent);
+out:
+ of_node_put(dev);
+ return ret;
+}
+
+
static int __of_address_to_resource(const struct device_node *dev,
const __be32 *addrp, u64 size, unsigned int flags,
const char *name, struct resource *r)
#include <dm/ofnode.h>
#include <linux/err.h>
#include <linux/ioport.h>
+#include <asm/global_data.h>
int ofnode_read_u32(ofnode node, const char *propname, u32 *outp)
{
return fdt_translate_dma_address(gd->fdt_blob, ofnode_to_offset(node), in_addr);
}
+int ofnode_get_dma_range(ofnode node, phys_addr_t *cpu, dma_addr_t *bus, u64 *size)
+{
+ if (ofnode_is_np(node))
+ return of_get_dma_range(ofnode_to_np(node), cpu, bus, size);
+ else
+ return fdt_get_dma_range(gd->fdt_blob, ofnode_to_offset(node),
+ cpu, bus, size);
+}
+
int ofnode_device_is_compatible(ofnode node, const char *compat)
{
if (ofnode_is_np(node))
#include <dm.h>
#include <dm/of_access.h>
#include <mapmem.h>
+#include <asm/global_data.h>
#include <asm/types.h>
#include <asm/io.h>
#include <linux/ioport.h>
return ofnode_translate_dma_address(dev_ofnode(dev), in_addr);
}
+int dev_get_dma_range(const struct udevice *dev, phys_addr_t *cpu,
+ dma_addr_t *bus, u64 *size)
+{
+ return ofnode_get_dma_range(dev_ofnode(dev), cpu, bus, size);
+}
+
int dev_read_alias_highest_id(const char *stem)
{
if (of_live_active())
#include <dm.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <mapmem.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <dm/acpi.h>
#include <dm/device.h>
int dm_uninit(void)
{
+ /* Remove non-vital devices first */
+ device_remove(dm_root(), DM_REMOVE_NON_VITAL);
device_remove(dm_root(), DM_REMOVE_NORMAL);
device_unbind(dm_root());
gd->dm_root = NULL;
#include <errno.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <cpu.h>
#include <dm.h>
#include <thermal.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <linux/bitops.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <u-boot/rsa-mod-exp.h>
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
#include <ram.h>
#include <reset.h>
+#include <asm/global_data.h>
#include "sdram_soc64.h"
#include <wait_bit.h>
#include <asm/arch/firewall.h>
#include <wait_bit.h>
#include <watchdog.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/misc.h>
#include <log.h>
#include <ram.h>
#include <reset.h>
+#include <asm/global_data.h>
#include "sdram_s10.h"
#include <wait_bit.h>
#include <asm/arch/firewall.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/sizes.h>
#endif
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
#define DEV_TYPE struct udevice
#else
/* Local udevice */
{
int ret;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, 0, buf, len);
#else
ret = i2c_read(dev->chip, addr, alen, buf, len);
{
uint8_t buf = 0;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
int ret;
DEV_TYPE *dev;
-#if defined(CONFIG_DM_I2C)
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
1, &dev);
if (ret) {
#include <common.h>
#include <log.h>
#include <spl.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <log.h>
#include <malloc.h>
#include <dm-demo.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/list.h>
dev = spi_flash_probe(bus, cs, speed, mode);
if (!dev) {
- printf("Failed to create SPI flash at %d:%d:%d:%d\n",
+ printf("Failed to create SPI flash at %u:%u:%u:%u\n",
bus, cs, speed, mode);
return NULL;
}
When flashing NAND enable the DROP_FFS flag to drop trailing all-0xff
pages.
-config FASTBOOT_MMC_BOOT1_SUPPORT
- bool "Enable EMMC_BOOT1 flash/erase"
- depends on FASTBOOT_FLASH_MMC && EFI_PARTITION && ARCH_MEDIATEK
+config FASTBOOT_MMC_BOOT_SUPPORT
+ bool "Enable EMMC_BOOT flash/erase"
+ depends on FASTBOOT_FLASH_MMC
help
The fastboot "flash" and "erase" commands normally does operations
- on EMMC userdata. Define this to enable the special commands to
- flash/erase EMMC_BOOT1.
- The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+ on eMMC userdata. Define this to enable the special commands to
+ flash/erase eMMC boot partition.
+ The default target name for updating eMMC boot partition 1/2 is
+ CONFIG_FASTBOOT_MMC_BOOT1_NAME/CONFIG_FASTBOOT_MMC_BOOT2_NAME.
config FASTBOOT_MMC_BOOT1_NAME
string "Target name for updating EMMC_BOOT1"
- depends on FASTBOOT_MMC_BOOT1_SUPPORT
+ depends on FASTBOOT_MMC_BOOT_SUPPORT
default "mmc0boot0"
help
The fastboot "flash" and "erase" commands support operations on
defined here.
The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+config FASTBOOT_MMC_BOOT2_NAME
+ string "Target name for updating EMMC_BOOT2"
+ depends on FASTBOOT_MMC_BOOT_SUPPORT
+ default "mmc0boot1"
+ help
+ The fastboot "flash" and "erase" commands support operations on
+ EMMC_BOOT2. This occurs when the specified "EMMC_BOOT2 name" on
+ the "fastboot flash" and "fastboot erase" commands match the value
+ defined here.
+ The default target name for updating EMMC_BOOT2 is "mmc0boot1".
+
+config FASTBOOT_MMC_USER_SUPPORT
+ bool "Enable eMMC userdata partition flash/erase"
+ depends on FASTBOOT_FLASH_MMC
+ help
+ Define this to enable the support "flash" and "erase" command on
+ eMMC userdata. The "flash" command only update the MBR and GPT
+ header when CONFIG_EFI_PARTITION is supported.
+ The "erase" command erase all the userdata.
+ This occurs when the specified "partition name" on the
+ fastboot command line matches the value CONFIG_FASTBOOT_MMC_USER_NAME.
+
config FASTBOOT_MMC_USER_NAME
- string "Target name for erasing EMMC_USER"
- depends on FASTBOOT_FLASH_MMC && EFI_PARTITION && ARCH_MEDIATEK
+ string "Target name for updating EMMC_USER"
+ depends on FASTBOOT_MMC_USER_SUPPORT
default "mmc0"
help
- The fastboot "erase" command supports erasing EMMC_USER. This occurs
- when the specified "EMMC_USER name" on the "fastboot erase" commands
- match the value defined here.
+ The fastboot "flash" and "erase" command supports EMMC_USER.
+ This occurs when the specified "EMMC_USER name" on the
+ "fastboot flash" and the "fastboot erase" commands match the value
+ defined here.
The default target name for erasing EMMC_USER is "mmc0".
config FASTBOOT_GPT_NAME
relies on the env variable partitions to contain the list of
partitions as required by the gpt command.
-config FASTBOOT_USE_BCB_SET_REBOOT_FLAG
- bool "Use BCB by fastboot to set boot reason"
- depends on CMD_BCB && !ARCH_MESON && !ARCH_ROCKCHIP && !TARGET_KC1 && \
- !TARGET_SNIPER && !TARGET_AM57XX_EVM && !TARGET_DRA7XX_EVM
- default y
- help
- Fastboot could implement setting of reboot reason in a generic fashion
- via BCB commands. BCB commands are able to write reboot reason into
- command field of boot control block. In general case it is sufficient
- implementation if your platform supports BCB commands and doesn't
- require any specific reboot reason handling.
+config FASTBOOT_CMD_OEM_PARTCONF
+ bool "Enable the 'oem partconf' command"
+ depends on FASTBOOT_FLASH_MMC && SUPPORT_EMMC_BOOT
+ help
+ Add support for the "oem partconf" command from a client. This set
+ the mmc boot-partition for the selecting eMMC device.
+
+config FASTBOOT_CMD_OEM_BOOTBUS
+ bool "Enable the 'oem bootbus' command"
+ depends on FASTBOOT_FLASH_MMC && SUPPORT_EMMC_BOOT
+ help
+ Add support for the "oem bootbus" command from a client. This set
+ the mmc boot configuration for the selecting eMMC device.
endif # FASTBOOT
obj-y += fb_command.o
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o
obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o
-obj-$(CONFIG_FASTBOOT_USE_BCB_SET_REBOOT_FLAG) += fb_bcb_impl.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2020 GlobalLogic.
- * Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
- */
-
-#include <common.h>
-#include <fastboot.h>
-
-/**
- * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader
- *
- * Set flag which indicates that we should reboot into the bootloader
- * following the reboot that fastboot executes after this function.
- *
- * This function should be overridden in your board file with one
- * which sets whatever flag your board specific Android bootloader flow
- * requires in order to re-enter the bootloader.
- */
-int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
-{
- char cmd[64];
-
- if (reason >= FASTBOOT_REBOOT_REASONS_COUNT)
- return -EINVAL;
-
- snprintf(cmd, sizeof(cmd), "bcb load %d misc",
- CONFIG_FASTBOOT_FLASH_MMC_DEV);
-
- if (run_command(cmd, 0))
- return -ENODEV;
-
- snprintf(cmd, sizeof(cmd), "bcb set command %s",
- fastboot_boot_cmds[reason]);
-
- if (run_command(cmd, 0))
- return -ENOEXEC;
-
- if (run_command("bcb store", 0))
- return -EIO;
-
- return 0;
-}
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
static void oem_format(char *, char *);
#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF)
+static void oem_partconf(char *, char *);
+#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS)
+static void oem_bootbus(char *, char *);
+#endif
static const struct {
const char *command;
.dispatch = oem_format,
},
#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF)
+ [FASTBOOT_COMMAND_OEM_PARTCONF] = {
+ .command = "oem partconf",
+ .dispatch = oem_partconf,
+ },
+#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS)
+ [FASTBOOT_COMMAND_OEM_BOOTBUS] = {
+ .command = "oem bootbus",
+ .dispatch = oem_bootbus,
+ },
+#endif
};
/**
}
}
#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF)
+/**
+ * oem_partconf() - Execute the OEM partconf command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void oem_partconf(char *cmd_parameter, char *response)
+{
+ char cmdbuf[32];
+
+ if (!cmd_parameter) {
+ fastboot_fail("Expected command parameter", response);
+ return;
+ }
+
+ /* execute 'mmc partconfg' command with cmd_parameter arguments*/
+ snprintf(cmdbuf, sizeof(cmdbuf), "mmc partconf %x %s 0",
+ CONFIG_FASTBOOT_FLASH_MMC_DEV, cmd_parameter);
+ printf("Execute: %s\n", cmdbuf);
+ if (run_command(cmdbuf, 0))
+ fastboot_fail("Cannot set oem partconf", response);
+ else
+ fastboot_okay(NULL, response);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS)
+/**
+ * oem_bootbus() - Execute the OEM bootbus command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void oem_bootbus(char *cmd_parameter, char *response)
+{
+ char cmdbuf[32];
+
+ if (!cmd_parameter) {
+ fastboot_fail("Expected command parameter", response);
+ return;
+ }
+
+ /* execute 'mmc bootbus' command with cmd_parameter arguments*/
+ snprintf(cmdbuf, sizeof(cmdbuf), "mmc bootbus %x %s",
+ CONFIG_FASTBOOT_FLASH_MMC_DEV, cmd_parameter);
+ printf("Execute: %s\n", cmdbuf);
+ if (run_command(cmdbuf, 0))
+ fastboot_fail("Cannot set oem bootbus", response);
+ else
+ fastboot_okay(NULL, response);
+}
+#endif
* Rob Herring <robh@kernel.org>
*/
+#include <bcb.h>
#include <common.h>
#include <command.h>
#include <env.h>
*/
int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
{
- return -ENOSYS;
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC_DEV)
+ static const char * const boot_cmds[] = {
+ [FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader",
+ [FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot",
+ [FASTBOOT_REBOOT_REASON_RECOVERY] = "boot-recovery"
+ };
+
+ if (reason >= FASTBOOT_REBOOT_REASONS_COUNT)
+ return -EINVAL;
+
+ return bcb_write_reboot_reason(CONFIG_FASTBOOT_FLASH_MMC_DEV, "misc", boot_cmds[reason]);
+#else
+ return -EINVAL;
+#endif
}
/**
fastboot_okay(NULL, response);
}
-#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT
+#if defined(CONFIG_FASTBOOT_MMC_BOOT_SUPPORT) || \
+ defined(CONFIG_FASTBOOT_MMC_USER_SUPPORT)
static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc)
{
lbaint_t blks;
return 0;
}
+#endif
-static void fb_mmc_boot1_ops(struct blk_desc *dev_desc, void *buffer,
- u32 buff_sz, char *response)
+#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT
+static void fb_mmc_boot_ops(struct blk_desc *dev_desc, void *buffer,
+ int hwpart, u32 buff_sz, char *response)
{
lbaint_t blkcnt;
lbaint_t blks;
unsigned long blksz;
- // To operate on EMMC_BOOT1 (mmc0boot0), we first change the hwpart
- if (blk_dselect_hwpart(dev_desc, 1)) {
+ // To operate on EMMC_BOOT1/2 (mmc0boot0/1) we first change the hwpart
+ if (blk_dselect_hwpart(dev_desc, hwpart)) {
pr_err("Failed to select hwpart\n");
fastboot_fail("Failed to select hwpart", response);
return;
return;
}
- debug("Start Flashing Image to EMMC_BOOT1...\n");
+ debug("Start Flashing Image to EMMC_BOOT%d...\n", hwpart);
blks = fb_mmc_blk_write(dev_desc, 0, blkcnt, buffer);
if (blks != blkcnt) {
- pr_err("Failed to write EMMC_BOOT1\n");
- fastboot_fail("Failed to write EMMC_BOOT1", response);
+ pr_err("Failed to write EMMC_BOOT%d\n", hwpart);
+ fastboot_fail("Failed to write EMMC_BOOT part",
+ response);
return;
}
- printf("........ wrote %lu bytes to EMMC_BOOT1\n",
- blkcnt * blksz);
+ printf("........ wrote %lu bytes to EMMC_BOOT%d\n",
+ blkcnt * blksz, hwpart);
} else { /* erase */
if (fb_mmc_erase_mmc_hwpart(dev_desc)) {
- fastboot_fail("Failed to erase EMMC_BOOT1", response);
+ pr_err("Failed to erase EMMC_BOOT%d\n", hwpart);
+ fastboot_fail("Failed to erase EMMC_BOOT part",
+ response);
return;
}
}
return;
}
-#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT
+#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) {
- fb_mmc_boot1_ops(dev_desc, download_buffer,
- download_bytes, response);
+ fb_mmc_boot_ops(dev_desc, download_buffer, 1,
+ download_bytes, response);
+ return;
+ }
+ if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) {
+ fb_mmc_boot_ops(dev_desc, download_buffer, 2,
+ download_bytes, response);
return;
}
#endif
#if CONFIG_IS_ENABLED(EFI_PARTITION)
-#ifndef CONFIG_FASTBOOT_MMC_USER_NAME
+#ifndef CONFIG_FASTBOOT_MMC_USER_SUPPORT
if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
#else
if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0 ||
response);
return;
}
+ part_init(dev_desc);
printf("........ success\n");
fastboot_okay(NULL, response);
return;
response);
return;
}
+ part_init(dev_desc);
printf("........ success\n");
fastboot_okay(NULL, response);
return;
return;
}
-#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT
+#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) {
/* erase EMMC boot1 */
- fb_mmc_boot1_ops(dev_desc, NULL, 0, response);
+ fb_mmc_boot_ops(dev_desc, NULL, 1, 0, response);
+ return;
+ }
+ if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) {
+ /* erase EMMC boot2 */
+ fb_mmc_boot_ops(dev_desc, NULL, 2, 0, response);
return;
}
#endif
-#ifdef CONFIG_FASTBOOT_MMC_USER_NAME
+#ifdef CONFIG_FASTBOOT_MMC_USER_SUPPORT
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) {
/* erase EMMC userdata */
if (fb_mmc_erase_mmc_hwpart(dev_desc))
int ret = 0;
size_t n;
+ if (!devices)
+ return 0;
+
for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
int ret2 = reset_free(devices->reset + n);
*/
#include <image.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/reset_manager.h>
if (ret < 0)
return ret;
- ret = fit_check_format(buffer_p);
- if (!ret) {
+ ret = fit_check_format(buffer_p, IMAGE_SIZE_INVAL);
+ if (ret) {
debug("FPGA: No valid FIT image was found.\n");
- return -EBADF;
+ return ret;
}
confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
#include <console.h>
#include <common.h>
+#include <compiler.h>
#include <cpu_func.h>
#include <log.h>
#include <zynqmppl.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <errno.h>
#include <malloc.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
#include <mach/gpio.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/io.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <clk.h>
#include <dm.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/pinctrl.h>
#include <errno.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <fdtdec.h>
#include <malloc.h>
#include <acpi/acpi_device.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <dm/device_compat.h>
#include <linux/bug.h>
#include <pci.h>
#include <syscon.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <pch.h>
#include <pci.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>
* based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
*
* Copyright 2010 eXMeritus, A Boeing Company
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
#include <common.h>
#include <asm/io.h>
#include <dm/of_access.h>
-struct ccsr_gpio {
- u32 gpdir;
- u32 gpodr;
- u32 gpdat;
- u32 gpier;
- u32 gpimr;
- u32 gpicr;
- u32 gpibe;
-};
-
struct mpc8xxx_gpio_data {
/* The bank's register base in memory */
struct ccsr_gpio __iomem *base;
{
struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
- fdt_addr_t addr;
- u32 i;
- u32 reg[4];
- if (ofnode_read_bool(dev_ofnode(dev), "little-endian"))
+ if (dev_read_bool(dev, "little-endian"))
data->little_endian = true;
- if (data->little_endian)
- dev_read_u32_array(dev, "reg", reg, 4);
- else
- dev_read_u32_array(dev, "reg", reg, 2);
-
- if (data->little_endian) {
- for (i = 0; i < 2; i++)
- reg[i] = be32_to_cpu(reg[i]);
- }
-
- addr = dev_translate_address(dev, reg);
-
- plat->addr = addr;
-
- if (data->little_endian)
- plat->size = reg[3];
- else
- plat->size = reg[1];
-
+ plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
return 0;
if (!str)
return -ENOMEM;
- if (ofnode_device_is_compatible(dev_ofnode(dev), "fsl,qoriq-gpio")) {
- unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio)
- - sizeof(u32);
-
- out_be32((unsigned int *)gpibe, 0xffffffff);
+ if (device_is_compatible(dev, "fsl,qoriq-gpio")) {
+ if (data->little_endian)
+ out_le32(&data->base->gpibe, 0xffffffff);
+ else
+ out_be32(&data->base->gpibe, 0xffffffff);
}
uc_priv->bank_name = str;
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <common.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <i2c.h>
#include <log.h>
#include <asm-generic/gpio.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <linux/compat.h>
+#include <asm/global_data.h>
static inline const struct hwspinlock_ops *
hwspinlock_dev_ops(struct udevice *dev)
device (bus child) info is kept as parent plat. The interface
is defined in include/i2c.h.
+config SPL_DM_I2C
+ bool "Enable Driver Model for I2C drivers in SPL"
+ depends on SPL_DM && DM_I2C
+ default y
+ help
+ Enable driver model for I2C. The I2C uclass interface: probe, read,
+ write and speed, is implemented with the bus drivers operations,
+ which provide methods for bus setting and data transfer. Each chip
+ device (bus child) info is kept as parent platdata. The interface
+ is defined in include/i2c.h.
+
config I2C_CROS_EC_TUNNEL
tristate "Chrome OS EC tunnel I2C bus"
depends on CROS_EC
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SPL_DM_I2C_GPIO
+ bool "Enable Driver Model for software emulated I2C bus driver in SPL"
+ depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO_SUPPORT
+ default y
+ help
+ Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
+ configuration is given by the device tree. Kernel-style device tree
+ bindings are supported.
+ Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+
config SYS_I2C_AT91
bool "Atmel I2C driver"
depends on DM_I2C && ARCH_AT91
if SYS_I2C_MXC_I2C1
config SYS_MXC_I2C1_SPEED
int "I2C Channel 1 speed"
- default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
+ default 40000000 if TARGET_LS2080A_EMU
default 100000
help
MXC I2C Channel 1 speed
if SYS_I2C_MXC_I2C2
config SYS_MXC_I2C2_SPEED
int "I2C Channel 2 speed"
- default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
+ default 40000000 if TARGET_LS2080A_EMU
default 100000
help
MXC I2C Channel 2 speed
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_DM_I2C) += i2c-uclass.o
+obj-$(CONFIG_$(SPL_)DM_I2C) += i2c-uclass.o
ifdef CONFIG_ACPIGEN
-obj-$(CONFIG_DM_I2C) += acpi_i2c.o
+obj-$(CONFIG_$(SPL_)DM_I2C) += acpi_i2c.o
endif
obj-$(CONFIG_$(SPL_)DM_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
*/
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <clk.h>
u32 i;
int ret = 0;
+ /* if there is no message to send/receive, just exit quietly */
+ if (msg->len == 0)
+ return ret;
+
readl(®->sr);
if (is_read) {
writel(TWI_CR_START, ®->cr);
#include <cros_ec.h>
#include <errno.h>
#include <i2c.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <linux/delay.h>
#include "davinci_i2c.h"
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
/* Information about i2c controller */
struct i2c_bus {
int id;
return rc;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
writel(IC_RX_TL, &i2c_base->ic_rx_tl);
writel(IC_TX_TL, &i2c_base->ic_tx_tl);
writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
_dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
writel(slaveaddr, &i2c_base->ic_sar);
#endif
return 0;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/*
* The legacy I2C functions. These need to get removed once
* all users of this driver are converted to DM.
#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pinmux.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include "s3c24x0_i2c.h"
#include <i2c.h> /* Functional interface */
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/fsl_i2c.h> /* HW definitions */
#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static const struct fsl_i2c_base *i2c_base[4] = {
(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
return speed;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static uint get_i2c_clock(int bus)
{
if (bus)
return 0;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
__i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
struct gpio_desc *sda = &bus->gpios[PIN_SDA];
if (bit)
- dm_gpio_set_dir_flags(sda, GPIOD_IS_IN);
+ sda->flags = (sda->flags & ~GPIOD_IS_OUT) | GPIOD_IS_IN;
else
- dm_gpio_set_dir_flags(sda, GPIOD_IS_OUT);
+ sda->flags = (sda->flags & (~GPIOD_IS_IN & ~GPIOD_IS_OUT_ACTIVE)) | GPIOD_IS_OUT;
+ dm_gpio_set_dir(sda);
}
static void i2c_gpio_scl_set(struct i2c_gpio_bus *bus, int bit)
int count = 0;
if (bit) {
- dm_gpio_set_dir_flags(scl, GPIOD_IS_IN);
+ scl->flags = (scl->flags & ~GPIOD_IS_OUT) | GPIOD_IS_IN;
+ dm_gpio_set_dir(scl);
while (!dm_gpio_get_value(scl) && count++ < 100000)
udelay(1);
if (!dm_gpio_get_value(scl))
pr_err("timeout waiting on slave to release scl\n");
} else {
- dm_gpio_set_dir_flags(scl, GPIOD_IS_OUT);
+ scl->flags = (scl->flags & (~GPIOD_IS_IN & ~GPIOD_IS_OUT_ACTIVE)) | GPIOD_IS_OUT;
+ dm_gpio_set_dir(scl);
}
}
static void i2c_gpio_scl_set_output_only(struct i2c_gpio_bus *bus, int bit)
{
struct gpio_desc *scl = &bus->gpios[PIN_SCL];
- ulong flags = GPIOD_IS_OUT;
+ scl->flags = (scl->flags & (~GPIOD_IS_IN & ~GPIOD_IS_OUT_ACTIVE)) | GPIOD_IS_OUT;
if (bit)
- flags |= GPIOD_IS_OUT_ACTIVE;
- dm_gpio_set_dir_flags(scl, flags);
+ scl->flags |= GPIOD_IS_OUT_ACTIVE;
+ dm_gpio_set_dir(scl);
}
static void i2c_gpio_write_bit(struct i2c_gpio_bus *bus, int delay, uchar bit)
#include <common.h>
#include <i2c.h>
#include <linker_lists.h>
+#include <asm/global_data.h>
struct i2c_adapter *i2c_get_adapter(int index)
{
#include <common.h>
#include <i2c.h>
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
#include <dm.h>
#include <regmap.h>
#else
#include <gdsys_fpga.h>
#endif
#include <log.h>
+#include <asm/global_data.h>
#include <asm/unaligned.h>
#include <linux/bitops.h>
#include <linux/delay.h>
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct ihs_i2c_priv {
uint speed;
struct regmap *map;
I2COP_READ = 1,
};
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static int wait_for_int(struct udevice *dev, int read)
#else
static int wait_for_int(bool read)
{
u16 val;
uint ctr = 0;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct ihs_i2c_priv *priv = dev_get_priv(dev);
#endif
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
debug("%s: timed out\n", __func__);
return -ETIMEDOUT;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
return (val & I2CINT_ERROR_EV) ? -EIO : 0;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
uchar *buffer, int len, int read, bool is_last)
#else
u16 val;
u16 data;
int res;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct ihs_i2c_priv *priv = dev_get_priv(dev);
#endif
/* Clear interrupt status */
data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_set(priv->map, interrupt_status, data);
ihs_i2c_get(priv->map, interrupt_status, &val);
#else
if (len > 1)
val |= buffer[1] << 8;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_set(priv->map, write_mailbox_ext, val);
#else
I2C_SET_REG(write_mailbox_ext, val);
| ((len > 1) ? I2CMB_2BYTE : 0)
| (is_last ? 0 : I2CMB_HOLD_BUS);
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_set(priv->map, write_mailbox, data);
#else
I2C_SET_REG(write_mailbox, data);
#endif
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
res = wait_for_int(dev, read);
#else
res = wait_for_int(read);
/* If we want to read, get the bytes from the mailbox */
if (read) {
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ihs_i2c_get(priv->map, read_mailbox_ext, &val);
#else
I2C_GET_REG(read_mailbox_ext, &val);
return 0;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
#else
static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
int transfer = min(len, 2);
bool is_last = len <= transfer;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
res = ihs_i2c_transfer(dev, chip, data, transfer, read,
hold_bus ? false : is_last);
#else
return 0;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
bool hold_bus)
#else
static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
#endif
{
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
#else
return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
#endif
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
int alen, uchar *buffer, int len, int read)
#else
if (len <= 0)
return -EINVAL;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
res = ihs_i2c_address(dev, chip, addr, alen, len);
#else
res = ihs_i2c_address(chip, addr, alen, len);
if (res)
return res;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
#else
return ihs_i2c_send_buffer(chip, buffer, len, false, read);
#endif
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int ihs_i2c_probe(struct udevice *bus)
{
*
*/
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <config.h>
#define LPC32XX_I2C_STAT_NAI 0x00000004
#define LPC32XX_I2C_STAT_TDI 0x00000001
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
(struct lpc32xx_i2c_base *)I2C1_BASE,
(struct lpc32xx_i2c_base *)I2C2_BASE,
return 0;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static void lpc32xx_i2c_init(struct i2c_adapter *adap,
int requested_speed, int slaveadd)
{
#include <i2c.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <linux/delay.h>
* Peng Fan <peng.fan@nxp.com>
*/
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <common.h>
#include <i2c.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm-generic/gpio.h>
return 0;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static struct mv_i2c *base_glob;
#include <common.h>
#include <i2c.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/compat.h>
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
#include <dm.h>
#endif
* settings
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#if defined(CONFIG_ARCH_ORION5X)
#include <asm/arch/orion5x.h>
#elif (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
* On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
* always have it.
*/
-#if defined(CONFIG_DM_I2C) && defined(CONFIG_ARCH_SUNXI)
+#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI)
#include <asm/arch/i2c.h>
#endif
#endif
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct mvtwsi_i2c_dev {
/* TWSI Register base for the device */
struct mvtwsi_registers *base;
return (1000000000u / speed) + 100;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/*
* twsi_get_base() - Get controller register base for specified adapter
writel(baud, &twsi->baudrate);
/* Wait for controller for one tick */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ndelay(calc_tick(highest_speed));
#else
ndelay(10000);
writel(slaveadd, &twsi->slave_address);
writel(0, &twsi->xtnd_slave_addr);
/* Assert STOP, but don't care for the result */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
(void) twsi_stop(twsi, calc_tick(*actual_speed));
#else
(void) twsi_stop(twsi, 10000);
return status != 0 ? status : stop_status;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
int slaveadd)
{
#include <log.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/delay.h>
#include <linux/errno.h>
#endif
};
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
{
if (i2c_bus && i2c_bus->idle_bus_fn)
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
__attribute__((weak, alias("__enable_i2c_clk")));
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/*
* Read data from I2C device
*
#include <asm/arch/reset.h>
#include <asm/arch/clk.h>
#include <asm/arch/nx_gpio.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#define I2C_WRITE 0
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
return i2c_error;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/*
* The legacy I2C functions. These need to get removed once
* all users of this driver are converted to DM.
#else
#include <asm/arch/s3c24x0_cpu.h>
#endif
+#include <asm/global_data.h>
#include <asm/io.h>
#include <i2c.h>
#include "s3c24x0_i2c.h"
#include <common.h>
#include <i2c.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#endif
#endif
#include <i2c.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
#include <log.h>
#include <misc.h>
#include <asm/arch-tegra/bpmp_abi.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
#include <input.h>
#include <keyboard.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <common.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/types.h>
obj-$(CONFIG_SANDBOX) += swap_case.o
endif
-ifdef CONFIG_DM_I2C
+ifdef CONFIG_$(SPL_)DM_I2C
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
endif
#include <errno.h>
#include <atsha204a-i2c.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <u-boot/crc.h>
#include <fs.h>
#include <fs_loader.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/string.h>
#include <mapmem.h>
#include <malloc.h>
#include <fuse.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <linux/arm-smccc.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/lists.h>
#include <common.h>
#include <hang.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <asm/arch/sci/sci.h>
#include <log.h>
#include <malloc.h>
#include <time.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <mailbox.h>
#include <common.h>
#include <dm.h>
#include <dm/test.h>
+#include <asm/global_data.h>
/* Records the last testbus device that was removed */
static struct udevice *testbus_removed;
help
Enable write access to MMC and SD Cards
+config MMC_PWRSEQ
+ bool "HW reset support for eMMC"
+ depends on PWRSEQ
+ help
+ Ths select Hardware reset support aka pwrseq-emmc for eMMC
+ devices.
+
config MMC_BROKEN_CD
bool "Poll for broken card detection case"
help
depends on MMC_SDHCI
depends on DM_MMC && OF_CONTROL && BLK
depends on REGMAP
+ select MMC_SDHCI_IO_ACCESSORS
help
Support for Secure Digital Host Controller Interface (SDHCI)
controllers present on TI's AM654 SOCs.
obj-y += mmc.o
obj-$(CONFIG_$(SPL_)DM_MMC) += mmc-uclass.o
obj-$(CONFIG_$(SPL_)MMC_WRITE) += mmc_write.o
+obj-$(CONFIG_MMC_PWRSEQ) += mmc-pwrseq.o
obj-$(CONFIG_MMC_SDHCI_ADMA_HELPERS) += sdhci-adma.o
ifndef CONFIG_$(SPL_)BLK
#include <common.h>
#include <dm.h>
#include <malloc.h>
+#include <mmc.h>
#include <power-domain.h>
#include <regmap.h>
#include <sdhci.h>
+#include <soc.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/err.h>
#define SEL100_MASK BIT(SEL100_SHIFT)
#define FREQSEL_SHIFT 8
#define FREQSEL_MASK GENMASK(10, 8)
+#define CLKBUFSEL_SHIFT 0
+#define CLKBUFSEL_MASK GENMASK(2, 0)
#define DLL_TRIM_ICP_SHIFT 4
#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
#define DR_TY_SHIFT 20
#define CALDONE_MASK BIT(CALDONE_SHIFT)
#define RETRIM_SHIFT 17
#define RETRIM_MASK BIT(RETRIM_SHIFT)
+#define SELDLYTXCLK_SHIFT 17
+#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
+#define SELDLYRXCLK_SHIFT 16
+#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
+#define ITAPDLYSEL_SHIFT 0
+#define ITAPDLYSEL_MASK GENMASK(4, 0)
+#define ITAPDLYENA_SHIFT 8
+#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
+#define ITAPCHGWIN_SHIFT 9
+#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
#define DRIVER_STRENGTH_50_OHM 0x0
#define DRIVER_STRENGTH_33_OHM 0x1
#define DRIVER_STRENGTH_40_OHM 0x4
#define AM654_SDHCI_MIN_FREQ 400000
+#define CLOCK_TOO_SLOW_HZ 50000000
struct am654_sdhci_plat {
struct mmc_config cfg;
struct regmap *base;
bool non_removable;
u32 otap_del_sel[MMC_MODES_END];
+ u32 itap_del_sel[MMC_MODES_END];
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
+ u32 clkbuf_sel;
u32 flags;
-#define DLL_PRESENT (1 << 0)
-#define IOMUX_PRESENT (1 << 1)
-#define FREQSEL_2_BIT (1 << 2)
-#define STRBSEL_4_BIT (1 << 3)
- bool dll_on;
+#define DLL_PRESENT BIT(0)
+#define IOMUX_PRESENT BIT(1)
+#define FREQSEL_2_BIT BIT(2)
+#define STRBSEL_4_BIT BIT(3)
+#define DLL_CALIB BIT(4)
};
struct timing_data {
- const char *binding;
+ const char *otap_binding;
+ const char *itap_binding;
u32 capability;
};
static const struct timing_data td[] = {
- [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
- [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
- [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
- [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
- [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
- [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
- [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
- [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
- [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
- [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
- [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
+ [MMC_LEGACY] = {"ti,otap-del-sel-legacy",
+ "ti,itap-del-sel-legacy",
+ 0},
+ [MMC_HS] = {"ti,otap-del-sel-mmc-hs",
+ "ti,itap-del-sel-mms-hs",
+ MMC_CAP(MMC_HS)},
+ [SD_HS] = {"ti,otap-del-sel-sd-hs",
+ "ti,itap-del-sel-sd-hs",
+ MMC_CAP(SD_HS)},
+ [UHS_SDR12] = {"ti,otap-del-sel-sdr12",
+ "ti,itap-del-sel-sdr12",
+ MMC_CAP(UHS_SDR12)},
+ [UHS_SDR25] = {"ti,otap-del-sel-sdr25",
+ "ti,itap-del-sel-sdr25",
+ MMC_CAP(UHS_SDR25)},
+ [UHS_SDR50] = {"ti,otap-del-sel-sdr50",
+ NULL,
+ MMC_CAP(UHS_SDR50)},
+ [UHS_SDR104] = {"ti,otap-del-sel-sdr104",
+ NULL,
+ MMC_CAP(UHS_SDR104)},
+ [UHS_DDR50] = {"ti,otap-del-sel-ddr50",
+ NULL,
+ MMC_CAP(UHS_DDR50)},
+ [MMC_DDR_52] = {"ti,otap-del-sel-ddr52",
+ "ti,itap-del-sel-ddr52",
+ MMC_CAP(MMC_DDR_52)},
+ [MMC_HS_200] = {"ti,otap-del-sel-hs200",
+ NULL,
+ MMC_CAP(MMC_HS_200)},
+ [MMC_HS_400] = {"ti,otap-del-sel-hs400",
+ NULL,
+ MMC_CAP(MMC_HS_400)},
};
struct am654_driver_data {
u32 flags;
};
-static void am654_sdhci_set_control_reg(struct sdhci_host *host)
+static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
+ unsigned int speed)
{
- struct mmc *mmc = (struct mmc *)host->mmc;
- u32 reg;
-
- if (IS_SD(host->mmc) &&
- mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
- reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- reg |= SDHCI_CTRL_VDD_180;
- sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+ int sel50, sel100, freqsel;
+ u32 mask, val;
+ int ret;
+
+ /* Disable delay chain mode */
+ regmap_update_bits(plat->base, PHY_CTRL5,
+ SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
+
+ if (plat->flags & FREQSEL_2_BIT) {
+ switch (speed) {
+ case 200000000:
+ sel50 = 0;
+ sel100 = 0;
+ break;
+ case 100000000:
+ sel50 = 0;
+ sel100 = 1;
+ break;
+ default:
+ sel50 = 1;
+ sel100 = 0;
+ }
+
+ /* Configure PHY DLL frequency */
+ mask = SEL50_MASK | SEL100_MASK;
+ val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
+ regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
+ } else {
+ switch (speed) {
+ case 200000000:
+ freqsel = 0x0;
+ break;
+ default:
+ freqsel = 0x4;
+ }
+ regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
+ freqsel << FREQSEL_SHIFT);
}
- sdhci_set_uhs_timing(host);
+ /* Configure DLL TRIM */
+ mask = DLL_TRIM_ICP_MASK;
+ val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
+
+ /* Configure DLL driver strength */
+ mask |= DR_TY_MASK;
+ val |= plat->drv_strength << DR_TY_SHIFT;
+ regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
+
+ /* Enable DLL */
+ regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
+ 0x1 << ENDLL_SHIFT);
+ /*
+ * Poll for DLL ready. Use a one second timeout.
+ * Works in all experiments done so far
+ */
+ ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
+ val & DLLRDY_MASK, 1000, 1000000);
+
+ return ret;
+}
+
+static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat,
+ u32 itapdly)
+{
+ /* Set ITAPCHGWIN before writing to ITAPDLY */
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
+ 1 << ITAPCHGWIN_SHIFT);
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYSEL_MASK,
+ itapdly << ITAPDLYSEL_SHIFT);
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
+}
+
+static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat,
+ int mode)
+{
+ u32 mask, val;
+
+ val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
+ mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
+ regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
+
+ am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]);
}
static int am654_sdhci_set_ios_post(struct sdhci_host *host)
struct udevice *dev = host->mmc->dev;
struct am654_sdhci_plat *plat = dev_get_plat(dev);
unsigned int speed = host->mmc->clock;
- int sel50, sel100, freqsel;
+ int mode = host->mmc->selected_mode;
u32 otap_del_sel;
u32 mask, val;
int ret;
val &= ~SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
- /* power off phy */
- if (plat->dll_on) {
- regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
-
- plat->dll_on = false;
- }
+ regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
/* restart clock */
sdhci_set_clock(host->mmc, speed);
/* switch phy back on */
- if (speed > AM654_SDHCI_MIN_FREQ) {
- otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
- mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
- val = (1 << OTAPDLYENA_SHIFT) |
- (otap_del_sel << OTAPDLYSEL_SHIFT);
-
- /* Write to STRBSEL for HS400 speed mode */
- if (host->mmc->selected_mode == MMC_HS_400) {
- if (plat->flags & STRBSEL_4_BIT)
- mask |= STRBSEL_4BIT_MASK;
- else
- mask |= STRBSEL_8BIT_MASK;
-
- val |= plat->strb_sel << STRBSEL_SHIFT;
- }
+ otap_del_sel = plat->otap_del_sel[mode];
+ mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
+ val = (1 << OTAPDLYENA_SHIFT) |
+ (otap_del_sel << OTAPDLYSEL_SHIFT);
- regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
-
- if (plat->flags & FREQSEL_2_BIT) {
- switch (speed) {
- case 200000000:
- sel50 = 0;
- sel100 = 0;
- break;
- case 100000000:
- sel50 = 0;
- sel100 = 1;
- break;
- default:
- sel50 = 1;
- sel100 = 0;
- }
-
- /* Configure PHY DLL frequency */
- mask = SEL50_MASK | SEL100_MASK;
- val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
- regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
- } else {
- switch (speed) {
- case 200000000:
- freqsel = 0x0;
- break;
- default:
- freqsel = 0x4;
- }
- regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
- freqsel << FREQSEL_SHIFT);
- }
+ /* Write to STRBSEL for HS400 speed mode */
+ if (host->mmc->selected_mode == MMC_HS_400) {
+ if (plat->flags & STRBSEL_4_BIT)
+ mask |= STRBSEL_4BIT_MASK;
+ else
+ mask |= STRBSEL_8BIT_MASK;
- /* Enable DLL */
- regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
- 0x1 << ENDLL_SHIFT);
- /*
- * Poll for DLL ready. Use a one second timeout.
- * Works in all experiments done so far
- */
- ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
- val & DLLRDY_MASK, 1000, 1000000);
+ val |= plat->strb_sel << STRBSEL_SHIFT;
+ }
+
+ regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+
+ if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {
+ ret = am654_sdhci_setup_dll(plat, speed);
if (ret)
return ret;
-
- plat->dll_on = true;
+ } else {
+ am654_sdhci_setup_delay_chain(plat, mode);
}
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ plat->clkbuf_sel);
+
return 0;
}
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
- if (plat->flags & DLL_PRESENT) {
+ if (plat->flags & DLL_CALIB) {
regmap_read(plat->base, PHY_STAT1, &val);
if (~val & CALDONE_MASK) {
/* Calibrate IO lines */
if (ret)
return ret;
}
-
- /* Configure DLL TRIM */
- mask = DLL_TRIM_ICP_MASK;
- val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
-
- /* Configure DLL driver strength */
- mask |= DR_TY_MASK;
- val |= plat->drv_strength << DR_TY_SHIFT;
- regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
}
/* Enable pins by setting IO mux to 0 */
return sdhci_probe(dev);
}
+static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+ if (reg == SDHCI_HOST_CONTROL) {
+ switch (host->mmc->selected_mode) {
+ /*
+ * According to the data manual, HISPD bit
+ * should not be set in these speed modes.
+ */
+ case SD_HS:
+ case MMC_HS:
+ case UHS_SDR12:
+ case UHS_SDR25:
+ val &= ~SDHCI_CTRL_HISPD;
+ default:
+ break;
+ }
+ }
+
+ writeb(val, host->ioaddr + reg);
+}
+#ifdef MMC_SUPPORTS_TUNING
+#define ITAP_MAX 32
+static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct udevice *dev = mmc->dev;
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
+ int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
+ u32 itap;
+
+ /* Enable ITAPDLY */
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
+ 1 << ITAPDLYENA_SHIFT);
+
+ for (itap = 0; itap < ITAP_MAX; itap++) {
+ am654_sdhci_write_itapdly(plat, itap);
+
+ cur_val = !mmc_send_tuning(mmc, opcode, NULL);
+ if (cur_val && !prev_val)
+ pass_window = itap;
+
+ if (!cur_val)
+ fail_len++;
+
+ prev_val = cur_val;
+ }
+ /*
+ * Having determined the length of the failing window and start of
+ * the passing window calculate the length of the passing window and
+ * set the final value halfway through it considering the range as a
+ * circular buffer
+ */
+ pass_len = ITAP_MAX - fail_len;
+ itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
+ am654_sdhci_write_itapdly(plat, itap);
+
+ return 0;
+}
+#endif
const struct sdhci_ops am654_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+ .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = &am654_sdhci_set_ios_post,
- .set_control_reg = &am654_sdhci_set_control_reg,
+ .set_control_reg = sdhci_set_control_reg,
+ .write_b = am654_sdhci_write_b,
};
const struct am654_driver_data am654_drv_data = {
.ops = &am654_sdhci_ops,
- .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
+ .flags = DLL_PRESENT | IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT,
+};
+
+const struct am654_driver_data am654_sr1_drv_data = {
+ .ops = &am654_sdhci_ops,
+ .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
+ STRBSEL_4_BIT,
};
const struct am654_driver_data j721e_8bit_drv_data = {
.ops = &am654_sdhci_ops,
- .flags = DLL_PRESENT,
+ .flags = DLL_PRESENT | DLL_CALIB,
};
static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ plat->clkbuf_sel);
+
return 0;
}
const struct sdhci_ops j721e_4bit_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+ .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post = &j721e_4bit_sdhci_set_ios_post,
+ .set_control_reg = sdhci_set_control_reg,
+ .write_b = am654_sdhci_write_b,
};
const struct am654_driver_data j721e_4bit_drv_data = {
.flags = IOMUX_PRESENT,
};
+const struct soc_attr am654_sdhci_soc_attr[] = {
+ { .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
+ {/* sentinel */}
+};
+
static int sdhci_am654_get_otap_delay(struct udevice *dev,
struct mmc_config *cfg)
{
* value is not found
*/
for (i = MMC_HS; i <= MMC_HS_400; i++) {
- ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);
+ ret = dev_read_u32(dev, td[i].otap_binding,
+ &plat->otap_del_sel[i]);
if (ret) {
- dev_dbg(dev, "Couldn't find %s\n", td[i].binding);
+ dev_dbg(dev, "Couldn't find %s\n", td[i].otap_binding);
/*
* Remove the corresponding capability
* if an otap-del-sel value is not found
*/
cfg->host_caps &= ~td[i].capability;
}
+
+ if (td[i].itap_binding)
+ dev_read_u32(dev, td[i].itap_binding,
+ &plat->itap_del_sel[i]);
}
return 0;
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
+ const struct soc_attr *soc;
+ const struct am654_driver_data *soc_drv_data;
struct clk clk;
unsigned long clock;
int ret;
host->max_clk = clock;
host->mmc = &plat->mmc;
host->mmc->dev = dev;
+ host->ops = drv_data->ops;
ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
AM654_SDHCI_MIN_FREQ);
if (ret)
if (ret)
return ret;
- host->ops = drv_data->ops;
+ /* Update ops based on SoC revision */
+ soc = soc_device_match(am654_sdhci_soc_attr);
+ if (soc && soc->data) {
+ soc_drv_data = soc->data;
+ host->ops = soc_drv_data->ops;
+ }
+
host->mmc->priv = host;
upriv->mmc = host->mmc;
}
}
+ dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel);
+
ret = mmc_of_parse(dev, cfg);
if (ret)
return ret;
struct am654_driver_data *drv_data =
(struct am654_driver_data *)dev_get_driver_data(dev);
struct am654_sdhci_plat *plat = dev_get_plat(dev);
+ const struct soc_attr *soc;
+ const struct am654_driver_data *soc_drv_data;
plat->flags = drv_data->flags;
+ /* Update flags based on SoC revision */
+ soc = soc_device_match(am654_sdhci_soc_attr);
+ if (soc && soc->data) {
+ soc_drv_data = soc->data;
+ plat->flags = soc_drv_data->flags;
+ }
+
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/clk.h>
+#include <asm/global_data.h>
#define ATMEL_SDHC_MIN_FREQ 400000
#define ATMEL_SDHC_GCK_RATE 240000000
#include <common.h>
#include <dwmmc.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <errno.h>
#include <common.h>
#include <dwmmc.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <errno.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <mmc.h>
#include <part.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <errno.h>
#include <malloc.h>
#include <sdhci.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <malloc.h>
#include <mmc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include <errno.h>
uint32_t val;
int ret;
-#ifdef CONFIG_PWRSEQ
- struct udevice *pwr_dev;
-#endif
-
/* Enable the clocks feeding the MMC controller */
ret = clk_get_bulk(dev, &clocks);
if (ret)
mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
-#ifdef CONFIG_PWRSEQ
+#ifdef CONFIG_MMC_PWRSEQ
/* Enable power if needed */
- ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
- &pwr_dev);
+ ret = mmc_pwrseq_get_power(dev, cfg);
if (!ret) {
- ret = pwrseq_set_power(pwr_dev, true);
+ ret = pwrseq_set_power(cfg->pwr_dev, true);
if (ret)
return ret;
}
.of_to_plat = meson_mmc_of_to_plat,
.plat_auto = sizeof(struct meson_mmc_plat),
};
-
-#ifdef CONFIG_PWRSEQ
-static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
-{
- struct gpio_desc reset;
- int ret;
-
- ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
- if (ret)
- return ret;
- dm_gpio_set_value(&reset, 1);
- udelay(1);
- dm_gpio_set_value(&reset, 0);
- udelay(200);
-
- return 0;
-}
-
-static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
- .set_power = meson_mmc_pwrseq_set_power,
-};
-
-static const struct udevice_id meson_mmc_pwrseq_ids[] = {
- { .compatible = "mmc-pwrseq-emmc" },
- { }
-};
-
-U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
- .name = "mmc_pwrseq_emmc",
- .id = UCLASS_PWRSEQ,
- .of_match = meson_mmc_pwrseq_ids,
- .ops = &meson_mmc_pwrseq_ops,
-};
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mmc.h>
+#include <pwrseq.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg)
+{
+ /* Enable power if needed */
+ return uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
+ &cfg->pwr_dev);
+}
+
+static int mmc_pwrseq_set_power(struct udevice *dev, bool enable)
+{
+ struct gpio_desc reset;
+ int ret;
+
+ ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
+ if (ret)
+ return ret;
+ dm_gpio_set_value(&reset, 1);
+ udelay(1);
+ dm_gpio_set_value(&reset, 0);
+ udelay(200);
+
+ return 0;
+}
+
+static const struct pwrseq_ops mmc_pwrseq_ops = {
+ .set_power = mmc_pwrseq_set_power,
+};
+
+static const struct udevice_id mmc_pwrseq_ids[] = {
+ { .compatible = "mmc-pwrseq-emmc" },
+ { }
+};
+
+U_BOOT_DRIVER(mmc_pwrseq_drv) = {
+ .name = "mmc_pwrseq_emmc",
+ .id = UCLASS_PWRSEQ,
+ .of_match = mmc_pwrseq_ids,
+ .ops = &mmc_pwrseq_ops,
+};
value);
return -EIO;
}
- if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
+ if (!ret && (status & MMC_STATUS_RDY_FOR_DATA) &&
+ (status & MMC_STATUS_CURR_STATE) == MMC_STATE_TRANS)
return 0;
udelay(100);
} while (get_timer(start) < timeout_ms);
static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
{
- int err;
+ int err = 0;
const struct mode_width_tuning *mwt;
const struct ext_csd_bus_width *ecbw;
#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
-/* Read and write blocks start with these tokens and end with crc;
+/*
+ * Read and write blocks start with these tokens and end with crc;
* on error, read tokens act like a subset of R2_SPI_* values.
*/
/* single block write multiblock read */
struct spi_slave *spi;
};
+/**
+ * mmc_spi_sendcmd() - send a command to the SD card
+ *
+ * @dev: mmc_spi device
+ * @cmdidx: command index
+ * @cmdarg: command argument
+ * @resp_type: card response type
+ * @resp: buffer to store the card response
+ * @resp_size: size of the card response
+ * @resp_match: if true, compare each of received bytes with @resp_match_value
+ * @resp_match_value: a value to be compared with each of received bytes
+ * @r1b: if true, receive additional bytes for busy signal token
+ * @return 0 if OK, -ETIMEDOUT if no card response is received, -ve on error
+ */
static int mmc_spi_sendcmd(struct udevice *dev,
ushort cmdidx, u32 cmdarg, u32 resp_type,
u8 *resp, u32 resp_size,
int i, rpos = 0, ret = 0;
u8 cmdo[7], r;
+ if (!resp || !resp_size)
+ return 0;
+
debug("%s: cmd%d cmdarg=0x%x resp_type=0x%x "
"resp_size=%d resp_match=%d resp_match_value=0x%x\n",
__func__, cmdidx, cmdarg, resp_type,
if (ret)
return ret;
- if (!resp || !resp_size)
- return 0;
-
debug("%s: cmd%d", __func__, cmdidx);
- if (resp_match) {
+ if (resp_match)
r = ~resp_match_value;
- i = CMD_TIMEOUT;
- while (i) {
- ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
- if (ret)
- return ret;
- debug(" resp%d=0x%x", rpos, r);
- rpos++;
- i--;
+ i = CMD_TIMEOUT;
+ while (i) {
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
+ if (ret)
+ return ret;
+ debug(" resp%d=0x%x", rpos, r);
+ rpos++;
+ i--;
+ if (resp_match) {
if (r == resp_match_value)
break;
+ } else {
+ if (!(r & 0x80))
+ break;
}
- if (!i && (r != resp_match_value))
+
+ if (!i)
return -ETIMEDOUT;
}
- for (i = 0; i < resp_size; i++) {
- if (i == 0 && resp_match) {
- resp[i] = resp_match_value;
- continue;
- }
+ resp[0] = r;
+ for (i = 1; i < resp_size; i++) {
ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
if (ret)
return ret;
return 0;
}
+/**
+ * mmc_spi_readdata() - read data block(s) from the SD card
+ *
+ * @dev: mmc_spi device
+ * @xbuf: buffer of the actual data (excluding token and crc) to read
+ * @bcnt: number of data blocks to transfer
+ * @bsize: size of the actual data (excluding token and crc) in bytes
+ * @return 0 if OK, -ECOMM if crc error, -ETIMEDOUT on other errors
+ */
static int mmc_spi_readdata(struct udevice *dev,
void *xbuf, u32 bcnt, u32 bsize)
{
if (ret)
return ret;
#ifdef CONFIG_MMC_SPI_CRC_ON
- if (be16_to_cpu(crc16_ccitt(0, buf, bsize)) != crc) {
- debug("%s: data crc error\n", __func__);
+ u16 crc_ok = be16_to_cpu(crc16_ccitt(0, buf, bsize));
+ if (crc_ok != crc) {
+ debug("%s: data crc error, expected %04x got %04x\n",
+ __func__, crc_ok, crc);
r1 = R1_SPI_COM_CRC;
break;
}
return ret;
}
+/**
+ * mmc_spi_writedata() - write data block(s) to the SD card
+ *
+ * @dev: mmc_spi device
+ * @xbuf: buffer of the actual data (excluding token and crc) to write
+ * @bcnt: number of data blocks to transfer
+ * @bsize: size of actual data (excluding token and crc) in bytes
+ * @multi: indicate a transfer by multiple block write command (CMD25)
+ * @return 0 if OK, -ECOMM if crc error, -ETIMEDOUT on other errors
+ */
static int mmc_spi_writedata(struct udevice *dev, const void *xbuf,
u32 bcnt, u32 bsize, int multi)
{
#include <malloc.h>
#include <sdhci.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <dm.h>
#include <malloc.h>
#include <sdhci.h>
+#include <asm/global_data.h>
#include <linux/mbus.h>
#define MVSDH_NAME "mv_sdh"
host->mmc->dev = dev;
host->mmc->priv = host;
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
return ret;
#include <malloc.h>
#include <part.h>
#include <mmc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <palmas.h>
#endif
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#ifdef CONFIG_OMAP54XX
#include <dm.h>
#include <sdhci.h>
#include <clk.h>
+#include <linux/errno.h>
+#include <mach/pic32.h>
struct pic32_sdhci_plat {
struct mmc_config cfg;
#include <malloc.h>
#include <mmc.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/compat.h>
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
- struct udevice *pwr_dev __maybe_unused;
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
host->fifo_mode = priv->fifo_mode;
-#ifdef CONFIG_PWRSEQ
+#ifdef CONFIG_MMC_PWRSEQ
/* Enable power if needed */
- ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
- &pwr_dev);
+ ret = mmc_pwrseq_get_power(dev, &plat->cfg);
if (!ret) {
- ret = pwrseq_set_power(pwr_dev, true);
+ ret = pwrseq_set_power(plat->cfg.pwr_dev, true);
if (ret)
return ret;
}
DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)
-
-#ifdef CONFIG_PWRSEQ
-static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
-{
- struct gpio_desc reset;
- int ret;
-
- ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
- if (ret)
- return ret;
- dm_gpio_set_value(&reset, 1);
- udelay(1);
- dm_gpio_set_value(&reset, 0);
- udelay(200);
-
- return 0;
-}
-
-static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
- .set_power = rockchip_dwmmc_pwrseq_set_power,
-};
-
-static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
- { .compatible = "mmc-pwrseq-emmc" },
- { }
-};
-
-U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
- .name = "mmc_pwrseq_emmc",
- .id = UCLASS_PWRSEQ,
- .of_match = rockchip_dwmmc_pwrseq_ids,
- .ops = &rockchip_dwmmc_pwrseq_ops,
-};
-#endif
#include <malloc.h>
#include <sdhci.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <asm/gpio.h>
#include <asm/arch/mmc.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <phys2bus.h>
+#include <power/regulator.h>
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
int *is_aligned, int trans_bytes)
{
+ dma_addr_t dma_addr;
unsigned char ctrl;
void *buf;
mmc_get_dma_dir(data));
if (host->flags & USE_SDMA) {
- sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
- SDHCI_DMA_ADDRESS);
+ dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
+ sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
}
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
else if (host->flags & (USE_ADMA | USE_ADMA64)) {
start_addr &=
~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
- sdhci_writel(host, phys_to_bus((ulong)start_addr),
- SDHCI_DMA_ADDRESS);
+ start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
+ start_addr);
+ sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
}
}
if (timeout-- > 0)
}
} while (!(stat & SDHCI_INT_DATA_END));
+#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
mmc_get_dma_dir(data));
+#endif
return 0;
}
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
}
+static void sdhci_set_voltage(struct sdhci_host *host)
+{
+ if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ switch (mmc->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
+ pr_err("failed to disable vqmmc-supply\n");
+ return;
+ }
+
+ if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
+ pr_err("failed to set vqmmc-voltage to 3.3V\n");
+ return;
+ }
+
+ if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
+ pr_err("failed to enable vqmmc-supply\n");
+ return;
+ }
+ }
+#endif
+ if (IS_SD(mmc)) {
+ ctrl &= ~SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
+
+ /* Wait for 5ms */
+ mdelay(5);
+
+ /* 3.3V regulator output should be stable within 5 ms */
+ if (IS_SD(mmc)) {
+ if (ctrl & SDHCI_CTRL_VDD_180) {
+ pr_err("3.3V regulator output did not become stable\n");
+ return;
+ }
+ }
+
+ break;
+ case MMC_SIGNAL_VOLTAGE_180:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
+ pr_err("failed to disable vqmmc-supply\n");
+ return;
+ }
+
+ if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
+ pr_err("failed to set vqmmc-voltage to 1.8V\n");
+ return;
+ }
+
+ if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
+ pr_err("failed to enable vqmmc-supply\n");
+ return;
+ }
+ }
+#endif
+ if (IS_SD(mmc)) {
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
+
+ /* Wait for 5 ms */
+ mdelay(5);
+
+ /* 1.8V regulator output has to be stable within 5 ms */
+ if (IS_SD(mmc)) {
+ if (!(ctrl & SDHCI_CTRL_VDD_180)) {
+ pr_err("1.8V regulator output did not become stable\n");
+ return;
+ }
+ }
+
+ break;
+ default:
+ /* No signal voltage switch required */
+ return;
+ }
+ }
+}
+
+void sdhci_set_control_reg(struct sdhci_host *host)
+{
+ sdhci_set_voltage(host);
+ sdhci_set_uhs_timing(host);
+}
+
#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
#include <linux/io.h>
#include <linux/sizes.h>
#include "sh_mmcif.h"
+#include <asm/global_data.h>
#define DRIVER_NAME "sh_mmcif"
#include <linux/sizes.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/sh_sdhi.h>
+#include <asm/global_data.h>
#include <clk.h>
#define DRIVER_NAME "sh-sdhi"
#include <dwmmc.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/intel-smc.h>
#include <linux/libfdt.h>
#include <reset-uclass.h>
#include <sdhci.h>
#include <asm/arch/sdhci.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <fdtdec.h>
#include <mmc.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/pinctrl.h>
#include <linux/compat.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <flash.h>
#include <log.h>
#include <mtd.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <init.h>
#include <irq_func.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <linux/err.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <asm/global_data.h>
#include <mtd.h>
#define MTD_NAME_MAX_LEN 20
if (ret)
return ret;
} else {
- ret = PTR_ERR(ctrl->clk);
- if (ret == -EPROBE_DEFER)
- return ret;
-
+ /* Ignore PTR_ERR(ctrl->clk) */
ctrl->clk = NULL;
}
EXPORT_SYMBOL(nand_get_flash_type);
#if CONFIG_IS_ENABLED(OF_CONTROL)
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand_bch.h>
#include <linux/mtd/nand_ecc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/types.h>
#include <asm/dma-mapping.h>
#include <malloc.h>
#include <fdtdec.h>
#include <nand.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/bitops.h>
#include <malloc.h>
#include <memalign.h>
#include <nand.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/bitops.h>
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <memalign.h>
#include <nand.h>
#include <flash.h>
#include <init.h>
#include <irq_func.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <mach/pic32.h>
#include <wait_bit.h>
#include <wait_bit.h>
#include <linux/bitops.h>
#include <mtd/cfi_flash.h>
+#include <asm/global_data.h>
#define RPC_CMNCR 0x0000 /* R/W */
#define RPC_CMNCR_MD BIT(31)
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
+config SPI_FLASH_UNLOCK_ALL
+ bool "Unlock the entire SPI flash on u-boot startup"
+ default y
+ help
+ Some flashes tend to power up with the software write protection
+ bits set. If this option is set, the whole flash will be unlocked.
+
+ For legacy reasons, this option default to y. But if you intend to
+ actually use the software protection bits you should say n here.
+
config SF_DUAL_FLASH
bool "SPI DUAL flash memory support"
help
#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include "sf_internal.h"
* Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
* with the software protection bits set
*/
- if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
- JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
- JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
- nor->info->flags & SPI_NOR_HAS_LOCK) {
+ if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) &&
+ (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
+ nor->info->flags & SPI_NOR_HAS_LOCK)) {
write_enable(nor);
write_sr(nor, 0);
spi_nor_wait_till_ready(nor);
This is currently implemented in net/mdio-mux-uclass.c
Look in include/miiphy.h for details.
+config DM_DSA
+ bool "Enable Driver Model for DSA switches"
+ depends on DM_ETH && DM_MDIO
+ depends on PHY_FIXED
+ help
+ Enable driver model for DSA switches
+
+ Adds UCLASS_DSA class supporting switches that follow the Distributed
+ Switch Architecture (DSA). These switches rely on the presence of a
+ management switch port connected to an Ethernet controller capable of
+ receiving frames from the switch. This host Ethernet controller is
+ called the "master" Ethernet interface in DSA terminology.
+ This is currently implemented in net/dsa-uclass.c, refer to
+ include/net/dsa.h for API details.
+
config MDIO_SANDBOX
depends on DM_MDIO && SANDBOX
default y
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
-obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_NS8382X) += ns8382x.o
obj-$(CONFIG_PCH_GBE) += pch_gbe.o
#include <malloc.h>
#include <net.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <miiphy.h>
#include <net.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/dma-mapping.h>
#include <asm/io.h>
#include "altera_tse.h"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-#include <common.h>
-#include <linux/delay.h>
-#include "ax88796.h"
-
-/*
- * Set 1 bit data
- */
-static void ax88796_bitset(u32 bit)
-{
- /* DATA1 */
- if( bit )
- EEDI_HIGH;
- else
- EEDI_LOW;
-
- EECLK_LOW;
- udelay(1000);
- EECLK_HIGH;
- udelay(1000);
- EEDI_LOW;
-}
-
-/*
- * Get 1 bit data
- */
-static u8 ax88796_bitget(void)
-{
- u8 bit;
-
- EECLK_LOW;
- udelay(1000);
- /* DATA */
- bit = EEDO;
- EECLK_HIGH;
- udelay(1000);
-
- return bit;
-}
-
-/*
- * Send COMMAND to EEPROM
- */
-static void ax88796_eep_cmd(u8 cmd)
-{
- ax88796_bitset(BIT_DUMMY);
- switch(cmd){
- case MAC_EEP_READ:
- ax88796_bitset(1);
- ax88796_bitset(1);
- ax88796_bitset(0);
- break;
-
- case MAC_EEP_WRITE:
- ax88796_bitset(1);
- ax88796_bitset(0);
- ax88796_bitset(1);
- break;
-
- case MAC_EEP_ERACE:
- ax88796_bitset(1);
- ax88796_bitset(1);
- ax88796_bitset(1);
- break;
-
- case MAC_EEP_EWEN:
- ax88796_bitset(1);
- ax88796_bitset(0);
- ax88796_bitset(0);
- break;
-
- case MAC_EEP_EWDS:
- ax88796_bitset(1);
- ax88796_bitset(0);
- ax88796_bitset(0);
- break;
- default:
- break;
- }
-}
-
-static void ax88796_eep_setaddr(u16 addr)
-{
- int i ;
-
- for( i = 7 ; i >= 0 ; i-- )
- ax88796_bitset(addr & (1 << i));
-}
-
-/*
- * Get data from EEPROM
- */
-static u16 ax88796_eep_getdata(void)
-{
- ushort data = 0;
- int i;
-
- ax88796_bitget(); /* DUMMY */
- for( i = 0 ; i < 16 ; i++ ){
- data <<= 1;
- data |= ax88796_bitget();
- }
- return data;
-}
-
-static void ax88796_mac_read(u8 *buff)
-{
- int i ;
- u16 data;
- u16 addr = 0;
-
- for( i = 0 ; i < 3; i++ )
- {
- EECS_HIGH;
- EEDI_LOW;
- udelay(1000);
- /* READ COMMAND */
- ax88796_eep_cmd(MAC_EEP_READ);
- /* ADDRESS */
- ax88796_eep_setaddr(addr++);
- /* GET DATA */
- data = ax88796_eep_getdata();
- *buff++ = (uchar)(data & 0xff);
- *buff++ = (uchar)((data >> 8) & 0xff);
- EECLK_LOW;
- EEDI_LOW;
- EECS_LOW;
- }
-}
-
-int get_prom(u8* mac_addr, u8* base_addr)
-{
- u8 prom[32];
- int i;
-
- ax88796_mac_read(prom);
- for (i = 0; i < 6; i++){
- mac_addr[i] = prom[i];
- }
- return 1;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * AX88796L(NE2000) support
- *
- * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __DRIVERS_AX88796L_H__
-#define __DRIVERS_AX88796L_H__
-
-#define DP_DATA (0x10 << 1)
-#define START_PG 0x40 /* First page of TX buffer */
-#define START_PG2 0x48
-#define STOP_PG 0x80 /* Last page +1 of RX ring */
-#define TX_PAGES 12
-#define RX_START (START_PG+TX_PAGES)
-#define RX_END STOP_PG
-
-#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE
-#define AX88796L_BYTE_ACCESS 0x00001000
-#define AX88796L_OFFSET 0x00000400
-#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \
- AX88796L_BYTE_ACCESS + AX88796L_OFFSET
-#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1)
-#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1)
-
-#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR))
-#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR))
-
-#define EECS_HIGH (AX88796L_MEMR |= 0x10)
-#define EECS_LOW (AX88796L_MEMR &= 0xef)
-#define EECLK_HIGH (AX88796L_MEMR |= 0x80)
-#define EECLK_LOW (AX88796L_MEMR &= 0x7f)
-#define EEDI_HIGH (AX88796L_MEMR |= 0x20)
-#define EEDI_LOW (AX88796L_MEMR &= 0xdf)
-#define EEDO ((AX88796L_MEMR & 0x40)>>6)
-
-#define PAGE0_SET (AX88796L_CR &= 0x3f)
-#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
-
-#define BIT_DUMMY 0
-#define MAC_EEP_READ 1
-#define MAC_EEP_WRITE 2
-#define MAC_EEP_ERACE 3
-#define MAC_EEP_EWEN 4
-#define MAC_EEP_EWDS 5
-
-/* R7780MP Specific code */
-#if defined(CONFIG_R7780MP)
-#define ISA_OFFSET 0x1400
-#define DP_IN(_b_, _o_, _d_) (_d_) = \
- *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
-#define DP_OUT(_b_, _o_, _d_) \
- *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
-#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
-#else
-/* Please change for your target boards */
-#define ISA_OFFSET 0x0000
-#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
-#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
-#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
-#endif
-
-#endif /* __DRIVERS_AX88796L_H__ */
struct eqos_config __maybe_unused eqos_imx_config = {
.reg_access_always_ok = false,
- .mdio_wait = 10000,
+ .mdio_wait = 10,
.swr_wait = 50,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
#include <net.h>
#include <netdev.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <power/regulator.h>
};
#endif
+#define MAX_NUM_RETRIES 1000
+
static u32 memac_in_32(u32 *reg)
{
#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
}
/*
+ * Wait until the MDIO bus is free
+ */
+static int memac_wait_until_free(struct memac_mdio_controller *regs)
+{
+ unsigned int timeout = MAX_NUM_RETRIES;
+
+ while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--)
+ ;
+
+ if (!timeout) {
+ printf("timeout waiting for MDIO bus to be free\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * Wait till the MDIO read or write operation is complete
+ */
+static int memac_wait_until_done(struct memac_mdio_controller *regs)
+{
+ unsigned int timeout = MAX_NUM_RETRIES;
+
+ while ((memac_in_32(®s->mdio_data) & MDIO_DATA_BSY) && timeout--)
+ ;
+
+ if (!timeout) {
+ printf("timeout waiting for MDIO operation to complete\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
* Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
struct memac_mdio_controller *regs;
u32 mdio_ctl;
u32 c45 = 1; /* Default to 10G interface */
+ int err;
#ifndef CONFIG_DM_ETH
regs = bus->priv;
} else
memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
- /* Wait till the bus is free */
- while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
- ;
+ err = memac_wait_until_free(regs);
+ if (err)
+ return err;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
if (c45)
memac_out_32(®s->mdio_addr, regnum & 0xffff);
- /* Wait till the bus is free */
- while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
- ;
+ err = memac_wait_until_free(regs);
+ if (err)
+ return err;
/* Write the value to the register */
memac_out_32(®s->mdio_data, MDIO_DATA(value));
- /* Wait till the MDIO write is complete */
- while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
- ;
+ err = memac_wait_until_done(regs);
+ if (err)
+ return err;
return 0;
}
struct memac_mdio_controller *regs;
u32 mdio_ctl;
u32 c45 = 1;
+ int err;
#ifndef CONFIG_DM_ETH
regs = bus->priv;
} else
memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
- /* Wait till the bus is free */
- while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
- ;
+ err = memac_wait_until_free(regs);
+ if (err)
+ return err;
/* Set the Port and Device Addrs */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
if (c45)
memac_out_32(®s->mdio_addr, regnum & 0xffff);
- /* Wait till the bus is free */
- while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
- ;
+ err = memac_wait_until_free(regs);
+ if (err)
+ return err;
/* Initiate the read */
mdio_ctl |= MDIO_CTL_READ;
memac_out_32(®s->mdio_ctl, mdio_ctl);
- /* Wait till the MDIO write is complete */
- while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
- ;
+ err = memac_wait_until_done(regs);
+ if (err)
+ return err;
/* Return all Fs if nothing was there */
if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
#include <image.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/bug.h>
#include <asm/io.h>
#include <linux/delay.h>
return -EINVAL;
}
- if (!fit_check_format(fit_hdr)) {
+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
return -EINVAL;
}
/* PCS replicator block for USXGMII */
#define ENETC_PCS_DEVAD_REPL 0x1f
+#define ENETC_PCS_REPL_LINK_TIMER_1 0x12
+#define ENETC_PCS_REPL_LINK_TIMER_1_DEF 0x0003
+#define ENETC_PCS_REPL_LINK_TIMER_2 0x13
+#define ENETC_PCS_REPL_LINK_TIMER_2_DEF 0x06a0
+
/* ENETC external MDIO registers */
#define ENETC_MDIO_BASE 0x1c00
#define ENETC_MDIO_CFG 0x00
#include <config.h>
#include <net.h>
#include <miiphy.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <asm/immap.h>
#include <env.h>
#include <malloc.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/io.h>
*/
static void ftmac100_reset(struct ftmac100_data *priv)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
debug ("%s()\n", __func__);
static void ftmac100_set_mac(struct ftmac100_data *priv ,
const unsigned char *mac)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
unsigned int maddr = mac[0] << 8 | mac[1];
unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
*/
static void _ftmac100_halt(struct ftmac100_data *priv)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
debug ("%s()\n", __func__);
writel (0, &ftmac100->maccr);
}
*/
static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6])
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
struct ftmac100_txdes *txdes = priv->txdes;
struct ftmac100_rxdes *rxdes = priv->rxdes;
unsigned int maccr;
*/
static int _ftmac100_send(struct ftmac100_data *priv, void *packet, int length)
{
- struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase;
+ struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase;
struct ftmac100_txdes *curr_des = priv->txdes;
ulong start;
#include <net.h>
#include <phy.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/clock.h>
#include <linux/bug.h>
#include <linux/compat.h>
#include <linux/delay.h>
+#include <asm/global_data.h>
#include "ldpaa_eth.h"
#ifdef CONFIG_PHYLIB
#include <cpu_func.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
/*
#include <net.h>
#include <miiphy.h>
#include <asm/fec.h>
+#include <asm/global_data.h>
#include <asm/immap.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#ifdef CONFIG_MCF547x_8x
#include <net.h>
#include <netdev.h>
#include <asm/cpm_8xx.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
select PHYLIB
help
This driver supports the Serval network switch device.
+
+config MSCC_FELIX_SWITCH
+ bool "Felix switch driver"
+ depends on DM_DSA && DM_PCI
+ select FSL_ENETC
+ help
+ This driver supports the Ethernet switch integrated in the
+ NXP LS1028A SoC.
obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o mscc_miim.o
obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o mscc_miim.o
obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o mscc_miim.o
+obj-$(CONFIG_MSCC_FELIX_SWITCH) += felix_switch.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Felix (VSC9959) Ethernet switch driver
+ * Copyright 2018-2021 NXP Semiconductors
+ */
+
+/*
+ * This driver is used for the Ethernet switch integrated into NXP LS1028A.
+ * Felix switch is derived from Microsemi Ocelot but there are several NXP
+ * adaptations that makes the two U-Boot drivers largely incompatible.
+ *
+ * Felix on LS1028A has 4 front panel ports and two internal ports, connected
+ * to ENETC interfaces. We're using one of the ENETC interfaces to push traffic
+ * into the switch. Injection/extraction headers are used to identify
+ * egress/ingress ports in the switch for Tx/Rx.
+ */
+
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <net/dsa.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <pci.h>
+
+/* defines especially around PCS are reused from enetc */
+#include "../fsl_enetc.h"
+
+#define PCI_DEVICE_ID_FELIX_ETHSW 0xEEF0
+
+/* Felix has in fact 6 ports, but we don't use the last internal one */
+#define FELIX_PORT_COUNT 5
+/* Front panel port mask */
+#define FELIX_FP_PORT_MASK 0xf
+
+/* Register map for BAR4 */
+#define FELIX_SYS 0x010000
+#define FELIX_ES0 0x040000
+#define FELIX_IS1 0x050000
+#define FELIX_IS2 0x060000
+#define FELIX_GMII(port) (0x100000 + (port) * 0x10000)
+#define FELIX_QSYS 0x200000
+
+#define FELIX_SYS_SYSTEM (FELIX_SYS + 0x00000E00)
+#define FELIX_SYS_SYSTEM_EN BIT(0)
+#define FELIX_SYS_RAM_CTRL (FELIX_SYS + 0x00000F24)
+#define FELIX_SYS_RAM_CTRL_INIT BIT(1)
+#define FELIX_SYS_SYSTEM_PORT_MODE(a) (FELIX_SYS_SYSTEM + 0xC + (a) * 4)
+#define FELIX_SYS_SYSTEM_PORT_MODE_CPU 0x0000001e
+
+#define FELIX_ES0_TCAM_CTRL (FELIX_ES0 + 0x000003C0)
+#define FELIX_ES0_TCAM_CTRL_EN BIT(0)
+#define FELIX_IS1_TCAM_CTRL (FELIX_IS1 + 0x000003C0)
+#define FELIX_IS1_TCAM_CTRL_EN BIT(0)
+#define FELIX_IS2_TCAM_CTRL (FELIX_IS2 + 0x000003C0)
+#define FELIX_IS2_TCAM_CTRL_EN BIT(0)
+
+#define FELIX_GMII_CLOCK_CFG(port) (FELIX_GMII(port) + 0x00000000)
+#define FELIX_GMII_CLOCK_CFG_LINK_1G 1
+#define FELIX_GMII_CLOCK_CFG_LINK_100M 2
+#define FELIX_GMII_CLOCK_CFG_LINK_10M 3
+#define FELIX_GMII_MAC_ENA_CFG(port) (FELIX_GMII(port) + 0x0000001C)
+#define FELIX_GMII_MAX_ENA_CFG_TX BIT(0)
+#define FELIX_GMII_MAX_ENA_CFG_RX BIT(4)
+#define FELIX_GMII_MAC_IFG_CFG(port) (FELIX_GMII(port) + 0x0000001C + 0x14)
+#define FELIX_GMII_MAC_IFG_CFG_DEF 0x515
+
+#define FELIX_QSYS_SYSTEM (FELIX_QSYS + 0x0000F460)
+#define FELIX_QSYS_SYSTEM_SW_PORT_MODE(a) \
+ (FELIX_QSYS_SYSTEM + 0x20 + (a) * 4)
+#define FELIX_QSYS_SYSTEM_SW_PORT_ENA BIT(14)
+#define FELIX_QSYS_SYSTEM_SW_PORT_LOSSY BIT(9)
+#define FELIX_QSYS_SYSTEM_SW_PORT_SCH(a) (((a) & 0x3800) << 11)
+#define FELIX_QSYS_SYSTEM_EXT_CPU_CFG (FELIX_QSYS_SYSTEM + 0x80)
+#define FELIX_QSYS_SYSTEM_EXT_CPU_PORT(a) (((a) & 0xf) << 8 | 0xff)
+
+/* internal MDIO in BAR0 */
+#define FELIX_PM_IMDIO_BASE 0x8030
+
+/* Serdes block on LS1028A */
+#define FELIX_SERDES_BASE 0x1ea0000L
+#define FELIX_SERDES_LNATECR0(lane) (FELIX_SERDES_BASE + 0x818 + \
+ (lane) * 0x40)
+#define FELIX_SERDES_LNATECR0_ADPT_EQ 0x00003000
+#define FELIX_SERDES_SGMIICR1(lane) (FELIX_SERDES_BASE + 0x1804 + \
+ (lane) * 0x10)
+#define FELIX_SERDES_SGMIICR1_SGPCS BIT(11)
+#define FELIX_SERDES_SGMIICR1_MDEV(a) (((a) & 0x1f) << 27)
+
+#define FELIX_PCS_CTRL 0
+#define FELIX_PCS_CTRL_RST BIT(15)
+
+/*
+ * The long prefix format used here contains two dummy MAC addresses, a magic
+ * value in place of a VLAN tag followed by the extraction/injection header and
+ * the original L2 frame. Out of all this we only use the port ID.
+ */
+#define FELIX_DSA_TAG_LEN sizeof(struct felix_dsa_tag)
+#define FELIX_DSA_TAG_MAGIC 0x0a008088
+#define FELIX_DSA_TAG_INJ_PORT 7
+#define FELIX_DSA_TAG_INJ_PORT_SET(a) (0x1 << ((a) & FELIX_FP_PORT_MASK))
+#define FELIX_DSA_TAG_EXT_PORT 10
+#define FELIX_DSA_TAG_EXT_PORT_GET(a) ((a) >> 3)
+
+struct felix_dsa_tag {
+ uchar d_mac[6];
+ uchar s_mac[6];
+ u32 magic;
+ uchar meta[16];
+};
+
+struct felix_priv {
+ void *regs_base;
+ void *imdio_base;
+ struct mii_dev imdio;
+};
+
+/* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
+static int felix_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct enetc_mdio_priv priv;
+
+ priv.regs_base = bus->priv;
+ return enetc_mdio_read_priv(&priv, addr, devad, reg);
+}
+
+static int felix_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct enetc_mdio_priv priv;
+
+ priv.regs_base = bus->priv;
+ return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
+}
+
+/* set up serdes for SGMII */
+static void felix_init_sgmii(struct mii_dev *imdio, int pidx, bool an)
+{
+ u16 reg;
+
+ /* set up PCS lane address */
+ out_le32(FELIX_SERDES_SGMIICR1(pidx), FELIX_SERDES_SGMIICR1_SGPCS |
+ FELIX_SERDES_SGMIICR1_MDEV(pidx));
+
+ /*
+ * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
+ * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
+ * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
+ * but intentional.
+ */
+ reg = ENETC_PCS_IF_MODE_SGMII;
+ reg |= an ? ENETC_PCS_IF_MODE_SGMII_AN : ENETC_PCS_IF_MODE_SPEED_1G;
+ felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
+ ENETC_PCS_IF_MODE, reg);
+
+ /* Dev ability - SGMII */
+ felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
+ ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
+
+ /* Adjust link timer for SGMII */
+ felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
+ ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
+ felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
+ ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
+
+ reg = ENETC_PCS_CR_DEF_VAL;
+ reg |= an ? ENETC_PCS_CR_RESET_AN : ENETC_PCS_CR_RST;
+ /* restart PCS AN */
+ felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
+ ENETC_PCS_CR, reg);
+}
+
+/* set up MAC and serdes for (Q)SXGMII */
+static int felix_init_sxgmii(struct mii_dev *imdio, int pidx)
+{
+ int timeout = 1000;
+
+ /* set up transit equalization control on serdes lane */
+ out_le32(FELIX_SERDES_LNATECR0(1), FELIX_SERDES_LNATECR0_ADPT_EQ);
+
+ /*reset lane */
+ felix_mdio_write(imdio, pidx, MDIO_MMD_PCS, FELIX_PCS_CTRL,
+ FELIX_PCS_CTRL_RST);
+ while (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS,
+ FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST &&
+ --timeout) {
+ mdelay(10);
+ }
+ if (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS,
+ FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST)
+ return -ETIME;
+
+ /* Dev ability - SXGMII */
+ felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
+ ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
+
+ /* Restart PCS AN */
+ felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL, ENETC_PCS_CR,
+ ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
+ felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
+ ENETC_PCS_REPL_LINK_TIMER_1,
+ ENETC_PCS_REPL_LINK_TIMER_1_DEF);
+ felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
+ ENETC_PCS_REPL_LINK_TIMER_2,
+ ENETC_PCS_REPL_LINK_TIMER_2_DEF);
+
+ return 0;
+}
+
+/* Apply protocol specific configuration to MAC, serdes as needed */
+static void felix_start_pcs(struct udevice *dev, int port,
+ struct phy_device *phy, struct mii_dev *imdio)
+{
+ bool autoneg = true;
+
+ if (phy->phy_id == PHY_FIXED_ID ||
+ phy->interface == PHY_INTERFACE_MODE_SGMII_2500)
+ autoneg = false;
+
+ switch (phy->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_QSGMII:
+ felix_init_sgmii(imdio, port, autoneg);
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_USXGMII:
+ if (felix_init_sxgmii(imdio, port))
+ dev_err(dev, "PCS reset timeout on port %d\n", port);
+ break;
+ default:
+ break;
+ }
+}
+
+void felix_init(struct udevice *dev)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct felix_priv *priv = dev_get_priv(dev);
+ void *base = priv->regs_base;
+ int timeout = 100;
+
+ /* Init core memories */
+ out_le32(base + FELIX_SYS_RAM_CTRL, FELIX_SYS_RAM_CTRL_INIT);
+ while (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT &&
+ --timeout)
+ udelay(10);
+ if (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT)
+ dev_err(dev, "Timeout waiting for switch memories\n");
+
+ /* Start switch core, set up ES0, IS1, IS2 */
+ out_le32(base + FELIX_SYS_SYSTEM, FELIX_SYS_SYSTEM_EN);
+ out_le32(base + FELIX_ES0_TCAM_CTRL, FELIX_ES0_TCAM_CTRL_EN);
+ out_le32(base + FELIX_IS1_TCAM_CTRL, FELIX_IS1_TCAM_CTRL_EN);
+ out_le32(base + FELIX_IS2_TCAM_CTRL, FELIX_IS2_TCAM_CTRL_EN);
+ udelay(20);
+
+ priv->imdio.read = felix_mdio_read;
+ priv->imdio.write = felix_mdio_write;
+ priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
+ strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+
+ /* set up CPU port */
+ out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG,
+ FELIX_QSYS_SYSTEM_EXT_CPU_PORT(pdata->cpu_port));
+ out_le32(base + FELIX_SYS_SYSTEM_PORT_MODE(pdata->cpu_port),
+ FELIX_SYS_SYSTEM_PORT_MODE_CPU);
+}
+
+/*
+ * Probe Felix:
+ * - enable the PCI function
+ * - map BAR 4
+ * - init switch core and port registers
+ */
+static int felix_probe(struct udevice *dev)
+{
+ struct felix_priv *priv = dev_get_priv(dev);
+
+ if (ofnode_valid(dev_ofnode(dev)) &&
+ !ofnode_is_available(dev_ofnode(dev))) {
+ dev_dbg(dev, "switch disabled\n");
+ return -ENODEV;
+ }
+
+ priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
+ if (!priv->imdio_base) {
+ dev_err(dev, "failed to map BAR0\n");
+ return -EINVAL;
+ }
+
+ priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0);
+ if (!priv->regs_base) {
+ dev_err(dev, "failed to map BAR4\n");
+ return -EINVAL;
+ }
+
+ /* register internal MDIO for debug */
+ if (!miiphy_get_dev_by_name(dev->name)) {
+ struct mii_dev *mii_bus;
+
+ mii_bus = mdio_alloc();
+ mii_bus->read = felix_mdio_read;
+ mii_bus->write = felix_mdio_write;
+ mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
+ strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
+ mdio_register(mii_bus);
+ }
+
+ dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
+
+ dsa_set_tagging(dev, FELIX_DSA_TAG_LEN, 0);
+
+ /* set up registers */
+ felix_init(dev);
+
+ return 0;
+}
+
+static int felix_port_enable(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
+ struct felix_priv *priv = dev_get_priv(dev);
+ void *base = priv->regs_base;
+
+ /* Set up MAC registers */
+ out_le32(base + FELIX_GMII_CLOCK_CFG(port),
+ FELIX_GMII_CLOCK_CFG_LINK_1G);
+
+ out_le32(base + FELIX_GMII_MAC_IFG_CFG(port),
+ FELIX_GMII_MAC_IFG_CFG_DEF);
+
+ out_le32(base + FELIX_GMII_MAC_ENA_CFG(port),
+ FELIX_GMII_MAX_ENA_CFG_TX | FELIX_GMII_MAX_ENA_CFG_RX);
+
+ out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(port),
+ FELIX_QSYS_SYSTEM_SW_PORT_ENA |
+ FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
+ FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
+
+ felix_start_pcs(dev, port, phy, &priv->imdio);
+
+ phy->supported &= supported;
+ phy->advertising &= supported;
+ phy_config(phy);
+
+ phy_startup(phy);
+
+ return 0;
+}
+
+static void felix_port_disable(struct udevice *dev, int pidx,
+ struct phy_device *phy)
+{
+ struct felix_priv *priv = dev_get_priv(dev);
+ void *base = priv->regs_base;
+
+ out_le32(base + FELIX_GMII_MAC_ENA_CFG(pidx), 0);
+
+ out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(pidx),
+ FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
+ FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
+
+ /*
+ * we don't call phy_shutdown here to avoid waiting next time we use
+ * the port, but the downside is that remote side will think we're
+ * actively processing traffic although we are not.
+ */
+}
+
+static int felix_xmit(struct udevice *dev, int pidx, void *packet, int length)
+{
+ struct felix_dsa_tag *tag = packet;
+
+ tag->magic = FELIX_DSA_TAG_MAGIC;
+ tag->meta[FELIX_DSA_TAG_INJ_PORT] = FELIX_DSA_TAG_INJ_PORT_SET(pidx);
+
+ return 0;
+}
+
+static int felix_rcv(struct udevice *dev, int *pidx, void *packet, int length)
+{
+ struct felix_dsa_tag *tag = packet;
+
+ if (tag->magic != FELIX_DSA_TAG_MAGIC)
+ return -EINVAL;
+
+ *pidx = FELIX_DSA_TAG_EXT_PORT_GET(tag->meta[FELIX_DSA_TAG_EXT_PORT]);
+
+ return 0;
+}
+
+static const struct dsa_ops felix_dsa_ops = {
+ .port_enable = felix_port_enable,
+ .port_disable = felix_port_disable,
+ .xmit = felix_xmit,
+ .rcv = felix_rcv,
+};
+
+U_BOOT_DRIVER(felix_ethsw) = {
+ .name = "felix-switch",
+ .id = UCLASS_DSA,
+ .probe = felix_probe,
+ .ops = &felix_dsa_ops,
+ .priv_auto = sizeof(struct felix_priv),
+};
+
+static struct pci_device_id felix_ethsw_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_FELIX_ETHSW) },
+ {}
+};
+
+U_BOOT_PCI_DEVICE(felix_ethsw, felix_ethsw_ids);
#include <malloc.h>
#include <miiphy.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <config.h>
#include <malloc.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <cpu_func.h>
#include <dm.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <pci.h>
#include <pci_ids.h>
#include <phy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/ctype.h>
#include <linux/delay.h>
return ret;
}
- if (!fit_check_format(pfe_fit_addr)) {
+ if (fit_check_format(pfe_fit_addr, IMAGE_SIZE_INVAL)) {
printf("PFE Firmware: Bad firmware image (bad FIT header)\n");
ret = -1;
return ret;
#include <phy.h>
#include <dm.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
/* check for mandatory properties within fixed-link node */
val = fdt_getprop_u32_default_node(gd->fdt_blob,
ofnode, 0, "speed", 0);
- if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000) {
+ if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000 &&
+ val != SPEED_2500 && val != SPEED_10000) {
printf("ERROR: no/invalid speed given in fixed-link node!");
return -EINVAL;
}
#include <ioports.h>
#include <ppc_asm.tmpl>
#include <miiphy.h>
+#include <asm/global_data.h>
#define BB_MII_RELOCATE(v,off) (v += (v?off:0))
#include <miiphy.h>
#include <phy.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#endif
#ifdef CONFIG_PHY_FIXED
+/**
+ * fixed_phy_create() - create an unconnected fixed-link pseudo-PHY device
+ * @node: OF node for the container of the fixed-link node
+ *
+ * Description: Creates a struct phy_device based on a fixed-link of_node
+ * description. Can be used without phy_connect by drivers which do not expose
+ * a UCLASS_ETH udevice.
+ */
+struct phy_device *fixed_phy_create(ofnode node)
+{
+ phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
+ const char *if_str;
+ ofnode subnode;
+
+ if_str = ofnode_read_string(node, "phy-mode");
+ if (!if_str) {
+ if_str = ofnode_read_string(node, "phy-interface-type");
+ }
+ if (if_str) {
+ interface = phy_get_interface_by_name(if_str);
+ }
+
+ subnode = ofnode_find_subnode(node, "fixed-link");
+ if (!ofnode_valid(subnode)) {
+ return NULL;
+ }
+
+ return phy_device_create(NULL, ofnode_to_offset(subnode), PHY_FIXED_ID,
+ false, interface);
+}
+
#ifdef CONFIG_DM_ETH
static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
struct udevice *dev,
* Copyright (C) 2018 Xilinx, Inc.
*/
+#include <common.h>
#include <dm.h>
#include <log.h>
#include <phy.h>
-#include <config.h>
-#include <common.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <console.h>
#include <time.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <errno.h>
#include <memalign.h>
#include <miiphy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include "dm_qe_uec.h"
break;
default:
return -EINVAL;
- }
- break;
+ }
+ break;
case SPEED_1000:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
switch (enet_if_mode) {
int grace_stopped_tx;
int grace_stopped_rx;
int the_first_run;
-#if !defined(COFIG_DM)
+#if !defined(CONFIG_DM)
/* PHY specific */
struct uec_mii_info *mii_info;
int oldspeed;
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
/* Registers */
#include <env.h>
#include <malloc.h>
#include <net.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <malloc.h>
#include <net.h>
#include <asm/eth.h>
+#include <asm/global_data.h>
#include <asm/test.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/cache.h>
#include <linux/delay.h>
#include <linux/errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#ifdef CONFIG_DM_ETH
#define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
/* The ethernet controller needs to use physical addresses */
-#if defined(CONFIG_SH_32BIT)
-#define ADDR_TO_PHY(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0x40000000))
-#else
#define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
-#endif
#elif defined(CONFIG_ARM)
#ifndef inl
#define inl readl
#include <reset.h>
#include <syscon.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <cpsw.h>
#include <dm/device_compat.h>
#include <common.h>
#include <command.h>
#include <console.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <dm.h>
#include <log.h>
#include <net.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <dm.h>
#include <console.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
- default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A
+ default "fsl,lx2160a-pcie" if ARCH_LX2160A
+ default "fsl,ls2088a-pcie" if ARCH_LX2162A
default "fsl,ls1021a-pcie" if ARCH_LS1021A
help
This compatible is used to find pci controller node in Kernel DT
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
- default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A
+ default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
default "fsl,ls-pcie-ep"
help
This compatible is used to find pci controller ep node in Kernel DT
#include <log.h>
#include <malloc.h>
#include <asm/fsl_serdes.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#include <pci.h>
#include <wait_bit.h>
#include <linux/bitops.h>
+#include <linux/log2.h>
#define PCIECAR 0x000010
#define PCIECCTLR 0x000018
struct rcar_gen3_pcie_priv *priv = dev_get_plat(udev);
u32 reg = where & ~3;
+ /* Root bus */
+ if (PCI_DEV(bdf) == 0) {
+ if (access_type == RCAR_PCI_ACCESS_READ)
+ *data = readl(priv->regs + PCICONF(where / 4));
+ else
+ writel(*data, priv->regs + PCICONF(where / 4));
+
+ return 0;
+ }
+
/* Clear errors */
clrbits_le32(priv->regs + PCIEERRFR, 0);
{
u32 slot;
+ if (PCI_BUS(d))
+ return -EINVAL;
+
if (PCI_FUNC(d))
return -EINVAL;
slot = PCI_DEV(d);
- if (slot != 1)
+ if (slot > 1)
return -EINVAL;
return 0;
if (hose->regions[i].phys_start == 0)
continue;
- mask = (hose->regions[i].size - 1) & ~0xf;
+ mask = (roundup_pow_of_two(hose->regions[i].size) - 1) & ~0xf;
mask |= LAR_ENABLE;
- writel(hose->regions[i].phys_start, priv->regs + PCIEPRAR(0));
- writel(hose->regions[i].phys_start, priv->regs + PCIELAR(0));
+ writel(rounddown_pow_of_two(hose->regions[i].phys_start),
+ priv->regs + PCIEPRAR(0));
+ writel(rounddown_pow_of_two(hose->regions[i].phys_start),
+ priv->regs + PCIELAR(0));
writel(mask, priv->regs + PCIELAMR(0));
break;
}
- writel(0, priv->regs + PCIEPRAR(4));
- writel(0, priv->regs + PCIELAR(4));
- writel(0, priv->regs + PCIELAMR(4));
+ writel(0, priv->regs + PCIEPRAR(1));
+ writel(0, priv->regs + PCIELAR(1));
+ writel(0, priv->regs + PCIELAMR(1));
ret = rcar_gen3_pcie_hw_init(dev);
if (ret)
#include <log.h>
#include <malloc.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <common.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <command.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/of_access.h>
u32 reg;
u32 data;
- debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
- PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
-
- /* Only allow one other device besides the local one on the local bus */
- if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
- if (local_dev == 0 && PCI_DEV(bdf) != 1) {
- debug("- out of range\n");
- /*
- * If local dev is 0, the first other dev can
- * only be 1
- */
- *valuep = pci_get_ff(size);
- return 0;
- } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
- debug("- out of range\n");
- /*
- * If local dev is not 0, the first other dev can
- * only be 0
- */
- *valuep = pci_get_ff(size);
- return 0;
- }
+ debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
+ local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+
+ /* Don't access the local host controller via this API */
+ if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
+ debug("- skipping host controller\n");
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ /* If local dev is 0, the first other dev can only be 1 */
+ if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
+ debug("- out of range\n");
+ *valuep = pci_get_ff(size);
+ return 0;
}
/* write address */
int local_dev = PCI_DEV(pcie->dev);
u32 data;
- debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
- PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
+ local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
- /* Only allow one other device besides the local one on the local bus */
- if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
- if (local_dev == 0 && PCI_DEV(bdf) != 1) {
- /*
- * If local dev is 0, the first other dev can
- * only be 1
- */
- return 0;
- } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
- /*
- * If local dev is not 0, the first other dev can
- * only be 0
- */
- return 0;
- }
+ /* Don't access the local host controller via this API */
+ if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
+ debug("- skipping host controller\n");
+ return 0;
+ }
+
+ /* If local dev is 0, the first other dev can only be 1 */
+ if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
+ debug("- out of range\n");
+ return 0;
}
writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
#include <log.h>
#include <malloc.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <video.h>
#include <video_fb.h>
#include <acpi/acpi_s3.h>
+#include <asm/global_data.h>
#include <linux/screen_info.h>
DECLARE_GLOBAL_DATA_PTR;
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
struct brcm_pcie *pcie = dev_get_priv(dev);
void __iomem *base = pcie->base;
+ struct pci_region region;
bool ssc_good = false;
int num_out_wins = 0;
u64 rc_bar2_offset, rc_bar2_size;
MISC_CTRL_SCB_ACCESS_EN_MASK |
MISC_CTRL_CFG_READ_UR_MODE_MASK |
MISC_CTRL_MAX_BURST_SIZE_128);
- /*
- * TODO: When support for other SoCs than BCM2711 is added we may
- * need to use the base address and size(s) provided in the dma-ranges
- * property.
- */
- rc_bar2_offset = 0;
- rc_bar2_size = 0xc0000000;
+
+ pci_get_dma_regions(dev, ®ion, 0);
+ rc_bar2_offset = region.bus_start - region.phys_start;
+ rc_bar2_size = 1ULL << fls64(region.size - 1);
tmp = lower_32_bits(rc_bar2_offset);
u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
return 0;
}
+static int brcm_pcie_remove(struct udevice *dev)
+{
+ struct brcm_pcie *pcie = dev_get_priv(dev);
+ void __iomem *base = pcie->base;
+
+ /* Assert fundamental reset */
+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK);
+
+ /* Turn off SerDes */
+ setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
+ PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
+
+ /* Shutdown bridge */
+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
+
+ return 0;
+}
+
static int brcm_pcie_of_to_plat(struct udevice *dev)
{
struct brcm_pcie *pcie = dev_get_priv(dev);
.ops = &brcm_pcie_ops,
.of_match = brcm_pcie_ids,
.probe = brcm_pcie_probe,
+ .remove = brcm_pcie_remove,
.of_to_plat = brcm_pcie_of_to_plat,
.priv_auto = sizeof(struct brcm_pcie),
+ .flags = DM_FLAG_OS_PREPARE,
};
#include <dm.h>
#include <log.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <linux/delay.h>
#include <reset.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <dm/device_compat.h>
#include <power-domain.h>
#include <regmap.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <dm/device_compat.h>
#include <common.h>
#include <dm.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_serdes.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include "pcie_fsl.h"
#include <common.h>
#include <dm.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
.probe = iproc_pcie_probe,
.remove = iproc_pcie_remove,
.priv_auto = sizeof(struct iproc_pcie),
- .flags = DM_REMOVE_OS_PREPARE,
+ .flags = DM_FLAG_OS_PREPARE,
};
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
#include <pci.h>
#include <linux/sizes.h>
+#include <asm/arch-fsl-layerscape/svr.h>
+#include <asm/arch-ls102xa/svr.h>
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
/* CS2 */
#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
-#define SVR_LS102XA 0
-#define SVR_VAR_PER_SHIFT 8
-#define SVR_LS102XA_MASK 0x700
-#define SVR_LS2088A 0x870900
-#define SVR_LS2084A 0x870910
-#define SVR_LS2048A 0x870920
-#define SVR_LS2044A 0x870930
-#define SVR_LS2081A 0x870918
-#define SVR_LS2041A 0x870914
-
/* LS1021a PCIE space */
#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/devres.h>
#include <errno.h>
#include <pci_ep.h>
#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
+#include <linux/libfdt.h>
#include "pcie_layerscape_fixup_common.h"
void ft_pci_setup(void *blob, struct bd_info *bd)
#include <log.h>
#include <asm/arch/fsl_serdes.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
#include <common.h>
#include <dm.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
/**
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <generic-phy.h>
#include <pci.h>
#include <common.h>
#include <dm.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <linux/log2.h>
#include <pci_ep.h>
#include <dm.h>
#include <errno.h>
#include <pci_ep.h>
+#include <asm/global_data.h>
#include <linux/sizes.h>
#include <linux/log2.h>
#include "pcie-cadence.h"
This is useful when a driver uses the PHY framework but no real PHY
hardware exists.
+config MIPI_DPHY_HELPERS
+ bool "MIPI D-PHY support helpers"
+ help
+ Provides a number of helpers a core functions for MIPI D-PHY drivers.
+
config BCM6318_USBH_PHY
bool "BCM6318 USBH PHY support"
depends on PHY && ARCH_BMIPS
This is the generic phy driver for the Amlogic Meson G12A
USB2 and USB3 PHYS.
+config MESON_AXG_MIPI_DPHY
+ bool "Amlogic Meson AXG MIPI D-PHY"
+ depends on PHY && ARCH_MESON && MESON_AXG
+ select MIPI_DPHY_HELPERS
+ imply REGMAP
+ help
+ This is the generic phy driver for the Amlogic Meson AXG
+ MIPI D-PHY.
+
+config MESON_AXG_MIPI_PCIE_ANALOG_PHY
+ bool "Amlogic Meson AXG MIPI PCIe Analog PHY"
+ depends on PHY && ARCH_MESON && MESON_AXG
+ select MIPI_DPHY_HELPERS
+ imply REGMAP
+ help
+ This is the generic phy driver for the Amlogic Meson AXG
+ MIPI PCIe Analog PHY.
+
config MSM8916_USB_PHY
bool "Qualcomm MSM8916 USB PHY support"
depends on PHY
obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
+obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o
obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o
obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o
+obj-$(CONFIG_MESON_AXG_MIPI_DPHY) += meson-axg-mipi-dphy.o
+obj-$(CONFIG_MESON_AXG_MIPI_PCIE_ANALOG_PHY) += meson-axg-mipi-pcie-analog.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
#include <common.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#include <common.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/arch/cpu.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Meson AXG MIPI DPHY driver
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <reset.h>
+#include <clk.h>
+#include <phy-mipi-dphy.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
+/* [31] soft reset for the phy.
+ * 1: reset. 0: dessert the reset.
+ * [30] clock lane soft reset.
+ * [29] data byte lane 3 soft reset.
+ * [28] data byte lane 2 soft reset.
+ * [27] data byte lane 1 soft reset.
+ * [26] data byte lane 0 soft reset.
+ * [25] mipi dsi pll clock selection.
+ * 1: clock from fixed 850Mhz clock source. 0: from VID2 PLL.
+ * [12] mipi HSbyteclk enable.
+ * [11] mipi divider clk selection.
+ * 1: select the mipi DDRCLKHS from clock divider.
+ * 0: from PLL clock.
+ * [10] mipi clock divider control.
+ * 1: /4. 0: /2.
+ * [9] mipi divider output enable.
+ * [8] mipi divider counter enable.
+ * [7] PLL clock enable.
+ * [5] LPDT data endian.
+ * 1 = transfer the high bit first. 0 : transfer the low bit first.
+ * [4] HS data endian.
+ * [3] force data byte lane in stop mode.
+ * [2] force data byte lane 0 in receiver mode.
+ * [1] write 1 to sync the txclkesc input. the internal logic have to
+ * use txclkesc to decide Txvalid and Txready.
+ * [0] enalbe the MIPI DPHY TxDDRClk.
+ */
+#define MIPI_DSI_PHY_CTRL 0x0
+
+/* [31] clk lane tx_hs_en control selection.
+ * 1: from register. 0: use clk lane state machine.
+ * [30] register bit for clock lane tx_hs_en.
+ * [29] clk lane tx_lp_en contrl selection.
+ * 1: from register. 0: from clk lane state machine.
+ * [28] register bit for clock lane tx_lp_en.
+ * [27] chan0 tx_hs_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [26] register bit for chan0 tx_hs_en.
+ * [25] chan0 tx_lp_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [24] register bit from chan0 tx_lp_en.
+ * [23] chan0 rx_lp_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [22] register bit from chan0 rx_lp_en.
+ * [21] chan0 contention detection enable control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [20] register bit from chan0 contention dectection enable.
+ * [19] chan1 tx_hs_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [18] register bit for chan1 tx_hs_en.
+ * [17] chan1 tx_lp_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [16] register bit from chan1 tx_lp_en.
+ * [15] chan2 tx_hs_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [14] register bit for chan2 tx_hs_en.
+ * [13] chan2 tx_lp_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [12] register bit from chan2 tx_lp_en.
+ * [11] chan3 tx_hs_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [10] register bit for chan3 tx_hs_en.
+ * [9] chan3 tx_lp_en control selection.
+ * 1: from register. 0: from chan0 state machine.
+ * [8] register bit from chan3 tx_lp_en.
+ * [4] clk chan power down. this bit is also used as the power down
+ * of the whole MIPI_DSI_PHY.
+ * [3] chan3 power down.
+ * [2] chan2 power down.
+ * [1] chan1 power down.
+ * [0] chan0 power down.
+ */
+#define MIPI_DSI_CHAN_CTRL 0x4
+
+/* [24] rx turn watch dog triggered.
+ * [23] rx esc watchdog triggered.
+ * [22] mbias ready.
+ * [21] txclkesc synced and ready.
+ * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
+ * [16:13] chan3 state{0, tx_stop, tx_ulps, tx_hs_active}
+ * [12:9] chan2 state.{0, tx_stop, tx_ulps, tx_hs_active}
+ * [8:5] chan1 state. {0, tx_stop, tx_ulps, tx_hs_active}
+ * [4:0] chan0 state. {TX_STOP, tx_ULPS, hs_active, direction, rxulpsesc}
+ */
+#define MIPI_DSI_CHAN_STS 0x8
+
+/* [31:24] TCLK_PREPARE.
+ * [23:16] TCLK_ZERO.
+ * [15:8] TCLK_POST.
+ * [7:0] TCLK_TRAIL.
+ */
+#define MIPI_DSI_CLK_TIM 0xc
+
+/* [31:24] THS_PREPARE.
+ * [23:16] THS_ZERO.
+ * [15:8] THS_TRAIL.
+ * [7:0] THS_EXIT.
+ */
+#define MIPI_DSI_HS_TIM 0x10
+
+/* [31:24] tTA_GET.
+ * [23:16] tTA_GO.
+ * [15:8] tTA_SURE.
+ * [7:0] tLPX.
+ */
+#define MIPI_DSI_LP_TIM 0x14
+
+/* wait time to MIPI DIS analog ready. */
+#define MIPI_DSI_ANA_UP_TIM 0x18
+
+/* TINIT. */
+#define MIPI_DSI_INIT_TIM 0x1c
+
+/* TWAKEUP. */
+#define MIPI_DSI_WAKEUP_TIM 0x20
+
+/* when in RxULPS check state, after the the logic enable the analog,
+ * how long we should wait to check the lP state .
+ */
+#define MIPI_DSI_LPOK_TIM 0x24
+
+/* Watchdog for RX low power state no finished. */
+#define MIPI_DSI_LP_WCHDOG 0x28
+
+/* tMBIAS, after send power up signals to analog,
+ * how long we should wait for analog powered up.
+ */
+#define MIPI_DSI_ANA_CTRL 0x2c
+
+/* [31:8] reserved for future.
+ * [7:0] tCLK_PRE.
+ */
+#define MIPI_DSI_CLK_TIM1 0x30
+
+/* watchdog for turn around waiting time. */
+#define MIPI_DSI_TURN_WCHDOG 0x34
+
+/* When in RxULPS state, how frequency we should to check
+ * if the TX side out of ULPS state.
+ */
+#define MIPI_DSI_ULPS_CHECK 0x38
+#define MIPI_DSI_TEST_CTRL0 0x3c
+#define MIPI_DSI_TEST_CTRL1 0x40
+
+#define NSEC_PER_MSEC 1000000L
+
+struct phy_meson_axg_mipi_dphy_priv {
+ struct regmap *regmap;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+ struct reset_ctl reset;
+ struct phy analog;
+ struct phy_configure_opts_mipi_dphy config;
+};
+
+static int phy_meson_axg_mipi_dphy_configure(struct phy *phy, void *params)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
+ struct phy_configure_opts_mipi_dphy *config = params;
+ int ret;
+
+ ret = phy_mipi_dphy_config_validate(config);
+ if (ret)
+ return ret;
+
+ ret = generic_phy_configure(&priv->analog, config);
+ if (ret)
+ return ret;
+
+ memcpy(&priv->config, config, sizeof(priv->config));
+
+ return 0;
+}
+
+static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
+ unsigned long temp;
+ int ret;
+
+ ret = generic_phy_power_on(&priv->analog);
+ if (ret)
+ return ret;
+
+ /* enable phy clock */
+ regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1);
+ regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,
+ BIT(0) | /* enable the DSI PLL clock . */
+ BIT(7) | /* enable pll clock which connected to DDR clock path */
+ BIT(8)); /* enable the clock divider counter */
+
+ /* enable the divider clock out */
+ regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9));
+
+ /* enable the byte clock generation. */
+ regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12));
+ regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31));
+ regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0);
+
+ /* Calculate lanebyteclk period in ps */
+ temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000);
+ temp = temp * 8 * 10;
+
+ regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,
+ DIV_ROUND_UP(priv->config.clk_trail, temp) |
+ (DIV_ROUND_UP(priv->config.clk_post +
+ priv->config.hs_trail, temp) << 8) |
+ (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
+ (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
+ regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
+ DIV_ROUND_UP(priv->config.clk_pre, temp));
+
+ regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
+ DIV_ROUND_UP(priv->config.hs_exit, temp) |
+ (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) |
+ (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) |
+ (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24));
+
+ regmap_write(priv->regmap, MIPI_DSI_LP_TIM,
+ DIV_ROUND_UP(priv->config.lpx, temp) |
+ (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) |
+ (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) |
+ (DIV_ROUND_UP(priv->config.ta_get, temp) << 24));
+
+ regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);
+ regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,
+ DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp));
+ regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,
+ DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp));
+ regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C);
+ regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C);
+ regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000);
+ regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000);
+
+ /* Powerup the analog circuit */
+ switch (priv->config.lanes) {
+ case 1:
+ regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe);
+ break;
+ case 2:
+ regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc);
+ break;
+ case 3:
+ regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8);
+ break;
+ case 4:
+ default:
+ regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0);
+ break;
+ }
+
+ /* Trigger a sync active for esc_clk */
+ regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1));
+
+ return 0;
+}
+
+static int phy_meson_axg_mipi_dphy_power_off(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
+
+ regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf);
+ regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31));
+
+ return generic_phy_power_off(&priv->analog);
+}
+
+static int phy_meson_axg_mipi_dphy_init(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = generic_phy_init(&priv->analog);
+ if (ret)
+ return ret;
+
+ ret = reset_assert(&priv->reset);
+ udelay(1);
+ ret |= reset_deassert(&priv->reset);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int phy_meson_axg_mipi_dphy_exit(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = generic_phy_exit(&priv->analog);
+ if (ret)
+ return ret;
+
+ return reset_assert(&priv->reset);
+}
+
+struct phy_ops meson_axg_mipi_dphy_ops = {
+ .init = phy_meson_axg_mipi_dphy_init,
+ .exit = phy_meson_axg_mipi_dphy_exit,
+ .power_on = phy_meson_axg_mipi_dphy_power_on,
+ .power_off = phy_meson_axg_mipi_dphy_power_off,
+ .configure = phy_meson_axg_mipi_dphy_configure,
+};
+
+int meson_axg_mipi_dphy_probe(struct udevice *dev)
+{
+ struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
+ if (ret)
+ return ret;
+
+ ret = generic_phy_get_by_index(dev, 0, &priv->analog);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_index(dev, 0, &priv->reset);
+ if (ret == -ENOTSUPP)
+ return 0;
+ else if (ret)
+ return ret;
+
+ ret = reset_deassert(&priv->reset);
+ if (ret) {
+ reset_release_all(&priv->reset, 1);
+ return ret;
+ }
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id meson_axg_mipi_dphy_ids[] = {
+ { .compatible = "amlogic,axg-mipi-dphy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_axg_mipi_dphy) = {
+ .name = "meson_axg_mipi_dphy",
+ .id = UCLASS_PHY,
+ .of_match = meson_axg_mipi_dphy_ids,
+ .probe = meson_axg_mipi_dphy_probe,
+ .ops = &meson_axg_mipi_dphy_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_meson_axg_mipi_dphy_priv),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic AXG MIPI + PCIE analog PHY driver
+ *
+ * Copyright (C) 2019 Remi Pommarel <repk@triplefau.lt>
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <reset.h>
+#include <clk.h>
+#include <phy-mipi-dphy.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
+#define HHI_MIPI_CNTL0 0x00
+#define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
+#define HHI_MIPI_CNTL0_ENABLE BIT(29)
+#define HHI_MIPI_CNTL0_BANDGAP BIT(26)
+#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(25, 16)
+#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
+
+#define HHI_MIPI_CNTL1 0x04
+#define HHI_MIPI_CNTL1_CH0_CML_PDR_EN BIT(12)
+#define HHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4)
+#define HHI_MIPI_CNTL1_LP_RESISTER BIT(3)
+#define HHI_MIPI_CNTL1_INPUT_SETTING BIT(2)
+#define HHI_MIPI_CNTL1_INPUT_SEL BIT(1)
+#define HHI_MIPI_CNTL1_PRBS7_EN BIT(0)
+
+#define HHI_MIPI_CNTL2 0x08
+#define HHI_MIPI_CNTL2_CH_PU GENMASK(31, 25)
+#define HHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19)
+#define HHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18)
+#define HHI_MIPI_CNTL2_CH_DIGDR_EN BIT(17)
+#define HHI_MIPI_CNTL2_LPULPS_EN BIT(16)
+#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
+#define HHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1)
+
+#define DSI_LANE_0 (1 << 4)
+#define DSI_LANE_1 (1 << 3)
+#define DSI_LANE_CLK (1 << 2)
+#define DSI_LANE_2 (1 << 1)
+#define DSI_LANE_3 (1 << 0)
+#define DSI_LANE_MASK (0x1F)
+
+struct phy_meson_axg_mipi_pcie_analog_priv {
+ struct regmap *regmap;
+ struct phy_configure_opts_mipi_dphy config;
+ bool dsi_configured;
+ bool dsi_enabled;
+ bool powered;
+};
+
+static void phy_bandgap_enable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
+{
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_BANDGAP, HHI_MIPI_CNTL0_BANDGAP);
+
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_ENABLE, HHI_MIPI_CNTL0_ENABLE);
+}
+
+static void phy_bandgap_disable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
+{
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_BANDGAP, 0);
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_ENABLE, 0);
+}
+
+static void phy_dsi_analog_enable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
+{
+ u32 reg;
+
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_DIF_REF_CTL1,
+ FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0x1b8));
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ BIT(31), BIT(31));
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_DIF_REF_CTL0,
+ FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8));
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x001e);
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL2,
+ (0x26e0 << 16) | (0x459 << 0));
+
+ reg = DSI_LANE_CLK;
+ switch (priv->config.lanes) {
+ case 4:
+ reg |= DSI_LANE_3;
+ fallthrough;
+ case 3:
+ reg |= DSI_LANE_2;
+ fallthrough;
+ case 2:
+ reg |= DSI_LANE_1;
+ fallthrough;
+ case 1:
+ reg |= DSI_LANE_0;
+ break;
+ default:
+ reg = 0;
+ }
+
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
+ HHI_MIPI_CNTL2_CH_EN,
+ FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
+
+ priv->dsi_enabled = true;
+}
+
+static void phy_dsi_analog_disable(struct phy_meson_axg_mipi_pcie_analog_priv *priv)
+{
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_DIF_REF_CTL1,
+ FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0));
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0, BIT(31), 0);
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_DIF_REF_CTL1, 0);
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x6);
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0x00200000);
+
+ priv->dsi_enabled = false;
+}
+
+static int phy_meson_axg_mipi_pcie_analog_configure(struct phy *phy, void *params)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
+ struct phy_configure_opts_mipi_dphy *config = params;
+ int ret;
+
+ ret = phy_mipi_dphy_config_validate(config);
+ if (ret)
+ return ret;
+
+ memcpy(&priv->config, config, sizeof(priv->config));
+
+ priv->dsi_configured = true;
+
+ /* If PHY was already powered on, setup the DSI analog part */
+ if (priv->powered) {
+ /* If reconfiguring, disable & reconfigure */
+ if (priv->dsi_enabled)
+ phy_dsi_analog_disable(priv);
+
+ udelay(100);
+
+ phy_dsi_analog_enable(priv);
+ }
+
+ return 0;
+}
+
+static int phy_meson_axg_mipi_pcie_analog_power_on(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
+
+ phy_bandgap_enable(priv);
+
+ if (priv->dsi_configured)
+ phy_dsi_analog_enable(priv);
+
+ priv->powered = true;
+
+ return 0;
+}
+
+static int phy_meson_axg_mipi_pcie_analog_power_off(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
+
+ phy_bandgap_disable(priv);
+
+ if (priv->dsi_enabled)
+ phy_dsi_analog_disable(priv);
+
+ priv->powered = false;
+
+ return 0;
+}
+
+struct phy_ops meson_axg_mipi_pcie_analog_ops = {
+ .power_on = phy_meson_axg_mipi_pcie_analog_power_on,
+ .power_off = phy_meson_axg_mipi_pcie_analog_power_off,
+ .configure = phy_meson_axg_mipi_pcie_analog_configure,
+};
+
+int meson_axg_mipi_pcie_analog_probe(struct udevice *dev)
+{
+ struct phy_meson_axg_mipi_pcie_analog_priv *priv = dev_get_priv(dev);
+
+ priv->regmap = syscon_node_to_regmap(dev_get_parent(dev)->node);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ return 0;
+}
+
+static const struct udevice_id meson_axg_mipi_pcie_analog_ids[] = {
+ { .compatible = "amlogic,axg-mipi-pcie-analog-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_axg_mipi_pcie_analog) = {
+ .name = "meson_axg_mipi_pcie_analog",
+ .id = UCLASS_PHY,
+ .of_match = meson_axg_mipi_pcie_analog_ids,
+ .probe = meson_axg_mipi_pcie_analog_probe,
+ .ops = &meson_axg_mipi_pcie_analog_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_meson_axg_mipi_pcie_analog_priv),
+};
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (C) 2018 Cadence Design Systems Inc.
+ */
+
+#include <common.h>
+#include <div64.h>
+
+#include <phy-mipi-dphy.h>
+
+#define PSEC_PER_SEC 1000000000000LL
+
+/*
+ * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
+ * from the valid ranges specified in Section 6.9, Table 14, Page 41
+ * of the D-PHY specification (v2.1).
+ */
+int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
+ unsigned int bpp,
+ unsigned int lanes,
+ struct phy_configure_opts_mipi_dphy *cfg)
+{
+ unsigned long long hs_clk_rate;
+ unsigned long long ui;
+
+ if (!cfg)
+ return -EINVAL;
+
+ hs_clk_rate = pixel_clock * bpp;
+ do_div(hs_clk_rate, lanes);
+
+ ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
+ do_div(ui, hs_clk_rate);
+
+ cfg->clk_miss = 0;
+ cfg->clk_post = 60000 + 52 * ui;
+ cfg->clk_pre = 8000;
+ cfg->clk_prepare = 38000;
+ cfg->clk_settle = 95000;
+ cfg->clk_term_en = 0;
+ cfg->clk_trail = 60000;
+ cfg->clk_zero = 262000;
+ cfg->d_term_en = 0;
+ cfg->eot = 0;
+ cfg->hs_exit = 100000;
+ cfg->hs_prepare = 40000 + 4 * ui;
+ cfg->hs_zero = 105000 + 6 * ui;
+ cfg->hs_settle = 85000 + 6 * ui;
+ cfg->hs_skip = 40000;
+
+ /*
+ * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
+ * contains this formula as:
+ *
+ * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
+ *
+ * where n = 1 for forward-direction HS mode and n = 4 for reverse-
+ * direction HS mode. There's only one setting and this function does
+ * not parameterize on anything other that ui, so this code will
+ * assumes that reverse-direction HS mode is supported and uses n = 4.
+ */
+ cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
+
+ cfg->init = 100;
+ cfg->lpx = 60000;
+ cfg->ta_get = 5 * cfg->lpx;
+ cfg->ta_go = 4 * cfg->lpx;
+ cfg->ta_sure = 2 * cfg->lpx;
+ cfg->wakeup = 1000;
+
+ cfg->hs_clk_rate = hs_clk_rate;
+ cfg->lanes = lanes;
+
+ return 0;
+}
+
+/*
+ * Validate D-PHY configuration according to MIPI D-PHY specification
+ * (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
+ */
+int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
+{
+ unsigned long long ui;
+
+ if (!cfg)
+ return -EINVAL;
+
+ ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
+ do_div(ui, cfg->hs_clk_rate);
+
+ if (cfg->clk_miss > 60000)
+ return -EINVAL;
+
+ if (cfg->clk_post < (60000 + 52 * ui))
+ return -EINVAL;
+
+ if (cfg->clk_pre < 8000)
+ return -EINVAL;
+
+ if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
+ return -EINVAL;
+
+ if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
+ return -EINVAL;
+
+ if (cfg->clk_term_en > 38000)
+ return -EINVAL;
+
+ if (cfg->clk_trail < 60000)
+ return -EINVAL;
+
+ if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
+ return -EINVAL;
+
+ if (cfg->d_term_en > (35000 + 4 * ui))
+ return -EINVAL;
+
+ if (cfg->eot > (105000 + 12 * ui))
+ return -EINVAL;
+
+ if (cfg->hs_exit < 100000)
+ return -EINVAL;
+
+ if (cfg->hs_prepare < (40000 + 4 * ui) ||
+ cfg->hs_prepare > (85000 + 6 * ui))
+ return -EINVAL;
+
+ if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
+ return -EINVAL;
+
+ if ((cfg->hs_settle < (85000 + 6 * ui)) ||
+ (cfg->hs_settle > (145000 + 10 * ui)))
+ return -EINVAL;
+
+ if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
+ return -EINVAL;
+
+ if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
+ return -EINVAL;
+
+ if (cfg->init < 100)
+ return -EINVAL;
+
+ if (cfg->lpx < 50000)
+ return -EINVAL;
+
+ if (cfg->ta_get != (5 * cfg->lpx))
+ return -EINVAL;
+
+ if (cfg->ta_go != (4 * cfg->lpx))
+ return -EINVAL;
+
+ if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
+ return -EINVAL;
+
+ if (cfg->wakeup < 1000)
+ return -EINVAL;
+
+ return 0;
+}
return ret;
}
+int generic_phy_configure(struct phy *phy, void *params)
+{
+ struct phy_ops const *ops;
+
+ if (!generic_phy_valid(phy))
+ return 0;
+ ops = phy_dev_ops(phy->dev);
+
+ return ops->configure ? ops->configure(phy, params) : 0;
+}
+
int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk)
{
int i, ret, count;
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <generic-phy.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <generic-phy.h>
#include <reset.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <generic-phy.h>
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <bitfield.h>
#include <dm.h>
#include <dm.h>
#include <dm/device.h>
#include <generic-phy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <syscon.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/pinctrl.h>
#include <mach/ar71xx_regs.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/pinctrl.h>
#include <mach/ar71xx_regs.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include "pinctrl-exynos.h"
#include <dm.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <config.h>
#include <dm.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <errno.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <asm/system.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include "pinctrl-nexell.h"
#include "pinctrl-s5pxx18.h"
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <common.h>
#include <malloc.h>
#include <mapmem.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/bitops.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/io.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/pinctrl.h>
#include <asm/hardware.h>
#include <linux/bitops.h>
#include <errno.h>
#include <regmap.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/pinctrl.h>
#include <linux/bug.h>
}
/*
- * STMFX pins[15:0] are called "stmfx_gpio[15:0]"
- * and STMFX pins[23:16] are called "stmfx_agpio[7:0]"
+ * STMFX pins[15:0] are called "gpio[15:0]"
+ * and STMFX pins[23:16] are called "agpio[7:0]"
*/
-#define MAX_PIN_NAME_LEN 7
-static char pin_name[MAX_PIN_NAME_LEN];
+static char pin_name[PINNAME_SIZE];
static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < STMFX_MAX_GPIO)
- snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_gpio%u", selector);
+ snprintf(pin_name, PINNAME_SIZE, "gpio%u", selector);
else
- snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_agpio%u", selector - 16);
+ snprintf(pin_name, PINNAME_SIZE, "agpio%u", selector - 16);
return pin_name;
}
#include <common.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
[STM32_GPIO_PUPD_DOWN] = "pull-down",
};
-static const char * const pinmux_input[] = {
+static const char * const pinmux_otype[] = {
[STM32_GPIO_OTYPE_PP] = "push-pull",
[STM32_GPIO_OTYPE_OD] = "open-drain",
};
selector, gpio_idx, mode);
priv = dev_get_priv(gpio_dev);
pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
-
+ otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
switch (mode) {
case GPIOF_UNKNOWN:
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
- snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
- pinmux_bias[pupd]);
+ snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
+ pinmux_otype[otype], pinmux_bias[pupd]);
break;
case GPIOF_OUTPUT:
- snprintf(buf, size, "%s %s %s",
- pinmux_mode[mode], pinmux_bias[pupd],
- label ? label : "");
+ snprintf(buf, size, "%s %s %s %s",
+ pinmux_mode[mode], pinmux_otype[otype],
+ pinmux_bias[pupd], label ? label : "");
break;
case GPIOF_INPUT:
- otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
- snprintf(buf, size, "%s %s %s %s",
- pinmux_mode[mode], pinmux_input[otype],
+ snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
pinmux_bias[pupd], label ? label : "");
break;
}
dev_for_each_subnode(node, dev) {
dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
+ if (!ofnode_is_enabled(node))
+ continue;
+
ofnode_get_property(node, "gpio-controller", &ret);
if (ret < 0)
continue;
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include <fdtdec.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
+#include <asm/global_data.h>
#include "pinctrl-rockchip.h"
#include <log.h>
#include <malloc.h>
#include <power-domain-uclass.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/power-domain.h>
#include <dm/device-internal.h>
#include <dm.h>
#include <malloc.h>
#include <power-domain-uclass.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/power-domain.h>
#include <asm/mach-imx/sys_proto.h>
return err;
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{
struct udevice *dev;
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <asm/global_data.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/bd71837.h>
#include <errno.h>
#include <fsl_pmic.h>
#include <i2c.h>
+#include <asm/global_data.h>
#include <power/pmic.h>
DECLARE_GLOBAL_DATA_PTR;
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/mp5416.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <i2c.h>
#include <log.h>
+#include <asm/global_data.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/pca9450.h>
#include <power/pmic.h>
#include <power/tps62362.h>
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *tps62362_dev __attribute__((section(".data"))) = NULL;
#endif
if (reg > TPS62362_NUM_REGS)
return 1;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1);
#else
if (!tps62362_dev)
#endif
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
int power_tps62362_init(unsigned char bus)
{
static const char name[] = "TPS62362";
*/
int tps65217_reg_read(uchar src_reg, uchar *src_val)
{
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
#else
return dm_i2c_read(tps65217_dev, src_reg, src_val, 1);
* mask
*/
if (mask != TPS65217_MASK_ALL_BITS) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1);
#else
ret = dm_i2c_read(tps65217_dev, dest_reg, &read_val, 1);
if (prot_level > 0) {
xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
&xor_reg, 1);
#else
if (ret)
return ret;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
#else
ret = dm_i2c_write(tps65217_dev, dest_reg, &dest_val, 1);
return ret;
if (prot_level == TPS65217_PROT_LEVEL_2) {
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
&xor_reg, 1);
#else
if (ret)
return ret;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
#else
ret = dm_i2c_write(tps65217_dev, dest_reg, &dest_val, 1);
int power_tps65217_init(unsigned char bus)
{
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev = NULL;
int rc;
#include <power/pmic.h>
#include <power/tps65218.h>
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
int tps65218_reg_read(uchar dest_reg, uchar *dest_val)
{
uchar read_val;
return 0;
}
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
int power_tps65218_init(unsigned char bus)
{
static const char name[] = "TPS65218_PMIC";
static inline int tps65910_read_reg(int addr, uchar *buf)
{
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
return i2c_read(TPS65910_CTRL_I2C_ADDR, addr, 1, buf, 1);
#else
int rc;
static inline int tps65910_write_reg(int addr, uchar *buf)
{
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
return i2c_write(TPS65910_CTRL_I2C_ADDR, addr, 1, buf, 1);
#else
return dm_i2c_reg_write(tps65910_dev, addr, *buf);
int power_tps65910_init(unsigned char bus)
{
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev = NULL;
int rc;
#include <errno.h>
#include <log.h>
#include <pwm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <power/regulator.h>
}
#endif
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{
struct udevice *dev;
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_MISC2, value);
}
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{
struct udevice *dev;
#include <dm.h>
#include <pwm.h>
#include <regmap.h>
+#include <asm/global_data.h>
#include <linux/io.h>
#include <linux/log2.h>
#include <linux/bitfield.h>
#include <pwm.h>
#include <regmap.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/pwm.h>
#include <linux/bitops.h>
#include <pwm.h>
#include <regmap.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <asm/arch/gpio.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_qe.h>
#include <common.h>
#include <malloc.h>
#include <command.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/immap_qe.h>
#include <ram.h>
#include <regmap.h>
#include <reset.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/scu_ast2500.h>
#include <asm/arch/sdram_ast2500.h>
#include <asm/io.h>
#include <asm/arch/scu_ast2600.h>
#include <asm/arch/sdram_ast2600.h>
+#include <asm/global_data.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/ast2600-clock.h>
#include <log.h>
#include <ram.h>
#include <asm/bitops.h>
+#include <asm/global_data.h>
#include <dt-bindings/memory/mpc83xx-sdram.h>
DECLARE_GLOBAL_DATA_PTR;
#include <i2c.h>
#include <ram.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <linux/io.h>
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <dm.h>
#include <errno.h>
#include <ram.h>
+#include <asm/global_data.h>
#include <asm/test.h>
DECLARE_GLOBAL_DATA_PTR;
#include <init.h>
#include <ram.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <wait_bit.h>
#include <malloc.h>
#include <ram.h>
#include <reset.h>
+#include <asm/global_data.h>
#include "stm32mp1_ddr.h"
#include "stm32mp1_tests.h"
#include <log.h>
#include <rand.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/log2.h>
#include "stm32mp1_tests.h"
#include <log.h>
#include <malloc.h>
#include <remoteproc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm.h>
dev_dbg(core->dev, "%s\n", __func__);
- core->atcm_enable = dev_read_u32_default(core->dev, "atcm-enable", 0);
- core->btcm_enable = dev_read_u32_default(core->dev, "btcm-enable", 1);
- core->loczrama = dev_read_u32_default(core->dev, "loczrama", 1);
+ core->atcm_enable = dev_read_u32_default(core->dev, "ti,atcm-enable", 0);
+ core->btcm_enable = dev_read_u32_default(core->dev, "ti,btcm-enable", 1);
+ core->loczrama = dev_read_u32_default(core->dev, "ti,loczrama", 1);
ret = ti_sci_proc_of_to_priv(core->dev, &core->tsp);
if (ret)
dev_dbg(dev, "%s\n", __func__);
- cluster->mode = dev_read_u32_default(dev, "lockstep-mode",
+ cluster->mode = dev_read_u32_default(dev, "ti,cluster-mode",
CLUSTER_MODE_LOCKSTEP);
if (device_get_child_count(dev) != 2) {
#include <fdtdec.h>
#include <log.h>
#include <remoteproc.h>
+#include <asm/global_data.h>
#include <mach/psc_defs.h>
DECLARE_GLOBAL_DATA_PTR;
#include <reset-uclass.h>
#include <regmap.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <dt-bindings/reset/stih407-resets.h>
#include <linux/bitops.h>
Enable random number generator for rockchip.This driver is
support rng module of crypto v1 and crypto v2.
+config RNG_IPROC200
+ bool "Broadcom iProc RNG200 random number generator"
+ depends on DM_RNG
+ default n
+ help
+ Enable random number generator for RPI4.
endif
obj-$(CONFIG_RNG_MSM) += msm_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
+obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2020, Matthias Brugger <mbrugger@suse.com>
+ *
+ * Driver for Raspberry Pi hardware random number generator
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <rng.h>
+#include <asm/io.h>
+
+#define usleep_range(a, b) udelay((b))
+
+#define RNG_CTRL_OFFSET 0x00
+#define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
+#define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
+#define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000
+
+#define RNG_SOFT_RESET_OFFSET 0x04
+#define RNG_SOFT_RESET 0x00000001
+
+#define RBG_SOFT_RESET_OFFSET 0x08
+#define RBG_SOFT_RESET 0x00000001
+
+#define RNG_INT_STATUS_OFFSET 0x18
+#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
+#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
+
+#define RNG_FIFO_DATA_OFFSET 0x20
+
+#define RNG_FIFO_COUNT_OFFSET 0x24
+#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
+
+struct iproc_rng200_platdata {
+ fdt_addr_t base;
+};
+
+static void iproc_rng200_enable(struct iproc_rng200_platdata *pdata, bool enable)
+{
+ fdt_addr_t rng_base = pdata->base;
+ u32 val;
+
+ val = readl(rng_base + RNG_CTRL_OFFSET);
+ val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+ if (enable)
+ val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+ else
+ val &= ~RNG_CTRL_RNG_RBGEN_ENABLE;
+
+ writel(val, rng_base + RNG_CTRL_OFFSET);
+}
+
+static void iproc_rng200_restart(struct iproc_rng200_platdata *pdata)
+{
+ fdt_addr_t rng_base = pdata->base;
+ u32 val;
+
+ iproc_rng200_enable(pdata, false);
+
+ /* Clear all interrupt status */
+ writel(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
+
+ /* Reset RNG and RBG */
+ val = readl(rng_base + RBG_SOFT_RESET_OFFSET);
+ val |= RBG_SOFT_RESET;
+ writel(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+ val = readl(rng_base + RNG_SOFT_RESET_OFFSET);
+ val |= RNG_SOFT_RESET;
+ writel(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+ val = readl(rng_base + RNG_SOFT_RESET_OFFSET);
+ val &= ~RNG_SOFT_RESET;
+ writel(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+ val = readl(rng_base + RBG_SOFT_RESET_OFFSET);
+ val &= ~RBG_SOFT_RESET;
+ writel(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+ iproc_rng200_enable(pdata, true);
+}
+
+static int iproc_rng200_read(struct udevice *dev, void *data, size_t len)
+{
+ struct iproc_rng200_platdata *priv = dev_get_plat(dev);
+ char *buf = (char *)data;
+ u32 num_remaining = len;
+ u32 status;
+
+ #define MAX_RESETS_PER_READ 1
+ u32 num_resets = 0;
+
+ while (num_remaining > 0) {
+
+ /* Is RNG sane? If not, reset it. */
+ status = readl(priv->base + RNG_INT_STATUS_OFFSET);
+ if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
+ RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
+
+ if (num_resets >= MAX_RESETS_PER_READ)
+ return len - num_remaining;
+
+ iproc_rng200_restart(priv);
+ num_resets++;
+ }
+
+ /* Are there any random numbers available? */
+ if ((readl(priv->base + RNG_FIFO_COUNT_OFFSET) &
+ RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
+
+ if (num_remaining >= sizeof(u32)) {
+ /* Buffer has room to store entire word */
+ *(u32 *)buf = readl(priv->base +
+ RNG_FIFO_DATA_OFFSET);
+ buf += sizeof(u32);
+ num_remaining -= sizeof(u32);
+ } else {
+ /* Buffer can only store partial word */
+ u32 rnd_number = readl(priv->base +
+ RNG_FIFO_DATA_OFFSET);
+ memcpy(buf, &rnd_number, num_remaining);
+ buf += num_remaining;
+ num_remaining = 0;
+ }
+
+ } else {
+ /* Can wait, give others chance to run */
+ usleep_range(min(num_remaining * 10, 500U), 500);
+ }
+ }
+
+ return 0;
+}
+
+static int iproc_rng200_probe(struct udevice *dev)
+{
+ struct iproc_rng200_platdata *priv = dev_get_plat(dev);
+
+ iproc_rng200_enable(priv, true);
+
+ return 0;
+}
+
+static int iproc_rng200_remove(struct udevice *dev)
+{
+ struct iproc_rng200_platdata *priv = dev_get_plat(dev);
+
+ iproc_rng200_enable(priv, false);
+
+ return 0;
+}
+
+static int iproc_rng200_ofdata_to_platdata(struct udevice *dev)
+{
+ struct iproc_rng200_platdata *pdata = dev_get_plat(dev);
+
+ pdata->base = dev_read_addr(dev);
+ if (!pdata->base)
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_rng_ops iproc_rng200_ops = {
+ .read = iproc_rng200_read,
+};
+
+static const struct udevice_id iproc_rng200_rng_match[] = {
+ { .compatible = "brcm,bcm2711-rng200", },
+ { .compatible = "brcm,iproc-rng200", },
+ {},
+};
+
+U_BOOT_DRIVER(iproc_rng200_rng) = {
+ .name = "iproc_rng200-rng",
+ .id = UCLASS_RNG,
+ .of_match = iproc_rng200_rng_match,
+ .ops = &iproc_rng200_ops,
+ .probe = iproc_rng200_probe,
+ .remove = iproc_rng200_remove,
+ .plat_auto = sizeof(struct iproc_rng200_platdata),
+ .of_to_plat = iproc_rng200_ofdata_to_platdata,
+};
config MXC_UART
bool "IMX serial port support"
- depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 || TARGET_MX35PDK \
+ depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \
|| MX5 || MX6 || MX7 || IMX8M
help
If you have a machine based on a Motorola IMX CPU you
#include <watchdog.h>
#include <serial.h>
#include <debug_uart.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <reset.h>
#include <serial.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <linux/err.h>
#include <linux/types.h>
#include <asm/io.h>
#include <os.h>
#include <serial.h>
#include <video.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/serial.h>
#include <asm/state.h>
#include <serial.h>
#include <stdio_dev.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
#include <dm/of_access.h>
#include <serial.h>
#include <stdio_dev.h>
#include <post.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <errno.h>
#include <linux/delay.h>
#include <common.h>
#include <dm.h>
#include <serial.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <serial.h>
#include <linux/compiler.h>
#include <fsl_lpuart.h>
#include <log.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <serial.h>
#include <dm/device_compat.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_coldfire.h>
#include <serial.h>
#include <linux/compiler.h>
#include <serial.h>
#include <watchdog.h>
#include <asm/cpm_8xx.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#include <malloc.h>
#include <serial.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <dm/pinctrl.h>
#include <log.h>
#include <serial.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/types.h>
#include <linux/err.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/global_data.h>
#include <dm/platform_data/serial_mxc.h>
#include <serial.h>
#include <linux/compiler.h>
#include <clock_legacy.h>
#include <ns16550.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
#include <malloc.h>
#include <serial.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <mach/pic32.h>
#include <dt-bindings/clock/microchip,clock.h>
/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
#include <common.h>
+#include <asm/global_data.h>
/* For get_bus_freq() */
#include <clock_legacy.h>
#include <dm.h>
#include <hang.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-uart.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/platform_data/serial_pxa.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <errno.h>
#include <clk.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <serial.h>
#include <fdtdec.h>
#include <log.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <serial.h>
{
struct sifive_uart_plat *plat = dev_get_plat(dev);
- plat->regs = (struct uart_sifive *)dev_read_addr(dev);
+ plat->regs = (struct uart_sifive *)(uintptr_t)dev_read_addr(dev);
if (IS_ERR(plat->regs))
return PTR_ERR(plat->regs);
#include <dm.h>
#include <log.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <dm.h>
#include <serial.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <linux/bug.h>
#include <common.h>
#include <errno.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <dm/of_access.h>
int ret;
if (!__smem)
- return -EPROBE_DEFER;
+ return -ENOMEM;
if (item < SMEM_ITEM_LAST_FIXED) {
dev_err(__smem->dev,
{
struct smem_partition_header *phdr;
size_t cacheln;
- void *ptr = ERR_PTR(-EPROBE_DEFER);
+ void *ptr = ERR_PTR(-ENOMEM);
if (!__smem)
return ptr;
unsigned int ret;
if (!__smem)
- return -EPROBE_DEFER;
+ return -ENOMEM;
if (host < SMEM_HOST_COUNT && __smem->partitions[host]) {
phdr = __smem->partitions[host];
#include <pch.h>
#include <sound.h>
#include <linux/bitops.h>
+#include <asm/global_data.h>
static int bd82x6x_azalia_probe(struct udevice *dev)
{
#include <log.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
*/
+#include <asm/global_data.h>
#include <asm/io.h>
#include <command.h>
#include <config.h>
#include <spi.h>
#include <spi-mem.h>
#include <reset.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
#include <log.h>
#include <spi.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <dm.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/spi.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
* Haikun Wang (B53464@freescale.com)
*/
+#include <asm/global_data.h>
#include <linux/math64.h>
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/immap_85xx.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <spi.h>
#include <spi-mem.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
.little_endian = false,
};
-static const struct fsl_qspi_devtype_data ls1088a_data = {
- .rxfifo = SZ_128,
- .txfifo = SZ_128,
- .ahb_buf_size = SZ_1K,
- .quirks = QUADSPI_QUIRK_TKT253890,
- .little_endian = true,
-};
-
static const struct fsl_qspi_devtype_data ls2080a_data = {
.rxfifo = SZ_128,
.txfifo = SZ_64,
op->data.nbytes > q->devtype_data->txfifo)
return false;
- return true;
+ return spi_mem_default_supports_op(slave, op);
}
static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
{ .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
{ .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, },
{ .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
- { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
+ { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, },
{ .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
{ }
};
#include <spi.h>
#include <clk.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <dm.h>
#include <spi.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <omap3_spi.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compat.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/spi_pl022.h>
#include <linux/io.h>
+#include <asm/global_data.h>
#include <spi.h>
#define SSP_CR0 0x000
*/
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <fdt_support.h>
#include <reset.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <malloc.h>
#include <spi.h>
#include <dm/device_compat.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <dm/lists.h>
#include <errno.h>
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <dm.h>
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#include <dm.h>
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/omap.h>
#include <malloc.h>
#include <dm.h>
#include <log.h>
#include <time.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <spi.h>
#include <time.h>
#include <clk.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <log.h>
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <spmi/spmi.h>
#include <dm/root.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <asm/global_data.h>
int sysreset_request(struct udevice *dev, enum sysreset_t type)
{
#include <sysreset.h>
#include <wait_bit.h>
#include <linux/delay.h>
+#include <asm/global_data.h>
#include "sysreset_mpc83xx.h"
#include <regmap.h>
#include <syscon.h>
#include <sysreset.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
obj-y += tee-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox.o
+obj-$(CONFIG_OPTEE_TA_RPC_TEST) += optee/supplicant.o
+obj-$(CONFIG_OPTEE_TA_RPC_TEST) += optee/i2c.o
obj-$(CONFIG_OPTEE) += optee/
obj-y += broadcom/
The TA can support the "avb" subcommands "read_rb", "write"rb"
and "is_unlocked".
+config OPTEE_TA_RPC_TEST
+ bool "Support RPC TEST TA"
+ depends on SANDBOX_TEE
+ default y
+ help
+ Enables support for RPC test trusted application emulation, which
+ permits to test reverse RPC calls to TEE supplicant. Should
+ be used only in sandbox env.
+
endmenu
endif
obj-y += core.o
obj-y += supplicant.o
+obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
--- /dev/null
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2020 Foundries.io Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <tee.h>
+#include "optee_msg.h"
+#include "optee_private.h"
+
+static int check_xfer_flags(struct udevice *chip, uint tee_flags)
+{
+ uint flags;
+ int ret;
+
+ ret = i2c_get_chip_flags(chip, &flags);
+ if (ret)
+ return ret;
+
+ if (tee_flags & OPTEE_MSG_RPC_CMD_I2C_FLAGS_TEN_BIT) {
+ if (!(flags & DM_I2C_CHIP_10BIT))
+ return -EINVAL;
+ } else {
+ if (flags & DM_I2C_CHIP_10BIT)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+void optee_suppl_cmd_i2c_transfer(struct optee_msg_arg *arg)
+{
+ const u8 attr[] = {
+ OPTEE_MSG_ATTR_TYPE_VALUE_INPUT,
+ OPTEE_MSG_ATTR_TYPE_VALUE_INPUT,
+ OPTEE_MSG_ATTR_TYPE_RMEM_INOUT,
+ OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT,
+ };
+ struct udevice *chip_dev;
+ struct tee_shm *shm;
+ u8 *buf;
+ int ret;
+
+ if (arg->num_params != ARRAY_SIZE(attr) ||
+ arg->params[0].attr != attr[0] ||
+ arg->params[1].attr != attr[1] ||
+ arg->params[2].attr != attr[2] ||
+ arg->params[3].attr != attr[3]) {
+ goto bad;
+ }
+
+ shm = (struct tee_shm *)(unsigned long)arg->params[2].u.rmem.shm_ref;
+ buf = shm->addr;
+ if (!buf)
+ goto bad;
+
+ if (i2c_get_chip_for_busnum((int)arg->params[0].u.value.b,
+ (int)arg->params[0].u.value.c,
+ 0, &chip_dev))
+ goto bad;
+
+ if (check_xfer_flags(chip_dev, arg->params[1].u.value.a))
+ goto bad;
+
+ switch (arg->params[0].u.value.a) {
+ case OPTEE_MSG_RPC_CMD_I2C_TRANSFER_RD:
+ ret = dm_i2c_read(chip_dev, 0, buf,
+ (size_t)arg->params[2].u.rmem.size);
+ break;
+ case OPTEE_MSG_RPC_CMD_I2C_TRANSFER_WR:
+ ret = dm_i2c_write(chip_dev, 0, buf,
+ (size_t)arg->params[2].u.rmem.size);
+ break;
+ default:
+ goto bad;
+ }
+
+ if (ret) {
+ arg->ret = TEE_ERROR_COMMUNICATION;
+ } else {
+ arg->params[3].u.value.a = arg->params[2].u.rmem.size;
+ arg->ret = TEE_SUCCESS;
+ }
+
+ return;
+bad:
+ arg->ret = TEE_ERROR_BAD_PARAMETERS;
+}
*/
#define OPTEE_MSG_RPC_CMD_SHM_FREE 7
+/*
+ * Access a device on an i2c bus
+ *
+ * [in] param[0].u.value.a mode: RD(0), WR(1)
+ * [in] param[0].u.value.b i2c adapter
+ * [in] param[0].u.value.c i2c chip
+ *
+ * [in] param[1].u.value.a i2c control flags
+ *
+ * [in/out] memref[2] buffer to exchange the transfer data
+ * with the secure world
+ *
+ * [out] param[3].u.value.a bytes transferred by the driver
+ */
+#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER 21
+/* I2C master transfer modes */
+#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER_RD 0
+#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER_WR 1
+/* I2C master control flags */
+#define OPTEE_MSG_RPC_CMD_I2C_FLAGS_TEN_BIT BIT(0)
+
#endif /* _OPTEE_MSG_H */
#define OPTEE_MSG_RPC_CMD_SHM_FREE 7
/*
+ * I2C bus access
+ */
+#define OPTEE_MSG_RPC_CMD_I2C_TRANSFER 21
+
+/*
* Was OPTEE_MSG_RPC_CMD_SQL_FS, which isn't supported any longer
*/
#define OPTEE_MSG_RPC_CMD_SQL_FS_RESERVED 8
}
#endif
+#ifdef CONFIG_DM_I2C
+/**
+ * optee_suppl_cmd_i2c_transfer() - route I2C requests to an I2C chip
+ * @arg: OP-TEE message (layout specified in optee_msg.h) defining the
+ * transfer mode (read/write), adapter, chip and control flags.
+ *
+ * Handles OP-TEE requests to transfer data to the I2C chip on the I2C adapter.
+ */
+void optee_suppl_cmd_i2c_transfer(struct optee_msg_arg *arg);
+#else
+static inline void optee_suppl_cmd_i2c_transfer(struct optee_msg_arg *arg)
+{
+ debug("OPTEE_MSG_RPC_CMD_I2C_TRANSFER not implemented\n");
+ arg->ret = TEE_ERROR_NOT_IMPLEMENTED;
+}
+#endif
+
void *optee_alloc_and_init_page_list(void *buf, ulong len, u64 *phys_buf_ptr);
#endif /* __OPTEE_PRIVATE_H */
case OPTEE_MSG_RPC_CMD_RPMB:
optee_suppl_cmd_rpmb(dev, arg);
break;
+ case OPTEE_MSG_RPC_CMD_I2C_TRANSFER:
+ optee_suppl_cmd_i2c_transfer(arg);
+ break;
default:
arg->ret = TEE_ERROR_NOT_IMPLEMENTED;
}
#include <sandboxtee.h>
#include <tee.h>
#include <tee/optee_ta_avb.h>
+#include <tee/optee_ta_rpc_test.h>
+
+#include "optee/optee_msg.h"
+#include "optee/optee_private.h"
/*
* The sandbox tee driver tries to emulate a generic Trusted Exectution
- * Environment (TEE) with the Trusted Application (TA) OPTEE_TA_AVB
- * available.
+ * Environment (TEE) with the Trusted Applications (TA) OPTEE_TA_AVB and
+ * OPTEE_TA_RPC_TEST available.
*/
static const u32 pstorage_max = 16;
struct tee_param *params);
};
-#ifdef CONFIG_OPTEE_TA_AVB
+static int get_msg_arg(struct udevice *dev, uint num_params,
+ struct tee_shm **shmp, struct optee_msg_arg **msg_arg)
+{
+ int rc;
+ struct optee_msg_arg *ma;
+
+ rc = __tee_shm_add(dev, OPTEE_MSG_NONCONTIG_PAGE_SIZE, NULL,
+ OPTEE_MSG_GET_ARG_SIZE(num_params), TEE_SHM_ALLOC,
+ shmp);
+ if (rc)
+ return rc;
+
+ ma = (*shmp)->addr;
+ memset(ma, 0, OPTEE_MSG_GET_ARG_SIZE(num_params));
+ ma->num_params = num_params;
+ *msg_arg = ma;
+
+ return 0;
+}
+
+void *optee_alloc_and_init_page_list(void *buf, ulong len,
+ u64 *phys_buf_ptr)
+{
+ /*
+ * An empty stub is added just to fix linking issues.
+ * This function isn't supposed to be called in sandbox
+ * setup, otherwise replace this with a proper
+ * implementation from optee/core.c
+ */
+ return NULL;
+}
+
static u32 get_attr(uint n, uint num_params, struct tee_param *params)
{
if (n >= num_params)
return TEE_ERROR_BAD_PARAMETERS;
}
+#ifdef CONFIG_OPTEE_TA_AVB
static u32 ta_avb_open_session(struct udevice *dev, uint num_params,
struct tee_param *params)
{
return TEE_ERROR_NOT_SUPPORTED;
}
}
-#endif /*OPTEE_TA_AVB*/
+#endif /* OPTEE_TA_AVB */
+
+#ifdef CONFIG_OPTEE_TA_RPC_TEST
+static u32 ta_rpc_test_open_session(struct udevice *dev, uint num_params,
+ struct tee_param *params)
+{
+ /*
+ * We don't expect additional parameters when opening a session to
+ * this TA.
+ */
+ return check_params(TEE_PARAM_ATTR_TYPE_NONE, TEE_PARAM_ATTR_TYPE_NONE,
+ TEE_PARAM_ATTR_TYPE_NONE, TEE_PARAM_ATTR_TYPE_NONE,
+ num_params, params);
+}
+
+static void fill_i2c_rpc_params(struct optee_msg_arg *msg_arg, u64 bus_num,
+ u64 chip_addr, u64 xfer_flags, u64 op,
+ struct tee_param_memref memref)
+{
+ msg_arg->params[0].attr = OPTEE_MSG_ATTR_TYPE_VALUE_INPUT;
+ msg_arg->params[1].attr = OPTEE_MSG_ATTR_TYPE_VALUE_INPUT;
+ msg_arg->params[2].attr = OPTEE_MSG_ATTR_TYPE_RMEM_INOUT;
+ msg_arg->params[3].attr = OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT;
+
+ /* trigger I2C services of TEE supplicant */
+ msg_arg->cmd = OPTEE_MSG_RPC_CMD_I2C_TRANSFER;
+
+ msg_arg->params[0].u.value.a = op;
+ msg_arg->params[0].u.value.b = bus_num;
+ msg_arg->params[0].u.value.c = chip_addr;
+ msg_arg->params[1].u.value.a = xfer_flags;
+
+ /* buffer to read/write data */
+ msg_arg->params[2].u.rmem.shm_ref = (ulong)memref.shm;
+ msg_arg->params[2].u.rmem.size = memref.size;
+ msg_arg->params[2].u.rmem.offs = memref.shm_offs;
+
+ msg_arg->num_params = 4;
+}
+
+static u32 ta_rpc_test_invoke_func(struct udevice *dev, u32 func,
+ uint num_params,
+ struct tee_param *params)
+{
+ struct tee_shm *shm;
+ struct tee_param_memref memref_data;
+ struct optee_msg_arg *msg_arg;
+ int chip_addr, bus_num, op, xfer_flags;
+ int res;
+
+ res = check_params(TEE_PARAM_ATTR_TYPE_VALUE_INPUT,
+ TEE_PARAM_ATTR_TYPE_MEMREF_INOUT,
+ TEE_PARAM_ATTR_TYPE_NONE,
+ TEE_PARAM_ATTR_TYPE_NONE,
+ num_params, params);
+ if (res)
+ return TEE_ERROR_BAD_PARAMETERS;
+
+ bus_num = params[0].u.value.a;
+ chip_addr = params[0].u.value.b;
+ xfer_flags = params[0].u.value.c;
+ memref_data = params[1].u.memref;
+
+ switch (func) {
+ case TA_RPC_TEST_CMD_I2C_READ:
+ op = OPTEE_MSG_RPC_CMD_I2C_TRANSFER_RD;
+ break;
+ case TA_RPC_TEST_CMD_I2C_WRITE:
+ op = OPTEE_MSG_RPC_CMD_I2C_TRANSFER_WR;
+ break;
+ default:
+ return TEE_ERROR_NOT_SUPPORTED;
+ }
+
+ /*
+ * Fill params for an RPC call to tee supplicant
+ */
+ res = get_msg_arg(dev, 4, &shm, &msg_arg);
+ if (res)
+ goto out;
+
+ fill_i2c_rpc_params(msg_arg, bus_num, chip_addr, xfer_flags, op,
+ memref_data);
+
+ /* Make an RPC call to tee supplicant */
+ optee_suppl_cmd(dev, shm, 0);
+ res = msg_arg->ret;
+out:
+ tee_shm_free(shm);
+
+ return res;
+}
+#endif /* CONFIG_OPTEE_TA_RPC_TEST */
static const struct ta_entry ta_entries[] = {
#ifdef CONFIG_OPTEE_TA_AVB
.invoke_func = ta_avb_invoke_func,
},
#endif
+#ifdef CONFIG_OPTEE_TA_RPC_TEST
+ { .uuid = TA_RPC_TEST_UUID,
+ .open_session = ta_rpc_test_open_session,
+ .invoke_func = ta_rpc_test_invoke_func,
+ },
+#endif
};
static void sandbox_tee_get_version(struct udevice *dev,
#include <errno.h>
#include <log.h>
#include <thermal.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/device.h>
#include <asm/arch/sci/sci.h>
#include <config.h>
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <errno.h>
#include <timer.h>
#include <asm/arcregs.h>
+#include <asm/global_data.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#include <errno.h>
#include <init.h>
#include <timer.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <time.h>
#include <timer.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/bitops.h>
#include <common.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <asm/global_data.h>
#include <dm/ofnode.h>
#include <mapmem.h>
#include <asm/arch-rockchip/timer.h>
#include <clk.h>
#include <cpu.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <time.h>
#include <timer.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/i8254.h>
#include <asm/ibmpc.h>
print_buffer(0, (void *)sendbuf, 1, send_size, 0);
#endif
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
res = i2c_write(0x29, 0, 0, (uchar *)sendbuf, send_size);
#else
res = dm_i2c_write(dev, 0, sendbuf, send_size);
}
start = get_timer(0);
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
while ((res = i2c_read(0x29, 0, 0, recvbuf, 10)))
#else
while ((res = dm_i2c_read(dev, 0, recvbuf, 10)))
return -1;
} else {
*recv_len = hdr_recv_len;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
res = i2c_read(0x29, 0, 0, recvbuf, *recv_len);
#else
res = dm_i2c_read(dev, 0, recvbuf, *recv_len);
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <linux/usb/otg.h>
#include <linux/usb/ch9.h>
#include <linux/usb/phy.h>
static const struct udevice_id dwc2_udc_otg_ids[] = {
{ .compatible = "snps,dwc2" },
{ .compatible = "brcm,bcm2835-usb" },
- { .compatible = "st,stm32mp1-hsotg",
+ { .compatible = "st,stm32mp15-hsotg",
.data = (ulong)dwc2_set_stm32mp1_hsotg_params },
{},
};
#include <dm.h>
#include <errno.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <log.h>
#include <pci.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <usb/ehci-ci.h>
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <usb.h>
#include <linux/delay.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <usb/ehci-ci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <usb.h>
#include <errno.h>
#include <wait_bit.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <usb/ehci-ci.h>
#include <log.h>
#include <usb.h>
#include <errno.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
{
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
#else
return dm_i2c_write(dev, reg, &value, 1);
static void isp1301_configure(struct udevice *dev)
{
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_set_bus_num(I2C_2);
#endif
u32 ret;
struct udevice *dev = NULL;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
if (ret) {
debug("%s: No bus %d\n", __func__, I2C_2);
struct udevice *dev = NULL;
int ret = 0;
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
if (ret) {
debug("%s: No bus %d\n", __func__, I2C_2);
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <malloc.h>
ctrl->dcbaa->dev_context_ptrs[0] = 0;
- free((void *)(uintptr_t)le64_to_cpu(ctrl->scratchpad->sp_array[0]));
+ free(xhci_bus_to_virt(ctrl, le64_to_cpu(ctrl->scratchpad->sp_array[0])));
free(ctrl->scratchpad->sp_array);
free(ctrl->scratchpad);
ctrl->scratchpad = NULL;
* @param link_trbs flag to indicate whether to link the trbs or NOT
* @return none
*/
-static void xhci_link_segments(struct xhci_segment *prev,
- struct xhci_segment *next, bool link_trbs)
+static void xhci_link_segments(struct xhci_ctrl *ctrl, struct xhci_segment *prev,
+ struct xhci_segment *next, bool link_trbs)
{
u32 val;
u64 val_64 = 0;
return;
prev->next = next;
if (link_trbs) {
- val_64 = virt_to_phys(next->trbs);
+ val_64 = xhci_virt_to_bus(ctrl, next->trbs);
prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
cpu_to_le64(val_64);
* @param link_trbs flag to indicate whether to link the trbs or NOT
* @return pointer to the newly created RING
*/
-struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs)
+struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs,
+ bool link_trbs)
{
struct xhci_ring *ring;
struct xhci_segment *prev;
next = xhci_segment_alloc();
BUG_ON(!next);
- xhci_link_segments(prev, next, link_trbs);
+ xhci_link_segments(ctrl, prev, next, link_trbs);
prev = next;
num_segs--;
}
- xhci_link_segments(prev, ring->first_seg, link_trbs);
+ xhci_link_segments(ctrl, prev, ring->first_seg, link_trbs);
if (link_trbs) {
/* See section 4.9.2.1 and 6.4.4.1 */
prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
struct xhci_hccr *hccr = ctrl->hccr;
struct xhci_hcor *hcor = ctrl->hcor;
struct xhci_scratchpad *scratchpad;
+ uint64_t val_64;
int num_sp;
uint32_t page_size;
void *buf;
scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
if (!scratchpad->sp_array)
goto fail_sp2;
- ctrl->dcbaa->dev_context_ptrs[0] =
- cpu_to_le64((uintptr_t)scratchpad->sp_array);
+
+ val_64 = xhci_virt_to_bus(ctrl, scratchpad->sp_array);
+ ctrl->dcbaa->dev_context_ptrs[0] = cpu_to_le64(val_64);
xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[0],
sizeof(ctrl->dcbaa->dev_context_ptrs[0]));
xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
for (i = 0; i < num_sp; i++) {
- uintptr_t ptr = (uintptr_t)buf + i * page_size;
- scratchpad->sp_array[i] = cpu_to_le64(ptr);
+ val_64 = xhci_virt_to_bus(ctrl, buf + i * page_size);
+ scratchpad->sp_array[i] = cpu_to_le64(val_64);
}
xhci_flush_cache((uintptr_t)scratchpad->sp_array,
}
/* Allocate endpoint 0 ring */
- virt_dev->eps[0].ring = xhci_ring_alloc(1, true);
+ virt_dev->eps[0].ring = xhci_ring_alloc(ctrl, 1, true);
- byte_64 = virt_to_phys(virt_dev->out_ctx->bytes);
+ byte_64 = xhci_virt_to_bus(ctrl, virt_dev->out_ctx->bytes);
/* Point to output device context in dcbaa. */
ctrl->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(byte_64);
return -ENOMEM;
}
- val_64 = virt_to_phys(ctrl->dcbaa);
+ val_64 = xhci_virt_to_bus(ctrl, ctrl->dcbaa);
/* Set the pointer in DCBAA register */
xhci_writeq(&hcor->or_dcbaap, val_64);
/* Command ring control pointer register initialization */
- ctrl->cmd_ring = xhci_ring_alloc(1, true);
+ ctrl->cmd_ring = xhci_ring_alloc(ctrl, 1, true);
/* Set the address in the Command Ring Control register */
- trb_64 = virt_to_phys(ctrl->cmd_ring->first_seg->trbs);
+ trb_64 = xhci_virt_to_bus(ctrl, ctrl->cmd_ring->first_seg->trbs);
val_64 = xhci_readq(&hcor->or_crcr);
val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
(trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
ctrl->ir_set = &ctrl->run_regs->ir_set[0];
/* Event ring does not maintain link TRB */
- ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false);
+ ctrl->event_ring = xhci_ring_alloc(ctrl, ERST_NUM_SEGS, false);
ctrl->erst.entries = xhci_malloc(sizeof(struct xhci_erst_entry) *
ERST_NUM_SEGS);
for (val = 0, seg = ctrl->event_ring->first_seg;
val < ERST_NUM_SEGS;
val++) {
- trb_64 = virt_to_phys(seg->trbs);
struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
+ trb_64 = xhci_virt_to_bus(ctrl, seg->trbs);
entry->seg_addr = cpu_to_le64(trb_64);
entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
entry->rsvd = 0;
xhci_flush_cache((uintptr_t)ctrl->erst.entries,
ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
- deq = virt_to_phys(ctrl->event_ring->dequeue);
+ deq = xhci_virt_to_bus(ctrl, ctrl->event_ring->dequeue);
/* Update HC event ring dequeue pointer */
xhci_writeq(&ctrl->ir_set->erst_dequeue,
/* this is the event ring segment table pointer */
val_64 = xhci_readq(&ctrl->ir_set->erst_base);
val_64 &= ERST_PTR_MASK;
- val_64 |= virt_to_phys(ctrl->erst.entries) & ~ERST_PTR_MASK;
+ val_64 |= xhci_virt_to_bus(ctrl, ctrl->erst.entries) & ~ERST_PTR_MASK;
xhci_writeq(&ctrl->ir_set->erst_base, val_64);
/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
- trb_64 = virt_to_phys(virt_dev->eps[0].ring->first_seg->trbs);
+ trb_64 = xhci_virt_to_bus(ctrl, virt_dev->eps[0].ring->first_seg->trbs);
ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
/*
struct phy_bulk phys;
int num_u2ports;
int num_u3ports;
+ u32 u3p_dis_msk;
+ u32 u2p_dis_msk;
};
static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
{
+ int u3_ports_disabed = 0;
u32 value;
u32 check_val;
int ret;
/* power on host ip */
clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
- /* power on and enable all u3 ports */
+ /* power on and enable u3 ports except skipped ones */
for (i = 0; i < mtk->num_u3ports; i++) {
+ if (BIT(i) & mtk->u3p_dis_msk) {
+ u3_ports_disabed++;
+ continue;
+ }
+
clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i),
CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
CTRL_U3_PORT_HOST_SEL);
}
- /* power on and enable all u2 ports */
+ /* power on and enable u2 ports except skipped ones */
for (i = 0; i < mtk->num_u2ports; i++) {
+ if (BIT(i) & mtk->u2p_dis_msk)
+ continue;
+
clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i),
CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
CTRL_U2_PORT_HOST_SEL);
check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
STS1_SYS125_RST | STS1_XHCI_RST;
- if (mtk->num_u3ports)
+ if (mtk->num_u3ports > u3_ports_disabed)
check_val |= STS1_U3_MAC_RST;
ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value,
if (ret)
debug("can't get vbus regulator %d!\n", ret);
+ /* optional properties to disable ports, ignore the error */
+ dev_read_u32(dev, "mediatek,u3p-dis-msk", &mtk->u3p_dis_msk);
+ dev_read_u32(dev, "mediatek,u2p-dis-msk", &mtk->u2p_dis_msk);
+ dev_info(dev, "ports disabled mask: u3p-0x%x, u2p-0x%x\n",
+ mtk->u3p_dis_msk, mtk->u2p_dis_msk);
+
return 0;
}
#include <usb.h>
#include <usb/xhci.h>
-static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
- struct xhci_hcor **ret_hcor)
+static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
+ struct xhci_hcor **ret_hcor)
{
struct xhci_hccr *hccr;
struct xhci_hcor *hcor;
hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ if (!hccr) {
+ printf("xhci-pci init cannot map PCI mem bar\n");
+ return -EIO;
+ }
+
hcor = (struct xhci_hcor *)((uintptr_t) hccr +
HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
dm_pci_write_config32(dev, PCI_COMMAND, cmd);
+ return 0;
}
static int xhci_pci_probe(struct udevice *dev)
{
struct xhci_hccr *hccr;
struct xhci_hcor *hcor;
+ int ret;
- xhci_pci_init(dev, &hccr, &hcor);
+ ret = xhci_pci_init(dev, &hccr, &hcor);
+ if (ret)
+ return ret;
return xhci_register(dev, hccr, hcor);
}
.ops = &xhci_usb_ops,
.plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct xhci_ctrl),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
+ .flags = DM_FLAG_OS_PREPARE | DM_FLAG_ALLOC_PRIV_DMA,
};
static struct pci_device_id xhci_pci_supported[] = {
u32 ep_index, trb_type cmd)
{
u32 fields[4];
- u64 val_64 = virt_to_phys(ptr);
+ u64 val_64 = 0;
BUG_ON(prepare_ring(ctrl, ctrl->cmd_ring, EP_STATE_RUNNING));
+ if (ptr)
+ val_64 = xhci_virt_to_bus(ctrl, ptr);
+
fields[0] = lower_32_bits(val_64);
fields[1] = upper_32_bits(val_64);
fields[2] = 0;
/* Inform the hardware */
xhci_writeq(&ctrl->ir_set->erst_dequeue,
- virt_to_phys(ctrl->event_ring->dequeue) | ERST_EHB);
+ xhci_virt_to_bus(ctrl, ctrl->event_ring->dequeue) | ERST_EHB);
}
/**
u64 addr;
int ret;
u32 trb_fields[4];
- u64 val_64 = virt_to_phys(buffer);
+ u64 val_64 = xhci_virt_to_bus(ctrl, buffer);
void *last_transfer_trb_addr;
int available_length;
return -ETIMEDOUT;
}
- if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer))
- != (uintptr_t)last_transfer_trb_addr) {
+ if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer)) !=
+ (uintptr_t)xhci_virt_to_bus(ctrl, last_transfer_trb_addr)) {
available_length -=
(int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len));
xhci_acknowledge_event(ctrl);
if (length > 0) {
if (req->requesttype & USB_DIR_IN)
field |= TRB_DIR_IN;
- buf_64 = virt_to_phys(buffer);
+ buf_64 = xhci_virt_to_bus(ctrl, buffer);
trb_fields[0] = lower_32_bits(buf_64);
trb_fields[1] = upper_32_bits(buf_64);
ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
/* Allocate the ep rings */
- virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
+ virt_dev->eps[ep_index].ring = xhci_ring_alloc(ctrl, 1, true);
if (!virt_dev->eps[ep_index].ring)
return -ENOMEM;
cpu_to_le32(MAX_BURST(max_burst) |
ERROR_COUNT(err_count));
- trb_64 = virt_to_phys(virt_dev->eps[ep_index].ring->enqueue);
+ trb_64 = xhci_virt_to_bus(ctrl, virt_dev->eps[ep_index].ring->enqueue);
ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
virt_dev->eps[ep_index].ring->cycle_state);
#include <asm/arch/da8xx-usb.h>
#include <linux/delay.h>
#include <linux/usb/otg.h>
+#include <asm/global_data.h>
#include <asm/omap_musb.h>
#include <generic-phy.h>
#include "linux-compat.h"
#include <dm/lists.h>
#include <linux/err.h>
#include <linux/usb/otg.h>
+#include <asm/global_data.h>
#include <asm/omap_common.h>
#include <asm/omap_musb.h>
#include <twl4030.h>
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/usb/otg.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <common.h>
#include <hang.h>
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
- struct video_uc_platdata. That memory is then reserved for use after
+ struct video_uc_plat. That memory is then reserved for use after
relocation. But PCI drivers cannot be bound before relocation unless
they are mentioned in the devicetree.
U-Boot) and then copied to the hardware frame-buffer as needed.
To use this, your video driver must set @copy_base in
- struct video_uc_platdata.
+ struct video_uc_plat.
config BACKLIGHT_PWM
bool "Generic PWM based Backlight Driver"
With this option you can adjust the text size and use a variety of
fonts. Note that this is noticeably slower than with normal console.
+config DM_PANEL_HX8238D
+ bool "Enable Himax HX-8238D LCD driver"
+ depends on DM_VIDEO
+ help
+ Support for HX-8238D LCD Panel
+ The HX8238-D is a single chip controller and driver LSI that
+ integrates the power circuit.
+ It can drive a maximum 960x240 dot graphics on a-TFT panel
+ displays in 16M colors with dithering.
+
config CONSOLE_TRUETYPE_SIZE
int "TrueType font size"
depends on CONSOLE_TRUETYPE
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
obj-$(CONFIG_PANEL) += panel-uclass.o
+obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o
obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
endif
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
-obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
#include <log.h>
#include <malloc.h>
#include <part.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <log.h>
#include <part.h>
#include <video.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
static const struct udevice_id bcm2835_video_ids[] = {
{ .compatible = "brcm,bcm2835-hdmi" },
+ { .compatible = "brcm,bcm2711-hdmi0" },
{ .compatible = "brcm,bcm2708-fb" },
{ }
};
#include <i2c.h>
#include <log.h>
#include <video_bridge.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <power/regulator.h>
#include <vbe.h>
#include <video.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/mtrr.h>
#include <version.h>
#include <malloc.h>
#include <video.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#if defined(CONFIG_VIDEO_MXS)
#include <malloc.h>
#include <memalign.h>
#include <video_fb.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <linux/fb.h>
#include <display.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <panel.h>
#include <video.h>
#include <log.h>
#include <malloc.h>
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <dm/devres.h>
#include <linux/libfdt.h>
#include <linux/compat.h>
#include <init.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copied from simple-panel
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2018 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
+ * Modified by Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
+ *
+ * Panel Initialization for HX8238D panel from Himax
+ * Resolution: 320x240
+ * Color-Mode: RGB
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <panel.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register Address */
+#define HX8238D_OUTPUT_CTRL_ADDR 0x01
+#define HX8238D_LCD_AC_CTRL_ADDR 0x02
+#define HX8238D_POWER_CTRL_1_ADDR 0x03
+#define HX8238D_DATA_CLR_CTRL_ADDR 0X04
+#define HX8238D_FUNCTION_CTRL_ADDR 0x05
+#define HX8238D_LED_CTRL_ADDR 0x08
+#define HX8238D_CONT_BRIGHT_CTRL_ADDR 0x0A
+#define HX8238D_FRAME_CYCLE_CTRL_ADDR 0x0B
+#define HX8238D_POWER_CTRL_2_ADDR 0x0D
+#define HX8238D_POWER_CTRL_3_ADDR 0x0E
+#define HX8238D_GATE_SCAN_POS_ADDR 0x0F
+#define HX8238D_HORIZONTAL_PORCH_ADDR 0x16
+#define HX8238D_VERTICAL_PORCH_ADDR 0x17
+#define HX8238D_POWER_CTRL_4_ADDR 0x1E
+#define HX8238D_GAMMA_CTRL_1_ADDR 0x30
+#define HX8238D_GAMMA_CTRL_2_ADDR 0x31
+#define HX8238D_GAMMA_CTRL_3_ADDR 0x32
+#define HX8238D_GAMMA_CTRL_4_ADDR 0x33
+#define HX8238D_GAMMA_CTRL_5_ADDR 0x34
+#define HX8238D_GAMMA_CTRL_6_ADDR 0x35
+#define HX8238D_GAMMA_CTRL_7_ADDR 0x36
+#define HX8238D_GAMMA_CTRL_8_ADDR 0x37
+#define HX8238D_GAMMA_CTRL_9_ADDR 0x3A
+#define HX8238D_GAMMA_CTRL_10_ADDR 0x3B
+
+/* Register Data */
+#define HX8238D_OUTPUT_CTRL 0x6300
+#define HX8238D_LCD_AC_CTRL 0x0200
+#define HX8238D_POWER_CTRL_1 0x6564
+#define HX8238D_DATA_CLR_CTRL 0x04C7
+#define HX8238D_FUNCTION_CTRL 0xA884
+#define HX8238D_LED_CTRL 0x00CE
+#define HX8238D_CONT_BRIGHT_CTRL 0x4008
+#define HX8238D_FRAME_CYCLE_CTRL 0xD400
+#define HX8238D_POWER_CTRL_2 0x3229
+#define HX8238D_POWER_CTRL_3 0x1200
+#define HX8238D_GATE_SCAN_POS 0x0000
+#define HX8238D_HORIZONTAL_PORCH 0x9F80
+#define HX8238D_VERTICAL_PORCH 0x3F02
+#define HX8238D_POWER_CTRL_4 0x005C
+
+/* Gamma Control */
+#define HX8238D_GAMMA_CTRL_1 0x0103
+#define HX8238D_GAMMA_CTRL_2 0x0407
+#define HX8238D_GAMMA_CTRL_3 0x0705
+#define HX8238D_GAMMA_CTRL_4 0x0002
+#define HX8238D_GAMMA_CTRL_5 0x0505
+#define HX8238D_GAMMA_CTRL_6 0x0303
+#define HX8238D_GAMMA_CTRL_7 0x0707
+#define HX8238D_GAMMA_CTRL_8 0x0100
+#define HX8238D_GAMMA_CTRL_9 0x1F00
+#define HX8238D_GAMMA_CTRL_10 0x000F
+
+/* Primary SPI register identification, 011100 */
+/* Select register, RS=0, RS=0 */
+/* Write register, RS=1, RW=0 */
+#define HX8238D_PRIMARY_SELECT_REG 0x70
+#define HX8238D_PRIMARY_WRITE_REG (HX8238D_PRIMARY_SELECT_REG | (0x1 << 1))
+
+#define HX8238D_REG_BIT_LEN 24
+
+struct hx8238d_priv {
+ struct spi_slave *spi;
+};
+
+static int hx8238d_ofdata_to_platdata(struct udevice *dev)
+{
+ struct hx8238d_priv *priv = dev_get_priv(dev);
+
+ priv->spi = dev_get_parent_priv(dev);
+
+ return 0;
+}
+
+/* data[0] => REGISTER ADDRESS */
+/* data[1] => REGISTER VALUE */
+struct hx8238d_command {
+ u16 data[2];
+};
+
+static struct hx8238d_command hx8238d_init_commands[] = {
+ { .data = { HX8238D_OUTPUT_CTRL_ADDR, HX8238D_OUTPUT_CTRL } },
+ { .data = { HX8238D_LCD_AC_CTRL_ADDR, HX8238D_LCD_AC_CTRL } },
+ { .data = { HX8238D_POWER_CTRL_1_ADDR, HX8238D_POWER_CTRL_1 } },
+ { .data = { HX8238D_DATA_CLR_CTRL_ADDR, HX8238D_DATA_CLR_CTRL } },
+ { .data = { HX8238D_FUNCTION_CTRL_ADDR, HX8238D_FUNCTION_CTRL } },
+ { .data = { HX8238D_LED_CTRL_ADDR, HX8238D_LED_CTRL } },
+ { .data = { HX8238D_CONT_BRIGHT_CTRL_ADDR, HX8238D_CONT_BRIGHT_CTRL } },
+ { .data = { HX8238D_FRAME_CYCLE_CTRL_ADDR, HX8238D_FRAME_CYCLE_CTRL } },
+ { .data = { HX8238D_POWER_CTRL_2_ADDR, HX8238D_POWER_CTRL_2 } },
+ { .data = { HX8238D_POWER_CTRL_3_ADDR, HX8238D_POWER_CTRL_3 } },
+ { .data = { HX8238D_GATE_SCAN_POS_ADDR, HX8238D_GATE_SCAN_POS } },
+ { .data = { HX8238D_HORIZONTAL_PORCH_ADDR, HX8238D_HORIZONTAL_PORCH } },
+ { .data = { HX8238D_VERTICAL_PORCH_ADDR, HX8238D_VERTICAL_PORCH } },
+ { .data = { HX8238D_POWER_CTRL_4_ADDR, HX8238D_POWER_CTRL_4 } },
+ { .data = { HX8238D_GAMMA_CTRL_1_ADDR, HX8238D_GAMMA_CTRL_1 } },
+ { .data = { HX8238D_GAMMA_CTRL_2_ADDR, HX8238D_GAMMA_CTRL_2 } },
+ { .data = { HX8238D_GAMMA_CTRL_3_ADDR, HX8238D_GAMMA_CTRL_3 } },
+ { .data = { HX8238D_GAMMA_CTRL_4_ADDR, HX8238D_GAMMA_CTRL_4 } },
+ { .data = { HX8238D_GAMMA_CTRL_5_ADDR, HX8238D_GAMMA_CTRL_5 } },
+ { .data = { HX8238D_GAMMA_CTRL_6_ADDR, HX8238D_GAMMA_CTRL_6 } },
+ { .data = { HX8238D_GAMMA_CTRL_7_ADDR, HX8238D_GAMMA_CTRL_7 } },
+ { .data = { HX8238D_GAMMA_CTRL_8_ADDR, HX8238D_GAMMA_CTRL_8 } },
+ { .data = { HX8238D_GAMMA_CTRL_9_ADDR, HX8238D_GAMMA_CTRL_9 } },
+ { .data = { HX8238D_GAMMA_CTRL_10_ADDR, HX8238D_GAMMA_CTRL_10 } },
+};
+
+/*
+ * Generate Primary Register Buffer for Register Select and Register Write
+ * First 6 MSB bits of Primary Register is represented with 011100
+ *
+ */
+static void hx8238d_generate_reg_buffers(struct hx8238d_command command,
+ u8 *sr_buf, uint8_t *wr_buf)
+{
+ struct hx8238d_command cmd = command;
+
+ sr_buf[0] = HX8238D_PRIMARY_SELECT_REG;
+ sr_buf[1] = (cmd.data[0] >> 8) & 0xff;
+ sr_buf[2] = (cmd.data[0]) & 0xff;
+
+ wr_buf[0] = HX8238D_PRIMARY_WRITE_REG;
+ wr_buf[1] = (cmd.data[1] >> 8) & 0xff;
+ wr_buf[2] = (cmd.data[1]) & 0xff;
+}
+
+static int hx8238d_probe(struct udevice *dev)
+{
+ struct hx8238d_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = spi_claim_bus(priv->spi);
+ if (ret) {
+ debug("Failed to claim bus: %d\n", ret);
+ return ret;
+ }
+
+ for (int i = 0; i < ARRAY_SIZE(hx8238d_init_commands); i++) {
+ u8 sr_buf[3], wr_buf[3];
+ const struct hx8238d_command cmd = hx8238d_init_commands[i];
+
+ hx8238d_generate_reg_buffers(cmd, sr_buf, wr_buf);
+ ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, sr_buf, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("Failed to select register %d\n", ret);
+ goto free;
+ }
+
+ ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, wr_buf, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("Failed to write value %d\n", ret);
+ goto free;
+ }
+ }
+
+free:
+ spi_release_bus(priv->spi);
+ return ret;
+}
+
+static const struct udevice_id hx8238d_ids[] = {
+ { .compatible = "himax,hx8238d" },
+ { }
+};
+
+U_BOOT_DRIVER(hx8238d) = {
+ .name = "hx8238d",
+ .id = UCLASS_PANEL,
+ .of_match = hx8238d_ids,
+ .ofdata_to_platdata = hx8238d_ofdata_to_platdata,
+ .probe = hx8238d_probe,
+ .priv_auto_alloc_size = sizeof(struct hx8238d_priv),
+};
#include <pci_rom.h>
#include <vbe.h>
#include <video.h>
+#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/mtrr.h>
#include <display.h>
#endif
#include <fdtdec.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <os.h>
#include <fdt_support.h>
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
- */
-
-/*
- * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
- * PCI and video mode code was derived from smiLynxEM driver.
- */
-
-#include <common.h>
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include <env.h>
-#include <pci.h>
-#include <video_fb.h>
-#include "videomodes.h"
-#include <mb862xx.h>
-
-#if defined(CONFIG_POST)
-#include <post.h>
-#endif
-
-/*
- * Graphic Device
- */
-GraphicDevice mb862xx;
-
-/*
- * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
- */
-#define VIDEO_MEM_SIZE 0x01FC0000
-
-#if defined(CONFIG_PCI)
-#if defined(CONFIG_VIDEO_CORALP)
-
-static struct pci_device_id supported[] = {
- { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
- { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
- { }
-};
-
-/* Internal clock frequency divider table, index is mode number */
-unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
-#endif
-#endif
-
-#if defined(CONFIG_VIDEO_CORALP)
-#define rd_io in32r
-#define wr_io out32r
-#else
-#define rd_io(addr) in_be32((volatile unsigned *)(addr))
-#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
-#endif
-
-#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
-#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
- (val))
-#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
-#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
- (val))
-#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
-#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
-
-#if defined(CONFIG_VIDEO_CORALP)
-#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
-#else
-#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
-#endif
-
-#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
- (GC_DISP_BASE | GC_L0PAL0) + \
- ((idx) << 2)), (val))
-
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
-static void gdc_sw_reset (void)
-{
- GraphicDevice *dev = &mb862xx;
-
- HOST_WR_REG (GC_SRST, 0x1);
- udelay(500);
- video_hw_init ();
-}
-
-
-static void de_wait (void)
-{
- GraphicDevice *dev = &mb862xx;
- int lc = 0x10000;
-
- /*
- * Sync with software writes to framebuffer,
- * try to reset if engine locked
- */
- while (DE_RD_REG (GC_CTR) & 0x00000131)
- if (lc-- < 0) {
- gdc_sw_reset ();
- puts ("gdc reset done after drawing engine lock.\n");
- break;
- }
-}
-
-static void de_wait_slots (int slots)
-{
- GraphicDevice *dev = &mb862xx;
- int lc = 0x10000;
-
- /* Wait for free fifo slots */
- while (DE_RD_REG (GC_IFCNT) < slots)
- if (lc-- < 0) {
- gdc_sw_reset ();
- puts ("gdc reset done after drawing engine lock.\n");
- break;
- }
-}
-#endif
-
-#if !defined(CONFIG_VIDEO_CORALP)
-static void board_disp_init (void)
-{
- GraphicDevice *dev = &mb862xx;
- const gdc_regs *regs = board_get_regs ();
-
- while (regs->index) {
- DISP_WR_REG (regs->index, regs->value);
- regs++;
- }
-}
-#endif
-
-/*
- * Init drawing engine if accel enabled.
- * Also clears visible framebuffer.
- */
-static void de_init (void)
-{
- GraphicDevice *dev = &mb862xx;
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
- int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
-
- dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
-
- /* Setup mode and fbbase, xres, fg, bg */
- de_wait_slots (2);
- DE_WR_FIFO (0xf1010108);
- DE_WR_FIFO (cf | 0x0300);
- DE_WR_REG (GC_FBR, 0x0);
- DE_WR_REG (GC_XRES, dev->winSizeX);
- DE_WR_REG (GC_FC, 0x0);
- DE_WR_REG (GC_BC, 0x0);
- /* Reset clipping */
- DE_WR_REG (GC_CXMIN, 0x0);
- DE_WR_REG (GC_CXMAX, dev->winSizeX);
- DE_WR_REG (GC_CYMIN, 0x0);
- DE_WR_REG (GC_CYMAX, dev->winSizeY);
-
- /* Clear framebuffer using drawing engine */
- de_wait_slots (3);
- DE_WR_FIFO (0x09410000);
- DE_WR_FIFO (0x00000000);
- DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
- /* sync with SW access to framebuffer */
- de_wait ();
-#else
- unsigned int i, *p;
-
- i = dev->winSizeX * dev->winSizeY;
- p = (unsigned int *)dev->frameAdrs;
- while (i--)
- *p++ = 0;
-#endif
-}
-
-#if defined(CONFIG_VIDEO_CORALP)
-/* use CCF and MMR parameters for Coral-P Eval. Board as default */
-#ifndef CONFIG_SYS_MB862xx_CCF
-#define CONFIG_SYS_MB862xx_CCF 0x00090000
-#endif
-#ifndef CONFIG_SYS_MB862xx_MMR
-#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
-#endif
-
-unsigned int pci_video_init (void)
-{
- GraphicDevice *dev = &mb862xx;
- pci_dev_t devbusfn;
- u16 device;
-
- if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
- puts("controller not present\n");
- return 0;
- }
-
- /* PCI setup */
- pci_write_config_dword (devbusfn, PCI_COMMAND,
- (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
- pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
- dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
-
- if (dev->frameAdrs == 0) {
- puts ("PCI config: failed to get base address\n");
- return 0;
- }
-
- dev->pciBase = dev->frameAdrs;
-
- puts("Coral-");
-
- pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
- switch (device) {
- case PCI_DEVICE_ID_CORAL_P:
- puts("P\n");
- break;
- case PCI_DEVICE_ID_CORAL_PA:
- puts("PA\n");
- break;
- default:
- puts("Unknown\n");
- return 0;
- }
-
- /* Setup clocks and memory mode for Coral-P(A) */
- HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
- udelay(200);
- HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
- udelay(100);
- return dev->frameAdrs;
-}
-
-unsigned int card_init (void)
-{
- GraphicDevice *dev = &mb862xx;
- unsigned int cf, videomode, div = 0;
- unsigned long t1, hsync, vsync;
- char *penv;
- int tmp, i, bpp;
- struct ctfb_res_modes *res_mode;
- struct ctfb_res_modes var_mode;
-
- memset (dev, 0, sizeof (GraphicDevice));
-
- if (!pci_video_init ())
- return 0;
-
- tmp = 0;
- videomode = 0x310;
- /* get video mode via environment */
- penv = env_get("videomode");
- if (penv) {
- /* decide if it is a string */
- if (penv[0] <= '9') {
- videomode = (int) simple_strtoul (penv, NULL, 16);
- tmp = 1;
- }
- } else {
- tmp = 1;
- }
-
- if (tmp) {
- /* parameter are vesa modes, search params */
- for (i = 0; i < VESA_MODES_COUNT; i++) {
- if (vesa_modes[i].vesanr == videomode)
- break;
- }
- if (i == VESA_MODES_COUNT) {
- printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
- videomode);
- i = 0;
- }
- res_mode = (struct ctfb_res_modes *)
- &res_mode_init[vesa_modes[i].resindex];
- if (vesa_modes[i].resindex > 2) {
- puts ("\tUnsupported resolution, using default\n");
- bpp = vesa_modes[1].bits_per_pixel;
- div = fr_div[1];
- }
- bpp = vesa_modes[i].bits_per_pixel;
- div = fr_div[vesa_modes[i].resindex];
- } else {
- res_mode = (struct ctfb_res_modes *) &var_mode;
- bpp = video_get_params (res_mode, penv);
- }
-
- /* calculate hsync and vsync freq (info only) */
- t1 = (res_mode->left_margin + res_mode->xres +
- res_mode->right_margin + res_mode->hsync_len) / 8;
- t1 *= 8;
- t1 *= res_mode->pixclock;
- t1 /= 1000;
- hsync = 1000000000L / t1;
- t1 *= (res_mode->upper_margin + res_mode->yres +
- res_mode->lower_margin + res_mode->vsync_len);
- t1 /= 1000;
- vsync = 1000000000L / t1;
-
- /* fill in Graphic device struct */
- sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
- res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
- printf ("\t%s\n", dev->modeIdent);
- dev->winSizeX = res_mode->xres;
- dev->winSizeY = res_mode->yres;
- dev->memSize = VIDEO_MEM_SIZE;
-
- switch (bpp) {
- case 8:
- dev->gdfIndex = GDF__8BIT_INDEX;
- dev->gdfBytesPP = 1;
- break;
- case 15:
- case 16:
- dev->gdfIndex = GDF_15BIT_555RGB;
- dev->gdfBytesPP = 2;
- break;
- default:
- printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
- bpp);
- puts ("\tfallback to 15bpp\n");
- dev->gdfIndex = GDF_15BIT_555RGB;
- dev->gdfBytesPP = 2;
- }
-
- /* Setup dot clock (internal pll, division rate) */
- DISP_WR_REG (GC_DCM1, div);
- /* L0 init */
- cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
- DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
- (dev->winSizeY - 1) | cf);
- DISP_WR_REG (GC_L0OA0, 0x0);
- DISP_WR_REG (GC_L0DA0, 0x0);
- DISP_WR_REG (GC_L0DY_L0DX, 0x0);
- DISP_WR_REG (GC_L0EM, 0x0);
- DISP_WR_REG (GC_L0WY_L0WX, 0x0);
- DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
-
- /* Display timing init */
- DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
- res_mode->left_margin +
- res_mode->right_margin +
- res_mode->hsync_len - 1) << 16);
- DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
- (dev->winSizeX - 1));
- DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
- (res_mode->hsync_len - 1) << 16 |
- (dev->winSizeX +
- res_mode->right_margin - 1));
- DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
- res_mode->upper_margin +
- res_mode->vsync_len - 1) << 16);
- DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
- (dev->winSizeY +
- res_mode->lower_margin - 1));
- DISP_WR_REG (GC_WY_WX, 0x0);
- DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
- /* Display enable, L0 layer */
- DISP_WR_REG (GC_DCM1, 0x80010000 | div);
-
- return dev->frameAdrs;
-}
-#endif
-
-
-#if !defined(CONFIG_VIDEO_CORALP)
-int mb862xx_probe(unsigned int addr)
-{
- GraphicDevice *dev = &mb862xx;
- unsigned int reg;
-
- dev->frameAdrs = addr;
- dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
-
- /* Try to access GDC ID/Revision registers */
- reg = HOST_RD_REG (GC_CID);
- reg = HOST_RD_REG (GC_CID);
- if (reg == 0x303) {
- reg = DE_RD_REG(GC_REV);
- reg = DE_RD_REG(GC_REV);
- if ((reg & ~0xff) == 0x20050100)
- return MB862XX_TYPE_LIME;
- }
-
- return 0;
-}
-#endif
-
-void *video_hw_init (void)
-{
- GraphicDevice *dev = &mb862xx;
-
- puts ("Video: Fujitsu ");
-
- memset (dev, 0, sizeof (GraphicDevice));
-
-#if defined(CONFIG_VIDEO_CORALP)
- if (card_init () == 0)
- return NULL;
-#else
- /*
- * Preliminary init of the onboard graphic controller,
- * retrieve base address
- */
- if ((dev->frameAdrs = board_video_init ()) == 0) {
- puts ("Controller not found!\n");
- return NULL;
- } else {
- puts ("Lime\n");
-
- /* Set Change of Clock Frequency Register */
- HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
- /* Delay required */
- udelay(300);
- /* Set Memory I/F Mode Register) */
- HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
- }
-#endif
-
- de_init ();
-
-#if !defined(CONFIG_VIDEO_CORALP)
- board_disp_init ();
-#endif
-
-#if (defined(CONFIG_LWMON5) || \
- defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
- /* Lamp on */
- board_backlight_switch (1);
-#endif
-
- return dev;
-}
-
-/*
- * Set a RGB color in the LUT
- */
-void video_set_lut (unsigned int index, unsigned char r,
- unsigned char g, unsigned char b)
-{
- GraphicDevice *dev = &mb862xx;
-
- L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
-}
-
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
-/*
- * Drawing engine Fill and BitBlt screen region
- */
-void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
- unsigned int dst_y, unsigned int dim_x,
- unsigned int dim_y, unsigned int color)
-{
- GraphicDevice *dev = &mb862xx;
-
- de_wait_slots (3);
- DE_WR_REG (GC_FC, color);
- DE_WR_FIFO (0x09410000);
- DE_WR_FIFO ((dst_y << 16) | dst_x);
- DE_WR_FIFO ((dim_y << 16) | dim_x);
- de_wait ();
-}
-
-void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
- unsigned int src_y, unsigned int dst_x,
- unsigned int dst_y, unsigned int width,
- unsigned int height)
-{
- GraphicDevice *dev = &mb862xx;
- unsigned int ctrl = 0x0d000000L;
-
- if (src_x >= dst_x && src_y >= dst_y)
- ctrl |= 0x00440000L;
- else if (src_x >= dst_x && src_y <= dst_y)
- ctrl |= 0x00460000L;
- else if (src_x <= dst_x && src_y >= dst_y)
- ctrl |= 0x00450000L;
- else
- ctrl |= 0x00470000L;
-
- de_wait_slots (4);
- DE_WR_FIFO (ctrl);
- DE_WR_FIFO ((src_y << 16) | src_x);
- DE_WR_FIFO ((dst_y << 16) | dst_x);
- DE_WR_FIFO ((height << 16) | width);
- de_wait (); /* sync */
-}
-#endif
#include <part.h>
#include <linux/sizes.h>
#include <asm/arch/mem.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
.probe = meson_vpu_probe,
.bind = meson_vpu_bind,
.priv_auto = sizeof(struct meson_vpu_priv),
- .flags = DM_FLAG_PRE_RELOC | DM_FLAG_REMOVE_WITH_PD_ON,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_LEAVE_PD_ON,
};
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/mach-imx/dma.h>
#include <asm/io.h>
#include <malloc.h>
#include <linux/compat.h>
#include <linux/err.h>
-#include <video.h> /* For struct video_uc_platdata */
+#include <video.h> /* For struct video_uc_plat */
#include <video_fb.h>
#include <lcd.h>
#include <asm/global_data.h>
#include <regmap.h>
#include <syscon.h>
#include <video.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <regmap.h>
#include <video.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include "rk_vop.h"
#include <panel.h>
#include <regmap.h>
#include <syscon.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <log.h>
#include <panel.h>
#include <regmap.h>
+#include <asm/global_data.h>
#include "rk_mipi.h"
#include <syscon.h>
#include <asm/gpio.h>
#include <regmap.h>
#include <syscon.h>
#include <video.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <fdtdec.h>
#include <log.h>
#include <video.h>
+#include <asm/global_data.h>
#include <asm/sdl.h>
#include <asm/state.h>
#include <asm/u-boot-sandbox.h>
{ .compatible = "auo,b133htn01" },
{ .compatible = "boe,nv140fhmn49" },
{ .compatible = "lg,lb070wv8" },
+ { .compatible = "sharp,lq123p1jx31" },
+ { .compatible = "boe,nv101wxmn51" },
{ }
};
#include <fdt_support.h>
#include <log.h>
#include <video.h>
+#include <asm/global_data.h>
static int simple_video_probe(struct udevice *dev)
{
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
#include <asm/arch/gpio.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
struct sunxi_lcd_priv {
#include <pwm.h>
#include <video.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <log.h>
#include <panel.h>
#include <video.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/utils.h>
#include "tilcdc.h"
#include <video.h>
#include <video_console.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/lists.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <edid.h>
#include <env.h>
#include <errno.h>
+#include <fdtdec.h>
#include <linux/ctype.h>
#include "videomodes.h"
#include <common.h>
#include <dm.h>
#include <wdt.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
*/
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_wdt.h>
#include <common.h>
#include <common.h>
#include <dm.h>
#include <wdt.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <dm.h>
#include <errno.h>
#include <wdt.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitfield.h>
#include <clk.h>
#include <log.h>
#include <wdt.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <asm/io.h>
.ops = &rti_wdt_ops,
.probe = rti_wdt_probe,
.priv_auto = sizeof(struct rti_wdt_priv),
- .flags = DM_FLAG_REMOVE_WITH_PD_ON,
+ .flags = DM_FLAG_LEAVE_PD_ON,
};
* Copyright 2020 NXP
*/
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <dm/device.h>
*/
#include <log.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <clk.h>
#include <log.h>
#include <time.h>
#include <wdt.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
* [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary
*/
#include <common.h>
+#include <asm/global_data.h>
#include <linux/compiler.h>
#include <log.h>
#include <malloc.h>
#include <part.h>
#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/xen/system.h>
#include <common.h>
#include <env.h>
#include <env_internal.h>
+#include <asm/global_data.h>
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
DECLARE_GLOBAL_DATA_PTR;
#include <env_internal.h>
#include <log.h>
#include <sort.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
#include <search.h>
#include <errno.h>
#include <eeprom.h>
#include <env.h>
#include <env_internal.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
#include <u-boot/crc.h>
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
#include <env.h>
#include <env_internal.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/bug.h>
#include <errno.h>
#include <ext4fs.h>
#include <mmc.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <env_internal.h>
#include <flash.h>
#include <log.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <search.h>
/* #define DEBUG */
#include <common.h>
+#include <asm/global_data.h>
#include <command.h>
#include <env.h>
#include <command.h>
#include <env.h>
#include <env_internal.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <memalign.h>
#include <command.h>
#include <env.h>
#include <env_internal.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
DECLARE_GLOBAL_DATA_PTR;
#include <command.h>
#include <env.h>
#include <env_internal.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
#include <search.h>
#include <errno.h>
#include <common.h>
#include <command.h>
#include <env_internal.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <search.h>
#include <common.h>
#include <command.h>
#include <env_internal.h>
+#include <asm/global_data.h>
#include <linux/stddef.h>
#include <u-boot/crc.h>
#include <errno.h>
#include <uuid.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <u-boot/crc.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <command.h>
#include <env.h>
}
*last_slash_cont = '\0';
- *basename = last_slash_cont + 1;
+ filename = last_slash_cont + 1;
} else {
*dirname = "/"; /* root by default */
- *basename = filename;
}
+ /*
+ * The FAT32 File System Specification v1.03 requires leading and
+ * trailing spaces as well as trailing periods to be ignored.
+ */
+ for (; *filename == ' '; ++filename)
+ ;
+
+ /* Keep special entries '.' and '..' */
+ if (filename[0] == '.' &&
+ (!filename[1] || (filename[1] == '.' && !filename[2])))
+ goto done;
+
+ /* Remove trailing periods and spaces */
+ for (p = filename + strlen(filename) - 1; p >= filename; --p) {
+ switch (*p) {
+ case ' ':
+ case '.':
+ *p = 0;
+ break;
+ default:
+ goto done;
+ }
+ }
+
+done:
+ *basename = filename;
+
return 0;
}
static int normalize_longname(char *l_filename, const char *filename)
{
const char *p, illegal[] = "<>:\"/\\|?*";
+ size_t len;
- if (strlen(filename) >= VFAT_MAXLEN_BYTES)
+ len = strlen(filename);
+ if (!len || len >= VFAT_MAXLEN_BYTES || filename[len - 1] == '.')
return -1;
for (p = filename; *p; ++p) {
goto exit;
}
- filename = basename;
- if (normalize_longname(l_filename, filename)) {
- printf("FAT: illegal filename (%s)\n", filename);
+ if (normalize_longname(l_filename, basename)) {
+ printf("FAT: illegal filename (%s)\n", basename);
ret = -EINVAL;
goto exit;
}
char shortname[SHORT_NAME_SIZE];
int ndent;
- if (itr->is_root) {
- /* root dir cannot have "." or ".." */
- if (!strcmp(l_filename, ".") ||
- !strcmp(l_filename, "..")) {
- ret = -EINVAL;
- goto exit;
- }
- }
-
if (pos) {
/* No hole allowed */
ret = -EINVAL;
}
/* Check if long name is needed */
- ndent = set_name(itr, filename, shortname);
+ ndent = set_name(itr, basename, shortname);
if (ndent < 0) {
ret = ndent;
goto exit;
goto exit;
if (ndent > 1) {
/* Set long name entries */
- ret = fill_dir_slot(itr, filename, shortname);
+ ret = fill_dir_slot(itr, basename, shortname);
if (ret)
goto exit;
}
return ret;
}
-int fat_mkdir(const char *new_dirname)
+int fat_mkdir(const char *dirname)
{
dir_entry *retdent;
fsdata datablock = { .fatbuf = NULL, };
fsdata *mydata = &datablock;
fat_itr *itr = NULL;
- char *dirname_copy, *parent, *dirname;
+ char *dirname_copy, *parent, *basename;
char l_dirname[VFAT_MAXLEN_BYTES];
int ret = -1;
loff_t actwrite;
unsigned int bytesperclust;
dir_entry *dotdent = NULL;
- dirname_copy = strdup(new_dirname);
+ dirname_copy = strdup(dirname);
if (!dirname_copy)
goto exit;
- split_filename(dirname_copy, &parent, &dirname);
- if (!strlen(dirname)) {
+ split_filename(dirname_copy, &parent, &basename);
+ if (!strlen(basename)) {
ret = -EINVAL;
goto exit;
}
- if (normalize_longname(l_dirname, dirname)) {
- printf("FAT: illegal filename (%s)\n", dirname);
+ if (normalize_longname(l_dirname, basename)) {
+ printf("FAT: illegal filename (%s)\n", basename);
ret = -EINVAL;
goto exit;
}
}
/* Check if long name is needed */
- ndent = set_name(itr, dirname, shortname);
+ ndent = set_name(itr, basename, shortname);
if (ndent < 0) {
ret = ndent;
goto exit;
goto exit;
if (ndent > 1) {
/* Set long name entries */
- ret = fill_dir_slot(itr, dirname, shortname);
+ ret = fill_dir_slot(itr, basename, shortname);
if (ret)
goto exit;
}
#include <sandboxfs.h>
#include <ubifs_uboot.h>
#include <btrfs.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <div64.h>
#include <linux/math64.h>
* from the original reiser fs code, as found in the linux kernel.
*/
+#include <compiler.h>
+
#ifndef __BYTE_ORDER
#if defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
#define __BYTE_ORDER __LITTLE_ENDIAN
#include <log.h>
#include <malloc.h>
#include <memalign.h>
+#include <asm/global_data.h>
#include "ubifs.h"
#include <part.h>
#include <dm/devres.h>
EXPORT_FUNC(simple_strtol, long, simple_strtol,
const char *, char **, unsigned int)
EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct)
-#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
+#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int)
EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int)
#else
/**
* @ram_top: top address of RAM used by U-Boot
*/
- unsigned long ram_top;
+ phys_addr_t ram_top;
/**
* @relocaddr: start address of U-Boot in RAM
*
*/
struct acpi_ctx *acpi_ctx;
#endif
+#if CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)
+ /**
+ * @smbios_version: Points to SMBIOS type 0 version
+ */
+ char *smbios_version;
+#endif
};
/**
#ifndef __AUDIO_CODEC_H__
#define __AUDIO_CODEC_H__
+struct udevice;
+
/*
* An audio codec turns digital data into sound with various parameters to
* control its operation.
#ifndef _AXI_H_
#define _AXI_H_
+struct udevice;
+
/**
* enum axi_size_t - Determine size of AXI transfer
* @AXI_SIZE_8: AXI sransfer is 8-bit wide
#ifndef _BACKLIGHT_H
#define _BACKLIGHT_H
+struct udevice;
+
enum {
BACKLIGHT_MAX = 100,
BACKLIGHT_MIN = 0,
#define _BOOTCOUNT_H__
#include <common.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <env.h>
#ifndef __BUTTON_H
#define __BUTTON_H
+struct udevice;
+
/**
* struct button_uc_plat - Platform data the uclass stores about each device
*
#ifndef __CACHE_H
#define __CACHE_H
+struct udevice;
+
/*
* Structure for the cache controller
*/
};
#if defined(CONFIG_CMD_RUN)
-extern int do_run(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
+int do_run(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
#endif
/* common/command.c */
char *const argv[], char last_char, int maxv,
char *cmdv[]);
-extern int cmd_usage(const struct cmd_tbl *cmdtp);
+int cmd_usage(const struct cmd_tbl *cmdtp);
/* Dummy ->cmd and ->cmd_rep wrappers. */
int cmd_always_repeatable(struct cmd_tbl *cmdtp, int flag, int argc,
}
#ifdef CONFIG_AUTO_COMPLETE
-extern int var_complete(int argc, char *const argv[], char last_char, int maxv,
- char *cmdv[]);
-extern int cmd_auto_complete(const char *const prompt, char *buf, int *np,
- int *colp);
+int var_complete(int argc, char *const argv[], char last_char, int maxv,
+ char *cmdv[]);
+int cmd_auto_complete(const char *const prompt, char *buf, int *np,
+ int *colp);
#endif
/**
#endif
#ifdef CONFIG_CMD_BOOTD
-extern int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
+int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
#endif
#ifdef CONFIG_CMD_BOOTM
-extern int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
-extern int bootm_maybe_autostart(struct cmd_tbl *cmdtp, const char *cmd);
+int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
+int bootm_maybe_autostart(struct cmd_tbl *cmdtp, const char *cmd);
#else
static inline int bootm_maybe_autostart(struct cmd_tbl *cmdtp, const char *cmd)
{
}
#endif
-extern int do_bootz(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
+int do_bootz(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
-extern int do_booti(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
+int do_booti(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
-extern int common_diskboot(struct cmd_tbl *cmdtp, const char *intf, int argc,
- char *const argv[]);
+int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[], int *repeatable);
-extern int do_reset(struct cmd_tbl *cmdtp, int flag, int argc,
+int common_diskboot(struct cmd_tbl *cmdtp, const char *intf, int argc,
char *const argv[]);
-extern int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
-extern unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
- char *const argv[]);
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
+int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+ char *const argv[]);
#if defined(CONFIG_CMD_NVEDIT_EFI)
-extern int do_env_print_efi(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
-extern int do_env_set_efi(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[]);
+int do_env_print_efi(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
+int do_env_set_efi(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
#endif
/**
#include <stdio.h>
#include <linux/kernel.h>
#include <asm/u-boot.h> /* boot information for Linux kernel */
-#include <asm/global_data.h> /* global data used for startup functions */
#include <display_options.h>
#include <vsprintf.h>
#endif /* __ASSEMBLY__ */
#define CONFIG_SYS_MAXARGS 16
#endif
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
# ifdef CONFIG_SYS_I2C
# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
# endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8544ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PCI1 1 /* PCI controller 1 */
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- *
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- *
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- *
- * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable
- *
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
- * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
- *
- * Localbus non-cacheable
- *
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
- *
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
-
-#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
-
-#define CONFIG_SYS_BR0_PRELIM 0xff801001
-#define CONFIG_SYS_BR1_PRELIM 0xfe801001
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806e65
-#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
-
-#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
-
-#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
- * register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
-#define PIXIS_VSPEED2_TSEC1SER 0x2
-#define PIXIS_VSPEED2_TSEC3SER 0x1
-#define PIXIS_VCFGEN1_TSEC1SER 0x20
-#define PIXIS_VCFGEN1_TSEC3SER 0x40
-#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
-#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
-#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
-#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
-#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME "ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* CONFIG_SCSI_AHCI */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1c
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE 0
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_IPADDR 192.168.1.251
-
-#define CONFIG_HOSTNAME "8544ds_unknown"
-#define CONFIG_ROOTPATH "/nfs/mpc85xx"
-#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
-#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.0.0
-
-#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=8544ds/ramdisk.uboot\0" \
-"fdtaddr=1e00000\0" \
-"fdtfile=8544ds/mpc8544ds.dtb\0" \
-"bdev=sda3\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#endif /* __CONFIG_H */
/*
* I2C
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8572ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
-#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
-#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
-#define CONFIG_SYS_DDR_MODE_1 0x00440462
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x24400000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/*
- * Make sure required options are set
- */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_PWR 0x5 /* PIXIS Power status register */
-#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VSTAT 0x11 /* VELA Status Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
-#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
-#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
-#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
-#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
-#define PIXIS_VWATCH 0x24 /* Watchdog Register */
-#define PIXIS_LED 0x25 /* LED Register */
-
-#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
-#define PIXIS_VSPEED2_TSEC1SER 0x8
-#define PIXIS_VSPEED2_TSEC2SER 0x4
-#define PIXIS_VSPEED2_TSEC3SER 0x2
-#define PIXIS_VSPEED2_TSEC4SER 0x1
-#define PIXIS_VCFGEN1_TSEC1SER 0x20
-#define PIXIS_VCFGEN1_TSEC2SER 0x20
-#define PIXIS_VCFGEN1_TSEC3SER 0x20
-#define PIXIS_VCFGEN1_TSEC4SER 0x20
-#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
- | PIXIS_VSPEED2_TSEC2SER \
- | PIXIS_VSPEED2_TSEC3SER \
- | PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
- | PIXIS_VCFGEN1_TSEC2SER \
- | PIXIS_VCFGEN1_TSEC3SER \
- | PIXIS_VCFGEN1_TSEC4SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
- CONFIG_SYS_NAND_BASE + 0x40000, \
- CONFIG_SYS_NAND_BASE + 0x80000,\
- CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_MAX_OOBFREE 5
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
- (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_NAME "ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
- #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* SCSI */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "eTSEC4"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1c
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
-#endif
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE 0
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR 192.168.1.254
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=8572ds/ramdisk.uboot\0" \
-"fdtaddr=1e00000\0" \
-"fdtfile=8572ds/mpc8572ds.dtb\0" \
-"bdev=sda3\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * MPC8610HPCD board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-
-/* video */
-#define CONFIG_FSL_DIU_FB
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR 0xff800000
-#endif
-
-/*
- * virtual address to be used for temporary mappings. There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA 0xc0000000
-
-#define CONFIG_PCI1 1 /* PCI controller 1 */
-#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
-#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_ALTIVEC 1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT 0
-#define L2_ENABLE (L2CR_L2E |0x00100000 )
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-
-#if 0 /* TODO */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x000f0000
-
-#endif
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
-#define CONFIG_SYS_FLASH_BASE2 0xf8000000
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-
-#define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
-
-#define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
-#if 0 /* TODO */
-#define CONFIG_SYS_BR2_PRELIM 0xf0000000
-#define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
-#endif
-#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE 256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-/* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_NAME "ULI"
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
-
-/* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#define CONFIG_ULI526X
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI 1
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-
-#if !defined(CONFIG_PCI_PNP)
-#define PCI_ENET0_IOADDR 0xe0000000
-#define PCI_ENET0_MEMADDR 0xe0000000
-#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif /* CONFIG_PCI */
-
-/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
- */
-#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
-
-/*
- * BAT1 1G Cache-inhibited, guarded
- * 0x8000_0000 256M PCI-1 Memory
- * 0xa000_0000 256M PCI-Express 1 Memory
- * 0x9000_0000 256M PCI-Express 2 Memory
- */
-
-#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-
-/*
- * BAT2 16M Cache-inhibited, guarded
- * 0xe100_0000 1M PCI-1 I/O
- */
-
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-
-/*
- * BAT3 4M Cache-inhibited, guarded
- * 0xe000_0000 4M CCSR
- */
-
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 1M PCI-Express 2 I/O
- * 0xe300_0000 1M PCI-Express 1 I/O
- */
-
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
-/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
-
-/*
- * BAT6 256M Cache-inhibited, guarded
- * 0xf000_0000 256M FLASH
- */
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7 4M Cache-inhibited, guarded
- * 0xe800_0000 4M PIXIS
- */
-#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_WATCHDOG /* watchdog enabled */
-#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_IPADDR 192.168.1.100
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x10000000
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
- "pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; run pcierr\0" \
- "pci1errc=setenv a e0008; run pcierrc\0"
-#else
-#define PCI_ENV ""
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
- "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
- "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
- "pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
- "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1err=setenv a e000a; run pcieerr\0" \
- "pcie2err=setenv a e0009; run pcieerr\0" \
- "pcie1errc=setenv a e000a; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; run pcieerrc\0"
-#else
-#define PCIE_ENV ""
-#endif
-
-#define DMA_ENV \
- "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
- "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
- "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
- "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
- "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
- "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
- "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
- "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
-
-#ifdef ENV_DEBUG
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=0x18000000\0" \
-"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
-"fdtaddr=0x17c00000\0" \
-"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
-"bdev=sda3\0" \
-"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
-"maxcpus=1" \
-"eoi=mw e00400b0 0\0" \
-"iack=md e00400a0 1\0" \
-"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
- "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
- "md ${a}f00 5\0" \
-"ddr1regs=setenv a e0002; run ddrreg\0" \
-"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
- "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
- "md ${a}e60 1; md ${a}ef0 1d\0" \
-"guregs=setenv a e00e0; run gureg\0" \
-"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
-"mcmregs=setenv a e0001; run mcmreg\0" \
-"diuregs=md e002c000 1d\0" \
-"dium=mw e002c01c\0" \
-"diuerr=md e002c014 1\0" \
-"pmregs=md e00e1000 2b\0" \
-"lawregs=md e0000c08 4b\0" \
-"lbcregs=md e0005000 36\0" \
-"dma0regs=md e0021100 12\0" \
-"dma1regs=md e0021180 12\0" \
-"dma2regs=md e0021200 12\0" \
-"dma3regs=md e0021280 12\0" \
- PCI_ENV \
- PCIE_ENV \
- DMA_ENV
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=0x18000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=0x17c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0"
-#endif
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2006, 2010-2011 Freescale Semiconductor.
- *
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- */
-
-/*
- * MPC8641HPCN board configuration file
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc. in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-
-/*
- * default CCSRBAR is at 0xff700000
- * assume U-Boot is less than 0.5MB
- */
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
-#endif
-
-/*
- * virtual address to be used for temporary mappings. There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA 0xe0000000
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-
-#define CONFIG_ALTIVEC 1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT 0
-#define L2_ENABLE (L2CR_L2E)
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-#endif
-
-/*
- * With the exception of PCI Memory and Rapid IO, most devices will simply
- * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
- * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
-#else
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-
-/* Physical addresses */
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH)
-
-#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/*
- * I2C addresses of SPD EEPROMs
- */
-#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
-#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
-#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
-
-/*
- * These are used when DDR doesn't use SPD.
- */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x39357322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06090100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400000
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
-#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
-
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
- | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
-
-/*
- * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
- * The PIXIS and CF by themselves aren't large enough to take up the 128k
- * required for the smallest BAT mapping, so there's a 64k hole.
- */
-#define CONFIG_SYS_LBC_BASE 0xffde0000
-#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
-
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
-#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
-#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH)
-#define PIXIS_SIZE 0x00008000 /* 32k */
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
-
-/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
-#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
-#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE 256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * RapidIO MMU
- */
-#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
- CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-
-#define CONFIG_SYS_PCIE1_NAME "ULI"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
- CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
-#define CONFIG_SYS_PCIE1_IO_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
-
-#ifdef CONFIG_PHYS_64BIT
-/*
- * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
- * This will increase the amount of PCI address space available for
- * for mapping RAM.
- */
-#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#endif
-#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
-#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
- + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
- + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
- + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI 1
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "eTSEC4"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_PHYS_64BIT
-#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
-#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
-
-/* Put physical address into the BAT format */
-#define BAT_PHYS_ADDR(low, high) \
- (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
-/* Convert high/low pairs to actual 64-bit value */
-#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
-#else
-/* 32-bit systems just ignore the "high" bits */
-#define BAT_PHYS_ADDR(low, high) (low)
-#define PAIRED_PHYS_TO_PHYS(low, high) (low)
-#endif
-
-/*
- * BAT0 DDR
- */
-#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-
-/*
- * BAT1 LBC (PIXIS/CF)
- */
-#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-
-/* if CONFIG_PCI:
- * BAT2 PCIE1 and PCIE1 MEM
- * if CONFIG_RIO
- * BAT2 Rapidio Memory
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
- CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
- CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
- CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
- CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#endif
-
-/*
- * BAT3 CCSR Space
- */
-#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4 PCIE1_IO and PCIE2_IO
- */
-#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
-/*
- * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
-
-/*
- * BAT6 FLASH
- */
-#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7 FREE - used later for tmp mappings
- */
-#define CONFIG_SYS_DBAT7L 0x00000000
-#define CONFIG_SYS_DBAT7U 0x00000000
-#define CONFIG_SYS_IBAT7L 0x00000000
-#define CONFIG_SYS_IBAT7U 0x00000000
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HAS_ETH0 1
-#define CONFIG_HAS_ETH1 1
-#define CONFIG_HAS_ETH2 1
-#define CONFIG_HAS_ETH3 1
-
-#define CONFIG_IPADDR 192.168.1.100
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x10000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=0x18000000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=0x17c00000\0" \
- "fdtfile=mpc8641_hpcn.dtb\0" \
- "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
- "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
- "maxcpus=2"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Solutions Migo-R board
- *
- * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __MIGO_R_H
-#define __MIGO_R_H
-
-#define CONFIG_CPU_SH7722 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* SMC9111 */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (0xB0000000)
-
-/* MEMORY */
-#define MIGO_R_SDRAM_BASE (0x8C000000)
-#define MIGO_R_FLASH_BASE_1 (0xA0000000)
-#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-/* Enable alternate, more extensive, memory test */
-/* Scratch address used by the alternate memory test */
-
-/* Enable temporary baudrate change while serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
-/* maybe more, but if so u-boot doesn't know about it... */
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-/* default load address for scripts ?!? */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
-
-/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
-#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
-/* Monitor size */
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-/* Physical start address of Flash memory */
-#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
-/* Max number of sectors on each Flash chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
-
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
-
-/* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/* ENV setting */
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#endif /* __MIGO_R_H */
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#endif
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SPL_SKIP_RELOCATE
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#undef CONFIG_DM_I2C
#endif
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#endif
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
/*
* I2C
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
/*
* I2C
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* Power */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Bluegiga Technologies Oy
- *
- * Authors:
- * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
- * Lauri Hintsala <lauri.hintsala@bluegiga.com>
- *
- * Based on m28evk.h:
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-#ifndef __CONFIGS_APX4DEVKIT_H__
-#define __CONFIGS_APX4DEVKIT_H__
-
-/* System configurations */
-#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
-
-/* Memory configuration */
-#define PHYS_SDRAM_1 0x40000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-/* Environment is in NAND */
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_RANGE (384 * 1024)
-#endif
-
-/* UBI and NAND partitioning */
-
-/* FEC Ethernet on SoC */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define IMX_FEC_BASE MXS_ENET0_BASE
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_MXS_PORT1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
-/* Boot Linux */
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
-#define CONFIG_LOADADDR 0x41000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-
-/* Extra Environments */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "verify=no\0" \
- "bootcmd=run bootcmd_nand\0" \
- "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
- "bootargs_nand=" \
- "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
- "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
- "bootcmd_nand=" \
- "run bootargs_nand && ubi part root 2048 && " \
- "ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \
- "bootm 41000000\0" \
- "bootargs_mmc=" \
- "setenv bootargs ${kernelargs} " \
- "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
- "bootcmd_mmc=" \
- "run bootargs_mmc && mmc rescan && " \
- "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
-""
-
-/* The rest of the configuration is shared */
-#include <configs/mxs.h>
-
-#endif /* __CONFIGS_APX4DEVKIT_H__ */
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef _CONFIG_DB_88F6281_BP_H
-#define _CONFIG_DB_88F6281_BP_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_SYS_TCLK 166666667
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-
-/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_GPIO 1
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-
-/*
- * U-Boot bootcode configuration
- */
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
-
-/* size in bytes reserved for initial data */
-
-#include <asm/arch/config.h>
-/* There is no PHY directly connected so don't ask it for link status */
-#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
-/*
- * SDIO/MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MVEBU_MMC
-#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
-#endif /* CONFIG_CMD_MMC */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-
-#endif /* _CONFIG_DB_88F6281_BP_H */
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PCA9450
-#undef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#endif
#include <linux/delay.h>
#include <linux/stringify.h>
extern void __set_direction(unsigned pin, int high);
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
#define KM_KIRKWOOD_SDA_PIN 8
#define KM_KIRKWOOD_SCL_PIN 9
#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ */
+
+#ifndef __KMCENT2_H
+#define __KMCENT2_H
+
+#define CONFIG_HOSTNAME "kmcent2"
+#define KM_BOARD_NAME CONFIG_HOSTNAME
+
+/*
+ * The Linux fsl_fman driver needs to be able to process frames with more
+ * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
+ * parameters
+ */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558"
+
+#include "km/keymile-common.h"
+
+/* Application IFC chip selects */
+#define SYS_LAWAPP_BASE 0xc0000000
+#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
+
+/* Application IFC CS4 MRAM */
+#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
+#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
+#define SYS_MRAM_CSPR_EXT (0x0f)
+#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+ CSPR_PORT_SIZE_8 | /* 8 bit */ \
+ CSPR_MSEL_GPCM | /* msel = gpcm */ \
+ CSPR_V /* bank is valid */)
+#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
+#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40
+/* MRAM Timing parameters for IFC CS4 */
+#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0xe))
+#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \
+ FTIM2_GPCM_TCH(0x2) | \
+ FTIM2_GPCM_TWP(0x8))
+#define SYS_MRAM_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
+#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
+#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
+#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
+#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
+#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
+#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
+#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
+
+/* Application IFC CS6: BFTIC */
+#define SYS_BFTIC_BASE 0xd0000000
+#define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE)
+#define SYS_BFTIC_CSPR_EXT (0x0f)
+#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40
+/* BFTIC Timing parameters for IFC CS6 */
+#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_BFTIC_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
+#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
+#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
+#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
+#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
+#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
+#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
+#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
+
+/* Application IFC CS7 PAXE */
+#define CONFIG_SYS_PAXE_BASE 0xd8000000
+#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define SYS_PAXE_CSPR_EXT (0x0f)
+#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40
+/* PAXE Timing parameters for IFC CS7 */
+#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_PAXE_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
+#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
+#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
+#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
+#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
+#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
+#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
+#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
+
+/* PRST */
+#define KM_BFTIC4_RST 0
+#define KM_DPAXE_RST 1
+#define KM_FEMT_RST 3
+#define KM_FOAM_RST 4
+#define KM_EFE_RST 5
+#define KM_ES_PHY_RST 6
+#define KM_XES_PHY_RST 7
+#define KM_ZL30158_RST 8
+#define KM_ZL30364_RST 9
+#define KM_BOBCAT_RST 10
+#define KM_ETHSW_DDR_RST 12
+#define KM_CFE_RST 13
+#define KM_PEXSW_RST 14
+#define KM_PEXSW_NT_RST 15
+
+/* QRIO GPIOs used for deblocking */
+#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
+#define KM_I2C_DEBLOCK_SCL 20
+#define KM_I2C_DEBLOCK_SDA 21
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+
+#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+/* Environment in parallel NOR-Flash */
+#define CONFIG_ENV_TOTAL_SIZE 0x040000
+#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+/* POST memory regions test */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE 256 << 10
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE 0x0
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM
+ */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR flash on IFC CS0 */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
+ CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_NOR | /* MSEL = NOR */\
+ CSPR_V) /* valid */
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
+ CSOR_NOR_TRHZ_20 | \
+ CSOR_NOR_BCTLD)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x7) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x21) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x21))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \
+ FTIM2_NOR_TCS(0x1) | \
+ FTIM2_NOR_TWP(0xb) | \
+ FTIM2_NOR_TWPH(0x6))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+/* More NOR Flash params */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC CS1*/
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xfa000000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_NAND | /* MSEL = NAND */\
+ CSPR_V) /* valid */
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+ CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \
+ CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \
+ CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \
+ CSOR_NAND_PGS_2K | /* Page size = 2K */ \
+ CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \
+ CSOR_NAND_PB(64) | /* 64 Pages/Block */ \
+ CSOR_NAND_TRHZ_40 | /**/ \
+ CSOR_NAND_BCTLD) /**/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+ FTIM0_NAND_TWP(0x8) | \
+ FTIM0_NAND_TWCHT(0x3) | \
+ FTIM0_NAND_TWH(0x5))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+ FTIM1_NAND_TWBE(0x1e) | \
+ FTIM1_NAND_TRR(0x6) | \
+ FTIM1_NAND_TRP(0x8))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+ FTIM2_NAND_TREH(0x5) | \
+ FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* More NAND Flash Params */
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* QRIO on IFC CS2 */
+#define CONFIG_SYS_QRIO_BASE 0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define SYS_QRIO_CSPR_EXT (0x0f)
+#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\
+ CSOR_GPCM_BCTLD)
+/* QRIO Timing parameters for IFC CS2 */
+#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x6))
+#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x7))
+#define SYS_QRIO_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
+#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
+#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
+#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
+#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
+
+#define CONFIG_MISC_INIT_F
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
+
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/*
+ * Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ * Retain non-DM serial port for debug purposes.
+ */
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#endif
+
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000
+#define CONFIG_SYS_QE_FW_ADDR 0xE8040000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+/* Qman / Bman */
+/* RGMII (FM1@DTESC5) is local managemant interface */
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
+#define CONFIG_ETHPRIME "fm1-mac5"
+
+/*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */
+#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV
+#endif
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_KM_DEF_ENV_CPU \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize}\0" \
+ "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
+ "set_fdthigh=true\0" \
+ "checkfdt=true\0" \
+ "fpgacfg=true\0" \
+ ""
+
+#define CONFIG_HW_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
+ "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+ "usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV \
+ "newenv=protect off " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "erase " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "protect on " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ARCH \
+ CONFIG_KM_NEW_ENV \
+ CONFIG_HW_ENV_SETTINGS \
+ "EEprom_ivm=pca9547:70:9\0" \
+ ""
+
+#endif /* __KMCENT2_H */
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
}
-#ifndef __ASSEMBLY__
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
-#endif
#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
func(MMC, mmc, 1) \
func(NVME, nvme, 0) \
func(USB, usb, 0) \
+ func(SCSI, scsi, 0) \
func(DHCP, dhcp, 0) \
func(PXE, pxe, 0)
#include <config_distro_bootcmd.h>
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SETUP_INITRD_TAG
#define CONFIG_BOOTCOMMAND \
CONFIG_SYS_SCSI_MAX_LUN)
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
* I2C
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
/*
* I2C
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
/*
* I2C
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#undef CONFIG_DM_I2C
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#endif
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* IFC */
#ifndef SPL_NO_IFC
#if defined(CONFIG_TFABOOT) || \
#endif
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define SPL_NO_QSPI
#define SPL_NO_USB
#define SPL_NO_SATA
-#undef CONFIG_DM_I2C
#endif
#if defined(CONFIG_SPL_BUILD) && \
(defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
#define CONFIG_SYS_MONITOR_LEN 0xa0000
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#endif
#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+#define COMMON_ENV \
+ "kernelheader_addr_r=0x80200000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0"
+
/* Initial environment variables */
#ifdef CONFIG_NXP_ESBC
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
#if defined(CONFIG_QSPI_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
#elif defined(CONFIG_SD_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x800\0" \
#else /* NOR BOOT */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor
- */
-
-#ifndef __LS2_EMU_H
-#define __LS2_EMU_H
-
-#include "ls2080a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
- FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
- FTIM2_NOR_TCH(0x0) | \
- FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
-
-/*
- * This trick allows users to load MC images into DDR directly without
- * copying from NOR flash. It dramatically improves speed.
- */
-#define CONFIG_SYS_LS_MC_FW_IN_DDR
-#define CONFIG_SYS_LS_MC_DPL_IN_DDR
-#define CONFIG_SYS_LS_MC_DPC_IN_DDR
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-
-#endif /* __LS2_EMU_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- */
-
-#ifndef __LS2_SIMU_H
-#define __LS2_SIMU_H
-
-#include "ls2080a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-#endif
-
-/* SMSC 91C111 ethernet configuration */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (0x2210000)
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
- FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
- FTIM2_NOR_TCH(0x0) | \
- FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#endif
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
-
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-
-#endif /* __LS2_SIMU_H */
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_QIXIS_I2C_ACCESS
#endif
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#endif
#define NXP_FSPI_FLASH_NUM 1
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/*
+ * Environment
+ */
+#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */
+
+/*
* Ethernet Driver configuration
*/
#define CONFIG_ARP_TIMEOUT 200
#include <config_distro_bootcmd.h>
+/* filler for default values filled by board_early_init_f() */
+#define ENV_RW_FILLER \
+ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for ethaddr= */ \
+ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth1addr= */ \
+ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth2addr= */ \
+ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth3addr= */ \
+ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for fdtfile= */ \
+ ""
+
/* fdt_addr and kernel_addr are needed for existing distribution boot scripts */
#define CONFIG_EXTRA_ENV_SETTINGS \
"scriptaddr=0x6d00000\0" \
"kernel_addr=0x7000000\0" \
"kernel_addr_r=0x7000000\0" \
"ramdisk_addr_r=0xa000000\0" \
- BOOTENV
+ BOOTENV \
+ ENV_RW_FILLER
#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Configuration for the MX35pdk Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX35
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Set TEXT at the beginning of the NOR flash */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/*
- * PMIC Configs
- */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
-#define CONFIG_RTC_MC13XXX
-
-/*
- * MFD MC9SDZ60
- */
-#define CONFIG_FSL_MC9SDZ60
-#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
-
-/*
- * UART (console)
- */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/*
- * Command definition
- */
-
-#define CONFIG_NET_RETRY_COUNT 100
-
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-/*
- * Ethernet on the debug board (SMC911)
- */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHPRIME
-
-/*
- * Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-
-/*
- * CFI FLASH driver setup
- */
-
-/* A non-standard buffered write algorithm */
-#define CONFIG_FLASH_SPANSION_S29WS_N
-
-/*
- * NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/* EHCI driver */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_MXC_USB_PORT 0
-#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
- MXC_EHCI_POWER_PINS_ENABLED | \
- MXC_EHCI_OC_PIN_ACTIVE_LOW)
-#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
-
-/* mmc driver */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "mx35pdk"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth1\0" \
- "ethprime=smc911x\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=80800000\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +80000;" \
- "erase ${uboot_addr} +80000;" \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "bootcmd=run net_nfs\0"
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PCA9450
-#undef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas R7780MP board
- *
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- */
-
-#ifndef __R7780RP_H
-#define __R7780RP_H
-
-#define CONFIG_CPU_SH7780 1
-#define CONFIG_R7780MP 1
-#define CONFIG_SYS_R7780MP_OLD_FLASH 1
-#define __LITTLE_ENDIAN__ 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_SDRAM_BASE (0x08000000)
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-
-/* Flash board support */
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
-/* NOR Flash (S29PL127J60TFI130) */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS (2)
-# define CONFIG_SYS_MAX_FLASH_SECT 270
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x100000,\
- CONFIG_SYS_FLASH_BASE + 0x400000,\
- CONFIG_SYS_FLASH_BASE + 0x700000, }
-#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
-/* NOR Flash (Spantion S29GL256P) */
-# define CONFIG_SYS_MAX_FLASH_BANKS (1)
-# define CONFIG_SYS_MAX_FLASH_SECT 256
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
-/* Address of u-boot image in Flash */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
-
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-#define CONFIG_SYS_RX_ETH_BUFFER (8)
-
-#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* PCI Controller */
-#if defined(CONFIG_CMD_PCI)
-#define CONFIG_SH4_PCI
-#define CONFIG_SH7780_PCI
-#define CONFIG_SH7780_PCI_LSR 0x07f00001
-#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_PCI_SCAN_SHOW 1
-#define __mem_pci
-
-#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
-
-#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
-#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
-#endif /* CONFIG_CMD_PCI */
-
-#if defined(CONFIG_CMD_NET)
-/* AX88796L Support(NE2000 base chip) */
-#define CONFIG_DRIVER_AX88796L
-#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
-#endif
-
-/* Compact flash Support */
-#if defined(CONFIG_IDE)
-#define CONFIG_IDE_RESET 1
-#define CONFIG_SYS_PIO_MODE 1
-#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
-#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
-#endif /* CONFIG_IDE */
-
-#endif /* __R7780RP_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7752evb board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __SH7752EVB_H
-#define __SH7752EVB_H
-
-#define CONFIG_CPU_SH7752 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7752EVB_SDRAM_BASE (0x40000000)
-#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
- 128 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT 0
-#define CONFIG_SH_ETHER_PHY_ADDR 18
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
-#define CONFIG_SH_ETHER_USE_GETHER 1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-
-#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
-#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)
-#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI
-#define SH7752EVB_ETHERNET_MAC_SIZE 17
-#define SH7752EVB_ETHERNET_NUM_CH 2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE 0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif /* __SH7752EVB_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7753evb board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __SH7753EVB_H
-#define __SH7753EVB_H
-
-#define CONFIG_CPU_SH7753 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7753EVB_SDRAM_BASE (0x40000000)
-#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
- 128 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT 0
-#define CONFIG_SH_ETHER_PHY_ADDR 18
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
-#define CONFIG_SH_ETHER_USE_GETHER 1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-
-#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
-#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
-#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
-#define SH7753EVB_ETHERNET_MAC_SIZE 17
-#define SH7753EVB_ETHERNET_NUM_CH 2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE 0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif /* __SH7753EVB_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7757lcr board
- *
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#ifndef __SH7757LCR_H
-#define __SH7757LCR_H
-
-#define CONFIG_CPU_SH7757 1
-#define CONFIG_SH7757LCR_DDR_ECC 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7757LCR_SDRAM_BASE (0x80000000)
-#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
-#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
-#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
- (128 + 16) * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT 0
-#define CONFIG_SH_ETHER_PHY_ADDR 1
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
-#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
-#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
-#define SH7757LCR_ETHERNET_MAC_SIZE 17
-#define SH7757LCR_ETHERNET_NUM_CH 2
-
-/* Gigabit Ether */
-#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE 0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* SH7757 board */
-#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
-#define SH7757LCR_GRA_OFFSET 0x1f000000
-#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
-#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
-#define SH7757LCR_PCIEBRG_ADDR 0x00090000
-#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif /* __SH7757LCR_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas SH7763RDP board
- *
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- */
-
-#ifndef __SH7763RDP_H
-#define __SH7763RDP_H
-
-#define CONFIG_CPU_SH7763 1
-#define __LITTLE_ENDIAN 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
- settings for this board */
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-/* Flash(NOR) */
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
-#define CONFIG_SYS_MAX_FLASH_BANKS (1)
-#define CONFIG_SYS_MAX_FLASH_SECT (520)
-
-/* U-Boot setting */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
-/* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-
-/* Clock */
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT (1)
-#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#endif /* __SH7763RDP_H */
"run distro_bootcmd;" \
"fi;\0"
+#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT
+/* eMMC default partitions for fastboot command: oem format */
+#define PARTS_DEFAULT \
+ "partitions=" \
+ "name=ssbl,size=2M;" \
+ "name=bootfs,size=64MB,bootable;" \
+ "name=vendorfs,size=16M;" \
+ "name=rootfs,size=746M;" \
+ "name=userfs,size=-\0"
+#else
+#define PARTS_DEFAULT
+#endif
+
#include <config_distro_bootcmd.h>
/*
"altbootcmd=run bootcmd\0" \
"env_check=if env info -p -d -q; then env save; fi\0" \
STM32MP_BOOTCMD \
+ PARTS_DEFAULT \
BOOTENV \
"boot_net_usb_start=true\0"
#define CONFIG_BOARD_SIZE_LIMIT 0x7e000
#endif
-#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
-/* If we have two devices (most likely eMMC + MMC), favour the eMMC */
-#else
-/* Otherwise, use the only device we have */
-#endif
#define CONFIG_SYS_MMC_MAX_DEVICE 4
#endif
/* I2C */
-#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
- defined CONFIG_SY8106A_POWER
-#endif
-
#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
#define CONFIG_SYS_I2C_MVTWSI
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x7f
#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
#endif
-/* PMU */
-#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
- defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \
- defined CONFIG_SY8106A_POWER
-#endif
-
-#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
-#if CONFIG_CONS_INDEX == 1
-#ifdef CONFIG_MACH_SUN9I
-#define OF_STDOUT_PATH "/soc/serial@07000000:115200"
-#else
-#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200"
-#endif
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
-#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
-#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
-#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
-#define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200"
-#else
-#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
-#endif
-#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */
-
#ifdef CONFIG_VIDEO_SUNXI
/*
* The amount of RAM to keep free at the top of RAM when relocating u-boot,
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* If DM_I2C, enable non-DM I2C support */
-#if !defined(CONFIG_DM_I2C)
+#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_I2C
#define CONFIG_SYS_I2C
#endif
#ifndef __CPU_H
#define __CPU_H
+struct udevice;
+
/**
* struct cpu_plat - platform data for a CPU
* @cpu_id: Platform-specific way of identifying the CPU.
#if !defined(__ACPI__)
struct nhlt;
+struct udevice;
/** enum acpi_dump_option - selects what ACPI information to dump */
enum acpi_dump_option {
*
* @dev: Pointer to device to remove
* @flags: Flags for selective device removal (DM_REMOVE_...)
- * @return 0 if OK, -ve on error (an error here is normally a very bad thing)
+ * @return 0 if OK, -EKEYREJECTED if not removed due to flags, -EPROBE_DEFER if
+ * this is a vital device and flags is DM_REMOVE_NON_VITAL, other -ve on
+ * error (such an error here is normally a very bad thing)
*/
#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
int device_remove(struct udevice *dev, uint flags);
/**
* device_chld_remove() - Stop all device's children
+ *
+ * This continues through all children recursively stopping part-way through if
+ * an error occurs. Return values of -EKEYREJECTED are ignored and processing
+ * continues, since they just indicate that the child did not elect to be
+ * removed based on the value of @flags. Return values of -EPROBE_DEFER cause
+ * processing of other children to continue, but the function will return
+ * -EPROBE_DEFER.
+ *
* @dev: The device whose children are to be removed
* @drv: The targeted driver
* @flags: Flag, if this functions is called in the pre-OS stage
- * @return 0 on success, -ve on error
+ * @return 0 on success, -EPROBE_DEFER if any child failed to remove, other
+ * -ve on error
*/
#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
int device_chld_remove(struct udevice *dev, struct driver *drv,
* Device is removed without switching off its power domain. This might
* be required, i. e. for serial console (debug) output when booting OS.
*/
-#define DM_FLAG_REMOVE_WITH_PD_ON (1 << 13)
+#define DM_FLAG_LEAVE_PD_ON (1 << 13)
+
+/*
+ * Device is vital to the operation of other devices. It is possible to remove
+ * removed this device after all regular devices are removed. This is useful
+ * e.g. for clock, which need to be active during the device-removal phase.
+ */
+#define DM_FLAG_VITAL (1 << 14)
/*
* One or multiple of these flags are passed to device_remove() so that
* a selective device removal as specified by the remove-stage and the
* driver flags can be done.
+ *
+ * DO NOT use these flags in your driver's @flags value...
+ * use the above DM_FLAG_... values instead
*/
enum {
/* Normal remove, remove all devices */
/* Remove devices which need some final OS preparation steps */
DM_REMOVE_OS_PREPARE = DM_FLAG_OS_PREPARE,
- /* Add more use cases here */
+ /* Remove only devices that are not marked vital */
+ DM_REMOVE_NON_VITAL = DM_FLAG_VITAL,
/* Remove devices with any active flag */
DM_REMOVE_ACTIVE_ALL = DM_REMOVE_ACTIVE_DMA | DM_REMOVE_OS_PREPARE,
* When CONFIG_DEVRES is enabled, devm_kmalloc() and friends will
* add to this list. Memory so-allocated will be freed
* automatically when the device is removed / unbound
+ * @dma_offset: Offset between the physical address space (CPU's) and the
+ * device's bus address space
*/
struct udevice {
const struct driver *driver;
#ifdef CONFIG_DEVRES
struct list_head devres_head;
#endif
+#if CONFIG_IS_ENABLED(DM_DMA)
+ ulong dma_offset;
+#endif
};
/* Maximum sequence number supported */
/* Returns non-zero if the device is active (probed and not removed) */
#define device_active(dev) (dev_get_flags(dev) & DM_FLAG_ACTIVATED)
+#if CONFIG_IS_ENABLED(DM_DMA)
+#define dev_set_dma_offset(_dev, _offset) _dev->dma_offset = _offset
+#define dev_get_dma_offset(_dev) _dev->dma_offset
+#else
+#define dev_set_dma_offset(_dev, _offset)
+#define dev_get_dma_offset(_dev) 0
+#endif
+
static inline int dev_of_offset(const struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
*/
u64 of_translate_dma_address(const struct device_node *no, const __be32 *in_addr);
+
+/**
+ * of_get_dma_range() - get dma-ranges for a specific DT node
+ *
+ * Get DMA ranges for a specifc node, this is useful to perform bus->cpu and
+ * cpu->bus address translations
+ *
+ * @param blob Pointer to device tree blob
+ * @param node_offset Node DT offset
+ * @param cpu Pointer to variable storing the range's cpu address
+ * @param bus Pointer to variable storing the range's bus address
+ * @param size Pointer to variable storing the range's size
+ * @return translated DMA address or OF_BAD_ADDR on error
+ */
+int of_get_dma_range(const struct device_node *dev, phys_addr_t *cpu,
+ dma_addr_t *bus, u64 *size);
+
/**
* of_get_address() - obtain an address from a node
*
ofnode ofnode_find_subnode(ofnode node, const char *subnode_name);
#if CONFIG_IS_ENABLED(DM_INLINE_OFNODE)
+#include <asm/global_data.h>
+
static inline bool ofnode_is_enabled(ofnode node)
{
if (ofnode_is_np(node)) {
u64 ofnode_translate_dma_address(ofnode node, const fdt32_t *in_addr);
/**
+ * ofnode_get_dma_range() - get dma-ranges for a specific DT node
+ *
+ * Get DMA ranges for a specifc node, this is useful to perform bus->cpu and
+ * cpu->bus address translations
+ *
+ * @param blob Pointer to device tree blob
+ * @param node_offset Node DT offset
+ * @param cpu Pointer to variable storing the range's cpu address
+ * @param bus Pointer to variable storing the range's bus address
+ * @param size Pointer to variable storing the range's size
+ * @return translated DMA address or OF_BAD_ADDR on error
+ */
+int ofnode_get_dma_range(ofnode node, phys_addr_t *cpu, dma_addr_t *bus,
+ u64 *size);
+
+/**
* ofnode_device_is_compatible() - check if the node is compatible with compat
*
* This allows to check whether the node is comaptible with the compat.
const fdt32_t *in_addr);
/**
+ * dev_get_dma_range() - Get a device's DMA constraints
+ *
+ * Provide the address bases and size of the linear mapping between the CPU and
+ * a device's BUS address space.
+ *
+ * @dev: device giving the context in which to translate the DMA address
+ * @cpu: base address for CPU's view of memory
+ * @bus: base address for BUS's view of memory
+ * @size: size of the address space
+ * @return 0 if ok, negative on error
+ */
+int dev_get_dma_range(const struct udevice *dev, phys_addr_t *cpu,
+ dma_addr_t *bus, u64 *size);
+
+/**
* dev_read_alias_highest_id - Get highest alias id for the given stem
* @stem: Alias stem to be examined
*
struct display_timing *config);
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
+#include <asm/global_data.h>
static inline int dev_read_u32(const struct udevice *dev,
const char *propname, u32 *outp)
return ofnode_translate_dma_address(dev_ofnode(dev), in_addr);
}
+static inline int dev_get_dma_range(const struct udevice *dev, phys_addr_t *cpu,
+ dma_addr_t *bus, u64 *size)
+{
+ return ofnode_get_dma_range(dev_ofnode(dev), cpu, bus, size);
+}
+
static inline int dev_read_alias_highest_id(const char *stem)
{
if (!CONFIG_IS_ENABLED(OF_LIBFDT) || !gd->fdt_blob)
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
UCLASS_DSI_HOST, /* Display Serial Interface host */
UCLASS_DMA, /* Direct Memory Access */
+ UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */
UCLASS_EFI, /* EFI managed devices */
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
#include <linux/errno.h>
#include <linux/types.h>
+struct udevice;
+
/*
* enum dma_direction - dma transfer direction indicator
* @DMA_MEM_TO_MEM: Memcpy mode
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* This file defines field values used by the versaclock 6 family
+ * for defining output type
+ */
+
+#define VC5_LVPECL 0
+#define VC5_CMOS 1
+#define VC5_HCSL33 2
+#define VC5_LVDS 3
+#define VC5_CMOS2 4
+#define VC5_CMOSD 5
+#define VC5_HCSL25 6
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for SERDES MUX for TI SoCs
+ */
+
+#ifndef _DT_BINDINGS_MUX_TI_SERDES
+#define _DT_BINDINGS_MUX_TI_SERDES
+
+/* J721E */
+
+#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
+#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
+#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
+#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
+#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
+#define J721E_SERDES0_LANE1_USB3_0 0x2
+#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
+#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
+#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
+#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
+
+#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
+#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
+#define J721E_SERDES1_LANE1_USB3_1 0x2
+#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
+
+#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
+#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
+#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
+#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
+
+#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
+#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
+#define J721E_SERDES2_LANE1_USB3_1 0x2
+#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
+
+#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
+#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
+#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
+#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
+
+#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
+#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
+#define J721E_SERDES3_LANE1_USB3_0 0x2
+#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
+#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
+#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
+#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
+#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
+#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
+#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
+
+#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
+#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
+#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
+#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
+
+/* J7200 */
+
+#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
+#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
+#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
+#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
+#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J7200_SERDES0_LANE3_USB 0x2
+#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
+
+#endif /* _DT_BINDINGS_MUX_TI_SERDES */
{
#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
static char default_environment[] = {
+#elif defined(DEFAULT_ENV_IS_RW)
+uchar default_environment[] = {
#else
const uchar default_environment[] = {
#endif
extern env_t embedded_environment;
#endif /* ENV_IS_EMBEDDED */
+#ifdef DEFAULT_ENV_IS_RW
+extern unsigned char default_environment[];
+#else
extern const unsigned char default_environment[];
+#endif
#ifndef DO_DEPS_ONLY
#define __EXPORTS_H__
#include <irq_func.h>
+#include <asm/global_data.h>
#include <linux/delay.h>
#ifndef __ASSEMBLY__
int strcmp(const char *cs, const char *ct);
unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
-#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
+#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
#endif
#ifndef __EXT_COMMON__
#define __EXT_COMMON__
+#include <compiler.h>
+
struct cmd_tbl;
#define SECTOR_SIZE 0x200
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
FASTBOOT_COMMAND_OEM_FORMAT,
#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF)
+ FASTBOOT_COMMAND_OEM_PARTCONF,
+#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS)
+ FASTBOOT_COMMAND_OEM_BOOTBUS,
+#endif
FASTBOOT_COMMAND_COUNT
};
};
/**
- * BCB boot commands
- */
-static const char * const fastboot_boot_cmds[] = {
- [FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader",
- [FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot",
- [FASTBOOT_REBOOT_REASON_RECOVERY] = "boot-recovery"
-};
-
-/**
* fastboot_response() - Writes a response of the form "$tag$reason".
*
* @tag: The first part of the response
u64 fdt_translate_dma_address(const void *blob, int node_offset,
const __be32 *in_addr);
+/**
+ * Get DMA ranges for a specifc node, this is useful to perform bus->cpu and
+ * cpu->bus address translations
+ *
+ * @param blob Pointer to device tree blob
+ * @param node_offset Node DT offset
+ * @param cpu Pointer to variable storing the range's cpu address
+ * @param bus Pointer to variable storing the range's bus address
+ * @param size Pointer to variable storing the range's size
+ * @return translated DMA address or OF_BAD_ADDR on error
+ */
+int fdt_get_dma_range(const void *blob, int node_offset, phys_addr_t *cpu,
+ dma_addr_t *bus, u64 *size);
+
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
phys_addr_t compat_off);
int fdt_alloc_phandle(void *blob);
#define QE_DATAONLY_BASE 0
#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
+struct udevice;
+
/* QE threads SNUM
*/
typedef enum qe_snum_state {
* @return 0 if OK, or a negative error code
*/
int (*power_off)(struct phy *phy);
+
+ /**
+ * configure - configure a PHY device
+ *
+ * @phy: PHY port to be configured
+ * @params: PHY Parameters, underlying data is specific to the PHY function
+ *
+ * During runtime, the PHY may need to be configured for it's main function.
+ * This function configures the PHY for it's main function following
+ * power_on/off() after beeing initialized.
+ *
+ * @return 0 if OK, or a negative error code
+ */
+ int (*configure)(struct phy *phy, void *params);
};
/**
*/
int generic_phy_power_off(struct phy *phy);
+/**
+ * generic_phy_configure() - configure a PHY device
+ *
+ * @phy: PHY port to be configured
+ * @params: PHY Parameters, underlying data is specific to the PHY function
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_configure(struct phy *phy, void *params);
+
/**
* generic_phy_get_by_index() - Get a PHY device by integer index.
*/
int acpi_i2c_of_to_plat(struct udevice *dev);
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/*
* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
* Copyright 2014 Broadcom Corporation.
*/
+#include <compiler.h>
#include <part.h>
#include <sparse_format.h>
extern ulong image_save_addr; /* Default Save Address */
extern ulong image_save_size; /* Default Save Size */
+/* An invalid size, meaning that the image size is not known */
+#define IMAGE_SIZE_INVAL (-1UL)
+
enum ih_category {
IH_ARCH,
IH_COMP,
int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
int fit_image_check_type(const void *fit, int noffset, uint8_t type);
int fit_image_check_comp(const void *fit, int noffset, uint8_t comp);
-int fit_check_format(const void *fit);
+
+/**
+ * fit_check_format() - Check that the FIT is valid
+ *
+ * This performs various checks on the FIT to make sure it is suitable for
+ * use, looking for mandatory properties, nodes, etc.
+ *
+ * If FIT_FULL_CHECK is enabled, it also runs it through libfdt to make
+ * sure that there are no strange tags or broken nodes in the FIT.
+ *
+ * @fit: pointer to the FIT format image header
+ * @return 0 if OK, -ENOEXEC if not an FDT file, -EINVAL if the full FDT check
+ * failed (e.g. due to bad structure), -ENOMSG if the description is
+ * missing, -ENODATA if the timestamp is missing, -ENOENT if the /images
+ * path is missing
+ */
+int fit_check_format(const void *fit, ulong size);
int fit_conf_find_compat(const void *fit, const void *fdt);
*/
int board_fit_config_name_match(const char *name);
-#if defined(CONFIG_SPL_FIT_IMAGE_POST_PROCESS) || \
- defined(CONFIG_FIT_IMAGE_POST_PROCESS)
/**
* board_fit_image_post_process() - Do any post-process on FIT binary data
*
* @return no return value (failure should be handled internally)
*/
void board_fit_image_post_process(void **p_image, size_t *p_size);
-#else
-static inline void board_fit_image_post_process(void **p_image, size_t *p_size)
-{
-}
-#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
#define FDT_ERROR ((ulong)(-1))
#ifndef __INIT_H_
#define __INIT_H_ 1
-#include <linux/types.h>
-
-struct global_data;
-
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+#include <linux/types.h>
+
/* Avoid using CONFIG_EFI_STUB directly as we may boot from other loaders */
#ifdef CONFIG_EFI_STUB
#define ll_boot_init() false
#else
+#include <asm/global_data.h>
+
#define ll_boot_init() (!(gd->flags & GD_FLG_SKIP_LL_INIT))
#endif
#endif
/* Print a numeric value (for use in arch_print_bdinfo()) */
-void bdinfo_print_num(const char *name, ulong value);
+void bdinfo_print_num_l(const char *name, ulong value);
+void bdinfo_print_num_ll(const char *name, unsigned long long value);
/* Print a clock speed in MHz */
void bdinfo_print_mhz(const char *name, unsigned long hz);
#ifdef CONFIG_EFI_APP
#include <efi.h>
#endif
+#include <asm/global_data.h>
/*
* To enable debugging. add #define DEBUG at the top of the including file.
*/
extern int cd_count[MAX_FILES];
+#define for_each_console_dev(i, file, dev) \
+ for (i = 0, dev = console_devices[file][i]; \
+ i < cd_count[file]; \
+ i++, dev = console_devices[file][i])
+
+int iomux_match_device(struct stdio_dev **, const int, struct stdio_dev *);
int iomux_doenv(const int, const char *);
+int iomux_replace_device(const int, const char *, const char *);
void iomux_printdevs(const int);
#endif /* _IO_MUX_H */
#ifndef __LED_H
#define __LED_H
+struct udevice;
+
/**
* struct led_uc_plat - Platform data the uclass stores about each device
*
#include <linux/bitops.h>
#include <linux/err.h>
#include <clk-uclass.h>
-#include <linux/err.h>
struct udevice;
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007
- * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
- */
-
-/*
- * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
- */
-
-#ifndef _MB862XX_H_
-#define _MB862XX_H_
-
-#define PCI_VENDOR_ID_FUJITSU 0x10CF
-#define PCI_DEVICE_ID_CORAL_P 0x2019
-#define PCI_DEVICE_ID_CORAL_PA 0x201E
-
-#define MB862XX_TYPE_LIME 0x1
-
-#define GC_HOST_BASE 0x01fc0000
-#define GC_DISP_BASE 0x01fd0000
-#define GC_DRAW_BASE 0x01ff0000
-
-/* Host interface registers */
-#define GC_SRST 0x0000002c
-#define GC_CCF 0x00000038
-#define GC_CID 0x000000f0
-#define GC_MMR 0x0000fffc
-
-/*
- * Display Controller registers
- * _A means the offset is aligned, we use these for boards
- * with 8-/16-bit GDC access not working or buggy.
- */
-#define GC_DCM0 0x00000000
-#define GC_HTP_A 0x00000004
-#define GC_HTP 0x00000006
-#define GC_HDB_HDP_A 0x00000008
-#define GC_HDP 0x00000008
-#define GC_HDB 0x0000000a
-#define GC_VSW_HSW_HSP_A 0x0000000c
-#define GC_HSP 0x0000000c
-#define GC_HSW 0x0000000e
-#define GC_VSW 0x0000000f
-#define GC_VTR_A 0x00000010
-#define GC_VTR 0x00000012
-#define GC_VDP_VSP_A 0x00000014
-#define GC_VSP 0x00000014
-#define GC_VDP 0x00000016
-#define GC_WY_WX 0x00000018
-#define GC_WH_WW 0x0000001c
-#define GC_L0M 0x00000020
-#define GC_L0OA0 0x00000024
-#define GC_L0DA0 0x00000028
-#define GC_L0DY_L0DX 0x0000002c
-#define GC_L2M 0x00000040
-#define GC_L2OA0 0x00000044
-#define GC_L2DA0 0x00000048
-#define GC_L2OA1 0x0000004c
-#define GC_L2DA1 0x00000050
-#define GC_L2DX 0x00000054
-#define GC_L2DY 0x00000056
-#define GC_DCM1 0x00000100
-#define GC_DCM2 0x00000104
-#define GC_DCM3 0x00000108
-#define GC_L0EM 0x00000110
-#define GC_L0WY_L0WX 0x00000114
-#define GC_L0WH_L0WW 0x00000118
-#define GC_L2EM 0x00000130
-#define GC_L2WX 0x00000134
-#define GC_L2WY 0x00000136
-#define GC_L2WW 0x00000138
-#define GC_L2WH 0x0000013a
-#define GC_L0PAL0 0x00000400
-
-/* Drawing registers */
-#define GC_CTR 0x00000400
-#define GC_IFCNT 0x00000408
-#define GC_FBR 0x00000440
-#define GC_XRES 0x00000444
-#define GC_CXMIN 0x00000454
-#define GC_CXMAX 0x00000458
-#define GC_CYMIN 0x0000045c
-#define GC_CYMAX 0x00000460
-#define GC_FC 0x00000480
-#define GC_BC 0x00000484
-#define GC_FIFO 0x000004a0
-#define GC_REV 0x00008084
-#define GC_GEO_FIFO 0x00008400
-
-typedef struct {
- unsigned int index;
- unsigned int value;
-} gdc_regs;
-
-int mb862xx_probe(unsigned int addr);
-const gdc_regs *board_get_regs (void);
-unsigned int board_video_init (void);
-void board_backlight_switch(int);
-
-#endif /* _MB862XX_H_ */
#ifndef _MISC_H_
#define _MISC_H_
+struct udevice;
+
/**
* misc_read() - Read the device to buffer, optional.
* @dev: the device
#define MMC_STATUS_ERROR (1 << 19)
#define MMC_STATE_PRG (7 << 9)
+#define MMC_STATE_TRANS (4 << 9)
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
uint f_max;
uint b_max;
unsigned char part_type;
+#ifdef CONFIG_MMC_PWRSEQ
+ struct udevice *pwr_dev;
+#endif
};
struct sd_ssr {
u8 hs400_tuning;
};
+#if CONFIG_IS_ENABLED(DM_MMC)
+#define mmc_to_dev(_mmc) _mmc->dev
+#else
+#define mmc_to_dev(_mmc) NULL
+#endif
+
struct mmc_hwpart_conf {
struct {
uint enh_start; /* in 512-byte sectors */
*/
int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
+#ifdef CONFIG_MMC_PWRSEQ
+/**
+ * mmc_pwrseq_get_power() - get a power device from device tree
+ *
+ * @dev: MMC device
+ * @cfg: MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg);
+#endif
+
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
/**
* maximum packet size and multiple of 32 bytes = 1536
*/
#define PKTSIZE 1522
+#ifndef CONFIG_DM_DSA
#define PKTSIZE_ALIGN 1536
+#else
+/* Maximum DSA tagging overhead (headroom and/or tailroom) */
+#define DSA_MAX_OVR 256
+#define PKTSIZE_ALIGN (1536 + DSA_MAX_OVR)
+#endif
/*
* Maximum receive ring size; that is, the number of packets
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+#ifndef __DSA_H__
+#define __DSA_H__
+
+#include <phy.h>
+#include <net.h>
+
+/**
+ * DSA stands for Distributed Switch Architecture and it is infrastructure
+ * intended to support drivers for Switches that rely on an intermediary
+ * Ethernet device for I/O. These switches may support cascading allowing
+ * them to be arranged as a tree.
+ * DSA is documented in detail in the Linux kernel documentation under
+ * Documentation/networking/dsa/dsa.txt
+ * The network layout of such a switch is shown below:
+ *
+ * |------|
+ * | eth0 | <--- master eth device (regular eth driver)
+ * |------|
+ * ^ |
+ * tag added by switch -->| |
+ * | |
+ * | |<-- tag added by DSA driver
+ * | v
+ * |--------------------------------------|
+ * | | CPU port | | <-- DSA (switch) device
+ * | ------------ | (DSA driver)
+ * | _________ _________ _________ |
+ * | | port0 | | port1 | ... | portn | | <-- ports as eth devices
+ * |-+-------+--+-------+-------+-------+-| ('dsa-port' eth driver)
+ *
+ * In U-Boot the intent is to allow access to front panel ports (shown at the
+ * bottom of the picture) through the master Ethernet dev (eth0 in the picture).
+ * Front panel ports are presented as regular Ethernet devices in U-Boot and
+ * they are expected to support the typical networking commands.
+ * In general DSA switches require the use of tags, extra headers added both by
+ * software on Tx and by the switch on Rx. These tags carry at a minimum port
+ * information and switch information for cascaded set-ups.
+ * In U-Boot these tags are inserted and parsed by the DSA switch driver, the
+ * class code helps with headroom/tailroom for the extra headers.
+ *
+ * TODO:
+ * - handle switch cascading, for now U-Boot only supports stand-alone switches.
+ * - Add support to probe DSA switches connected to a MDIO bus, this is needed
+ * to convert switch drivers that are now under drivers/net/phy.
+ */
+
+#define DSA_PORT_NAME_LENGTH 16
+
+/* Maximum number of ports each DSA device can have */
+#define DSA_MAX_PORTS 12
+
+/**
+ * struct dsa_ops - DSA operations
+ *
+ * @port_enable: Initialize a switch port for I/O.
+ * @port_disable: Disable I/O for a port.
+ * @xmit: Insert the DSA tag for transmission.
+ * DSA drivers receive a copy of the packet with headroom and
+ * tailroom reserved and set to 0. 'packet' points to headroom
+ * and 'length' is updated to include both head and tailroom.
+ * @rcv: Process the DSA tag on reception and return the port index
+ * from the h/w provided tag. Return the index via 'portp'.
+ * 'packet' and 'length' describe the frame as received from
+ * master including any additional headers.
+ */
+struct dsa_ops {
+ int (*port_enable)(struct udevice *dev, int port,
+ struct phy_device *phy);
+ void (*port_disable)(struct udevice *dev, int port,
+ struct phy_device *phy);
+ int (*xmit)(struct udevice *dev, int port, void *packet, int length);
+ int (*rcv)(struct udevice *dev, int *portp, void *packet, int length);
+};
+
+#define dsa_get_ops(dev) ((struct dsa_ops *)(dev)->driver->ops)
+
+/**
+ * struct dsa_port_pdata - DSA port platform data
+ *
+ * @phy: PHY device associated with this port.
+ * The uclass code attempts to set this field for all ports except CPU
+ * port, based on DT information. It may be NULL.
+ * @index: Port index in the DSA switch, set by the uclass code.
+ * @name: Name of the port Eth device. If a label property is present in the
+ * port DT node, it is used as name.
+ */
+struct dsa_port_pdata {
+ struct phy_device *phy;
+ u32 index;
+ char name[DSA_PORT_NAME_LENGTH];
+};
+
+/**
+ * struct dsa_pdata - Per-device platform data for DSA DM
+ *
+ * @num_ports: Number of ports the device has, must be <= DSA_MAX_PORTS.
+ * This number is extracted from the DT 'ports' node of this
+ * DSA device, and it counts the CPU port and all the other
+ * port subnodes including the disabled ones.
+ * @cpu_port: Index of the switch port linked to the master Ethernet.
+ * The uclass code sets this based on DT information.
+ * @master_node: OF node of the host Ethernet controller.
+ * @cpu_port_node: DT node of the switch's CPU port.
+ */
+struct dsa_pdata {
+ int num_ports;
+ u32 cpu_port;
+ ofnode master_node;
+ ofnode cpu_port_node;
+};
+
+/**
+ * dsa_set_tagging() - Configure the headroom and/or tailroom sizes
+ *
+ * The DSA class code allocates headroom and tailroom on Tx before
+ * calling the DSA driver's xmit function.
+ * All drivers must call this at probe time.
+ *
+ * @dev: DSA device pointer
+ * @headroom: Size, in bytes, of headroom needed for the DSA tag.
+ * @tailroom: Size, in bytes, of tailroom needed for the DSA tag.
+ * Total headroom and tailroom size should not exceed
+ * DSA_MAX_OVR.
+ * @return 0 if OK, -ve on error
+ */
+int dsa_set_tagging(struct udevice *dev, ushort headroom, ushort tailroom);
+
+/* DSA helpers */
+
+/**
+ * dsa_get_master() - Return a reference to the master Ethernet device
+ *
+ * Can be called at driver probe time or later.
+ *
+ * @dev: DSA device pointer
+ * @return Master Eth 'udevice' pointer if OK, NULL on error
+ */
+struct udevice *dsa_get_master(struct udevice *dev);
+
+/**
+ * dsa_port_get_pdata() - Helper that returns the platdata of an active
+ * (non-CPU) DSA port device.
+ *
+ * Can be called at driver probe time or later.
+ *
+ * @pdev: DSA port device pointer
+ * @return 'dsa_port_pdata' pointer if OK, NULL on error
+ */
+static inline struct dsa_port_pdata *
+ dsa_port_get_pdata(struct udevice *pdev)
+{
+ struct eth_pdata *eth = dev_get_plat(pdev);
+
+ if (!eth)
+ return NULL;
+
+ return eth->priv_pdata;
+}
+
+#endif /* __DSA_H__ */
#define _NETDEV_H_
#include <phy_interface.h>
+struct udevice;
+
/*
* Board and CPU-specific initialization functions
* board_eth_init() has highest priority. cpu_eth_init() only
/**
* os_abort() - raise SIGABRT to exit sandbox (e.g. to debugger)
*/
-void os_abort(void);
+void os_abort(void) __attribute__((noreturn));
/**
* os_mprotect_allow() - Remove write-protection on a region of memory
#define BB_VSEL_VBAT (3 << 1)
#define BB_CHRG_EN (1 << 0)
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
/*
* Functions to read and write from TPS659038/TWL6035/TWL6037
* or other Palmas family of TI PMICs
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Cadence Design Systems Inc.
+ */
+
+#ifndef __PHY_MIPI_DPHY_H_
+#define __PHY_MIPI_DPHY_H_
+
+/**
+ * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * MIPI D-PHY phy.
+ */
+struct phy_configure_opts_mipi_dphy {
+ /**
+ * @clk_miss:
+ *
+ * Timeout, in picoseconds, for receiver to detect absence of
+ * Clock transitions and disable the Clock Lane HS-RX.
+ *
+ * Maximum value: 60000 ps
+ */
+ unsigned int clk_miss;
+
+ /**
+ * @clk_post:
+ *
+ * Time, in picoseconds, that the transmitter continues to
+ * send HS clock after the last associated Data Lane has
+ * transitioned to LP Mode. Interval is defined as the period
+ * from the end of @hs_trail to the beginning of @clk_trail.
+ *
+ * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
+ */
+ unsigned int clk_post;
+
+ /**
+ * @clk_pre:
+ *
+ * Time, in UI, that the HS clock shall be driven by
+ * the transmitter prior to any associated Data Lane beginning
+ * the transition from LP to HS mode.
+ *
+ * Minimum value: 8 UI
+ */
+ unsigned int clk_pre;
+
+ /**
+ * @clk_prepare:
+ *
+ * Time, in picoseconds, that the transmitter drives the Clock
+ * Lane LP-00 Line state immediately before the HS-0 Line
+ * state starting the HS transmission.
+ *
+ * Minimum value: 38000 ps
+ * Maximum value: 95000 ps
+ */
+ unsigned int clk_prepare;
+
+ /**
+ * @clk_settle:
+ *
+ * Time interval, in picoseconds, during which the HS receiver
+ * should ignore any Clock Lane HS transitions, starting from
+ * the beginning of @clk_prepare.
+ *
+ * Minimum value: 95000 ps
+ * Maximum value: 300000 ps
+ */
+ unsigned int clk_settle;
+
+ /**
+ * @clk_term_en:
+ *
+ * Time, in picoseconds, for the Clock Lane receiver to enable
+ * the HS line termination.
+ *
+ * Maximum value: 38000 ps
+ */
+ unsigned int clk_term_en;
+
+ /**
+ * @clk_trail:
+ *
+ * Time, in picoseconds, that the transmitter drives the HS-0
+ * state after the last payload clock bit of a HS transmission
+ * burst.
+ *
+ * Minimum value: 60000 ps
+ */
+ unsigned int clk_trail;
+
+ /**
+ * @clk_zero:
+ *
+ * Time, in picoseconds, that the transmitter drives the HS-0
+ * state prior to starting the Clock.
+ */
+ unsigned int clk_zero;
+
+ /**
+ * @d_term_en:
+ *
+ * Time, in picoseconds, for the Data Lane receiver to enable
+ * the HS line termination.
+ *
+ * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
+ */
+ unsigned int d_term_en;
+
+ /**
+ * @eot:
+ *
+ * Transmitted time interval, in picoseconds, from the start
+ * of @hs_trail or @clk_trail, to the start of the LP- 11
+ * state following a HS burst.
+ *
+ * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps
+ */
+ unsigned int eot;
+
+ /**
+ * @hs_exit:
+ *
+ * Time, in picoseconds, that the transmitter drives LP-11
+ * following a HS burst.
+ *
+ * Minimum value: 100000 ps
+ */
+ unsigned int hs_exit;
+
+ /**
+ * @hs_prepare:
+ *
+ * Time, in picoseconds, that the transmitter drives the Data
+ * Lane LP-00 Line state immediately before the HS-0 Line
+ * state starting the HS transmission.
+ *
+ * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps
+ * Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps
+ */
+ unsigned int hs_prepare;
+
+ /**
+ * @hs_settle:
+ *
+ * Time interval, in picoseconds, during which the HS receiver
+ * shall ignore any Data Lane HS transitions, starting from
+ * the beginning of @hs_prepare.
+ *
+ * Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps
+ * Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps
+ */
+ unsigned int hs_settle;
+
+ /**
+ * @hs_skip:
+ *
+ * Time interval, in picoseconds, during which the HS-RX
+ * should ignore any transitions on the Data Lane, following a
+ * HS burst. The end point of the interval is defined as the
+ * beginning of the LP-11 state following the HS burst.
+ *
+ * Minimum value: 40000 ps
+ * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps
+ */
+ unsigned int hs_skip;
+
+ /**
+ * @hs_trail:
+ *
+ * Time, in picoseconds, that the transmitter drives the
+ * flipped differential state after last payload data bit of a
+ * HS transmission burst
+ *
+ * Minimum value: max(8 * @hs_clk_rate period in ps,
+ * 60000 ps + 4 * @hs_clk_rate period in ps)
+ */
+ unsigned int hs_trail;
+
+ /**
+ * @hs_zero:
+ *
+ * Time, in picoseconds, that the transmitter drives the HS-0
+ * state prior to transmitting the Sync sequence.
+ */
+ unsigned int hs_zero;
+
+ /**
+ * @init:
+ *
+ * Time, in microseconds for the initialization period to
+ * complete.
+ *
+ * Minimum value: 100 us
+ */
+ unsigned int init;
+
+ /**
+ * @lpx:
+ *
+ * Transmitted length, in picoseconds, of any Low-Power state
+ * period.
+ *
+ * Minimum value: 50000 ps
+ */
+ unsigned int lpx;
+
+ /**
+ * @ta_get:
+ *
+ * Time, in picoseconds, that the new transmitter drives the
+ * Bridge state (LP-00) after accepting control during a Link
+ * Turnaround.
+ *
+ * Value: 5 * @lpx
+ */
+ unsigned int ta_get;
+
+ /**
+ * @ta_go:
+ *
+ * Time, in picoseconds, that the transmitter drives the
+ * Bridge state (LP-00) before releasing control during a Link
+ * Turnaround.
+ *
+ * Value: 4 * @lpx
+ */
+ unsigned int ta_go;
+
+ /**
+ * @ta_sure:
+ *
+ * Time, in picoseconds, that the new transmitter waits after
+ * the LP-10 state before transmitting the Bridge state
+ * (LP-00) during a Link Turnaround.
+ *
+ * Minimum value: @lpx
+ * Maximum value: 2 * @lpx
+ */
+ unsigned int ta_sure;
+
+ /**
+ * @wakeup:
+ *
+ * Time, in microseconds, that a transmitter drives a Mark-1
+ * state prior to a Stop state in order to initiate an exit
+ * from ULPS.
+ *
+ * Minimum value: 1000 us
+ */
+ unsigned int wakeup;
+
+ /**
+ * @hs_clk_rate:
+ *
+ * Clock rate, in Hertz, of the high-speed clock.
+ */
+ unsigned long hs_clk_rate;
+
+ /**
+ * @lp_clk_rate:
+ *
+ * Clock rate, in Hertz, of the low-power clock.
+ */
+ unsigned long lp_clk_rate;
+
+ /**
+ * @lanes:
+ *
+ * Number of active, consecutive, data lanes, starting from
+ * lane 0, used for the transmissions.
+ */
+ unsigned char lanes;
+};
+
+int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
+ unsigned int bpp,
+ unsigned int lanes,
+ struct phy_configure_opts_mipi_dphy *cfg);
+int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg);
+
+#endif /* __PHY_MIPI_DPHY_H_ */
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
phy_interface_t interface);
+#ifdef CONFIG_PHY_FIXED
+
+/**
+ * fixed_phy_create() - create an unconnected fixed-link pseudo-PHY device
+ * @node: OF node for the container of the fixed-link node
+ *
+ * Description: Creates a struct phy_device based on a fixed-link of_node
+ * description. Can be used without phy_connect by drivers which do not expose
+ * a UCLASS_ETH udevice.
+ */
+struct phy_device *fixed_phy_create(ofnode node);
+
+#else
+
+static inline struct phy_device *fixed_phy_create(ofnode node)
+{
+ return NULL;
+}
+
+#endif
+
#ifdef CONFIG_DM_ETH
/**
}
#endif
+#if CONFIG_IS_ENABLED(DM)
+#include <dm/device.h>
+
+static inline dma_addr_t dev_phys_to_bus(struct udevice *dev, phys_addr_t phys)
+{
+ return phys - dev_get_dma_offset(dev);
+}
+
+static inline phys_addr_t dev_bus_to_phys(struct udevice *dev, dma_addr_t bus)
+{
+ return bus + dev_get_dma_offset(dev);
+}
+#else
+#define dev_phys_to_bus(_, _addr) _addr
+#define dev_bus_to_phys(_, _addr) _addr
+#endif
+
#endif
#ifndef __POWER_AS3722_H__
#define __POWER_AS3722_H__
+struct udevice;
+
#define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
#define AS3722_GPIO_INVERT (1 << 1)
#ifndef _INCLUDE_REGULATOR_H_
#define _INCLUDE_REGULATOR_H_
+struct udevice;
+
/**
* U-Boot Voltage/Current Regulator
* ================================
#ifndef _pwm_h_
#define _pwm_h_
+struct udevice;
+
/* struct pwm_ops: Operations for the PWM uclass */
struct pwm_ops {
/**
#ifndef __RAM_H
#define __RAM_H
+struct udevice;
+
struct ram_info {
phys_addr_t base;
size_t size;
#include <asm/cache.h>
#include <linux/dma-direction.h>
+struct udevice;
+
struct scsi_cmd {
unsigned char cmd[16]; /* command */
/* for request sense */
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
+
+/**
+ * sdhci_set_control_reg - Set control registers
+ *
+ * This is used set up control registers for voltage level and UHS speed
+ * mode.
+ *
+ * @host: SDHCI host structure
+ */
+void sdhci_set_control_reg(struct sdhci_host *host);
extern const struct dm_mmc_ops sdhci_ops;
#else
#endif
u16 handle;
u8 reserved[6];
u8 boot_status;
- u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
};
struct __packed smbios_type127 {
u8 type;
u8 length;
u16 handle;
- u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
};
struct __packed smbios_header {
}
/**
- * Function prototype to write a specific type of SMBIOS structure
- *
- * @addr: start address to write the structure
- * @handle: the structure's handle, a unique 16-bit number
- * @node: node containing the information to write (ofnode_null() if none)
- * @return: size of the structure
- */
-typedef int (*smbios_write_type)(ulong *addr, int handle, ofnode node);
-
-/**
* write_smbios_table() - Write SMBIOS table
*
* This writes SMBIOS table at a given address.
*/
const char *smbios_string(const struct smbios_header *header, int index);
+/**
+ * smbios_update_version() - Update the version string
+ *
+ * This can be called after the SMBIOS tables are written (e.g. after the U-Boot
+ * main loop has started) to update the BIOS version string (SMBIOS table 0).
+ *
+ * @version: New version string to use
+ * @return 0 if OK, -ENOENT if no version string was previously written,
+ * -ENOSPC if the new string is too large to fit
+ */
+int smbios_update_version(const char *version);
+
#endif /* _SMBIOS_H_ */
#define SOC_MAX_STR_SIZE 128
+struct udevice;
+
/**
* struct soc_attr - Contains SoC identify information to be used in
* SoC matching. An array of these structs
int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op);
+bool spi_mem_default_supports_op(struct spi_slave *mem,
+ const struct spi_mem_op *op);
+
#ifndef __UBOOT__
int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
struct module *owner);
/**
* board_spl_fit_post_load - allow process images after loading finished
- *
+ * @fit: Pointer to a valid Flattened Image Tree blob
*/
-void board_spl_fit_post_load(ulong load_addr, size_t length);
+void board_spl_fit_post_load(const void *fit);
/**
* board_spl_fit_size_align - specific size align before processing payload
#define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */
#define DEV_FLAGS_DM 0x00000004 /* Device priv is a struct udevice * */
+int stdio_file_to_flags(const int file);
+
/* Device information */
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int stdio_init(void);
void stdio_print_current_devices(void);
-int stdio_deregister(const char *devname, int force);
/**
* stdio_deregister_dev() - deregister the device "devname".
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
+struct udevice;
+
/*
* This uclass encapsulates hardware methods to gather information about a
* sysinfo or a specific device such as hard-wired GPIOs on GPIO expanders,
* to read the serial number.
*/
-#if CONFIG_IS_ENABLED(SYSINFO)
+/** enum sysinfo_id - Standard IDs defined by U-Boot */
+enum sysinfo_id {
+ SYSINFO_ID_NONE,
+
+ SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
+ SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
+
+ /* First value available for downstream/board used */
+ SYSINFO_ID_USER = 0x1000,
+};
+
struct sysinfo_ops {
/**
* detect() - Run the hardware info detection procedure for this
#define sysinfo_get_ops(dev) ((struct sysinfo_ops *)(dev)->driver->ops)
+#if CONFIG_IS_ENABLED(SYSINFO)
/**
* sysinfo_detect() - Run the hardware info detection procedure for this device.
*
#ifndef __SYSRESET_H
#define __SYSRESET_H
+struct udevice;
+
enum sysreset_t {
SYSRESET_WARM, /* Reset CPU, keep GPIOs active */
SYSRESET_COLD, /* Reset CPU and GPIOs */
#define __TEE_H
#include <linux/bitops.h>
+#include <linux/list.h>
+
#define TEE_UUID_LEN 16
#define TEE_GEN_CAP_GP BIT(0) /* GlobalPlatform compliant TEE */
--- /dev/null
+/* SPDX-License-Identifier: BSD-2-Clause */
+/* Copyright (c) 2020 Foundries Ltd */
+
+#ifndef __TA_RPC_TEST_H
+#define __TA_RPC_TEST_H
+
+#define TA_RPC_TEST_UUID { 0x48420575, 0x96ca, 0x401a, \
+ { 0x89, 0x91, 0x1e, 0xfd, 0xce, 0xbd, 0x7d, 0x04 } }
+
+/*
+ * Does a reverse RPC call for I2C read
+ *
+ * in params[0].value.a: bus number
+ * in params[0].value.b: chip address
+ * in params[0].value.c: control flags
+ * inout params[1].u.memref: buffer to read data
+ */
+#define TA_RPC_TEST_CMD_I2C_READ 0
+
+/*
+ * Does a reverse RPC call for I2C write
+ *
+ * in params[0].value.a: bus number
+ * in params[0].value.b: chip address
+ * in params[0].value.c: control flags
+ * inout params[1].u.memref: buffer with data to write
+ */
+#define TA_RPC_TEST_CMD_I2C_WRITE 1
+
+#endif /* __TA_RPC_TEST_H */
#include <command.h>
+struct udevice;
+
enum tpm_duration {
TPM_SHORT = 0,
TPM_MEDIUM = 1,
#include <tpm-common.h>
#include <linux/bitops.h>
+struct udevice;
+
/* Useful constants */
enum {
TPM_REQUEST_HEADER_LENGTH = 10,
#include <tpm-common.h>
+struct udevice;
+
#define TPM2_DIGEST_LEN 32
#define TPM2_SHA1_DIGEST_SIZE 20
#ifndef _TPS6586X_H_
#define _TPS6586X_H_
+struct udevice;
+
enum {
/* SM0-2 PWM/PFM Mode Selection */
TPS6586X_PWM_SM0 = 1 << 0,
* examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
* TWL4030_LED_LEDEN.
*/
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{
return i2c_write(chip_no, reg, 1, &val, 1);
};
/* Functions to read and write from TWL6030 */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{
return i2c_write(chip_no, reg, 1, &val, 1);
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef _UFS_H
#define _UFS_H
+
+struct udevice;
+
/**
* ufs_probe() - initialize all devices in the UFS uclass
*
#ifndef HOST_XHCI_H_
#define HOST_XHCI_H_
+#include <phys2bus.h>
#include <reset.h>
#include <asm/types.h>
#include <asm/cache.h>
#define XHCI_MTK_HOST BIT(0)
};
+#if CONFIG_IS_ENABLED(DM_USB)
+#define xhci_to_dev(_ctrl) _ctrl->dev
+#else
+#define xhci_to_dev(_ctrl) NULL
+#endif
+
unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);
struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
void xhci_flush_cache(uintptr_t addr, u32 type_len);
void xhci_inval_cache(uintptr_t addr, u32 type_len);
void xhci_cleanup(struct xhci_ctrl *ctrl);
-struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs);
+struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs,
+ bool link_trbs);
int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id);
int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
struct xhci_hcor *hcor);
struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev);
+static inline dma_addr_t xhci_virt_to_bus(struct xhci_ctrl *ctrl, void *addr)
+{
+ return dev_phys_to_bus(xhci_to_dev(ctrl), virt_to_phys(addr));
+}
+
+static inline void *xhci_bus_to_virt(struct xhci_ctrl *ctrl, dma_addr_t addr)
+{
+ return phys_to_virt(dev_bus_to_phys(xhci_to_dev(ctrl), addr));
+}
+
#endif /* HOST_XHCI_H_ */
#include <tables_csum.h>
#include <version.h>
#include <acpi/acpi_table.h>
+#include <asm/global_data.h>
#include <dm/acpi.h>
int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags)
#include <common.h>
#include <asm-offsets.h>
+#include <asm/global_data.h>
#include <linux/kbuild.h>
#include <errno.h>
#include <init.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <linux/err.h>
#include <linux/types.h>
#include <efi.h>
#include <efi.h>
#include <errno.h>
#include <mapmem.h>
+#include <asm/global_data.h>
int efi_info_get(enum efi_entry_t type, void **datap, int *sizep)
{
#include <u-boot/crc.h>
#include <usb.h>
#include <watchdog.h>
+#include <asm/global_data.h>
#include <linux/libfdt_env.h>
DECLARE_GLOBAL_DATA_PTR;
static __maybe_unused unsigned int get_last_capsule(void)
{
u16 value16[11]; /* "CapsuleXXXX": non-null-terminated */
- char value[11], *p;
+ char value[5];
efi_uintn_t size;
unsigned long index = 0xffff;
efi_status_t ret;
+ int i;
size = sizeof(value16);
ret = efi_get_variable_int(L"CapsuleLast", &efi_guid_capsule_report,
NULL, &size, value16, NULL);
- if (ret != EFI_SUCCESS || u16_strncmp(value16, L"Capsule", 7))
+ if (ret != EFI_SUCCESS || size != 22 ||
+ u16_strncmp(value16, L"Capsule", 7))
goto err;
+ for (i = 0; i < 4; ++i) {
+ u16 c = value16[i + 7];
- p = value;
- utf16_utf8_strcpy(&p, value16);
- strict_strtoul(&value[7], 16, &index);
+ if (!c || c > 0x7f)
+ goto err;
+ value[i] = c;
+ }
+ value[4] = 0;
+ if (strict_strtoul(value, 16, &index))
+ index = 0xffff;
err:
return index;
}
if (!tmp_size)
break;
- if (!(dirent->attribute & EFI_FILE_DIRECTORY) &&
- u16_strcmp(dirent->file_name, L".") &&
- u16_strcmp(dirent->file_name, L".."))
+ if (!(dirent->attribute & EFI_FILE_DIRECTORY))
count++;
}
cddp->partition_start, cddp->partition_size);
break;
}
+ case DEVICE_PATH_SUB_TYPE_VENDOR_PATH: {
+ int i, n;
+ struct efi_device_path_vendor *vdp =
+ (struct efi_device_path_vendor *)dp;
+
+ s += sprintf(s, "VenMedia(%pUl", &vdp->guid);
+ n = (int)vdp->dp.length - sizeof(struct efi_device_path_vendor);
+ if (n > 0) {
+ s += sprintf(s, ",");
+ for (i = 0; i < n; ++i)
+ s += sprintf(s, "%02x", vdp->vendor_data[i]);
+ }
+ s += sprintf(s, ")");
+ break;
+ }
case DEVICE_PATH_SUB_TYPE_FILE_PATH: {
struct efi_device_path_file_path *fp =
(struct efi_device_path_file_path *)dp;
if (!device_path)
goto out;
- while (device_path &&
- str + MAX_NODE_LEN < buffer + MAX_PATH_LEN) {
- *str++ = '/';
- str = efi_convert_single_device_node_to_text(str, device_path);
- device_path = efi_dp_next(device_path);
+ while (device_path && str + MAX_NODE_LEN < buffer + MAX_PATH_LEN) {
+ if (device_path->type == DEVICE_PATH_TYPE_END) {
+ if (device_path->sub_type !=
+ DEVICE_PATH_SUB_TYPE_INSTANCE_END)
+ break;
+ *str++ = ',';
+ } else {
+ *str++ = '/';
+ str = efi_convert_single_device_node_to_text(
+ str, device_path);
+ }
+ *(u8 **)&device_path += device_path->length;
}
text = efi_str_to_u16(buffer);
struct efi_system_partition efi_system_partition;
const efi_guid_t efi_block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID;
+const efi_guid_t efi_system_partition_guid = PARTITION_SYSTEM_GUID;
/**
* struct efi_disk_obj - EFI disk object
(uintptr_t)buffer & (this->media->io_align - 1))
return EFI_INVALID_PARAMETER;
if (lba * this->media->block_size + buffer_size >
- this->media->last_block * this->media->block_size)
+ (this->media->last_block + 1) * this->media->block_size)
return EFI_INVALID_PARAMETER;
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
(uintptr_t)buffer & (this->media->io_align - 1))
return EFI_INVALID_PARAMETER;
if (lba * this->media->block_size + buffer_size >
- this->media->last_block * this->media->block_size)
+ (this->media->last_block + 1) * this->media->block_size)
return EFI_INVALID_PARAMETER;
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
{
struct efi_disk_obj *diskobj;
struct efi_object *handle;
+ const efi_guid_t *guid = NULL;
efi_status_t ret;
/* Don't add empty devices */
efi_free_pool(node);
diskobj->offset = part_info->start;
diskobj->media.last_block = part_info->size - 1;
+ if (part_info->bootable & PART_EFI_SYSTEM_PARTITION)
+ guid = &efi_system_partition_guid;
} else {
diskobj->dp = efi_dp_from_part(desc, part);
diskobj->offset = 0;
handle = &diskobj->header;
ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
&handle, &efi_guid_device_path, diskobj->dp,
- &efi_block_io_guid, &diskobj->ops, NULL));
+ &efi_block_io_guid, &diskobj->ops,
+ guid, NULL, NULL));
if (ret != EFI_SUCCESS)
return ret;
/* Store first EFI system partition */
if (part && !efi_system_partition.if_type) {
- int r;
- struct disk_partition info;
-
- r = part_get_info(desc, part, &info);
- if (r)
- return EFI_DEVICE_ERROR;
- if (info.bootable & PART_EFI_SYSTEM_PARTITION) {
+ if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) {
efi_system_partition.if_type = desc->if_type;
efi_system_partition.devnum = desc->devnum;
efi_system_partition.part = part;
#include <common.h>
#include <efi_dt_fixup.h>
#include <efi_loader.h>
+#include <fdtdec.h>
#include <mapmem.h>
const efi_guid_t efi_guid_dt_fixup_protocol = EFI_DT_FIXUP_PROTOCOL_GUID;
{
efi_status_t ret;
size_t required_size;
+ size_t total_size;
bootm_headers_t img = { 0 };
EFI_ENTRY("%p, %p, %p, %d", this, dtb, buffer_size, flags);
goto out;
}
if (flags & EFI_DT_APPLY_FIXUPS) {
+ /* Check size */
required_size = fdt_off_dt_strings(dtb) +
fdt_size_dt_strings(dtb) +
0x3000;
- } else {
- required_size = fdt_totalsize(dtb);
- }
- if (required_size > *buffer_size) {
- *buffer_size = required_size;
- ret = EFI_BUFFER_TOO_SMALL;
- goto out;
- }
- fdt_set_totalsize(dtb, *buffer_size);
+ total_size = fdt_totalsize(dtb);
+ if (required_size < total_size)
+ required_size = total_size;
+ if (required_size > *buffer_size) {
+ *buffer_size = required_size;
+ ret = EFI_BUFFER_TOO_SMALL;
+ goto out;
+ }
- if (flags & EFI_DT_APPLY_FIXUPS) {
+ fdt_set_totalsize(dtb, *buffer_size);
if (image_setup_libfdt(&img, dtb, 0, NULL)) {
log_err("failed to process device tree\n");
ret = EFI_INVALID_PARAMETER;
if (flags & EFI_DT_RESERVE_MEMORY)
efi_carve_out_dt_rsv(dtb);
- if (EFI_DT_INSTALL_TABLE) {
+ if (flags & EFI_DT_INSTALL_TABLE) {
ret = efi_install_configuration_table(&efi_guid_fdt, dtb);
if (ret != EFI_SUCCESS) {
- log_err("ERROR: failed to install device tree\n");
+ log_err("failed to install device tree\n");
goto out;
}
}
#include <log.h>
#include <malloc.h>
#include <video.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
sec->Misc.VirtualSize);
memcpy(efi_reloc + sec->VirtualAddress,
efi + sec->PointerToRawData,
- sec->SizeOfRawData);
+ min(sec->Misc.VirtualSize, sec->SizeOfRawData));
}
/* Run through relocations */
#include <mapmem.h>
#include <watchdog.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <linux/list_sort.h>
#include <linux/sizes.h>
#include <efi_rng.h>
#include <log.h>
#include <rng.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <log.h>
#include <malloc.h>
#include <rtc.h>
+#include <asm/global_data.h>
#include <u-boot/crc.h>
/* For manual relocation support */
asflags-y += -DHOST_ARCH="$(HOST_ARCH)"
ccflags-y += -DHOST_ARCH="$(HOST_ARCH)"
-CFLAGS_dtbdump_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI)
CFLAGS_efi_selftest_miniapp_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI)
#include <common.h>
#include <efi_api.h>
#include <efi_dt_fixup.h>
+#include <part.h>
+#include <linux/libfdt.h>
#define BUFFER_SIZE 64
#define ESC 0x17
static struct efi_system_table *systable;
static const efi_guid_t efi_dt_fixup_protocol_guid = EFI_DT_FIXUP_PROTOCOL_GUID;
static const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID;
+static const efi_guid_t efi_system_partition_guid = PARTITION_SYSTEM_GUID;
/**
* print() - print string
}
/**
+ * open_file_system() - open simple file system protocol
+ *
+ * file_system: interface of the simple file system protocol
+ * Return: status code
+ */
+static efi_status_t
+open_file_system(struct efi_simple_file_system_protocol **file_system)
+{
+ struct efi_loaded_image *loaded_image;
+ efi_status_t ret;
+ efi_handle_t *handle_buffer = NULL;
+ efi_uintn_t count;
+
+ ret = bs->open_protocol(handle, &loaded_image_guid,
+ (void **)&loaded_image, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ error(L"Loaded image protocol not found\r\n");
+ return ret;
+ }
+
+ /* Open the simple file system protocol on the same partition */
+ ret = bs->open_protocol(loaded_image->device_handle,
+ &guid_simple_file_system_protocol,
+ (void **)file_system, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret == EFI_SUCCESS)
+ return ret;
+
+ /* Open the simple file system protocol on the UEFI system partition */
+ ret = bs->locate_handle_buffer(BY_PROTOCOL, &efi_system_partition_guid,
+ NULL, &count, &handle_buffer);
+ if (ret == EFI_SUCCESS && handle_buffer)
+ ret = bs->open_protocol(handle_buffer[0],
+ &guid_simple_file_system_protocol,
+ (void **)file_system, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS)
+ error(L"Failed to open simple file system protocol\r\n");
+ if (handle)
+ bs->free_pool(handle_buffer);
+
+ return ret;
+}
+
+/**
* do_load() - load and install device-tree
*
* @filename: file name
efi_status_t do_load(u16 *filename)
{
struct efi_dt_fixup_protocol *dt_fixup_prot;
- struct efi_loaded_image *loaded_image;
struct efi_simple_file_system_protocol *file_system;
struct efi_file_handle *root = NULL, *file = NULL;
u64 addr = 0;
filename = skip_whitespace(filename);
- ret = bs->open_protocol(handle, &loaded_image_guid,
- (void **)&loaded_image, NULL, NULL,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);
- if (ret != EFI_SUCCESS) {
- error(L"Loaded image protocol not found\r\n");
- return ret;
- }
- /* Open the simple file system protocol */
- ret = bs->open_protocol(loaded_image->device_handle,
- &guid_simple_file_system_protocol,
- (void **)&file_system, NULL, NULL,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);
- if (ret != EFI_SUCCESS) {
- error(L"Failed to open simple file system protocol\r\n");
+ ret = open_file_system(&file_system);
+ if (ret != EFI_SUCCESS)
goto out;
- }
/* Open volume */
ret = file_system->open_volume(file_system, &root);
*/
efi_status_t do_save(u16 *filename)
{
- struct efi_loaded_image *loaded_image;
struct efi_simple_file_system_protocol *file_system;
efi_uintn_t dtb_size;
struct efi_file_handle *root, *file;
filename = skip_whitespace(filename);
- ret = bs->open_protocol(handle, &loaded_image_guid,
- (void **)&loaded_image, NULL, NULL,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);
- if (ret != EFI_SUCCESS) {
- error(L"Loaded image protocol not found\r\n");
- return ret;
- }
-
- /* Open the simple file system protocol */
- ret = bs->open_protocol(loaded_image->device_handle,
- &guid_simple_file_system_protocol,
- (void **)&file_system, NULL, NULL,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);
- if (ret != EFI_SUCCESS) {
- error(L"Failed to open simple file system protocol\r\n");
+ ret = open_file_system(&file_system);
+ if (ret != EFI_SUCCESS)
return ret;
- }
/* Open volume */
ret = file_system->open_volume(file_system, &root);
static u8 *dp2;
static u8 *dp3;
+static struct {
+ struct efi_device_path_sd_mmc_path sd1;
+ struct efi_device_path sep1;
+ struct efi_device_path_sd_mmc_path sd2;
+ struct efi_device_path sep2;
+ struct efi_device_path_sd_mmc_path sd3;
+ struct efi_device_path end;
+} multi_part_dp = {
+ {
+ {
+ DEVICE_PATH_TYPE_MESSAGING_DEVICE,
+ DEVICE_PATH_SUB_TYPE_MSG_SD,
+ sizeof(struct efi_device_path_sd_mmc_path),
+ },
+ 0,
+ },
+ {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_INSTANCE_END,
+ sizeof(struct efi_device_path),
+ },
+ {
+ {
+ DEVICE_PATH_TYPE_MESSAGING_DEVICE,
+ DEVICE_PATH_SUB_TYPE_MSG_SD,
+ sizeof(struct efi_device_path_sd_mmc_path),
+ },
+ 1,
+ },
+ {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_INSTANCE_END,
+ sizeof(struct efi_device_path),
+ },
+ {
+ {
+ DEVICE_PATH_TYPE_MESSAGING_DEVICE,
+ DEVICE_PATH_SUB_TYPE_MSG_SD,
+ sizeof(struct efi_device_path_sd_mmc_path),
+ },
+ 2,
+ },
+ {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_END,
+ sizeof(struct efi_device_path),
+ },
+};
+
struct efi_device_path_to_text_protocol *device_path_to_text;
/*
return EFI_ST_FAILURE;
}
+ string = device_path_to_text->convert_device_path_to_text(
+ (struct efi_device_path *)&multi_part_dp, true, false);
+ if (efi_st_strcmp_16_8(
+ string,
+ "/SD(0),/SD(1),/SD(2)")
+ ) {
+ efi_st_printf("multi_part_dp: %ps\n", string);
+ efi_st_error("Incorrect text from ConvertDevicePathToText\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+
/* Test ConvertDeviceNodeToText */
string = device_path_to_text->convert_device_node_to_text(
(struct efi_device_path *)&dp_node, true, false);
#include <mapmem.h>
#include <linux/libfdt.h>
#include <serial.h>
+#include <asm/global_data.h>
#include <asm/sections.h>
#include <linux/ctype.h>
#include <linux/lzo.h>
void *fdt_blob = NULL;
#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
- if (CONFIG_IS_ENABLED(SEPARATE_BSS))
+ if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
fdt_blob = (ulong *)&_image_binary_end;
else
fdt_blob = (ulong *)&__bss_end;
return -1;
}
# elif defined(CONFIG_OF_PRIOR_STAGE)
- gd->fdt_blob = (void *)prior_stage_fdt_address;
+ gd->fdt_blob = (void *)(uintptr_t)prior_stage_fdt_address;
# endif
# ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
*/
#include <common.h>
+#include <fdtdec.h>
#include <image.h>
#include <log.h>
#include <malloc.h>
#include <env.h>
#include <mapmem.h>
#include <smbios.h>
+#include <sysinfo.h>
#include <tables_csum.h>
#include <version.h>
#ifdef CONFIG_CPU
#include <dm/uclass-internal.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ SMBIOS_STR_MAX = 64, /* Maximum length allowed for a string */
+};
+
+/**
+ * struct smbios_ctx - context for writing SMBIOS tables
+ *
+ * @node: node containing the information to write (ofnode_null() if none)
+ * @dev: sysinfo device to use (NULL if none)
+ * @eos: end-of-string pointer for the table being processed. This is set
+ * up when we start processing a table
+ * @next_ptr: pointer to the start of the next string to be added. When the
+ * table is nopt empty, this points to the byte after the \0 of the
+ * previous string.
+ * @last_str: points to the last string that was written to the table, or NULL
+ * if none
+ */
+struct smbios_ctx {
+ ofnode node;
+ struct udevice *dev;
+ char *eos;
+ char *next_ptr;
+ char *last_str;
+};
+
+/**
+ * Function prototype to write a specific type of SMBIOS structure
+ *
+ * @addr: start address to write the structure
+ * @handle: the structure's handle, a unique 16-bit number
+ * @ctx: context for writing the tables
+ * @return: size of the structure
+ */
+typedef int (*smbios_write_type)(ulong *addr, int handle,
+ struct smbios_ctx *ctx);
+
/**
* struct smbios_write_method - Information about a table-writing function
*
* This adds a string to the string area which is appended directly after
* the formatted portion of an SMBIOS structure.
*
- * @start: string area start address
+ * @ctx: SMBIOS context
* @str: string to add
* @return: string number in the string area (1 or more)
*/
-static int smbios_add_string(char *start, const char *str)
+static int smbios_add_string(struct smbios_ctx *ctx, const char *str)
{
int i = 1;
- char *p = start;
+ char *p = ctx->eos;
+
if (!*str)
str = "Unknown";
for (;;) {
if (!*p) {
+ ctx->last_str = p;
strcpy(p, str);
p += strlen(str);
*p++ = '\0';
+ ctx->next_ptr = p;
*p++ = '\0';
return i;
}
- if (!strcmp(p, str))
+ if (!strcmp(p, str)) {
+ ctx->last_str = p;
return i;
+ }
p += strlen(p) + 1;
i++;
}
/**
- * smbios_add_prop() - Add a property from the device tree
+ * smbios_add_prop_si() - Add a property from the devicetree or sysinfo
*
- * @start: string area start address
- * @node: node containing the information to write (ofnode_null() if none)
+ * Sysinfo is used if available, with a fallback to devicetree
+ *
+ * @ctx: context for writing the tables
* @prop: property to write
* @return 0 if not found, else SMBIOS string number (1 or more)
*/
-static int smbios_add_prop(char *start, ofnode node, const char *prop)
+static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop,
+ int sysinfo_id)
{
+ if (sysinfo_id && ctx->dev) {
+ char val[SMBIOS_STR_MAX];
+ int ret;
+ ret = sysinfo_get_str(ctx->dev, sysinfo_id, sizeof(val), val);
+ if (!ret)
+ return smbios_add_string(ctx, val);
+ }
if (IS_ENABLED(CONFIG_OF_CONTROL)) {
const char *str;
- str = ofnode_read_string(node, prop);
+ str = ofnode_read_string(ctx->node, prop);
if (str)
- return smbios_add_string(start, str);
+ return smbios_add_string(ctx, str);
}
return 0;
}
/**
+ * smbios_add_prop() - Add a property from the devicetree
+ *
+ * @prop: property to write
+ * @return 0 if not found, else SMBIOS string number (1 or more)
+ */
+static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop)
+{
+ return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE);
+}
+
+static void smbios_set_eos(struct smbios_ctx *ctx, char *eos)
+{
+ ctx->eos = eos;
+ ctx->next_ptr = eos;
+ ctx->last_str = NULL;
+}
+
+int smbios_update_version(const char *version)
+{
+ char *ptr = gd->smbios_version;
+ uint old_len, len;
+
+ if (!ptr)
+ return log_ret(-ENOENT);
+
+ /*
+ * This string is supposed to have at least enough bytes and is
+ * padded with spaces. Update it, taking care not to move the
+ * \0 terminator, so that other strings in the string table
+ * are not disturbed. See smbios_add_string()
+ */
+ old_len = strnlen(ptr, SMBIOS_STR_MAX);
+ len = strnlen(version, SMBIOS_STR_MAX);
+ if (len > old_len)
+ return log_ret(-ENOSPC);
+
+ log_debug("Replacing SMBIOS type 0 version string '%s'\n", ptr);
+ memcpy(ptr, version, len);
+#ifdef LOG_DEBUG
+ print_buffer((ulong)ptr, ptr, 1, old_len + 1, 0);
+#endif
+
+ return 0;
+}
+
+/**
* smbios_string_table_len() - compute the string area size
*
* This computes the size of the string area including the string terminator.
*
- * @start: string area start address
+ * @ctx: SMBIOS context
* @return: string area size
*/
-static int smbios_string_table_len(char *start)
+static int smbios_string_table_len(const struct smbios_ctx *ctx)
{
- char *p = start;
- int i, len = 0;
-
- while (*p) {
- i = strlen(p) + 1;
- p += i;
- len += i;
- }
-
- return len + 1;
+ /* Allow for the final \0 after all strings */
+ return (ctx->next_ptr + 1) - ctx->eos;
}
-static int smbios_write_type0(ulong *current, int handle, ofnode node)
+static int smbios_write_type0(ulong *current, int handle,
+ struct smbios_ctx *ctx)
{
struct smbios_type0 *t;
int len = sizeof(struct smbios_type0);
t = map_sysmem(*current, len);
memset(t, 0, sizeof(struct smbios_type0));
fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle);
- t->vendor = smbios_add_string(t->eos, "U-Boot");
- t->bios_ver = smbios_add_string(t->eos, PLAIN_VERSION);
- t->bios_release_date = smbios_add_string(t->eos, U_BOOT_DMI_DATE);
+ smbios_set_eos(ctx, t->eos);
+ t->vendor = smbios_add_string(ctx, "U-Boot");
+
+ t->bios_ver = smbios_add_prop(ctx, "version");
+ if (!t->bios_ver)
+ t->bios_ver = smbios_add_string(ctx, PLAIN_VERSION);
+ if (t->bios_ver)
+ gd->smbios_version = ctx->last_str;
+ log_debug("smbios_version = %p: '%s'\n", gd->smbios_version,
+ gd->smbios_version);
+#ifdef LOG_DEBUG
+ print_buffer((ulong)gd->smbios_version, gd->smbios_version,
+ 1, strlen(gd->smbios_version) + 1, 0);
+#endif
+ t->bios_release_date = smbios_add_string(ctx, U_BOOT_DMI_DATE);
#ifdef CONFIG_ROM_SIZE
t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1;
#endif
#endif
t->bios_characteristics_ext2 = BIOS_CHARACTERISTICS_EXT2_TARGET;
- t->bios_major_release = 0xff;
- t->bios_minor_release = 0xff;
+ /* bios_major_release has only one byte, so drop century */
+ t->bios_major_release = U_BOOT_VERSION_NUM % 100;
+ t->bios_minor_release = U_BOOT_VERSION_NUM_PATCH;
t->ec_major_release = 0xff;
t->ec_minor_release = 0xff;
- len = t->length + smbios_string_table_len(t->eos);
+ len = t->length + smbios_string_table_len(ctx);
*current += len;
unmap_sysmem(t);
return len;
}
-static int smbios_write_type1(ulong *current, int handle, ofnode node)
+static int smbios_write_type1(ulong *current, int handle,
+ struct smbios_ctx *ctx)
{
struct smbios_type1 *t;
int len = sizeof(struct smbios_type1);
t = map_sysmem(*current, len);
memset(t, 0, sizeof(struct smbios_type1));
fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
- t->manufacturer = smbios_add_prop(t->eos, node, "manufacturer");
- t->product_name = smbios_add_prop(t->eos, node, "product");
- t->version = smbios_add_prop(t->eos, node, "version");
+ smbios_set_eos(ctx, t->eos);
+ t->manufacturer = smbios_add_prop(ctx, "manufacturer");
+ t->product_name = smbios_add_prop(ctx, "product");
+ t->version = smbios_add_prop_si(ctx, "version",
+ SYSINFO_ID_SMBIOS_SYSTEM_VERSION);
if (serial_str) {
- t->serial_number = smbios_add_string(t->eos, serial_str);
+ t->serial_number = smbios_add_string(ctx, serial_str);
strncpy((char *)t->uuid, serial_str, sizeof(t->uuid));
} else {
- t->serial_number = smbios_add_prop(t->eos, node, "serial");
+ t->serial_number = smbios_add_prop(ctx, "serial");
}
- t->sku_number = smbios_add_prop(t->eos, node, "sku");
- t->family = smbios_add_prop(t->eos, node, "family");
+ t->sku_number = smbios_add_prop(ctx, "sku");
+ t->family = smbios_add_prop(ctx, "family");
- len = t->length + smbios_string_table_len(t->eos);
+ len = t->length + smbios_string_table_len(ctx);
*current += len;
unmap_sysmem(t);
return len;
}
-static int smbios_write_type2(ulong *current, int handle, ofnode node)
+static int smbios_write_type2(ulong *current, int handle,
+ struct smbios_ctx *ctx)
{
struct smbios_type2 *t;
int len = sizeof(struct smbios_type2);
t = map_sysmem(*current, len);
memset(t, 0, sizeof(struct smbios_type2));
fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
- t->manufacturer = smbios_add_prop(t->eos, node, "manufacturer");
- t->product_name = smbios_add_prop(t->eos, node, "product");
- t->asset_tag_number = smbios_add_prop(t->eos, node, "asset-tag");
+ smbios_set_eos(ctx, t->eos);
+ t->manufacturer = smbios_add_prop(ctx, "manufacturer");
+ t->product_name = smbios_add_prop(ctx, "product");
+ t->version = smbios_add_prop_si(ctx, "version",
+ SYSINFO_ID_SMBIOS_BASEBOARD_VERSION);
+ t->asset_tag_number = smbios_add_prop(ctx, "asset-tag");
t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
t->board_type = SMBIOS_BOARD_MOTHERBOARD;
- len = t->length + smbios_string_table_len(t->eos);
+ len = t->length + smbios_string_table_len(ctx);
*current += len;
unmap_sysmem(t);
return len;
}
-static int smbios_write_type3(ulong *current, int handle, ofnode node)
+static int smbios_write_type3(ulong *current, int handle,
+ struct smbios_ctx *ctx)
{
struct smbios_type3 *t;
int len = sizeof(struct smbios_type3);
t = map_sysmem(*current, len);
memset(t, 0, sizeof(struct smbios_type3));
fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
- t->manufacturer = smbios_add_prop(t->eos, node, "manufacturer");
+ smbios_set_eos(ctx, t->eos);
+ t->manufacturer = smbios_add_prop(ctx, "manufacturer");
t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
t->bootup_state = SMBIOS_STATE_SAFE;
t->power_supply_state = SMBIOS_STATE_SAFE;
t->thermal_state = SMBIOS_STATE_SAFE;
t->security_status = SMBIOS_SECURITY_NONE;
- len = t->length + smbios_string_table_len(t->eos);
+ len = t->length + smbios_string_table_len(ctx);
*current += len;
unmap_sysmem(t);
return len;
}
-static void smbios_write_type4_dm(struct smbios_type4 *t, ofnode node)
+static void smbios_write_type4_dm(struct smbios_type4 *t,
+ struct smbios_ctx *ctx)
{
u16 processor_family = SMBIOS_PROCESSOR_FAMILY_UNKNOWN;
const char *vendor = "Unknown";
#endif
t->processor_family = processor_family;
- t->processor_manufacturer = smbios_add_string(t->eos, vendor);
- t->processor_version = smbios_add_string(t->eos, name);
+ t->processor_manufacturer = smbios_add_string(ctx, vendor);
+ t->processor_version = smbios_add_string(ctx, name);
}
-static int smbios_write_type4(ulong *current, int handle, ofnode node)
+static int smbios_write_type4(ulong *current, int handle,
+ struct smbios_ctx *ctx)
{
struct smbios_type4 *t;
int len = sizeof(struct smbios_type4);
t = map_sysmem(*current, len);
memset(t, 0, sizeof(struct smbios_type4));
fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, handle);
+ smbios_set_eos(ctx, t->eos);
t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
- smbios_write_type4_dm(t, node);
+ smbios_write_type4_dm(t, ctx);
t->status = SMBIOS_PROCESSOR_STATUS_ENABLED;
t->processor_upgrade = SMBIOS_PROCESSOR_UPGRADE_NONE;
t->l1_cache_handle = 0xffff;
t->l3_cache_handle = 0xffff;
t->processor_family2 = t->processor_family;
- len = t->length + smbios_string_table_len(t->eos);
+ len = t->length + smbios_string_table_len(ctx);
*current += len;
unmap_sysmem(t);
return len;
}
-static int smbios_write_type32(ulong *current, int handle, ofnode node)
+static int smbios_write_type32(ulong *current, int handle,
+ struct smbios_ctx *ctx)
{
struct smbios_type32 *t;
int len = sizeof(struct smbios_type32);
t = map_sysmem(*current, len);
memset(t, 0, sizeof(struct smbios_type32));
fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, handle);
+ smbios_set_eos(ctx, t->eos);
*current += len;
unmap_sysmem(t);
return len;
}
-static int smbios_write_type127(ulong *current, int handle, ofnode node)
+static int smbios_write_type127(ulong *current, int handle,
+ struct smbios_ctx *ctx)
{
struct smbios_type127 *t;
int len = sizeof(struct smbios_type127);
}
static struct smbios_write_method smbios_write_funcs[] = {
- { smbios_write_type0, },
+ { smbios_write_type0, "bios", },
{ smbios_write_type1, "system", },
{ smbios_write_type2, "baseboard", },
{ smbios_write_type3, "chassis", },
{
ofnode parent_node = ofnode_null();
struct smbios_entry *se;
- struct udevice *dev;
+ struct smbios_ctx ctx;
ulong table_addr;
ulong tables;
int len = 0;
int isize;
int i;
+ ctx.node = ofnode_null();
if (IS_ENABLED(CONFIG_OF_CONTROL)) {
- uclass_first_device(UCLASS_SYSINFO, &dev);
- if (dev)
- parent_node = dev_read_subnode(dev, "smbios");
+ uclass_first_device(UCLASS_SYSINFO, &ctx.dev);
+ if (ctx.dev)
+ parent_node = dev_read_subnode(ctx.dev, "smbios");
+ } else {
+ ctx.dev = NULL;
}
/* 16 byte align the table address */
/* populate minimum required tables */
for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) {
const struct smbios_write_method *method;
- ofnode node = ofnode_null();
int tmp;
method = &smbios_write_funcs[i];
if (IS_ENABLED(CONFIG_OF_CONTROL) && method->subnode_name)
- node = ofnode_find_subnode(parent_node,
- method->subnode_name);
- tmp = method->write((ulong *)&addr, handle++, node);
+ ctx.node = ofnode_find_subnode(parent_node,
+ method->subnode_name);
+ tmp = method->write((ulong *)&addr, handle++, &ctx);
max_struct_size = max(max_struct_size, tmp);
len += tmp;
#include <timer.h>
#include <watchdog.h>
#include <div64.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <mapmem.h>
#include <time.h>
#include <trace.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/sections.h>
* - added inflateIncomp
*/
-#include <common.h>
+#include <compiler.h>
#ifdef CONFIG_GZIP_COMPRESSED
#define NO_DUMMY_DECL
obj-$(CONFIG_CMD_BOOTP) += bootp.o
obj-$(CONFIG_CMD_CDP) += cdp.o
obj-$(CONFIG_CMD_DNS) += dns.o
+obj-$(CONFIG_DM_DSA) += dsa-uclass.o
ifdef CONFIG_DM_ETH
obj-$(CONFIG_NET) += eth-uclass.o
else
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+#include <net/dsa.h>
+#include <dm/lists.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <linux/bitmap.h>
+#include <miiphy.h>
+
+#define DSA_PORT_CHILD_DRV_NAME "dsa-port"
+
+/* per-device internal state structure */
+struct dsa_priv {
+ struct phy_device *cpu_port_fixed_phy;
+ struct udevice *master_dev;
+ int num_ports;
+ u32 cpu_port;
+ int headroom;
+ int tailroom;
+};
+
+/* external API */
+int dsa_set_tagging(struct udevice *dev, ushort headroom, ushort tailroom)
+{
+ struct dsa_priv *priv;
+
+ if (!dev || !dev_get_uclass_priv(dev))
+ return -ENODEV;
+
+ if (headroom + tailroom > DSA_MAX_OVR)
+ return -EINVAL;
+
+ priv = dev_get_uclass_priv(dev);
+
+ if (headroom > 0)
+ priv->headroom = headroom;
+ if (tailroom > 0)
+ priv->tailroom = tailroom;
+
+ return 0;
+}
+
+/* returns the DSA master Ethernet device */
+struct udevice *dsa_get_master(struct udevice *dev)
+{
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+
+ if (!priv)
+ return NULL;
+
+ return priv->master_dev;
+}
+
+/*
+ * Start the desired port, the CPU port and the master Eth interface.
+ * TODO: if cascaded we may need to _start ports in other switches too
+ */
+static int dsa_port_start(struct udevice *pdev)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+ struct udevice *master = dsa_get_master(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+ int err;
+
+ if (!priv)
+ return -ENODEV;
+
+ if (!master) {
+ dev_err(pdev, "DSA master Ethernet device not found!\n");
+ return -EINVAL;
+ }
+
+ if (ops->port_enable) {
+ struct dsa_port_pdata *port_pdata;
+
+ port_pdata = dev_get_parent_plat(pdev);
+ err = ops->port_enable(dev, port_pdata->index,
+ port_pdata->phy);
+ if (err)
+ return err;
+
+ err = ops->port_enable(dev, priv->cpu_port,
+ priv->cpu_port_fixed_phy);
+ if (err)
+ return err;
+ }
+
+ return eth_get_ops(master)->start(master);
+}
+
+/* Stop the desired port, the CPU port and the master Eth interface */
+static void dsa_port_stop(struct udevice *pdev)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+ struct udevice *master = dsa_get_master(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+
+ if (!priv)
+ return;
+
+ if (ops->port_disable) {
+ struct dsa_port_pdata *port_pdata;
+
+ port_pdata = dev_get_parent_plat(pdev);
+ ops->port_disable(dev, port_pdata->index, port_pdata->phy);
+ ops->port_disable(dev, priv->cpu_port, NULL);
+ }
+
+ /*
+ * stop master only if it's active, don't probe it otherwise.
+ * Under normal usage it would be active because we're using it, but
+ * during tear-down it may have been removed ahead of us.
+ */
+ if (master && device_active(master))
+ eth_get_ops(master)->stop(master);
+}
+
+/*
+ * Insert a DSA tag and call master Ethernet send on the resulting packet
+ * We copy the frame to a stack buffer where we have reserved headroom and
+ * tailroom space. Headroom and tailroom are set to 0.
+ */
+static int dsa_port_send(struct udevice *pdev, void *packet, int length)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+ int head = priv->headroom, tail = priv->tailroom;
+ struct udevice *master = dsa_get_master(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+ uchar dsa_packet_tmp[PKTSIZE_ALIGN];
+ struct dsa_port_pdata *port_pdata;
+ int err;
+
+ if (!master)
+ return -EINVAL;
+
+ if (length + head + tail > PKTSIZE_ALIGN)
+ return -EINVAL;
+
+ memset(dsa_packet_tmp, 0, head);
+ memset(dsa_packet_tmp + head + length, 0, tail);
+ memcpy(dsa_packet_tmp + head, packet, length);
+ length += head + tail;
+ /* copy back to preserve original buffer alignment */
+ memcpy(packet, dsa_packet_tmp, length);
+
+ port_pdata = dev_get_parent_plat(pdev);
+ err = ops->xmit(dev, port_pdata->index, packet, length);
+ if (err)
+ return err;
+
+ return eth_get_ops(master)->send(master, packet, length);
+}
+
+/* Receive a frame from master Ethernet, process it and pass it on */
+static int dsa_port_recv(struct udevice *pdev, int flags, uchar **packetp)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+ int head = priv->headroom, tail = priv->tailroom;
+ struct udevice *master = dsa_get_master(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+ struct dsa_port_pdata *port_pdata;
+ int length, port_index, err;
+
+ if (!master)
+ return -EINVAL;
+
+ length = eth_get_ops(master)->recv(master, flags, packetp);
+ if (length <= 0)
+ return length;
+
+ /*
+ * If we receive frames from a different port or frames that DSA driver
+ * doesn't like we discard them here.
+ * In case of discard we return with no frame and expect to be called
+ * again instead of looping here, so upper layer can deal with timeouts.
+ */
+ port_pdata = dev_get_parent_plat(pdev);
+ err = ops->rcv(dev, &port_index, *packetp, length);
+ if (err || port_index != port_pdata->index || (length <= head + tail)) {
+ if (eth_get_ops(master)->free_pkt)
+ eth_get_ops(master)->free_pkt(master, *packetp, length);
+ return -EAGAIN;
+ }
+
+ /*
+ * We move the pointer over headroom here to avoid a copy. If free_pkt
+ * gets called we move the pointer back before calling master free_pkt.
+ */
+ *packetp += head;
+
+ return length - head - tail;
+}
+
+static int dsa_port_free_pkt(struct udevice *pdev, uchar *packet, int length)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct udevice *master = dsa_get_master(dev);
+ struct dsa_priv *priv;
+
+ if (!master)
+ return -EINVAL;
+
+ priv = dev_get_uclass_priv(dev);
+ if (eth_get_ops(master)->free_pkt) {
+ /* return the original pointer and length to master Eth */
+ packet -= priv->headroom;
+ length += priv->headroom - priv->tailroom;
+
+ return eth_get_ops(master)->free_pkt(master, packet, length);
+ }
+
+ return 0;
+}
+
+static int dsa_port_of_to_pdata(struct udevice *pdev)
+{
+ struct dsa_port_pdata *port_pdata;
+ struct dsa_pdata *dsa_pdata;
+ struct eth_pdata *eth_pdata;
+ struct udevice *dev;
+ const char *label;
+ u32 index;
+ int err;
+
+ if (!pdev)
+ return -ENODEV;
+
+ err = ofnode_read_u32(dev_ofnode(pdev), "reg", &index);
+ if (err)
+ return err;
+
+ dev = dev_get_parent(pdev);
+ dsa_pdata = dev_get_uclass_plat(dev);
+
+ port_pdata = dev_get_parent_plat(pdev);
+ port_pdata->index = index;
+
+ label = ofnode_read_string(dev_ofnode(pdev), "label");
+ if (label)
+ strncpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH);
+
+ eth_pdata = dev_get_plat(pdev);
+ eth_pdata->priv_pdata = port_pdata;
+
+ dev_dbg(pdev, "port %d node %s\n", port_pdata->index,
+ ofnode_get_name(dev_ofnode(pdev)));
+
+ return 0;
+}
+
+static const struct eth_ops dsa_port_ops = {
+ .start = dsa_port_start,
+ .send = dsa_port_send,
+ .recv = dsa_port_recv,
+ .stop = dsa_port_stop,
+ .free_pkt = dsa_port_free_pkt,
+};
+
+static int dsa_port_probe(struct udevice *pdev)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct eth_pdata *eth_pdata, *master_pdata;
+ unsigned char env_enetaddr[ARP_HLEN];
+ struct dsa_port_pdata *port_pdata;
+ struct dsa_priv *dsa_priv;
+ struct udevice *master;
+
+ port_pdata = dev_get_parent_plat(pdev);
+ dsa_priv = dev_get_uclass_priv(dev);
+
+ port_pdata->phy = dm_eth_phy_connect(pdev);
+ if (!port_pdata->phy)
+ return -ENODEV;
+
+ /*
+ * Inherit port's hwaddr from the DSA master, unless the port already
+ * has a unique MAC address specified in the environment.
+ */
+ eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
+ if (!is_zero_ethaddr(env_enetaddr))
+ return 0;
+
+ master = dsa_get_master(dev);
+ if (!master)
+ return 0;
+
+ master_pdata = dev_get_plat(master);
+ eth_pdata = dev_get_plat(pdev);
+ memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
+ eth_env_set_enetaddr_by_index("eth", dev_seq(pdev),
+ master_pdata->enetaddr);
+
+ return 0;
+}
+
+static int dsa_port_remove(struct udevice *pdev)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct dsa_port_pdata *port_pdata;
+ struct dsa_priv *dsa_priv;
+
+ port_pdata = dev_get_parent_plat(pdev);
+ dsa_priv = dev_get_uclass_priv(dev);
+
+ port_pdata->phy = NULL;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(dsa_port) = {
+ .name = DSA_PORT_CHILD_DRV_NAME,
+ .id = UCLASS_ETH,
+ .ops = &dsa_port_ops,
+ .probe = dsa_port_probe,
+ .remove = dsa_port_remove,
+ .of_to_plat = dsa_port_of_to_pdata,
+ .plat_auto = sizeof(struct eth_pdata),
+};
+
+/*
+ * This function mostly deals with pulling information out of the device tree
+ * into the pdata structure.
+ * It goes through the list of switch ports, registers an eth device for each
+ * front panel port and identifies the cpu port connected to master eth device.
+ * TODO: support cascaded switches
+ */
+static int dsa_post_bind(struct udevice *dev)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ ofnode node = dev_ofnode(dev), pnode;
+ int i, err, first_err = 0;
+
+ if (!pdata || !ofnode_valid(node))
+ return -ENODEV;
+
+ pdata->master_node = ofnode_null();
+
+ node = ofnode_find_subnode(node, "ports");
+ if (!ofnode_valid(node))
+ node = ofnode_find_subnode(node, "ethernet-ports");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "ports node is missing under DSA device!\n");
+ return -EINVAL;
+ }
+
+ pdata->num_ports = ofnode_get_child_count(node);
+ if (pdata->num_ports <= 0 || pdata->num_ports > DSA_MAX_PORTS) {
+ dev_err(dev, "invalid number of ports (%d)\n",
+ pdata->num_ports);
+ return -EINVAL;
+ }
+
+ /* look for the CPU port */
+ ofnode_for_each_subnode(pnode, node) {
+ u32 ethernet;
+
+ if (ofnode_read_u32(pnode, "ethernet", ðernet))
+ continue;
+
+ pdata->master_node = ofnode_get_by_phandle(ethernet);
+ pdata->cpu_port_node = pnode;
+ break;
+ }
+
+ if (!ofnode_valid(pdata->master_node)) {
+ dev_err(dev, "master eth node missing!\n");
+ return -EINVAL;
+ }
+
+ if (ofnode_read_u32(pnode, "reg", &pdata->cpu_port)) {
+ dev_err(dev, "CPU port node not valid!\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "master node %s on port %d\n",
+ ofnode_get_name(pdata->master_node), pdata->cpu_port);
+
+ for (i = 0; i < pdata->num_ports; i++) {
+ char name[DSA_PORT_NAME_LENGTH];
+ struct udevice *pdev;
+
+ /*
+ * If this is the CPU port don't register it as an ETH device,
+ * we skip it on purpose since I/O to/from it from the CPU
+ * isn't useful.
+ */
+ if (i == pdata->cpu_port)
+ continue;
+
+ /*
+ * Set up default port names. If present, DT port labels
+ * will override the default port names.
+ */
+ snprintf(name, DSA_PORT_NAME_LENGTH, "%s@%d", dev->name, i);
+
+ ofnode_for_each_subnode(pnode, node) {
+ u32 reg;
+
+ if (ofnode_read_u32(pnode, "reg", ®))
+ continue;
+
+ if (reg == i)
+ break;
+ }
+
+ /*
+ * skip registration if port id not found or if the port
+ * is explicitly disabled in DT
+ */
+ if (!ofnode_valid(pnode) || !ofnode_is_available(pnode))
+ continue;
+
+ err = device_bind_driver_to_node(dev, DSA_PORT_CHILD_DRV_NAME,
+ name, pnode, &pdev);
+ if (pdev) {
+ struct dsa_port_pdata *port_pdata;
+
+ port_pdata = dev_get_parent_plat(pdev);
+ strncpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH);
+ pdev->name = port_pdata->name;
+ }
+
+ /* try to bind all ports but keep 1st error */
+ if (err && !first_err)
+ first_err = err;
+ }
+
+ if (first_err)
+ return first_err;
+
+ dev_dbg(dev, "DSA ports successfully bound\n");
+
+ return 0;
+}
+
+/**
+ * Initialize the uclass per device internal state structure (priv).
+ * TODO: pick up references to other switch devices here, if we're cascaded.
+ */
+static int dsa_pre_probe(struct udevice *dev)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+
+ if (!pdata || !priv)
+ return -ENODEV;
+
+ priv->num_ports = pdata->num_ports;
+ priv->cpu_port = pdata->cpu_port;
+ priv->cpu_port_fixed_phy = fixed_phy_create(pdata->cpu_port_node);
+ if (!priv->cpu_port_fixed_phy) {
+ dev_err(dev, "Failed to register fixed-link for CPU port\n");
+ return -ENODEV;
+ }
+
+ uclass_find_device_by_ofnode(UCLASS_ETH, pdata->master_node,
+ &priv->master_dev);
+ return 0;
+}
+
+UCLASS_DRIVER(dsa) = {
+ .id = UCLASS_DSA,
+ .name = "dsa",
+ .post_bind = dsa_post_bind,
+ .pre_probe = dsa_pre_probe,
+ .per_device_auto = sizeof(struct dsa_priv),
+ .per_device_plat_auto = sizeof(struct dsa_pdata),
+ .per_child_plat_auto = sizeof(struct dsa_port_pdata),
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
#include <env.h>
#include <log.h>
#include <net.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <net/pcap.h>
#include <log.h>
#include <net.h>
#include <phy.h>
+#include <asm/global_data.h>
#include <linux/bug.h>
#include <linux/errno.h>
#include <net/pcap.h>
struct ofnode_phandle_args phandle = {.node = ofnode_null()};
int i;
+ if (CONFIG_IS_ENABLED(PHY_FIXED) &&
+ ofnode_valid(dev_read_subnode(ethdev, "fixed-link"))) {
+ phy = phy_connect(NULL, -1, ethdev, interface);
+ goto out;
+ }
+
for (i = 0; i < PHY_HANDLE_STR_CNT; i++)
if (!dev_read_phandle_with_args(ethdev, phy_handle_str[i], NULL,
0, 0, &phandle))
phy = dm_mdio_phy_connect(mdiodev, phy_addr, ethdev, interface);
+out:
if (phy)
phy->node = phandle.node;
#include <log.h>
#include <mapmem.h>
#include <net.h>
+#include <asm/global_data.h>
#include <net/tftp.h>
#include "bootp.h"
#ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
break;
}
+ if (len < tftp_block_size) {
+ tftp_send();
+ tftp_complete();
+ break;
+ }
+
/*
* Acknowledge the block just received, which will prompt
* the remote for the next one.
tftp_send();
tftp_next_ack += tftp_windowsize;
}
-
- if (len < tftp_block_size) {
- tftp_send();
- tftp_complete();
- }
break;
case TFTP_ERROR:
#include <common.h>
#include <log.h>
+#include <asm/global_data.h>
/* Memory test
*
#include <watchdog.h>
#include <div64.h>
#include <post.h>
+#include <asm/global_data.h>
#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO
#include <asm/gpio.h>
CONFIG_AT91_LED
CONFIG_AT91_WANTS_COMMON_PHY
CONFIG_ATAPI
-CONFIG_ATI_RADEON_FB
CONFIG_ATM
CONFIG_ATMEL_LCD
CONFIG_ATMEL_LCD_BGR555
CONFIG_CPU_PXA26X
CONFIG_CPU_PXA27X
CONFIG_CPU_PXA300
-CONFIG_CPU_SH7722
CONFIG_CPU_SH7751
-CONFIG_CPU_SH7752
-CONFIG_CPU_SH7753
-CONFIG_CPU_SH7757
-CONFIG_CPU_SH7763
-CONFIG_CPU_SH7780
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
CONFIG_CQSPI_REF_CLK
CONFIG_DRIVER_AT91EMAC
CONFIG_DRIVER_AT91EMAC_PHYADDR
CONFIG_DRIVER_AT91EMAC_QUIET
-CONFIG_DRIVER_AX88796L
CONFIG_DRIVER_DM9000
CONFIG_DRIVER_EP93XX_MAC
CONFIG_DRIVER_NE2000
CONFIG_FSL_IIM
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_LBC
-CONFIG_FSL_MC9SDZ60
CONFIG_FSL_MEMAC
CONFIG_FSL_NGPIXIS
CONFIG_FSL_PCI_INIT
-CONFIG_FSL_PIXIS
CONFIG_FSL_PMIC_BITLEN
CONFIG_FSL_PMIC_BUS
CONFIG_FSL_PMIC_CLK
CONFIG_ODROID_REV_AIN
CONFIG_OFF_PADCONF
CONFIG_OF_
-CONFIG_OF_STDOUT_PATH
CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI
CONFIG_QUOTA
-CONFIG_R7780MP
CONFIG_RAMBOOT
CONFIG_RAMBOOTCOMMAND
CONFIG_RAMBOOT_NAND
CONFIG_RAMDISKFILE
CONFIG_RAMDISK_ADDR
CONFIG_RAMDISK_BOOT
-CONFIG_RAM_BOOT
-CONFIG_RAM_BOOT_PHYS
CONFIG_RD_LVL
CONFIG_REALMODE_DEBUG
CONFIG_RED_LED
CONFIG_SET_DFU_ALT_BUF_LEN
CONFIG_SFIO
CONFIG_SGI_IP28
-CONFIG_SH4_PCI
CONFIG_SH73A0
CONFIG_SH7751_PCI
-CONFIG_SH7757LCR_DDR_ECC
-CONFIG_SH7780_PCI
-CONFIG_SH7780_PCI_BAR
-CONFIG_SH7780_PCI_LAR
-CONFIG_SH7780_PCI_LSR
CONFIG_SHARP_LM8V31
CONFIG_SHARP_LQ035Q7DH06
CONFIG_SHEEVA_88SV131
CONFIG_SH_ETHER_PHY_ADDR
CONFIG_SH_ETHER_PHY_MODE
CONFIG_SH_ETHER_SH7734_MII
-CONFIG_SH_ETHER_USE_GETHER
CONFIG_SH_ETHER_USE_PORT
CONFIG_SH_GPIO_PFC
CONFIG_SH_I2C_8BIT
CONFIG_SH_I2C_CLOCK
CONFIG_SH_I2C_DATA_HIGH
CONFIG_SH_I2C_DATA_LOW
-CONFIG_SH_MMCIF_ADDR
CONFIG_SH_MMCIF_CLK
CONFIG_SH_QSPI_BASE
CONFIG_SH_SCIF_CLK_FREQ
CONFIG_SH_SDHI_FREQ
CONFIG_SH_SDRAM_OFFSET
-CONFIG_SH_SPI_BASE
CONFIG_SIEMENS_MACH_TYPE
-CONFIG_SIMU
CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
CONFIG_SKIP_LOWLEVEL_INIT
CONFIG_SKIP_LOWLEVEL_INIT_ONLY
CONFIG_SPI_FLASH_SIZE
CONFIG_SPI_HALF_DUPLEX
CONFIG_SPI_IDLE_VAL
-CONFIG_SPI_LENGTH
CONFIG_SPI_N25Q256A_RESET
CONFIG_SPLL_FREQ
CONFIG_SPL_
CONFIG_SYS_FLASH_BASE2
CONFIG_SYS_FLASH_BASE_PHYS
CONFIG_SYS_FLASH_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH_BASE_PHYS_LOW
CONFIG_SYS_FLASH_BR_PRELIM
CONFIG_SYS_FLASH_CFI_AMD_RESET
-CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
CONFIG_SYS_FLASH_CFI_NONBLOCK
CONFIG_SYS_FLASH_CFI_WIDTH
CONFIG_SYS_FLASH_CHECKSUM
CONFIG_SYS_LBC1_BASE_PHYS
CONFIG_SYS_LBCR_ADDR
CONFIG_SYS_LBC_ADDR
-CONFIG_SYS_LBC_BASE
-CONFIG_SYS_LBC_BASE_PHYS_LOW
CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LBC_FLASH_BASE
CONFIG_SYS_LBC_LBCR
CONFIG_SYS_LBC_LSDMR_RFEN
CONFIG_SYS_LBC_LSRT
CONFIG_SYS_LBC_MRTPR
-CONFIG_SYS_LBC_NONCACHE_BASE
CONFIG_SYS_LBC_SDRAM_BASE
CONFIG_SYS_LBC_SDRAM_BASE_PHYS
CONFIG_SYS_LBC_SDRAM_SIZE
CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
-CONFIG_SYS_LS_MC_DPC_ADDR
CONFIG_SYS_LS_MC_DPC_IN_DDR
-CONFIG_SYS_LS_MC_DPC_IN_NOR
CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
-CONFIG_SYS_LS_MC_DPL_ADDR
CONFIG_SYS_LS_MC_DPL_IN_DDR
-CONFIG_SYS_LS_MC_DPL_IN_NOR
CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
CONFIG_SYS_PCIE1_IO_BASE
CONFIG_SYS_PCIE1_IO_BUS
CONFIG_SYS_PCIE1_IO_PHYS
-CONFIG_SYS_PCIE1_IO_PHYS_LOW
CONFIG_SYS_PCIE1_IO_SIZE
CONFIG_SYS_PCIE1_IO_VIRT
CONFIG_SYS_PCIE1_MEM_BASE
CONFIG_SYS_PCIE1_MEM_BUS
CONFIG_SYS_PCIE1_MEM_PHYS
-CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
-CONFIG_SYS_PCIE1_MEM_PHYS_LOW
CONFIG_SYS_PCIE1_MEM_SIZE
CONFIG_SYS_PCIE1_MEM_VIRT
CONFIG_SYS_PCIE1_NAME
CONFIG_SYS_PCIE2_IO_BASE
CONFIG_SYS_PCIE2_IO_BUS
CONFIG_SYS_PCIE2_IO_PHYS
-CONFIG_SYS_PCIE2_IO_PHYS_LOW
CONFIG_SYS_PCIE2_IO_SIZE
CONFIG_SYS_PCIE2_IO_VIRT
CONFIG_SYS_PCIE2_MEM_BASE
CONFIG_SYS_PCIE2_MEM_BUS
CONFIG_SYS_PCIE2_MEM_PHYS
-CONFIG_SYS_PCIE2_MEM_PHYS_HIGH
-CONFIG_SYS_PCIE2_MEM_PHYS_LOW
CONFIG_SYS_PCIE2_MEM_SIZE
CONFIG_SYS_PCIE2_MEM_VIRT
CONFIG_SYS_PCIE2_NAME
CONFIG_SYS_PCIE3_IO_SIZE
CONFIG_SYS_PCIE3_IO_VIRT
CONFIG_SYS_PCIE3_MEM_BUS
-CONFIG_SYS_PCIE3_MEM_BUS2
CONFIG_SYS_PCIE3_MEM_PHYS
-CONFIG_SYS_PCIE3_MEM_PHYS2
CONFIG_SYS_PCIE3_MEM_SIZE
-CONFIG_SYS_PCIE3_MEM_SIZE2
CONFIG_SYS_PCIE3_MEM_VIRT
-CONFIG_SYS_PCIE3_MEM_VIRT2
CONFIG_SYS_PCIE3_NAME
CONFIG_SYS_PCIE3_PHYS_ADDR
CONFIG_SYS_PCIE3_PHYS_SIZE
CONFIG_SYS_PCIE4_PHYS_ADDR
CONFIG_SYS_PCIE4_PHYS_SIZE
CONFIG_SYS_PCIE_MMAP_SIZE
-CONFIG_SYS_PCIE_PHYS
-CONFIG_SYS_PCIE_VIRT
CONFIG_SYS_PCI_BAR0
CONFIG_SYS_PCI_BAR1
CONFIG_SYS_PCI_BAR2
CONFIG_SYS_PEHLPAR
CONFIG_SYS_PEPAR
CONFIG_SYS_PFPAR
-CONFIG_SYS_PHYS_ADDR_HIGH
CONFIG_SYS_PHY_UBOOT_BASE
CONFIG_SYS_PIB_BASE
CONFIG_SYS_PIB_WINDOW_SIZE
CONFIG_SYS_QRIO_BASE_PHYS
CONFIG_SYS_QRIO_BR_PRELIM
CONFIG_SYS_QRIO_OR_PRELIM
-CONFIG_SYS_R7780MP_OLD_FLASH
CONFIG_SYS_RAMBOOT
CONFIG_SYS_RCAR_I2C0_BASE
CONFIG_SYS_RCAR_I2C1_BASE
CONFIG_SYS_SRIO1_MEM_BASE
CONFIG_SYS_SRIO1_MEM_BUS
CONFIG_SYS_SRIO1_MEM_PHYS
-CONFIG_SYS_SRIO1_MEM_PHYS_HIGH
-CONFIG_SYS_SRIO1_MEM_PHYS_LOW
CONFIG_SYS_SRIO1_MEM_SIZE
CONFIG_SYS_SRIO1_MEM_VIRT
CONFIG_SYS_SRIO2_MEM_PHYS
CONFIG_UEC_ETH7
CONFIG_UEC_ETH8
CONFIG_UID16
-CONFIG_ULI526X
CONFIG_ULPI_REF_CLK
CONFIG_UPDATEB
CONFIG_UPDATE_LOAD_ADDR
CONFIG_VIDEO_FONT_4X6
CONFIG_VIDEO_LCD_I2C_BUS
CONFIG_VIDEO_LOGO
-CONFIG_VIDEO_MB862xx
-CONFIG_VIDEO_MB862xx_ACCEL
CONFIG_VIDEO_MXS
CONFIG_VIDEO_MXS_MODE_SYSTEM
CONFIG_VIDEO_STD_TIMINGS
unsigned depth = 0;
const void *prop;
const char *propname;
+ bool expect_end = false;
if (bufsize < FDT_V1_SIZE)
return -FDT_ERR_TRUNCATED;
if (nextoffset < 0)
return nextoffset;
+ /* If we see two root nodes, something is wrong */
+ if (expect_end && tag != FDT_END)
+ return -FDT_ERR_BADLAYOUT;
+
switch (tag) {
case FDT_NOP:
break;
depth++;
if (depth > INT_MAX)
return -FDT_ERR_BADSTRUCTURE;
+
+ /* The root node must have an empty name */
+ if (depth == 1) {
+ const char *name;
+ int len;
+
+ name = fdt_get_name(fdt, offset, &len);
+ if (*name || len)
+ return -FDT_ERR_BADLAYOUT;
+ }
break;
case FDT_END_NODE:
if (depth == 0)
return -FDT_ERR_BADSTRUCTURE;
depth--;
+ if (depth == 0)
+ expect_end = true;
break;
case FDT_PROP:
#include <bloblist.h>
#include <log.h>
#include <mapmem.h>
+#include <asm/global_data.h>
#include <test/suites.h>
#include <test/test.h>
#include <test/ut.h>
#include <common.h>
#include <bootm.h>
+#include <asm/global_data.h>
#include <test/suites.h>
#include <test/test.h>
#include <test/ut.h>
#include <common.h>
#include <command.h>
+#include <asm/global_data.h>
#include <display_options.h>
#include <test/lib.h>
#include <test/test.h>
obj-$(CONFIG_UT_DM) += test-uclass.o
obj-$(CONFIG_UT_DM) += core.o
+obj-$(CONFIG_UT_DM) += read.o
+obj-$(CONFIG_UT_DM) += phys2bus.o
ifneq ($(CONFIG_SANDBOX),)
obj-$(CONFIG_ACPIGEN) += acpi.o
obj-$(CONFIG_ACPIGEN) += acpigen.o
#include <acpi/acpigen.h>
#include <acpi/acpi_device.h>
#include <acpi/acpi_table.h>
+#include <asm/global_data.h>
#include <dm/acpi.h>
#include <dm/test.h>
#include <test/ut.h>
#include <dm.h>
#include <part.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <asm/state.h>
#include <dm/test.h>
#include <test/test.h>
#include <os.h>
#endif
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/test.h>
#include <common.h>
#include <dm.h>
+#include <adc.h>
#include <button.h>
+#include <power/regulator.h>
+#include <power/sandbox_pmic.h>
#include <asm/gpio.h>
#include <dm/test.h>
#include <test/ut.h>
{
struct udevice *dev;
- /* Get the top-level device */
+ /* Get the top-level gpio buttons device */
ut_assertok(uclass_get_device(UCLASS_BUTTON, 0, &dev));
+ /* Get the 2 gpio buttons */
ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, &dev));
ut_assertok(uclass_get_device(UCLASS_BUTTON, 2, &dev));
- ut_asserteq(-ENODEV, uclass_get_device(UCLASS_BUTTON, 3, &dev));
+
+ /* Get the top-level adc buttons device */
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 3, &dev));
+ /* Get the 3 adc buttons */
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 4, &dev));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 5, &dev));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 6, &dev));
+
+ ut_asserteq(-ENODEV, uclass_get_device(UCLASS_BUTTON, 7, &dev));
return 0;
}
return 0;
}
DM_TEST(dm_test_button_label, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test adc-keys driver */
+static int dm_test_button_keys_adc(struct unit_test_state *uts)
+{
+ struct udevice *supply;
+ struct udevice *dev;
+ int uV;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
+
+ ut_assertok(regulator_get_by_devname(SANDBOX_BUCK2_DEVNAME, &supply));
+ ut_assertok(regulator_set_value(supply, SANDBOX_BUCK2_SET_UV));
+ ut_asserteq(SANDBOX_BUCK2_SET_UV, regulator_get_value(supply));
+ /* Update ADC plat and get new Vdd value */
+ ut_assertok(adc_vdd_value(dev, &uV));
+ ut_asserteq(SANDBOX_BUCK2_SET_UV, uV);
+
+ /*
+ * sandbox-adc returns constant value on channel 3, is used by adc-keys:
+ * SANDBOX_ADC_CHANNEL3_DATA * SANDBOX_BUCK2_SET_UV / SANDBOX_ADC_DATA_MASK =
+ * 0x3000 * 3300000 / 0xffff = 618759uV
+ * This means that button3 and button4 are released and button5
+ * is pressed.
+ */
+ ut_assertok(button_get_by_label("button3", &dev));
+ ut_asserteq(BUTTON_OFF, button_get_state(dev));
+ ut_assertok(button_get_by_label("button4", &dev));
+ ut_asserteq(BUTTON_OFF, button_get_state(dev));
+ ut_assertok(button_get_by_label("button5", &dev));
+ ut_asserteq(BUTTON_ON, button_get_state(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_button_keys_adc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/root.h>
#include <dm/util.h>
.name = "test_act_dma_drv",
};
+static struct driver_info driver_info_vital_clk = {
+ .name = "test_vital_clk_drv",
+};
+
+static struct driver_info driver_info_act_dma_vital_clk = {
+ .name = "test_act_dma_vital_clk_drv",
+};
+
void dm_leak_check_start(struct unit_test_state *uts)
{
uts->start = mallinfo();
}
DM_TEST(dm_test_remove_active_dma, 0);
+/* Test removal of 'vital' devices */
+static int dm_test_remove_vital(struct unit_test_state *uts)
+{
+ struct dm_test_state *dms = uts->priv;
+ struct udevice *normal, *dma, *vital, *dma_vital;
+
+ /* Skip the behaviour in test_post_probe() */
+ dms->skip_post_probe = 1;
+
+ ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
+ &normal));
+ ut_assertnonnull(normal);
+
+ ut_assertok(device_bind_by_name(dms->root, false, &driver_info_act_dma,
+ &dma));
+ ut_assertnonnull(dma);
+
+ ut_assertok(device_bind_by_name(dms->root, false,
+ &driver_info_vital_clk, &vital));
+ ut_assertnonnull(vital);
+
+ ut_assertok(device_bind_by_name(dms->root, false,
+ &driver_info_act_dma_vital_clk,
+ &dma_vital));
+ ut_assertnonnull(dma_vital);
+
+ /* Probe the devices */
+ ut_assertok(device_probe(normal));
+ ut_assertok(device_probe(dma));
+ ut_assertok(device_probe(vital));
+ ut_assertok(device_probe(dma_vital));
+
+ /* Check that devices are active right now */
+ ut_asserteq(true, device_active(normal));
+ ut_asserteq(true, device_active(dma));
+ ut_asserteq(true, device_active(vital));
+ ut_asserteq(true, device_active(dma_vital));
+
+ /* Remove active devices via selective remove flag */
+ dm_remove_devices_flags(DM_REMOVE_NON_VITAL | DM_REMOVE_ACTIVE_ALL);
+
+ /*
+ * Check that this only has an effect on the dma device, since two
+ * devices are vital and the third does not have active DMA
+ */
+ ut_asserteq(true, device_active(normal));
+ ut_asserteq(false, device_active(dma));
+ ut_asserteq(true, device_active(vital));
+ ut_asserteq(true, device_active(dma_vital));
+
+ /* Remove active devices via selective remove flag */
+ ut_assertok(device_probe(dma));
+ dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+
+ /* This should have affected both active-dma devices */
+ ut_asserteq(true, device_active(normal));
+ ut_asserteq(false, device_active(dma));
+ ut_asserteq(true, device_active(vital));
+ ut_asserteq(false, device_active(dma_vital));
+
+ /* Remove non-vital devices */
+ ut_assertok(device_probe(dma));
+ ut_assertok(device_probe(dma_vital));
+ dm_remove_devices_flags(DM_REMOVE_NON_VITAL);
+
+ /* This should have affected only non-vital devices */
+ ut_asserteq(false, device_active(normal));
+ ut_asserteq(false, device_active(dma));
+ ut_asserteq(true, device_active(vital));
+ ut_asserteq(true, device_active(dma_vital));
+
+ /* Remove vital devices via normal remove flag */
+ ut_assertok(device_probe(normal));
+ ut_assertok(device_probe(dma));
+ dm_remove_devices_flags(DM_REMOVE_NORMAL);
+
+ /* Check that all devices are inactive right now */
+ ut_asserteq(false, device_active(normal));
+ ut_asserteq(false, device_active(dma));
+ ut_asserteq(false, device_active(vital));
+ ut_asserteq(false, device_active(dma_vital));
+
+ return 0;
+}
+DM_TEST(dm_test_remove_vital, 0);
+
static int dm_test_uclass_before_ready(struct unit_test_state *uts)
{
struct uclass *uc;
return 0;
}
DM_TEST(dm_test_all_have_seq, UT_TESTF_SCAN_PDATA);
+
+static int dm_test_dma_offset(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ ofnode node;
+
+ /* Make sure the bus's dma-ranges aren't taken into account here */
+ node = ofnode_path("/mmio-bus@0");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_BUS, node, &dev));
+ ut_asserteq_64(0, dev->dma_offset);
+
+ /* Device behind a bus with dma-ranges */
+ node = ofnode_path("/mmio-bus@0/subnode@0");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_FDT, node, &dev));
+ ut_asserteq_64(-0x10000000ULL, dev->dma_offset);
+
+ /* This one has no dma-ranges */
+ node = ofnode_path("/mmio-bus@1");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_BUS, node, &dev));
+ node = ofnode_path("/mmio-bus@1/subnode@0");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_FDT, node, &dev));
+ ut_asserteq_64(0, dev->dma_offset);
+
+ return 0;
+}
+DM_TEST(dm_test_dma_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
#include <common.h>
#include <dm.h>
+#include <asm/global_data.h>
#include <dm/of_extra.h>
#include <dm/test.h>
#include <test/ut.h>
#include <mux-internal.h>
#include <dm/test.h>
#include <test/ut.h>
+#include <asm/global_data.h>
struct mux_emul_priv {
u32 state;
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
+#include <asm/global_data.h>
/* Test that we can find a device using of-platdata */
static int dm_test_of_plat_base(struct unit_test_state *uts)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <phys2bus.h>
+#include <dm/device.h>
+#include <dm/ofnode.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+#include <test/ut.h>
+
+static int dm_test_phys_to_bus(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ ofnode node;
+
+ node = ofnode_path("/mmio-bus@0");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_BUS, node, &dev));
+ /* In this case it should be transparent, no dma-ranges in parent bus */
+ ut_asserteq_addr((void*)0xfffffULL, (void*)dev_phys_to_bus(dev, 0xfffff));
+ ut_asserteq_addr((void*)0xfffffULL, (void*)(ulong)dev_bus_to_phys(dev, 0xfffff));
+
+ node = ofnode_path("/mmio-bus@0/subnode@0");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_FDT, node, &dev));
+ ut_asserteq_addr((void*)0x100fffffULL, (void*)dev_phys_to_bus(dev, 0xfffff));
+ ut_asserteq_addr((void*)0xfffffULL, (void*)(ulong)dev_bus_to_phys(dev, 0x100fffff));
+
+ return 0;
+}
+DM_TEST(dm_test_phys_to_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
#include <common.h>
#include <dm.h>
#include <ram.h>
+#include <asm/global_data.h>
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/ofnode.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+#include <test/ut.h>
+
+static int dm_test_dma_ranges(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ phys_addr_t cpu;
+ dma_addr_t bus;
+ ofnode node;
+ u64 size;
+
+ /* dma-ranges are on the device's node */
+ node = ofnode_path("/mmio-bus@0");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_BUS, node, &dev));
+ ut_assertok(dev_get_dma_range(dev, &cpu, &bus, &size));
+ ut_asserteq_64(0x40000, size);
+ ut_asserteq_64(0x0, cpu);
+ ut_asserteq_64(0x10000000, bus);
+
+ /* dma-ranges are on the bus' node */
+ node = ofnode_path("/mmio-bus@0/subnode@0");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_FDT, node, &dev));
+ ut_assertok(dev_get_dma_range(dev, &cpu, &bus, &size));
+ ut_asserteq_64(0x40000, size);
+ ut_asserteq_64(0x0, cpu);
+ ut_asserteq_64(0x10000000, bus);
+
+ /* No dma-ranges available */
+ node = ofnode_path("/mmio-bus@1");
+ ut_assert(ofnode_valid(node));
+ ut_assertok(uclass_get_device_by_ofnode(UCLASS_TEST_BUS, node, &dev));
+ ut_asserteq(-ENOENT, dev_get_dma_range(dev, &cpu, &bus, &size));
+
+ return 0;
+}
+DM_TEST(dm_test_dma_ranges, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
#include <test/test.h>
#include <test/ut.h>
#include <tee/optee_ta_avb.h>
+#include <tee/optee_ta_rpc_test.h>
-static int open_session(struct udevice *dev, u32 *session)
+static int open_session(struct udevice *dev, u32 *session,
+ struct tee_optee_ta_uuid *uuid)
{
struct tee_open_session_arg arg;
- const struct tee_optee_ta_uuid uuid = TA_AVB_UUID;
int rc;
memset(&arg, 0, sizeof(arg));
- tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
+ tee_optee_ta_uuid_to_octets(arg.uuid, uuid);
rc = tee_open_session(dev, &arg, 0, NULL);
if (rc)
return rc;
return 0;
}
-static int invoke_func(struct udevice *dev, u32 session)
+static int invoke_func_avb(struct udevice *dev, u32 session)
{
struct tee_param param = { .attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT };
struct tee_invoke_arg arg;
return 0;
}
+static int invoke_func_rpc_test(struct udevice *dev, u32 session,
+ u64 op, u64 busnum, u64 chip_addr,
+ u64 xfer_flags, u8 *buf, size_t buf_size)
+{
+ struct tee_param param[2];
+ struct tee_invoke_arg arg;
+ struct tee_shm *shm_buf;
+ int rc;
+
+ memset(&arg, 0, sizeof(arg));
+ arg.session = session;
+ arg.func = op;
+
+ rc = tee_shm_alloc(dev, buf_size,
+ TEE_SHM_ALLOC, &shm_buf);
+ if (rc)
+ return rc;
+
+ if (op == TA_RPC_TEST_CMD_I2C_WRITE)
+ memcpy(shm_buf->addr, buf, buf_size);
+
+ memset(param, 0, sizeof(param));
+ param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT;
+ param[0].u.value.a = busnum;
+ param[0].u.value.b = chip_addr;
+ param[0].u.value.c = xfer_flags;
+ param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT;
+ param[1].u.memref.shm = shm_buf;
+ param[1].u.memref.size = buf_size;
+
+ if (tee_invoke_func(dev, &arg, 2, param) || arg.ret) {
+ rc = -1;
+ goto out;
+ }
+
+ if (op == TA_RPC_TEST_CMD_I2C_READ)
+ memcpy(buf, shm_buf->addr, buf_size);
+out:
+ tee_shm_free(shm_buf);
+ return rc;
+}
+
static int match(struct tee_version_data *vers, const void *data)
{
return vers->gen_caps & TEE_GEN_CAP_GP;
struct tee_version_data vers;
struct udevice *dev;
struct sandbox_tee_state *state;
+ struct tee_optee_ta_uuid avb_uuid = TA_AVB_UUID;
u32 session = 0;
int rc;
u8 data[128];
state = dev_get_priv(dev);
ut_assert(!state->session);
- rc = open_session(dev, &session);
+ rc = open_session(dev, &session, &avb_uuid);
ut_assert(!rc);
ut_assert(session == state->session);
- rc = invoke_func(dev, session);
+ rc = invoke_func_avb(dev, session);
ut_assert(!rc);
rc = tee_close_session(dev, session);
vars->alloc_shm = NULL;
ut_assert(!state->num_shms);
- return 0;
+ return rc;
+}
+
+#define I2C_BUF_SIZE 64
+
+static int test_tee_rpc(struct unit_test_state *uts)
+{
+ struct tee_version_data vers;
+ struct udevice *dev;
+ struct sandbox_tee_state *state;
+ struct tee_optee_ta_uuid rpc_test_uuid = TA_RPC_TEST_UUID;
+ u32 session = 0;
+ int rc;
+
+ char *test_str = "Test string";
+ u8 data[I2C_BUF_SIZE] = {0};
+ u8 data_from_eeprom[I2C_BUF_SIZE] = {0};
+
+ /* Use sandbox I2C EEPROM emulation; bus: 0, chip: 0x2c */
+ u64 bus = 0;
+ u64 chip = 0x2c;
+ u64 xfer_flags = 0;
+
+ dev = tee_find_device(NULL, match, NULL, &vers);
+ ut_assert(dev);
+ state = dev_get_priv(dev);
+ ut_assert(!state->session);
+
+ /* Test RPC call asking for I2C service */
+ rc = open_session(dev, &session, &rpc_test_uuid);
+ ut_assert(!rc);
+ ut_assert(session == state->session);
+
+ /* Write buffer */
+ strncpy((char *)data, test_str, strlen(test_str));
+ rc = invoke_func_rpc_test(dev, session, TA_RPC_TEST_CMD_I2C_WRITE,
+ bus, chip, xfer_flags, data, sizeof(data));
+ ut_assert(!rc);
+
+ /* Read buffer */
+ rc = invoke_func_rpc_test(dev, session, TA_RPC_TEST_CMD_I2C_READ,
+ bus, chip, xfer_flags, data_from_eeprom,
+ sizeof(data_from_eeprom));
+ ut_assert(!rc);
+
+ /* Compare */
+ ut_assert(!memcmp(data, data_from_eeprom, sizeof(data)));
+
+ rc = tee_close_session(dev, session);
+ ut_assert(!rc);
+ ut_assert(!state->session);
+
+ return rc;
}
static int dm_test_tee(struct unit_test_state *uts)
struct test_tee_vars vars = { NULL, NULL };
int rc = test_tee(uts, &vars);
+ if (rc)
+ goto out;
+
+ if (IS_ENABLED(CONFIG_OPTEE_TA_RPC_TEST))
+ rc = test_tee_rpc(uts);
+out:
/* In case test_tee() asserts these may still remain allocated */
tee_shm_free(vars.reg_shm);
tee_shm_free(vars.alloc_shm);
.unbind = test_manual_unbind,
.flags = DM_FLAG_ACTIVE_DMA,
};
+
+U_BOOT_DRIVER(test_vital_clk_drv) = {
+ .name = "test_vital_clk_drv",
+ .id = UCLASS_TEST,
+ .ops = &test_manual_ops,
+ .bind = test_manual_bind,
+ .probe = test_manual_probe,
+ .remove = test_manual_remove,
+ .unbind = test_manual_unbind,
+ .flags = DM_FLAG_VITAL,
+};
+
+U_BOOT_DRIVER(test_act_dma_vital_clk_drv) = {
+ .name = "test_act_dma_vital_clk_drv",
+ .id = UCLASS_TEST,
+ .ops = &test_manual_ops,
+ .bind = test_manual_bind,
+ .probe = test_manual_probe,
+ .remove = test_manual_remove,
+ .unbind = test_manual_unbind,
+ .flags = DM_FLAG_VITAL | DM_FLAG_ACTIVE_DMA,
+};
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/test.h>
#include <dm/root.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <asm/state.h>
#include <dm/test.h>
#include <dm/root.h>
/* check the device can be successfully removed */
dev_or_flags(dev, DM_FLAG_ACTIVATED);
- ut_assertok(device_remove(bus, DM_REMOVE_ACTIVE_ALL));
+ ut_asserteq(-EKEYREJECTED, device_remove(bus, DM_REMOVE_ACTIVE_ALL));
+
+ ut_asserteq(false, device_active(dev));
return 0;
}
#include <common.h>
#include <command.h>
#include <display_options.h>
+#include <asm/global_data.h>
#include <test/lib.h>
#include <test/test.h>
#include <test/ut.h>
#include <common.h>
#include <console.h>
+#include <asm/global_data.h>
#include <test/log.h>
#include <test/test.h>
#include <test/suites.h>
#include <common.h>
#include <console.h>
#include <log.h>
+#include <asm/global_data.h>
#include <test/log.h>
#include <test/ut.h>
#include <common.h>
#include <command.h>
#include <log.h>
+#include <asm/global_data.h>
#include <test/log.h>
#include <test/ut.h>
#include <common.h>
#include <console.h>
+#include <asm/global_data.h>
#include <test/log.h>
#include <test/test.h>
#include <test/suites.h>
#include <test/test.h>
#include <test/suites.h>
#include <test/ut.h>
+#include <asm/global_data.h>
#include <linux/printk.h>
#define BUFFSIZE 64
#define LOG_DEBUG
#include <common.h>
+#include <asm/global_data.h>
#include <dm/device.h>
#include <hexdump.h>
#include <test/log.h>
*/
#include <common.h>
+#include <asm/global_data.h>
#include <dm/device.h>
#include <hexdump.h>
#include <test/log.h>
pbr==5.4.3
pluggy==0.13.0
py==1.8.0
+pyelftools==0.27
+pygit2==1.4.0
pyparsing==2.4.2
pytest==5.2.1
python-mimeparse==1.6.0
#address-cells = <1>;
images {
- kernel@1 {
+ kernel-1 {
data = /incbin/("%(kernel)s");
type = "kernel";
arch = "sandbox";
load = <0x40000>;
entry = <0x8>;
};
- kernel@2 {
+ kernel-2 {
data = /incbin/("%(loadables1)s");
type = "kernel";
arch = "sandbox";
%(loadables1_load)s
entry = <0x0>;
};
- fdt@1 {
+ fdt-1 {
description = "snow";
data = /incbin/("%(fdt)s");
type = "flat_dt";
arch = "sandbox";
%(fdt_load)s
compression = "%(compression)s";
- signature@1 {
+ signature-1 {
algo = "sha1,rsa2048";
key-name-hint = "dev";
};
};
- ramdisk@1 {
+ ramdisk-1 {
description = "snow";
data = /incbin/("%(ramdisk)s");
type = "ramdisk";
%(ramdisk_load)s
compression = "%(compression)s";
};
- ramdisk@2 {
+ ramdisk-2 {
description = "snow";
data = /incbin/("%(loadables2)s");
type = "ramdisk";
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel-1";
+ fdt = "fdt-1";
%(ramdisk_config)s
%(loadables_config)s
};
# Try a ramdisk
with cons.log.section('Kernel + FDT + Ramdisk load'):
- params['ramdisk_config'] = 'ramdisk = "ramdisk@1";'
+ params['ramdisk_config'] = 'ramdisk = "ramdisk-1";'
params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr']
fit = make_fit(mkimage, params)
cons.restart_uboot()
# Configuration with some Loadables
with cons.log.section('Kernel + FDT + Ramdisk load + Loadables'):
- params['loadables_config'] = 'loadables = "kernel@2", "ramdisk@2";'
+ params['loadables_config'] = 'loadables = "kernel-2", "ramdisk-2";'
params['loadables1_load'] = ('load = <%#x>;' %
params['loadables1_addr'])
params['loadables2_load'] = ('load = <%#x>;' %
Tests run with both SHA1 and SHA256 hashing.
"""
+import shutil
import struct
import pytest
import u_boot_utils as util
import vboot_forge
+import vboot_evil
+# Only run the full suite on a few combinations, since it doesn't add any more
+# test coverage.
TESTDATA = [
- ['sha1', '', None, False],
- ['sha1', '', '-E -p 0x10000', False],
- ['sha1', '-pss', None, False],
- ['sha1', '-pss', '-E -p 0x10000', False],
- ['sha256', '', None, False],
- ['sha256', '', '-E -p 0x10000', False],
- ['sha256', '-pss', None, False],
- ['sha256', '-pss', '-E -p 0x10000', False],
- ['sha256', '-pss', None, True],
- ['sha256', '-pss', '-E -p 0x10000', True],
+ ['sha1', '', None, False, True],
+ ['sha1', '', '-E -p 0x10000', False, False],
+ ['sha1', '-pss', None, False, False],
+ ['sha1', '-pss', '-E -p 0x10000', False, False],
+ ['sha256', '', None, False, False],
+ ['sha256', '', '-E -p 0x10000', False, False],
+ ['sha256', '-pss', None, False, False],
+ ['sha256', '-pss', '-E -p 0x10000', False, False],
+ ['sha256', '-pss', None, True, False],
+ ['sha256', '-pss', '-E -p 0x10000', True, True],
]
@pytest.mark.boardspec('sandbox')
@pytest.mark.requiredtool('fdtget')
@pytest.mark.requiredtool('fdtput')
@pytest.mark.requiredtool('openssl')
-@pytest.mark.parametrize("sha_algo,padding,sign_options,required", TESTDATA)
-def test_vboot(u_boot_console, sha_algo, padding, sign_options, required):
+@pytest.mark.parametrize("sha_algo,padding,sign_options,required,full_test",
+ TESTDATA)
+def test_vboot(u_boot_console, sha_algo, padding, sign_options, required,
+ full_test):
"""Test verified boot signing with mkimage and verification with 'bootm'.
This works using sandbox only as it needs to update the device tree used
util.run_and_log(cons, 'dtc %s %s%s -O dtb '
'-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
- def run_bootm(sha_algo, test_type, expect_string, boots):
+ def run_bootm(sha_algo, test_type, expect_string, boots, fit=None):
"""Run a 'bootm' command U-Boot.
This always starts a fresh U-Boot instance since the device tree may
use.
boots: A boolean that is True if Linux should boot and False if
we are expected to not boot
+ fit: FIT filename to load and verify
"""
+ if not fit:
+ fit = '%stest.fit' % tmpdir
cons.restart_uboot()
with cons.log.section('Verified boot %s %s' % (sha_algo, test_type)):
output = cons.run_command_list(
- ['host load hostfs - 100 %stest.fit' % tmpdir,
+ ['host load hostfs - 100 %s' % fit,
'fdt addr 100',
'bootm 100'])
assert expect_string in ''.join(output)
util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb])
- # Make sure that U-Boot checks that the config is in the list of hashed
- # nodes. If it isn't, a security bypass is possible.
- with open(fit, 'rb') as fd:
- root, strblock = vboot_forge.read_fdt(fd)
- root, strblock = vboot_forge.manipulate(root, strblock)
- with open(fit, 'w+b') as fd:
- vboot_forge.write_fdt(root, strblock, fd)
- util.run_and_log_expect_exception(
- cons, [fit_check_sign, '-f', fit, '-k', dtb],
- 1, 'Failed to verify required signature')
-
- run_bootm(sha_algo, 'forged config', 'Bad Data Hash', False)
+ if full_test:
+ # Make sure that U-Boot checks that the config is in the list of
+ # hashed nodes. If it isn't, a security bypass is possible.
+ ffit = '%stest.forged.fit' % tmpdir
+ shutil.copyfile(fit, ffit)
+ with open(ffit, 'rb') as fd:
+ root, strblock = vboot_forge.read_fdt(fd)
+ root, strblock = vboot_forge.manipulate(root, strblock)
+ with open(ffit, 'w+b') as fd:
+ vboot_forge.write_fdt(root, strblock, fd)
+ util.run_and_log_expect_exception(
+ cons, [fit_check_sign, '-f', ffit, '-k', dtb],
+ 1, 'Failed to verify required signature')
+
+ run_bootm(sha_algo, 'forged config', 'Bad Data Hash', False, ffit)
+
+ # Try adding an evil root node. This should be detected.
+ efit = '%stest.evilf.fit' % tmpdir
+ shutil.copyfile(fit, efit)
+ vboot_evil.add_evil_node(fit, efit, evil_kernel, 'fakeroot')
+
+ util.run_and_log_expect_exception(
+ cons, [fit_check_sign, '-f', efit, '-k', dtb],
+ 1, 'Failed to verify required signature')
+ run_bootm(sha_algo, 'evil fakeroot', 'Bad FIT kernel image format',
+ False, efit)
+
+ # Try adding an @ to the kernel node name. This should be detected.
+ efit = '%stest.evilk.fit' % tmpdir
+ shutil.copyfile(fit, efit)
+ vboot_evil.add_evil_node(fit, efit, evil_kernel, 'kernel@')
+
+ msg = 'Signature checking prevents use of unit addresses (@) in nodes'
+ util.run_and_log_expect_exception(
+ cons, [fit_check_sign, '-f', efit, '-k', dtb],
+ 1, msg)
+ run_bootm(sha_algo, 'evil kernel@', msg, False, efit)
# Create a new properly signed fit and replace header bytes
make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
create_rsa_pair('prod')
# Create a number kernel image with zeroes
- with open('%stest-kernel.bin' % tmpdir, 'w') as fd:
- fd.write(500 * chr(0))
+ with open('%stest-kernel.bin' % tmpdir, 'wb') as fd:
+ fd.write(500 * b'\0')
+
+ # Create a second kernel image with ones
+ evil_kernel = '%stest-kernel1.bin' % tmpdir
+ with open(evil_kernel, 'wb') as fd:
+ fd.write(500 * b'\x01')
try:
# We need to use our own device tree file. Remember to restore it
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation
+
+"""Modifies a devicetree to add a fake root node, for testing purposes"""
+
+import hashlib
+import struct
+import sys
+
+FDT_PROP = 0x3
+FDT_BEGIN_NODE = 0x1
+FDT_END_NODE = 0x2
+FDT_END = 0x9
+
+FAKE_ROOT_ATTACK = 0
+KERNEL_AT = 1
+
+MAGIC = 0xd00dfeed
+
+EVIL_KERNEL_NAME = b'evil_kernel'
+FAKE_ROOT_NAME = b'f@keroot'
+
+
+def getstr(dt_strings, off):
+ """Get a string from the devicetree string table
+
+ Args:
+ dt_strings (bytes): Devicetree strings section
+ off (int): Offset of string to read
+
+ Returns:
+ str: String read from the table
+ """
+ output = ''
+ while dt_strings[off]:
+ output += chr(dt_strings[off])
+ off += 1
+
+ return output
+
+
+def align(offset):
+ """Align an offset to a multiple of 4
+
+ Args:
+ offset (int): Offset to align
+
+ Returns:
+ int: Resulting aligned offset (rounds up to nearest multiple)
+ """
+ return (offset + 3) & ~3
+
+
+def determine_offset(dt_struct, dt_strings, searched_node_name):
+ """Determines the offset of an element, either a node or a property
+
+ Args:
+ dt_struct (bytes): Devicetree struct section
+ dt_strings (bytes): Devicetree strings section
+ searched_node_name (str): element path, ex: /images/kernel@1/data
+
+ Returns:
+ tuple: (node start offset, node end offset)
+ if element is not found, returns (None, None)
+ """
+ offset = 0
+ depth = -1
+
+ path = '/'
+
+ object_start_offset = None
+ object_end_offset = None
+ object_depth = None
+
+ while offset < len(dt_struct):
+ (tag,) = struct.unpack('>I', dt_struct[offset:offset + 4])
+
+ if tag == FDT_BEGIN_NODE:
+ depth += 1
+
+ begin_node_offset = offset
+ offset += 4
+
+ node_name = getstr(dt_struct, offset)
+ offset += len(node_name) + 1
+ offset = align(offset)
+
+ if path[-1] != '/':
+ path += '/'
+
+ path += str(node_name)
+
+ if path == searched_node_name:
+ object_start_offset = begin_node_offset
+ object_depth = depth
+
+ elif tag == FDT_PROP:
+ begin_prop_offset = offset
+
+ offset += 4
+ len_tag, nameoff = struct.unpack('>II',
+ dt_struct[offset:offset + 8])
+ offset += 8
+ prop_name = getstr(dt_strings, nameoff)
+
+ len_tag = align(len_tag)
+
+ offset += len_tag
+
+ node_path = path + '/' + str(prop_name)
+
+ if node_path == searched_node_name:
+ object_start_offset = begin_prop_offset
+
+ elif tag == FDT_END_NODE:
+ offset += 4
+
+ path = path[:path.rfind('/')]
+ if not path:
+ path = '/'
+
+ if depth == object_depth:
+ object_end_offset = offset
+ break
+ depth -= 1
+ elif tag == FDT_END:
+ break
+
+ else:
+ print('unknown tag=0x%x, offset=0x%x found!' % (tag, offset))
+ break
+
+ return object_start_offset, object_end_offset
+
+
+def modify_node_name(dt_struct, node_offset, replcd_name):
+ """Change the name of a node
+
+ Args:
+ dt_struct (bytes): Devicetree struct section
+ node_offset (int): Offset of node
+ replcd_name (str): New name for node
+
+ Returns:
+ bytes: New dt_struct contents
+ """
+
+ # skip 4 bytes for the FDT_BEGIN_NODE
+ node_offset += 4
+
+ node_name = getstr(dt_struct, node_offset)
+ node_name_len = len(node_name) + 1
+
+ node_name_len = align(node_name_len)
+
+ replcd_name += b'\0'
+
+ # align on 4 bytes
+ while len(replcd_name) % 4:
+ replcd_name += b'\0'
+
+ dt_struct = (dt_struct[:node_offset] + replcd_name +
+ dt_struct[node_offset + node_name_len:])
+
+ return dt_struct
+
+
+def modify_prop_content(dt_struct, prop_offset, content):
+ """Overwrite the value of a property
+
+ Args:
+ dt_struct (bytes): Devicetree struct section
+ prop_offset (int): Offset of property (FDT_PROP tag)
+ content (bytes): New content for the property
+
+ Returns:
+ bytes: New dt_struct contents
+ """
+ # skip FDT_PROP
+ prop_offset += 4
+ (len_tag, nameoff) = struct.unpack('>II',
+ dt_struct[prop_offset:prop_offset + 8])
+
+ # compute padded original node length
+ original_node_len = len_tag + 8 # content length + prop meta data len
+
+ original_node_len = align(original_node_len)
+
+ added_data = struct.pack('>II', len(content), nameoff)
+ added_data += content
+ while len(added_data) % 4:
+ added_data += b'\0'
+
+ dt_struct = (dt_struct[:prop_offset] + added_data +
+ dt_struct[prop_offset + original_node_len:])
+
+ return dt_struct
+
+
+def change_property_value(dt_struct, dt_strings, prop_path, prop_value,
+ required=True):
+ """Change a given property value
+
+ Args:
+ dt_struct (bytes): Devicetree struct section
+ dt_strings (bytes): Devicetree strings section
+ prop_path (str): full path of the target property
+ prop_value (bytes): new property name
+ required (bool): raise an exception if property not found
+
+ Returns:
+ bytes: New dt_struct contents
+
+ Raises:
+ ValueError: if the property is not found
+ """
+ (rt_node_start, _) = determine_offset(dt_struct, dt_strings, prop_path)
+ if rt_node_start is None:
+ if not required:
+ return dt_struct
+ raise ValueError('Fatal error, unable to find prop %s' % prop_path)
+
+ dt_struct = modify_prop_content(dt_struct, rt_node_start, prop_value)
+
+ return dt_struct
+
+def change_node_name(dt_struct, dt_strings, node_path, node_name):
+ """Change a given node name
+
+ Args:
+ dt_struct (bytes): Devicetree struct section
+ dt_strings (bytes): Devicetree strings section
+ node_path (str): full path of the target node
+ node_name (str): new node name, just node name not full path
+
+ Returns:
+ bytes: New dt_struct contents
+
+ Raises:
+ ValueError: if the node is not found
+ """
+ (rt_node_start, rt_node_end) = (
+ determine_offset(dt_struct, dt_strings, node_path))
+ if rt_node_start is None or rt_node_end is None:
+ raise ValueError('Fatal error, unable to find root node')
+
+ dt_struct = modify_node_name(dt_struct, rt_node_start, node_name)
+
+ return dt_struct
+
+def get_prop_value(dt_struct, dt_strings, prop_path):
+ """Get the content of a property based on its path
+
+ Args:
+ dt_struct (bytes): Devicetree struct section
+ dt_strings (bytes): Devicetree strings section
+ prop_path (str): full path of the target property
+
+ Returns:
+ bytes: Property value
+
+ Raises:
+ ValueError: if the property is not found
+ """
+ (offset, _) = determine_offset(dt_struct, dt_strings, prop_path)
+ if offset is None:
+ raise ValueError('Fatal error, unable to find prop')
+
+ offset += 4
+ (len_tag,) = struct.unpack('>I', dt_struct[offset:offset + 4])
+
+ offset += 8
+ tag_data = dt_struct[offset:offset + len_tag]
+
+ return tag_data
+
+
+def kernel_at_attack(dt_struct, dt_strings, kernel_content, kernel_hash):
+ """Conduct the kernel@ attack
+
+ It fetches from /configurations/default the name of the kernel being loaded.
+ Then, if the kernel name does not contain any @sign, duplicates the kernel
+ in /images node and appends '@evil' to its name.
+ It inserts a new kernel content and updates its images digest.
+
+ Inputs:
+ - FIT dt_struct
+ - FIT dt_strings
+ - kernel content blob
+ - kernel hash blob
+
+ Important note: it assumes the U-Boot loading method is 'kernel' and the
+ loaded kernel hash's subnode name is 'hash-1'
+ """
+
+ # retrieve the default configuration name
+ default_conf_name = get_prop_value(
+ dt_struct, dt_strings, '/configurations/default')
+ default_conf_name = str(default_conf_name[:-1], 'utf-8')
+
+ conf_path = '/configurations/' + default_conf_name
+
+ # fetch the loaded kernel name from the default configuration
+ loaded_kernel = get_prop_value(dt_struct, dt_strings, conf_path + '/kernel')
+
+ loaded_kernel = str(loaded_kernel[:-1], 'utf-8')
+
+ if loaded_kernel.find('@') != -1:
+ print('kernel@ attack does not work on nodes already containing an @ sign!')
+ sys.exit()
+
+ # determine boundaries of the loaded kernel
+ (krn_node_start, krn_node_end) = (determine_offset(
+ dt_struct, dt_strings, '/images/' + loaded_kernel))
+ if krn_node_start is None and krn_node_end is None:
+ print('Fatal error, unable to find root node')
+ sys.exit()
+
+ # copy the loaded kernel
+ loaded_kernel_copy = dt_struct[krn_node_start:krn_node_end]
+
+ # insert the copy inside the tree
+ dt_struct = dt_struct[:krn_node_start] + \
+ loaded_kernel_copy + dt_struct[krn_node_start:]
+
+ evil_kernel_name = loaded_kernel+'@evil'
+
+ # change the inserted kernel name
+ dt_struct = change_node_name(
+ dt_struct, dt_strings, '/images/' + loaded_kernel, bytes(evil_kernel_name, 'utf-8'))
+
+ # change the content of the kernel being loaded
+ dt_struct = change_property_value(
+ dt_struct, dt_strings, '/images/' + evil_kernel_name + '/data', kernel_content)
+
+ # change the content of the kernel being loaded
+ dt_struct = change_property_value(
+ dt_struct, dt_strings, '/images/' + evil_kernel_name + '/hash-1/value', kernel_hash)
+
+ return dt_struct
+
+
+def fake_root_node_attack(dt_struct, dt_strings, kernel_content, kernel_digest):
+ """Conduct the fakenode attack
+
+ It duplicates the original root node at the beginning of the tree.
+ Then it modifies within this duplicated tree:
+ - The loaded kernel name
+ - The loaded kernel data
+
+ Important note: it assumes the UBoot loading method is 'kernel' and the loaded kernel
+ hash's subnode name is hash@1
+ """
+
+ # retrieve the default configuration name
+ default_conf_name = get_prop_value(
+ dt_struct, dt_strings, '/configurations/default')
+ default_conf_name = str(default_conf_name[:-1], 'utf-8')
+
+ conf_path = '/configurations/'+default_conf_name
+
+ # fetch the loaded kernel name from the default configuration
+ loaded_kernel = get_prop_value(dt_struct, dt_strings, conf_path + '/kernel')
+
+ loaded_kernel = str(loaded_kernel[:-1], 'utf-8')
+
+ # determine root node start and end:
+ (rt_node_start, rt_node_end) = (determine_offset(dt_struct, dt_strings, '/'))
+ if (rt_node_start is None) or (rt_node_end is None):
+ print('Fatal error, unable to find root node')
+ sys.exit()
+
+ # duplicate the whole tree
+ duplicated_node = dt_struct[rt_node_start:rt_node_end]
+
+ # dchange root name (empty name) to fake root name
+ new_dup = change_node_name(duplicated_node, dt_strings, '/', FAKE_ROOT_NAME)
+
+ dt_struct = new_dup + dt_struct
+
+ # change the value of /<fake_root_name>/configs/<default_config_name>/kernel
+ # so our modified kernel will be loaded
+ base = '/' + str(FAKE_ROOT_NAME, 'utf-8')
+ value_path = base + conf_path+'/kernel'
+ dt_struct = change_property_value(dt_struct, dt_strings, value_path,
+ EVIL_KERNEL_NAME + b'\0')
+
+ # change the node of the /<fake_root_name>/images/<original_kernel_name>
+ images_path = base + '/images/'
+ node_path = images_path + loaded_kernel
+ dt_struct = change_node_name(dt_struct, dt_strings, node_path,
+ EVIL_KERNEL_NAME)
+
+ # change the content of the kernel being loaded
+ data_path = images_path + str(EVIL_KERNEL_NAME, 'utf-8') + '/data'
+ dt_struct = change_property_value(dt_struct, dt_strings, data_path,
+ kernel_content, required=False)
+
+ # update the digest value
+ hash_path = images_path + str(EVIL_KERNEL_NAME, 'utf-8') + '/hash-1/value'
+ dt_struct = change_property_value(dt_struct, dt_strings, hash_path,
+ kernel_digest)
+
+ return dt_struct
+
+def add_evil_node(in_fname, out_fname, kernel_fname, attack):
+ """Add an evil node to the devicetree
+
+ Args:
+ in_fname (str): Filename of input devicetree
+ out_fname (str): Filename to write modified devicetree to
+ kernel_fname (str): Filename of kernel data to add to evil node
+ attack (str): Attack type ('fakeroot' or 'kernel@')
+
+ Raises:
+ ValueError: Unknown attack name
+ """
+ if attack == 'fakeroot':
+ attack = FAKE_ROOT_ATTACK
+ elif attack == 'kernel@':
+ attack = KERNEL_AT
+ else:
+ raise ValueError('Unknown attack name!')
+
+ with open(in_fname, 'rb') as fin:
+ input_data = fin.read()
+
+ hdr = input_data[0:0x28]
+
+ offset = 0
+ magic = struct.unpack('>I', hdr[offset:offset + 4])[0]
+ if magic != MAGIC:
+ raise ValueError('Wrong magic!')
+
+ offset += 4
+ (totalsize, off_dt_struct, off_dt_strings, off_mem_rsvmap, version,
+ last_comp_version, boot_cpuid_phys, size_dt_strings,
+ size_dt_struct) = struct.unpack('>IIIIIIIII', hdr[offset:offset + 36])
+
+ rsv_map = input_data[off_mem_rsvmap:off_dt_struct]
+ dt_struct = input_data[off_dt_struct:off_dt_struct + size_dt_struct]
+ dt_strings = input_data[off_dt_strings:off_dt_strings + size_dt_strings]
+
+ with open(kernel_fname, 'rb') as kernel_file:
+ kernel_content = kernel_file.read()
+
+ # computing inserted kernel hash
+ val = hashlib.sha1()
+ val.update(kernel_content)
+ hash_digest = val.digest()
+
+ if attack == FAKE_ROOT_ATTACK:
+ dt_struct = fake_root_node_attack(dt_struct, dt_strings, kernel_content,
+ hash_digest)
+ elif attack == KERNEL_AT:
+ dt_struct = kernel_at_attack(dt_struct, dt_strings, kernel_content,
+ hash_digest)
+
+ # now rebuild the new file
+ size_dt_strings = len(dt_strings)
+ size_dt_struct = len(dt_struct)
+ totalsize = 0x28 + len(rsv_map) + size_dt_struct + size_dt_strings
+ off_mem_rsvmap = 0x28
+ off_dt_struct = off_mem_rsvmap + len(rsv_map)
+ off_dt_strings = off_dt_struct + len(dt_struct)
+
+ header = struct.pack('>IIIIIIIIII', MAGIC, totalsize, off_dt_struct,
+ off_dt_strings, off_mem_rsvmap, version,
+ last_comp_version, boot_cpuid_phys, size_dt_strings,
+ size_dt_struct)
+
+ with open(out_fname, 'wb') as output_file:
+ output_file.write(header)
+ output_file.write(rsv_map)
+ output_file.write(dt_struct)
+ output_file.write(dt_strings)
+
+if __name__ == '__main__':
+ if len(sys.argv) != 5:
+ print('usage: %s <input_filename> <output_filename> <kernel_binary> <attack_name>' %
+ sys.argv[0])
+ print('valid attack names: [fakeroot, kernel@]')
+ sys.exit(1)
+
+ add_evil_node(sys.argv[1:])
"""
Maliciously manipulates the structure to create a crafted FIT file
"""
- # locate /images/kernel@1 (frankly, it just expects it to be the first one)
+ # locate /images/kernel-1 (frankly, it just expects it to be the first one)
kernel_node = root[0][0]
# clone it to save time filling all the properties
fake_kernel = kernel_node.clone()
# rename the node
- fake_kernel.name = b'kernel@2'
+ fake_kernel.name = b'kernel-2'
# get rid of signatures/hashes
fake_kernel.children = []
# NOTE: this simply replaces the first prop... either description or data
root[0].children.append(fake_kernel)
# modify the default configuration
- root[1].props[0].value = b'conf@2\x00'
+ root[1].props[0].value = b'conf-2\x00'
# clone the first (only?) configuration
fake_conf = root[1][0].clone()
# rename and change kernel and fdt properties to select the crafted kernel
- fake_conf.name = b'conf@2'
- fake_conf.props[0].value = b'kernel@2\x00'
- fake_conf.props[1].value = b'fdt@1\x00'
+ fake_conf.name = b'conf-2'
+ fake_conf.props[0].value = b'kernel-2\x00'
+ fake_conf.props[1].value = b'fdt-1\x00'
# insert the new configuration under /configurations
root[1].children.append(fake_conf)
#ifdef CONFIG_SANDBOX
#include <asm/state.h>
#endif
+#include <asm/global_data.h>
#include <test/test.h>
#include <test/ut.h>
term = threading.Thread(target=self.queue.join)
term.setDaemon(True)
term.start()
- while term.isAlive():
+ while term.is_alive():
term.join(100)
# Wait until we have processed all output
int fit_verify_header(unsigned char *ptr, int image_size,
struct image_tool_params *params)
{
- if (fdt_check_header(ptr) != EXIT_SUCCESS || !fit_check_format(ptr))
+ if (fdt_check_header(ptr) != EXIT_SUCCESS ||
+ fit_check_format(ptr, IMAGE_SIZE_INVAL))
return EXIT_FAILURE;
return EXIT_SUCCESS;
/* Indent string is defined in header image.h */
p = IMAGE_INDENT_STRING;
- if (!fit_check_format(fit)) {
+ if (fit_check_format(fit, IMAGE_SIZE_INVAL)) {
printf("Bad FIT image format\n");
return -1;
}
#define debug(fmt,args...)
#endif /* MKIMAGE_DEBUG */
+#define log_debug(fmt, args...) debug(fmt, ##args)
+
static inline void *map_sysmem(ulong paddr, unsigned long len)
{
return (void *)(uintptr_t)paddr;
projects / platform / kernel / u-boot.git / commitdiff