board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <env_internal.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <net.h>
  16 #include <sata.h>
  17 #include <ahci.h>
  18 #include <scsi.h>
  19 #include <malloc.h>
  20 #include <wdt.h>
  21 #include <asm/arch/clk.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/psu_init_gpl.h>
  25 #include <asm/cache.h>
  26 #include <asm/global_data.h>
  27 #include <asm/io.h>
  28 #include <asm/ptrace.h>
  29 #include <dm/device.h>
  30 #include <dm/uclass.h>
  31 #include <usb.h>
  32 #include <dwc3-uboot.h>
  33 #include <zynqmppl.h>
  34 #include <zynqmp_firmware.h>
  35 #include <g_dnl.h>
  36 #include <linux/bitops.h>
  37 #include <linux/delay.h>
  38 #include <linux/sizes.h>
  39 #include "../common/board.h"
  40
  41 #include "pm_cfg_obj.h"
  42
  43 #define ZYNQMP_VERSION_SIZE     7
  44 #define EFUSE_VCU_DIS_MASK      0x100
  45 #define EFUSE_VCU_DIS_SHIFT     8
  46 #define EFUSE_GPU_DIS_MASK      0x20
  47 #define EFUSE_GPU_DIS_SHIFT     5
  48 #define IDCODE2_PL_INIT_MASK    0x200
  49 #define IDCODE2_PL_INIT_SHIFT   9
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
  54 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  55
  56 enum {
  57         ZYNQMP_VARIANT_EG = BIT(0U),
  58         ZYNQMP_VARIANT_EV = BIT(1U),
  59         ZYNQMP_VARIANT_CG = BIT(2U),
  60         ZYNQMP_VARIANT_DR = BIT(3U),
  61 };
  62
  63 static const struct {
  64         u32 id;
  65         u8 device;
  66         u8 variants;
  67 } zynqmp_devices[] = {
  68         {
  69                 .id = 0x04711093,
  70                 .device = 2,
  71                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  72         },
  73         {
  74                 .id = 0x04710093,
  75                 .device = 3,
  76                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  77         },
  78         {
  79                 .id = 0x04721093,
  80                 .device = 4,
  81                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  82                         ZYNQMP_VARIANT_EV,
  83         },
  84         {
  85                 .id = 0x04720093,
  86                 .device = 5,
  87                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  88                         ZYNQMP_VARIANT_EV,
  89         },
  90         {
  91                 .id = 0x04739093,
  92                 .device = 6,
  93                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  94         },
  95         {
  96                 .id = 0x04730093,
  97                 .device = 7,
  98                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  99                         ZYNQMP_VARIANT_EV,
 100         },
 101         {
 102                 .id = 0x04738093,
 103                 .device = 9,
 104                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 105         },
 106         {
 107                 .id = 0x04740093,
 108                 .device = 11,
 109                 .variants = ZYNQMP_VARIANT_EG,
 110         },
 111         {
 112                 .id = 0x04750093,
 113                 .device = 15,
 114                 .variants = ZYNQMP_VARIANT_EG,
 115         },
 116         {
 117                 .id = 0x04759093,
 118                 .device = 17,
 119                 .variants = ZYNQMP_VARIANT_EG,
 120         },
 121         {
 122                 .id = 0x04758093,
 123                 .device = 19,
 124                 .variants = ZYNQMP_VARIANT_EG,
 125         },
 126         {
 127                 .id = 0x047E1093,
 128                 .device = 21,
 129                 .variants = ZYNQMP_VARIANT_DR,
 130         },
 131         {
 132                 .id = 0x047E3093,
 133                 .device = 23,
 134                 .variants = ZYNQMP_VARIANT_DR,
 135         },
 136         {
 137                 .id = 0x047E5093,
 138                 .device = 25,
 139                 .variants = ZYNQMP_VARIANT_DR,
 140         },
 141         {
 142                 .id = 0x047E4093,
 143                 .device = 27,
 144                 .variants = ZYNQMP_VARIANT_DR,
 145         },
 146         {
 147                 .id = 0x047E0093,
 148                 .device = 28,
 149                 .variants = ZYNQMP_VARIANT_DR,
 150         },
 151         {
 152                 .id = 0x047E2093,
 153                 .device = 29,
 154                 .variants = ZYNQMP_VARIANT_DR,
 155         },
 156         {
 157                 .id = 0x047E6093,
 158                 .device = 39,
 159                 .variants = ZYNQMP_VARIANT_DR,
 160         },
 161         {
 162                 .id = 0x047FD093,
 163                 .device = 43,
 164                 .variants = ZYNQMP_VARIANT_DR,
 165         },
 166         {
 167                 .id = 0x047F8093,
 168                 .device = 46,
 169                 .variants = ZYNQMP_VARIANT_DR,
 170         },
 171         {
 172                 .id = 0x047FF093,
 173                 .device = 47,
 174                 .variants = ZYNQMP_VARIANT_DR,
 175         },
 176         {
 177                 .id = 0x047FB093,
 178                 .device = 48,
 179                 .variants = ZYNQMP_VARIANT_DR,
 180         },
 181         {
 182                 .id = 0x047FE093,
 183                 .device = 49,
 184                 .variants = ZYNQMP_VARIANT_DR,
 185         },
 186 };
 187
 188 static char *zynqmp_get_silicon_idcode_name(void)
 189 {
 190         u32 i;
 191         u32 idcode, idcode2;
 192         char name[ZYNQMP_VERSION_SIZE];
 193         u32 ret_payload[PAYLOAD_ARG_CNT];
 194         int ret;
 195
 196         ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
 197         if (ret) {
 198                 debug("%s: Getting chipid failed\n", __func__);
 199                 return "unknown";
 200         }
 201
 202         /*
 203          * Firmware returns:
 204          * payload[0][31:0]  = status of the operation
 205          * payload[1]] = IDCODE
 206          * payload[2][19:0]  = Version
 207          * payload[2][28:20] = EXTENDED_IDCODE
 208          * payload[2][29] = PL_INIT
 209          */
 210
 211         idcode  = ret_payload[1];
 212         idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 213         debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
 214               idcode2);
 215
 216         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 217                 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
 218                         break;
 219         }
 220
 221         if (i >= ARRAY_SIZE(zynqmp_devices))
 222                 return "unknown";
 223
 224         /* Add device prefix to the name */
 225         ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
 226                        zynqmp_devices[i].device);
 227         if (ret < 0)
 228                 return "unknown";
 229
 230         if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
 231                 /* Devices with EV variant might be EG/CG/EV family */
 232                 if (idcode2 & IDCODE2_PL_INIT_MASK) {
 233                         u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
 234                                       EFUSE_VCU_DIS_SHIFT) << 1 |
 235                                      ((idcode2 & EFUSE_GPU_DIS_MASK) >>
 236                                       EFUSE_GPU_DIS_SHIFT);
 237
 238                         /*
 239                          * Get family name based on extended idcode values as
 240                          * determined on UG1087, EXTENDED_IDCODE register
 241                          * description
 242                          */
 243                         switch (family) {
 244                         case 0x00:
 245                                 strncat(name, "ev", 2);
 246                                 break;
 247                         case 0x10:
 248                                 strncat(name, "eg", 2);
 249                                 break;
 250                         case 0x11:
 251                                 strncat(name, "cg", 2);
 252                                 break;
 253                         default:
 254                                 /* Do not append family name*/
 255                                 break;
 256                         }
 257                 } else {
 258                         /*
 259                          * When PL powered down the VCU Disable efuse cannot be
 260                          * read. So, ignore the bit and just findout if it is CG
 261                          * or EG/EV variant.
 262                          */
 263                         strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
 264                                 "e", 2);
 265                 }
 266         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
 267                 /* Devices with CG variant might be EG or CG family */
 268                 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
 269         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
 270                 strncat(name, "eg", 2);
 271         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
 272                 strncat(name, "dr", 2);
 273         } else {
 274                 debug("Variant not identified\n");
 275         }
 276
 277         return strdup(name);
 278 }
 279 #endif
 280
 281 int board_early_init_f(void)
 282 {
 283 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 284         int ret;
 285
 286         ret = psu_init();
 287         if (ret)
 288                 return ret;
 289
 290         /* Delay is required for clocks to be propagated */
 291         udelay(1000000);
 292 #endif
 293
 294 #ifdef CONFIG_DEBUG_UART
 295         /* Uart debug for sure */
 296         debug_uart_init();
 297         puts("Debug uart enabled\n"); /* or printch() */
 298 #endif
 299
 300         return 0;
 301 }
 302
 303 static int multi_boot(void)
 304 {
 305         u32 multiboot;
 306
 307         multiboot = readl(&csu_base->multi_boot);
 308
 309         printf("Multiboot:\t%d\n", multiboot);
 310
 311         return 0;
 312 }
 313
 314 #define PS_SYSMON_ANALOG_BUS_VAL        0x3210
 315 #define PS_SYSMON_ANALOG_BUS_REG        0xFFA50914
 316
 317 int board_init(void)
 318 {
 319 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 320         struct udevice *dev;
 321
 322         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 323         if (!dev)
 324                 panic("PMU Firmware device not found - Enable it");
 325 #endif
 326
 327 #if defined(CONFIG_SPL_BUILD)
 328         /* Check *at build time* if the filename is an non-empty string */
 329         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 330                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 331                                                 zynqmp_pm_cfg_obj_size);
 332         printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
 333 #else
 334         if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
 335                 xilinx_read_eeprom();
 336 #endif
 337
 338         printf("EL Level:\tEL%d\n", current_el());
 339
 340         /* Bug in ROM sets wrong value in this register */
 341         writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 342
 343 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 344         zynqmppl.name = zynqmp_get_silicon_idcode_name();
 345         printf("Chip ID:\t%s\n", zynqmppl.name);
 346         fpga_init();
 347         fpga_add(fpga_xilinx, &zynqmppl);
 348 #endif
 349
 350         if (current_el() == 3)
 351                 multi_boot();
 352
 353         return 0;
 354 }
 355
 356 int board_early_init_r(void)
 357 {
 358         u32 val;
 359
 360         if (current_el() != 3)
 361                 return 0;
 362
 363         val = readl(&crlapb_base->timestamp_ref_ctrl);
 364         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 365
 366         if (!val) {
 367                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 368                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 369                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 370
 371                 /* Program freq register in System counter */
 372                 writel(zynqmp_get_system_timer_freq(),
 373                        &iou_scntr_secure->base_frequency_id_register);
 374                 /* And enable system counter */
 375                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 376                        &iou_scntr_secure->counter_control_register);
 377         }
 378         return 0;
 379 }
 380
 381 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 382                          char *const argv[])
 383 {
 384         int ret = 0;
 385
 386         if (current_el() > 1) {
 387                 smp_kick_all_cpus();
 388                 dcache_disable();
 389                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 390                                     ES_TO_AARCH64);
 391         } else {
 392                 printf("FAIL: current EL is not above EL1\n");
 393                 ret = EINVAL;
 394         }
 395         return ret;
 396 }
 397
 398 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 399 int dram_init_banksize(void)
 400 {
 401         int ret;
 402
 403         ret = fdtdec_setup_memory_banksize();
 404         if (ret)
 405                 return ret;
 406
 407         mem_map_fill();
 408
 409         return 0;
 410 }
 411
 412 int dram_init(void)
 413 {
 414         if (fdtdec_setup_mem_size_base() != 0)
 415                 return -EINVAL;
 416
 417         return 0;
 418 }
 419 #else
 420 int dram_init_banksize(void)
 421 {
 422         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 423         gd->bd->bi_dram[0].size = get_effective_memsize();
 424
 425         mem_map_fill();
 426
 427         return 0;
 428 }
 429
 430 int dram_init(void)
 431 {
 432         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 433                                     CONFIG_SYS_SDRAM_SIZE);
 434
 435         return 0;
 436 }
 437 #endif
 438
 439 void reset_cpu(ulong addr)
 440 {
 441 }
 442
 443 static u8 __maybe_unused zynqmp_get_bootmode(void)
 444 {
 445         u8 bootmode;
 446         u32 reg = 0;
 447         int ret;
 448
 449         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 450         if (ret)
 451                 return -EINVAL;
 452
 453         if (reg >> BOOT_MODE_ALT_SHIFT)
 454                 reg >>= BOOT_MODE_ALT_SHIFT;
 455
 456         bootmode = reg & BOOT_MODES_MASK;
 457
 458         return bootmode;
 459 }
 460
 461 #if defined(CONFIG_BOARD_LATE_INIT)
 462 static const struct {
 463         u32 bit;
 464         const char *name;
 465 } reset_reasons[] = {
 466         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 467         { RESET_REASON_SOFT, "SOFT" },
 468         { RESET_REASON_SRST, "SRST" },
 469         { RESET_REASON_PSONLY, "PS-ONLY" },
 470         { RESET_REASON_PMU, "PMU" },
 471         { RESET_REASON_INTERNAL, "INTERNAL" },
 472         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 473         {}
 474 };
 475
 476 static int reset_reason(void)
 477 {
 478         u32 reg;
 479         int i, ret;
 480         const char *reason = NULL;
 481
 482         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 483         if (ret)
 484                 return -EINVAL;
 485
 486         puts("Reset reason:\t");
 487
 488         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 489                 if (reg & reset_reasons[i].bit) {
 490                         reason = reset_reasons[i].name;
 491                         printf("%s ", reset_reasons[i].name);
 492                         break;
 493                 }
 494         }
 495
 496         puts("\n");
 497
 498         env_set("reset_reason", reason);
 499
 500         return 0;
 501 }
 502
 503 static int set_fdtfile(void)
 504 {
 505         char *compatible, *fdtfile;
 506         const char *suffix = ".dtb";
 507         const char *vendor = "xilinx/";
 508         int fdt_compat_len;
 509
 510         if (env_get("fdtfile"))
 511                 return 0;
 512
 513         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
 514                                          &fdt_compat_len);
 515         if (compatible && fdt_compat_len) {
 516                 char *name;
 517
 518                 debug("Compatible: %s\n", compatible);
 519
 520                 name = strchr(compatible, ',');
 521                 if (!name)
 522                         return -EINVAL;
 523
 524                 name++;
 525
 526                 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
 527                                  strlen(suffix) + 1);
 528                 if (!fdtfile)
 529                         return -ENOMEM;
 530
 531                 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
 532
 533                 env_set("fdtfile", fdtfile);
 534                 free(fdtfile);
 535         }
 536
 537         return 0;
 538 }
 539
 540 int board_late_init(void)
 541 {
 542         u8 bootmode;
 543         struct udevice *dev;
 544         int bootseq = -1;
 545         int bootseq_len = 0;
 546         int env_targets_len = 0;
 547         const char *mode;
 548         char *new_targets;
 549         char *env_targets;
 550         int ret;
 551
 552 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 553         usb_ether_init();
 554 #endif
 555
 556         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 557                 debug("Saved variables - Skipping\n");
 558                 return 0;
 559         }
 560
 561         if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
 562                 return 0;
 563
 564         ret = set_fdtfile();
 565         if (ret)
 566                 return ret;
 567
 568         bootmode = zynqmp_get_bootmode();
 569
 570         puts("Bootmode: ");
 571         switch (bootmode) {
 572         case USB_MODE:
 573                 puts("USB_MODE\n");
 574                 mode = "usb";
 575                 env_set("modeboot", "usb_dfu_spl");
 576                 break;
 577         case JTAG_MODE:
 578                 puts("JTAG_MODE\n");
 579                 mode = "jtag pxe dhcp";
 580                 env_set("modeboot", "jtagboot");
 581                 break;
 582         case QSPI_MODE_24BIT:
 583         case QSPI_MODE_32BIT:
 584                 mode = "qspi0";
 585                 puts("QSPI_MODE\n");
 586                 env_set("modeboot", "qspiboot");
 587                 break;
 588         case EMMC_MODE:
 589                 puts("EMMC_MODE\n");
 590                 if (uclass_get_device_by_name(UCLASS_MMC,
 591                                               "mmc@ff160000", &dev) &&
 592                     uclass_get_device_by_name(UCLASS_MMC,
 593                                               "sdhci@ff160000", &dev)) {
 594                         puts("Boot from EMMC but without SD0 enabled!\n");
 595                         return -1;
 596                 }
 597                 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
 598
 599                 mode = "mmc";
 600                 bootseq = dev_seq(dev);
 601                 break;
 602         case SD_MODE:
 603                 puts("SD_MODE\n");
 604                 if (uclass_get_device_by_name(UCLASS_MMC,
 605                                               "mmc@ff160000", &dev) &&
 606                     uclass_get_device_by_name(UCLASS_MMC,
 607                                               "sdhci@ff160000", &dev)) {
 608                         puts("Boot from SD0 but without SD0 enabled!\n");
 609                         return -1;
 610                 }
 611                 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
 612
 613                 mode = "mmc";
 614                 bootseq = dev_seq(dev);
 615                 env_set("modeboot", "sdboot");
 616                 break;
 617         case SD1_LSHFT_MODE:
 618                 puts("LVL_SHFT_");
 619                 /* fall through */
 620         case SD_MODE1:
 621                 puts("SD_MODE1\n");
 622                 if (uclass_get_device_by_name(UCLASS_MMC,
 623                                               "mmc@ff170000", &dev) &&
 624                     uclass_get_device_by_name(UCLASS_MMC,
 625                                               "sdhci@ff170000", &dev)) {
 626                         puts("Boot from SD1 but without SD1 enabled!\n");
 627                         return -1;
 628                 }
 629                 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
 630
 631                 mode = "mmc";
 632                 bootseq = dev_seq(dev);
 633                 env_set("modeboot", "sdboot");
 634                 break;
 635         case NAND_MODE:
 636                 puts("NAND_MODE\n");
 637                 mode = "nand0";
 638                 env_set("modeboot", "nandboot");
 639                 break;
 640         default:
 641                 mode = "";
 642                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 643                 break;
 644         }
 645
 646         if (bootseq >= 0) {
 647                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 648                 debug("Bootseq len: %x\n", bootseq_len);
 649                 env_set_hex("bootseq", bootseq);
 650         }
 651
 652         /*
 653          * One terminating char + one byte for space between mode
 654          * and default boot_targets
 655          */
 656         env_targets = env_get("boot_targets");
 657         if (env_targets)
 658                 env_targets_len = strlen(env_targets);
 659
 660         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 661                              bootseq_len);
 662         if (!new_targets)
 663                 return -ENOMEM;
 664
 665         if (bootseq >= 0)
 666                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 667                         env_targets ? env_targets : "");
 668         else
 669                 sprintf(new_targets, "%s %s", mode,
 670                         env_targets ? env_targets : "");
 671
 672         env_set("boot_targets", new_targets);
 673
 674         reset_reason();
 675
 676         return board_late_init_xilinx();
 677 }
 678 #endif
 679
 680 int checkboard(void)
 681 {
 682         puts("Board: Xilinx ZynqMP\n");
 683         return 0;
 684 }
 685
 686 enum env_location env_get_location(enum env_operation op, int prio)
 687 {
 688         u32 bootmode = zynqmp_get_bootmode();
 689
 690         if (prio)
 691                 return ENVL_UNKNOWN;
 692
 693         switch (bootmode) {
 694         case EMMC_MODE:
 695         case SD_MODE:
 696         case SD1_LSHFT_MODE:
 697         case SD_MODE1:
 698                 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
 699                         return ENVL_FAT;
 700                 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
 701                         return ENVL_EXT4;
 702                 return ENVL_UNKNOWN;
 703         case NAND_MODE:
 704                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
 705                         return ENVL_NAND;
 706                 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
 707                         return ENVL_UBI;
 708                 return ENVL_UNKNOWN;
 709         case QSPI_MODE_24BIT:
 710         case QSPI_MODE_32BIT:
 711                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
 712                         return ENVL_SPI_FLASH;
 713                 return ENVL_UNKNOWN;
 714         case JTAG_MODE:
 715         default:
 716                 return ENVL_NOWHERE;
 717         }
 718 }