+commit 369d0aa9674b65c83f8553b9bcf9d207dc369223
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Feb 18 17:43:59 2009 -0600
+
+ sata_sil3114: fix compiler warning
+
+ judging from other printfs in the same file, it seems ata should be
+ postpended with the interface number, not the address of the global
+ port variable. Fixes this for current u-boot-mpc83xx tree:
+
+ Configuring for MPC8349ITX board...
+ sata_sil3114.c: In function 'sata_bus_softreset':
+ sata_sil3114.c:99: warning: format '%u' expects type 'unsigned int', but argument 2 has type 'struct sata_port *'
+ sata_sil3114.c:108: warning: format '%u' expects type 'unsigned int', but argument 2 has type 'struct sata_port *'
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit f5675aa5ceeef30740970ab8ca0c8cbc324945cd
+Author: Ron Madrid <ron_madrid@sbcglobal.net>
+Date: Wed Feb 18 14:30:44 2009 -0800
+
+ Create configuration option for restricted ns16550 functions
+
+ This patch will create a configuration option for a minimum configuration for
+ the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new
+ configuration option to the SIMPC8313.h config file in order to fix the NAND
+ bootstrap build error. This option will exclude all functions with exception of
+ NS16550_putc and NS16550_init. This will be used primarily to save space and
+ remove unused code from builds in which space is limited.
+
+ Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
+
+commit 7b0bc0219db8981613259473cf19699ac259b4fb
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Wed Feb 18 16:14:29 2009 -0600
+
+ mkconfig: include board config.h before asm/config.h
+
+ swapping the include order suppresses warnings for board configs
+ that define their own CONFIG_MAX_MEM_MAPPED:
+
+ In file included from /home/r1aaha/git/u-boot/include/config.h:5,
+ from /home/r1aaha/git/u-boot/include/common.h:35,
+ from simpc8313.c:26:
+ /home/r1aaha/git/u-boot/include/configs/SIMPC8313.h:81:1: warning:
+ "CONFIG_MAX_MEM_MAPPED" redefined
+ In file included from /home/r1aaha/git/u-boot/include/config.h:4,
+ from /home/r1aaha/git/u-boot/include/common.h:35,
+ from simpc8313.c:26:
+ /home/r1aaha/git/u-boot/include/asm/config.h:28:1: warning: this is
+ the location of the previous definition
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit b8845abdc0dcf20d0944e965153f5ae7a9c3077c
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Feb 18 21:35:38 2009 +0100
+
+ Fix build errors after making flash_get_info() non-static
+
+ Fix for these build problems:
+ error: static declaration of 'flash_get_info' follows non-static declaration
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5f0320108870e5d62983d1d5c13a2a087dddf686
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Feb 1 17:07:52 2009 +0100
+
+ common/console: avoid ifdef CONFIG_CONSOLE_MUX when it's possible
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit ec6f14994602276660f7264c6ab3b91ef1f7614d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Feb 1 17:07:51 2009 +0100
+
+ common/console: coding style cleanup
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit daaf74f176b548dfd34a9990231f4189201d57ba
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jan 29 20:02:23 2009 -0500
+
+ mpc8xx_pcmcia: move CONFIG_8xx out of .c file and into Makefile
+
+ Move the CONFIG_8xx mpc8xx_pcmcia.c protection out of the C file and
+ into the Makefile so we avoid pointless compiling of the file.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 7bd2722e890bc877a3c057d7ccddc80451c99939
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jan 29 20:02:07 2009 -0500
+
+ disk: convert part_* files to COBJ-$(CONFIG_XXX) style
+
+ Move the CONFIG_XXX out of the part_XXX.c file and into Makefile to
+ avoid pointless compiles.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit f05fa9205e04986176dc7ab8b710bcb5fbe9f338
+Author: Petri Lehtinen <petri.lehtinen@inoi.fi>
+Date: Thu Jan 29 10:35:40 2009 +0200
+
+ include/image.h: Ease grepping of image_* functions
+
+ Because the functions have been defined using macros, grepping for
+ their definitions is not possible. This patch adds the real function
+ names in comments.
+
+ Signed-off-by: Petri Lehtinen <petri.lehtinen@inoi.fi>
+ Acked-by: Mike Frysinger <vapier@gentoo.org>
+
+commit bdab39d358e63aa47f400a8a76b8d5f283842df3
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Jan 28 19:08:14 2009 -0500
+
+ rename CONFIG_CMD_ENV to CONFIG_CMD_SAVEENV
+
+ The CONFIG_CMD_ENV option controls enablement of the `saveenv` command
+ rather than a generic "env" command, or anything else related to the
+ environment. So, let's make sure the define is named accordingly.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8b0592b89e0f9f81c9e150c81d96f8a43e4d6101
+Author: Valeriy Glushkov <gvv@lstec.com>
+Date: Fri Jan 23 20:02:17 2009 +0200
+
+ disable imls command if no flash is defined
+
+ Default CONFIG_CMD_IMLS must be disabled when CONFIG_SYS_NO_FLASH is defined
+
+ Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
+
+commit 923aa48126259c13de95131203f1d28bfa5cb889
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Jan 23 13:27:18 2009 +0100
+
+ API: Improve glue mid-layer of the API demo application.
+
+ - Extend ub_dev_read() and ub_dev_recv() so they return the length actually
+ read, which allows for better control and error handling (this introduces
+ additional error code API_ESYSC returned by the glue mid-layer).
+
+ - Clean up definitions naming and usage.
+
+ - Other minor cosmetics.
+
+ Note these changes do not touch the API proper, so the interface between
+ U-Boot and standalone applications remains unchanged.
+
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 44a94e596ba0f6d0951b165403c520bf55b1c56f
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Jan 23 13:27:17 2009 +0100
+
+ API: Only output test data when reading was successful.
+
+ Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+
+commit 7fb6c4f9b06c5539043c8bfc6565710b8090841d
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Jan 23 13:27:16 2009 +0100
+
+ API: Provide syscall entry point for the ARM architecture.
+
+ Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+ Acked-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit b84d7d8f1e1066f810866304a16a3583f88e7c98
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Jan 23 13:27:15 2009 +0100
+
+ API: Use stack pointer as API signature search hint in the glue layer.
+
+ De-hardcode range in RAM we search for the API signature. Instead use the stack
+ pointer as a hint to narrow down the range in which the signature could reside
+ (it is malloc'ed on the U-Boot heap, and is hoped to remain in some proximity
+ from stack area). Adjust PowerPC code in API demo to the new scheme.
+
+ Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+ Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit 86b4bafdfaf669ede8fd99044abc7e27ea29b4f5
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Feb 17 10:26:38 2009 +0100
+
+ TQM8260: fix locations of kernel and ramdisk images in flash
+
+ After introducing redundant environment the kernel images was
+ overlapping with environment.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e1ac387f4645499746856adc1aeaa9787da2eca6
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Oct 30 16:50:14 2008 -0500
+
+ 83xx: Add eSDHC support on 8379 EMDS board
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 80522dc8369a89938369fbcee572e662373bc9a3
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Oct 30 16:51:33 2008 -0500
+
+ 85xx: Add eSDHC support for 8536 DS
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 50586ef24ed5caf6ce5591df76f355009da2cd79
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Oct 30 16:47:16 2008 -0500
+
+ Add support for the Freescale eSDHC found on 8379 and 8536 SoCs
+
+ This uses the new MMC framework
+
+ Some contributions by Dave Liu <daveliu@freescale.com>
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 272cc70b211e945e4413122aa73868f6ada732a5
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Oct 30 16:41:01 2008 -0500
+
+ Add MMC Framework
+
+ Here's a new framework (based roughly off the linux one) for managing
+ MMC controllers. It handles all of the standard SD/MMC transactions,
+ leaving the host drivers to implement only what is necessary to
+ deal with their specific hardware.
+
+ This also hooks the infrastructure into the PowerPC board code
+ (similar to how the ethernet infrastructure now hooks in)
+
+ Some of this code was contributed by Dave Liu <daveliu@freescale.com>
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 1de97f9856f697380cc504126ab92561ed238803
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Oct 30 16:31:39 2008 -0500
+
+ Eliminated arch-specific mmc header requirement
+
+ The current MMC infrastructure relies on the existence of an
+ arch-specific header file. This isn't necessary, and a couple
+ drivers were forced to implement dummy files to meet this requirement.
+ Instead, we move the stuff in those header files into a more appropriate
+ place, and eliminate the stubs and the #include of asm/arch/mmc.h
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit abb5466ccf4ce50f412d459586f4f4b81cb73ac3
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Oct 30 16:21:00 2008 -0500
+
+ Convert mmc_init to mmc_legacy_init
+
+ This is to get it out of the way of incoming MMC framework
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit b2e2ed0233a5ef299361abec4fbdaefb63456eff
+Author: Andy Fleming <afleming@freescale.com>
+Date: Thu Oct 30 16:19:25 2008 -0500
+
+ Eliminate support for using MMC as memory
+
+ MMC cards are not memory, so we stop treating them that way.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit e1be0d25ecf494ae81245ca438738ba839d6329b
+Author: Poonam_Aggrwal-b10812 <b10812@freescale.com>
+Date: Sun Jan 4 08:46:38 2009 +0530
+
+ 32bit BUg fix for DDR2 on 8572
+
+ This errata fix is required for 32 bit DDR2 controller on 8572.
+ May also be required for P10XX20XX platforms
+
+ Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
+
+commit e0c4fac79d4d74572ddd43f75e7189cecca8d0ad
+Author: Andy Fleming <afleming@freescale.com>
+Date: Mon Feb 16 09:40:20 2009 -0600
+
+ TQM85xx: Fix a couple warnings in TQM8548 build
+
+ The ecm variable in sdram.c was being declared for all 8548, but only
+ used by specific 8548 boards, so we make that variable require those
+ specific boards, too
+
+ The nand code was using an index "i" into a table, and then re-using "i"
+ to set addresses for each upm. However, then it relied on the old value
+ of i still being there to enable things. Changed the second "i" to "j"
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit cf07a5baece0ecfc5284cfda8a4e68eaf92782f8
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:26 2009 +0100
+
+ MPC85xx: TQM8548: workaround for erratum DDR 19 and 20
+
+ This patch adds the workaround for erratum DDR20 according to MPC8548
+ Device Errata document, Rev. 1: "CKE signal may not function correctly
+ after assertion of HRESET". Furthermore, the bug DDR19 is fixed in
+ processor version 2.1 and the work-around must be removed.
+
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit 080408fdc71706adcb883d22125637c54f6010b1
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:25 2009 +0100
+
+ MPC85xx: TQM8548: use cache for AG and BE variants
+
+ This patch makes accesses to the system memory cachable by removing the
+ caching-inhibited and guarded flags from the relevant TLB entries for
+ the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards
+ are configured similarly.
+
+ This results in a big averall performace improvement. TFTP downloads,
+ NAND Flash accesses, kernel boots, etc. are much faster.
+
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit dc5f55d636d7bf21ba17758fac4b929ec4c059f2
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:24 2009 +0100
+
+ MPC85xx: TQM8548_AG: add 1 GiB DDR2-SDRAM configuration
+
+ This patch add support for the 1 GiB DDR2-SDRAM on the TQM8548_AG
+ module.
+
+ Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit 88b0e88d186479349e5a2b771e82775109e10fb4
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:23 2009 +0100
+
+ MPC85xx: TQM8548: fix SDRAM timing for 533 MHz
+
+ According to new TQM8548 timing specification:
+ Refresh Recovery: 34 -> 53 clocks
+ CKE pulse width: 1 -> 3 cycles
+ Window for four activities: 13 -> 14 cycles
+
+ Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit a865bcdac89278cac4dfc07dec8299403110499d
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:22 2009 +0100
+
+ MPC85xx: TQM8548: add support for the TQM8548_AG module
+
+ The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory,
+ CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module
+ with "$ make TQM8548_AG_config".
+
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit ad7ee5d43b0db94079d56521dabca25674f28747
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:21 2009 +0100
+
+ MPC85xx: TQM8548: add support for the TQM8548_BE module
+
+ The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN
+ interface. With NAND support, the image is significantly larger and
+ TEXT_BASE is adjusted accordingly. U-Boot can be built for this
+ module with "$ make TQM8548_BE_config".
+
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit a318234878c346e673b2ef8dc4b14b338fe7fc2b
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:20 2009 +0100
+
+ MPC85xx: TQM85xx: make standard PCI/PCI-X configurable
+
+ The TQM8548_AG module does not have the standard PCI/PCI-X interface
+ connected but just the PCI Express interface . So far it was not
+ possible to disable it without disabling the complete PCI interface
+ (CONFIG_PCI) including PCI Express.
+
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit 31ca9119c3186cec579b54d2a7a2b361b4d2b7bf
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date: Wed Feb 11 18:38:19 2009 +0100
+
+ MPC85xx: TQM85xx: fix flash protection for boot loader
+
+ As the reset vector is located at 0xfffffffc, all flash sectors from the
+ beginning of the U-Boot binary to 0xffffffff must be protected. On the
+ TQM8548-AG having small sectors at the end of the flash it happened that
+ the last two sector were not protected and an "erase all" left an
+ un-bootable system behind:
+
+ Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors
+ AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E
+ Erase timeout: 8192 ms, write timeout: 1 ms
+
+ FFFA0000 E RO FFFC0000 RO FFFE0000 RO FFFE4000 RO FFFE8000 RO
+ FFFEC000 RO FFFF0000 RO FFFF4000 RO FFFF8000 E FFFFC000
+
+ The same bug seems to be in drivers/mtd/cfi_flash.c:flash_init() and many
+ board BSPs as well.
+
+ Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit a1c8a719262151f97119e76166043ee3da3f97b2
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Feb 6 14:30:40 2009 -0600
+
+ 86xx: Update CPU info output on bootup
+
+ - Update style of 86xx CPU information on boot to more closely
+ match 85xx boards
+ - Fix detection of 8641/8641D
+ - Use strmhz() to display frequencies
+ - Display L1 information
+ - Display L2 cache size
+ - Fixed CPU/SVR version output
+
+ == Before ==
+ Freescale PowerPC
+ CPU:
+ Core: E600 Core 0, Version: 0.2, (0x80040202)
+ System: Unknown, Version: 2.1, (0x80900121)
+ Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
+ L2: Enabled
+ Board: X-ES XPedite5170 3U VPX SBC
+
+ == After ==
+ CPU: 8641D, Version: 2.1, (0x80900121)
+ Core: E600 Core 0, Version: 2.2, (0x80040202)
+ Clock Configuration:
+ CPU:1066.667 MHz, MPX:533.333 MHz
+ DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
+ L1: D-cache 32 KB enabled
+ I-cache 32 KB enabled
+ L2: 512 KB enabled
+ Board: X-ES XPedite5170 3U VPX SBC
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 22c00f8d7d454d77e759df58415d2d3f3d7e154c
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Thu Feb 5 11:25:24 2009 -0600
+
+ 86xx: Update Global Utilities structure
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 4ef630df773e45806d701bf5d25c328778bb4cde
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Thu Feb 5 11:25:25 2009 -0600
+
+ 86xx: Reset update
+
+ Update the 86xx reset sequence to try executing a board-specific reset
+ function. If the board-specific reset is not implemented or does not
+ succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
+ reset procedure than the previous method and allows all board
+ peripherals to be reset if needed.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit edf0e2524a8c6a3e91c009c496a0aa0ae89cd8ab
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Feb 10 23:53:40 2009 -0600
+
+ fsl-ddr: Allow system to boot if we have more than 4G of memory
+
+ Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
+ an error and hang. Instead of doing that since DDR is mapped in the
+ lowest priority LAWs we setup the DDR controller and the max amount
+ of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 8d949aff38cfb4388cbd73876e77bcd06d601f20
+Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+Date: Wed Jan 21 17:17:33 2009 -0600
+
+ mpc85xx: Add support for the P2020
+
+ Added various p2020 processor specific details:
+ * SVR for p2020, p2020E
+ * immap updates for LAWs and DDR on p2020
+ * LAW defines related to p2020
+
+ Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit cb69e4de8702e108324e1c40363f30ef6f2e2918
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Feb 10 17:36:15 2009 -0600
+
+ 85xx: print boot header info to distinquish 36-bit addr map on MPC8572 DS
+
+ Added some info that is printed out when we boot to distiquish if we
+ built MPC8572DS_config vs MPC8572DS_36BIT_config since they have
+ different address maps.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit feede8b07013b33fca8dd2a916b3ac86bf4d4c0a
+Author: Andy Fleming <afleming@freescale.com>
+Date: Fri Dec 5 20:10:22 2008 -0600
+
+ Fixup SGMII PHY ids in the device tree
+
+ The device tree's PHY addresses need to be fixed up if we're using the
+ SGMII Riser Card.
+
+ The 8572, 8536, and 8544 DS boards were modified to call this function.
+
+ Code idea taken from Liu Yu <yu.liu@freescale.com>
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 5dc0cf68f8f101042997d75188081d8526d705ea
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Feb 11 15:10:31 2009 -0600
+
+ Make some minor whitespace changes to eliminate line-wrapping
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 9e56986a2b74d197f51eca70fad7b836b1900c4d
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Feb 11 15:07:24 2009 -0600
+
+ Add eth_get_dev_by_index
+
+ This allows code to iterate through the ethernet devices
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit b67305120aaf268a6140125346678166d14f1f47
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Feb 9 22:03:04 2009 -0600
+
+ 85xx: Fix bug in device tree setup in 36-bit physical confg
+
+ In the 36-bit physical config for MPC8572DS when need the start address
+ of memory and it size to be kept in phys_*_t instead of a ulong since
+ we support >4G of memory in the config and ulong cant represent that.
+ Otherwise we end up seeing the memory node in the device tree reporting
+ back we have memory starting @ 0 and of size 0.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ad97dce18445ff05bf326094e691a01aa95aa8dc
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Feb 9 22:03:05 2009 -0600
+
+ 85xx: Fix address map for 36-bit config of MPC8572DS
+
+ When we introduced the 36-bit config of the MPC8572DS board we had the
+ wrong PCI MEM bus address map. Additionally, the change to the address
+ map exposes a small issue in our dummy read on the ULI bus. We need
+ to use the new mapping functions to handle that read properly in the
+ 36-bit config.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f8523cb0815b2d3d2d780b7d49ca614105555f58
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Feb 6 09:56:35 2009 -0600
+
+ 85xx: Fix how we map DDR memory
+
+ Previously we only allowed power-of-two memory sizes and didnt
+ handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
+ and should properly handle any size that we can make in the TLBs
+ we have available to us
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Feb 6 09:56:34 2009 -0600
+
+ fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller
+
+ If we only have one controller we can completely ignore how
+ memctl_intlv_ctl is set. Otherwise other levels of code get confused
+ and think we have twice as much memory.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b29dee3c906e9daaf6baf7772d2e15e26b8636b8
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Feb 4 09:35:57 2009 -0600
+
+ 85xx: Format cpu freq printing to handle 8 cores
+
+ Only print 4 cpu freq per line. This way when we have 8 cores its a
+ bit more readable.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9704f9caf53f5cae547d8c5e1ae94aa4e57b160f
+Author: Abraham, Thomas <t-abraham@ti.com>
+Date: Tue Oct 28 16:51:31 2008 +0530
+
+ USB: Remove LUN number from CDB
+
+ The LUN number is not part of the Command Descriptor Block (CDB) for scsi inquiry, request sense, test unit ready, read capacity and read10 commands. This patch removes the LUN number information from the CDB.
+
+ Signed-off-by: Thomas Abraham <t-abraham@ti.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit f3c0de636252f3a18654c8f9c6370a9574a7e755
+Author: Atin Malaviya <atin.malaviya@gmail.com>
+Date: Tue Feb 3 15:17:10 2009 -0500
+
+ Added usbtty_configured() check. Fixed attribute(packed) warnings.
+
+ V3: Fixed line-wrap problem due to user error in mail!
+
+ Added usb_configured() checks in usbtty_puts() and usbtty_putc() to get around a hang
+ when usb is not connected and the user has set up multi-io (setenv stdout serial,usbtty etc).
+ Got rid of redundant __attribute__((packed)) directives that were causing warnings from gcc.
+
+ Signed-off-by: Atin Malaviya <atin.malaviya@gmail.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit e7de18afe8ecf96a51ef981d06066eeb6b1254e7
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Fri Feb 13 09:23:36 2009 +0100
+
+ i.MX31: Start the I2C clock on driver initialisation
+
+ i.MX31 powers on with most clocks running, so, after a power on this explicit
+ clock start up is not required. However, as Linux boots it disables most clocks
+ to save power. This includes the I2C clock. If we then soft reboot from Linux
+ the I2C clock stays off. This breaks the phycore, which has its environment in
+ I2C EEPROM. Fix the problem by explicitly starting the clock in I2C driver
+ initialisation routine.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+ Ack-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 15208ac9eae1c340c4bc11f70cbf5c9da78a57ba
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Feb 11 20:36:14 2009 -0500
+
+ i2c.h: drop i2c_reg_{read, write} hack for Blackfin parts
+
+ The Blackfin i2c driver has been rewritten thus the special ifdefs in the
+ common code are no longer needed.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c2d9befa0b4695b89476fb5d259742c09afe243f
+Author: Heiko Schocher <hs@denx.de>
+Date: Thu Feb 12 08:08:54 2009 +0100
+
+ 82xx, mgcoge: fix compile error
+
+ With actual u-boot compiling the mgcoge port fails, because
+ since commit ba705b5b1a97b47388ed48858bef6bf7b6bfcd56 it is
+ necessary to define CONFIG_NET_MULTI.
+
+ Seems to me the mgcoge port is the only actual existing 8260
+ port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed
+ to be fixed.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 9cacf4fc4035eabe9d9ae2a9a188c51a8027c91e
+Author: Dirk Eibach <eibach@gdsys.de>
+Date: Mon Feb 9 08:18:34 2009 +0100
+
+ ppc4xx: Add README entry for CONFIG_PCI_DISABLE_PCIE
+
+ Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7369f0e384e2a831be13a7773a58242c9173fa9c
+Author: Carolyn Smith <carolyn.smith@tektronix.com>
+Date: Thu Feb 12 06:13:44 2009 +0100
+
+ ppc4xx: Fix initialization of the SDRAM_CODT register
+
+ This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
+ initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
+ and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.
+
+ Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cef0efaf2fa55d1f25066cfb02bd984c27f9ca31
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Feb 11 09:29:33 2009 +0100
+
+ ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boards
+
+ Some AMCC eval boards do have a board_eth_init() function calling
+ pci_eth_init(). These boards need to call cpu_eth_init() explicitly now
+ with the new eth_init rework.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c645012aefebb301e6907d148c6c8efacac049d4
+Author: Adam Graham <agraham@amcc.com>
+Date: Mon Feb 9 13:18:12 2009 -0800
+
+ ppc4xx: Autocalibration can set RDCC to over aggressive value.
+
+ The criteria of the AMCC SDRAM Controller DDR autocalibration
+ U-Boot code is to pick the largest passing write/read/compare
+ window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
+ Cycle Select value.
+
+ On some Kilauea boards the DDR autocalibration algorithm can
+ find a large passing write/read/compare window with a small
+ SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
+ value "T1 Sample".
+
+ This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
+ "T1 Sample" proves to be to aggressive when later on U-Boot
+ relocates into DDR memory and executes.
+
+ The memory traces on the Kilauea board are short so on some
+ Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
+ value of "T1 Sample" shows up as a potentially valid value for
+ the DDR autocalibratiion algorithm.
+
+ The fix is to define a weak default function which provides
+ the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
+ to accept for DDR autocalibration. The default will be the
+ "T2 Sample" value. A board developer who has a well defined
+ board and chooses to be more aggressive can always provide
+ their own board specific string function with the more
+ aggressive "T1 Sample" value or stick with the default
+ minimum SDRAM_RDCC.[RDSS] value of "T2".
+
+ Also put in a autocalibration loop fix for case where current
+ write/read/compare passing window size is the same as a prior
+ window size, then in this case choose the write/read/compare
+ result that has the associated smallest RDCC T-Sample value.
+
+ Signed-off-by: Adam Graham <agraham@amcc.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2ede879fcb67470524847bb4fc8972651bb46184
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Feb 11 09:37:12 2009 +0100
+
+ ppc4xx: Fix problem with CONFIG_MAX_MEM_MAPPED in include/asm-ppc/config.h
+
+ CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is
+ included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB.
+
+ It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx
+ boards right now.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f15c6515fc23f83c51f3de272ca23d86b80e81b1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Feb 12 00:08:39 2009 +0100
+
+ Coding style cleanup; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5fc56b907d993260b9ebdb137af66fe69635ae9e
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Fri Jan 30 16:36:40 2009 -0600
+
+ Add feature-removal-schedule.txt
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 255d28e1642e8fc32a6753226be1a96b481ce111
+Author: Heiko Schocher <hs@denx.de>
+Date: Tue Feb 10 09:32:38 2009 +0100
+
+ 8xx serial, smc: Coding-Style cleanup serial SMC driver
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 2b3f12c214346508cae3f1245808c1ca54c81fdd
+Author: Heiko Schocher <hs@denx.de>
+Date: Tue Feb 10 09:31:47 2009 +0100
+
+ 8xx serial, smc: add configurable SMC Rx buffer len
+
+ This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
+ With this option it is possible to allow the receive
+ buffer for the SMC on 8xx to be greater then 1. In case
+ CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
+ old version.
+
+ When defining CONFIG_SYS_SMC_RXBUFLEN also
+ CONFIG_SYS_MAXIDLE must be defined to setup the maximum
+ idle timeout for the SMC.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit e915f8bb73d74178bc21d3a457959883b1afd1c0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Feb 5 21:04:36 2009 -0500
+
+ common/{hush, kgdb, serial}.c: build by COBJS-$(...) in Makefile
+
+ Move global '#ifdef CONFIG_xxx .... #endif' out of the .c files and into
+ the COBJS-$(CONFIG_xxx) in the Makefile. Also delete unused var in kgdb
+ code in the process.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ab76e9848a1f4db64d14233741d739a3b3360c93
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Feb 5 21:04:50 2009 -0500
+
+ bzip2: move ifdef handling to Makefile COBJS-$(...)
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ae0b05df04e1cc65c5ad19ccd362f4be82df7316
+Author: Jerry Van Baren <gvb.uboot@gmail.com>
+Date: Thu Feb 5 22:18:02 2009 -0500
+
+ Fix whitespace damage: double space changed to a tab
+
+ At some point an intentional double space at the end of the sentence
+ got changed into a tab in the GPL header line:
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+
+ This patch fixes the damage.
+
+ Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 4f975678de995b55749d5e84590c268972a7c835
+Author: Heiko Schocher <hs@denx.de>
+Date: Tue Feb 10 09:53:29 2009 +0100
+
+ cfi: make flash_get_info() non static
+
+ If on your board is more than one flash, you must know
+ the size of every single flash, for example, for updating
+ the DTS before booting Linux. So make this function
+ flash_get_info() extern, and you can have all info
+ about your flashes.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 86321fc1128c93a10ac4afb9d317b0df8ece0f9e
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Thu Feb 5 23:58:25 2009 -0800
+
+ net: removed board-specific CONFIGs from MPC5xxx FEC driver
+
+ Added new CONFIG options for the three type of MAC-PHY interconnect and
+ applied them all relevant board config files
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 638ed3e296e70fab286d157b7adedaaa4a09a474
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Feb 5 21:04:47 2009 -0500
+
+ net/sntp.c: move ifdef into Makefile COBJS-$(...)
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 9e5be8214ba751436e57c3be044bf6dccb9a6687
+Author: Andy Fleming <afleming@freescale.com>
+Date: Tue Feb 3 18:26:41 2009 -0600
+
+ tsec: Fix a bug in soft-resetting
+
+ SOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30
+ clock cycles, so it's been mostly working. But we had no guarantee, and at
+ slower bitrates, it's just over a microsecond (over 1000 clock cycles). This
+ enforces a 2 microsecond gap between assertion and deassertion.
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 09fcc8b5d86903b76e7e4d1d879d6f4bca25c27b
+Author: Simon Munton <simon@nidoran.m5data.com>
+Date: Mon Feb 2 09:44:08 2009 +0000
+
+ Fix 100Mbs ethernet operation on sh7763 based boards
+
+ 100Mbs ethernet does not work on sh7763 chips due to the wrong value being
+ used in the GECMR register. Following diff fixes the problem
+
+ Signed-off-by: Simon Munton <simon@nidoran.m5data.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 2bc2a8f6dc9fdda465317da59474e65c24a398a2
+Author: ksi@koi8.net <ksi@koi8.net>
+Date: Fri Feb 6 16:27:55 2009 -0800
+
+ Fix MPC8260 with ethernet on SCC
+
+ This fixes MPC8260 compilation with ethernet on SCC. Probably was a
+ typo or something...
+
+ Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit ae5d8f613cec1a6af7bf1fc9c42a3b856f021023
+Author: Heiko Schocher <hs@denx.de>
+Date: Fri Jan 30 12:56:15 2009 +0100
+
+ 82xx serial, smc: Coding-Style cleanup serial SMC driver
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit c92fac91a06c60f874c605e3ca80dd407c1caaa7
+Author: Heiko Schocher <hs@denx.de>
+Date: Fri Jan 30 12:55:38 2009 +0100
+
+ 82xx serial, smc: add configurable SMC Rx buffer len
+
+ This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
+ With this option it is possible to allow the receive
+ buffer for the SMC on 82xx to be greater then 1. In case
+ CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
+ old version.
+
+ When defining CONFIG_SYS_SMC_RXBUFLEN also
+ CONFIG_SYS_MAXIDLE must be defined to setup the maximum
+ idle timeout for the SMC.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit bced7ccefa08512c54a6d146658ff7dbc33d5dfe
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Feb 6 08:08:06 2009 -0600
+
+ ppc: Fix roll over bug in flush_cache()
+
+ If we call flush_cache(0xfffff000, 0x1000) it would never
+ terminate the loop since end = 0xffffffff and we'd roll over
+ our counter from 0xfffffe0 to 0 (assuming a 32-byte cache line)
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 87c9063963561d3d01064be34d0c30855a56587b
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Feb 5 20:40:58 2009 -0600
+
+ ppc: Move CONFIG_MAX_MEM_MAPPED to common config.h
+
+ Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent
+ between the two current users (lib_ppc/board.c, 44x SPD DDR2).
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Stefan Roese <sr@denx.de>
+
+commit 47d41cc3a11a03c6d56146d056145df73f47eb50
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Feb 5 20:40:57 2009 -0600
+
+ Add an architecture specific config.h for common defines
+
+ We have common defines that we duplicate in various ways. Having an
+ arch specific config.h gives us a common location for those defines.
+
+ Eventually we should be able to replace this when we have proper
+ Kconfig support.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 4c78d4a6c01621721b732418e1c6da684a56bbb1
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:56 2009 -0600
+
+ mpc8641hpcn: Change PCI MEM pci bus address
+
+ Now that the rest of u-boot can support it, change the PCI bus
+ address of the PCI MEM regions from 0x80000000 to 0xc0000000,
+ and use the same bus address for both PCI1 and PCI2. This will
+ maximize the amount of PCI address space left over to map RAM
+ on systems with large amounts of memory.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 1785dbeed43599eed1d8875673c96912cd770141
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:55 2009 -0600
+
+ drivers/block/ahci: Fix pci mapping bug
+
+ The code assumes that the pci bus address and the virtual
+ address used to access a region are the same, but they might
+ not be. Fix this assumption.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit d591a80e74091e7a0658d165721e6c7de2ef0bcd
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:54 2009 -0600
+
+ MPC8641HPCN: Enable CONFIG_ADDR_MAP
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 49f46f3bf08aaf7b1db131a1082f1e603bb7a94b
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:53 2009 -0600
+
+ mpc8641hpcn: Clean up PCI mapping concepts
+
+ Clean up PCI mapping concepts in the 8641 config - rename _BASE
+ to _BUS, as it's actually a PCI bus address, separate virtual
+ and physical addresses into _VIRT and _PHYS, and use each
+ appopriately.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit c9315e6b4f244981de0b2eaaa29a7838a165b494
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:52 2009 -0600
+
+ mpc86xx: Add support to populate addr map based on BATs
+
+ If CONFIG_ADDR_MAP is enabled, update the address map
+ whenever we write a bat.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit d35ae5a938679bd7e18167faf79d0fb3c6639b51
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:51 2009 -0600
+
+ powerpc: Move duplicated BAT defines to mmu.h
+
+ The BAT fields are architected; there's no need for these to be in
+ cpu-specific files. Drop the duplication and move these to
+ include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only
+ used by the alaska board, and switch to using the BATU_BL_xxx defines
+ used by all the other boards. The BL_ defines previously in use
+ had to be shifted into the proper position for use, which was inefficient.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 6e61fae4d360a1380b63e7d007b31477e366bcce
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:50 2009 -0600
+
+ drivers/pci: Create pci_map_bar function
+
+ It is no longer always true that the pci bus address can be
+ used as the virtual address for pci accesses. pci_map_bar()
+ is created to return the virtual address for a pci region.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 2ecca3401775b125c3b9ff65766befb23989414b
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Tue Feb 3 18:10:49 2009 -0600
+
+ mpc8641hpcn: Set up outbound pci windows before inbound
+
+ Because the inbound pci windows are mapped generously, set up
+ the more specific outbound windows first. This way, when we
+ search the pci regions for something, we will hit on the more
+ specific region. This can actually be a problem on systems
+ with large amounts of RAM.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit b81b773ead0687114dc8a800f99ea6e504447739
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Mon Feb 2 16:34:52 2009 -0600
+
+ mpc8641hpcn: Use physical address in flash banks defintion
+
+ If the VA and PA of the flash aren't the same, the banks list
+ should be initialized to hold the physical address. Correct this.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 2d43e873a29ca4959ba6a30fc7fb396d3fd0dccf
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Feb 6 09:49:32 2009 -0600
+
+ pci: give preference to non-PCI_REGION_SYS_MEMORY regions when matching
+
+ When we search for an address match in pci_hose_{phys_to_bus,bus_to_phys}
+ we should give preference to memory regions that aren't system memory.
+
+ Its possible that we have over mapped system memory in the regions and
+ we want to avoid depending on the order of the regions.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ff4e66e93c1ad47644be3b4ffd6a46e1ce9b6612
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Feb 6 09:49:31 2009 -0600
+
+ pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity
+
+ The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
+ can be confusing when reading the code.
+
+ Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
+ for system memory mapping purposes.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 8da601280a8acbc3385784780ed35130e53812f1
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Feb 4 13:47:22 2009 -0600
+
+ NAND: Add timeout for reset command
+
+ Without the timeout present an infinite loop can occur if the
+ NAND device is broken or not present.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 10dc6a9bef73d7d4cb25b3fde27ee91f8484b126
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Feb 4 13:39:40 2009 -0600
+
+ NAND: Silence warning when CONFIG_SYS_NAND_QUIET_TEST
+
+ Commit cfa460adfdefcc30d104e1a9ee44994ee349bb7b removed support
+ for disabling the "No NAND device found!!!" warning when
+ CONFIG_SYS_NAND_QUIET_TEST was defined. This re-adds support
+ for silencing the warning.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit ad09ab2e3ac28f304372eceb4a5cb4d24e102a13
+Author: Valeriy Glushkov <gvv@lstec.com>
+Date: Mon Jan 19 16:32:59 2009 +0200
+
+ NAND: Fixed invalid pointers to static relocated chip names
+
+ Dear Wolfgang,
+
+ You are right, the patch was ugly.
+ The new one seems to be better.
+
+ Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 5a9427dc9b8438759db3f67a1e547062f76eb18d
+Author: derek@siconix.com <derek@siconix.com>
+Date: Mon Jan 26 14:08:17 2009 -0700
+
+ env_nand: fix env memory release
+
+ This fixes a bug that tmp environment memory not being released.
+
+ Signed-off-by: Derek Ou <dou@siconix.com>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 6989e4f546d960a407dd5425f800dff9751c8132
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Thu Feb 5 09:33:50 2009 -0500
+
+ Coldfire: M527x: Add missing GPIO register address defines
+
+ Add missing GPIO registers address definition for Coldfire M5271.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit c4ff77f5e6c3a01610ce97434c0d59acb1476f95
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Fri Jan 23 14:42:58 2009 -0500
+
+ Coldfire: mcfmii: Allow non-autonegotiating PHYs to use mii command
+
+ Modified mii_init to support boards with PHYs that are not set to
+ autonegotiate, but still want to use u-boot's mii commands to probe
+ the smi bus. Such PHYs will not set the Autonegotiate-done bit.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit 92d3e6e0ffcbb7224c83104f8d87b5b4bf39a38f
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Fri Jan 23 11:44:30 2009 -0500
+
+ Coldfire: Applied baudrate formula of serial_init to serial_setbrg
+
+ Applied the patch for baudrate divider value truncation for
+ serial_init to serial_setbrg as well.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit 8706ef378f2db1ef65b9c2f909561f23e3dc2148
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Fri Jan 23 14:07:05 2009 -0500
+
+ Coldfire: M5271EVB: Board header update (dependencies)
+
+ Cleanup for M5271EVB:
+ Added clarification on the use of CONFIG_SYS_CLOCK.
+ Modified to use u-boot's HUSH parser.
+ Cleanup on environment settings.
+ Removed compiler warning by defining CONFIG_SYS_CS0_*
+
+ Dependencies:
+ Added the use of CONFIG_SYS_MCF_SYNCR for clock multiplier.
+ This depends on a patch to include/asm-m68k/m5271.h
+ that defines the multiplier and divider ratios.
+
+ Removed the definition of CONFIG_SYS_FECI2C.
+ This depends on a patch that removes the use of it in
+ cpu/mcf52x2/cpu_init.c
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit e0db344fabfeb4f9649846f94838f51172f6a1f6
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Thu Jan 29 14:36:06 2009 -0500
+
+ Coldfire: M5271: Allow board header file to specify clock multiplier
+
+ M5271 dynamic clock multiplier. It is currently fixed at 100MHz.
+
+ Allow the board header file to set their own multiplier and divider.
+ Added the #define for the multiplier and divider to the cpu header file.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit d1ef25dd81c79dcfad5c2ff0162b1bea21d04bc3
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Fri Jan 23 10:47:13 2009 -0500
+
+ Coldfire: M5271EVB: Remove usage of CONFIG_SYS_FECI2C
+
+ Discontinue the use of CONFIG_SYS_FECI2C (only used by M5271EVB).
+ Use read-modify-write to activate the FEC pins without disabling I2C.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit ee73cc59ab904976af3c33b454fc84f78618b2d1
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Fri Jan 23 09:45:34 2009 -0500
+
+ Coldfire: cmd_bdinfo cleanup
+
+ CONFIG_M68K bdinfo cleanup:
+
+ Fixed compiler warning about baudrate printing.
+ format '%d' expects type 'int', but argument 2 has type 'long unsigned int'.
+
+ Added printing of "cpufreq"
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit 4ffc39050aa46ed8a3d29732293dff769e54fffa
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date: Fri Jan 23 09:27:00 2009 -0500
+
+ Coldfire: Fix half-baud UART by adding M5271 to Coldfire v2 core list
+
+ Added the CONFIG_M5271 to the list of Coldfire V2 processor. This
+ was causing the bus clock (not CPU clock) to be declared twice as
+ fast as it actually is. This causes UARTS to operate at half the
+ specified baudrate.
+
+ Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit 59d1bda7f92c8a28c3aba94e48063749d425949f
+Author: Dirk Eibach <eibach@gdsys.de>
+Date: Tue Feb 3 15:15:21 2009 +0100
+
+ ppc4xx: Make PCIE support selectable
+
+ On some platforms PCIE support is not required, but would be included
+ because the cpu supports it. To reduce fooprint it is now configurable
+ via CONFIG_PCI_DISABLE_PCIE.
+
+ Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b129eff5ede394cc1faeb6dbf6a987e91abce552
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Tue Feb 3 22:13:16 2009 +0100
+
+ ppc4xx: Only fixup opb attached UARTs
+
+ This patch updates the fdt UART clock fixup code to
+ only touch CPU internal UARTs on 4xx systems.
+ Only these UARTs are definitely clocked by gd->uart_clk.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4b7e3d045cc82f7f7b6f3a19b54a814da36ac52c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Jan 13 11:00:29 2009 -0500
+
+ Blackfin: move default boot SPI CS to common code
+
+ Move the default SPI CS that we boot from into common code so that it can
+ be used in other SPI drivers and environment settings.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit f790ef6ff12381cb0e43de54fb2b0f1204ad8ed6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Dec 10 12:33:54 2008 -0500
+
+ Blackfin: dynamically update UART speed when initializing
+
+ Previously, booting over the UART required the baud rate to be known ahead
+ of time. Using a bit of tricky simple math, we can calculate the new board
+ rate based on the old divisors.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
+
+commit 97f265f14f23050f3cb997f617f3a6917b843ea2
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Dec 9 17:21:08 2008 -0500
+
+ Blackfin: add support for fast SPI reads with Boot ROM
+
+ Newer Blackfin boot roms support using the fast SPI read command rather than
+ just the slow one. If the functionality is available, then use it.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 67619982bfc5cd62710a48e3cbffc304cb78c341
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:46:52 2008 -0400
+
+ Blackfin: check for reserved settings in DDR MMRs
+
+ Some bits of the DDR MMRs should not be set. If they do, bad things may
+ happen (like random failures or hardware destruction).
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 622a8dc0958dd599743348ea94eb10b9d0be8ae6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:54:00 2008 -0400
+
+ Blackfin: set default voltage levels for BF538/BF539 parts
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 09dc6b0bbd1d5e39cdddeebc059f9a75630e4f6f
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 1 01:29:57 2008 -0400
+
+ Blackfin: use on-chip syscontrol() rom function when available
+
+ Newer Blackfin's have an on-chip rom with a syscontrol() function that needs
+ to be used to properly program the memory and voltage settings as it will
+ include (possibly critical) factory tested bias values.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e1fb6d0d52fbe3fbc1a4c651dacf11e9c1417f63
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Feb 5 11:44:52 2009 +0100
+
+ cfi_flash: Fix typo in cfi_flash.c
+
+ Patch "flash/cfi_flash: Use virtual sector start address, not phys"
+ introduced a small typo and compilation warning for systems with CFI
+ legacy support (e.g. hcu4). This patch fixes it.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 28745db969b72693754991c838f68a7fb4a8b1ab
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jan 29 11:21:38 2009 +0100
+
+ jedec_flash: Only use manufacturer defines from common flash.h
+
+ This patch removes the double defined manufacturer defines from
+ jedec_flash.c. Since the common defines in flash.h are 32bit
+ we now need the (16) cast. This patch also removes the compilation
+ warning (e.g. seen on hcu5):
+
+ ./MAKEALL hcu5
+ Configuring for hcu5 board...
+ jedec_flash.c:219: warning: large integer implicitly truncated to unsigned type
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ec21d5cfcb6b4e7fcdd5c6e926e1a824900706f2
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Feb 5 11:25:57 2009 +0100
+
+ cfi_flash: Silence compilation warning
+
+ Patch "flash/cfi_flash: Use virtual sector start address, not phys"
+ introduced a small compilation warning. This patch fixes it.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 09ce9921a7d8b1ce764656b14b42217bbf4faa38
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Mon Feb 2 16:34:51 2009 -0600
+
+ flash/cfi_flash: Use virtual sector start address, not phys
+
+ include/flash.h was commented to say that the address in
+ flash_info->start was a physical address. However, from u-boot's
+ point of view, and looking at most flash code, it makes more
+ sense for this to be a virtual address. So I corrected the
+ comment to indicate that this was a virtual address.
+
+ The only flash driver that was actually treating the address
+ as physical was the mtd/cfi_flash driver. However, this code
+ was using it inconsistently as it actually directly dereferenced
+ the "start" element, while it used map_physmem to get a
+ virtual address in other places. I changed this driver so
+ that the code which initializes the info->start field calls
+ map_physmem to get a virtual address, eliminating the need for
+ further map_physmem calls. The code is now consistent.
+
+ The *only* place a physical address should be used is when defining the
+ flash banks list that is used to initialize the flash_info struct,
+ usually found in the board config file.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 657f2062d8e17ebf4a55f52c9e71c07c0c94c779
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Feb 4 09:42:20 2009 +0100
+
+ Fix compiler warning
+
+ (shows up only when DEBUG is enabled)
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 47832cd15ae02fb6fde8ebed5b272f85775f2ceb
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 03:45:55 2008 -0400
+
+ Blackfin: update anomaly lists
+
+ Update the anomaly lists to match latest anomaly sheets.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 70a4da45e16b72e8e5b0baaecdaee9be8619647d
+Author: Ralph Kondziella <rk@argos-messtechnik.de>
+Date: Mon Jan 26 12:34:36 2009 -0700
+
+ ADS5121 Add PATA support
+
+ Original patch from Ralph Kondziella
+ plus clean up by Wolfgang Denk
+ plus changes by John Rigby
+ use ips clock not lpc
+ port forward to current u-boot release
+
+ Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit abfbd0ae4967df18102345db4f4b529a13da107b
+Author: Martha Marx <mmarx@silicontkx.com>
+Date: Mon Jan 26 10:45:07 2009 -0700
+
+ ADS5121 Add IC Ident Module (IIM) support
+
+ IIM (IC Identification Module) is the fusebox for the mpc5121.
+ Use #define CONFIG_IIM to turn on the clock for this module
+ use #define CONFIG_CMD_FUSE to add fusebox commands.
+ Fusebox commands include the ability to read
+ the status, read the register cache, override the register cache,
+ program the fuses and sense them.
+
+ Signed-off-by: Martha Marx <mmarx@silicontkx.com>
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit 14d19cd1bce9a24b1335598f1568140f4950e4d9
+Author: John Rigby <jrigby@freescale.com>
+Date: Fri Jan 23 10:33:15 2009 -0700
+
+ ADS5121 Fix rev2 silicon pci iopad config
+
+ Reset config is not correct
+
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit 4c154252c480b13f69ce1b71a9530b0515da76a6
+Author: John Rigby <jrigby@freescale.com>
+Date: Wed Nov 19 13:57:34 2008 -0700
+
+ ADS5121 DIU Add diu_bmp_addr env
+
+ Add support for using a bmp other than
+ FSL_Logo_BMP for the DIU splash screen.
+
+ Can now set the env var "diu_bmp_addr" to
+ the address of a BMP in flash to use instead
+ of the default FSL_Logo_BMP.
+
+ Signed-off-by: Martha Marx <mmarx@silicontkx.com>
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit 92c20fbd3a7788c1a154f50a3f44f28a7763f99a
+Author: John Rigby <jrigby@freescale.com>
+Date: Thu Oct 30 16:39:35 2008 -0600
+
+ ADS5121 DIU Make inclusion of FSL logo optional
+
+ Make inclusion of FSL logo optional and
+ turn it off by default.
+
+ Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit bd99ec149abe94e7f6b2bda4766d701b4005053f
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Sun Feb 1 12:27:53 2009 +0100
+
+ Compile warning fix in onenand_uboot.h
+
+ Regression since merge window after 2009.01
+
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit a270d1e7295c3d829f42c0480117941dfc1c6477
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jan 29 06:33:55 2009 +0100
+
+ USB: Add EHCI support for VCT EHCI controller (really with driver now)
+
+ Somehow I missed the real driver part in my last patch version. This patch
+ now adds the driver.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 716ebf436c9e43df6740e0172f6b2a81ddbf1b8e
+Author: Cliff Cai <cliff.cai@analog.com>
+Date: Sat Nov 29 18:22:38 2008 -0500
+
+ Blackfin: add driver for on-chip MMC/SD controller
+
+ This is a port of the Linux Blackfin on-chip SDH driver to U-Boot.
+
+ Signed-off-by: Cliff Cai <cliff.cai@analog.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 6e87ea0ca951465eba144ab2e6dba6fb507737a2
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 22:47:34 2008 -0400
+
+ Blackfin: add port muxing for BF51x SPI
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit fc68f9f85959664d528daea2aef5ef54974331ce
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Jan 6 06:16:19 2009 -0500
+
+ Blackfin: output booting source when booting
+
+ Knowing the booting source of the part is useful, especially when the part
+ can switch dynamically between sources.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8df3ce0f49c37947800ac7c84e751499882619fc
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Dec 11 06:30:46 2008 -0500
+
+ Blackfin: set default CONFIG_ENV_SPI_CS based on bootrom
+
+ Set the default CONFIG_ENV_SPI_CS value to match the SPI CS that is used by
+ the Blackfin on-chip bootrom to boot out of SPI flash.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2b4a486e6fac502d8b883e344cc4012283945b3d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Dec 11 04:06:26 2008 -0500
+
+ Blackfin: update asm-blackfin/posix_types.h to latest Linux version
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e5eb93e77391bcc308697116c544ea1340aaae8a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Dec 6 02:54:52 2008 -0500
+
+ Blackfin: add port I bits
+
+ Some people need to access port I, so make sure the pins are defined.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8a6b272596d43de0db4943eac7af58c3534c4026
+Author: Sonic Zhang <Sonic.Zhang@analog.com>
+Date: Wed Nov 26 22:16:45 2008 -0500
+
+ Blackfin: add driver for on-chip ATAPI controller
+
+ This is a port of the Linux Blackfin on-chip ATAPI driver to U-Boot.
+
+ Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit be9d8c780e6831cb84b7d4590ceae03dca8fc10b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 26 21:43:06 2008 -0500
+
+ Blackfin: add driver for on-chip NAND controller
+
+ This is a port of the Linux Blackfin on-chip NFC driver to U-Boot.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 4148e02abae9a099f4444b5e168ebc2b911d2295
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 12 07:18:15 2008 -0500
+
+ Blackfin: build with -mno-fdpic
+
+ Use the -mno-fdpic flag so that any Blackfin toolchain can be used to build
+ up u-boot, including ones that output FDPIC ELF by default.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 70e95589a24a2d83ad00317e4a9611d0211ecb58
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Nov 11 05:43:57 2008 -0500
+
+ Blackfin: fix up EBIU defines
+
+ The EBIU defines for EBSZ 256/512 were incorrect.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 961954ea0ec8dc4341034c1a1ff3107ec0527809
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 5 12:45:24 2008 -0500
+
+ Blackfin: use 8/16/32 bit transfer widths in dma_memcpy()
+
+ Rather than using 8bit transfers for everything, use 8/16/32 bit transfers
+ as usable with the source/destination addresses and the count size.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b93c68648426f906d63b98117496b6415f505f39
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 5 08:50:23 2008 -0500
+
+ Blackfin: only flag L1 instruction for DMA memcpy
+
+ The performance difference from doing an 8 bit DMA memcpy vs an optimized
+ core memcpy can be pretty big when you add in the overhead of setting up the
+ MDMA registers, cache flushes, etc... So only use dma_memcpy() when we
+ actually require it.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e347c092a3b3a2ce1e72f25f4829163634d09fbe
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 5 07:20:37 2008 -0500
+
+ Blackfin: dma_memcpy(): fix random failures
+
+ We have to make sure the DMA channel is actually disabled in hardware before
+ attempting to reprogram it. Otherwise the new settings are ignored and we
+ end up with random hangs/failures.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit fdce83c108846d6f0d5b1774e1cc29f2573a6ad3
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Nov 4 00:04:03 2008 -0500
+
+ Blackfin: rewrite cache handling functions
+
+ Take the cache flush functions from the kernel as they use hardware loops in
+ order to get optimal performance.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 84c5f0dc47d17593fd81206614891bdc94f6d51c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Nov 3 22:30:05 2008 -0500
+
+ Blackfin: setup bi_enetaddr for single nets
+
+ For systems with CONFIG_NET_MULTI disabled, bi_enetaddr does not get setup
+ based on $ethaddr, so set it up.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 40599239e7875b39e2a5c12e6545992041c72c52
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Oct 24 22:48:47 2008 -0400
+
+ Blackfin: cache core/system clock values
+
+ Calculating the clocks requires a bit of calls to gcc math functions, so
+ cache the values after the first run since they'll most likely never
+ change once U-Boot is up and running.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 6957a6209b02f6b69607fc47425f13731cc477f1
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Oct 24 18:18:16 2008 -0400
+
+ Blackfin: enable --gc-sections
+
+ Start building all Blackfin boards with -ffunction-sections/-fdata-sections
+ and linking with --gc-sections.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ee1d2001ea7fbabb2b9256026dc5468f057337f8
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 20 21:08:54 2008 -0400
+
+ Blackfin: dont check baud if it wont actually get used
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 400f5778f375bc99c73c8488c555def261ccfab7
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Oct 14 07:54:09 2008 -0400
+
+ Blackfin: add driver for on-chip SPI controller
+
+ This fills out the SPI backend for the Blackfin on-chip SPI peripheral.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 7a1e87b1062e6eac0704c6fc2f7c661caf8814cd
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 18 05:33:51 2008 -0400
+
+ Blackfin: only build post code when CONFIG_POST
+
+ Save some time by using CONFIG_POST in the Makefile rather than C files.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 6d7d4803c74bb86e1b401b1199e63381a62b9382
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jan 8 11:57:57 2009 -0500
+
+ Blackfin: bfin_mac: cleanup pointer/casts for aliasing issues
+
+ Redo how pointers are managed to get rid of ugly casts and strict pointer
+ aliasing issues that are highlighted by gcc 4.3.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 092d2487baf7c29343c165e3ae82ea8a7f9e679b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Dec 9 17:46:21 2008 -0500
+
+ Blackfin: bfin_mac: convert CONFIG_BFIN_MAC_RMII to CONFIG_RMII
+
+ No point in having a Blackfin-specific define "CONFIG_BFIN_MAC_RMII" that
+ does exactly the same thing as common "CONFIG_RMII".
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8eed6ca51e50fade6887e8bdb1ff6a44116b42b5
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 5 06:36:15 2008 -0500
+
+ Blackfin: bfin_mac: use common debug()
+
+ Rather then defining our own DEBUGF(), just use the common debug().
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit a7ec6ac8b2c6dce6fc670a2a855deb6eee340e04
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 20 13:59:51 2008 -0400
+
+ Blackfin: bfin_mac: respect CONFIG_PHY_{ADDR,CLOCK_FREQ}
+
+ Rather than having the on-chip MAC hardcoded to phy address 1 and a speed
+ of 2.5mhz, use these as defaults if the board doesn't specify otherwise.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit ac45af4e63ea925f4accc98453aab1a1166c196d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Oct 14 04:52:00 2008 -0400
+
+ Blackfin: bfin_mac: cleanup MII/PHY functions
+
+ Cleanup and rewrite the MII/PHY related functions so that we can reuse the
+ existing common linux/miiphy.h code and hook into the `mii` command.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 6b310a05f0d10c751f22468040932139f71c71d3
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Oct 14 00:31:30 2008 -0400
+
+ Blackfin: bfin_mac: set MDCDIV based on SCLK
+
+ Rather than hardcoding MDCDIV to 24 (which is correct for ~125mhz SCLK),
+ use the real algorithm so it gets set correctly regardless of SCLK.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 930590f3e49c8f32256edf2e5861e1535a329c6c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 31 09:10:48 2009 +0100
+
+ ixp: move serial to drivers/serial
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f90c8022f448bc5e93090e4b714368e52e912f0f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 31 09:04:58 2009 +0100
+
+ ixp: move pci init in arm/board instead of cpu
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8cb79b5f275f1888ccb278a2d2197140444a84b7
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 31 08:56:49 2009 +0100
+
+ ixp: move pci drivers to drivers/pci
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 012d5bab09a534e4800b02f50cf508e6837202ea
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 31 08:53:44 2009 +0100
+
+ ixp: Move conditional compilation to Makefile
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f693f501d67434df1f815fd1824a71973ae08207
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 31 08:53:44 2009 +0100
+
+ ixp: add missing os define
+
+ need by arm-elf toolchains and no impact on the arm-linux one
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit b4e2f89dfcb206a22d34fa6b34878d85b498b39f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 31 09:53:39 2009 +0100
+
+ ixp: remove the option to include the Microcode
+
+ instead the board will have to load it from flash or ram
+ which will be specified by npe_ucode env var
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1b017baf2071d8daf643bce87250db898c606c66
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Jan 30 09:45:23 2009 +0100
+
+ ixp/npe: Move conditional compilation to Makefile
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 4e69087a1d6ef2eca6f46026cf5e7399b6c9e7c0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Jan 28 21:58:04 2009 +0100
+
+ SX1: add hardware V2 support
+
+ In the V2 the 2 flash has been replace by one 32MB flash
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f877f2233dbcd7417c2f0babe6a849099b167f3c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Jan 28 21:58:03 2009 +0100
+
+ SX1: Fix second flash mapping
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 47fd3bffed6430c91eb2660f859574ed98be5bd8
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Jan 28 21:58:03 2009 +0100
+
+ SX1: add CONFIG_STDOUT_USBTTY to enable preboot stdout redirect to usbtty
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit cfca33837ec83829c6a49c3bcc86c31bc2495ff6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Jan 28 21:57:59 2009 +0100
+
+ move Samsung's board to board/samsung
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e4943ec57466ea5dfa085e7a9e0ec44cb93c4e1e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Jan 29 12:07:21 2009 +0100
+
+ move ARM Ltd. to vendor dir
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit a87fb1b308a2a375cb9ca74ca0dd3e2c5793d3bf
+Author: Larry Johnson <lrj@acm.org>
+Date: Wed Jan 28 15:30:37 2009 -0500
+
+ ppc4xx: Clean up configuration file for Korat board
+
+ This patch updates the default environmental variables for the
+ Korat PPC 440EPx board, and makes additional minor fixes.
+
+ Signed-off-by: Larry Johnson <lrj@acm.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f20405e31680efc36293c59b4963db57c9d93df4
+Author: Larry Johnson <lrj@acm.org>
+Date: Wed Jan 28 15:30:02 2009 -0500
+
+ ppc4xx: Add variable "korat_usbcf" for Korat board
+
+ The new environment variable "korat_usbcf" selects the USB
+ port used by the Korat board's CompactFlash controller.
+
+ Signed-off-by: Larry Johnson <lrj@acm.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fc01ea1e27d5b124f0a1868d0ce569f156d58dfe
+Author: Gunnar Rangoy <gunnar@rangoy.com>
+Date: Fri Jan 23 12:56:31 2009 +0100
+
+ AVR32: macb - Search for PHY id
+
+ This patch adds support for searching through available PHY-addresses in
+ the macb-driver. This is needed for the ATEVK1100 evaluation board,
+ where the PHY-address will be initialized to either 1 or 7.
+
+ This patch adds a config option, CONFIG_MACB_SEARCH_PHY, which when
+ enabled tells the driver to search for the PHY address.
+
+ Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com>
+ Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com>
+ Signed-off-by: Olav Morken <olavmrk@gmail.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit af8626e0c08a780d9ded1d9c4883a89355f60e75
+Author: Olav Morken <olavmrk@gmail.com>
+Date: Fri Jan 23 12:56:26 2009 +0100
+
+ Fix IP alignment problem
+
+ This patch removes volatile from:
+ volatile IP_t *ip = (IP_t *)xip;
+
+ Due to a bug, avr32-gcc will assume that ip is aligned on a word boundary when
+ using volatile, which causes an exception since xip isn't aligned on a word
+ boundary.
+
+ Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com>
+ Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com>
+ Signed-off-by: Olav Morken <olavmrk@gmail.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 12a8b9db12f82a189ff143a58731007f5469da61
+Author: Ron Madrid <ron_madrid@sbcglobal.net>
+Date: Wed Jan 28 16:17:21 2009 -0800
+
+ Marvell 88E1118 interrupt fix
+
+ This patch adjusts the LED control so that interrupt lines are not reading LEDs
+ and effectively causing indefinite interrupts to the controller.
+
+ Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 9a37f2acc31a3296dddd3574ea9eaf7f319807b9
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Jan 21 17:14:26 2009 +0100
+
+ net: smc911x.c: Add LAN9211 to chip_ids[] array
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 75edebe3011c963a7cd84be0f4a987477f2aaf89
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Jan 27 16:53:39 2009 -0500
+
+ Move is_valid_ether_addr() to include/net.h
+
+ Import the is_valid_ether_addr() function from the Linux kernel.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 268859338c0188eab1d0d3b867b7dad3c5cc734a
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Jan 5 12:25:13 2009 +0100
+
+ net: Sort Makefile labels
+
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 1fbcbe9a95f39afb2df6ab8cba25b284b47ebfb2
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jan 28 23:06:42 2009 +0100
+
+ 85xx: Fix compile breakage with sbc8540 and sbc8560
+
+ This fixes an error which raises just a warning:
+ sbc8560.c:250: warning: passing argument 2 of 'strmhz' makes integer from pointer without a cast
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 62625c0b081bd4019cecab14e9fc2e05e48d2a58
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Jan 28 13:48:55 2009 -0500
+
+ SPD823TS: do not define CONFIG_CMD_ENV
+
+ Since the SPD823TS board does not actually have any writable flash to save
+ its environment, undefine CONFIG_CMD_ENV so the "saveenv" command is
+ disabled.
+
+ This fixes the build error:
+ common/libcommon.a(cmd_nvedit.o): In function `do_saveenv':
+ common/cmd_nvedit.c:557: undefined reference to `saveenv'
+ make: *** [u-boot] Error 1
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 7379f45a7bc71941c3920c2f6b3c3faa4d7fd315
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Wed Jan 28 21:40:16 2009 +0100
+
+ OMAP3: Add Zoom1 board support
+
+ Support for Zoom MDK with OMAP3430. Details of Zoom MDK available here:
+ http://www.logicpd.com/products/devkit/ti/zoom_mobile_development_kit
+
+ Signed-off-by: Nishanth Menon <nm@ti.com>
+ Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+
+commit 2be2c6cc674e26237962f5cf4c0d311e139e4241
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Wed Jan 28 21:39:58 2009 +0100
+
+ OMAP3: Add Pandora support
+
+ Add Pandora support.
+
+ Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+ Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+
+commit ad9bc8e52d174d699d1367be0b90089e4fdeb933
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Wed Jan 28 21:39:58 2009 +0100
+
+ OMAP3: Add EVM board
+
+ Add EVM board support.
+
+ Signed-off-by: Manikandan Pillai <mani.pillai@ti.com>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+ Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+
+commit 9d0fc8110e7e755239329c26f300d5fc9946d3ec
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Wed Jan 28 21:39:57 2009 +0100
+
+ OMAP3: Add Overo board
+
+ Add Overo board support.
+
+ Signed-off-by: Steve Sakoman <sakoman@gmail.com>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+ Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+
+commit f904cdbb68167c647887f19929ad295dbaac8862
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Tue Jan 27 18:19:12 2009 +0100
+
+ OMAP3: Add common power code, README, and BeagleBoard
+
+ Add BeagleBoard support, common power code and README.
+
+ Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 9cda4f104b5313fadc21b75aa781c7a6aaf6ea60
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Jan 28 08:31:10 2009 -0600
+
+ 85xx: Fix compile breakage with MPC8540EVAL
+
+ Configuring for MPC8540EVAL board...
+ mpc8540eval.c: In function 'checkboard':
+ mpc8540eval.c:53: error: invalid operands to binary /
+ make[1]: *** [mpc8540eval.o] Error 1
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1a448db77b10153703bc5e4ad13dd55d88beb1d6
+Author: Bryan Wu <bryan.wu@analog.com>
+Date: Sun Jan 18 23:04:27 2009 -0500
+
+ usb_scan_devices: fix output with no devices
+
+ We should check the return of usb_new_device() so that if no USB device is
+ found, we print out the right message rather than always saying "new usb
+ device found".
+
+ Signed-off-by: Bryan Wu <bryan.wu@analog.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit f1c1f540243438246aefb703fdcf16957e3a72e1
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Jan 22 10:11:21 2009 +0100
+
+ USB: Add high-speed (480Mb/s) to all USB related outputs
+
+ With this patch the USB related connection speed output ("usb tree" command and
+ debug output) is now high-speed enabled.
+
+ This patch also fixes a compilation warning when debugging is enabled.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit daa2dafb450a8073a4e42fd46cd4e995b208e4cb
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Jan 21 17:12:19 2009 +0100
+
+ USB: Add dcache support to the EHCI driver
+
+ This patch adds routines to handle (flush/invalidate) the dcache for the
+ QH and qTD structures and data buffers. This is needed on platforms using
+ this EHCI support with dcache enabled (like the MIPS VCT board port).
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 4e0ea0efc1e501186aca8577a4042fc6fa641602
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Jan 21 17:12:28 2009 +0100
+
+ USB: Add EHCI support for VCT EHCI controller
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 832e61418eedfea172bd2fdfd0ea0d199cc70a9d
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Jan 21 17:12:10 2009 +0100
+
+ USB: Add config option to call ehci_hcd_init() again after EHCI reset
+
+ This patch adds the config option CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ to call ehci_hcd_init() again after ehci_reset() is executed. This
+ is needed for the upcoming VCT EHCI support which needs to re-init
+ the hcd part again after the EHCI CMD_RESET is executed.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 597eb28bd9691266b7b804364cda577cdb51d106
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Jan 21 17:12:01 2009 +0100
+
+ USB: Fix speed detection on EHCI cntr with root hub transaction translators
+
+ This patch fixes an issue that the speed of USB devices was not detected
+ correctly on some EHCI controllers. This will be used on the upcoming VCT
+ EHCI support.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 20cc06611ea33fc0a67a5e56e6476379d2de3091
+Author: Thomas Abraham <t-abraham@ti.com>
+Date: Sun Jan 4 09:41:20 2009 +0530
+
+ usb : musb : Enabling USB MSC support for DM6446 (TI DaVinci) platform
+
+ Enabling USB MSC support for DM6446 (TI DaVinci) platform in the
+ configuration file.
+
+ Signed-off-by: Ravi Babu <ravibabu@ti.com>
+ Signed-off-by: Swaminathan S <swami.iyer@ti.com>
+ Signed-off-by: Thomas Abraham <t-abraham@ti.com>
+ Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 538ef967715322f64ee08efa2296d9682111b014
+Author: Thomas Abraham <t-abraham@ti.com>
+Date: Sun Jan 4 09:41:16 2009 +0530
+
+ usb : musb : Enabling DM6446 (TI DaVinci) USB module power
+
+ Enabling DM6446 (TI DaVinci) USB module power and MUSB low-level
+ controller hook up to USB core layer.
+
+ Signed-off-by: Ravi Babu <ravibabu@ti.com>
+ Signed-off-by: Swaminathan S <swami.iyer@ti.com>
+ Signed-off-by: Thomas Abraham <t-abraham@ti.com>
+ Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit e142e9f35f8ec61e74bf8019428b003f5070c33b
+Author: Thomas Abraham <t-abraham@ti.com>
+Date: Sun Jan 4 09:41:13 2009 +0530
+
+ usb : musb : Adding DM6446 (TI DaVinci) platform specific USB support
+
+ Adding DM6446 (TI DaVinci) platform specific USB functionality for
+ USB Phy and VBUS initialization.
+
+ Signed-off-by: Ravi Babu <ravibabu@ti.com>
+ Signed-off-by: Swaminathan S <swami.iyer@ti.com>
+ Signed-off-by: Thomas Abraham <t-abraham@ti.com>
+ Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit a9d39ebe91ecdd5ac0a0cf56ea162a19773db8da
+Author: Thomas Abraham <t-abraham@ti.com>
+Date: Sun Jan 4 09:41:09 2009 +0530
+
+ usb : musb : Adding USB VBUS enable functionality for DM644x DVEVM
+
+ Adding USB VBUS enable functionality for DM644x DVEVM (TI DaVinci)
+ platform.
+
+ Signed-off-by: Ravi Babu <ravibabu@ti.com>
+ Signed-off-by: Swaminathan S <swami.iyer@ti.com>
+ Signed-off-by: Thomas Abraham <t-abraham@ti.com>
+ Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit a142896934c755e679ba87e227a8e449f39b0012
+Author: Thomas Abraham <t-abraham@ti.com>
+Date: Sun Jan 4 09:41:03 2009 +0530
+
+ usb : musb : Adding host controller driver for Mentor USB controller
+
+ Adding Mentor USB core functionality and Mentor USB Host controller
+ functionality for Mentor USB OTG controller (musbhdrc).
+
+ Signed-off-by: Ravi Babu <ravibabu@ti.com>
+ Signed-off-by: Swaminathan S <swami.iyer@ti.com>
+ Signed-off-by: Thomas Abraham <t-abraham@ti.com>
+ Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit c7d703f3f3c3d6b020bda4cf633f8a6167c3cd2a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jan 1 18:27:27 2009 -0500
+
+ usb.h: use standard __LITTLE_ENDIAN from Linux headers
+
+ Rather than forcing people to define a custom "LITTLEENDIAN", just use the
+ __LITTLE_ENDIAN one from the Linux byteorder headers that every arch is
+ already setting up.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 7b6e31eb17e3ff76238a60803fc531517d516223
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Wed Dec 31 10:33:56 2008 +0100
+
+ USB ehci ixp4xx support
+
+ Add USB ehci ixp4xx host controller. Test on ixdp465 board.
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 1ed9f9adc88218841dfeb60b9094a5a548bff009
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Wed Dec 31 10:33:22 2008 +0100
+
+ USB ehci remove infinite loop and use handshake function
+
+ USB ehci code cleanup. Use handshake instead of infinite while loop
+ to check the STD_ASS status
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 8fea2914ac974029b65926ef8247d908f84d202d
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Wed Dec 31 10:32:41 2008 +0100
+
+ Add initial support for USB ehci pci
+
+ Add USB ehci pci support. This patch doesn't include any
+ pci_ids and it is not tested on real hardware.
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 14e4111cdab7e7738ff6a203d445e4d8377f058f
+Author: Bryan Wu <Bryan.Wu@analog.com>
+Date: Thu Jan 1 19:48:07 2009 -0500
+
+ usb_storage: do not reset SanDisk Corporation U3 Cruzer Micro USB thumb drive
+
+ The SanDisk Corporation U3 Cruzer Micro 1/4GB Flash Drive 000016244373FFB4
+ does not like to be reset, so check for it.
+
+ Signed-off-by: Bryan Wu <bryan.wu@analog.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 1eb734fed3b79a5e6106dad16e88041894fdab30
+Author: Thomas Abraham <t-abraham@ti.com>
+Date: Sun Jan 4 12:15:35 2009 +0530
+
+ usb : usb_kbd : Populating 'priv' member of USB keyboard device_t structure
+
+ This patch populates the 'priv' field of the USB keyboard device_t
+ structure. The 'priv' field is populated with the address of the
+ 'struct usb_device' structure that represents the USB device.
+
+ The 'priv' field can then be used in the 'usb_event_poll' function to
+ determine the USB device that requires to be polled. An
+ example of its usage in 'usb_event_poll' function is as below.
+
+ device_t *dev;
+ struct usb_device *usb_kbd_dev;
+
+ <snip>
+
+ dev = device_get_by_name("usbkbd");
+ usb_kbd_dev = (struct usb_device *)dev->priv;
+ iface = &usb_kbd_dev->config.if_desc[0];
+
+ Signed-off-by: Thomas Abraham <t-abraham@ti.com>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 366523c26b6320af171459b19e6e0e9e3baa83ca
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Thu Dec 18 10:05:37 2008 +0100
+
+ USB change speed
+
+ USB changes the speed according to the port status
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit c0d722fe7ee1cb452dfd9246419188b3f6d9c4df
+Author: Remy Böhmer <linux@bohmer.net>
+Date: Sat Dec 13 22:51:58 2008 +0100
+
+ EHCI fix code and ixp4xx test.
+ USB ehci configuration parameter:
+
+ #define CONFIG_CMD_USB 1
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_EHCI
+ #define CONFIG_USB_EHCI_IXP4XX 1
+ #define CONFIG_EHCI_IS_TDI 1
+ #define CONFIG_EHCI_DESC_BIG_ENDIAN 1
+ #define CONFIG_EHCI_MMIO_BIG_ENDIAN 1
+ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
+ #define CONFIG_LEGACY_USB_INIT_SEQ 1
+
+ 2 USB Device(s) found
+ scanning bus for storage devices... 0 Storage Device(s) found
+ => usb tree
+
+ Device Tree:
+ 1 Hub (1.5MBit/s, 0mA)
+ | u-boot EHCI Host Controller
+ |
+ |+-2 Mass Storage (12MBit/s, 100mA)
+ Sony Storage Media 0C07040930296
+
+ =>
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit 51ab142b8b546d5e627b2c8c36d0adae222565f7
+Author: michael <michael@panicking.retis>
+Date: Thu Dec 11 13:43:55 2008 +0100
+
+ [PATCH] This patch add varius fix to the ehci.
+ - fix ehci_readl, ehci_writel
+ - introduce new define in ehci.h
+ - introduce the handshake function for waiting on a register
+ - fix usb_ehci_fsl with the new HC_LENGTH macro
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit db63299b1dd2894ade542278210bccd046de6435
+Author: michael <michael@panicking.retis>
+Date: Wed Dec 10 17:55:19 2008 +0100
+
+ [PATCH] Fix EHCI usb. I start to test on a
+ IXP465 board and I find some errors in the code. This
+ patch fix:
+ - descriptor initizialization (config, interface and endpoint
+ must be one next-to the other when the USB_DT_CONFIG message
+ is send.
+ - FIX little/endian bigendian (introduce the CONFIG_EHCI_DESC_BIG_ENDIAN
+ and the CONFIG_EHCI_MMIO_BIG_ENDIAN)
+ - Introduce the linux version of the usb_config_descriptor and
+ usb_interface descriptor. This descriptor does't contains
+ u-boot extension.
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit 6b92487dcf9afe83a3570153d66940fdb293be76
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Fri Nov 28 13:22:09 2008 +0100
+
+ USB ehci freescale support
+
+ Add USB ehci freescale support
+
+ Signed-off-by: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+ Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit aaf098cfeed04595d4c5100ffd39095d79edbf90
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Fri Nov 28 13:20:46 2008 +0100
+
+ USB ehci core support
+
+ Add USB ehci core support
+
+ Signed-off-by: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+ Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit 3e126484df7868e341545cce740b24b62b0cd3b7
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Fri Nov 28 13:19:19 2008 +0100
+
+ Prepare USB layer for ehci
+
+ Prepare USB layer for ehci support
+
+ Signed-off-by: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+ Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit a0cb3fc31e58996a1c5732715ac04159d4d284fd
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date: Wed Dec 10 15:52:06 2008 +0100
+
+ USB storage cleanup patch
+
+ Cleanup usb storage
+
+ Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it>
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit fe033ad6d0883063fe857237abb9436fab03208c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 06:02:55 2008 -0400
+
+ Blackfin: fixup misc warnings such as printf's and missing casts
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1f4a3bb50343719c434d7e2541a2f86480a6d25c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Oct 12 22:09:26 2008 -0400
+
+ Blackfin: convert old boards to use COBJS-y Makefile style
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1f75d6f0ff005762d3e6ad92ae4ce2ab366b3bb5
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 22:38:37 2008 -0400
+
+ Blackfin: bf533-stamp: rewrite resource swap logic
+
+ The old swap function tended to clobber unrelated pins and screw up masks.
+ Rewrite the thing from scratch so it only uses the resources it needs.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 29d4ea0a9073c82469184331010136f52edf8db6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 22:08:42 2008 -0400
+
+ Blackfin: bootldr: implement BF53x/BF56x LDR loader
+
+ The BF53x/BF56x parts do not have an on-chip ROM to boot LDRs out of
+ arbitrary memory locations, so implement a basic one in software.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8b35e3aeff6c2d747c37697997b3f8a808432329
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 22:05:42 2008 -0400
+
+ Blackfin: implement real write support for OTP
+
+ Now that real documentation has been released for the OTP interface and
+ the on-chip ROM wrt writing/timings, implement support for reading/writing
+ as well as dumping/locking.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 9372c3214808fab545227d8d0f76b3bfcc6760ec
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 22:04:05 2008 -0400
+
+ Blackfin: update on-chip ROM API
+
+ This brings the API for the on-chip ROM in line with the toolchain and
+ hardware documentation.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 7633903bff432ec7b27905dce7396958553f2be6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:52:17 2008 -0400
+
+ Blackfin: allow serial console to be disabled
+
+ Some devices have no UART device pulled out, so allow people to disable the
+ driver completely in favor of other methods (like JTAG-console).
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 36ea8e9ad1107af12d244bba8c73e85b9f655e45
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:51:20 2008 -0400
+
+ Blackfin: support console-over-JTAG
+
+ The Blackfin JTAG has the ability to pass data via a back-channel without
+ halting the processor. Utilize that channel to emulate a console.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit cf8f2efb5f39c5225da92391c14a07eecbeca881
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:49:06 2008 -0400
+
+ Blackfin: handle new anomalies with reset
+
+ Workaround fun new anomalies related to software reset of the processor.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b1e9435b643043dd8fbd1fcc47309c6acb7b3c8e
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:44:00 2008 -0400
+
+ Blackfin: pass RETX to Linux
+
+ Make sure we save the value of RETX at power on and then pass it on to the
+ kernel so that it can nicely debug a "double-fault-caused-a-reset" crash.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b5eba3fafcccd1979380f12a256bd0e19be3d61e
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:40:26 2008 -0400
+
+ Blackfin: clarify relocation comment during init
+
+ People often ask questions about the init process and when things go
+ from flash to relocated base, so clarify the comments a bit.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 95433f6d43ede6b40c1d900f3f704c839aa074f1
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:23:41 2008 -0400
+
+ Blackfin: just set SP register directly during init
+
+ No need to set the SP register indirectly to the configured value when it
+ can be set directly.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 51230e6e356ccf4c932e0c4ff54f1e49da02285c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 21:15:53 2008 -0400
+
+ Blackfin: add portmuxing for UARTs on the BF51x
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 4f6a313240c531042f16909a3a170ab047b95779
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 1 01:26:29 2008 -0400
+
+ Blackfin: respect CONFIG_CLKIN_HALF
+
+ As pointed out by Ivan Koryakovskiy, the initialization code was not
+ actually respecting the CONFIG_CLKIN_HALF option when configuring the
+ PLL_CTL register.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit dc2bfb0b58d7462b9eba68f3ae38e38cada0ad33
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Jun 1 01:21:34 2008 -0400
+
+ Blackfin: use common memcpy routine during init
+
+ Rather than using a local custom memcpy function, just call the existing
+ optimized Blackfin version.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 362c943347364e9373af4c5530778491ab56ec2e
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Apr 9 02:27:06 2008 -0400
+
+ Blackfin: set default boot SPI CS for BF538/BF539
+
+ The BF538/BF539 use CS2 for booting off of rather than CS1 like newer
+ Blackfin parts.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 74dde80bd5d55bc146630853ca191aaeea7c30f4
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Apr 9 02:20:59 2008 -0400
+
+ Blackfin: punt unused BF533-STAMP definitions
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit fee531eeefc3b5f2c63c7fe27b9f55d924c59c26
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Apr 18 20:44:11 2008 -0400
+
+ Blackfin: resurrect BF533-STAMP video splash driver
+
+ This video driver used to live in the Blackfin cpu directory, but it was
+ lost during the unification process. This brings it back.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit a750d038f2548d846ea1e046d873dc932d041319
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Apr 9 02:31:29 2008 -0400
+
+ Blackfin: tighten up post memory coding style
+
+ No functional changes here; just cleanup code style a bit.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0649908f92c9bd214dd139aa3d4698c1654a45c6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Apr 9 02:29:18 2008 -0400
+
+ Blackfin: bf537-stamp nand: fix more style errors in previous commit
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 41f3325ae9add641036d7cb362e884b698e53f07
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 20:31:17 2008 -0400
+
+ Blackfin: drop dead/wrong debug code in initdram()
+
+ The DEBUG code in initdram() is quite old and was never really useful, so
+ just drop it altogether. Common Blackfin debug code does a better job.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 65ba1abd3b90e0b2585745809b78e2651bd3bacb
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 20:30:28 2008 -0400
+
+ Blackfin: bf533-ezkit: shuffle flash defines a little
+
+ Some of the flash defines weren't in the correct location and caused build
+ problems in some configurations, so let's move types and defines to better
+ local locations.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit be853bf86b41e91f4c422f0f56fdf87ea3191266
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 04:16:47 2008 -0400
+
+ Blackfin: overhaul i2c driver
+
+ The current Blackfin i2c driver does not work properly with certain devices
+ due to it breaking up transfers incorrectly. This is a rewrite of the
+ driver and relocates it to the newer place in the source tree.
+
+ Also remove duplicated I2C speed defines in Blackfin board configs and
+ disable I2C slave address usage since it isn't implemented.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b6edc719a106ab7fa6e6950b4d97bc39c1368e45
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 04:00:07 2008 -0400
+
+ Blackfin: respect CONFIG_SYS_MONITOR_LEN for default flash protection
+
+ Respect the CONFIG_SYS_MONITOR_LEN define rather than assuming a size of
+ 128kB when setting up the default flash protection region for U-Boot
+ itself.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 78a0ba7dc24c9682371f6ee8549b569fb573a329
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 03:57:39 2008 -0400
+
+ Blackfin: respect/check CONFIG_SYS_GBL_DATA_SIZE
+
+ When setting up the global data, rather than relying on sizeof(), use the
+ common CONFIG_SYS_GBL_DATA_SIZE define.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 01815c2d06c5b838f2cd536703e47bd2c9148194
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 03:52:24 2008 -0400
+
+ Blackfin: implement general support for CONFIG_STATUS_LED
+
+ Here are the Blackfin-specific and board-independent pieces for status leds.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 6882b5a79a3247494b62c05015fa672557f1bfaa
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 03:49:32 2008 -0400
+
+ Blackfin: do not init i2c in Blackfin board init
+
+ The common code takes care of calling i2c_init() when needed, so no point
+ in us doing it as well.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 1118ea73698eee6e72ef5cbfc00e41746040304f
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 03:42:20 2008 -0400
+
+ Blackfin: bfin_mac: update port muxing
+
+ Adds support more Blackfin parts and fixes broken muxing for older ones.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 05b75e48832fc4afeecf8e76d704349557dffa35
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Oct 6 03:35:44 2008 -0400
+
+ Blackfin: fix dcache handling when doing dma memcpy's
+
+ Our dcache invalidate function doesn't just invalidate, it also flushes.
+ So rename the function accordingly and fix the dma_memcpy() function so it
+ doesn't inadvertently corrupt the data destination.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 68e5632494168095d75f120af70043b68afd2476
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 18:56:56 2008 -0400
+
+ Blackfin: dont generate ldrs with --force
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 746290dfd86a70b41fc5fdd3df1424a647d5c5e8
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 18:55:30 2008 -0400
+
+ Blackfin: pass --bmode/--initcode when creating ldr
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0332e4df71fccf9a96c5a4393e3c5d5daa50880a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 18:39:27 2008 -0400
+
+ Blackfin: minimize time cache is turned off when replacing cplb entries
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 21d631360430cf0ae9099612273cd4de28911ba9
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 15:31:13 2008 -0400
+
+ Blackfin: split cache handling out of dma_memcpy()
+
+ Creating a new dma_memcpy() function that skips all cache checks allows us
+ to use the function in very early init where the cache is not yet setup.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d31eb38512bed377d5d4b3c696662e52120a2e4c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 15:30:49 2008 -0400
+
+ Blackfin: abort dma_memcpy() for L1 scratchpad
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 81b799add709177e838466461f7b9989488b0fd5
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 15:27:52 2008 -0400
+
+ Blackfin: rename bootm.c to boot.c
+
+ The boot file contains functions for more than just "bootm", so rename it
+ accordingly.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d7ca7dd5bfc418ac173e9d2712f6cc2d8147a091
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 13:22:37 2008 -0400
+
+ Blackfin: set more sane default board config values
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 36cd52a00794fb15ffab05d640acca92d7482993
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 15:24:59 2008 -0400
+
+ Blackfin: convert CMD_LINE_ADDR to CONFIG_LINUX_CMDLINE_{ADDR,SIZE}
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c8054bc12e00669bd7588f2b30fef48aa94babac
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 13:21:27 2008 -0400
+
+ Blackfin: add bit defines for DDR parts
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 154502fe0796f3b7a4698378c5d2080ae28a9782
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Aug 7 13:21:11 2008 -0400
+
+ Blackfin: add defines to describe active bootrom behavior
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2b6fd5c77db9c6ed3cea9799c86ff922cf0107b2
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date: Tue Jan 27 16:03:53 2009 -0600
+
+ mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 build
+
+ extend commit c70564e6b1bd08f3230182392238907f3531a87e
+ "NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency
+ to the simpc8313 build and fix this:
+
+ ...Large Page NAND...Configuring for SIMPC8313 board...
+ nand_boot_fsl_elbc.o: In function `nand_boot':
+ nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache'
+ make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1
+ make: *** [nand_spl] Error 2
+
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 54a7cc4912feefa45be961cc47cc159563725d2f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jan 28 09:25:31 2009 +0100
+
+ mpc8536ds.c: include sata.h to for needed function prototypes
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2fb2604d5c20beb061b0a94282b7f6eb14d00cb8
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jan 27 18:03:12 2009 -0600
+
+ Command usage cleanup
+
+ Remove command name from all command "usage" fields and update
+ common/command.c to display "name - usage" instead of
+ just "usage". Also remove newlines from command usage fields.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 79621bc10ba8b8c45d348994aba5b9e4923cb77b
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jan 27 18:03:11 2009 -0600
+
+ amcc: Clean up command usage output
+
+ Update taihu and taishan commands to use cmd_usage() function
+ to display usage messages.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 62c3ae7c6ef215b1afa614abdf61acf077752207
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jan 27 18:03:10 2009 -0600
+
+ Standardize command usage messages with cmd_usage()
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 84cde2bb409c07c6ef36a192d194359d4e9ccd70
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jan 27 18:03:09 2009 -0600
+
+ pcs440ep: Clean up led command definition
+
+ The pcs440ep's led command usage formatting is non-standard. It
+ was made standard in preparation for larger command usage updates.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 9507e7867e04dc48c80ee333c2a9a5e70e887f62
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Jan 27 18:03:08 2009 -0600
+
+ Clean up diufb command definitions
+
+ The diufb command usage formatting is non-standard. It was
+ made standard in preparation for larger command usage updates.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 6450a8485836fc80615ae6de6a864c33369b44f5
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jan 28 00:29:26 2009 +0100
+
+ Update CHANGELOG, tiny coding style cleanup.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit cf7e399fb35b3aea90a27d1df72f45f5d6156204
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Jan 27 16:12:21 2009 -0500
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+commit de832a99414ff06a4b2cdc9f5280b387da039834
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Jan 26 10:05:20 2009 +0100
+
+ nand_spl: Fix compile problem with board_nand_init() prototype
+
+ This patch removes the now obsolete and additionally wrongly defined
+ board_nand_init() prototype from nand_spl/nand_boot.c.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
commit e8eac437189430d8e04a5d254ed92c58bc534a79
Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Date: Wed Jan 14 08:44:26 2009 -0500
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 71a040f4f556cca4d30f06805d82e717b3ef1020
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date: Fri Nov 21 12:06:26 2008 +0900
+
+ sh: sh7763rdp: Update sh7763rdp config
+
+ Add CONFIG_NET_MULTI in config file, because sh_eth changed new newwork API.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit ba705b5b1a97b47388ed48858bef6bf7b6bfcd56
+Author: Gary Jennejohn <garyj@denx.de>
+Date: Thu Nov 20 12:28:38 2008 +0100
+
+ mgcoge make ether_scc.c work with CONFIG_NET_MULTI
+
+ This change is needed for mgcoge because it uses two ethernet drivers.
+
+ Add a check for the presence of the PIGGY board on mgcoge. Without this
+ board networking cannot work and the initialization must be aborted.
+
+ Only allocate rtx once to prevent DPRAM exhaustion.
+
+ Initialize ether_scc.c and the keymile-specific HDLC driver (to be added
+ soon) in eth.c.
+
+ Signed-off-by: Gary Jennejohn <garyj@denx.de>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit bd3980cc095af1728b994cdd8bf1ac430b6289e6
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date: Fri Nov 21 12:04:18 2008 +0900
+
+ sh: sh_eth: Change new network API
+
+ sh_eth used old network API. This patch changed new API.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 890a02e8ee6b8c26a6e3e505e1a2d29cd73aa6f6
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Nov 12 13:31:02 2008 +0100
+
+ net: smc911x: Make register read/write functions weak
+
+ This patch changes the reg_read/_write to smc911x_reg_read/_write
+ and defines then as weak so that they can be overridden by board
+ specific version.
+
+ This will be used by the upcoming VCTH board support.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8b69b563039989885969d24465c56f8ac4c07c4c
+Author: Heiko Schocher <hs@denx.de>
+Date: Thu Nov 20 09:57:14 2008 +0100
+
+ powerpc: net: support for the SMSC LAN8700 PHY
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit d5254f149da9e6cd649d887b042ce577ef3ba78d
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Sat Jan 24 18:10:37 2009 +0100
+
+ Initial support for Nomadik 8815 development board
+
+ The NMDK8815 board is distributed by ST Microelectornics.
+ Other (proprietary) code must be run to unlock the CPU before
+ U-Boot runs. doc/README.nmdk8815 outlines the boot sequence.
+
+ This is the initial port, with basic infrastructure and
+ a working serial port.
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7d264c1ef267cfc8d928bc8577a7cc907f2f5e47
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:18 2008 +0100
+
+ OMAP3: Add I2C support
+
+ Add I2C support.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit b1c3bf99fb477675d464aeadb5dd69d2cbc9dc7b
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:17 2008 +0100
+
+ OMAP3: Add MMC support
+
+ Add MMC support.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 12201a13547ec22ddcdae278e74465e54a3be60c
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:16 2008 +0100
+
+ OMAP3: Add NAND support
+
+ Add NAND support.
+
+ Signed-off-by: Nishanth Menon <nm@ti.com>
+ Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 91eee546737ae21d930af479530997174c342b13
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:15 2008 +0100
+
+ OMAP3: Add common board, interrupt and system info
+
+ Add common board, interrupt and system info code.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 5ed3e8659e5373f6a229877ac506c0b00a054fb8
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:14 2008 +0100
+
+ OMAP3: Add common clock, memory and low level code
+
+ Add common clock, memory and low level code
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 0b02b184003e6a5023e05d5f31de54db279b1431
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:13 2008 +0100
+
+ OMAP3: Add common cpu and start code
+
+ Add common cpu and start code.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit a8b6450546cd507d331b8fde384791d84bde5651
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:12 2008 +0100
+
+ OMAP3: Add OMAP3, memory and function prototype headers
+
+ Add OMAP3, memory and function prototype header files for OMAP3.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 2c803210a464abbac35752ca1c737514360b4c32
+Author: Dirk Behme <dirk.behme@googlemail.com>
+Date: Sun Dec 14 09:47:11 2008 +0100
+
+ OMAP3: Add pin mux, clock and cpu headers
+
+ Add pin mux, clock and cpu header files for OMAP3.
+
+ Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 685533646f4ff17a84ec9265cabb60af325b6e1f
+Author: Maxim Artamonov <scn1874@yandex.ru>
+Date: Wed Dec 3 05:38:17 2008 +0300
+
+ bugfix for i.mx31 CCM_UPCTL reg
+
+ Signed-off-by: Maxim Artamonov <scn1874 at yandex.ru>
+
commit 24113a44ed5cd3257a0237c3961e121812fca6db
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Dec 30 03:15:38 2008 -0500
Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+commit 4cd8ed40615a7d741ef2f09ee53779ec6907b8a6
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Tue Dec 9 23:26:31 2008 -0800
+
+ Fix compile error in building MBX860T.
+ Bug was introduced in 9eb79bd8856bcab896ed5e1f1bca159807a124dd
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
commit 97a24a78ee6f34b89b821cb70eda1cf34aa11d97
Author: Jerry Van Baren <gvb.uboot@gmail.com>
Date: Mon Nov 24 08:15:02 2008 -0500
TQM8540 \
TQM8541 \
TQM8548 \
+ TQM8548_AG \
+ TQM8548_BE \
TQM8555 \
TQM8560 \
XPEDITE5200 \
TQM8540_config \
TQM8541_config \
TQM8548_config \
+TQM8548_AG_config \
+TQM8548_BE_config \
TQM8555_config \
TQM8560_config: unconfig
@mkdir -p $(obj)include
- @CTYPE=$(subst TQM,,$(@:_config=)); \
- $(XECHO) "... TQM"$${CTYPE}; \
+ @BTYPE=$(@:_config=); \
+ CTYPE=$(subst TQM,,$(subst _AG,,$(subst _BE,,$(@:_config=)))); \
+ $(XECHO) "... "$${BTYPE}" (MPC"$${CTYPE}")"; \
echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
- echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
+ echo "#define CONFIG_$${BTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
- echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
+ echo "#define CONFIG_BOARDNAME \"$${BTYPE}\"">>$(obj)include/config.h;
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
+ @echo "CONFIG_$(@:_config=) = y">>$(obj)include/config.mk;
XPEDITE5200_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
CONFIG_SYS_BAUDRATE_TABLE, see below.
CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
+- Console Rx buffer length
+ With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
+ the maximum receive buffer length for the SMC.
+ This option is actual only for 82xx and 8xx possible.
+ If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
+ must be defined, to setup the maximum idle timeout for
+ the SMC.
+
- Interrupt driven serial port input:
CONFIG_SERIAL_SOFTWARE_FIFO
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EEPROM * EEPROM read/write support
CONFIG_CMD_ELF * bootelf, bootvx
- CONFIG_CMD_ENV saveenv
+ CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT partition support
CONFIG_CMD_FDOS * Dos diskette Support
- CONFIG_SYS_64BIT_STRTOUL:
Adds simple_strtoull that returns a 64bit value
+- CONFIG_NS16550_MIN_FUNCTIONS:
+ Define this if you desire to only have use of the NS16550_init
+ and NS16550_putc functions for the serial driver located at
+ drivers/serial/ns16550.c. This option is useful for saving
+ space for already greatly restricted images, including but not
+ limited to NAND_SPL configurations.
+
Low Level (hardware related) configuration options:
---------------------------------------------------
CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
+- CONFIG_PCI_DISABLE_PCIE:
+ Disable PCI-Express on systems where it is supported but not
+ required.
+
- CONFIG_SPD_EEPROM
Get DDR timing information from an I2C EEPROM. Common
with pluggable memory modules such as SODIMMs
ifeq ($(ARCH),ppc)
LOAD_ADDR = 0x40000
endif
-
-#ifeq ($(ARCH),arm)
-#LOAD_ADDR = 0xc100000
-#endif
+ifeq ($(ARCH),arm)
+LOAD_ADDR = 0x1000000
+endif
include $(TOPDIR)/config.mk
#if defined(CONFIG_PPC)
.text
-
.globl _start
_start:
+ lis %r11, search_hint@ha
+ addi %r11, %r11, search_hint@l
+ stw %r1, 0(%r11)
b main
mtctr %r11
bctr
+#elif defined(CONFIG_ARM)
+
+ .text
+ .globl _start
+_start:
+ ldr ip, =search_hint
+ str sp, [ip]
+ b main
+
+
+ .globl syscall
+syscall:
+ ldr ip, =syscall_ptr
+ ldr pc, [ip]
+
+#else
+#error No support for this arch!
+#endif
.globl syscall_ptr
syscall_ptr:
.align 4
.long 0
-#else
-#error No support for this arch!
-#endif
+
+ .globl search_hint
+search_hint:
+ .long 0
int main(int argc, char *argv[])
{
- int rv = 0;
- int h, i, j;
- int devs_no;
+ int rv = 0, h, i, j, devs_no;
struct api_signature *sig = NULL;
ulong start, now;
struct device_info *di;
+ lbasize_t rlen;
if (!api_search_sig(&sig))
return -1;
if (devs_no == 0)
return -1;
-
printf("\n*** Show devices ***\n");
for (i = 0; i < devs_no; i++) {
test_dump_di(i);
if ((rv = ub_dev_open(i)) != 0)
errf("open device %d error %d\n", i, rv);
- else if ((rv = ub_dev_read(i, buf, 1, 0)) != 0)
+ else if ((rv = ub_dev_read(i, buf, 1, 0, &rlen)) != 0)
errf("could not read from device %d, error %d\n", i, rv);
-
- printf("Sector 0 dump (512B):\n");
- test_dump_buf(buf, 512);
+ else {
+ printf("Sector 0 dump (512B):\n");
+ test_dump_buf(buf, 512);
+ }
ub_dev_close(i);
}
printf("%s = %s\n", env, ub_env_get(env));
/* reset */
+ printf("\n*** Resetting board ***\n");
ub_reset();
printf("\nHmm, reset returned...?!\n");
/*
- * (C) Copyright 2007 Semihalf
- *
- * Written by: Rafal Jaworowski <raj@semihalf.com>
+ * (C) Copyright 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* returns 1/0 depending on found/not found result
*/
-int api_search_sig(struct api_signature **sig) {
-
+int api_search_sig(struct api_signature **sig)
+{
unsigned char *sp;
+ uint32_t search_start = 0;
+ uint32_t search_end = 0;
if (sig == NULL)
return 0;
- sp = (unsigned char *)API_SEARCH_START;
+ if (search_hint == 0)
+ search_hint = 255 * 1024 * 1024;
+
+ search_start = search_hint & ~0x000fffff;
+ search_end = search_start + API_SEARCH_LEN - API_SIG_MAGLEN;
- while ((sp + (int)API_SIG_MAGLEN) < (unsigned char *)API_SEARCH_END) {
+ sp = (unsigned char *)search_start;
+ while ((sp + API_SIG_MAGLEN) < (unsigned char *)search_end) {
if (!memcmp(sp, API_SIG_MAGIC, API_SIG_MAGLEN)) {
*sig = (struct api_signature *)sp;
if (valid_sig(*sig))
syscall(API_RESET, NULL);
}
-#define MR_MAX 5
-static struct mem_region mr[MR_MAX];
+static struct mem_region mr[UB_MAX_MR];
static struct sys_info si;
struct sys_info * ub_get_sys_info(void)
memset(&si, 0, sizeof(struct sys_info));
si.mr = mr;
- si.mr_no = MR_MAX;
+ si.mr_no = UB_MAX_MR;
memset(&mr, 0, sizeof(mr));
if (!syscall(API_GET_SYS_INFO, &err, (u_int32_t)&si))
*
* devices
*
- * Devices are identified by handles: numbers 0, 1, 2, ..., MAX_DEVS-1
+ * Devices are identified by handles: numbers 0, 1, 2, ..., UB_MAX_DEV-1
*
***************************************************************************/
-#define MAX_DEVS 6
-
-static struct device_info devices[MAX_DEVS];
+static struct device_info devices[UB_MAX_DEV];
struct device_info * ub_dev_get(int i)
{
- return ((i < 0 || i >= MAX_DEVS) ? NULL : &devices[i]);
+ return ((i < 0 || i >= UB_MAX_DEV) ? NULL : &devices[i]);
}
/*
struct device_info *di;
int n = 0;
- memset(&devices, 0, sizeof(struct device_info) * MAX_DEVS);
+ memset(&devices, 0, sizeof(struct device_info) * UB_MAX_DEV);
di = &devices[0];
if (!syscall(API_DEV_ENUM, NULL, di))
while (di->cookie != NULL) {
- if (++n >= MAX_DEVS)
+ if (++n >= UB_MAX_DEV)
break;
/* take another device_info */
struct device_info *di;
int err = 0;
- if (handle < 0 || handle >= MAX_DEVS)
+ if (handle < 0 || handle >= UB_MAX_DEV)
return API_EINVAL;
di = &devices[handle];
{
struct device_info *di;
- if (handle < 0 || handle >= MAX_DEVS)
+ if (handle < 0 || handle >= UB_MAX_DEV)
return API_EINVAL;
di = &devices[handle];
*/
static int dev_valid(int handle)
{
- if (handle < 0 || handle >= MAX_DEVS)
+ if (handle < 0 || handle >= UB_MAX_DEV)
return 0;
if (devices[handle].state != DEV_STA_OPEN)
return 1;
}
-int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start)
+int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start,
+ lbasize_t *rlen)
{
struct device_info *di;
lbasize_t act_len;
di = &devices[handle];
if (!syscall(API_DEV_READ, &err, di, buf, &len, &start, &act_len))
- return -1;
-
- if (err)
- return err;
+ return API_ESYSC;
- if (act_len != len)
- return API_EIO;
+ if (!err && rlen)
+ *rlen = act_len;
- return 0;
+ return err;
}
static int dev_net_valid(int handle)
return 1;
}
-int ub_dev_recv(int handle, void *buf, int len)
+int ub_dev_recv(int handle, void *buf, int len, int *rlen)
{
struct device_info *di;
int err = 0, act_len;
di = &devices[handle];
if (!syscall(API_DEV_READ, &err, di, buf, &len, &act_len))
- return -1;
+ return API_ESYSC;
- if (err)
- return -1;
+ if (!err && rlen)
+ *rlen = act_len;
- return act_len;
+ return (err);
}
int ub_dev_send(int handle, void *buf, int len)
di = &devices[handle];
if (!syscall(API_DEV_WRITE, &err, di, buf, &len))
- return -1;
+ return API_ESYSC;
return err;
}
syscall(API_ENV_SET, NULL, (uint32_t)name, (uint32_t)value);
}
-
static char env_name[256];
const char * ub_env_enum(const char *last)
#ifndef _API_GLUE_H_
#define _API_GLUE_H_
-#define API_SEARCH_START (255 * 1024 * 1024) /* start at 1MB below top RAM */
-#define API_SEARCH_END (256 * 1024 * 1024 - 1) /* ...and search to the end */
+#define API_SEARCH_LEN (3 * 1024 * 1024) /* 3MB search range */
-int syscall(int, int *, ...);
-void * syscall_ptr;
+#define UB_MAX_MR 5 /* max mem regions number */
+#define UB_MAX_DEV 6 /* max devices number */
+
+extern void *syscall_ptr;
+extern uint32_t search_hint;
+int syscall(int, int *, ...);
int api_search_sig(struct api_signature **sig);
/*
- * ub_ library calls are part of the application, not U-Boot code! They are
- * front-end wrappers that are used by the consumer application: they prepare
- * arguments for particular syscall and jump to the low level syscall()
+ * The ub_ library calls are part of the application, not U-Boot code! They
+ * are front-end wrappers that are used by the consumer application: they
+ * prepare arguments for particular syscall and jump to the low level
+ * syscall()
*/
/* console */
int ub_dev_enum(void);
int ub_dev_open(int handle);
int ub_dev_close(int handle);
-int ub_dev_read(int handle, void *buf,
- lbasize_t len, lbastart_t start);
+int ub_dev_read(int handle, void *buf, lbasize_t len,
+ lbastart_t start, lbasize_t *rlen);
int ub_dev_send(int handle, void *buf, int len);
-int ub_dev_recv(int handle, void *buf, int len);
+int ub_dev_recv(int handle, void *buf, int len, int *rlen);
struct device_info * ub_dev_get(int);
#endif /* _API_GLUE_H_ */
ARTICIAS_SYS_BUS,
ARTICIAS_SYS_PHYS,
ARTICIAS_SYS_MAXSIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(articiaS_hose.regions + 1,
#include <i2c.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
CLOCK_SCCR1_LPC_EN | \
CLOCK_SCCR1_PSCFIFO_EN | \
CLOCK_SCCR1_DDR_EN | \
CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_PATA_EN | \
CLOCK_SCCR1_PCI_EN | \
CLOCK_SCCR1_TPR_EN)
*/
im->clk.sccr[0] = SCCR1_CLOCKS_EN;
im->clk.sccr[1] = SCCR2_CLOCKS_EN;
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+ im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
+#endif
return 0;
}
}
};
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+ /* FUNC0=PCI Sets next 54 to PCI pads */
+ {
+ IOCTL_PCI_AD31, 54, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+ }
+};
+
int checkboard (void)
{
ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
/* initialize function mux & slew rate IO inter alia on IO Pins */
-
iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
+ if (SVR_MJREV (im->sysconf.spridr) >= 2) {
+ iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+ }
return 0;
}
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ debug ("init_ide_reset\n");
+
+ /*
+ * Clear the reset bit to reset the interface
+ * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
+ */
+ immr->pata.pata_ata_control = 0;
+ udelay(100);
+ /* Assert the reset bit to enable the interface */
+ immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+ udelay(100);
+
+}
+
+void ide_set_reset (int idereset)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ debug ("ide_set_reset(%d)\n", idereset);
+
+ if (idereset) {
+ immr->pata.pata_ata_control = 0;
+ udelay(100);
+ } else {
+ immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+ udelay(100);
+ }
+}
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+int ide_preinit (void)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ long t;
+ const struct {
+ short t0;
+ short t1;
+ short t2_8;
+ short t2_16;
+ short t2i;
+ short t4;
+ short t9;
+ short tA;
+ } pio_specs = {
+ .t0 = 600,
+ .t1 = 70,
+ .t2_8 = 290,
+ .t2_16 = 165,
+ .t2i = 0,
+ .t4 = 30,
+ .t9 = 20,
+ .tA = 50,
+ };
+ union {
+ u32 config;
+ struct {
+ u8 field1;
+ u8 field2;
+ u8 field3;
+ u8 field4;
+ }bytes;
+ }cfg;
+
+ debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
+ (u32)&immr->pata);
+
+ /* Set the reset bit to 1 to enable the interface */
+ immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+
+ /* Init timings : we use PIO mode 0 timings */
+ t = 1000000000 / gd->ips_clk; /* period in ns */
+ cfg.bytes.field1 = 3;
+ cfg.bytes.field2 = 3;
+ cfg.bytes.field3 = (pio_specs.t1 + t) / t;
+ cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
+
+ immr->pata.pata_time1 = cfg.config;
+
+ cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
+ cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
+ cfg.bytes.field3 = 1;
+ cfg.bytes.field4 = (pio_specs.t4 + t) / t;
+
+ immr->pata.pata_time2 = cfg.config;
+
+ cfg.config = immr->pata.pata_time3;
+ cfg.bytes.field1 = (pio_specs.t9 + t) / t;
+
+ immr->pata.pata_time3 = cfg.config;
+ debug ("PATA preinit complete.\n");
+
+ return 0;
+}
+
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
#include <video_fb.h>
#endif
+#ifdef CONFIG_FSL_DIU_LOGO_BMP
extern unsigned int FSL_Logo_BMP[];
+#else
+#define FSL_Logo_BMP NULL
+#endif
static int xres, yres;
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
}
+char *valid_bmp(char *addr)
+{
+ unsigned long h_addr;
+
+ h_addr = simple_strtoul(addr, NULL, 16);
+ if (h_addr < CONFIG_SYS_FLASH_BASE ||
+ h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+ printf("bmp addr %lx is not a valid flash address\n", h_addr);
+ return 0;
+ } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
+ printf("bmp addr is not a bmp\n");
+ return 0;
+ } else
+ return (char *)h_addr;
+}
+
int ads5121_diu_init(void)
{
unsigned int pixel_format;
+ char *bmp = NULL;
+ char *bmp_env;
xres = 1024;
yres = 768;
pixel_format = 0x88883316;
- return fsl_diu_init(xres, pixel_format, 0,
- (unsigned char *)FSL_Logo_BMP);
+ debug("ads5121_diu_init\n");
+ bmp_env = getenv("diu_bmp_addr");
+ if (bmp_env) {
+ bmp = valid_bmp(bmp_env);
+ }
+ if (!bmp)
+ bmp = FSL_Logo_BMP;
+ return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp);
}
int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
/* Flash 0 */
#if defined (CONFIG_SYS_AMD_BOOT)
- batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
#else
- batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
#endif
batl = CONFIG_SYS_FLASH0_BASE | 0x22;
write_bat (IBAT0, batu, batl);
/* Flash 1 */
#if defined (CONFIG_SYS_AMD_BOOT)
- batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
#else
- batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
#endif
batl = CONFIG_SYS_FLASH1_BASE | 0x22;
write_bat (IBAT1, batu, batl);
write_bat (DBAT1, batu, batl);
/* CPLD */
- batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_CPLD_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
batl = CONFIG_SYS_CPLD_BASE | 0x22;
write_bat (IBAT2, 0, 0);
write_bat (DBAT2, batu, batl);
/* FPGA */
- batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_FPGA_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
batl = CONFIG_SYS_FPGA_BASE | 0x22;
write_bat (IBAT3, 0, 0);
write_bat (DBAT3, batu, batl);
mtspr (DBAT5U, batu);
if (size <= 0x800000) /* 8MB */
- blocksize = BL_8M << 2;
+ blocksize = BATU_BL_8M;
else if (size <= 0x1000000) /* 16MB */
- blocksize = BL_16M << 2;
+ blocksize = BATU_BL_16M;
else if (size <= 0x2000000) /* 32MB */
- blocksize = BL_32M << 2;
+ blocksize = BATU_BL_32M;
else if (size <= 0x4000000) /* 64MB */
- blocksize = BL_64M << 2;
+ blocksize = BATU_BL_64M;
else if (size <= 0x8000000) /* 128MB */
- blocksize = BL_128M << 2;
+ blocksize = BATU_BL_128M;
else if (size <= 0x10000000) /* 256MB */
- blocksize = BL_256M << 2;
+ blocksize = BATU_BL_256M;
/* Memory */
batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
} else {
size -= 0x10000000;
if (size <= 0x800000) /* 8MB */
- blocksize = BL_8M << 2;
+ blocksize = BATU_BL_8M;
else if (size <= 0x1000000) /* 16MB */
- blocksize = BL_16M << 2;
+ blocksize = BATU_BL_16M;
else if (size <= 0x2000000) /* 32MB */
- blocksize = BL_32M << 2;
+ blocksize = BATU_BL_32M;
else if (size <= 0x4000000) /* 64MB */
- blocksize = BL_64M << 2;
+ blocksize = BATU_BL_64M;
else if (size <= 0x8000000) /* 128MB */
- blocksize = BL_128M << 2;
+ blocksize = BATU_BL_128M;
else if (size <= 0x10000000) /* 256MB */
- blocksize = BL_256M << 2;
+ blocksize = BATU_BL_256M;
batu = (CONFIG_SYS_SDRAM_BASE +
0x10000000) | blocksize | BPP_RW | BPP_RX;
int board_eth_init(bd_t *bis)
{
+ cpu_eth_init(bis);
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
+ cpu_eth_init(bis);
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
+ cpu_eth_init(bis);
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
+ cpu_eth_init(bis);
return pci_eth_init(bis);
}
pci_set_region (hose->regions + 0,
AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
AP1000_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI Memory space */
pci_set_region (hose->regions + 1,
/* System memory space */
pci_set_region (hose->regions + 0,
0x00000000, 0x40000000, 0x01000000,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI Memory - config space */
pci_set_region (hose->regions + 1,
* BF51x, BF533, BF561: SSEL2
*/
#ifndef CONFIG_SPI_FLASH_SSEL
-# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
- defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
- defined(__ADSPBF51x__)
-# define CONFIG_SPI_FLASH_SSEL 2
-# else
-# define CONFIG_SPI_FLASH_SSEL 1
-# endif
+# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL
#endif
#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL)
/* System memory space */
pci_set_region(hose->regions + 0,
0x00000000, 0x00000000, 0x01000000,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI Memory space */
pci_set_region(hose->regions + 1,
i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
}
#endif
-
* so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1)
*/
CONFIG_SYS_PCI_MEMORY_SIZE-1,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
+flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
* flash_init()
/*-----------------------------------------------------------------------
*/
-static flash_info_t *flash_get_info(ulong base)
+flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
/* System memory space */
pci_set_region(hose->regions + 0,
0x00000000, 0x00000000, 0x01000000,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI Memory space */
pci_set_region(hose->regions + 1,
#include <asm/processor.h>
#include <asm/pci_io.h>
#include <mpc824x.h>
+#include <asm/mmu.h>
int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
int (*write_dword)(flash_info_t*, ulong, uint64_t);
#include <i2c.h>
#include <netdev.h>
#include <asm/processor.h>
+#include <asm/mmu.h>
int checkboard(void)
{
static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
-static flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
-static flash_info_t *flash_get_info(ulong base)
+flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
#include <config.h>
#include <common.h>
+#include <net.h>
+#include <libfdt.h>
#include <tsec.h>
void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
if (tsec_info[i].flags & TSEC_SGMII)
tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
}
+
+void fsl_sgmii_riser_fdt_fixup(void *fdt)
+{
+ struct eth_device *dev;
+ int node;
+ int i = -1;
+ int etsec_num = 0;
+
+ node = fdt_path_offset(fdt, "/aliases");
+ if (node < 0)
+ return;
+
+ while ((dev = eth_get_dev_by_index(++i)) != NULL) {
+ struct tsec_private *priv;
+ int enet_node;
+ char enet[16];
+ const u32 *phyh;
+ int phynode;
+ const char *model;
+ const char *path;
+
+ printf("Updating PHY address for %s\n", dev->name);
+ if (!strstr(dev->name, "eTSEC"))
+ continue;
+
+ sprintf(enet, "ethernet%d", etsec_num++);
+ path = fdt_getprop(fdt, node, enet, NULL);
+ if (!path) {
+ debug("No alias for %s\n", enet);
+ continue;
+ }
+
+ enet_node = fdt_path_offset(fdt, path);
+ if (enet_node < 0)
+ continue;
+
+ model = fdt_getprop(fdt, enet_node, "model", NULL);
+
+ printf("%s's model is %s\n", enet, model);
+ /*
+ * We only want to do this to eTSECs. On some platforms
+ * there are more than one type of gianfar-style ethernet
+ * controller, and as we are creating an implicit connection
+ * between ethernet nodes and eTSEC devices, it is best to
+ * make the connection use as much explicit information
+ * as exists.
+ */
+ if (!strstr(model, "TSEC"))
+ continue;
+
+ phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
+ if (!phyh)
+ continue;
+
+ phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh));
+
+ priv = dev->priv;
+
+ printf("Device flags are %x\n", priv->flags);
+ if (priv->flags & TSEC_SGMII)
+ fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
+ }
+}
*/
void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num);
+void fsl_sgmii_riser_fdt_fixup(void *fdt);
CONFIG_SYS_PCI_SLV_MEM_LOCAL,
CONFIG_SYS_PCI_SLV_MEM_BUS,
CONFIG_SYS_PCI_SLV_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose[0].region_count = 4;
pci_set_region(hose->regions + 3,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+ gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
pci_set_region(hose->regions + 3,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+ gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
CONFIG_SYS_PCI_SLV_MEM_LOCAL,
CONFIG_SYS_PCI_SLV_MEM_BUS,
CONFIG_SYS_PCI_SLV_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose[0].region_count = 4;
int board_early_init_f(void)
{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
/* Enable flash write */
/* Clear all of the interrupt of BCSR */
bcsr[0xe] = 0xff;
+#ifdef CONFIG_MMC
+ /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
+ bcsr[0xc] |= 0x4c;
+
+ /* Set proper bits in SICR to allow SD signals through */
+ clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+
+ clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI),
+ (SICRH_GPIO2_E_SD | SICRH_SPI_SD));
+
+#endif
+
#ifdef CONFIG_FSL_SERDES
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
u32 spridr = in_be32(&immr->sysconf.spridr);
switch (PARTID_NO_E(spridr)) {
case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
case SPR_8378:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
- FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
+ FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
break;
case SPR_8379:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
default:
printf("serdes not configured: unknown CPU part number: "
- "%04x\n", spridr >> 16);
+ "%04x\n", spridr >> 16);
break;
}
#endif /* CONFIG_FSL_SERDES */
phys_size_t fixed_sdram(void);
+int board_early_init_f (void)
+{
+#ifdef CONFIG_MMC
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SD_DATA |
+ MPC85xx_PMUXCR_SDHC_CD |
+ MPC85xx_PMUXCR_SDHC_WP));
+
+#endif
+ return 0;
+}
+
int checkboard (void)
{
printf ("Board: MPC8536DS, System ID: 0x%02x, "
return 0;
}
+#ifdef CONFIG_FSL_SGMII_RISER
if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
fsl_sgmii_riser_init(tsec_info, num);
+#endif
tsec_eth_init(bis, tsec_info, num);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
#endif
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
}
#endif
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
#endif
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
}
#endif
int checkboard (void)
{
- printf ("Board: MPC8572DS, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
+ puts ("Board: MPC8572DS ");
+#ifdef CONFIG_PHYS_64BIT
+ puts ("(36-bit addrmap) ");
+#endif
+ printf ("Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
return 0;
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
PCI_BASE_ADDRESS_1, &temp32);
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
- debug(" uli1572 read to %x\n", temp32);
- in_be32((unsigned *)temp32);
+ void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+ temp32, 4, 0);
+ debug(" uli1572 read to %p\n", p);
+ in_be32(p);
}
} else {
printf (" PCIE3: disabled\n");
return 0;
}
+#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_init(tsec_info, num);
+#endif
tsec_eth_init(bis, tsec_info, num);
void ft_board_setup(void *blob, bd_t *bd)
{
- ulong base, size;
+ phys_addr_t base;
+ phys_size_t size;
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
}
#endif
{
return pci_eth_init(bis);
}
+
+void board_reset(void)
+{
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+
+ while (1)
+ ;
+}
}
debug("\n");
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE
+ in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
+ CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
} else {
struct pci_controller *hose = &pci2_hose;
struct pci_region *r = hose->regions;
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
cpu_eth_init(bis);
return pci_eth_init(bis);
}
+
+void board_reset(void)
+{
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+
+ while (1)
+ ;
+}
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
-
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
-
PCI_MEMORY_BUS,
PCI_MEMORY_PHYS,
PCI_MEMORY_MAXSIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(local_hose.regions + 1,
PCI_MEMORY_BUS,
PCI_MEMORY_PHYS,
PCI_MEMORY_MAXSIZE,
- PCI_REGION_MEMORY);
+ PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(cpci_hose.regions + 1,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* outbound memory */
pci_set_region(r++,
return val;
}
+
+void board_reset(void)
+{
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ ulong addr = CONFIG_SYS_RESET_ADDRESS;
+
+ /* flush and disable I/D cache */
+ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
+ __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
+ __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
+ __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 4");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 5");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * SRR0 has system reset vector, SRR1 has default MSR value
+ * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
+ */
+ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
+ __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
+ __asm__ __volatile__ ("mtspr 27, 4");
+ __asm__ __volatile__ ("rfi");
+#endif
+}
pci_set_region (hose->regions + 3,
0x00000000,
0x80000000,
- 0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+ 0x04000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
#
# tqm85xx board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 256k
#
+ifeq ($(CONFIG_TQM8548_BE),y)
+TEXT_BASE = 0xfff80000
+else
TEXT_BASE = 0xfffc0000
+endif
#endif
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
*/
static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
{
- uint i;
+ uint i, j;
uint or3 = CONFIG_SYS_OR3_PRELIM;
uint clock = get_lbc_clock ();
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
- for (i = 0; i < 64; i++) {
- upmb_write (i, *nand_upm_patt);
+ for (j = 0; j < 64; j++) {
+ upmb_write (j, *nand_upm_patt);
nand_upm_patt++;
}
+
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
typedef struct sdram_conf_s sdram_conf_t;
#ifdef CONFIG_TQM8548
+#ifdef CONFIG_TQM8548_AG
+sdram_conf_t ddr_cs_conf[] = {
+ {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
+ { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
+ { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
+ { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
+};
+#else /* !CONFIG_TQM8548_AG */
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
{(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
};
+#endif /* CONFIG_TQM8548_AG */
#else /* !CONFIG_TQM8548 */
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#ifdef CONFIG_TQM8548
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+#endif
#else /* !CONFIG_TQM8548 */
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
ddr->sdram_cfg = 0;
#ifdef CONFIG_TQM8548
+ /* Timing and refresh settings for DDR2-533 and below */
+
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
- ddr->timing_cfg_3 = 0x00010000;
+ ddr->timing_cfg_3 = 0x00020000;
/* TIMING CFG 1, 533MHz
* PRETOACT: 4 Clocks
* ACTTOPRE: 12 Clocks
* ACTTORW: 4 Clocks
* CASLAT: 4 Clocks
- * REFREC: 34 Clocks
+ * REFREC: EXT_REFREC:REFREC 53 Clocks
* WRREC: 4 Clocks
* ACTTOACT: 3 Clocks
* WRTORD: 2 Clocks
*/
- ddr->timing_cfg_1 = 0x4C47A432;
+ ddr->timing_cfg_1 = 0x4C47D432;
/* TIMING CFG 2, 533MHz
* ADD_LAT: 3 Clocks
* WR_LAT: 3 Clocks
* RD_TO_PRE: 2 Clocks
* WR_DATA_DELAY: 1/2 Clock
- * CKE_PLS: 1 Clock
- * FOUR_ACT: 13 Clocks
+ * CKE_PLS: 3 Clock
+ * FOUR_ACT: 14 Clocks
*/
- ddr->timing_cfg_2 = 0x3318484D;
+ ddr->timing_cfg_2 = 0x331848CE;
/* DDR SDRAM Mode, 533MHz
* MRS: Extended Mode Register
ddr->sdram_interval = (1040 << 16) | 0x100;
/*
- * workaround for erratum DD10 of MPC8458 family below rev. 2.0:
- * DDR IO receiver must be set to an acceptable bias point by modifying
- * a hidden register.
+ * Workaround for erratum DDR19 according to MPC8548 Device Errata
+ * document, Rev. 1: DDR IO receiver must be set to an acceptable
+ * bias point by modifying a hidden register.
*/
- if (SVR_REV (get_svr ()) < 0x20) {
+ if (SVR_REV (get_svr ()) < 0x21)
gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
- }
/* DDR SDRAM CFG 2
* FRC_SR: normal mode
/* wait for clock stabilization */
asm ("sync;isync;msync");
- udelay(1000);
+ udelay (1000);
+
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+ /*
+ * Workaround for erratum DDR20 according to MPC8548 Device Errata
+ * document, Rev. 1: "CKE signal may not function correctly after
+ * assertion of HRESET"
+ */
+
+ /* 1. Configure DDR register as is done in normal DDR configuration.
+ * Do not set DDR_SDRAM_CFG[MEM_EN].
+ *
+ * 2. Set reserved bit EEBACR[3] at offset 0x1000
+ */
+ ecm->eebacr |= 0x10000000;
+
+ /*
+ * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
+ *
+ * DDR_SDRAM_CFG_2:
+ * FRC_SR: normal mode
+ * SR_IE: no self-refresh interrupt
+ * DLL_RST_DIS: don't care, leave at reset value
+ * DQS_CFG: differential DQS signals
+ * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
+ * LVWx_CFG: don't care, leave at reset value
+ * NUM_PR: 1 refresh will be issued at a time
+ * DM_CFG: don't care, leave at reset value
+ * D_INIT: enable data initialization
+ */
+ ddr->sdram_cfg_2 |= 0x00000010;
+
+ /*
+ * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
+ * training
+ */
+ ddr->debug_3 |= 0x00000400;
+
+ /*
+ * 5. Wait 200 micro-seconds
+ */
+ udelay (200);
+
+ /*
+ * 6. Set DDR_SDRAM_CFG[MEM_EN]
+ *
+ * BTW, initialize DDR_SDRAM_CFG:
+ * MEM_EN: enabled
+ * SREN: don't care, leave at reset value
+ * ECC_EN: no error report
+ * RD_EN: no registered DIMMs
+ * SDRAM_TYPE: DDR2
+ * DYN_PWR: no power management
+ * 32_BE: don't care, leave at reset value
+ * 8_BE: 4 beat burst
+ * NCAP: don't care, leave at reset value
+ * 2T_EN: 1T Timing
+ * BA_INTLV_CTL: no interleaving
+ * x32_EN: x16 organization
+ * PCHB8: MA[10] for auto-precharge
+ * HSE: half strength for single and 2-layer stacks
+ * (full strength for 3- and 4-layer stacks not
+ * yet considered)
+ * MEM_HALT: no halt
+ * BI: automatic initialization
+ */
+ ddr->sdram_cfg = 0x83000008;
+
+ /*
+ * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
+ */
+ asm ("sync;isync;msync");
+ while (ddr->sdram_cfg_2 & 0x00000010)
+ asm ("eieio");
+
+ /*
+ * 8. Clear D3[21] to re-enable data training
+ */
+ ddr->debug_3 &= ~0x00000400;
+
+ /*
+ * 9. Set D2(21) to force data training to run
+ */
+ ddr->debug_2 |= 0x00000400;
+
+ /*
+ * 10. Poll on D2[21] until it is cleared by hardware
+ */
+ asm ("sync;isync;msync");
+ while (ddr->debug_2 & 0x00000400)
+ asm ("eieio");
+
+ /*
+ * 11. Clear reserved bit EEBACR[3] at offset 0x1000
+ */
+ ecm->eebacr &= ~0x10000000;
+
+#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
/* DDR SDRAM CLK CNTL
* MEM_EN: enabled
* BI: automatic initialization
*/
ddr->sdram_cfg = 0x83000008;
- asm ("sync; isync; msync");
- udelay(1000);
+#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
+
+ asm ("sync; isync; msync");
+ udelay (1000);
#else /* !CONFIG_TQM8548 */
switch (casl) {
case 20:
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
+#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
+ /*
+ * TLB 7+8: 2G DDR, cache enabled
+ * 0x00000000 2G DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ */
+ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_1G, 1),
+
+ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#else
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
-
+#endif
#ifdef CONFIG_PCIE1
/*
* TLB 9: 16M Non-cacheable, guarded
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_MONITOR_BASE, 0xffffffff,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI || CONFIG_PCI1 */
+#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
static inline void init_pci1(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#ifdef CONFIG_PCI1
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
} else {
puts ("PCI1: disabled\n");
}
-#else /* !(CONFIG_PCI || CONFIG_PCI1) */
+#else /* !CONFIG_PCI1 */
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
-#endif /* CONFIG_PCI || CONFIG_PCI1) */
+#endif /* CONFIG_PCI1 */
}
static inline void init_pcie1(void)
{
ft_cpu_setup (blob, bd);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
COBJS-y += devices.o
COBJS-y += dlmalloc.o
COBJS-y += exports.o
-COBJS-y += hush.o
+COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
COBJS-y += image.o
COBJS-y += memsize.o
COBJS-y += s_record.o
-COBJS-y += serial.o
+COBJS-$(CONFIG_SERIAL_MULTI) += serial.o
COBJS-y += xyzModem.o
# core command
COBJS-$(CONFIG_CMD_DOC) += docecc.o
COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
COBJS-y += flash.o
-COBJS-y += kgdb.o
+COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
COBJS-$(CONFIG_LCD) += lcd.o
COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
COBJS-$(CONFIG_UPDATE_TFTP) += update.o
#if defined(CONFIG_SYS_MBAR)
print_num ("mbar", bd->bi_mbar_base);
#endif
+ print_str ("cpufreq", strmhz(buf, bd->bi_intfreq));
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
#ifdef CONFIG_PCI
print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq));
puts ("\nip_addr = ");
print_IPaddr (bd->bi_ip_addr);
#endif
- printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
+ printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate);
return 0;
}
#include <mpc5xxx.h>
#endif
+#ifdef CONFIG_MPC512X
+#include <mpc512x.h>
+#endif
+
#include <ide.h>
#include <ata.h>
#include <common.h>
#include <command.h>
-#if defined(CONFIG_CMD_MMC)
-#include <mmc.h>
-#endif
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
#endif
}
#endif
-#if defined(CONFIG_CMD_MMC)
- if (mmc2info(dest)) {
- int rc;
-
- puts ("Copy to MMC... ");
- switch (rc = mmc_write ((uchar *)addr, dest, count*size)) {
- case 0:
- putc ('\n');
- return 1;
- case -1:
- puts ("failed\n");
- return 1;
- default:
- printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc);
- return 1;
- }
- puts ("done\n");
- return 0;
- }
-
- if (mmc2info(addr)) {
- int rc;
-
- puts ("Copy from MMC... ");
- switch (rc = mmc_read (addr, (uchar *)dest, count*size)) {
- case 0:
- putc ('\n');
- return 1;
- case -1:
- puts ("failed\n");
- return 1;
- default:
- printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc);
- return 1;
- }
- puts ("done\n");
- return 0;
- }
-#endif
-
#ifdef CONFIG_HAS_DATAFLASH
/* Check if we are copying from RAM or Flash to DataFlash */
if (addr_dataflash(dest) && !addr_dataflash(addr)){
#include <command.h>
#include <mmc.h>
+#ifndef CONFIG_GENERIC_MMC
int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- if (mmc_init (1) != 0) {
+ if (mmc_legacy_init (1) != 0) {
printf ("No MMC card found\n");
return 1;
}
"init mmc card",
NULL
);
+#endif /* !CONFIG_GENERIC_MMC */
+
+static void print_mmcinfo(struct mmc *mmc)
+{
+ printf("Device: %s\n", mmc->name);
+ printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24);
+ printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff);
+ printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff,
+ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
+ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
+
+ printf("Tran Speed: %d\n", mmc->tran_speed);
+ printf("Rd Block Len: %d\n", mmc->read_bl_len);
+
+ printf("%s version %d.%d\n", IS_SD(mmc) ? "SD" : "MMC",
+ (mmc->version >> 4) & 0xf, mmc->version & 0xf);
+
+ printf("High Capacity: %s\n", mmc->high_capacity ? "Yes" : "No");
+ printf("Capacity: %lld\n", mmc->capacity);
+
+ printf("Bus Width: %d-bit\n", mmc->bus_width);
+}
+
+int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ struct mmc *mmc;
+ int dev_num;
+
+ if (argc < 2)
+ dev_num = 0;
+ else
+ dev_num = simple_strtoul(argv[1], NULL, 0);
+
+ mmc = find_mmc_device(dev_num);
+
+ if (mmc) {
+ mmc_init(mmc);
+
+ print_mmcinfo(mmc);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(mmcinfo, 2, 0, do_mmcinfo, "mmcinfo <dev num>-- display MMC info\n",
+ NULL);
+
+int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int rc = 0;
+
+ switch (argc) {
+ case 3:
+ if (strcmp(argv[1], "rescan") == 0) {
+ int dev = simple_strtoul(argv[2], NULL, 10);
+ struct mmc *mmc = find_mmc_device(dev);
+
+ mmc_init(mmc);
+
+ return 0;
+ }
+
+ case 0:
+ case 1:
+ case 4:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+
+ case 2:
+ if (!strcmp(argv[1], "list")) {
+ print_mmc_devices('\n');
+ return 0;
+ }
+ return 1;
+ default: /* at least 5 args */
+ if (strcmp(argv[1], "read") == 0) {
+ int dev = simple_strtoul(argv[2], NULL, 10);
+ void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
+ u32 cnt = simple_strtoul(argv[5], NULL, 16);
+ u32 n;
+ u32 blk = simple_strtoul(argv[4], NULL, 16);
+ struct mmc *mmc = find_mmc_device(dev);
+
+ printf("\nMMC read: dev # %d, block # %d, count %d ... ",
+ dev, blk, cnt);
+
+ mmc_init(mmc);
+
+ n = mmc->block_dev.block_read(dev, blk, cnt, addr);
+
+ /* flush cache after read */
+ flush_cache((ulong)addr, cnt * 512); /* FIXME */
+
+ printf("%d blocks read: %s\n",
+ n, (n==cnt) ? "OK" : "ERROR");
+ return (n == cnt) ? 0 : 1;
+ } else if (strcmp(argv[1], "write") == 0) {
+ int dev = simple_strtoul(argv[2], NULL, 10);
+ void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
+ u32 cnt = simple_strtoul(argv[5], NULL, 16);
+ u32 n;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ int blk = simple_strtoul(argv[4], NULL, 16);
+
+ printf("\nMMC write: dev # %d, block # %d, count %d ... ",
+ dev, blk, cnt);
+
+ mmc_init(mmc);
+
+ n = mmc->block_dev.block_write(dev, blk, cnt, addr);
+
+ printf("%d blocks written: %s\n",
+ n, (n == cnt) ? "OK" : "ERROR");
+ return (n == cnt) ? 0 : 1;
+ } else {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rc = 1;
+ }
+
+ return rc;
+ }
+}
+
+U_BOOT_CMD(
+ mmc, 6, 1, do_mmcops,
+ "mmc - MMC sub system\n",
+ "mmc read <device num> addr blk# cnt\n"
+ "mmc write <device num> addr blk# cnt\n"
+ "mmc rescan <device num>\n"
+ "mmc list - lists available devices\n");
return (-1);
}
-#if defined(CONFIG_CMD_ENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
* environment are used
*/
#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-extern int overwrite_console (void);
-#define OVERWRITE_CONSOLE overwrite_console ()
+extern int overwrite_console(void);
+#define OVERWRITE_CONSOLE overwrite_console()
#else
#define OVERWRITE_CONSOLE 0
#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
-static int console_setfile (int file, device_t * dev)
+static int console_setfile(int file, device_t * dev)
{
int error = 0;
case stderr:
/* Start new device */
if (dev->start) {
- error = dev->start ();
+ error = dev->start();
/* If it's not started dont use it */
if (error < 0)
break;
* only from fgetc() which assures it.
* No attempt is made to demultiplex multiple input sources.
*/
-static int iomux_getc(void)
+static int console_getc(int file)
{
unsigned char ret;
return ret;
}
-static int iomux_tstc(int file)
+static int console_tstc(int file)
{
int i, ret;
device_t *dev;
return 0;
}
-static void iomux_putc(int file, const char c)
+static void console_putc(int file, const char c)
{
int i;
device_t *dev;
}
}
-static void iomux_puts(int file, const char *s)
+static void console_puts(int file, const char *s)
{
int i;
device_t *dev;
dev->puts(s);
}
}
+
+static inline void console_printdevs(int file)
+{
+ iomux_printdevs(file);
+}
+
+static inline void console_doenv(int file, device_t *dev)
+{
+ iomux_doenv(file, dev->name);
+}
+#else
+static inline int console_getc(int file)
+{
+ return stdio_devices[file]->getc();
+}
+
+static inline int console_tstc(int file)
+{
+ return stdio_devices[file]->tstc();
+}
+
+static inline void console_putc(int file, const char c)
+{
+ stdio_devices[file]->putc(c);
+}
+
+static inline void console_puts(int file, const char *s)
+{
+ stdio_devices[file]->puts(s);
+}
+
+static inline void console_printdevs(int file)
+{
+ printf("%s\n", stdio_devices[file]->name);
+}
+
+static inline void console_doenv(int file, device_t *dev)
+{
+ console_setfile(file, dev);
+}
#endif /* defined(CONFIG_CONSOLE_MUX) */
/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/
-void serial_printf (const char *fmt, ...)
+void serial_printf(const char *fmt, ...)
{
va_list args;
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
- va_start (args, fmt);
+ va_start(args, fmt);
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
- i = vsprintf (printbuffer, fmt, args);
- va_end (args);
+ i = vsprintf(printbuffer, fmt, args);
+ va_end(args);
- serial_puts (printbuffer);
+ serial_puts(printbuffer);
}
-int fgetc (int file)
+int fgetc(int file)
{
if (file < MAX_FILES) {
#if defined(CONFIG_CONSOLE_MUX)
* check for that first.
*/
if (tstcdev != NULL)
- return iomux_getc();
- iomux_tstc(file);
+ return console_getc(file);
+ console_tstc(file);
#ifdef CONFIG_WATCHDOG
/*
* If the watchdog must be rate-limited then it should
#endif
}
#else
- return stdio_devices[file]->getc ();
+ return console_getc(file);
#endif
}
return -1;
}
-int ftstc (int file)
+int ftstc(int file)
{
if (file < MAX_FILES)
-#if defined(CONFIG_CONSOLE_MUX)
- return iomux_tstc(file);
-#else
- return stdio_devices[file]->tstc ();
-#endif
+ return console_tstc(file);
return -1;
}
-void fputc (int file, const char c)
+void fputc(int file, const char c)
{
if (file < MAX_FILES)
-#if defined(CONFIG_CONSOLE_MUX)
- iomux_putc(file, c);
-#else
- stdio_devices[file]->putc (c);
-#endif
+ console_putc(file, c);
}
-void fputs (int file, const char *s)
+void fputs(int file, const char *s)
{
if (file < MAX_FILES)
-#if defined(CONFIG_CONSOLE_MUX)
- iomux_puts(file, s);
-#else
- stdio_devices[file]->puts (s);
-#endif
+ console_puts(file, s);
}
-void fprintf (int file, const char *fmt, ...)
+void fprintf(int file, const char *fmt, ...)
{
va_list args;
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
- va_start (args, fmt);
+ va_start(args, fmt);
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
- i = vsprintf (printbuffer, fmt, args);
- va_end (args);
+ i = vsprintf(printbuffer, fmt, args);
+ va_end(args);
/* Send to desired file */
- fputs (file, printbuffer);
+ fputs(file, printbuffer);
}
/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/
-int getc (void)
+int getc(void)
{
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
if (gd->flags & GD_FLG_DEVINIT) {
/* Get from the standard input */
- return fgetc (stdin);
+ return fgetc(stdin);
}
/* Send directly to the handler */
- return serial_getc ();
+ return serial_getc();
}
-int tstc (void)
+int tstc(void)
{
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
if (gd->flags & GD_FLG_DEVINIT) {
/* Test the standard input */
- return ftstc (stdin);
+ return ftstc(stdin);
}
/* Send directly to the handler */
- return serial_tstc ();
+ return serial_tstc();
}
-void putc (const char c)
+void putc(const char c)
{
#ifdef CONFIG_SILENT_CONSOLE
if (gd->flags & GD_FLG_SILENT)
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
- fputc (stdout, c);
+ fputc(stdout, c);
} else {
/* Send directly to the handler */
- serial_putc (c);
+ serial_putc(c);
}
}
-void puts (const char *s)
+void puts(const char *s)
{
#ifdef CONFIG_SILENT_CONSOLE
if (gd->flags & GD_FLG_SILENT)
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
- fputs (stdout, s);
+ fputs(stdout, s);
} else {
/* Send directly to the handler */
- serial_puts (s);
+ serial_puts(s);
}
}
-void printf (const char *fmt, ...)
+void printf(const char *fmt, ...)
{
va_list args;
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
- va_start (args, fmt);
+ va_start(args, fmt);
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
- i = vsprintf (printbuffer, fmt, args);
- va_end (args);
+ i = vsprintf(printbuffer, fmt, args);
+ va_end(args);
/* Print the string */
- puts (printbuffer);
+ puts(printbuffer);
}
-void vprintf (const char *fmt, va_list args)
+void vprintf(const char *fmt, va_list args)
{
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
- i = vsprintf (printbuffer, fmt, args);
+ i = vsprintf(printbuffer, fmt, args);
/* Print the string */
- puts (printbuffer);
+ puts(printbuffer);
}
/* test if ctrl-c was pressed */
static int ctrlc_disabled = 0; /* see disable_ctrl() */
static int ctrlc_was_pressed = 0;
-int ctrlc (void)
+int ctrlc(void)
{
if (!ctrlc_disabled && gd->have_console) {
- if (tstc ()) {
- switch (getc ()) {
+ if (tstc()) {
+ switch (getc()) {
case 0x03: /* ^C - Control C */
ctrlc_was_pressed = 1;
return 1;
/* pass 1 to disable ctrlc() checking, 0 to enable.
* returns previous state
*/
-int disable_ctrlc (int disable)
+int disable_ctrlc(int disable)
{
int prev = ctrlc_disabled; /* save previous state */
return ctrlc_was_pressed;
}
-void clear_ctrlc (void)
+void clear_ctrlc(void)
{
ctrlc_was_pressed = 0;
}
i = vsprintf(printbuffer, fmt, args);
va_end(args);
- if ((screen + sizeof(screen) - 1 - cursor) < strlen(printbuffer)+1) {
+ if ((screen + sizeof(screen) - 1 - cursor)
+ < strlen(printbuffer) + 1) {
memset(screen, 0, sizeof(screen));
cursor = screen;
}
/** U-Boot INIT FUNCTIONS *************************************************/
-device_t *search_device (int flags, char *name)
+device_t *search_device(int flags, char *name)
{
device_t *dev;
dev = device_get_by_name(name);
- if(dev && (dev->flags & flags))
+ if (dev && (dev->flags & flags))
return dev;
return NULL;
}
-int console_assign (int file, char *devname)
+int console_assign(int file, char *devname)
{
int flag;
device_t *dev;
dev = search_device(flag, devname);
- if(dev)
- return console_setfile (file, dev);
+ if (dev)
+ return console_setfile(file, dev);
return -1;
}
/* Called before relocation - use serial functions */
-int console_init_f (void)
+int console_init_f(void)
{
gd->have_console = 1;
gd->flags |= GD_FLG_SILENT;
#endif
- return (0);
+ return 0;
}
#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Called after the relocation - use desired console functions */
-int console_init_r (void)
+int console_init_r(void)
{
char *stdinname, *stdoutname, *stderrname;
device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL;
/* stdin stdout and stderr are in environment */
/* scan for it */
- stdinname = getenv ("stdin");
- stdoutname = getenv ("stdout");
- stderrname = getenv ("stderr");
+ stdinname = getenv("stdin");
+ stdoutname = getenv("stdout");
+ stderrname = getenv("stderr");
if (OVERWRITE_CONSOLE == 0) { /* if not overwritten by config switch */
- inputdev = search_device (DEV_FLAGS_INPUT, stdinname);
- outputdev = search_device (DEV_FLAGS_OUTPUT, stdoutname);
- errdev = search_device (DEV_FLAGS_OUTPUT, stderrname);
+ inputdev = search_device(DEV_FLAGS_INPUT, stdinname);
+ outputdev = search_device(DEV_FLAGS_OUTPUT, stdoutname);
+ errdev = search_device(DEV_FLAGS_OUTPUT, stderrname);
#ifdef CONFIG_CONSOLE_MUX
iomux_err = iomux_doenv(stdin, stdinname);
iomux_err += iomux_doenv(stdout, stdoutname);
}
/* if the devices are overwritten or not found, use default device */
if (inputdev == NULL) {
- inputdev = search_device (DEV_FLAGS_INPUT, "serial");
+ inputdev = search_device(DEV_FLAGS_INPUT, "serial");
}
if (outputdev == NULL) {
- outputdev = search_device (DEV_FLAGS_OUTPUT, "serial");
+ outputdev = search_device(DEV_FLAGS_OUTPUT, "serial");
}
if (errdev == NULL) {
- errdev = search_device (DEV_FLAGS_OUTPUT, "serial");
+ errdev = search_device(DEV_FLAGS_OUTPUT, "serial");
}
/* Initializes output console first */
if (outputdev != NULL) {
-#ifdef CONFIG_CONSOLE_MUX
/* need to set a console if not done above. */
- iomux_doenv(stdout, outputdev->name);
-#else
- console_setfile (stdout, outputdev);
-#endif
+ console_doenv(stdout, outputdev);
}
if (errdev != NULL) {
-#ifdef CONFIG_CONSOLE_MUX
/* need to set a console if not done above. */
- iomux_doenv(stderr, errdev->name);
-#else
- console_setfile (stderr, errdev);
-#endif
+ console_doenv(stderr, errdev);
}
if (inputdev != NULL) {
-#ifdef CONFIG_CONSOLE_MUX
/* need to set a console if not done above. */
- iomux_doenv(stdin, inputdev->name);
-#else
- console_setfile (stdin, inputdev);
-#endif
+ console_doenv(stdin, inputdev);
}
#ifdef CONFIG_CONSOLE_MUX
#ifndef CONFIG_SYS_CONSOLE_INFO_QUIET
/* Print information */
- puts ("In: ");
+ puts("In: ");
if (stdio_devices[stdin] == NULL) {
- puts ("No input devices available!\n");
+ puts("No input devices available!\n");
} else {
-#ifdef CONFIG_CONSOLE_MUX
- iomux_printdevs(stdin);
-#else
- printf ("%s\n", stdio_devices[stdin]->name);
-#endif
+ console_printdevs(stdin);
}
- puts ("Out: ");
+ puts("Out: ");
if (stdio_devices[stdout] == NULL) {
- puts ("No output devices available!\n");
+ puts("No output devices available!\n");
} else {
-#ifdef CONFIG_CONSOLE_MUX
- iomux_printdevs(stdout);
-#else
- printf ("%s\n", stdio_devices[stdout]->name);
-#endif
+ console_printdevs(stdout);
}
- puts ("Err: ");
+ puts("Err: ");
if (stdio_devices[stderr] == NULL) {
- puts ("No error devices available!\n");
+ puts("No error devices available!\n");
} else {
-#ifdef CONFIG_CONSOLE_MUX
- iomux_printdevs(stderr);
-#else
- printf ("%s\n", stdio_devices[stderr]->name);
-#endif
+ console_printdevs(stderr);
}
#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
#ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/* set the environment variables (will overwrite previous env settings) */
for (i = 0; i < 3; i++) {
- setenv (stdio_names[i], stdio_devices[i]->name);
+ setenv(stdio_names[i], stdio_devices[i]->name);
}
#endif /* CONFIG_SYS_CONSOLE_ENV_OVERWRITE */
#if 0
/* If nothing usable installed, use only the initial console */
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
- return (0);
+ return 0;
#endif
- return (0);
+ return 0;
}
#else /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
/* Called after the relocation - use desired console functions */
-int console_init_r (void)
+int console_init_r(void)
{
device_t *inputdev = NULL, *outputdev = NULL;
int i;
device_t *dev;
#ifdef CONFIG_SPLASH_SCREEN
- /* suppress all output if splash screen is enabled and we have
- a bmp to display */
+ /*
+ * suppress all output if splash screen is enabled and we have
+ * a bmp to display
+ */
if (getenv("splashimage") != NULL)
gd->flags |= GD_FLG_SILENT;
#endif
/* Initializes output console first */
if (outputdev != NULL) {
- console_setfile (stdout, outputdev);
- console_setfile (stderr, outputdev);
+ console_setfile(stdout, outputdev);
+ console_setfile(stderr, outputdev);
#ifdef CONFIG_CONSOLE_MUX
console_devices[stdout][0] = outputdev;
console_devices[stderr][0] = outputdev;
/* Initializes input console */
if (inputdev != NULL) {
- console_setfile (stdin, inputdev);
+ console_setfile(stdin, inputdev);
#ifdef CONFIG_CONSOLE_MUX
console_devices[stdin][0] = inputdev;
#endif
#ifndef CONFIG_SYS_CONSOLE_INFO_QUIET
/* Print information */
- puts ("In: ");
+ puts("In: ");
if (stdio_devices[stdin] == NULL) {
- puts ("No input devices available!\n");
+ puts("No input devices available!\n");
} else {
- printf ("%s\n", stdio_devices[stdin]->name);
+ printf("%s\n", stdio_devices[stdin]->name);
}
- puts ("Out: ");
+ puts("Out: ");
if (stdio_devices[stdout] == NULL) {
- puts ("No output devices available!\n");
+ puts("No output devices available!\n");
} else {
- printf ("%s\n", stdio_devices[stdout]->name);
+ printf("%s\n", stdio_devices[stdout]->name);
}
- puts ("Err: ");
+ puts("Err: ");
if (stdio_devices[stderr] == NULL) {
- puts ("No error devices available!\n");
+ puts("No error devices available!\n");
} else {
- printf ("%s\n", stdio_devices[stderr]->name);
+ printf("%s\n", stdio_devices[stderr]->name);
}
#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
/* Setting environment variables */
for (i = 0; i < 3; i++) {
- setenv (stdio_names[i], stdio_devices[i]->name);
+ setenv(stdio_names[i], stdio_devices[i]->name);
}
#if 0
/* If nothing usable installed, use only the initial console */
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
- return (0);
+ return 0;
#endif
- return (0);
+ return 0;
}
#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)
+#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_FLASH)
#define CMD_SAVEENV
#elif defined(CONFIG_ENV_ADDR_REDUND)
-#error Cannot use CONFIG_ENV_ADDR_REDUND without CONFIG_CMD_ENV & CONFIG_CMD_FLASH
+#error Cannot use CONFIG_ENV_ADDR_REDUND without CONFIG_CMD_SAVEENV & CONFIG_CMD_FLASH
#endif
#if defined(CONFIG_ENV_SIZE_REDUND) && (CONFIG_ENV_SIZE_REDUND < CONFIG_ENV_SIZE)
#include <malloc.h>
#include <nand.h>
-#if defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)
+#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND)
#define CMD_SAVEENV
#elif defined(CONFIG_ENV_OFFSET_REDUND)
-#error Cannot use CONFIG_ENV_OFFSET_REDUND without CONFIG_CMD_ENV & CONFIG_CMD_NAND
+#error Cannot use CONFIG_ENV_OFFSET_REDUND without CONFIG_CMD_SAVEENV & CONFIG_CMD_NAND
#endif
#if defined(CONFIG_ENV_SIZE_REDUND) && (CONFIG_ENV_SIZE_REDUND != CONFIG_ENV_SIZE)
crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
- if(!crc1_ok && !crc2_ok)
+ if(!crc1_ok && !crc2_ok) {
+ free(tmp_env1);
+ free(tmp_env2);
return use_default();
- else if(crc1_ok && !crc2_ok)
+ } else if(crc1_ok && !crc2_ok)
gd->env_valid = 1;
else if(!crc1_ok && crc2_ok)
gd->env_valid = 2;
for (r = 0; r < hose->region_count; r++) {
u64 bus_start, phys_start, size;
- /* skip if !PCI_REGION_MEMORY */
- if (!(hose->regions[r].flags & PCI_REGION_MEMORY))
+ /* skip if !PCI_REGION_SYS_MEMORY */
+ if (!(hose->regions[r].flags & PCI_REGION_SYS_MEMORY))
continue;
bus_start = (u64)hose->regions[r].bus_start;
/*cmd_boot.c*/
extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* do_bootd */
#endif
-#ifdef CONFIG_SYS_HUSH_PARSER
#ifndef __U_BOOT__
#include <ctype.h> /* isalpha, isdigit */
#include <unistd.h> /* getpid */
);
#endif
-#endif /* CONFIG_SYS_HUSH_PARSER */
/****************************************************************************/
#include <kgdb.h>
#include <command.h>
-#if defined(CONFIG_CMD_KGDB)
-
#undef KGDB_DEBUG
/*
" program if it is executed (see the \"hello_world\"\n"
" example program in the U-Boot examples directory)."
);
-#else
-
-int kgdb_not_configured = 1;
-
-#endif
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SERIAL_MULTI)
-
static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
serial_current->puts (s);
}
-
-#endif /* CONFIG_SERIAL_MULTI */
do {
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_INQUIRY;
- srb->cmd[1] = srb->lun<<5;
srb->cmd[4] = 36;
srb->datalen = 36;
srb->cmdlen = 12;
ptr = (char *)srb->pdata;
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_REQ_SENSE;
- srb->cmd[1] = srb->lun << 5;
srb->cmd[4] = 18;
srb->datalen = 18;
srb->pdata = &srb->sense_buf[0];
do {
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_TST_U_RDY;
- srb->cmd[1] = srb->lun << 5;
srb->datalen = 0;
srb->cmdlen = 12;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
do {
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_RD_CAPAC;
- srb->cmd[1] = srb->lun << 5;
srb->datalen = 8;
srb->cmdlen = 12;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
{
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_READ10;
- srb->cmd[1] = srb->lun << 5;
srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
return 0;
}
-int mmc_init(int verbose)
+int mmc_legacy_init(int verbose)
{
int ret = -ENODEV;
if (verbose)
- printf("mmc_init\n");
+ printf("mmc_legacy_init\n");
spi_init();
/* this meeds to be done twice */
return ret;
}
-int mmc_write(uchar * src, ulong dst, int size)
-{
-#ifdef MMC_DEBUG
- printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size);
-#endif
- /* Since mmc2info always returns 0 this function will never be called */
- return 0;
-}
-
-int mmc_read(ulong src, uchar * dst, int size)
-{
-#ifdef MMC_DEBUG
- printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size);
-#endif
- /* Since mmc2info always returns 0 this function will never be called */
- return 0;
-}
-
-int mmc2info(ulong addr)
-{
- /* This function is used by cmd_cp to determine if source or destination
- address resides on MMC-card or not. We do not support copy to and from
- MMC-card so we always return 0. */
- return 0;
-}
-
#endif /* CONFIG_MMC */
{
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
}
-
#include "serial.h"
__attribute__((always_inline))
-static inline uint32_t serial_init(void)
+static inline void serial_init(void)
{
#ifdef __ADSPBF54x__
# ifdef BFIN_BOOT_UART_USE_RTS
}
#endif
- uint32_t old_baud;
- if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
- old_baud = serial_early_get_baud();
- else
- old_baud = CONFIG_BAUDRATE;
-
if (BFIN_DEBUG_EARLY_SERIAL) {
+ int ucen = *pUART_GCTL & UCEN;
serial_early_init();
/* If the UART is off, that means we need to program
* the baud rate ourselves initially.
*/
- if (!old_baud) {
- old_baud = CONFIG_BAUDRATE;
+ if (ucen != UCEN)
serial_early_set_baud(CONFIG_BAUDRATE);
- }
}
-
- return old_baud;
}
__attribute__((always_inline))
#endif
}
-/* We need to reset the baud rate when we have early debug turned on
- * or when we are booting over the UART.
- * XXX: we should fix this to calc the old baud and restore it rather
- * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
- * to figure out how to avoid the division in the baud calc ...
- */
-__attribute__((always_inline))
-static inline void serial_reset_baud(uint32_t baud)
-{
- if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
- return;
-
-#ifndef CONFIG_LDR_LOAD_BAUD
-# define CONFIG_LDR_LOAD_BAUD 115200
-#endif
-
- if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
- serial_early_set_baud(baud);
- else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
- serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
- else
- serial_early_set_baud(CONFIG_BAUDRATE);
-}
-
__attribute__((always_inline))
static inline void serial_putc(char c)
{
}
-/* Max SCLK can be 133MHz ... dividing that by 4 gives
- * us a freq of 33MHz for SPI which should generally be
+/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
+ * us a freq of 16MHz for SPI which should generally be
* slow enough for the slow reads the bootrom uses.
*/
+#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
+ ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
+ (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
+# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
+#else
+# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
+#endif
#ifndef CONFIG_SPI_BAUD_INITBLOCK
-# define CONFIG_SPI_BAUD_INITBLOCK 4
+# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
+#endif
+#ifdef SPI0_BAUD
+# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
#endif
/* PLL_DIV defines */
#ifndef CONFIG_EBIU_RSTCTL_VAL
# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
#endif
+#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
+# error invalid EBIU_RSTCTL value: must not set reserved bits
+#endif
#ifndef CONFIG_EBIU_MBSCTL_VAL
# define CONFIG_EBIU_MBSCTL_VAL 0
#endif
+#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
+# error invalid EBIU_DDRQUE value: must not set reserved bits
+#endif
+
/* Make sure our voltage value is sane so we don't blow up! */
#ifndef CONFIG_VR_CTL_VAL
# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
# elif defined(__ADSPBF54x__) /* TBD; use default */
# undef CONFIG_VR_CTL_VLEV
# define CONFIG_VR_CTL_VLEV VLEV_120
+# elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
+# undef CONFIG_VR_CTL_VLEV
+# define CONFIG_VR_CTL_VLEV VLEV_125
# endif
# ifdef CONFIG_BFIN_MAC
# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
#endif
-__attribute__((saveall))
+BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bootstruct)
{
- uint32_t old_baud = serial_init();
+ /* Save the clock pieces that are used in baud rate calculation */
+ unsigned int sdivB, divB, vcoB;
+ serial_init();
+ if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+ sdivB = bfin_read_PLL_DIV() & 0xf;
+ vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+ divB = serial_early_get_div();
+ }
#ifdef CONFIG_HW_WATCHDOG
# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
* boot. Once we switch over to u-boot's SPI flash driver, we'll
* increase the speed appropriately.
*/
- if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#ifdef SPI0_BAUD
- bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
-#else
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
+ if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
+ bootstruct->dFlags |= BFLAG_FASTREAD;
bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
-#endif
+ }
serial_putc('B');
bfin_write_SIC_IWR(1);
#endif
- serial_putc('L');
+ /* With newer bootroms, we use the helper function to set up
+ * the memory controller. Older bootroms lacks such helpers
+ * so we do it ourselves.
+ */
+ if (BOOTROM_CAPS_SYSCONTROL) {
+ serial_putc('S');
+
+ ADI_SYSCTRL_VALUES memory_settings;
+ memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+ memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
+ memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
+ memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
+ syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
+ (CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
+ } else {
+ serial_putc('L');
- bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
+ bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
- serial_putc('A');
+ serial_putc('A');
- /* Only reprogram when needed to avoid triggering unnecessary
- * PLL relock sequences.
- */
- if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
- serial_putc('!');
- bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
- asm("idle;");
- }
+ /* Only reprogram when needed to avoid triggering unnecessary
+ * PLL relock sequences.
+ */
+ if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
+ serial_putc('!');
+ bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
+ asm("idle;");
+ }
- serial_putc('C');
+ serial_putc('C');
- bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
+ bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
- serial_putc('K');
+ serial_putc('K');
- /* Only reprogram when needed to avoid triggering unnecessary
- * PLL relock sequences.
- */
- if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
- serial_putc('!');
- bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
- asm("idle;");
+ /* Only reprogram when needed to avoid triggering unnecessary
+ * PLL relock sequences.
+ */
+ if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+ serial_putc('!');
+ bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
+ asm("idle;");
+ }
}
/* Since we've changed the SCLK above, we may need to update
* the UART divisors (UART baud rates are based on SCLK).
+ * Do the division by hand as there are no native instructions
+ * for dividing which means we'd generate a libgcc reference.
*/
- serial_reset_baud(old_baud);
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+ unsigned int sdivR, vcoR;
+ sdivR = bfin_read_PLL_DIV() & 0xf;
+ vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+ int dividend = sdivB * divB * vcoR;
+ int divisor = vcoB * sdivR;
+ unsigned int quotient;
+ for (quotient = 0; dividend > 0; ++quotient)
+ dividend -= divisor;
+ serial_early_put_div(quotient - ANOMALY_05000230);
+ }
serial_putc('F');
}
__attribute__((always_inline))
-static inline uint32_t serial_early_get_baud(void)
+static inline void serial_early_put_div(uint16_t divisor)
{
- /* If the UART isnt enabled, then we are booting an LDR
- * from a non-UART source (so like flash) which means
- * the baud rate here is meaningless.
- */
- if ((*pUART_GCTL & UCEN) != UCEN)
- return 0;
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
-#if (0) /* See comment for serial_reset_baud() in initcode.c */
+ /* Program the divisor to get the baud rate we want */
+ *pUART_DLL = LOB(divisor);
+ *pUART_DLH = HIB(divisor);
+ SSYNC();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint16_t serial_early_get_div(void)
+{
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH();
SSYNC();
uint8_t dll = *pUART_DLL;
uint8_t dlh = *pUART_DLH;
uint16_t divisor = (dlh << 8) | dll;
- uint32_t baud = get_sclk() / (divisor * 16);
/* Clear DLAB in LCR to Access THR RBR IER */
ACCESS_PORT_IER();
SSYNC();
- return baud;
-#else
- return CONFIG_BAUDRATE;
-#endif
+ return divisor;
}
__attribute__((always_inline))
* weird multiplication is to make sure we over sample just
* a little rather than under sample the incoming signals.
*/
- uint16_t divisor = (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230;
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- /* Program the divisor to get the baud rate we want */
- *pUART_DLL = LOB(divisor);
- *pUART_DLH = HIB(divisor);
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
+ serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
}
#ifndef BFIN_IN_INITCODE
#endif
.endm
-/* Recursively expand calls to _serial_putc for every byte
- * passed to us. Append a newline when we're all done.
- */
-.macro _serial_early_putc byte:req morebytes:vararg
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
- R0 = \byte;
- call _serial_putc;
-.ifnb \morebytes
- _serial_early_putc \morebytes
-.else
-.if (\byte != '\n')
- _serial_early_putc '\n'
-.endif
-.endif
-#endif
-.endm
-
-/* Wrapper around recurisve _serial_early_putc macro which
- * simply prepends the string "Early: "
- */
-.macro serial_early_putc byte:req morebytes:vararg
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
- _serial_early_putc 'E', 'a', 'r', 'l', 'y', ':', ' ', \byte, \morebytes
-#endif
-.endm
-
/* Since we embed the string right into our .text section, we need
* to find its address. We do this by getting our PC and adding 2
* bytes (which is the length of the jump instruction). Then we
SC520_PCI_MEMORY_BUS,
SC520_PCI_MEMORY_PHYS,
SC520_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
/* FlexBus Chipselect */
init_fbcs();
+#ifdef CONFIG_SYS_MCF_SYNCR
+ /* Set clockspeed according to board header file */
+ mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
+#else
/* Set clockspeed to 100MHz */
- mbar_writeShort(MCF_FMPLL_SYNCR,
+ mbar_writeLong(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
+#endif
while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}
{
if (setclear) {
/* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C,
+ (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
} else {
}
#endif
gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+ defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
START = start.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
+ifdef CONFIG_IIM
+COBJS += iim.o
+endif
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
--- /dev/null
+/*
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * ADS5121 IIM (Fusebox) Interface
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CMD_FUSE
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char cur_bank = '1';
+
+char *iim_err_msg(u32 err)
+{
+ static char *IIM_errs[] = {
+ "Parity Error in cache",
+ "Explicit Sense Cycle Error",
+ "Write to Locked Register Error",
+ "Read Protect Error",
+ "Override Protect Error",
+ "Write Protect Error"};
+
+ int i;
+
+ if (!err)
+ return "";
+ for (i = 1; i < 8; i++)
+ if (err & (1 << i))
+ printf("IIM - %s\n", IIM_errs[i-1]);
+ return "";
+}
+
+int in_range(int n, int min, int max, char *err, char *usg)
+{
+ if (n > max || n < min) {
+ printf(err);
+ printf("Usage:\n%s\n", usg);
+ return 0;
+ }
+ return 1;
+}
+
+int ads5121_fuse_read(int bank, int fstart, int num)
+{
+ iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+ u32 *iim_fb, dummy;
+ int f, ctr;
+
+ out_be32(&iim->err, in_be32(&iim->err));
+ if (bank == 0)
+ iim_fb = (u32 *)&(iim->fbac0);
+ else
+ iim_fb = (u32 *)&(iim->fbac1);
+/* try a read to see if Read Protect is set */
+ dummy = in_be32(&iim_fb[0]);
+ if (in_be32(&iim->err) & IIM_ERR_RPE) {
+ printf("\tRead protect fuse is set\n");
+ out_be32(&iim->err, IIM_ERR_RPE);
+ return 0;
+ }
+ printf("Reading Bank %d cache\n", bank);
+ for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) {
+ if (ctr % 4 == 0)
+ printf("F%2d:", f);
+ printf("\t%#04x", (u8)(iim_fb[f]));
+ if (ctr % 4 == 3)
+ printf("\n");
+ }
+ if (ctr % 4 != 0)
+ printf("\n");
+}
+
+int ads5121_fuse_override(int bank, int f, u8 val)
+{
+ iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+ u32 *iim_fb;
+ u32 iim_stat;
+ int i;
+
+ out_be32(&iim->err, in_be32(&iim->err));
+ if (bank == 0)
+ iim_fb = (u32 *)&(iim->fbac0);
+ else
+ iim_fb = (u32 *)&(iim->fbac1);
+/* try a read to see if Read Protect is set */
+ iim_stat = in_be32(&iim_fb[0]);
+ if (in_be32(&iim->err) & IIM_ERR_RPE) {
+ printf("Read protect fuse is set on bank %d;"
+ "Override protect may also be set\n", bank);
+ printf("An attempt will be made to override\n");
+ out_be32(&iim->err, IIM_ERR_RPE);
+ }
+ if (iim_stat & IIM_FBAC_FBOP) {
+ printf("Override protect fuse is set on bank %d\n", bank);
+ return 1;
+ }
+ if (f > IIM_FMAX) /* reset the entire bank */
+ for (i = 0; i < IIM_FMAX + 1; i++)
+ out_be32(&iim_fb[i], 0);
+ else
+ out_be32(&iim_fb[f], val);
+ return 0;
+}
+
+int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno)
+{
+ iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+ int f, i, bitno;
+ u32 stat, err;
+
+ f = simple_strtol(fuseno_bitno, NULL, 10);
+ if (f == 0 && fuseno_bitno[0] != '0')
+ f = -1;
+ if (!in_range(f, 0, IIM_FMAX,
+ "<frow> must be between 0-31\n\n", cmdtp->usage))
+ return 1;
+ bitno = -1;
+ for (i = 0; i < 6; i++) {
+ if (fuseno_bitno[i] == '_') {
+ bitno = simple_strtol(&(fuseno_bitno[i+1]), NULL, 10);
+ if (bitno == 0 && fuseno_bitno[i+1] != '0')
+ bitno = -1;
+ break;
+ }
+ }
+ if (!in_range(bitno, 0, 7, "Bit number ranges from 0-7\n"
+ "Example of <frow_bitno>: \"18_4\" sets bit 4 of row 18\n",
+ cmdtp->usage))
+ return 1;
+ out_be32(&iim->err, in_be32(&iim->err));
+ out_be32(&iim->prg_p, IIM_PRG_P_SET);
+ out_be32(&iim->ua, IIM_SET_UA(bank, f));
+ out_be32(&iim->la, IIM_SET_LA(f, bitno));
+#ifdef DEBUG
+ printf("Programming disabled with DEBUG defined \n");
+ printf(""Set up to pro
+ printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la);
+#else
+ out_be32(&iim->fctl, IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG);
+ do
+ udelay(20);
+ while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
+ out_be32(&iim->prg_p, 0);
+ err = in_be32(&iim->err);
+ if (stat & IIM_STAT_PRGD) {
+ if (!(err & (IIM_ERR_WPE | IIM_ERR_WPE))) {
+ printf("Fuse is successfully set");
+ if (err)
+ printf(" - however there are other errors");
+ printf("\n");
+ }
+ iim->stat = 0;
+ }
+ if (err) {
+ iim_err_msg(err);
+ out_be32(&iim->err, in_be32(&iim->err));
+ }
+#endif
+}
+
+int ads5121_fuse_sense(int bank, int fstart, int num)
+{
+ iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+ u32 iim_fbac;
+ u32 stat, err, err_hold = 0;
+ int f, ctr;
+
+ out_be32(&iim->err, in_be32(&iim->err));
+ if (bank == 0)
+ iim_fbac = in_be32(&iim->fbac0);
+ else
+ iim_fbac = in_be32(&iim->fbac1);
+ if (iim_fbac & IIM_FBAC_FBESP) {
+ printf("\tSense Protect disallows this operation\n");
+ out_be32(&iim->err, IIM_FBAC_FBESP);
+ return 1;
+ }
+ err = in_be32(&iim->err);
+ if (err) {
+ iim_err_msg(err);
+ err_hold |= err;
+ }
+ if (err & IIM_ERR_RPE)
+ printf("\tRead protect fuse is set; "
+ "Sense Protect may be set but will be attempted\n");
+ if (err)
+ out_be32(&iim->err, err);
+ printf("Sensing fuse(s) on Bank %d\n", bank);
+ for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) {
+ out_be32(&iim->ua, IIM_SET_UA(bank, f));
+ out_be32(&iim->la, IIM_SET_LA(f, 0));
+ out_be32(&iim->fctl, IIM_FCTL_ESNS_N);
+ do
+ udelay(20);
+ while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
+ err = in_be32(&iim->err);
+ if (err & IIM_ERR_SNSE) {
+ iim_err_msg(err);
+ out_be32(&iim->err, IIM_ERR_SNSE);
+ return 1;
+ }
+ if (stat & IIM_STAT_SNSD) {
+ out_be32(&iim->stat, 0);
+ if (ctr % 4 == 0)
+ printf("F%2d:", f);
+ printf("\t%#04x", (u8)iim->sdat);
+ if (ctr % 4 == 3)
+ printf("\n");
+ }
+ if (err) {
+ err_hold |= err;
+ out_be32(&iim->err, err);
+ }
+ }
+ if (ctr % 4 != 0)
+ printf("\n");
+ if (err_hold)
+ iim_err_msg(err_hold);
+
+ return 0;
+}
+
+int ads5121_fuse_stat(int bank)
+{
+ iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+ u32 iim_fbac;
+ u32 err;
+
+ out_be32(&iim->err, in_be32(&iim->err));
+ if (bank == 0)
+ iim_fbac = in_be32(&iim->fbac0);
+ else
+ iim_fbac = in_be32(&iim->fbac1);
+ err = in_be32(&iim->err);
+ if (err)
+ iim_err_msg(err);
+ if (err & IIM_ERR_RPE || iim_fbac & IIM_FBAC_FBRP) {
+ if (iim_fbac == 0)
+ printf("Since protection settings can't be read - "
+ "try sensing fuse row 0;\n");
+ return 0;
+ }
+ if (iim_fbac & IIM_PROTECTION)
+ printf("Protection Fuses Bank %d = %#04x:\n", bank, iim_fbac);
+ else if (!(err & IIM_ERR_RPE))
+ printf("No Protection fuses are set\n");
+ if (iim_fbac & IIM_FBAC_FBWP)
+ printf("\tWrite Protect fuse is set\n");
+ if (iim_fbac & IIM_FBAC_FBOP)
+ printf("\tOverride Protect fuse is set\n");
+ if (iim_fbac & IIM_FBAC_FBESP)
+ printf("\tSense Protect Fuse is set\n");
+ out_be32(&iim->err, in_be32(&iim->err));
+
+ return 0;
+}
+
+int do_ads5121_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int frow, n, v, bank;
+
+ if (cur_bank == '0')
+ bank = 0;
+ else
+ bank = 1;
+
+ switch (argc) {
+ case 0:
+ case 1:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 2:
+ if (strncmp(argv[1], "stat", 4) == 0)
+ return ads5121_fuse_stat(bank);
+ if (strncmp(argv[1], "read", 4) == 0)
+ return ads5121_fuse_read(bank, 0, IIM_FMAX + 1);
+ if (strncmp(argv[1], "sense", 5) == 0)
+ return ads5121_fuse_sense(bank, 0, IIM_FMAX + 1);
+ if (strncmp(argv[1], "ovride", 6) == 0)
+ return ads5121_fuse_override(bank, IIM_FMAX + 1, 0);
+ if (strncmp(argv[1], "bank", 4) == 0) {
+ printf("Active Fuse Bank is %c\n", cur_bank);
+ return 0;
+ }
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 3:
+ if (strncmp(argv[1], "bank", 4) == 0) {
+ if (argv[2][0] == '0')
+ cur_bank = '0';
+ else if (argv[2][0] == '1')
+ cur_bank = '1';
+ else {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ printf("Setting Active Fuse Bank to %c\n", cur_bank);
+ return 0;
+ }
+ if (strncmp(argv[1], "prog", 4) == 0)
+ return ads5121_fuse_prog(cmdtp, bank, argv[2]);
+
+ frow = (int)simple_strtol(argv[2], NULL, 10);
+ if (frow == 0 && argv[2][0] != '0')
+ frow = -1;
+ if (!in_range(frow, 0, IIM_FMAX,
+ "<frow> must be between 0-31\n\n", cmdtp->usage))
+ return 1;
+ if (strncmp(argv[1], "read", 4) == 0)
+ return ads5121_fuse_read(bank, frow, 1);
+ if (strncmp(argv[1], "ovride", 6) == 0)
+ return ads5121_fuse_override(bank, frow, 0);
+ if (strncmp(argv[1], "sense", 5) == 0)
+ return ads5121_fuse_sense(bank, frow, 1);
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 4:
+ frow = (int)simple_strtol(argv[2], NULL, 10);
+ if (frow == 0 && argv[2][0] != '0')
+ frow = -1;
+ if (!in_range(frow, 0, IIM_FMAX,
+ "<frow> must be between 0-31\n\n", cmdtp->usage))
+ return 1;
+ if (strncmp(argv[1], "read", 4) == 0) {
+ n = (int)simple_strtol(argv[3], NULL, 10);
+ if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
+ "<frow>+<n> must be between 1-32\n\n",
+ cmdtp->usage))
+ return 1;
+ return ads5121_fuse_read(bank, frow, n);
+ }
+ if (strncmp(argv[1], "ovride", 6) == 0) {
+ v = (int)simple_strtol(argv[3], NULL, 10);
+ return ads5121_fuse_override(bank, frow, v);
+ }
+ if (strncmp(argv[1], "sense", 5) == 0) {
+ n = (int)simple_strtol(argv[3], NULL, 10);
+ if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
+ "<frow>+<n> must be between 1-32\n\n",
+ cmdtp->usage))
+ return 1;
+ return ads5121_fuse_sense(bank, frow, n);
+ }
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ default: /* at least 5 args */
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+}
+
+U_BOOT_CMD(
+ fuse, CONFIG_SYS_MAXARGS, 0, do_ads5121_fuse,
+ " - Read, Sense, Override or Program Fuses\n",
+ "bank <n> - sets active Fuse Bank to 0 or 1\n"
+ " no args shows current active bank\n"
+ "fuse stat - print active fuse bank's protection status\n"
+ "fuse read [<frow> [<n>]] - print <n> fuse rows starting at <frow>\n"
+ " no args to print entire bank's fuses\n"
+ "fuse ovride [<frow> [<v>]]- override fuses at <frow> with <v>\n"
+ " no <v> defaults to 0 for the row\n"
+ " no args resets entire bank to 0\n"
+ " NOTE - settings persist until hard reset\n"
+ "fuse sense [<frow>] - senses current fuse at <frow>\n"
+ " no args for entire bank\n"
+ "fuse prog <frow_bit> - program fuse at row <frow>, bit <_bit>\n"
+ " <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
+ " WARNING - this is permanent\n"
+ );
+#endif /* CONFIG_CMD_FUSE */
CONFIG_PCI_MEMORY_BUS,
CONFIG_PCI_MEMORY_PHYS,
CONFIG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
CHRP_PCI_MEMORY_BUS,
CHRP_PCI_MEMORY_PHYS,
CHRP_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
fec_initialize(bis);
#endif
#if defined(CONFIG_ETHER_ON_SCC)
- mpc82xx_scc_enet_initialize(bd);
+ mpc82xx_scc_enet_initialize(bis);
#endif
return 0;
}
pci_set_region (hose->regions + 0,
PCI_SLV_MEM_BUS,
PCI_SLV_MEM_LOCAL,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+ gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#else
pci_set_region (hose->regions + 0,
CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_BASE,
- 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+ 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#endif
/* PCI memory space */
#endif
+#if !defined(CONFIG_SYS_SMC_RXBUFLEN)
+#define CONFIG_SYS_SMC_RXBUFLEN 1
+#define CONFIG_SYS_MAXIDLE 0
+#else
+#if !defined(CONFIG_SYS_MAXIDLE)
+#error "you must define CONFIG_SYS_MAXIDLE"
+#endif
+#endif
+
+typedef volatile struct serialbuffer {
+ cbd_t rxbd; /* Rx BD */
+ cbd_t txbd; /* Tx BD */
+ uint rxindex; /* index for next character to read */
+ volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
+ volatile uchar txbuf; /* tx buffers */
+} serialbuffer_t;
+
/* map rs_table index to baud rate generator index */
static unsigned char brg_map[] = {
6, /* BRG7 for SMC1 */
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
- volatile cbd_t *tbdf, *rbdf;
volatile cpm8260_t *cp = &(im->im_cpm);
uint dpaddr;
+ volatile serialbuffer_t *rtx;
/* initialize pointers to SMC */
*(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
- /* Disable transmitter/receiver.
- */
+ /* Disable transmitter/receiver. */
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
* damm: allocating space after the two buffers for rx/tx data
*/
- dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
+ /* allocate size of struct serialbuffer with bd rx/tx,
+ * buffer rx/tx and rx index
+ */
+ dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16);
+
+ rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr];
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
- rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
- rbdf->cbd_bufaddr = (uint) (rbdf+2);
- rbdf->cbd_sc = 0;
- tbdf = rbdf + 1;
- tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
- tbdf->cbd_sc = 0;
+ rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
+ rtx->rxbd.cbd_sc = 0;
+
+ rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
+ rtx->txbd.cbd_sc = 0;
- /* Set up the uart parameters in the parameter ram.
- */
+ /* Set up the uart parameters in the parameter ram. */
up->smc_rbase = dpaddr;
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = CPMFCR_EB;
*/
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
- /* Mask all interrupts and remove anything pending.
- */
+ /* Mask all interrupts and remove anything pending. */
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
*/
im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
- /* Set up the baud rate generator.
- */
+ /* Set up the baud rate generator. */
serial_setbrg ();
- /* Make the first buffer the only buffer.
- */
- tbdf->cbd_sc |= BD_SC_WRAP;
- rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+ /* Make the first buffer the only buffer. */
+ rtx->txbd.cbd_sc |= BD_SC_WRAP;
+ rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
- /* Single character receive.
- */
- up->smc_mrblr = 1;
- up->smc_maxidl = 0;
+ /* single/multi character receive. */
+ up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
+ up->smc_maxidl = CONFIG_SYS_MAXIDLE;
+ rtx->rxindex = 0;
- /* Initialize Tx/Rx parameters.
- */
+ /* Initialize Tx/Rx parameters. */
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
- /* Enable transmitter/receiver.
- */
+ /* Enable transmitter/receiver. */
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
return (0);
void
serial_putc(const char c)
{
- volatile cbd_t *tbdf;
- volatile char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ volatile serialbuffer_t *rtx;
if (c == '\n')
serial_putc ('\r');
up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
- tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
+ rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
- /* Wait for last character to go.
- */
- buf = (char *)tbdf->cbd_bufaddr;
- while (tbdf->cbd_sc & BD_SC_READY)
+ /* Wait for last character to go. */
+ while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY)
;
-
- *buf = c;
- tbdf->cbd_datlen = 1;
- tbdf->cbd_sc |= BD_SC_READY;
+ rtx->txbuf = c;
+ rtx->txbd.cbd_datlen = 1;
+ rtx->txbd.cbd_sc |= BD_SC_READY;
}
void
int
serial_getc(void)
{
- volatile cbd_t *rbdf;
- volatile unsigned char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- unsigned char c;
+ volatile serialbuffer_t *rtx;
+ unsigned char c;
up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
- rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
+ rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
- /* Wait for character to show up.
- */
- buf = (unsigned char *)rbdf->cbd_bufaddr;
- while (rbdf->cbd_sc & BD_SC_EMPTY)
+ /* Wait for character to show up. */
+ while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
;
- c = *buf;
- rbdf->cbd_sc |= BD_SC_EMPTY;
+ /* the characters are read one by one,
+ * use the rxindex to know the next char to deliver
+ */
+ c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex);
+ rtx->rxindex++;
+
+ /* check if all char are readout, then make prepare for next receive */
+ if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
+ rtx->rxindex = 0;
+ rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
+ }
return(c);
}
int
serial_tstc()
{
- volatile cbd_t *rbdf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ volatile serialbuffer_t *rtx;
up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
+ rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
- rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
-
- return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+ return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
}
#endif /* CONFIG_CONS_ON_SMC */
*(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
- /* Disable transmitter/receiver.
- */
+ /* Disable transmitter/receiver. */
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = 0;
- /* Set up the uart parameters in the parameter ram.
- */
+ /* Set up the uart parameters in the parameter ram. */
up->smc_rbase = dpaddr;
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = CPMFCR_EB;
*/
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
- /* Mask all interrupts and remove anything pending.
- */
+ /* Mask all interrupts and remove anything pending. */
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
im->im_cpmux.cmx_smr =
(im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
- /* Set up the baud rate generator.
- */
+ /* Set up the baud rate generator. */
#if defined(CONFIG_KGDB_USE_EXTC)
m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
#endif
- /* Make the first buffer the only buffer.
- */
+ /* Make the first buffer the only buffer. */
tbdf->cbd_sc |= BD_SC_WRAP;
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
- /* Single character receive.
- */
+ /* Single character receive. */
up->smc_mrblr = 1;
up->smc_maxidl = 0;
- /* Initialize Tx/Rx parameters.
- */
+ /* Initialize Tx/Rx parameters. */
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
- /* Enable transmitter/receiver.
- */
+ /* Enable transmitter/receiver. */
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
- /* Wait for last character to go.
- */
+ /* Wait for last character to go. */
buf = (char *)tbdf->cbd_bufaddr;
while (tbdf->cbd_sc & BD_SC_READY)
;
rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
- /* Wait for character to show up.
- */
+ /* Wait for character to show up. */
buf = (unsigned char *)rbdf->cbd_bufaddr;
while (rbdf->cbd_sc & BD_SC_EMPTY)
;
#include <libfdt.h>
#include <tsec.h>
#include <netdev.h>
+#include <fsl_esdhc.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
return 0;
}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
hose->regions[i].bus_start = 0;
hose->regions[i].phys_start = 0;
hose->regions[i].size = gd->ram_size;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+ hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->regions[i].bus_start = 0;
hose->regions[i].phys_start = 0;
hose->regions[i].size = gd->ram_size;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+ hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
i = hose->region_count++;
hose->regions[i].bus_start = CONFIG_SYS_IMMR;
hose->regions[i].phys_start = CONFIG_SYS_IMMR;
hose->regions[i].size = 0x100000;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+ hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
hose->first_busno = max_bus;
hose->last_busno = 0xff;
# supports ddr1/2/3
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
+COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
#include <command.h>
#include <tsec.h>
#include <netdev.h>
+#include <fsl_esdhc.h>
#include <asm/cache.h>
#include <asm/io.h>
CPU_TYPE_ENTRY(8568, 8568_E),
CPU_TYPE_ENTRY(8572, 8572),
CPU_TYPE_ENTRY(8572, 8572_E),
+ CPU_TYPE_ENTRY(P2020, P2020),
+ CPU_TYPE_ENTRY(P2020, P2020_E),
};
struct cpu_type *identify_cpu(u32 ver)
get_sys_info(&sysinfo);
- puts("Clock Configuration:\n ");
- for (i = 0; i < CONFIG_NUM_CPUS; i++)
+ puts("Clock Configuration:");
+ for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+ if (!(i & 3))
+ printf ("\n ");
printf("CPU%d:%-4s MHz, ",
i,strmhz(buf1, sysinfo.freqProcessor[i]));
- printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+ }
+ printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
switch (ddr_ratio) {
case 0x0:
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
tsec_standard_init(bis);
#endif
+
+ return 0;
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
return 0;
+#endif
}
{
unsigned int i;
volatile ccsr_ddr_t *ddr;
+ u32 temp_sdram_cfg;
switch (ctrl_num) {
case 0:
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ /* Do not enable the memory */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+ temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
/*
* For 8572 DDR1 erratum - DDR controller may enter illegal state
* when operatiing in 32-bit bus mode with 4-beat bursts,
udelay(200);
asm volatile("sync;isync");
- out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+ /* Let the controller go */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
unsigned int tlb_size;
- unsigned int ram_tlb_index;
- unsigned int ram_tlb_address;
+ unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
+ unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
+ u64 size, memsize = (u64)memsize_in_meg << 20;
- /*
- * Determine size of each TLB1 entry.
- */
- switch (memsize_in_meg) {
- case 16:
- case 32:
- tlb_size = BOOKE_PAGESZ_16M;
- break;
- case 64:
- case 128:
- tlb_size = BOOKE_PAGESZ_64M;
- break;
- case 256:
- case 512:
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- case 1024:
- case 2048:
- if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
- tlb_size = BOOKE_PAGESZ_1G;
- else
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- default:
- puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
- " and 2G are supported.\n");
-
- /*
- * The memory was not able to be mapped.
- * Default to a small size.
- */
- tlb_size = BOOKE_PAGESZ_64M;
- memsize_in_meg = 64;
- break;
- }
+ size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+
+ /* Convert (4^max) kB to (2^max) bytes */
+ max_cam = max_cam * 2 + 10;
+
+ for (; size && ram_tlb_index < 16; ram_tlb_index++) {
+ u32 camsize = __ilog2_u64(size) & ~1U;
+ u32 align = __ilog2(ram_tlb_address) & ~1U;
+
+ if (align == -2) align = max_cam;
+ if (camsize > align)
+ camsize = align;
+
+ if (camsize > max_cam)
+ camsize = max_cam;
+
+ tlb_size = (camsize - 10) / 2;
- /*
- * Configure DDR TLB1 entries.
- * Starting at TLB1 8, use no more than 8 TLB1 entries.
- */
- ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
- ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
- while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
- && ram_tlb_index < 16) {
set_tlb(1, ram_tlb_address, ram_tlb_address,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
- ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
- ram_tlb_index++;
+ size -= 1ULL << camsize;
+ memsize -= 1ULL << camsize;
+ ram_tlb_address += 1UL << camsize;
}
+ if (memsize)
+ printf("%lldM left unmapped\n", memsize >> 20);
+
/*
* Confirm that the requested amount of memory was mapped.
*/
#include <asm/fsl_law.h>
+/*
+ * Default board reset function
+ */
+static void
+__board_reset(void)
+{
+ /* Do nothing */
+}
+void board_reset(void) __attribute((weak, alias("__board_reset")));
+
+
int
checkcpu(void)
{
uint pvr, svr;
uint ver;
uint major, minor;
+ char buf1[32], buf2[32];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
-
- puts("Freescale PowerPC\n");
-
- pvr = get_pvr();
- ver = PVR_VER(pvr);
- major = PVR_MAJ(pvr);
- minor = PVR_MIN(pvr);
-
- puts("CPU:\n");
- puts(" Core: ");
-
- switch (ver) {
- case PVR_VER(PVR_86xx):
- {
- uint msscr0 = mfspr(MSSCR0);
- printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
- if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
- puts("\n Core1Translation Enabled");
- debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
- }
- break;
- default:
- puts("Unknown");
- break;
- }
- printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
+ uint msscr0 = mfspr(MSSCR0);
svr = get_svr();
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
- puts(" System: ");
+ puts("CPU: ");
+
switch (ver) {
case SVR_8641:
- if (SVR_SUBVER(svr) == 1) {
- puts("8641D");
- } else {
puts("8641");
- }
- break;
+ break;
+ case SVR_8641D:
+ puts("8641D");
+ break;
case SVR_8610:
puts("8610");
break;
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
+ puts("Core: ");
+
+ pvr = get_pvr();
+ ver = PVR_E600_VER(pvr);
+ major = PVR_E600_MAJ(pvr);
+ minor = PVR_E600_MIN(pvr);
+
+ printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
+ if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
+ puts("\n Core1Translation Enabled");
+ debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
+
+ printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
- puts(" Clocks: ");
- printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
- printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
- printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+ puts("Clock Configuration:\n");
+ printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
+ printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
+ printf(" DDR:%-4s MHz (%s MT/s data rate), ",
+ strmhz(buf1, sysinfo.freqSystemBus / 2),
+ strmhz(buf2, sysinfo.freqSystemBus));
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
- printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
+ printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
}
- puts(" L2: ");
- if (get_l2cr() & 0x80000000)
- puts("Enabled\n");
- else
+ puts("L1: D-cache 32 KB enabled\n");
+ puts(" I-cache 32 KB enabled\n");
+
+ puts("L2: ");
+ if (get_l2cr() & 0x80000000) {
+#if defined(CONFIG_MPC8610)
+ puts("256");
+#elif defined(CONFIG_MPC8641)
+ puts("512");
+#endif
+ puts(" KB enabled\n");
+ } else {
puts("Disabled\n");
+ }
return 0;
}
-static inline void
-soft_restart(unsigned long addr)
-{
-#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
-
- /*
- * SRR0 has system reset vector, SRR1 has default MSR value
- * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
- */
-
- __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
- __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
- __asm__ __volatile__ ("mtspr 27, 4");
- __asm__ __volatile__ ("rfi");
-
-#else /* CONFIG_MPC8641HPCN */
-
- out8(PIXIS_BASE + PIXIS_RST, 0);
-
-#endif /* !CONFIG_MPC8641HPCN */
-
- while (1) ; /* not reached */
-}
-
-
-/*
- * No generic way to do board reset. Simply call soft_reset.
- */
void
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
-#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
-
-#ifdef CONFIG_SYS_RESET_ADDRESS
- ulong addr = CONFIG_SYS_RESET_ADDRESS;
-#else
- /*
- * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
- * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
- * address. Better pick an address known to be invalid on your
- * system and assign it to CONFIG_SYS_RESET_ADDRESS.
- */
- ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
-#endif
-
- /* flush and disable I/D cache */
- __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
- __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
- __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
- __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 4");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 5");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
-
- soft_restart(addr);
-
-#else /* CONFIG_MPC8641HPCN */
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
- out8(PIXIS_BASE + PIXIS_RST, 0);
+ /* Attempt board-specific reset */
+ board_reset();
-#endif /* !CONFIG_MPC8641HPCN */
+ /* Next try asserting HRESET_REQ */
+ out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
- while (1) ; /* not reached */
+ while (1)
+ ;
}
return;
}
+
+#ifdef CONFIG_ADDR_MAP
+/* Initialize address mapping array */
+void init_addr_map(void)
+{
+ int i;
+ ppc_bat_t bat = DBAT0;
+ phys_size_t size;
+ unsigned long upper, lower;
+
+ for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
+ if (read_bat(bat, &upper, &lower) != -1) {
+ if (!BATU_VALID(upper))
+ size = 0;
+ else
+ size = BATU_SIZE(upper);
+ addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
+ size, i);
+ }
+#ifdef CONFIG_HIGH_BATS
+ /* High bats are not contiguous with low BAT numbers */
+ if (bat == DBAT3)
+ bat = DBAT4 - 1;
+#endif
+ }
+}
+#endif
#endif /* CONFIG_8xx_CONS_SCCx */
+#if !defined(CONFIG_SYS_SMC_RXBUFLEN)
+#define CONFIG_SYS_SMC_RXBUFLEN 1
+#define CONFIG_SYS_MAXIDLE 0
+#else
+#if !defined(CONFIG_SYS_MAXIDLE)
+#error "you must define CONFIG_SYS_MAXIDLE"
+#endif
+#endif
+
+typedef volatile struct serialbuffer {
+ cbd_t rxbd; /* Rx BD */
+ cbd_t txbd; /* Tx BD */
+ uint rxindex; /* index for next character to read */
+ volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
+ volatile uchar txbuf; /* tx buffers */
+} serialbuffer_t;
+
static void serial_setdivisor(volatile cpm8xx_t *cp)
{
int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
- volatile cbd_t *tbdf, *rbdf;
volatile cpm8xx_t *cp = &(im->im_cpm);
#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
#endif
uint dpaddr;
+ volatile serialbuffer_t *rtx;
/* initialize pointers to SMC */
up->smc_rpbase = 0;
#endif
- /* Disable transmitter/receiver.
- */
+ /* Disable transmitter/receiver. */
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
- /* Enable SDMA.
- */
+ /* Enable SDMA. */
im->im_siu_conf.sc_sdcr = 1;
/* clear error conditions */
#endif
#if defined(CONFIG_8xx_CONS_SMC1)
- /* Use Port B for SMC1 instead of other functions.
- */
+ /* Use Port B for SMC1 instead of other functions. */
cp->cp_pbpar |= 0x000000c0;
cp->cp_pbdir &= ~0x000000c0;
cp->cp_pbodr &= ~0x000000c0;
#else /* CONFIG_8xx_CONS_SMC2 */
# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
- /* Use Port A for SMC2 instead of other functions.
- */
+ /* Use Port A for SMC2 instead of other functions. */
ip->iop_papar |= 0x00c0;
ip->iop_padir &= ~0x00c0;
ip->iop_paodr &= ~0x00c0;
# else /* must be a 860 then */
/* Use Port B for SMC2 instead of other functions.
- */
+ */
cp->cp_pbpar |= 0x00000c00;
cp->cp_pbdir &= ~0x00000c00;
cp->cp_pbodr &= ~0x00000c00;
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
- dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
+ /* allocate
+ * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
+ */
+ dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
#else
dpaddr = CPM_SERIAL_BASE ;
#endif
+ rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
* change with newer versions of the firmware.
* damm: allocating space after the two buffers for rx/tx data
*/
- rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
- rbdf->cbd_bufaddr = (uint) (rbdf+2);
- rbdf->cbd_sc = 0;
- tbdf = rbdf + 1;
- tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
- tbdf->cbd_sc = 0;
+ rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
+ rtx->rxbd.cbd_sc = 0;
- /* Set up the uart parameters in the parameter ram.
- */
+ rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
+ rtx->txbd.cbd_sc = 0;
+
+ /* Set up the uart parameters in the parameter ram. */
up->smc_rbase = dpaddr;
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = SMC_EB;
smc_setbrg ();
#endif
- /* Make the first buffer the only buffer.
- */
- tbdf->cbd_sc |= BD_SC_WRAP;
- rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+ /* Make the first buffer the only buffer. */
+ rtx->txbd.cbd_sc |= BD_SC_WRAP;
+ rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
- /* Single character receive.
- */
- up->smc_mrblr = 1;
- up->smc_maxidl = 0;
-
- /* Initialize Tx/Rx parameters.
- */
+ /* single/multi character receive. */
+ up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
+ up->smc_maxidl = CONFIG_SYS_MAXIDLE;
+ rtx->rxindex = 0;
+ /* Initialize Tx/Rx parameters. */
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
- /* Enable transmitter/receiver.
- */
+ /* Enable transmitter/receiver. */
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
return (0);
static void
smc_putc(const char c)
{
- volatile cbd_t *tbdf;
- volatile char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
+ volatile serialbuffer_t *rtx;
#ifdef CONFIG_MODEM_SUPPORT
if (gd->be_quiet)
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
- tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
-
- /* Wait for last character to go.
- */
-
- buf = (char *)tbdf->cbd_bufaddr;
+ rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
- *buf = c;
- tbdf->cbd_datlen = 1;
- tbdf->cbd_sc |= BD_SC_READY;
+ /* Wait for last character to go. */
+ rtx->txbuf = c;
+ rtx->txbd.cbd_datlen = 1;
+ rtx->txbd.cbd_sc |= BD_SC_READY;
__asm__("eieio");
- while (tbdf->cbd_sc & BD_SC_READY) {
+ while (rtx->txbd.cbd_sc & BD_SC_READY) {
WATCHDOG_RESET ();
__asm__("eieio");
}
static int
smc_getc(void)
{
- volatile cbd_t *rbdf;
- volatile unsigned char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
- unsigned char c;
+ volatile serialbuffer_t *rtx;
+ unsigned char c;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
+ rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
- rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
-
- /* Wait for character to show up.
- */
- buf = (unsigned char *)rbdf->cbd_bufaddr;
-
- while (rbdf->cbd_sc & BD_SC_EMPTY)
+ /* Wait for character to show up. */
+ while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
WATCHDOG_RESET ();
- c = *buf;
- rbdf->cbd_sc |= BD_SC_EMPTY;
+ /* the characters are read one by one,
+ * use the rxindex to know the next char to deliver
+ */
+ c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
+ rtx->rxindex++;
+ /* check if all char are readout, then make prepare for next receive */
+ if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
+ rtx->rxindex = 0;
+ rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
+ }
return(c);
}
static int
smc_tstc(void)
{
- volatile cbd_t *rbdf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
+ volatile serialbuffer_t *rtx;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
- rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
- return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+ return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
}
struct serial_device serial_smc_device =
}
#endif /* CONFIG_LWMON */
- /* Disable transmitter/receiver.
- */
+ /* Disable transmitter/receiver. */
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
#endif
- /* Allocate space for two buffer descriptors in the DP ram.
- */
+ /* Allocate space for two buffer descriptors in the DP ram. */
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
dpaddr = CPM_SERIAL2_BASE ;
#endif
- /* Enable SDMA.
- */
+ /* Enable SDMA. */
im->im_siu_conf.sc_sdcr = 0x0001;
/* Set the physical address of the host memory buffers in
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = 0;
- /* Set up the baud rate generator.
- */
+ /* Set up the baud rate generator. */
scc_setbrg ();
- /* Set up the uart parameters in the parameter ram.
- */
+ /* Set up the uart parameters in the parameter ram. */
up->scc_genscc.scc_rbase = dpaddr;
up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
- /* Initialize Tx/Rx parameters.
- */
+ /* Initialize Tx/Rx parameters. */
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
up->scc_char8 = 0x8000;
up->scc_rccm = 0xc0ff;
- /* Set low latency / small fifo.
- */
+ /* Set low latency / small fifo. */
sp->scc_gsmrh = SCC_GSMRH_RFW;
/* Set SCC(x) clock mode to 16x
* Wire BRG1 to SCCn
*/
- /* Set UART mode, clock divider 16 on Tx and Rx
- */
+ /* Set UART mode, clock divider 16 on Tx and Rx */
sp->scc_gsmrl &= ~0xF;
sp->scc_gsmrl |=
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
sp->scc_psmr = 0;
sp->scc_psmr |= SCU_PSMR_CL;
- /* Mask all interrupts and remove anything pending.
- */
+ /* Mask all interrupts and remove anything pending. */
sp->scc_sccm = 0;
sp->scc_scce = 0xffff;
sp->scc_dsr = 0x7e7e;
sp->scc_psmr = 0x3000;
- /* Make the first buffer the only buffer.
- */
+ /* Make the first buffer the only buffer. */
tbdf->cbd_sc |= BD_SC_WRAP;
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
- /* Enable transmitter/receiver.
- */
+ /* Enable transmitter/receiver. */
sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
return (0);
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
- /* Wait for last character to go.
- */
+ /* Wait for last character to go. */
buf = (char *)tbdf->cbd_bufaddr;
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
- /* Wait for character to show up.
- */
+ /* Wait for character to show up. */
buf = (unsigned char *)rbdf->cbd_bufaddr;
while (rbdf->cbd_sc & BD_SC_EMPTY)
if (max_end >= 0xff) {
printf("This U-Boot only supports < 4G of DDR\n");
printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
- return 0; /* Ensure DDR setup failure. */
+ return CONFIG_MAX_MEM_MAPPED;
}
#endif
unsigned int ctrl_num)
{
unsigned int i;
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
const char *p;
+#endif
/* Chip select options. */
* requested ranks interleaved together such that the result
* should be a subset of the requested configuration.
*/
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
if ((p = getenv("memctl_intlv_ctl")) != NULL) {
if (pdimm[0].n_ranks == 0) {
printf("There is no rank on CS0. Because only rank on "
break;
}
}
+#endif
fsl_ddr_board_options(popts, pdimm, ctrl_num);
* SDRAM. This is because we only map the first 2GB on such systems, and therefore
* the ECC parity byte of the remaining area can't be written.
*/
-#ifndef CONFIG_MAX_MEM_MAPPED
-#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
-#endif
/*
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
* Set the SDRAM Controller On Die Termination Register
*-----------------------------------------------------------------*/
mfsdram(SDRAM_CODT, codt);
- codt |= (SDRAM_CODT_IO_NMODE
- & (~SDRAM_CODT_DQS_SINGLE_END
- & ~SDRAM_CODT_CKSE_SINGLE_END
- & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
- & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
+ codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
+ codt |= SDRAM_CODT_IO_NMODE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] != SDRAM_NONE) {
#define NUMLOOPS 1 /* configure as you deem approporiate */
#define NUMMEMWORDS 16
+#define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n))
+
/* Private Structure Definitions */
struct autocal_regs {
}
ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
+u32 __ddr_rdss_opt(u32 default_val)
+{
+ return default_val;
+}
+u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt")));
+
+
static u32 *get_membase(int bxcr_num)
{
ulong bxcf;
ppcDcbf((ulong)&(base_address[j]));
}
sync();
+ iobarrier_rw();
for (l = 0; l < NUMLOOPS; l++) {
for (j = 0; j < NUMMEMWORDS; j++) {
if (base_address[j] != test[i][j]) {
ppcDcbf((u32)&(base_address[j]));
} /* for (j = 0; j < NUMMEMWORDS; j++) */
sync();
+ iobarrier_rw();
} /* for (l=0; l<NUMLOOPS; l++) */
}
* Program RDCC register
* Read sample cycle auto-update enable
*/
- mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T1 | SDRAM_RDCC_RSAE_ENABLE);
+ mtsdram(SDRAM_RDCC,
+ ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
#ifdef DEBUG
mfsdram(SDRAM_RDCC, temp);
* Program RDCC register
* Read sample cycle auto-update enable
*/
- mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T2 | SDRAM_RDCC_RSAE_ENABLE);
+ mtsdram(SDRAM_RDCC,
+ ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
#ifdef DEBUG
mfsdram(SDRAM_RDCC, temp);
* if no passing window was found, or is the
* size of the RFFD passing window.
*/
- if (result != 0) {
- tcal.autocal.flags = 1;
- debug("*** (%d)(%d) result passed window size: 0x%08x, "
- "rqfd = 0x%08x, rffd = 0x%08x, rdcc = 0x%08x\n",
- wdtr, clkp, result, ddrcal.rqfd,
- ddrcal.rffd, ddrcal.rdcc);
- /*
- * Save the SDRAM_WRDTR and SDRAM_CLKTR
- * settings for the largest returned
- * RFFD passing window size.
- */
- if (result > best_result) {
+ /*
+ * want the lowest Read Sample Cycle Select
+ */
+ val = SDRAM_RDCC_RDSS_DECODE(val);
+ debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
+ val, best_rdcc);
+
+ if ((result != 0) &&
+ (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) {
+ if (((result == best_result) && (val < best_rdcc)) ||
+ ((result > best_result) && (val <= best_rdcc))) {
+ tcal.autocal.flags = 1;
+ debug("*** (%d)(%d) result passed window "
+ "size: 0x%08x, rqfd = 0x%08x, "
+ "rffd = 0x%08x, rdcc = 0x%08x\n",
+ wdtr, clkp, result, ddrcal.rqfd,
+ ddrcal.rffd, ddrcal.rdcc);
+
/*
- * want the lowest Read Sample Cycle Select
+ * Save the SDRAM_WRDTR and SDRAM_CLKTR
+ * settings for the largest returned
+ * RFFD passing window size.
*/
- val = (val & SDRAM_RDCC_RDSS_MASK) >> 30;
- debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
- val, best_rdcc);
- if (val <= best_rdcc) {
- best_rdcc = val;
- tcal.clocks.wrdtr = wdtr;
- tcal.clocks.clktr = clkp;
- tcal.clocks.rdcc = (val << 30);
- tcal.autocal.rqfd = ddrcal.rqfd;
- tcal.autocal.rffd = ddrcal.rffd;
- best_result = result;
+ best_rdcc = val;
+ tcal.clocks.wrdtr = wdtr;
+ tcal.clocks.clktr = clkp;
+ tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val);
+ tcal.autocal.rqfd = ddrcal.rqfd;
+ tcal.autocal.rffd = ddrcal.rffd;
+ best_result = result;
if (verbose_lvl > 2) {
printf("** (%d)(%d) "
"loop FCSR: 0x%08x\n",
wdtr, clkp, val);
}
- } /* if (val <= best_rdcc) */
- } /* if (result >= best_result) */
- } /* if (result != 0) */
+ }
+ } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */
scan_list++;
} /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
ptmpcila[i], ptmla[i],
~(ptmms[i] & 0xfffff000) + 1,
PCI_REGION_MEM |
- PCI_REGION_MEMORY);
+ PCI_REGION_SYS_MEMORY);
}
/* PCI memory spaces */
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY );
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
#endif
hose->region_count = reg_num;
int busno;
busno = pci_440_init (&ppc440_hose);
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if (defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
+ !defined(CONFIG_PCI_DISABLE_PCIE)
pcie_setup_hoses(busno + 1);
#endif
}
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
- defined(CONFIG_PCI)
+ defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
#include <asm/4xx_pcie.h>
void ft_cpu_setup(void *blob, bd_t *bd)
{
sys_info_t sys_info;
+ int off, ndepth = 0;
get_sys_info(&sys_info);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
/*
- * Setup all baudrates for the UARTs
+ * Fixup all UART clocks for CPU internal UARTs
+ * (only these UARTs are definitely clocked by gd->uart_clk)
+ *
+ * These UARTs are direct childs of /plb/opb. This code
+ * does not touch any UARTs that are connected to the ebc.
*/
- do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
+ off = fdt_path_offset(blob, "/plb/opb");
+ while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
+ /*
+ * process all sub nodes and stop when we are back
+ * at the starting depth
+ */
+ if (ndepth <= 0)
+ break;
+
+ /* only update direct childs */
+ if ((ndepth == 1) &&
+ (fdt_node_check_compatible(blob, off, "ns16550") == 0))
+ fdt_setprop(blob, off,
+ "clock-frequency",
+ (void*)&(gd->uart_clk), 4);
+ }
/*
* Fixup all ethernet nodes
#include <asm/arch/hardware.h>
#include <part.h>
+#include "mmc.h"
+
#ifdef CONFIG_MMC
extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no);
int
/****************************************************/
-mmc_init(int verbose)
+mmc_legacy_init(int verbose)
/****************************************************/
{
int retries, rc = -ENODEV;
return rc;
}
-int mmc_ident(block_dev_desc_t * dev)
-{
- return 0;
-}
-
-int mmc2info(ulong addr)
-{
- if (addr >= CONFIG_SYS_MMC_BASE
- && addr < CONFIG_SYS_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) {
- return 1;
- }
- return 0;
-}
-
#endif /* CONFIG_MMC */
LIB = $(obj)libdisk.a
COBJS-y += part.o
-COBJS-y += part_mac.o
-COBJS-y += part_dos.o
-COBJS-y += part_iso.o
-COBJS-y += part_amiga.o
-COBJS-y += part_efi.o
+COBJS-$(CONFIG_MAC_PARTITION) += part_mac.o
+COBJS-$(CONFIG_DOS_PARTITION) += part_dos.o
+COBJS-$(CONFIG_ISO_PARTITION) += part_iso.o
+COBJS-$(CONFIG_AMIGA_PARTITION) += part_amiga.o
+COBJS-$(CONFIG_EFI_PARTITION) += part_efi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#include <ide.h>
#include "part_amiga.h"
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_AMIGA_PARTITION)
+#if defined(CONFIG_CMD_IDE) || \
+ defined(CONFIG_CMD_SCSI) || \
+ defined(CONFIG_CMD_USB) || \
+ defined(CONFIG_MMC) || \
+ defined(CONFIG_SYSTEMACE)
#undef AMIGA_DEBUG
#include <ide.h>
#include "part_dos.h"
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_DOS_PARTITION)
+#if defined(CONFIG_CMD_IDE) || \
+ defined(CONFIG_CMD_SATA) || \
+ defined(CONFIG_CMD_SCSI) || \
+ defined(CONFIG_CMD_USB) || \
+ defined(CONFIG_MMC) || \
+ defined(CONFIG_SYSTEMACE)
/* Convert char[4] in little endian format to the host format integer
*/
#include <malloc.h>
#include "part_efi.h"
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_EFI_PARTITION)
+#if defined(CONFIG_CMD_IDE) || \
+ defined(CONFIG_CMD_SATA) || \
+ defined(CONFIG_CMD_SCSI) || \
+ defined(CONFIG_CMD_USB) || \
+ defined(CONFIG_MMC) || \
+ defined(CONFIG_SYSTEMACE)
/* Convert char[2] in little endian format to the host format integer
*/
#include <command.h>
#include "part_iso.h"
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_ISO_PARTITION)
+#if defined(CONFIG_CMD_IDE) || \
+ defined(CONFIG_CMD_SCSI) || \
+ defined(CONFIG_CMD_SATA) || \
+ defined(CONFIG_CMD_USB) || \
+ defined(CONFIG_MMC) || \
+ defined(CONFIG_SYSTEMACE)
/* #define ISO_PART_DEBUG */
#include <ide.h>
#include "part_mac.h"
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_MAC_PARTITION)
+#if defined(CONFIG_CMD_IDE) || \
+ defined(CONFIG_CMD_SCSI) || \
+ defined(CONFIG_CMD_SATA) || \
+ defined(CONFIG_CMD_USB) || \
+ defined(CONFIG_MMC) || \
+ defined(CONFIG_SYSTEMACE)
/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
#ifndef __ldiv_t_defined
2008-02-22, Larry Johnson <lrj@acm.org>
-
The CompactFlash(R) controller on the Korat board provides a hi-speed USB
interface. This may be connected to either a dedicated port on the on-board
USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot
-------------
1. Build kernel image for core0:
- a. $ make 85xx/mpc8572_ds_defconfig
+ a. $ make 85xx/mpc8572_ds_defconfig
- b. $ make menuconfig
- - un-select "Processor support"->"Symetric multi-processing support"
+ b. $ make menuconfig
+ - un-select "Processor support"->"Symetric multi-processing support"
- c. $ make uImage
+ c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
2. Build kernel image for core1:
- a. $ make 85xx/mpc8572_ds_defconfig
+ a. $ make 85xx/mpc8572_ds_defconfig
- b. $ make menuconfig
- - Un-select "Processor support"->"Symetric multi-processing support"
- - Select "Advanced setup" -> " Prompt for advanced kernel
- configuration options"
- - Select "Set physical address where the kernel is loaded" and
- set it to 0x20000000, asssuming core1 will start from 512MB.
- - Select "Set custom page offset address"
- - Select "Set custom kernel base address"
- - Select "Set maximum low memory"
- - "Exit" and save the selection.
+ b. $ make menuconfig
+ - Un-select "Processor support"->"Symetric multi-processing support"
+ - Select "Advanced setup" -> " Prompt for advanced kernel
+ configuration options"
+ - Select "Set physical address where the kernel is loaded" and
+ set it to 0x20000000, asssuming core1 will start from 512MB.
+ - Select "Set custom page offset address"
+ - Select "Set custom kernel base address"
+ - Select "Set maximum low memory"
+ - "Exit" and save the selection.
- c. $ make uImage
+ c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
3. Create dtb for core0:
- $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
+ $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
4. Create dtb for core1:
- $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
+ $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
5. Bring up two cores separately:
- a. Power on the board, under u-boot prompt:
- => setenv <serverip>
- => setenv <ipaddr>
- => setenv bootargs root=/dev/ram rw console=ttyS0,115200
- b. Bring up core1's kernel first:
- => setenv bootm_low 0x20000000
- => setenv bootm_size 0x10000000
- => tftp 21000000 8572/uImage.core1
- => tftp 22000000 8572/ramdiskfile
- => tftp 20c00000 8572/mpc8572ds_core1.dtb
- => interrupts off
- => bootm start 21000000 22000000 20c00000
- => bootm loados
- => bootm ramdisk
- => bootm fdt
- => fdt boardsetup
- => fdt chosen $initrd_start $initrd_end
- => bootm prep
- => cpu 1 release $bootm_low - $fdtaddr -
- c. Bring up core0's kernel(on the same u-boot console):
- => setenv bootm_low 0
- => setenv bootm_size 0x20000000
- => tftp 1000000 8572/uImage.core0
- => tftp 2000000 8572/ramdiskfile
- => tftp c00000 8572/mpc8572ds_core0.dtb
- => bootm 1000000 2000000 c00000
+ a. Power on the board, under u-boot prompt:
+ => setenv <serverip>
+ => setenv <ipaddr>
+ => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+ b. Bring up core1's kernel first:
+ => setenv bootm_low 0x20000000
+ => setenv bootm_size 0x10000000
+ => tftp 21000000 8572/uImage.core1
+ => tftp 22000000 8572/ramdiskfile
+ => tftp 20c00000 8572/mpc8572ds_core1.dtb
+ => interrupts off
+ => bootm start 21000000 22000000 20c00000
+ => bootm loados
+ => bootm ramdisk
+ => bootm fdt
+ => fdt boardsetup
+ => fdt chosen $initrd_start $initrd_end
+ => bootm prep
+ => cpu 1 release $bootm_low - $fdtaddr -
+ c. Bring up core0's kernel(on the same u-boot console):
+ => setenv bootm_low 0
+ => setenv bootm_size 0x20000000
+ => tftp 1000000 8572/uImage.core0
+ => tftp 2000000 8572/ramdiskfile
+ => tftp c00000 8572/mpc8572ds_core0.dtb
+ => bootm 1000000 2000000 c00000
Please note only core0 will run u-boot, core1 starts kernel directly after
"cpu release" command is issued.
--- /dev/null
+The following is a list of files and features that are going to be
+removed from the U-Boot source tree. Every entry should contain what
+exactly is going away, when it will be gone, why it is being removed,
+and who is going to be doing the work. When the feature is removed
+from U-Boot, its corresponding entry should also be removed from this
+file.
+
+---------------------------
+
+What: "autoscr" command
+When: August 2009
+Why: "autosrc" is an ugly and completely non-standard name. The "autoscr"
+ command is deprecated and will be replaced the "source" command as
+ used by other shells such as bash. Both commands will be supported
+ for a transition period of 6 months after which "autoscr" will be
+ removed.
+Who: Peter Tyser <ptyser@xes-inc.com>
+
+---------------------------
+
+What: Individual I2C commands
+When: April 2009
+Why: Per the U-Boot README, individual I2C commands such as "imd", "imm",
+ "imw", etc are deprecated. The single "i2c" command which is
+ currently enabled via CONFIG_I2C_CMD_TREE contains the same
+ functionality as the individual I2C commands. The individual
+ I2C commands should be removed as well as any references to
+ CONFIG_I2C_CMD_TREE.
+Who: Peter Tyser <ptyser@xes-inc.com>
+
+---------------------------
+
+What: Legacy NAND code
+When: April 2009
+Why: Legacy NAND code is deprecated. Similar functionality exists in
+ more recent NAND code ported from the Linux kernel.
+Who: Scott Wood <scottwood@freescale.com>
static int ahci_init_one(pci_dev_t pdev)
{
- u32 iobase;
u16 vendor;
int rc;
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->dev = pdev;
- pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
- iobase &= ~0xf;
-
probe_ent->host_flags = ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- probe_ent->mmio_base = iobase;
+ probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
+ PCI_REGION_MEM);
/* Take from kernel:
* JMicron-specific fixup:
}
if (status & ATA_BUSY) {
- printf ("ata%u is slow to respond,plz be patient\n", port);
+ printf ("ata%u is slow to respond,plz be patient\n", num);
}
while ((status & ATA_BUSY)) {
}
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond : ", port);
+ printf ("ata%u failed to respond : ", num);
printf ("bus reset failed\n");
port[num].dev_mask = 0;
return 1;
#ifdef CONFIG_SYS_I2C_MX31_PORT1
#define I2C_BASE 0x43f80000
+#define I2C_CLK_OFFSET 26
#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
#define I2C_BASE 0x43f98000
+#define I2C_CLK_OFFSET 28
#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
#define I2C_BASE 0x43f84000
+#define I2C_CLK_OFFSET 30
#else
#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver"
#endif
int freq = mx31_get_ipg_clk();
int i;
+ /* start the required I2C clock */
+ __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET);
+
for (i = 0; i < 0x1f; i++)
if (freq / div[i] <= speed)
break;
defined(CONFIG_MPC8568) || \
defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
#define FSL_HW_NUM_LAWS 10
-#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572)
+#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
+ defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
#else
#error FSL_HW_NUM_LAWS not defined for this platform
LIB := $(obj)libmmc.a
+COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
+COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
dtocyc << shift, dtor);
}
-int mmc_init(int verbose)
+int mmc_legacy_init(int verbose)
{
struct mmc_cid cid;
struct mmc_csd csd;
return 0;
}
-
-int mmc_read(ulong src, uchar *dst, int size)
-{
- return -ENOSYS;
-}
-
-int mmc_write(uchar *src, ulong dst, int size)
-{
- return -ENOSYS;
-}
-
-int mmc2info(ulong addr)
-{
- return 0;
-}
--- /dev/null
+/*
+ * Copyright 2007, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <mmc.h>
+#include <part.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fsl_esdhc {
+ uint dsaddr;
+ uint blkattr;
+ uint cmdarg;
+ uint xfertyp;
+ uint cmdrsp0;
+ uint cmdrsp1;
+ uint cmdrsp2;
+ uint cmdrsp3;
+ uint datport;
+ uint prsstat;
+ uint proctl;
+ uint sysctl;
+ uint irqstat;
+ uint irqstaten;
+ uint irqsigen;
+ uint autoc12err;
+ uint hostcapblt;
+ uint wml;
+ char reserved1[8];
+ uint fevt;
+ char reserved2[168];
+ uint hostver;
+ char reserved3[780];
+ uint scr;
+};
+
+/* Return the XFERTYP flags for a given command and data packet */
+uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ uint xfertyp = 0;
+
+ if (data) {
+ xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
+
+ if (data->blocks > 1) {
+ xfertyp |= XFERTYP_MSBSEL;
+ xfertyp |= XFERTYP_BCEN;
+ }
+
+ if (data->flags & MMC_DATA_READ)
+ xfertyp |= XFERTYP_DTDSEL;
+ }
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ xfertyp |= XFERTYP_CCCEN;
+ if (cmd->resp_type & MMC_RSP_OPCODE)
+ xfertyp |= XFERTYP_CICEN;
+ if (cmd->resp_type & MMC_RSP_136)
+ xfertyp |= XFERTYP_RSPTYP_136;
+ else if (cmd->resp_type & MMC_RSP_BUSY)
+ xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+ else if (cmd->resp_type & MMC_RSP_PRESENT)
+ xfertyp |= XFERTYP_RSPTYP_48;
+
+ return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
+}
+
+static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
+{
+ uint wml_value;
+ int timeout;
+ struct fsl_esdhc *regs = mmc->priv;
+
+ wml_value = data->blocksize/4;
+
+ if (data->flags & MMC_DATA_READ) {
+ if (wml_value > 0x10)
+ wml_value = 0x10;
+
+ wml_value = 0x100000 | wml_value;
+
+ out_be32(®s->dsaddr, (u32)data->dest);
+ } else {
+ if (wml_value > 0x80)
+ wml_value = 0x80;
+ if ((in_be32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+ return TIMEOUT;
+ }
+ wml_value = wml_value << 16 | 0x10;
+ out_be32(®s->dsaddr, (u32)data->src);
+ }
+
+ out_be32(®s->wml, wml_value);
+
+ out_be32(®s->blkattr, data->blocks << 16 | data->blocksize);
+
+ /* Calculate the timeout period for data transactions */
+ timeout = __ilog2(mmc->tran_speed/10);
+ timeout -= 13;
+
+ if (timeout > 14)
+ timeout = 14;
+
+ if (timeout < 0)
+ timeout = 0;
+
+ clrsetbits_be32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
+
+ return 0;
+}
+
+
+/*
+ * Sends a command out on the bus. Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int
+esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ uint xfertyp;
+ uint irqstat;
+ volatile struct fsl_esdhc *regs = mmc->priv;
+
+ out_be32(®s->irqstat, -1);
+
+ sync();
+
+ /* Wait for the bus to be idle */
+ while ((in_be32(®s->prsstat) & PRSSTAT_CICHB) ||
+ (in_be32(®s->prsstat) & PRSSTAT_CIDHB));
+
+ while (in_be32(®s->prsstat) & PRSSTAT_DLA);
+
+ /* Wait at least 8 SD clock cycles before the next command */
+ /*
+ * Note: This is way more than 8 cycles, but 1ms seems to
+ * resolve timing issues with some cards
+ */
+ udelay(1000);
+
+ /* Set up for a data transfer if we have one */
+ if (data) {
+ int err;
+
+ err = esdhc_setup_data(mmc, data);
+ if(err)
+ return err;
+ }
+
+ /* Figure out the transfer arguments */
+ xfertyp = esdhc_xfertyp(cmd, data);
+
+ /* Send the command */
+ out_be32(®s->cmdarg, cmd->cmdarg);
+ out_be32(®s->xfertyp, xfertyp);
+
+ /* Wait for the command to complete */
+ while (!(in_be32(®s->irqstat) & IRQSTAT_CC));
+
+ irqstat = in_be32(®s->irqstat);
+ out_be32(®s->irqstat, irqstat);
+
+ if (irqstat & CMD_ERR)
+ return COMM_ERR;
+
+ if (irqstat & IRQSTAT_CTOE)
+ return TIMEOUT;
+
+ /* Copy the response to the response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
+
+ cmdrsp3 = in_be32(®s->cmdrsp3);
+ cmdrsp2 = in_be32(®s->cmdrsp2);
+ cmdrsp1 = in_be32(®s->cmdrsp1);
+ cmdrsp0 = in_be32(®s->cmdrsp0);
+ ((uint *)(cmd->response))[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
+ ((uint *)(cmd->response))[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
+ ((uint *)(cmd->response))[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
+ ((uint *)(cmd->response))[3] = (cmdrsp0 << 8);
+ } else
+ ((uint *)(cmd->response))[0] = in_be32(®s->cmdrsp0);
+
+ /* Wait until all of the blocks are transferred */
+ if (data) {
+ do {
+ irqstat = in_be32(®s->irqstat);
+
+ if (irqstat & DATA_ERR)
+ return COMM_ERR;
+
+ if (irqstat & IRQSTAT_DTOE)
+ return TIMEOUT;
+ } while (!(irqstat & IRQSTAT_TC) &&
+ (in_be32(®s->prsstat) & PRSSTAT_DLA));
+ }
+
+ out_be32(®s->irqstat, -1);
+
+ return 0;
+}
+
+void set_sysctl(struct mmc *mmc, uint clock)
+{
+ int sdhc_clk = gd->sdhc_clk;
+ int div, pre_div;
+ volatile struct fsl_esdhc *regs = mmc->priv;
+ uint clk;
+
+ if (sdhc_clk / 16 > clock) {
+ for (pre_div = 2; pre_div < 256; pre_div *= 2)
+ if ((sdhc_clk / pre_div) <= (clock * 16))
+ break;
+ } else
+ pre_div = 2;
+
+ for (div = 1; div <= 16; div++)
+ if ((sdhc_clk / (div * pre_div)) <= clock)
+ break;
+
+ pre_div >>= 1;
+ div -= 1;
+
+ clk = (pre_div << 8) | (div << 4);
+
+ clrsetbits_be32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
+
+ udelay(10000);
+
+ setbits_be32(®s->sysctl, SYSCTL_PEREN);
+}
+
+static void esdhc_set_ios(struct mmc *mmc)
+{
+ struct fsl_esdhc *regs = mmc->priv;
+
+ /* Set the clock speed */
+ set_sysctl(mmc, mmc->clock);
+
+ /* Set the bus width */
+ clrbits_be32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
+
+ if (mmc->bus_width == 4)
+ setbits_be32(®s->proctl, PROCTL_DTW_4);
+ else if (mmc->bus_width == 8)
+ setbits_be32(®s->proctl, PROCTL_DTW_8);
+}
+
+static int esdhc_init(struct mmc *mmc)
+{
+ struct fsl_esdhc *regs = mmc->priv;
+ int timeout = 1000;
+
+ /* Enable cache snooping */
+ out_be32(®s->scr, 0x00000040);
+
+ out_be32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+
+ /* Set the initial clock speed */
+ set_sysctl(mmc, 400000);
+
+ /* Disable the BRR and BWR bits in IRQSTAT */
+ clrbits_be32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
+
+ /* Put the PROCTL reg back to the default */
+ out_be32(®s->proctl, PROCTL_INIT);
+
+ while (!(in_be32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
+ udelay(1000);
+
+ if (timeout <= 0)
+ return NO_CARD_ERR;
+
+ return 0;
+}
+
+static int esdhc_initialize(bd_t *bis)
+{
+ struct fsl_esdhc *regs = (struct fsl_esdhc *)CONFIG_SYS_FSL_ESDHC_ADDR;
+ struct mmc *mmc;
+ u32 caps;
+
+ mmc = malloc(sizeof(struct mmc));
+
+ sprintf(mmc->name, "FSL_ESDHC");
+ mmc->priv = regs;
+ mmc->send_cmd = esdhc_send_cmd;
+ mmc->set_ios = esdhc_set_ios;
+ mmc->init = esdhc_init;
+
+ caps = regs->hostcapblt;
+
+ if (caps & ESDHC_HOSTCAPBLT_VS18)
+ mmc->voltages |= MMC_VDD_165_195;
+ if (caps & ESDHC_HOSTCAPBLT_VS30)
+ mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+ if (caps & ESDHC_HOSTCAPBLT_VS33)
+ mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+
+ if (caps & ESDHC_HOSTCAPBLT_HSS)
+ mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ mmc->f_min = 400000;
+ mmc->f_max = MIN(gd->sdhc_clk, 50000000);
+
+ mmc_register(mmc);
+
+ return 0;
+}
+
+int fsl_esdhc_mmc_init(bd_t *bis)
+{
+ return esdhc_initialize(bis);
+}
--- /dev/null
+/*
+ * Copyright 2008, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the Linux code
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <mmc.h>
+#include <part.h>
+#include <malloc.h>
+#include <linux/list.h>
+#include <mmc.h>
+
+static struct list_head mmc_devices;
+static int cur_dev_num = -1;
+
+int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ return mmc->send_cmd(mmc, cmd, data);
+}
+
+int mmc_set_blocklen(struct mmc *mmc, int len)
+{
+ struct mmc_cmd cmd;
+
+ cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = len;
+ cmd.flags = 0;
+
+ return mmc_send_cmd(mmc, &cmd, NULL);
+}
+
+struct mmc *find_mmc_device(int dev_num)
+{
+ struct mmc *m;
+ struct list_head *entry;
+
+ list_for_each(entry, &mmc_devices) {
+ m = list_entry(entry, struct mmc, link);
+
+ if (m->block_dev.dev == dev_num)
+ return m;
+ }
+
+ printf("MMC Device %d not found\n", dev_num);
+
+ return NULL;
+}
+
+static ulong
+mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ int err;
+ int stoperr = 0;
+ struct mmc *mmc = find_mmc_device(dev_num);
+ int blklen;
+
+ if (!mmc)
+ return -1;
+
+ blklen = mmc->write_bl_len;
+
+ err = mmc_set_blocklen(mmc, mmc->write_bl_len);
+
+ if (err) {
+ printf("set write bl len failed\n\r");
+ return err;
+ }
+
+ if (blkcnt > 1)
+ cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+ else
+ cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
+
+ if (mmc->high_capacity)
+ cmd.cmdarg = start;
+ else
+ cmd.cmdarg = start * blklen;
+
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.flags = 0;
+
+ data.src = src;
+ data.blocks = blkcnt;
+ data.blocksize = blklen;
+ data.flags = MMC_DATA_WRITE;
+
+ err = mmc_send_cmd(mmc, &cmd, &data);
+
+ if (err) {
+ printf("mmc write failed\n\r");
+ return err;
+ }
+
+ if (blkcnt > 1) {
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.flags = 0;
+ stoperr = mmc_send_cmd(mmc, &cmd, NULL);
+ }
+
+ return blkcnt;
+}
+
+int mmc_read_block(struct mmc *mmc, void *dst, uint blocknum)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+
+ cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
+
+ if (mmc->high_capacity)
+ cmd.cmdarg = blocknum;
+ else
+ cmd.cmdarg = blocknum * mmc->read_bl_len;
+
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.flags = 0;
+
+ data.dest = dst;
+ data.blocks = 1;
+ data.blocksize = mmc->read_bl_len;
+ data.flags = MMC_DATA_READ;
+
+ return mmc_send_cmd(mmc, &cmd, &data);
+}
+
+int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size)
+{
+ char *buffer;
+ int i;
+ int blklen = mmc->read_bl_len;
+ int startblock = src / blklen;
+ int endblock = (src + size - 1) / blklen;
+ int err = 0;
+
+ /* Make a buffer big enough to hold all the blocks we might read */
+ buffer = malloc(blklen);
+
+ if (!buffer) {
+ printf("Could not allocate buffer for MMC read!\n");
+ return -1;
+ }
+
+ /* We always do full block reads from the card */
+ err = mmc_set_blocklen(mmc, mmc->read_bl_len);
+
+ if (err)
+ return err;
+
+ for (i = startblock; i <= endblock; i++) {
+ int segment_size;
+ int offset;
+
+ err = mmc_read_block(mmc, buffer, i);
+
+ if (err)
+ goto free_buffer;
+
+ /*
+ * The first block may not be aligned, so we
+ * copy from the desired point in the block
+ */
+ offset = (src & (blklen - 1));
+ segment_size = MIN(blklen - offset, size);
+
+ memcpy(dst, buffer + offset, segment_size);
+
+ dst += segment_size;
+ src += segment_size;
+ size -= segment_size;
+ }
+
+free_buffer:
+ free(buffer);
+
+ return err;
+}
+
+static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst)
+{
+ int err;
+ int i;
+ struct mmc *mmc = find_mmc_device(dev_num);
+
+ if (!mmc)
+ return 0;
+
+ /* We always do full block reads from the card */
+ err = mmc_set_blocklen(mmc, mmc->read_bl_len);
+
+ if (err) {
+ return 0;
+ }
+
+ for (i = start; i < start + blkcnt; i++, dst += mmc->read_bl_len) {
+ err = mmc_read_block(mmc, dst, i);
+
+ if (err) {
+ printf("block read failed: %d\n", err);
+ return i - start;
+ }
+ }
+
+ return blkcnt;
+}
+
+int mmc_go_idle(struct mmc* mmc)
+{
+ struct mmc_cmd cmd;
+ int err;
+
+ udelay(1000);
+
+ cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_NONE;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ udelay(2000);
+
+ return 0;
+}
+
+int
+sd_send_op_cond(struct mmc *mmc)
+{
+ int timeout = 1000;
+ int err;
+ struct mmc_cmd cmd;
+
+ do {
+ cmd.cmdidx = MMC_CMD_APP_CMD;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
+ cmd.resp_type = MMC_RSP_R3;
+ cmd.cmdarg = mmc->voltages;
+
+ if (mmc->version == SD_VERSION_2)
+ cmd.cmdarg |= OCR_HCS;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ udelay(1000);
+ } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
+
+ if (timeout <= 0)
+ return UNUSABLE_ERR;
+
+ if (mmc->version != SD_VERSION_2)
+ mmc->version = SD_VERSION_1_0;
+
+ mmc->ocr = ((uint *)(cmd.response))[0];
+
+ mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
+ mmc->rca = 0;
+
+ return 0;
+}
+
+int mmc_send_op_cond(struct mmc *mmc)
+{
+ int timeout = 1000;
+ struct mmc_cmd cmd;
+ int err;
+
+ /* Some cards seem to need this */
+ mmc_go_idle(mmc);
+
+ do {
+ cmd.cmdidx = MMC_CMD_SEND_OP_COND;
+ cmd.resp_type = MMC_RSP_R3;
+ cmd.cmdarg = OCR_HCS | mmc->voltages;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ udelay(1000);
+ } while (!(cmd.response[0] & OCR_BUSY) && timeout--);
+
+ if (timeout <= 0)
+ return UNUSABLE_ERR;
+
+ mmc->version = MMC_VERSION_UNKNOWN;
+ mmc->ocr = ((uint *)(cmd.response))[0];
+
+ mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
+ mmc->rca = 0;
+
+ return 0;
+}
+
+
+int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ int err;
+
+ /* Get the Card Status Register */
+ cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+ cmd.flags = 0;
+
+ data.dest = ext_csd;
+ data.blocks = 1;
+ data.blocksize = 512;
+ data.flags = MMC_DATA_READ;
+
+ err = mmc_send_cmd(mmc, &cmd, &data);
+
+ return err;
+}
+
+
+int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
+{
+ struct mmc_cmd cmd;
+
+ cmd.cmdidx = MMC_CMD_SWITCH;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
+ (index << 16) |
+ (value << 8);
+ cmd.flags = 0;
+
+ return mmc_send_cmd(mmc, &cmd, NULL);
+}
+
+int mmc_change_freq(struct mmc *mmc)
+{
+ char ext_csd[512];
+ char cardtype;
+ int err;
+
+ mmc->card_caps = 0;
+
+ /* Only version 4 supports high-speed */
+ if (mmc->version < MMC_VERSION_4)
+ return 0;
+
+ mmc->card_caps |= MMC_MODE_4BIT;
+
+ err = mmc_send_ext_csd(mmc, ext_csd);
+
+ if (err)
+ return err;
+
+ if (ext_csd[212] || ext_csd[213] || ext_csd[214] || ext_csd[215])
+ mmc->high_capacity = 1;
+
+ cardtype = ext_csd[196] & 0xf;
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+
+ if (err)
+ return err;
+
+ /* Now check to see that it worked */
+ err = mmc_send_ext_csd(mmc, ext_csd);
+
+ if (err)
+ return err;
+
+ /* No high-speed support */
+ if (!ext_csd[185])
+ return 0;
+
+ /* High Speed is set, there are two types: 52MHz and 26MHz */
+ if (cardtype & MMC_HS_52MHZ)
+ mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ else
+ mmc->card_caps |= MMC_MODE_HS;
+
+ return 0;
+}
+
+int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+
+ /* Switch the frequency */
+ cmd.cmdidx = SD_CMD_SWITCH_FUNC;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = (mode << 31) | 0xffffff;
+ cmd.cmdarg &= ~(0xf << (group * 4));
+ cmd.cmdarg |= value << (group * 4);
+ cmd.flags = 0;
+
+ data.dest = (char *)resp;
+ data.blocksize = 64;
+ data.blocks = 1;
+ data.flags = MMC_DATA_READ;
+
+ return mmc_send_cmd(mmc, &cmd, &data);
+}
+
+
+int sd_change_freq(struct mmc *mmc)
+{
+ int err;
+ struct mmc_cmd cmd;
+ uint scr[2];
+ uint switch_status[16];
+ struct mmc_data data;
+ int timeout;
+
+ mmc->card_caps = 0;
+
+ /* Read the SCR to find out if this card supports higher speeds */
+ cmd.cmdidx = MMC_CMD_APP_CMD;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = mmc->rca << 16;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ cmd.cmdidx = SD_CMD_APP_SEND_SCR;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+ cmd.flags = 0;
+
+ timeout = 3;
+
+retry_scr:
+ data.dest = (char *)&scr;
+ data.blocksize = 8;
+ data.blocks = 1;
+ data.flags = MMC_DATA_READ;
+
+ err = mmc_send_cmd(mmc, &cmd, &data);
+
+ if (err) {
+ if (timeout--)
+ goto retry_scr;
+
+ return err;
+ }
+
+ mmc->scr[0] = scr[0];
+ mmc->scr[1] = scr[1];
+
+ switch ((mmc->scr[0] >> 24) & 0xf) {
+ case 0:
+ mmc->version = SD_VERSION_1_0;
+ break;
+ case 1:
+ mmc->version = SD_VERSION_1_10;
+ break;
+ case 2:
+ mmc->version = SD_VERSION_2;
+ break;
+ default:
+ mmc->version = SD_VERSION_1_0;
+ break;
+ }
+
+ /* Version 1.0 doesn't support switching */
+ if (mmc->version == SD_VERSION_1_0)
+ return 0;
+
+ timeout = 4;
+ while (timeout--) {
+ err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
+ (u8 *)&switch_status);
+
+ if (err)
+ return err;
+
+ /* The high-speed function is busy. Try again */
+ if (!switch_status[7] & SD_HIGHSPEED_BUSY)
+ break;
+ }
+
+ if (mmc->scr[0] & SD_DATA_4BIT)
+ mmc->card_caps |= MMC_MODE_4BIT;
+
+ /* If high-speed isn't supported, we return */
+ if (!(switch_status[3] & SD_HIGHSPEED_SUPPORTED))
+ return 0;
+
+ err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)&switch_status);
+
+ if (err)
+ return err;
+
+ if ((switch_status[4] & 0x0f000000) == 0x01000000)
+ mmc->card_caps |= MMC_MODE_HS;
+
+ return 0;
+}
+
+/* frequency bases */
+/* divided by 10 to be nice to platforms without floating point */
+int fbase[] = {
+ 10000,
+ 100000,
+ 1000000,
+ 10000000,
+};
+
+/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
+ * to platforms without floating point.
+ */
+int multipliers[] = {
+ 0, /* reserved */
+ 10,
+ 12,
+ 13,
+ 15,
+ 20,
+ 25,
+ 30,
+ 35,
+ 40,
+ 45,
+ 50,
+ 55,
+ 60,
+ 70,
+ 80,
+};
+
+void mmc_set_ios(struct mmc *mmc)
+{
+ mmc->set_ios(mmc);
+}
+
+void mmc_set_clock(struct mmc *mmc, uint clock)
+{
+ if (clock > mmc->f_max)
+ clock = mmc->f_max;
+
+ if (clock < mmc->f_min)
+ clock = mmc->f_min;
+
+ mmc->clock = clock;
+
+ mmc_set_ios(mmc);
+}
+
+void mmc_set_bus_width(struct mmc *mmc, uint width)
+{
+ mmc->bus_width = width;
+
+ mmc_set_ios(mmc);
+}
+
+int mmc_startup(struct mmc *mmc)
+{
+ int err;
+ uint mult, freq;
+ u64 cmult, csize;
+ struct mmc_cmd cmd;
+
+ /* Put the Card in Identify Mode */
+ cmd.cmdidx = MMC_CMD_ALL_SEND_CID;
+ cmd.resp_type = MMC_RSP_R2;
+ cmd.cmdarg = 0;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ memcpy(mmc->cid, cmd.response, 16);
+
+ /*
+ * For MMC cards, set the Relative Address.
+ * For SD cards, get the Relatvie Address.
+ * This also puts the cards into Standby State
+ */
+ cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
+ cmd.cmdarg = mmc->rca << 16;
+ cmd.resp_type = MMC_RSP_R6;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ if (IS_SD(mmc))
+ mmc->rca = (((uint *)(cmd.response))[0] >> 16) & 0xffff;
+
+ /* Get the Card-Specific Data */
+ cmd.cmdidx = MMC_CMD_SEND_CSD;
+ cmd.resp_type = MMC_RSP_R2;
+ cmd.cmdarg = mmc->rca << 16;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ mmc->csd[0] = ((uint *)(cmd.response))[0];
+ mmc->csd[1] = ((uint *)(cmd.response))[1];
+ mmc->csd[2] = ((uint *)(cmd.response))[2];
+ mmc->csd[3] = ((uint *)(cmd.response))[3];
+
+ if (mmc->version == MMC_VERSION_UNKNOWN) {
+ int version = (cmd.response[0] >> 2) & 0xf;
+
+ switch (version) {
+ case 0:
+ mmc->version = MMC_VERSION_1_2;
+ break;
+ case 1:
+ mmc->version = MMC_VERSION_1_4;
+ break;
+ case 2:
+ mmc->version = MMC_VERSION_2_2;
+ break;
+ case 3:
+ mmc->version = MMC_VERSION_3;
+ break;
+ case 4:
+ mmc->version = MMC_VERSION_4;
+ break;
+ default:
+ mmc->version = MMC_VERSION_1_2;
+ break;
+ }
+ }
+
+ /* divide frequency by 10, since the mults are 10x bigger */
+ freq = fbase[(cmd.response[3] & 0x7)];
+ mult = multipliers[((cmd.response[3] >> 3) & 0xf)];
+
+ mmc->tran_speed = freq * mult;
+
+ mmc->read_bl_len = 1 << ((((uint *)(cmd.response))[1] >> 16) & 0xf);
+
+ if (IS_SD(mmc))
+ mmc->write_bl_len = mmc->read_bl_len;
+ else
+ mmc->write_bl_len = 1 << ((((uint *)(cmd.response))[3] >> 22) & 0xf);
+
+ if (mmc->high_capacity) {
+ csize = (mmc->csd[1] & 0x3f) << 16
+ | (mmc->csd[2] & 0xffff0000) >> 16;
+ cmult = 8;
+ } else {
+ csize = (mmc->csd[1] & 0x3ff) << 2
+ | (mmc->csd[2] & 0xc0000000) >> 30;
+ cmult = (mmc->csd[2] & 0x00038000) >> 15;
+ }
+
+ mmc->capacity = (csize + 1) << (cmult + 2);
+ mmc->capacity *= mmc->read_bl_len;
+
+ if (mmc->read_bl_len > 512)
+ mmc->read_bl_len = 512;
+
+ if (mmc->write_bl_len > 512)
+ mmc->write_bl_len = 512;
+
+ /* Select the card, and put it into Transfer Mode */
+ cmd.cmdidx = MMC_CMD_SELECT_CARD;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = mmc->rca << 16;
+ cmd.flags = 0;
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ if (IS_SD(mmc))
+ err = sd_change_freq(mmc);
+ else
+ err = mmc_change_freq(mmc);
+
+ if (err)
+ return err;
+
+ /* Restrict card's capabilities by what the host can do */
+ mmc->card_caps &= mmc->host_caps;
+
+ if (IS_SD(mmc)) {
+ if (mmc->card_caps & MMC_MODE_4BIT) {
+ cmd.cmdidx = MMC_CMD_APP_CMD;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = mmc->rca << 16;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+
+ cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 2;
+ cmd.flags = 0;
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+
+ mmc_set_bus_width(mmc, 4);
+ }
+
+ if (mmc->card_caps & MMC_MODE_HS)
+ mmc_set_clock(mmc, 50000000);
+ else
+ mmc_set_clock(mmc, 25000000);
+ } else {
+ if (mmc->card_caps & MMC_MODE_4BIT) {
+ /* Set the card to use 4 bit*/
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH,
+ EXT_CSD_BUS_WIDTH_4);
+
+ if (err)
+ return err;
+
+ mmc_set_bus_width(mmc, 4);
+ } else if (mmc->card_caps & MMC_MODE_8BIT) {
+ /* Set the card to use 8 bit*/
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH,
+ EXT_CSD_BUS_WIDTH_8);
+
+ if (err)
+ return err;
+
+ mmc_set_bus_width(mmc, 8);
+ }
+
+ if (mmc->card_caps & MMC_MODE_HS) {
+ if (mmc->card_caps & MMC_MODE_HS_52MHz)
+ mmc_set_clock(mmc, 52000000);
+ else
+ mmc_set_clock(mmc, 26000000);
+ } else
+ mmc_set_clock(mmc, 20000000);
+ }
+
+ /* fill in device description */
+ mmc->block_dev.lun = 0;
+ mmc->block_dev.type = 0;
+ mmc->block_dev.blksz = mmc->read_bl_len;
+ mmc->block_dev.lba = mmc->capacity/mmc->read_bl_len;
+ sprintf(mmc->block_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x%02x",
+ mmc->cid[0], mmc->cid[1], mmc->cid[2],
+ mmc->cid[9], mmc->cid[10], mmc->cid[11], mmc->cid[12]);
+ sprintf(mmc->block_dev.product,"%c%c%c%c%c", mmc->cid[3],
+ mmc->cid[4], mmc->cid[5], mmc->cid[6], mmc->cid[7]);
+ sprintf(mmc->block_dev.revision,"%d.%d", mmc->cid[8] >> 4,
+ mmc->cid[8] & 0xf);
+ init_part(&mmc->block_dev);
+
+ return 0;
+}
+
+int mmc_send_if_cond(struct mmc *mmc)
+{
+ struct mmc_cmd cmd;
+ int err;
+
+ cmd.cmdidx = SD_CMD_SEND_IF_COND;
+ /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
+ cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa;
+ cmd.resp_type = MMC_RSP_R7;
+ cmd.flags = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ if ((((uint *)(cmd.response))[0] & 0xff) != 0xaa)
+ return UNUSABLE_ERR;
+ else
+ mmc->version = SD_VERSION_2;
+
+ return 0;
+}
+
+int mmc_register(struct mmc *mmc)
+{
+ /* Setup the universal parts of the block interface just once */
+ mmc->block_dev.if_type = IF_TYPE_MMC;
+ mmc->block_dev.dev = cur_dev_num++;
+ mmc->block_dev.removable = 1;
+ mmc->block_dev.block_read = mmc_bread;
+ mmc->block_dev.block_write = mmc_bwrite;
+
+ INIT_LIST_HEAD (&mmc->link);
+
+ list_add_tail (&mmc->link, &mmc_devices);
+
+ return 0;
+}
+
+block_dev_desc_t *mmc_get_dev(int dev)
+{
+ struct mmc *mmc = find_mmc_device(dev);
+
+ return &mmc->block_dev;
+}
+
+int mmc_init(struct mmc *mmc)
+{
+ int err;
+
+ err = mmc->init(mmc);
+
+ if (err)
+ return err;
+
+ /* Reset the Card */
+ err = mmc_go_idle(mmc);
+
+ if (err)
+ return err;
+
+ /* Test for SD version 2 */
+ err = mmc_send_if_cond(mmc);
+
+ /* If we got an error other than timeout, we bail */
+ if (err && err != TIMEOUT)
+ return err;
+
+ /* Now try to get the SD card's operating condition */
+ err = sd_send_op_cond(mmc);
+
+ /* If the command timed out, we check for an MMC card */
+ if (err == TIMEOUT) {
+ err = mmc_send_op_cond(mmc);
+
+ if (err) {
+ printf("Card did not respond to voltage select!\n");
+ return UNUSABLE_ERR;
+ }
+ }
+
+ return mmc_startup(mmc);
+}
+
+/*
+ * CPU and board-specific MMC initializations. Aliased function
+ * signals caller to move on
+ */
+static int __def_mmc_init(bd_t *bis)
+{
+ return -1;
+}
+
+int cpu_mmc_init(bd_t *bis) __attribute((weak, alias("__def_mmc_init")));
+int board_mmc_init(bd_t *bis) __attribute((weak, alias("__def_mmc_init")));
+
+void print_mmc_devices(char separator)
+{
+ struct mmc *m;
+ struct list_head *entry;
+
+ list_for_each(entry, &mmc_devices) {
+ m = list_entry(entry, struct mmc, link);
+
+ printf("%s: %d", m->name, m->block_dev.dev);
+
+ if (entry->next != &mmc_devices)
+ printf("%c ", separator);
+ }
+
+ printf("\n");
+}
+
+int mmc_initialize(bd_t *bis)
+{
+ INIT_LIST_HEAD (&mmc_devices);
+ cur_dev_num = 0;
+
+ if (board_mmc_init(bis) < 0)
+ cpu_mmc_init(bis);
+
+ print_mmc_devices(',');
+
+ return 0;
+}
/*-----------------------------------------------------------------------
*/
#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
-static flash_info_t *flash_get_info(ulong base)
+flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info = 0;
{
unsigned int byte_offset = offset * info->portwidth;
- return map_physmem(info->start[sect] + byte_offset,
- flash_sector_size(info, sect) - byte_offset,
- MAP_NOCACHE);
+ return (void *)(info->start[sect] + byte_offset);
}
static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
unsigned int offset, void *addr)
{
- unsigned int byte_offset = offset * info->portwidth;
-
- unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset);
}
/*-----------------------------------------------------------------------
int i;
char *cp;
- cp = (unsigned char *) &data;
+ cp = (char *) &data;
for (i = 0; i < 8; i++)
sprintf (&str[i * 2], "%2.2x", *cp++);
}
static int flash_write_cfiword (flash_info_t * info, ulong dest,
cfiword_t cword)
{
- void *dstaddr;
+ void *dstaddr = (void *)dest;
int flag;
flash_sect_t sect = 0;
char sect_found = 0;
- dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE);
-
/* Check if Flash is (sufficiently) erased */
switch (info->portwidth) {
case FLASH_CFI_8BIT:
flag = 0;
break;
}
- if (!flag) {
- unmap_physmem(dstaddr, info->portwidth);
+ if (!flag)
return ERR_NOT_ERASED;
- }
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
if (flag)
enable_interrupts ();
- unmap_physmem(dstaddr, info->portwidth);
-
if (!sect_found)
sect = find_sector (info, dest);
int cnt;
int retcode;
void *src = cp;
- void *dst = map_physmem(dest, len, MAP_NOCACHE);
+ void *dst = (void *)dest;
void *dst2 = dst;
int flag = 0;
uint offset = 0;
}
out_unmap:
- unmap_physmem(dst, len);
return retcode;
}
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
/* handle unaligned start */
if ((aln = addr - wp) != 0) {
cword.l = 0;
- p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
+ p = (uchar *)wp;
for (i = 0; i < aln; ++i)
flash_add_byte (info, &cword, flash_read8(p + i));
flash_add_byte (info, &cword, flash_read8(p + i));
rc = flash_write_cfiword (info, wp, cword);
- unmap_physmem(p, info->portwidth);
if (rc != 0)
return rc;
* handle unaligned tail bytes
*/
cword.l = 0;
- p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
+ p = (uchar *)wp;
for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
flash_add_byte (info, &cword, *src++);
--cnt;
}
for (; i < info->portwidth; ++i)
flash_add_byte (info, &cword, flash_read8(p + i));
- unmap_physmem(p, info->portwidth);
return flash_write_cfiword (info, wp, cword);
}
* board_flash_get_legacy needs to fill in at least:
* info->portwidth, info->chipwidth and info->interface for Jedec probing.
*/
-static int flash_detect_legacy(ulong base, int banknum)
+static int flash_detect_legacy(phys_addr_t base, int banknum)
{
flash_info_t *info = &flash_info[banknum];
for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
info->vendor = modes[i];
- info->start[0] = base;
+ info->start[0] =
+ (ulong)map_physmem(base,
+ info->portwidth,
+ MAP_NOCACHE);
if (info->portwidth == FLASH_CFI_8BIT
&& info->interface == FLASH_CFI_X8X16) {
info->addr_unlock1 = 0x2AAA;
info->manufacturer_id,
info->device_id,
info->device_id2);
- if (jedec_flash_match(info, base))
+ if (jedec_flash_match(info, info->start[0]))
break;
+ else
+ unmap_physmem((void *)info->start[0],
+ MAP_NOCACHE);
}
}
return 0; /* use CFI */
}
#else
-static inline int flash_detect_legacy(ulong base, int banknum)
+static inline int flash_detect_legacy(phys_addr_t base, int banknum)
{
return 0; /* use CFI */
}
* The following code cannot be run from FLASH!
*
*/
-ulong flash_get_size (ulong base, int banknum)
+ulong flash_get_size (phys_addr_t base, int banknum)
{
flash_info_t *info = &flash_info[banknum];
int i, j;
flash_sect_t sect_cnt;
- unsigned long sector;
+ phys_addr_t sector;
unsigned long tmp;
int size_ratio;
uchar num_erase_regions;
info->legacy_unlock = 0;
#endif
- info->start[0] = base;
+ info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
if (flash_detect_cfi (info, &qry)) {
info->vendor = le16_to_cpu(qry.p_id);
printf("ERROR: too many flash sectors\n");
break;
}
- info->start[sect_cnt] = sector;
+ info->start[sect_cnt] =
+ (ulong)map_physmem(sector,
+ info->portwidth,
+ MAP_NOCACHE);
sector += (erase_region_size * size_ratio);
/*
char *s = getenv("unlock");
#endif
-#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i])
+#define BANK_BASE(i) (((phys_addr_t [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i])
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
#define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
-/* Manufacturers */
-#define MANUFACTURER_AMD 0x0001
-#define MANUFACTURER_SST 0x00BF
-
/* AMD */
#define AM29DL800BB 0x22CB
#define AM29DL800BT 0x224A
static const struct amd_flash_info jedec_table[] = {
#ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
{
- .mfr_id = MANUFACTURER_SST,
+ .mfr_id = (u16)SST_MANUFACT,
.dev_id = SST39LF020,
.name = "SST 39LF020",
.uaddr = {
#endif
#ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
{
- .mfr_id = MANUFACTURER_AMD,
+ .mfr_id = (u16)AMD_MANUFACT,
.dev_id = AM29LV040B,
.name = "AMD AM29LV040B",
.uaddr = {
}
},
{
- .mfr_id = MANUFACTURER_SST,
+ .mfr_id = (u16)SST_MANUFACT,
.dev_id = SST39LF040,
.name = "SST 39LF040",
.uaddr = {
}
},
{
- .mfr_id = STM_MANUFACT,
+ .mfr_id = (u16)STM_MANUFACT,
.dev_id = STM_ID_M29W040B,
.name = "ST Micro M29W040B",
.uaddr = {
#endif
#ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
{
- .mfr_id = MANUFACTURER_AMD,
+ .mfr_id = (u16)AMD_MANUFACT,
.dev_id = AM29LV400BB,
.name = "AMD AM29LV400BB",
.uaddr = {
}
},
{
- .mfr_id = MANUFACTURER_AMD,
+ .mfr_id = (u16)AMD_MANUFACT,
.dev_id = AM29LV800BB,
.name = "AMD AM29LV800BB",
.uaddr = {
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
int nand_curr_device = -1;
nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
if (nand_scan(mtd, 1) == 0) {
if (!mtd->name)
mtd->name = (char *)default_nand_name;
+ else
+ mtd->name += gd->reloc_off;
} else
mtd->name = NULL;
} else {
#include <jffs2/jffs2.h>
#endif
+/*
+ * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
+ * a flash. NAND flash is initialized prior to interrupts so standard timers
+ * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
+ * which is greater than (max NAND reset time / NAND status read time).
+ * A conservative default of 200000 (500 us / 25 ns) is used as a default.
+ */
+#ifndef CONFIG_SYS_NAND_RESET_CNT
+#define CONFIG_SYS_NAND_RESET_CNT 200000
+#endif
+
/* Define default oob placement schemes for large and small page devices */
static struct nand_ecclayout nand_oob_8 = {
.eccbytes = 3,
{
register struct nand_chip *chip = mtd->priv;
int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
+ uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
/*
* Write out the command to the device.
NAND_CTRL_CLE | NAND_CTRL_CHANGE);
chip->cmd_ctrl(mtd,
NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
+ while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
+ (rst_sts_cnt--));
return;
/* This applies to read commands */
int column, int page_addr)
{
register struct nand_chip *chip = mtd->priv;
+ uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
/* Emulate NAND_CMD_READOOB */
if (command == NAND_CMD_READOOB) {
NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
chip->cmd_ctrl(mtd, NAND_CMD_NONE,
NAND_NCE | NAND_CTRL_CHANGE);
- while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
+ while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
+ (rst_sts_cnt--));
return;
case NAND_CMD_RNDOUT:
type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
if (IS_ERR(type)) {
+#ifndef CONFIG_SYS_NAND_QUIET_TEST
printk(KERN_WARNING "No NAND device found!!!\n");
+#endif
chip->select_chip(mtd, -1);
return PTR_ERR(type);
}
volatile FEC_T *fecp;
struct eth_device *dev;
int miispd = 0, i = 0;
- u16 autoneg = 0;
+ u16 status = 0;
+ u16 linkgood = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info->phy_addr = mii_discover_phy(dev);
-#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
- autoneg = 0;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+ status = 0;
i++;
-
- if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+ /* Read PHY control register */
+ miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &status);
+
+ /* If phy set to autonegotiate, wait for autonegotiation done,
+ * if phy is not autonegotiating, just wait for link up.
+ */
+ if ((status & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
+ linkgood = (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS);
+ } else {
+ linkgood = PHY_BMSR_LS;
+ }
+ /* Read PHY status register */
+ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &status);
+ if ((status & linkgood) == linkgood)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
- printf("Auto Negotiation not complete\n");
+ printf("Link UP timeout\n");
}
- /* adapt to the half/full speed settings */
+ /* adapt to the duplex and speed settings of the phy */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/* #define DEBUG 0x28 */
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
- defined(CONFIG_MPC5xxx_FEC)
-
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_CANMB) || \
- defined(CONFIG_CM5200) || \
- defined(CONFIG_HMI1001) || \
- defined(CONFIG_ICECUBE) || \
- defined(CONFIG_INKA4X0) || \
- defined(CONFIG_JUPITER) || \
- defined(CONFIG_MCC200) || \
- defined(CONFIG_MOTIONPRO) || \
- defined(CONFIG_MUCMC52) || \
- defined(CONFIG_O2DNT) || \
- defined(CONFIG_PM520) || \
- defined(CONFIG_TOP5200) || \
- defined(CONFIG_TQM5200) || \
- defined(CONFIG_UC101) || \
- defined(CONFIG_V38B) || \
- defined(CONFIG_MUNICES)
-# ifndef CONFIG_FEC_10MBIT
+#if defined(CONFIG_MPC5xxx_FEC_MII100)
fec->xcv_type = MII100;
-# else
+#elif defined(CONFIG_MPC5xxx_FEC_MII10)
fec->xcv_type = MII10;
-# endif
-#elif defined(CONFIG_TOTAL5200)
+#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
fec->xcv_type = SEVENWIRE;
#else
#error fec->xcv_type not initialized.
/**/ return crc;
}
#endif /* DEBUG */
-
-#endif /* CONFIG_MPC5xxx_FEC */
/* GECMR */
enum GECMR_BIT {
- GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00,
+ GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
};
/* EDRRR*/
/* Reset the MAC */
priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
+ udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci_set_region(r++, bus_start, phys_start, pci_sz,
- PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
sz -= pci_sz;
debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci_set_region(r++, bus_start, phys_start, pci_sz,
- PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
sz -= pci_sz;
bus_start += pci_sz;
CONFIG_SYS_PCI64_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
pci_sz,
- PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
#else
pci_sz = 1ull << __ilog2_u64(sz);
debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci_set_region(r++, bus_start, phys_start, pci_sz,
- PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
sz -= pci_sz;
bus_start += pci_sz;
for (r=0; r<hose->region_count; r++) {
u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
- if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
+ if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
u32 flag = PIWAR_EN | PIWAR_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
pi->pitar = (hose->regions[r].phys_start >> 12);
PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
+/* Get a virtual address associated with a BAR region */
+void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
+{
+ pci_addr_t pci_bus_addr;
+ u32 bar_response;
+
+ /* read BAR address */
+ pci_read_config_dword(pdev, bar, &bar_response);
+ pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+
+ /*
+ * Pass "0" as the length argument to pci_bus_to_virt. The arg
+ * isn't actualy used on any platform because u-boot assumes a static
+ * linear mapping. In the future, this could read the BAR size
+ * and pass that as the size if needed.
+ */
+ return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
+}
+
/*
*
*/
*
*/
-pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
- phys_addr_t phys_addr,
- unsigned long flags)
+int __pci_hose_phys_to_bus (struct pci_controller *hose,
+ phys_addr_t phys_addr,
+ unsigned long flags,
+ unsigned long skip_mask,
+ pci_addr_t *ba)
{
struct pci_region *res;
pci_addr_t bus_addr;
int i;
- if (!hose) {
- printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
- goto Done;
- }
-
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
continue;
+ if (res->flags & skip_mask)
+ continue;
+
bus_addr = phys_addr - res->phys_start + res->bus_start;
if (bus_addr >= res->bus_start &&
bus_addr < res->bus_start + res->size) {
- return bus_addr;
+ *ba = bus_addr;
+ return 0;
}
}
- printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
-
-Done:
- return 0;
+ return 1;
}
-phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
- pci_addr_t bus_addr,
- unsigned long flags)
+pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
+ phys_addr_t phys_addr,
+ unsigned long flags)
{
- struct pci_region *res;
- int i;
+ pci_addr_t bus_addr = 0;
+ int ret;
if (!hose) {
- printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
- goto Done;
+ puts ("pci_hose_phys_to_bus: invalid hose\n");
+ return bus_addr;
}
+ /* if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set */
+ if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
+ ret = __pci_hose_phys_to_bus(hose, phys_addr,
+ flags, PCI_REGION_SYS_MEMORY, &bus_addr);
+ if (!ret)
+ return bus_addr;
+ }
+
+ ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
+
+ if (ret)
+ puts ("pci_hose_phys_to_bus: invalid physical address\n");
+
+ return bus_addr;
+}
+
+int __pci_hose_bus_to_phys (struct pci_controller *hose,
+ pci_addr_t bus_addr,
+ unsigned long flags,
+ unsigned long skip_mask,
+ phys_addr_t *pa)
+{
+ struct pci_region *res;
+ int i;
+
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
continue;
+ if (res->flags & skip_mask)
+ continue;
+
if (bus_addr >= res->bus_start &&
bus_addr < res->bus_start + res->size) {
- return bus_addr - res->bus_start + res->phys_start;
+ *pa = (bus_addr - res->bus_start + res->phys_start);
+ return 0;
}
}
- printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
+ return 1;
+}
-Done:
- return 0;
+phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
+ pci_addr_t bus_addr,
+ unsigned long flags)
+{
+ phys_addr_t phys_addr = 0;
+ int ret;
+
+ if (!hose) {
+ puts ("pci_hose_bus_to_phys: invalid hose\n");
+ return phys_addr;
+ }
+
+ /* if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set */
+ if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
+ ret = __pci_hose_bus_to_phys(hose, bus_addr,
+ flags, PCI_REGION_SYS_MEMORY, &phys_addr);
+ if (!ret)
+ return phys_addr;
+ }
+
+ ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
+
+ if (ret)
+ puts ("pci_hose_bus_to_phys: invalid physical address\n");
+
+ return phys_addr;
}
/*
/* System memory space */
pci_set_region (hose->regions + 0,
PCI_MEMORY_BUS,
- PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY);
+ PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region (hose->regions + 1,
pci_set_region (hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
+ CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region (hose->regions + 1,
LIB := $(obj)libpcmcia.a
COBJS-$(CONFIG_I82365) += i82365.o
-COBJS-y += mpc8xx_pcmcia.o
+COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o
COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o
COBJS-y += rpx_pcmcia.o
COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
#include <common.h>
-#if defined(CONFIG_8xx)
#include <mpc8xx.h>
-#endif
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#define CONFIG_PCMCIA
#endif
-#if defined(CONFIG_8xx) && defined(CONFIG_PCMCIA)
+#if defined(CONFIG_PCMCIA)
#if defined(CONFIG_IDE_8xx_PCCARD)
extern int check_ide_device (int slot);
}
#endif /* 0 */
-#endif /* CONFIG_8xx && CONFIG_PCMCIA */
+#endif /* CONFIG_PCMCIA */
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
u32 counter;
- counter = ((gd->bus_clk / gd->baudrate)) >> 5;
- counter++;
+ /* Setting up BaudRate */
+ counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
+ counter = counter / gd->baudrate;
/* write to CTUR: divide counter upper byte */
uart->ubg1 = ((counter & 0xff00) >> 8);
#endif
}
+#ifndef CONFIG_NS16550_MIN_FUNCTIONS
void NS16550_reinit (NS16550_t com_port, int baud_divisor)
{
com_port->ier = 0x00;
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCRVAL;
}
+#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
void NS16550_putc (NS16550_t com_port, char c)
{
com_port->thr = c;
}
+#ifndef CONFIG_NS16550_MIN_FUNCTIONS
char NS16550_getc (NS16550_t com_port)
{
while ((com_port->lsr & LSR_DR) == 0) {
return ((com_port->lsr & LSR_DR) != 0);
}
+#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
#endif
/* Slave Interface */
struct usb_interface_descriptor data_class_interface;
- struct usb_endpoint_descriptor
- data_endpoints[NUM_ENDPOINTS-1] __attribute__((packed));
+ struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS-1];
} __attribute__((packed));
static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
struct gserial_config_desc {
struct usb_configuration_descriptor configuration_desc;
- struct usb_interface_descriptor
- interface_desc[NUM_GSERIAL_INTERFACES] __attribute__((packed));
- struct usb_endpoint_descriptor
- data_endpoints[NUM_ENDPOINTS] __attribute__((packed));
+ struct usb_interface_descriptor interface_desc[NUM_GSERIAL_INTERFACES];
+ struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS];
} __attribute__((packed));
*/
void usbtty_putc (const char c)
{
+ if (!usbtty_configured ())
+ return;
+
buf_push (&usbtty_output, &c, 1);
/* If \n, also do \r */
if (c == '\n')
void usbtty_puts (const char *str)
{
int n;
- int len = strlen (str);
+ int len;
+
+ if (!usbtty_configured ())
+ return;
+ len = strlen (str);
/* add '\r' for each '\n' */
while (len > 0) {
n = next_nl_pos (str);
extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
extern void enable_vbus(void);
#endif /* __DAVINCI_USB_H__ */
-
extern inline u8 musb_readb(u32 offset);
#endif /* __MUSB_HDRC_DEFS_H__ */
-
/* Start the host controller. */
cmd = ehci_readl(&hcor->or_usbcmd);
- /* Philips, Intel, and maybe others need CMD_RUN before the
- * root hub will detect new devices (why?); NEC doesn't */
+ /*
+ * Philips, Intel, and maybe others need CMD_RUN before the
+ * root hub will detect new devices (why?); NEC doesn't
+ */
cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
cmd |= CMD_RUN;
ehci_writel(&hcor->or_usbcmd, cmd);
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-/*----------------------------------------------------------------
- * BAT settings. Look in config_<BOARD>.h for the actual setup
- */
-
-#define BATU_BL_128K 0x00000000
-#define BATU_BL_256K 0x00000004
-#define BATU_BL_512K 0x0000000c
-#define BATU_BL_1M 0x0000001c
-#define BATU_BL_2M 0x0000003c
-#define BATU_BL_4M 0x0000007c
-#define BATU_BL_8M 0x000000fc
-#define BATU_BL_16M 0x000001fc
-#define BATU_BL_32M 0x000003fc
-#define BATU_BL_64M 0x000007fc
-#define BATU_BL_128M 0x00000ffc
-#define BATU_BL_256M 0x00001ffc
-
-#define BATU_VS 0x00000002
-#define BATU_VP 0x00000001
-#define BATU_INVALID 0x00000000
-
-#define BATL_WRITETHROUGH 0x00000040
-#define BATL_CACHEINHIBIT 0x00000020
-#define BATL_MEMCOHERENCE 0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
-#define BATL_NO_ACCESS 0x00000000
-
-#define BATL_PP_MSK 0x00000003
-#define BATL_PP_00 0x00000000 /* No access */
-#define BATL_PP_01 0x00000001 /* Read-only */
-#define BATL_PP_10 0x00000002 /* Read-write */
-#define BATL_PP_11 0x00000003
-
-#define BATL_PP_NO_ACCESS BATL_PP_00
-#define BATL_PP_RO BATL_PP_01
-#define BATL_PP_RW BATL_PP_10
-
#ifndef __ASSEMBLY__
/* cpu ids we detect */
typedef enum __cpu_t {
#define API_ENOMEM 3 /* no memory */
#define API_EBUSY 4 /* busy, occupied etc. */
#define API_EIO 5 /* I/O error */
+#define API_ESYSC 6 /* syscall error */
typedef int (*scp_t)(int, int *, ...);
#endif
#endif /* __ASM_ARCH_OMAP_GPMC_H */
-
/*
- * A dummy header file for use with the LPC2292 port to keep the
- * compiler happy.
+ * Copyright 2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
*/
-#ifndef _MMC_ARM_TDM_H_
-#define _MMC_ARM_TDM_H_
-#endif /* _MMC_ARM_TDM_H_ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
+++ /dev/null
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_AVR32_MMC_H
-#define __ASM_AVR32_MMC_H
-
-struct mmc_cid {
- unsigned long psn;
- unsigned short oid;
- unsigned char mid;
- unsigned char prv;
- unsigned char mdt;
- char pnm[7];
-};
-
-struct mmc_csd
-{
- u8 csd_structure:2,
- spec_vers:4,
- rsvd1:2;
- u8 taac;
- u8 nsac;
- u8 tran_speed;
- u16 ccc:12,
- read_bl_len:4;
- u64 read_bl_partial:1,
- write_blk_misalign:1,
- read_blk_misalign:1,
- dsr_imp:1,
- rsvd2:2,
- c_size:12,
- vdd_r_curr_min:3,
- vdd_r_curr_max:3,
- vdd_w_curr_min:3,
- vdd_w_curr_max:3,
- c_size_mult:3,
- sector_size:5,
- erase_grp_size:5,
- wp_grp_size:5,
- wp_grp_enable:1,
- default_ecc:2,
- r2w_factor:3,
- write_bl_len:4,
- write_bl_partial:1,
- rsvd3:5;
- u8 file_format_grp:1,
- copy:1,
- perm_write_protect:1,
- tmp_write_protect:1,
- file_format:2,
- ecc:2;
- u8 crc:7;
- u8 one:1;
-};
-
-#define R1_ILLEGAL_COMMAND (1 << 22)
-#define R1_APP_CMD (1 << 5)
-
-#endif /* __ASM_AVR32_MMC_H */
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
}
#endif
+/* Define the default SPI CS used when booting out of SPI */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+ defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
+ defined(__ADSPBF51x__)
+# define BFIN_BOOT_SPI_SSEL 2
+#else
+# define BFIN_BOOT_SPI_SSEL 1
+#endif
+
#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
*/
/* This file shoule be up to date with:
- * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
+ * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
+# define ANOMALY_BF526 1
+#else
+# define ANOMALY_BF526 0
+#endif
+#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
+# define ANOMALY_BF527 1
+#else
+# define ANOMALY_BF527 0
+#endif
+
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
+#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (1)
+#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (1)
+#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (1)
+#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (1)
+#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (1)
+#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0xE510
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (1)
+#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (ANOMALY_BF526)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
+#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
+#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
+#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
-/* New Feature: Higher Default CCLK Rate */
-#define ANOMALY_05000368 (1)
+/* Incorrect Default CSEL Value in PLL_DIV */
+#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
+#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
+#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (1)
-/* USB Full-speed Mode not Fully Tested */
-#define ANOMALY_05000381 (1)
-/* New Feature: Boot from OTP Memory */
-#define ANOMALY_05000385 (1)
-/* New Feature: bfrom_SysControl() Routine */
-#define ANOMALY_05000386 (1)
-/* New Feature: Programmable Preboot Settings */
-#define ANOMALY_05000387 (1)
+#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
+/* Host Must Not Read Back During Host DMA Boot */
+#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (1)
-/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (1)
-/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (1)
-/* New Feature: Log Buffer Functionality */
-#define ANOMALY_05000394 (1)
-/* New Feature: Hook Routine Functionality */
-#define ANOMALY_05000395 (1)
-/* New Feature: Header Indirect Bit */
-#define ANOMALY_05000396 (1)
-/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
-#define ANOMALY_05000397 (1)
-/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
-#define ANOMALY_05000398 (1)
-/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
-#define ANOMALY_05000399 (1)
+#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
+#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
+#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (1)
+#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+/* Incorrect Default Internal Voltage Regulator Setting */
+#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* DEB2_URGENT Bit Not Functional */
+#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
+#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
+#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
+/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
+#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
+/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
+#define ANOMALY_05000421 (1)
+/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
+#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
+#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
+/* Internal Voltage Regulator Not Trimmed */
+#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
+#define ANOMALY_05000432 (ANOMALY_BF526)
+/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
+#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000285 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
#endif
*/
/* This file shoule be up to date with:
- * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
/* UART STB Bit Incorrectly Affects Receiver Setting */
#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
/* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
+#define ANOMALY_05000265 (1)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (1)
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (1)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (1)
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (1)
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
/* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (1)
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (1)
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (1)
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
+#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (1)
+#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
/* PPI Is Level-Sensitive on First Transfer */
-#define ANOMALY_05000313 (1)
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (1)
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
+#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
+#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
/* UART Break Signal Issues */
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
+#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
-
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
#define ANOMALY_05000266 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
#endif
*/
/* This file shoule be up to date with:
- * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
#endif
*/
/* This file shoule be up to date with:
- * - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
/* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
/* PLL Status Register Is Inaccurate */
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (1)
+#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (1)
+#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
#define ANOMALY_05000379 (1)
/* 8-Bit NAND Flash Boot Mode Not Functional */
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (1)
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (1)
+#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (1)
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (1)
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (1)
-/* FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000412 (1)
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (1)
+#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (1)
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
+#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
#endif
*/
/* This file shoule be up to date with:
- * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000371 (1)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
+/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
+#define ANOMALY_05000412 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
+#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
#define MCF_FMPLL_SYNCR 0x120000
#define MCF_FMPLL_SYNSR 0x120004
+
#define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
+#define MCF_SYNCR_MFD_4X 0x00000000
+#define MCF_SYNCR_MFD_6X 0x01000000
+#define MCF_SYNCR_MFD_8X 0x02000000
+#define MCF_SYNCR_MFD_10X 0x03000000
+#define MCF_SYNCR_MFD_12X 0x04000000
+#define MCF_SYNCR_MFD_14X 0x05000000
+#define MCF_SYNCR_MFD_16X 0x06000000
+#define MCF_SYNCR_MFD_18X 0x07000000
+
#define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19)
+#define MCF_SYNCR_RFD_DIV1 0x00000000
+#define MCF_SYNCR_RFD_DIV2 0x00080000
+#define MCF_SYNCR_RFD_DIV4 0x00100000
+#define MCF_SYNCR_RFD_DIV8 0x00180000
+#define MCF_SYNCR_RFD_DIV16 0x00200000
+#define MCF_SYNCR_RFD_DIV32 0x00280000
+#define MCF_SYNCR_RFD_DIV64 0x00300000
+#define MCF_SYNCR_RFD_DIV128 0x00380000
+
#define MCF_FMPLL_SYNSR_LOCK 0x8
#define MCF_WTM_WCR 0x140000
#define MCF_RCM_RCR_FRCRSTOUT 0x40
#define MCF_RCM_RCR_SOFTRST 0x80
+#define MCF_GPIO_PODR_ADDR 0x100000
+#define MCF_GPIO_PODR_DATAH 0x100001
+#define MCF_GPIO_PODR_DATAL 0x100002
+#define MCF_GPIO_PODR_BUSCTL 0x100003
+#define MCF_GPIO_PODR_BS 0x100004
+#define MCF_GPIO_PODR_CS 0x100005
+#define MCF_GPIO_PODR_SDRAM 0x100006
+#define MCF_GPIO_PODR_FECI2C 0x100007
+#define MCF_GPIO_PODR_UARTH 0x100008
+#define MCF_GPIO_PODR_UARTL 0x100009
+#define MCF_GPIO_PODR_QSPI 0x10000A
+#define MCF_GPIO_PODR_TIMER 0x10000B
+
+#define MCF_GPIO_PDDR_ADDR 0x100010
+#define MCF_GPIO_PDDR_DATAH 0x100011
+#define MCF_GPIO_PDDR_DATAL 0x100012
+#define MCF_GPIO_PDDR_BUSCTL 0x100013
+#define MCF_GPIO_PDDR_BS 0x100014
+#define MCF_GPIO_PDDR_CS 0x100015
+#define MCF_GPIO_PDDR_SDRAM 0x100016
+#define MCF_GPIO_PDDR_FECI2C 0x100017
+#define MCF_GPIO_PDDR_UARTH 0x100018
+#define MCF_GPIO_PDDR_UARTL 0x100019
+#define MCF_GPIO_PDDR_QSPI 0x10001A
+#define MCF_GPIO_PDDR_TIMER 0x10001B
+
+#define MCF_GPIO_PPDSDR_ADDR 0x100020
+#define MCF_GPIO_PPDSDR_DATAH 0x100021
+#define MCF_GPIO_PPDSDR_DATAL 0x100022
+#define MCF_GPIO_PPDSDR_BUSCTL 0x100023
+#define MCF_GPIO_PPDSDR_BS 0x100024
+#define MCF_GPIO_PPDSDR_CS 0x100025
+#define MCF_GPIO_PPDSDR_SDRAM 0x100026
+#define MCF_GPIO_PPDSDR_FECI2C 0x100027
+#define MCF_GPIO_PPDSDR_UARTH 0x100028
+#define MCF_GPIO_PPDSDR_UARTL 0x100029
+#define MCF_GPIO_PPDSDR_QSPI 0x10002A
+#define MCF_GPIO_PPDSDR_TIMER 0x10002B
+
+#define MCF_GPIO_PCLRR_ADDR 0x100030
+#define MCF_GPIO_PCLRR_DATAH 0x100031
+#define MCF_GPIO_PCLRR_DATAL 0x100032
+#define MCF_GPIO_PCLRR_BUSCTL 0x100033
+#define MCF_GPIO_PCLRR_BS 0x100034
+#define MCF_GPIO_PCLRR_CS 0x100035
+#define MCF_GPIO_PCLRR_SDRAM 0x100036
+#define MCF_GPIO_PCLRR_FECI2C 0x100037
+#define MCF_GPIO_PCLRR_UARTH 0x100038
+#define MCF_GPIO_PCLRR_UARTL 0x100039
+#define MCF_GPIO_PCLRR_QSPI 0x10003A
+#define MCF_GPIO_PCLRR_TIMER 0x10003B
+
#define MCF_GPIO_PAR_AD 0x100040
+#define MCF_GPIO_PAR_BUSCTL 0x100042
+#define MCF_GPIO_PAR_BS 0x100044
#define MCF_GPIO_PAR_CS 0x100045
#define MCF_GPIO_PAR_SDRAM 0x100046
#define MCF_GPIO_PAR_FECI2C 0x100047
#define MCF_GPIO_PAR_UART 0x100048
+#define MCF_GPIO_PAR_QSPI 0x10004A
+#define MCF_GPIO_PAR_TIMER 0x10004C
+
+#define MCF_DSCR_EIM 0x100050
+#define MCF_DCSR_FEC12C 0x100052
+#define MCF_DCSR_UART 0x100053
+#define MCF_DCSR_QSPI 0x100054
+#define MCF_DCSR_TIMER 0x100055
#define MCF_CCM_CIR 0x11000A
#define MCF_CCM_CIR_PRN_MASK 0x3F
#define MCF_CCM_CIR_PIN_LEN 6
-#define MCF_CCM_CIR_PIN_MCF5270 0x2e
-#define MCF_CCM_CIR_PIN_MCF5271 0x80
+#define MCF_CCM_CIR_PIN_MCF5270 0x002e
+#define MCF_CCM_CIR_PIN_MCF5271 0x0032
#define MCF_GPIO_AD_ADDR23 0x80
#define MCF_GPIO_AD_ADDR22 0x40
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#ifndef CONFIG_MAX_MEM_MAPPED
+#if defined(CONFIG_4xx) || defined(CONFIG_E500)
+#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
+#else
+#define CONFIG_MAX_MEM_MAPPED (256 << 20)
+#endif
+#endif
+
+#endif
#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
-
-/* BAT (block address translation */
-#define BATU_BEPI_MSK 0xfffe0000
-#define BATU_BL_MSK 0x00001ffc
-
-#define BATU_BL_128K 0x00000000
-#define BATU_BL_256K 0x00000004
-#define BATU_BL_512K 0x0000000c
-#define BATU_BL_1M 0x0000001c
-#define BATU_BL_2M 0x0000003c
-#define BATU_BL_4M 0x0000007c
-#define BATU_BL_8M 0x000000fc
-#define BATU_BL_16M 0x000001fc
-#define BATU_BL_32M 0x000003fc
-#define BATU_BL_64M 0x000007fc
-#define BATU_BL_128M 0x00000ffc
-#define BATU_BL_256M 0x00001ffc
-
-#define BATU_VS 0x00000002
-#define BATU_VP 0x00000001
-
-#define BATL_BRPN_MSK 0xfffe0000
-#define BATL_WIMG_MSK 0x00000078
-
-#define BATL_WRITETHROUGH 0x00000040
-#define BATL_CACHEINHIBIT 0x00000020
-#define BATL_MEMCOHERENCE 0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
-
-#define BATL_PP_MSK 0x00000003
-#define BATL_PP_00 0x00000000 /* No access */
-#define BATL_PP_01 0x00000001 /* Read-only */
-#define BATL_PP_10 0x00000002 /* Read-write */
-#define BATL_PP_11 0x00000003
-
#endif /* __E300_H__ */
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_32_BE 0x00080000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_NCAP 0x00020000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_BI 0x00000001
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
-#ifndef CONFIG_MPC8572
+#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
LAW_TRGT_IF_LBC = 0x04,
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
-#ifdef CONFIG_MPC8572
+#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
* IIM
*/
typedef struct iim512x {
- u8 fixme[0x1000];
+ u32 stat; /* IIM status register */
+ u32 statm; /* IIM status IRQ mask */
+ u32 err; /* IIM errors register */
+ u32 emask; /* IIM error IRQ mask */
+ u32 fctl; /* IIM fuse control register */
+ u32 ua; /* IIM upper address register */
+ u32 la; /* IIM lower address register */
+ u32 sdat; /* IIM explicit sense data */
+ u8 res0[0x08];
+ u32 prg_p; /* IIM program protection register */
+ u8 res1[0x10];
+ u32 divide; /* IIM divide factor register */
+ u8 res2[0x7c0];
+ u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */
+ u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */
+ u8 res3[0x380];
+ u32 fbac1; /* IIM fuse bank 1 protection */
+ u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */
+ u8 res4[0x380];
} iim512x_t;
/*
* PATA
*/
typedef struct pata512x {
- u8 fixme[0x100];
+ /* LOCAL Registers */
+ u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
+ u32 pata_time2; /* Time register 2: PIO timing parameter */
+ u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
+ u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
+ u32 pata_time5; /* Time register 5: UDMA timing parameter */
+ u32 pata_time6; /* Time register 6: UDMA timing parameter */
+ u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
+ u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
+ u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
+ u32 pata_ata_control; /* ATA Interface control register */
+ u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
+ u32 pata_irq_enable; /* Interrupt enable register */
+ u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
+ u32 pata_fifo_alarm; /* fifo alarm threshold */
+ u32 res1[0x1A];
+ /* DRIVE Registers */
+ u32 pata_drive_data; /* drive data register*/
+ u32 pata_drive_features;/* drive features register */
+ u32 pata_drive_sectcnt; /* drive sector count register */
+ u32 pata_drive_sectnum; /* drive sector number register */
+ u32 pata_drive_cyllow; /* drive cylinder low register */
+ u32 pata_drive_cylhigh; /* drive cylinder high register */
+ u32 pata_drive_dev_head;/* drive device head register */
+ u32 pata_drive_command; /* write = drive command, read = drive status reg */
+ u32 res2[0x06];
+ u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
+ u32 res3[0x09];
} pata512x_t;
/*
} immap_t;
#endif
+#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
+#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
#endif /* __IMMAP_83xx__ */
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
char res19[4];
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
- char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
+ char res19_8a[20];
+ uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
+ char res19_8b[4];
+ uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
+ char res19_9a[20];
+ uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
+ char res19_9b[4];
+ uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
+ char res19_10a[20];
+ uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */
+ char res19_10b[4];
+ uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */
+ char res19_11a[20];
+ uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */
+ char res19_11b[4];
+ uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */
+ char res20[652];
uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
char res21[12];
uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
- char res8_1b[2672];
+ char res8_1b[2456];
+ uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */
+ uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */
+ uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */
+ uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */
+ char res8_1c[200];
uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
char res8_2[512];
uint gpindr; /* 0xe0050 - General-purpose input data register */
char res5[12];
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_SD_DATA 0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
uint mcpsumr; /* 0xe0090 - Machine check summary register */
- char res9[12];
+ uint rstrscr; /* 0xe0094 - Reset request status and control register */
+ char res9[8];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
- char res10a[1880];
+ char res10a[8];
+ uint rstcr; /* 0xe00b0 - Reset control register */
+#define MPC86xx_RSTCR_HRST_REQ 0x00000002
+ char res10b[1868];
uint clkdvdr; /* 0xe0800 - Clock Divide register */
- char res10b[1532];
+ char res10c[796];
+ uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */
+ char res10d[4];
+ uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */
+ char res10e[724];
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
char res12[12];
uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
- int res13[57];
- uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
- int res14[6];
- uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
- char res15[216];
+ char res13a[224];
+ uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */
+ char res13b[4];
+ uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */
+ char res14[24];
+ uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
+ char res15a[24];
+ uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
+ uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */
+ char res16[184];
} ccsr_gur_t;
/*
extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
extern void _tlbia(void); /* invalidate all TLB entries */
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
+
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3,
#endif /* __ASSEMBLY__ */
-/* Block size masks */
-#define BL_128K 0x000
-#define BL_256K 0x001
-#define BL_512K 0x003
-#define BL_1M 0x007
-#define BL_2M 0x00F
-#define BL_4M 0x01F
-#define BL_8M 0x03F
-#define BL_16M 0x07F
-#define BL_32M 0x0FF
-#define BL_64M 0x1FF
-#define BL_128M 0x3FF
-#define BL_256M 0x7FF
+#define BATU_VS 0x00000002
+#define BATU_VP 0x00000001
+#define BATU_INVALID 0x00000000
+
+#define BATL_WRITETHROUGH 0x00000040
+#define BATL_CACHEINHIBIT 0x00000020
+#define BATL_MEMCOHERENCE 0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+#define BATL_NO_ACCESS 0x00000000
+
+#define BATL_PP_MSK 0x00000003
+#define BATL_PP_00 0x00000000 /* No access */
+#define BATL_PP_01 0x00000001 /* Read-only */
+#define BATL_PP_10 0x00000002 /* Read-write */
+#define BATL_PP_11 0x00000003
+
+#define BATL_PP_NO_ACCESS BATL_PP_00
+#define BATL_PP_RO BATL_PP_01
+#define BATL_PP_RW BATL_PP_10
+
+/* BAT Block size values */
+#define BATU_BL_128K 0x00000000
+#define BATU_BL_256K 0x00000004
+#define BATU_BL_512K 0x0000000c
+#define BATU_BL_1M 0x0000001c
+#define BATU_BL_2M 0x0000003c
+#define BATU_BL_4M 0x0000007c
+#define BATU_BL_8M 0x000000fc
+#define BATU_BL_16M 0x000001fc
+#define BATU_BL_32M 0x000003fc
+#define BATU_BL_64M 0x000007fc
+#define BATU_BL_128M 0x00000ffc
+#define BATU_BL_256M 0x00001ffc
+
+/* Block lengths for processors that support extended block length */
+#ifdef HID0_XBSEN
+#define BATU_BL_512M 0x00003ffc
+#define BATU_BL_1G 0x00007ffc
+#define BATU_BL_2G 0x0000fffc
+#define BATU_BL_4G 0x0001fffc
+#define BATU_BL_MAX BATU_BL_4G
+#else
+#define BATU_BL_MAX BATU_BL_256M
+#endif
/* BAT Access Protection */
#define BPP_XX 0x00 /* No access */
#define BPP_RX 0x01 /* Read only */
#define BPP_RW 0x02 /* Read/write */
+/* Macros to get values from BATs, once data is in the BAT register format */
+#define BATU_VALID(x) (x & 0x3)
+#define BATU_VADDR(x) (x & 0xfffe0000)
+#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
+ | ((x & 0x0e00ULL) << 24) \
+ | ((x & 0x04ULL) << 30)))
+#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+
/* Used to set up SDR1 register */
#define HASH_TABLE_SIZE_64K 0x00010000
#define HASH_TABLE_SIZE_128K 0x00020000
extern void disable_tlb(u8 esel);
extern void invalidate_tlb(u8 tlb);
extern void init_tlbs(void);
-#ifdef CONFIG_ADDR_MAP
-extern void init_addr_map(void);
-#endif
+
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
#define SDRAM_RDCC_RSAE_MASK 0x00000001
#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
+#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30)
+#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03)
/*
* SDRAM Read Feedback Delay Control Register
#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
+#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
+#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
+/* e600 core PVR fields */
+
+#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
+#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
+#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
+#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
+
/* Processor Version Numbers */
#define PVR_403GA 0x00200000
#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
#define PVR_86xx 0x80040000
-#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
#define PVR_VIRTEX5 0x7ff21912
#define SVR_8568_E 0x807D00
#define SVR_8572 0x80E000
#define SVR_8572_E 0x80E800
+#define SVR_P2020 0x80E200
+#define SVR_P2020_E 0x80EA00
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
-#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
+#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_IMLS /* List all found images */
+#endif
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
/*
* Ethernet configuration
*
- * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
+ * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
*/
#define CONFIG_MPC5xxx_FEC 1
-#undef CONFIG_FEC_10MBIT
+#define CONFIG_MPC5xxx_FEC_MII100
+#undef CONFIG_MPC5xxx_MII10
#define CONFIG_PHY_ADDR 0x00
/*
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_NET
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_FEC_MII100 1
-#endif
/*
* GPIO configuration
#define CONFIG_CMD_MISC
#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#define CONFIG_SYS_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_RETRY_COUNT 5
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
-#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_HOSTNAME M5271EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr) ${u-boot}\0" \
+ "uboot=u-boot.bin\0" \
+ "load=tftp $loadaddr $uboot\0" \
"upd=run load; run prog\0" \
- "prog=prot off ffe00000 ffe2ffff;" \
- "era ffe00000 ffe2ffff;" \
- "cp.b ${loadaddr} 0 ${filesize};" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b $loadaddr ffe00000 $filesize;" \
"save\0" \
""
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ 1000000
+
+/* Clock configuration
+ * The external oscillator is a 25.000 MHz
+ * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
+ * bus_clk = (cpu_clk/2) (fixed ratio)
+ *
+ * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
+ * match the new clock speed. Max cpu_clk is 150 MHz.
+ */
#define CONFIG_SYS_CLK 100000000
+#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
/*
* Low Level Configuration Settings
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
-/* Port configuration */
-#define CONFIG_SYS_FECI2C 0xF0
+/* Chip Select 0 : Boot Flash */
+#define CONFIG_SYS_CS0_BASE 0xFFE00000
+#define CONFIG_SYS_CS0_MASK 0x001F0001
+#define CONFIG_SYS_CS0_CTRL 0x00001980
+
+/* Chip Select 1 : External SRAM */
+#define CONFIG_SYS_CS1_BASE 0x30000000
+#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CONFIG_SYS_CS1_CTRL 0x00001900
#endif /* _M5271EVB_H */
#define CONFIG_CMD_PCI
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMD_PCI
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
#endif
#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
/* DDR Setup */
#define CONFIG_SYS_DDR_TLB_START 9
+#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else
+#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_DIAG_ADDR 0xff800000
#endif
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-
/*
* virtual address to be used for temporary mappings. There
* should be 128k free at this VA.
#define CONFIG_CMD_MII
#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#endif
#if defined(CONFIG_PCI)
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
+#define CONFIG_ADDR_MAP 1 /* Use addr map */
#ifdef RUN_DIAG
#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-
/*
* virtual address to be used for temporary mappings. There
* should be 128k free at this VA.
#define CONFIG_ENV_OVERWRITE
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
+#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#define CONFIG_ALTIVEC 1
#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
| CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| 0x00001001) /* port size 16bit */
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
#else
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
| CONFIG_SYS_PHYS_ADDR_HIGH)
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
#define _IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
+#ifdef CONFIG_PHYS_64BIT
+/*
+ * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
+ * This will increase the amount of PCI address space available for
+ * for mapping RAM.
+ */
+#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS
+#else
+#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \
+ + CONFIG_SYS_PCI1_MEM_SIZE)
+#endif
+#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \
+ CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
+ CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
+ CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
| BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#endif
#if defined(CONFIG_PCI)
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_RUN
#define CONFIG_CMD_NFS
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
*/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
/*
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMMAP
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CMD_JFFS2
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMD_IDE
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FLASH
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR 0x1f
#define CONFIG_PHY_TYPE 0x79c874
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
/*
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=tqm8260/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40200000\0" \
+ "kernel_addr=400C0000\0" \
+ "ramdisk_addr=40240000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+#define CONFIG_TQM8548
+#endif
+
#define CONFIG_PCI
+#ifndef CONFIG_TQM8548_AG
+#define CONFIG_PCI1 /* PCI/PCI-X controller */
+#endif
+#ifdef CONFIG_TQM8548
+#define CONFIG_PCIE1 /* PCI Express interface */
+#endif
+
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
-#ifdef CONFIG_TQM8548
-#define CONFIG_PCI1
-#define CONFIG_PCIE1
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
* Warning: NAND support will likely increase the U-Boot image size
* to more than 256 KB. Please adjust TEXT_BASE if necessary.
*/
-#undef CONFIG_NAND
+#ifdef CONFIG_TQM8548_BE
+#define CONFIG_NAND
+#endif
/*
* MPC8540 and MPC8548 don't have CPM module
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#undef CONFIG_CAN_DRIVER /* CAN Driver support */
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+#define CONFIG_CAN_DRIVER /* CAN Driver support */
+#endif
/*
* sysclk for MPC85xx
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#ifdef CONFIG_TQM8548_AG
+#define CONFIG_VERY_BIG_RAM
+#endif
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#ifndef CONFIG_TQM8548_AG
#define CONFIG_CMD_DATE
+#endif
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DTT
#define CONFIG_CMD_MII
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_SEVENWIRE
/* dummy, 7-wire FEC does not have phy address */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMLS
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
+#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */
/* video */
#undef CONFIG_VIDEO
#endif
/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
/*
* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
* For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for IDE not supported */
+
+#define CONFIG_IDE_RESET /* reset for IDE supported */
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA
+
+/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#define ATA_BASE_ADDR MPC512X_PATA
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
+#define FSL_ATA_CTRL_IORDY_EN 0x01000000
+
#endif /* __CONFIG_H */
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x0
/*
* GPIO configuration:
*/
#include <config_cmd_default.h>
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0
*/
#include <config_cmd_default.h>
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_IMI
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MII
#else
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FPGA
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII 1 /* MII PHY management */
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMI
*/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_MEMORY
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
/*
*/
#define CONFIG_PHYS_64BIT
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
/*
* Include common defines/options for all AMCC eval boards
*
* DDR Autocalibration Method_B is the default.
*/
-#if 0
-/*
- * Needs FIX!!!
- * Disable autocalibration for now, because of the unresolved problem
- * with kilauea board using 200MHz PLB/DDR2 frequency
- */
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
-#endif
#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
#endif
#if defined(CFG_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_RUN
#define CONFIG_CMD_IMI
#define CONFIG_CMD_NFS
#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_AUTO_COMPLETE
/*
* Ethernet configuration
*/
-/*#define CONFIG_MPC5xxx_FEC 1*/
+/* #define CONFIG_MPC5xxx_FEC 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII100 */
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 1
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_UDP_CHECKSUM 1
#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
#undef CONFIG_ETHER_NONE /* No external Ethernet */
+#define CONFIG_NET_MULTI 1
#define CONFIG_ETHER_INDEX 4
#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
#define CONFIG_CMD_JFFS2
#if !defined(RAMENV)
- #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SAVES
#endif
#else
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x2
#define CONFIG_PHY_TYPE 0x79c874
#define CONFIG_RESET_PHY_R 1
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define __MPR2_H
/* Supported commands */
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_FLASH
#define CONFIG_MS7720SE 1
#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_CMD_DFL
#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 38400
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII 1 /* MII PHY management */
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x01
#define CONFIG_MII 1
#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_JFFS2
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
/*
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FPGA
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
*/
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_UDP_CHECKSUM 1
#include <config_cmd_default.h>
#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NFS
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NFS
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_RUN
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
#if defined(CONFIG_BOOT_ONENAND)
#define CONFIG_CMD_ONENAND
#define CONFIG_CMD_I2C
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#else
#define CONFIG_CMD_ELF
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#else
#define CONFIG_CMD_ELF
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_MEMORY
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_MISC
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII 1
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII 1
#define CONFIG_CMD_BDI
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
/*
#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_JFFS2
#ifdef TURN_ON_ETHERNET
#define CONFIG_CMD_PING
#else
- #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_NET
ulong size; /* total bank size in bytes */
ushort sector_count; /* number of erase units */
ulong flash_id; /* combined device & manufacturer code */
- ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* physical sector start addresses */
+ ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */
uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */
#ifdef CONFIG_SYS_FLASH_CFI
uchar portwidth; /* the width of the port */
#define CFI_CMDSET_AMD_LEGACY 0xFFF0
#endif
+#if defined(CONFIG_SYS_FLASH_CFI)
+extern flash_info_t *flash_get_info(ulong base);
+#endif
/*-----------------------------------------------------------------------
* return codes from flash_write():
--- /dev/null
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2007-2008, Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *-------------------------------------------------------------------
+ *
+ */
+
+#ifndef __FSL_ESDHC_H__
+#define __FSL_ESDHC_H__
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL 0x0002e02c
+#define SYSCTL_INITA 0x08000000
+#define SYSCTL_TIMEOUT_MASK 0x000f0000
+#define SYSCTL_CLOCK_MASK 0x00000fff
+#define SYSCTL_PEREN 0x00000004
+#define SYSCTL_HCKEN 0x00000002
+#define SYSCTL_IPGEN 0x00000001
+
+#define IRQSTAT 0x0002e030
+#define IRQSTAT_DMAE (0x10000000)
+#define IRQSTAT_AC12E (0x01000000)
+#define IRQSTAT_DEBE (0x00400000)
+#define IRQSTAT_DCE (0x00200000)
+#define IRQSTAT_DTOE (0x00100000)
+#define IRQSTAT_CIE (0x00080000)
+#define IRQSTAT_CEBE (0x00040000)
+#define IRQSTAT_CCE (0x00020000)
+#define IRQSTAT_CTOE (0x00010000)
+#define IRQSTAT_CINT (0x00000100)
+#define IRQSTAT_CRM (0x00000080)
+#define IRQSTAT_CINS (0x00000040)
+#define IRQSTAT_BRR (0x00000020)
+#define IRQSTAT_BWR (0x00000010)
+#define IRQSTAT_DINT (0x00000008)
+#define IRQSTAT_BGE (0x00000004)
+#define IRQSTAT_TC (0x00000002)
+#define IRQSTAT_CC (0x00000001)
+
+#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
+
+#define IRQSTATEN 0x0002e034
+#define IRQSTATEN_DMAE (0x10000000)
+#define IRQSTATEN_AC12E (0x01000000)
+#define IRQSTATEN_DEBE (0x00400000)
+#define IRQSTATEN_DCE (0x00200000)
+#define IRQSTATEN_DTOE (0x00100000)
+#define IRQSTATEN_CIE (0x00080000)
+#define IRQSTATEN_CEBE (0x00040000)
+#define IRQSTATEN_CCE (0x00020000)
+#define IRQSTATEN_CTOE (0x00010000)
+#define IRQSTATEN_CINT (0x00000100)
+#define IRQSTATEN_CRM (0x00000080)
+#define IRQSTATEN_CINS (0x00000040)
+#define IRQSTATEN_BRR (0x00000020)
+#define IRQSTATEN_BWR (0x00000010)
+#define IRQSTATEN_DINT (0x00000008)
+#define IRQSTATEN_BGE (0x00000004)
+#define IRQSTATEN_TC (0x00000002)
+#define IRQSTATEN_CC (0x00000001)
+
+#define PRSSTAT 0x0002e024
+#define PRSSTAT_CLSL (0x00800000)
+#define PRSSTAT_WPSPL (0x00080000)
+#define PRSSTAT_CDPL (0x00040000)
+#define PRSSTAT_CINS (0x00010000)
+#define PRSSTAT_BREN (0x00000800)
+#define PRSSTAT_DLA (0x00000004)
+#define PRSSTAT_CICHB (0x00000002)
+#define PRSSTAT_CIDHB (0x00000001)
+
+#define PROCTL 0x0002e028
+#define PROCTL_INIT 0x00000020
+#define PROCTL_DTW_4 0x00000002
+#define PROCTL_DTW_8 0x00000004
+
+#define CMDARG 0x0002e008
+
+#define XFERTYP 0x0002e00c
+#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL 0x0
+#define XFERTYP_CMDTYP_SUSPEND 0x00400000
+#define XFERTYP_CMDTYP_RESUME 0x00800000
+#define XFERTYP_CMDTYP_ABORT 0x00c00000
+#define XFERTYP_DPSEL 0x00200000
+#define XFERTYP_CICEN 0x00100000
+#define XFERTYP_CCCEN 0x00080000
+#define XFERTYP_RSPTYP_NONE 0
+#define XFERTYP_RSPTYP_136 0x00010000
+#define XFERTYP_RSPTYP_48 0x00020000
+#define XFERTYP_RSPTYP_48_BUSY 0x00030000
+#define XFERTYP_MSBSEL 0x00000020
+#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_AC12EN 0x00000004
+#define XFERTYP_BCEN 0x00000002
+#define XFERTYP_DMAEN 0x00000001
+
+#define CINS_TIMEOUT 1000
+
+#define DSADDR 0x2e004
+
+#define CMDRSP0 0x2e010
+#define CMDRSP1 0x2e014
+#define CMDRSP2 0x2e018
+#define CMDRSP3 0x2e01c
+
+#define DATPORT 0x2e020
+
+#define WML 0x2e044
+#define WML_WRITE 0x00010000
+
+#define BLKATTR 0x2e004
+#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x) (x & 0x1fff)
+#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18 0x04000000
+#define ESDHC_HOSTCAPBLT_VS30 0x02000000
+#define ESDHC_HOSTCAPBLT_VS33 0x01000000
+#define ESDHC_HOSTCAPBLT_SRS 0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
+#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+
+int fsl_esdhc_mmc_init(bd_t *bis);
+
+#endif /* __FSL_ESDHC_H__ */
printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
#endif
-#ifdef CONFIG_BLACKFIN
- /* This ifdef will become unneccessary in a future version of the
- * blackfin I2C driver.
- */
- i2c_read(addr, reg, 0, &buf, 1);
-#else
i2c_read(addr, reg, 1, &buf, 1);
-#endif
return buf;
}
__func__, addr, reg, val);
#endif
-#ifdef CONFIG_BLACKFIN
- /* This ifdef will become unneccessary in a future version of the
- * blackfin I2C driver.
- */
- i2c_write(addr, reg, 0, &val, 1);
-#else
i2c_write(addr, reg, 1, &val, 1);
-#endif
}
/*
{ \
return uimage_to_cpu (hdr->ih_##f); \
}
-image_get_hdr_l (magic);
-image_get_hdr_l (hcrc);
-image_get_hdr_l (time);
-image_get_hdr_l (size);
-image_get_hdr_l (load);
-image_get_hdr_l (ep);
-image_get_hdr_l (dcrc);
+image_get_hdr_l (magic); /* image_get_magic */
+image_get_hdr_l (hcrc); /* image_get_hcrc */
+image_get_hdr_l (time); /* image_get_time */
+image_get_hdr_l (size); /* image_get_size */
+image_get_hdr_l (load); /* image_get_load */
+image_get_hdr_l (ep); /* image_get_ep */
+image_get_hdr_l (dcrc); /* image_get_dcrc */
#define image_get_hdr_b(f) \
static inline uint8_t image_get_##f(image_header_t *hdr) \
{ \
return hdr->ih_##f; \
}
-image_get_hdr_b (os);
-image_get_hdr_b (arch);
-image_get_hdr_b (type);
-image_get_hdr_b (comp);
+image_get_hdr_b (os); /* image_get_os */
+image_get_hdr_b (arch); /* image_get_arch */
+image_get_hdr_b (type); /* image_get_type */
+image_get_hdr_b (comp); /* image_get_comp */
static inline char *image_get_name (image_header_t *hdr)
{
{ \
hdr->ih_##f = cpu_to_uimage (val); \
}
-image_set_hdr_l (magic);
-image_set_hdr_l (hcrc);
-image_set_hdr_l (time);
-image_set_hdr_l (size);
-image_set_hdr_l (load);
-image_set_hdr_l (ep);
-image_set_hdr_l (dcrc);
+image_set_hdr_l (magic); /* image_set_magic */
+image_set_hdr_l (hcrc); /* image_set_hcrc */
+image_set_hdr_l (time); /* image_set_time */
+image_set_hdr_l (size); /* image_set_size */
+image_set_hdr_l (load); /* image_set_load */
+image_set_hdr_l (ep); /* image_set_ep */
+image_set_hdr_l (dcrc); /* image_set_dcrc */
#define image_set_hdr_b(f) \
static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
{ \
hdr->ih_##f = val; \
}
-image_set_hdr_b (os);
-image_set_hdr_b (arch);
-image_set_hdr_b (type);
-image_set_hdr_b (comp);
+image_set_hdr_b (os); /* image_set_os */
+image_set_hdr_b (arch); /* image_set_arch */
+image_set_hdr_b (type); /* image_set_type */
+image_set_hdr_b (comp); /* image_set_comp */
static inline void image_set_name (image_header_t *hdr, const char *name)
{
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright 2008, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
*
* See file CREDITS for list of people who contributed to this
* project.
#ifndef _MMC_H_
#define _MMC_H_
-#include <asm/arch/mmc.h>
-/* MMC command numbers */
+#include <linux/list.h>
+
+#define SD_VERSION_SD 0x20000
+#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
+#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
+#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
+#define MMC_VERSION_MMC 0x10000
+#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
+#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
+#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
+#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
+#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
+#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
+
+#define MMC_MODE_HS 0x001
+#define MMC_MODE_HS_52MHz 0x010
+#define MMC_MODE_4BIT 0x100
+#define MMC_MODE_8BIT 0x200
+
+#define SD_DATA_4BIT 0x00040000
+
+#define IS_SD(x) (mmc->version & SD_VERSION_SD)
+
+#define MMC_DATA_READ 1
+#define MMC_DATA_WRITE 2
+
+#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
+#define UNUSABLE_ERR -17 /* Unusable Card */
+#define COMM_ERR -18 /* Communications Error */
+#define TIMEOUT -19
+
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
#define MMC_CMD_ALL_SEND_CID 2
#define MMC_CMD_SET_RELATIVE_ADDR 3
#define MMC_CMD_SET_DSR 4
+#define MMC_CMD_SWITCH 6
#define MMC_CMD_SELECT_CARD 7
+#define MMC_CMD_SEND_EXT_CSD 8
#define MMC_CMD_SEND_CSD 9
#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_STOP_TRANSMISSION 12
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
-#define MMC_CMD_WRITE_BLOCK 24
+#define MMC_CMD_WRITE_SINGLE_BLOCK 24
+#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define MMC_CMD_APP_CMD 55
-/* SD Card command numbers */
#define SD_CMD_SEND_RELATIVE_ADDR 3
-#define SD_CMD_SWITCH 6
+#define SD_CMD_SWITCH_FUNC 6
#define SD_CMD_SEND_IF_COND 8
#define SD_CMD_APP_SET_BUS_WIDTH 6
#define SD_CMD_APP_SEND_OP_COND 41
+#define SD_CMD_APP_SEND_SCR 51
+
+/* SCR definitions in different words */
+#define SD_HIGHSPEED_BUSY 0x00020000
+#define SD_HIGHSPEED_SUPPORTED 0x00020000
+
+#define MMC_HS_TIMING 0x00000100
+#define MMC_HS_52MHZ 0x2
+
+#define OCR_BUSY 0x80
+#define OCR_HCS 0x40000000
+
+#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
+#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
+
+#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
+#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
+ addressed by index which are
+ 1 in value field */
+#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
+ addressed by index, which are
+ 1 in value field */
+#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
+
+#define SD_SWITCH_CHECK 0
+#define SD_SWITCH_SWITCH 1
+
+/*
+ * EXT_CSD fields
+ */
+
+#define EXT_CSD_BUS_WIDTH 183 /* R/W */
+#define EXT_CSD_HS_TIMING 185 /* R/W */
+#define EXT_CSD_CARD_TYPE 196 /* RO */
+#define EXT_CSD_REV 192 /* RO */
+#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
+
+/*
+ * EXT_CSD field definitions
+ */
+
+#define EXT_CSD_CMD_SET_NORMAL (1<<0)
+#define EXT_CSD_CMD_SET_SECURE (1<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
+
+#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
+
+#define R1_ILLEGAL_COMMAND (1 << 22)
+#define R1_APP_CMD (1 << 5)
+
+#define MMC_RSP_PRESENT (1 << 0)
+#define MMC_RSP_136 (1 << 1) /* 136 bit response */
+#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
+#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
+#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
+
+#define MMC_RSP_NONE (0)
+#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
+ MMC_RSP_BUSY)
+#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
+#define MMC_RSP_R3 (MMC_RSP_PRESENT)
+#define MMC_RSP_R4 (MMC_RSP_PRESENT)
+#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+
+
+struct mmc_cid {
+ unsigned long psn;
+ unsigned short oid;
+ unsigned char mid;
+ unsigned char prv;
+ unsigned char mdt;
+ char pnm[7];
+};
+
+struct mmc_csd
+{
+ u8 csd_structure:2,
+ spec_vers:4,
+ rsvd1:2;
+ u8 taac;
+ u8 nsac;
+ u8 tran_speed;
+ u16 ccc:12,
+ read_bl_len:4;
+ u64 read_bl_partial:1,
+ write_blk_misalign:1,
+ read_blk_misalign:1,
+ dsr_imp:1,
+ rsvd2:2,
+ c_size:12,
+ vdd_r_curr_min:3,
+ vdd_r_curr_max:3,
+ vdd_w_curr_min:3,
+ vdd_w_curr_max:3,
+ c_size_mult:3,
+ sector_size:5,
+ erase_grp_size:5,
+ wp_grp_size:5,
+ wp_grp_enable:1,
+ default_ecc:2,
+ r2w_factor:3,
+ write_bl_len:4,
+ write_bl_partial:1,
+ rsvd3:5;
+ u8 file_format_grp:1,
+ copy:1,
+ perm_write_protect:1,
+ tmp_write_protect:1,
+ file_format:2,
+ ecc:2;
+ u8 crc:7;
+ u8 one:1;
+};
+
+struct mmc_cmd {
+ ushort cmdidx;
+ uint resp_type;
+ uint cmdarg;
+ char response[18];
+ uint flags;
+};
+
+struct mmc_data {
+ union {
+ char *dest;
+ const char *src; /* src buffers don't get written to */
+ };
+ uint flags;
+ uint blocks;
+ uint blocksize;
+};
+
+struct mmc {
+ struct list_head link;
+ char name[32];
+ void *priv;
+ uint voltages;
+ uint version;
+ uint f_min;
+ uint f_max;
+ int high_capacity;
+ uint bus_width;
+ uint clock;
+ uint card_caps;
+ uint host_caps;
+ uint ocr;
+ uint scr[2];
+ uint csd[4];
+ char cid[16];
+ ushort rca;
+ uint tran_speed;
+ uint read_bl_len;
+ uint write_bl_len;
+ u64 capacity;
+ block_dev_desc_t block_dev;
+ int (*send_cmd)(struct mmc *mmc,
+ struct mmc_cmd *cmd, struct mmc_data *data);
+ void (*set_ios)(struct mmc *mmc);
+ int (*init)(struct mmc *mmc);
+};
-int mmc_init(int verbose);
-int mmc_read(ulong src, uchar *dst, int size);
-int mmc_write(uchar *src, ulong dst, int size);
-int mmc2info(ulong addr);
+int mmc_register(struct mmc *mmc);
+int mmc_initialize(bd_t *bis);
+int mmc_init(struct mmc *mmc);
+int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
+struct mmc *find_mmc_device(int dev_num);
+void print_mmc_devices(char separator);
+#ifndef CONFIG_GENERIC_MMC
+int mmc_legacy_init(int verbose);
+#endif
#endif /* _MMC_H_ */
/* Register Offset Base */
#define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800)
+#define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200)
+
+/* IIM control */
+#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5))
+#define IIM_SET_LA(f, bit) (((f & 0x0000001f) << 3) | bit)
+#define IIM_STAT_BUSY 0x00000080
+#define IIM_STAT_PRGD 0x00000002
+#define IIM_STAT_SNSD 0x00000001
+#define IIM_ERR_WPE 0x00000040
+#define IIM_ERR_OPE 0x00000020
+#define IIM_ERR_RPE 0x00000010
+#define IIM_ERR_WLRE 0x00000008
+#define IIM_ERR_SNSE 0x00000004
+#define IIM_ERR_PARITYE 0x00000002
+#define IIM_PRG_P_SET 0x000000aa
+#define IIM_PRG_P_UNSET 0
+#define IIM_FCTL_PROG_PULSE 0x00000020
+#define IIM_FCTL_PROG 0x00000001
+#define IIM_FCTL_ESNS_N 0x00000008
+#define IIM_FBAC_FBWP 0x00000080
+#define IIM_FBAC_FBOP 0x00000040
+#define IIM_FBAC_FBRP 0x00000020
+#define IIM_FBAC_FBESP 0x00000008
+#define IIM_PROTECTION 0x000000e8
+#define IIM_FMAX 31
/* Number of I2C buses */
#define I2C_BUS_CNT 3
#define MICR_EADDR_MASK 0x30000000
#define MICR_EADDR_SHIFT 28
-#define BATU_BEPI_MSK 0xfffe0000
-#define BATU_BL_MSK 0x00001ffc
-
-#define BATU_BL_128K 0x00000000
-#define BATU_BL_256K 0x00000004
-#define BATU_BL_512K 0x0000000c
-#define BATU_BL_1M 0x0000001c
-#define BATU_BL_2M 0x0000003c
-#define BATU_BL_4M 0x0000007c
-#define BATU_BL_8M 0x000000fc
-#define BATU_BL_16M 0x000001fc
-#define BATU_BL_32M 0x000003fc
-#define BATU_BL_64M 0x000007fc
-#define BATU_BL_128M 0x00000ffc
-#define BATU_BL_256M 0x00001ffc
-
-#define BATU_VS 0x00000002
-#define BATU_VP 0x00000001
-
-#define BATL_BRPN_MSK 0xfffe0000
-#define BATL_WIMG_MSK 0x00000078
-
-#define BATL_WRITETHROUGH 0x00000040
-#define BATL_CACHEINHIBIT 0x00000020
-#define BATL_MEMCOHERENCE 0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
-
-#define BATL_PP_MSK 0x00000003
-#define BATL_PP_00 0x00000000 /* No access */
-#define BATL_PP_01 0x00000001 /* Read-only */
-#define BATL_PP_10 0x00000002 /* Read-write */
-#define BATL_PP_11 0x00000003
-
-/*
- * I'd attempt to do defines for the PP bits, but it's use is a bit
- * too complex, see the PowerPC Operating Environment Architecture
- * section in the PowerPc arch book, chapter 4.
- */
-
/*eumb and epic config*/
#define EPIC_FPR 0x00041000
/* SICRL bits - MPC837x specific */
#define SICRL_USB_A 0xC0000000
#define SICRL_USB_B 0x30000000
+#define SICRL_USB_B_SD 0x20000000
#define SICRL_UART 0x0C000000
#define SICRL_GPIO_A 0x02000000
#define SICRL_GPIO_B 0x01000000
#define SICRH_GPIO2_C 0x00002000
#define SICRH_GPIO2_D 0x00001000
#define SICRH_GPIO2_E 0x00000C00
+#define SICRH_GPIO2_E_SD 0x00000800
#define SICRH_GPIO2_F 0x00000300
#define SICRH_GPIO2_G 0x000000C0
#define SICRH_GPIO2_H 0x00000030
#define SICRH_SPI 0x00000003
+#define SICRH_SPI_SD 0x00000001
#endif
/* SWCRR - System Watchdog Control Register
#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-/*
- * BAT settings. Look in config_<BOARD>.h for the actual setup
- */
-
-#define BATU_BL_128K 0x00000000
-#define BATU_BL_256K 0x00000004
-#define BATU_BL_512K 0x0000000c
-#define BATU_BL_1M 0x0000001c
-#define BATU_BL_2M 0x0000003c
-#define BATU_BL_4M 0x0000007c
-#define BATU_BL_8M 0x000000fc
-#define BATU_BL_16M 0x000001fc
-#define BATU_BL_32M 0x000003fc
-#define BATU_BL_64M 0x000007fc
-#define BATU_BL_128M 0x00000ffc
-#define BATU_BL_256M 0x00001ffc
-#define BATU_BL_512M 0x00003ffc
-#define BATU_BL_1G 0x00007ffc
-#define BATU_BL_2G 0x0000fffc
-#define BATU_BL_4G 0x0001fffc
-
-#define BATU_VS 0x00000002
-#define BATU_VP 0x00000001
-#define BATU_INVALID 0x00000000
-
-#define BATL_WRITETHROUGH 0x00000040
-#define BATL_CACHEINHIBIT 0x00000020
-#define BATL_MEMCOHERENCE 0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
-#define BATL_NO_ACCESS 0x00000000
-
-#define BATL_PP_MSK 0x00000003
-#define BATL_PP_00 0x00000000 /* No access */
-#define BATL_PP_01 0x00000001 /* Read-only */
-#define BATL_PP_10 0x00000002 /* Read-write */
-#define BATL_PP_11 0x00000003
-
-#define BATL_PP_NO_ACCESS BATL_PP_00
-#define BATL_PP_RO BATL_PP_01
-#define BATL_PP_RW BATL_PP_10
-
#define HID0_XBSEN 0x00000100
#define HID0_HIGH_BAT_EN 0x00800000
#define HID0_XAEN 0x00020000
void *priv;
};
-extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */
-extern int eth_register(struct eth_device* dev);/* Register network device */
-extern void eth_try_another(int first_restart); /* Change the device */
+extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */
+extern int eth_register(struct eth_device* dev);/* Register network device */
+extern void eth_try_another(int first_restart); /* Change the device */
#ifdef CONFIG_NET_MULTI
-extern void eth_set_current(void); /* set nterface to ethcur var. */
+extern void eth_set_current(void); /* set nterface to ethcur var */
#endif
-extern struct eth_device *eth_get_dev(void); /* get the current device MAC */
-extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */
-extern int eth_get_dev_index (void); /* get the device index */
-extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */
-
-extern int eth_init(bd_t *bis); /* Initialize the device */
-extern int eth_send(volatile void *packet, int length); /* Send a packet */
+extern struct eth_device *eth_get_dev(void); /* get the current device MAC */
+extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */
+extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
+extern int eth_get_dev_index (void); /* get the device index */
+extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */
+
+extern int eth_init(bd_t *bis); /* Initialize the device */
+extern int eth_send(volatile void *packet, int length); /* Send a packet */
#ifdef CONFIG_API
-extern int eth_receive(volatile void *packet, int length); /* Receive a packet */
+extern int eth_receive(volatile void *packet, int length); /* Receive a packet*/
#endif
-extern int eth_rx(void); /* Check for received packets */
-extern void eth_halt(void); /* stop SCC */
-extern char *eth_get_name(void); /* get name of current device */
+extern int eth_rx(void); /* Check for received packets */
+extern void eth_halt(void); /* stop SCC */
+extern char *eth_get_name(void); /* get name of current device */
#ifdef CONFIG_MCAST_TFTP
int eth_mcast_join( IPaddr_t mcast_addr, u8 join);
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#define PCI_REGION_TYPE 0x00000001
#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
-#define PCI_REGION_MEMORY 0x00000100 /* System memory */
+#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
#define PCI_REGION_RO 0x00000200 /* Read-only memory */
extern __inline__ void pci_set_region(struct pci_region *reg,
#define pci_bus_to_phys(dev, addr, flags) \
pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
-#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
-#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
-#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
-#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+#define pci_virt_to_bus(dev, addr, flags) \
+ pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
+ (virt_to_phys(addr)), (flags))
+#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+ map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
+ (addr), (flags)), \
+ (len), (map_flags))
+
+#define pci_phys_to_mem(dev, addr) \
+ pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_phys(dev, addr) \
+ pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define pci_virt_to_mem(dev, addr) \
+ pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_virt(dev, addr, len, map_flags) \
+ pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define pci_virt_to_io(dev, addr) \
+ pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_virt(dev, addr, len, map_flags) \
+ pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u16 val);
+extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
extern void pci_register_hose(struct pci_controller* hose);
extern struct pci_controller* pci_bus_to_hose(int bus);
jumptable_init ();
+#if defined(CONFIG_API)
+ /* Initialize API */
+ api_init ();
+#endif
+
console_init_r (); /* fully init console as a device */
#if defined(CONFIG_MISC_INIT_R)
LIB = $(obj)libgeneric.a
COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
-COBJS-y += bzlib.o
-COBJS-y += bzlib_crctable.o
-COBJS-y += bzlib_decompress.o
-COBJS-y += bzlib_randtable.o
-COBJS-y += bzlib_huffman.o
+COBJS-$(CONFIG_BZIP2) += bzlib.o
+COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
+COBJS-$(CONFIG_BZIP2) += bzlib_decompress.o
+COBJS-$(CONFIG_BZIP2) += bzlib_randtable.o
+COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o
COBJS-y += crc16.o
COBJS-y += crc32.o
COBJS-y += ctype.o
#include <config.h>
#include <common.h>
#include <watchdog.h>
-#ifdef CONFIG_BZIP2
/*
* This file is a modified version of bzlib.c from the bzip2-1.0.2
/*-------------------------------------------------------------*/
/*--- end bzlib.c ---*/
/*-------------------------------------------------------------*/
-
-#endif /* CONFIG_BZIP2 */
#include <config.h>
-#ifdef CONFIG_BZIP2
/*-------------------------------------------------------------*/
/*--- Table for doing CRCs ---*/
/*-------------------------------------------------------------*/
/*--- end crctable.c ---*/
/*-------------------------------------------------------------*/
-
-#endif /* CONFIG_BZIP2 */
#include <config.h>
#include <common.h>
#include <watchdog.h>
-#ifdef CONFIG_BZIP2
/*-------------------------------------------------------------*/
/*--- Decompression machinery ---*/
/*-------------------------------------------------------------*/
/*--- end decompress.c ---*/
/*-------------------------------------------------------------*/
-
-#endif /* CONFIG_BZIP2 */
#include <config.h>
-#ifdef CONFIG_BZIP2
/*-------------------------------------------------------------*/
/*--- Huffman coding low-level stuff ---*/
/*-------------------------------------------------------------*/
/*--- end huffman.c ---*/
/*-------------------------------------------------------------*/
-
-#endif /* CONFIG_BZIP2 */
#include <config.h>
-#ifdef CONFIG_BZIP2
/*-------------------------------------------------------------*/
/*--- Table for randomising repetitive blocks ---*/
/*-------------------------------------------------------------*/
/*--- end randtable.c ---*/
/*-------------------------------------------------------------*/
-
-#endif /* CONFIG_BZIP2 */
#include <asm/mmu.h>
#include <asm/io.h>
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
+ int batn = -1;
+
sync();
switch (bat) {
case DBAT0:
mtspr (DBAT0L, lower);
mtspr (DBAT0U, upper);
+ batn = 0;
break;
case IBAT0:
mtspr (IBAT0L, lower);
case DBAT1:
mtspr (DBAT1L, lower);
mtspr (DBAT1U, upper);
+ batn = 1;
break;
case IBAT1:
mtspr (IBAT1L, lower);
case DBAT2:
mtspr (DBAT2L, lower);
mtspr (DBAT2U, upper);
+ batn = 2;
break;
case IBAT2:
mtspr (IBAT2L, lower);
case DBAT3:
mtspr (DBAT3L, lower);
mtspr (DBAT3U, upper);
+ batn = 3;
break;
case IBAT3:
mtspr (IBAT3L, lower);
case DBAT4:
mtspr (DBAT4L, lower);
mtspr (DBAT4U, upper);
+ batn = 4;
break;
case IBAT4:
mtspr (IBAT4L, lower);
case DBAT5:
mtspr (DBAT5L, lower);
mtspr (DBAT5U, upper);
+ batn = 5;
break;
case IBAT5:
mtspr (IBAT5L, lower);
case DBAT6:
mtspr (DBAT6L, lower);
mtspr (DBAT6U, upper);
+ batn = 6;
break;
case IBAT6:
mtspr (IBAT6L, lower);
case DBAT7:
mtspr (DBAT7L, lower);
mtspr (DBAT7U, upper);
+ batn = 7;
break;
case IBAT7:
mtspr (IBAT7L, lower);
return (-1);
}
+#ifdef CONFIG_ADDR_MAP
+ if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
+ phys_size_t size;
+ if (!BATU_VALID(upper))
+ size = 0;
+ else
+ size = BATU_SIZE(upper);
+ addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
+ size, batn);
+ }
+#endif
+
sync();
isync();
#include <status_led.h>
#endif
#include <net.h>
+#ifdef CONFIG_GENERIC_MMC
+#include <mmc.h>
+#endif
#include <serial.h>
#ifdef CONFIG_SYS_ALLOC_DPRAM
#if !defined(CONFIG_CPM2)
NULL, /* Terminate this list */
};
-#ifndef CONFIG_MAX_MEM_MAPPED
-#define CONFIG_MAX_MEM_MAPPED (256 << 20)
-#endif
ulong get_effective_memsize(void)
{
#ifndef CONFIG_VERY_BIG_RAM
*/
trap_init (dest_addr);
-#if defined(CONFIG_ADDR_MAP) && defined(CONFIG_E500)
+#ifdef CONFIG_ADDR_MAP
init_addr_map();
#endif
scsi_init ();
#endif
+#ifdef CONFIG_GENERIC_MMC
+ WATCHDOG_RESET ();
+ puts ("MMC: ");
+ mmc_initialize (bd);
+#endif
+
#if defined(CONFIG_CMD_DOC)
WATCHDOG_RESET ();
puts ("DOC: ");
start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
end = start_addr + size - 1;
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+ for (addr = start; (addr <= end) && (addr >= start);
+ addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
WATCHDOG_RESET();
}
/* wait for all dcbst to complete on bus */
asm volatile("sync" : : : "memory");
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+ for (addr = start; (addr <= end) && (addr >= start);
+ addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
WATCHDOG_RESET();
}
fi
echo "/* Automatically generated - do not edit */" >>config.h
echo "#include <configs/$1.h>" >>config.h
+echo "#include <asm/config.h>" >>config.h
exit 0
COBJS-y += rarp.o
COBJS-y += eth.o
COBJS-y += nfs.o
-COBJS-y += sntp.o
+COBJS-$(CONFIG_CMD_SNTP) += sntp.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
return target_dev;
}
+struct eth_device *eth_get_dev_by_index(int index)
+{
+ struct eth_device *dev, *target_dev;
+ int idx = 0;
+
+ if (!eth_devices)
+ return NULL;
+
+ dev = eth_devices;
+ target_dev = NULL;
+ do {
+ if (idx == index) {
+ target_dev = dev;
+ break;
+ }
+ dev = dev->next;
+ idx++;
+ } while (dev != eth_devices);
+
+ return target_dev;
+}
+
int eth_get_dev_index (void)
{
struct eth_device *dev;
#include "sntp.h"
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_SNTP)
-
#define SNTP_TIMEOUT 10000UL
static int SntpOurPort;
SntpSend ();
}
-
-#endif
projects / platform / kernel / u-boot.git / commitdiff