tegra20-trimslice.dtb \
tegra20-ventana.dtb \
tegra20-whistler.dtb \
- tegra20-colibri_t20_iris.dtb \
+ tegra20-colibri.dtb \
tegra30-apalis.dtb \
tegra30-beaver.dtb \
tegra30-cardhu.dtb \
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len);
+struct pmux_pingrp_desc {
+ u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+ u8 ctl_id;
+ u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
#define PMUX_SLWF_MIN 0
#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
-struct pmux_pingrp_desc {
- u8 funcs[4];
-#if defined(CONFIG_TEGRA20)
- u8 ctl_id;
- u8 pull_id;
-#endif /* CONFIG_TEGRA20 */
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+struct pmux_mipipadctrlgrp_config {
+ u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */
+ u32 func:8; /* function to assign PMUX_FUNC_... */
};
-extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+void pinmux_config_mipipadctrlgrp_table(
+ const struct pmux_mipipadctrlgrp_config *config, int len);
+
+struct pmux_mipipadctrlgrp_desc {
+ u8 funcs[2];
+};
+
+extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
#endif /* _TEGRA_PINMUX_H_ */
PMUX_DRVGRP_COUNT,
};
+enum pmux_mipipadctrlgrp {
+ PMUX_MIPIPADCTRLGRP_DSI_B,
+ PMUX_MIPIPADCTRLGRP_COUNT,
+};
+
enum pmux_func {
PMUX_FUNC_DEFAULT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
PMUX_FUNC_CPU,
+ PMUX_FUNC_CSI,
PMUX_FUNC_DAP,
PMUX_FUNC_DAP1,
PMUX_FUNC_DAP2,
PMUX_FUNC_DISPLAYA_ALT,
PMUX_FUNC_DISPLAYB,
PMUX_FUNC_DP,
+ PMUX_FUNC_DSI_B,
PMUX_FUNC_DTV,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
};
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
#define TEGRA_PMX_GRPS_HAVE_LPMD
#define TEGRA_PMX_GRPS_HAVE_SCHMT
#define TEGRA_PMX_GRPS_HAVE_HSM
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#ifdef __aarch64__
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-#endif
-
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define MACH_TYPE_CWME9210 3320
#define MACH_TYPE_CWME9210JS 3321
#define MACH_TYPE_PGS_SITARA 3322
-#define MACH_TYPE_COLIBRI_TEGRA2 3323
+#define MACH_TYPE_COLIBRI_T20 3323
#define MACH_TYPE_W21 3324
#define MACH_TYPE_POLYSAT1 3325
#define MACH_TYPE_DATAWAY 3326
# define machine_is_pgs_v1() (0)
#endif
-#ifdef CONFIG_MACH_COLIBRI_TEGRA2
+#ifdef CONFIG_MACH_COLIBRI_T20
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_COLIBRI_TEGRA2
+# define machine_arch_type MACH_TYPE_COLIBRI_T20
# endif
-# define machine_is_colibri_tegra2() (machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2)
+# define machine_is_colibri_t20() (machine_arch_type == MACH_TYPE_COLIBRI_T20)
#else
-# define machine_is_colibri_tegra2() (0)
+# define machine_is_colibri_t20() (0)
#endif
#ifdef CONFIG_MACH_W21
* Set up initial C runtime environment and call board_init_f(0).
*/
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
- sub x0, x0, #GD_SIZE /* allocate one GD above SP */
+ sub x18, x0, #GD_SIZE /* allocate one GD above SP */
+ bic x18, x18, #0x7 /* 8-byte alignment for GD */
+zero_gd:
+ sub x0, x0, #0x8
+ str xzr, [x0]
+ cmp x0, x18
+ b.gt zero_gd
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN
+ str x0, [x18, #GD_MALLOC_BASE]
+#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
- mov x18, sp /* GD is above SP */
mov x0, #0
bl board_init_f
#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
+#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4))
+
/*
* We could force arch-tegraNN/pinmux.h to define all of these. However,
* that's a lot of defines, and for now it's manageable to just put a
for (i = 0; i < len; i++)
pinmux_config_drvgrp(&config[i]);
}
-#endif /* TEGRA_PMX_HAS_DRVGRPS */
+#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
+
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+
+#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT))
+
+static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp,
+ enum pmux_func func)
+{
+ u32 *reg = MIPIPADCTRL_REG(grp);
+ int i, mux = -1;
+ u32 val;
+
+ if (func == PMUX_FUNC_DEFAULT)
+ return;
+
+ /* Error check grp and func */
+ assert(pmux_mipipadctrlgrp_isvalid(grp));
+ assert(pmux_func_isvalid(func));
+
+ if (func >= PMUX_FUNC_RSVD1) {
+ mux = (func - PMUX_FUNC_RSVD1) & 1;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 2; i++) {
+ if (tegra_soc_mipipadctrl_groups[grp].funcs[i]
+ == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ val = readl(reg);
+ val &= ~(1 << 1);
+ val |= (mux << 1);
+ writel(val, reg);
+}
+
+static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config)
+{
+ enum pmux_mipipadctrlgrp grp = config->grp;
+
+ pinmux_mipipadctrl_set_func(grp, config->func);
+}
+
+void pinmux_config_mipipadctrlgrp_table(
+ const struct pmux_mipipadctrlgrp_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_mipipadctrlgrp(&config[i]);
+}
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
+
+#define MIPIPADCTRL_GRP(grp, f0, f1) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ }, \
+ }
+
+#define MIPIPADCTRL_RESERVED {}
+
+static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = {
+ /* pin, f0, f1 */
+ /* Offset 0x820 */
+ MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B),
+};
+const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups;
config TARGET_WHISTLER
bool "NVIDIA Tegra20 Whistler evaluation board"
-config TARGET_COLIBRI_T20_IRIS
+config TARGET_COLIBRI_T20
bool "Toradex Colibri T20 board"
endchoice
source "board/compulab/trimslice/Kconfig"
source "board/nvidia/ventana/Kconfig"
source "board/nvidia/whistler/Kconfig"
-source "board/toradex/colibri_t20_iris/Kconfig"
+source "board/toradex/colibri_t20/Kconfig"
endif
break;
case FUNCMUX_NDFLASH_KBC_8_BIT:
pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
+ pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+ pinmux_tristate_disable(PMUX_PINGRP_KBCB);
pinmux_tristate_disable(PMUX_PINGRP_KBCC);
pinmux_tristate_disable(PMUX_PINGRP_KBCD);
pinmux_tristate_disable(PMUX_PINGRP_KBCE);
#include <netdev.h>
#include <asm/io.h>
#include <linux/compiler.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
DECLARE_GLOBAL_DATA_PTR;
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = V2M_UART0,
+ .type = TYPE_PL011,
+ .clock = 2400 * 1000,
+};
+
+U_BOOT_DEVICE(vexpress_serials) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
int board_init(void)
{
return 0;
void gpio_early_init_uart(void)
{
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
- gpio_request(GPIO_PI3, NULL);
+ gpio_request(GPIO_PI3, "uart_en");
gpio_direction_output(GPIO_PI3, 0);
}
#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Lucas Stach
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void colibri_t20_common_pin_mux_usb(void);
-if TARGET_COLIBRI_T20_IRIS
+if TARGET_COLIBRI_T20
config SYS_BOARD
- default "colibri_t20_iris"
+ default "colibri_t20"
config SYS_VENDOR
default "toradex"
config SYS_CONFIG_NAME
- default "colibri_t20_iris"
+ default "colibri_t20"
endif
--- /dev/null
+COLIBRI_T20
+M: Lucas Stach <dev@lynxeye.de>
+S: Maintained
+F: board/toradex/colibri_t20/
+F: include/configs/colibri_t20.h
+F: configs/colibri_t20_defconfig
+F: arch/arm/dts/tegra20-colibri.dtb
--- /dev/null
+#
+# (C) Copyright 2012 Lucas Stach
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y += colibri_t20.o
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/board.h>
+#include <asm/gpio.h>
-#include "colibri_t20-common.h"
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+ pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+
+ /*
+ * configure pingroup ATC to something unrelated to
+ * avoid ATC overriding KBC
+ */
+ pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
+}
+#endif
#ifdef CONFIG_USB_EHCI_TEGRA
-void colibri_t20_common_pin_mux_usb(void)
+void pin_mux_usb(void)
{
/* module internal USB bus to connect ethernet chipset */
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+
/* ULPI reference clock output */
pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+
/* PHY reset GPIO */
pinmux_tristate_disable(PMUX_PINGRP_UAC);
+
/* VBus GPIO */
pinmux_tristate_disable(PMUX_PINGRP_DTE);
-}
-#endif
-#ifdef CONFIG_TEGRA_NAND
-void pin_mux_nand(void)
-{
- funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+ /* Reset ASIX using LAN_RESET */
+ gpio_request(GPIO_PV4, "LAN_RESET");
+ gpio_direction_output(GPIO_PV4, 0);
+ pinmux_tristate_disable(PMUX_PINGRP_GPV);
+ udelay(5);
+ gpio_set_value(GPIO_PV4, 1);
+
+ /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
+ pinmux_tristate_disable(PMUX_PINGRP_SPIG);
}
#endif
+++ /dev/null
-COLIBRI_T20_IRIS BOARD
-M: Lucas Stach <dev@lynxeye.de>
-S: Maintained
-F: board/toradex/colibri_t20_iris/
-F: include/configs/colibri_t20_iris.h
-F: configs/colibri_t20_iris_defconfig
+++ /dev/null
-#
-# (C) Copyright 2012 Lucas Stach
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ../../nvidia/common/board.o
-obj-y += ../colibri_t20-common/colibri_t20-common.o
-obj-y += colibri_t20_iris.o
+++ /dev/null
-/*
- * Copyright (C) 2012 Lucas Stach
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/board.h>
-
-#include "../colibri_t20-common/colibri_t20-common.h"
-
-#ifdef CONFIG_USB_EHCI_TEGRA
-void pin_mux_usb(void)
-{
- colibri_t20_common_pin_mux_usb();
-
- /* USB 1 aka Tegra USB port 3 VBus*/
- pinmux_tristate_disable(PMUX_PINGRP_SPIG);
-}
-#endif
-
-#ifdef CONFIG_TEGRA_MMC
-/*
- * Routine: pin_mux_mmc
- * Description: setup the pin muxes/tristate values for the SDMMC(s)
- */
-void pin_mux_mmc(void)
-{
- funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
- pinmux_tristate_disable(PMUX_PINGRP_GMB);
-}
-#endif
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_COLIBRI_T20=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TEGRA=y
-CONFIG_TEGRA20=y
-CONFIG_TARGET_COLIBRI_T20_IRIS=y
-CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris"
/*
- * Copyright (C) 2012 Lucas Stach
+ * Copyright (C) 2012 Lucas Stach
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Colibri) # "
-#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris"
+#define V_PROMPT "Colibri T20 # "
+#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20"
/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_SDIO1
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T20
/* SD/MMC support */
#define CONFIG_MMC
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT
-#define CONFIG_USB_STORAGE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CACHE
+/* Miscellaneous commands */
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_FAT_WRITE
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 32
+
+#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
-#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
-
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
/* I2C */
#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H
+#define CONFIG_DM
+
/* We use generic board for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000)
/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
/* Ethernet Configuration */
#endif
/* PL011 Serial Configuration */
+#define CONFIG_BAUDRATE 115200
+#ifdef CONFIG_DM
+#define CONFIG_DM_SERIAL
+#define CONFIG_PL01X_SERIAL
+#else
+#define CONFIG_SYS_SERIAL0 V2M_UART0
+#define CONFIG_SYS_SERIAL1 V2M_UART1
+#define CONFIG_CONS_INDEX 0
#define CONFIG_PL011_SERIAL
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7273800
#endif
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
-#define CONFIG_CONS_INDEX 0
+#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_SERIAL0 V2M_UART0
run_list_real 1996 2000 +4
do_nandboot 760 756 -4
do_mem_crc 168 68 -100
- colibri_t20_iris: all -9 rodata -29 text +20
+ colibri_t20 : all -9 rodata -29 text +20
u-boot: add: 1/0, grow: 2/-3 bytes: 140/-112 (28)
function old new delta
hash_command 80 160 +80
projects / platform / kernel / u-boot.git / commitdiff