Convert CONFIG_NAND_OMAP_ECCSCHEME to Kconfig
authorTom Rini <trini@konsulko.com>
Wed, 22 Sep 2021 18:50:39 +0000 (14:50 -0400)
committerTom Rini <trini@konsulko.com>
Wed, 6 Oct 2021 13:16:24 +0000 (09:16 -0400)
The values of CONFIG_NAND_OMAP_ECCSCHEME map to the enum in
include/linux/mtd/omap_gpmc.h for valid ECC schemes.  Make which one we
will use be a choice statement, enumerating the ones which we have
implemented.

Signed-off-by: Tom Rini <trini@konsulko.com>
37 files changed:
configs/am335x_guardian_defconfig
configs/am3517_evm_defconfig
configs/am43xx_evm_defconfig
configs/am43xx_evm_rtconly_defconfig
configs/am43xx_evm_usbhost_boot_defconfig
configs/am43xx_hs_evm_defconfig
configs/devkit8000_defconfig
configs/etamin_defconfig
configs/igep00x0_defconfig
configs/omap35_logic_defconfig
configs/omap35_logic_somlv_defconfig
configs/omap3_beagle_defconfig
configs/omap3_evm_defconfig
configs/omap3_logic_defconfig
configs/omap3_logic_somlv_defconfig
doc/README.nand
drivers/mtd/nand/raw/Kconfig
include/configs/am335x_evm.h
include/configs/am335x_guardian.h
include/configs/am335x_igep003x.h
include/configs/am3517_evm.h
include/configs/am43xx_evm.h
include/configs/baltos.h
include/configs/brppt1.h
include/configs/chiliboard.h
include/configs/cm_t43.h
include/configs/devkit8000.h
include/configs/dra7xx_evm.h
include/configs/etamin.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_igep00x0.h
include/configs/omap3_logic.h
include/configs/phycore_am335x_r2.h
include/configs/siemens-am33x-common.h
include/configs/tam3517-common.h
include/configs/ti816x_evm.h

index 272d5b8..ea4032f 100644 (file)
@@ -88,6 +88,7 @@ CONFIG_MISC=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
index fa3c229..1bdebf5 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_DM_PCA953X=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index 98cd6b4..108db83 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
index 2ec0762..f558fd5 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
index c08e0b6..0b91f3a 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_MISC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
index 26c1b59..efa6cd0 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
index 1c067fd..ccdd4f6 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_TWL4030_LED=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index 65bdcf6..59a919b 100644 (file)
@@ -85,6 +85,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_COUNT=0x80
index 17e793c..8f6e13e 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_SYS_MTDPARTS_RUNTIME=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index fe37a98..9d8ac94 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index 29d1063..ee0c58a 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index 46a792f..80e2cc6 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_TWL4030_LED=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index 0174b3a..b89ab39 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index 18e87f1..becf862 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_OMAP36XX_PINS=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index f7470c1..ece92fe 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
index f6460db..ffcea90 100644 (file)
@@ -200,72 +200,6 @@ Platform specific options
        so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
         SPL-NAND driver with software ECC correction support.
 
-   CONFIG_NAND_OMAP_ECCSCHEME
-       On OMAP platforms, this CONFIG specifies NAND ECC scheme.
-       It can take following values:
-       OMAP_ECC_HAM1_CODE_SW
-               1-bit Hamming code using software lib.
-               (for legacy devices only)
-       OMAP_ECC_HAM1_CODE_HW
-               1-bit Hamming code using GPMC hardware.
-               (for legacy devices only)
-       OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
-               4-bit BCH code (unsupported)
-       OMAP_ECC_BCH4_CODE_HW
-               4-bit BCH code (unsupported)
-       OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-               8-bit BCH code with
-               - ecc calculation using GPMC hardware engine,
-               - error detection using software library.
-               - requires CONFIG_BCH to enable software BCH library
-               (For legacy device which do not have ELM h/w engine)
-       OMAP_ECC_BCH8_CODE_HW
-               8-bit BCH code with
-               - ecc calculation using GPMC hardware engine,
-               - error detection using ELM hardware engine.
-       OMAP_ECC_BCH16_CODE_HW
-               16-bit BCH code with
-               - ecc calculation using GPMC hardware engine,
-               - error detection using ELM hardware engine.
-
-       How to select ECC scheme on OMAP and AMxx platforms ?
-       -----------------------------------------------------
-       Though higher ECC schemes have more capability to detect and correct
-       bit-flips, but still selection of ECC scheme is dependent on following
-       - hardware engines present in SoC.
-               Some legacy OMAP SoC do not have ELM h/w engine thus such
-               SoC cannot support BCHx_HW ECC schemes.
-       - size of OOB/Spare region
-               With higher ECC schemes, more OOB/Spare area is required to
-               store ECC. So choice of ECC scheme is limited by NAND oobsize.
-
-       In general following expression can help:
-               NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
-       where
-               NAND_OOBSIZE    = number of bytes available in
-                               OOB/spare area per NAND page.
-               NAND_PAGESIZE   = bytes in main-area of NAND page.
-               ECC_BYTES       = number of ECC bytes generated to
-                               protect 512 bytes of data, which is:
-                               3 for HAM1_xx ecc schemes
-                               7 for BCH4_xx ecc schemes
-                               14 for BCH8_xx ecc schemes
-                               26 for BCH16_xx ecc schemes
-
-               example to check for BCH16 on 2K page NAND
-               NAND_PAGESIZE = 2048
-               NAND_OOBSIZE = 64
-               2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
-               Thus BCH16 cannot be supported on 2K page NAND.
-
-               However, for 4K pagesize NAND
-               NAND_PAGESIZE = 4096
-               NAND_OOBSIZE = 224
-               ECC_BYTES = 26
-               2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
-               Thus BCH16 can be supported on 4K page NAND.
-
-
     CONFIG_NAND_OMAP_GPMC_PREFETCH
        On OMAP platforms that use the GPMC controller
        (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
index 2e6fe14..790ee34 100644 (file)
@@ -156,9 +156,10 @@ config NAND_OMAP_GPMC
          do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
          and BCH16 ECC algorithms.
 
+if NAND_OMAP_GPMC
+
 config NAND_OMAP_GPMC_PREFETCH
        bool "Enable GPMC Prefetch"
-       depends on NAND_OMAP_GPMC
        default y
        help
          On OMAP platforms that use the GPMC controller
@@ -167,7 +168,7 @@ config NAND_OMAP_GPMC_PREFETCH
 
 config NAND_OMAP_ELM
        bool "Enable ELM driver for OMAPxx and AMxx platforms."
-       depends on NAND_OMAP_GPMC && !OMAP34XX
+       depends on !OMAP34XX
        help
          ELM controller is used for ECC error detection (not ECC calculation)
          of BCH4, BCH8 and BCH16 ECC algorithms.
@@ -176,6 +177,104 @@ config NAND_OMAP_ELM
          detection. However ECC calculation on such plaforms would still be
          done by GPMC controller.
 
+choice
+       prompt "ECC scheme"
+       default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+       help
+       On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+       It can take following values:
+       OMAP_ECC_HAM1_CODE_SW
+               1-bit Hamming code using software lib.
+               (for legacy devices only)
+       OMAP_ECC_HAM1_CODE_HW
+               1-bit Hamming code using GPMC hardware.
+               (for legacy devices only)
+       OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+               4-bit BCH code (unsupported)
+       OMAP_ECC_BCH4_CODE_HW
+               4-bit BCH code (unsupported)
+       OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+               8-bit BCH code with
+               - ecc calculation using GPMC hardware engine,
+               - error detection using software library.
+               - requires CONFIG_BCH to enable software BCH library
+               (For legacy device which do not have ELM h/w engine)
+       OMAP_ECC_BCH8_CODE_HW
+               8-bit BCH code with
+               - ecc calculation using GPMC hardware engine,
+               - error detection using ELM hardware engine.
+       OMAP_ECC_BCH16_CODE_HW
+               16-bit BCH code with
+               - ecc calculation using GPMC hardware engine,
+               - error detection using ELM hardware engine.
+
+       How to select ECC scheme on OMAP and AMxx platforms ?
+       -----------------------------------------------------
+       Though higher ECC schemes have more capability to detect and correct
+       bit-flips, but still selection of ECC scheme is dependent on following
+       - hardware engines present in SoC.
+               Some legacy OMAP SoC do not have ELM h/w engine thus such
+               SoC cannot support BCHx_HW ECC schemes.
+       - size of OOB/Spare region
+               With higher ECC schemes, more OOB/Spare area is required to
+               store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+       In general following expression can help:
+               NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+       where
+               NAND_OOBSIZE    = number of bytes available in
+                               OOB/spare area per NAND page.
+               NAND_PAGESIZE   = bytes in main-area of NAND page.
+               ECC_BYTES       = number of ECC bytes generated to
+                               protect 512 bytes of data, which is:
+                               3 for HAM1_xx ecc schemes
+                               7 for BCH4_xx ecc schemes
+                               14 for BCH8_xx ecc schemes
+                               26 for BCH16_xx ecc schemes
+
+               example to check for BCH16 on 2K page NAND
+               NAND_PAGESIZE = 2048
+               NAND_OOBSIZE = 64
+               2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+               Thus BCH16 cannot be supported on 2K page NAND.
+
+               However, for 4K pagesize NAND
+               NAND_PAGESIZE = 4096
+               NAND_OOBSIZE = 224
+               ECC_BYTES = 26
+               2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+               Thus BCH16 can be supported on 4K page NAND.
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+       bool "1-bit Hamming code using software lib"
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+       bool "1-bit Hamming code using GPMC hardware"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+       bool "8-bit BCH code with HW calculation SW error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+       bool "8-bit BCH code with HW calculation and error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+       bool "16-bit BCH code with HW calculation and error detection"
+
+endchoice
+
+config NAND_OMAP_ECCSCHEME
+       int
+       default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+       default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+       default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+       default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+       default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+       help
+         This must be kept in sync with the enum in
+         include/linux/mtd/omap_gpmc.h
+
+endif
+
 config NAND_VF610_NFC
        bool "Support for Freescale NFC for VF610"
        select SYS_NAND_SELF_INIT
index dc8c3e2..7fb1b3a 100644 (file)
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 /* NAND: SPL related configs */
 #ifdef CONFIG_SPL_OS_BOOT
 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS        0x00200000 /* kernel offset */
index fd7d589..68b4e4f 100644 (file)
                        }
 #define CONFIG_SYS_NAND_ECCSIZE         512
 #define CONFIG_SYS_NAND_ECCBYTES        26
-#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH16_CODE_HW
 #define MTDIDS_DEFAULT                  "nand0=nand.0"
 
 #endif /* CONFIG_MTD_RAW_NAND */
index 4a303b7..339a975 100644 (file)
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 
 #endif /* ! __CONFIG_IGEP003X_H */
index 3b70741..bf01a77 100644 (file)
@@ -28,7 +28,6 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       13
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 #define CONFIG_SYS_NAND_MAX_OOBFREE    2
 #define CONFIG_SYS_NAND_MAX_ECCPOS     56
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
index 5b7418b..7bea61e 100644 (file)
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH16_CODE_HW
 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
                                10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
                                20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
index f55f57c..32f2174 100644 (file)
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #endif
 #endif
index caedd30..4c56a8a 100644 (file)
@@ -144,7 +144,6 @@ NANDTGTS \
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x8000000
 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_ECCPOS         {2, 3, 4, 5, 6, 7, 8, 9, \
                                        10, 11, 12, 13, 14, 15, 16, 17, \
                                        18, 19, 20, 21, 22, 23, 24, 25, \
index c7b2131..49a8d71 100644 (file)
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 /* NAND: SPL related configs */
 
 /* USB configuration */
index 49916c9..e250dc9 100644 (file)
@@ -24,7 +24,6 @@
 /* NAND support */
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_ECCPOS         { 2, 3, 4, 5, 6, 7, 8, 9, \
                                         10, 11, 12, 13, 14, 15, 16, 17, \
                                         18, 19, 20, 21, 22, 23, 24, 25, \
index 8113d75..591a33f 100644 (file)
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       3
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_HAM1_CODE_HW
 
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    0x200000
 
index 11ef07c..c54f375 100644 (file)
@@ -81,7 +81,6 @@
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_ECCPOS         { 2, 3, 4, 5, 6, 7, 8, 9, \
                                         10, 11, 12, 13, 14, 15, 16, 17, \
                                         18, 19, 20, 21, 22, 23, 24, 25, \
index 20a8e26..3ff86ee 100644 (file)
@@ -16,8 +16,6 @@
 /* NAND specific changes for etamin due to different page size */
 #undef CONFIG_SYS_NAND_ECCPOS
 #undef CONFIG_SYS_ENV_SECT_SIZE
-#undef CONFIG_NAND_OMAP_ECCSCHEME
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH16_CODE_HW
 
 #define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
index 86fc8ed..158773a 100644 (file)
@@ -26,7 +26,6 @@
                                          10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE         512
 #define CONFIG_SYS_NAND_ECCBYTES        3
-#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
 /* NAND: SPL falcon mode configs */
 #if defined(CONFIG_SPL_OS_BOOT)
index 8d1233c..eeb9ef8 100644 (file)
@@ -31,7 +31,6 @@
                                          10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE         512
 #define CONFIG_SYS_NAND_ECCBYTES        3
-#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 #define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
 /* NAND: SPL falcon mode configs */
 #if defined(CONFIG_SPL_OS_BOOT)
index ced449d..c1ef040 100644 (file)
@@ -84,6 +84,5 @@
                                         50, 51, 52, 53, 54, 55, 56, 57, }
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 
 #endif /* __IGEP00X0_H */
index 0da7388..e71f737 100644 (file)
@@ -27,7 +27,6 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       13
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 #define CONFIG_SYS_NAND_MAX_OOBFREE    2
 #define CONFIG_SYS_NAND_MAX_ECCPOS     56
 #endif
index 935bb7a..af6f7e1 100644 (file)
@@ -96,7 +96,6 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 
 /* NAND: SPL related configs */
 #ifdef CONFIG_SPL_OS_BOOT
index fd74d57..615458c 100644 (file)
@@ -82,7 +82,6 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 
 #define CONFIG_SYS_NAND_ECCSTEPS       4
 #define        CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * \
index ede7199..a47e2c5 100644 (file)
                                         56, 57, 58, 59, 60, 61, 62, 63}
 #define CONFIG_SYS_NAND_ECCSIZE                256
 #define CONFIG_SYS_NAND_ECCBYTES       3
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_HAM1_CODE_SW
 
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 
index 5964b59..fa99152 100644 (file)
@@ -68,7 +68,6 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
-#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
 
 /* SPL */
 /* Defines for SPL */