config ARCH_AT91
bool "Atmel AT91"
+ select SPL_BOARD_INIT if SPL
config TARGET_EDB93XX
bool "Support edb93xx"
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7
+ imply CMD_HASH
config TARGET_BCMNSP
bool "Support bcmnsp"
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
select CPU_V7
+ select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
imply FIT
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_MMC_SUPPORT if GENERIC_MMC
+ imply SPL_MMC_SUPPORT if MMC
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
+ select SPL_BOARD_INIT if SPL
select SPL_OF_CONTROL if SPL
select DM
select DM_ETH
select DM_SERIAL
select SUPPORT_SPL
select CLK
+ select SPL_BOARD_INIT if SPL
select SPL_CLK
select DM_USB if USB
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
+ config TARGET_LS2081ARDB
+ bool "Support ls2081ardb"
+ select ARCH_LS2080A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select ARCH_MISC_INIT
+ help
+ Support for Freescale LS2081ARDB platform.
+ The LS2081A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2081A/LS2041A
+ Layerscape Architecture processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
select OF_CONTROL
select OF_LIBFDT
select PINCTRL
+ select SPL_BOARD_INIT if SPL
select SPL_DM if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
+ socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_mcvevk.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
- fsl-ls2080a-rdb.dtb
+ fsl-ls2080a-rdb.dtb \
+ fsl-ls2081a-rdb.dtb \
+ fsl-ls2088a-rdb-qspi.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb
-dtb-$(CONFIG_MX7) += imx7-colibri.dtb
+dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
+ imx7d-sdb.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define CONFIG_SPI_FLASH_SPANSION
- #define CONFIG_SPI_FLASH_BAR
- #define FSL_QSPI_FLASH_SIZE (1 << 24)
+ #define FSL_QSPI_FLASH_SIZE SZ_64M
#define FSL_QSPI_FLASH_NUM 2
/*
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* Command line configuration */
-#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_HZ 1000
#endif
#ifdef CONFIG_QSPI_BOOT
- #define CONFIG_SYS_TEXT_BASE 0x40010000
+ #define CONFIG_SYS_TEXT_BASE 0x40100000
#endif
#ifdef CONFIG_NAND_BOOT
/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_FSL_DEVICE_DISABLE
- #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
+ #define CONFIG_SYS_QE_FW_ADDR 0x60940000
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SD_BOOT)
- #define CONFIG_ENV_OFFSET 0x100000
+ #define CONFIG_ENV_OFFSET 0x300000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_MISC_INIT_R
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#endif
#ifdef CONFIG_QSPI_BOOT
- #define CONFIG_SYS_TEXT_BASE 0x40010000
+ #define CONFIG_SYS_TEXT_BASE 0x40100000
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
- #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
+ #define CONFIG_SYS_QE_FW_ADDR 0x60940000
/*
* Environment
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SD_BOOT)
- #define CONFIG_ENV_OFFSET 0x100000
+ #define CONFIG_ENV_OFFSET 0x300000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_ENV_OFFSET 0x100000
+ #define CONFIG_ENV_OFFSET 0x300000
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_MISC_INIT_R
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#endif
/* Command line configuration */
-#ifndef SPL_NO_ENV
-#define CONFIG_CMD_ENV
-#endif
/* MMC */
#ifndef SPL_NO_MMC
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_NAND_BOOT
- /* Store Fman ucode at offeset 0x160000(11 blocks). */
+ /* Store Fman ucode at offeset 0x900000(72 blocks). */
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
- #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+ #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 1MB (2040 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
+ * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
- #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+ #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
- #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+ #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 1000000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
- #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
+ #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#endif /* __LS1043A_COMMON_H */
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4
+ /* PCIe */
+ #define CONFIG_PCIE1 /* PCIE controller 1 */
+ #define CONFIG_PCIE2 /* PCIE controller 2 */
+ #define CONFIG_PCIE3 /* PCIE controller 3 */
+
+ #ifdef CONFIG_PCI
+ #define CONFIG_PCI_SCAN_SHOW
+ #define CONFIG_CMD_PCI
+ #endif
+
/* Command line configuration */
-#ifndef SPL_NO_ENV
-#define CONFIG_CMD_ENV
-#endif
/* MMC */
#ifndef SPL_NO_MMC
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
- #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+ #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
- #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000
+ #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 1000000
#define CONFIG_ENV_SPI_MODE 0x03
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
- #define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+ #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
- #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
+ #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#endif /* __LS1046A_COMMON_H */
/*
+ * Copyright 2017 NXP
* Copyright (C) 2014 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
#else
#define CONFIG_SYS_TEXT_BASE 0x30100000
#endif
+ #else
+ #define CONFIG_SYS_TEXT_BASE 0x20100000
+ #define CONFIG_ENV_IS_IN_SPI_FLASH
+ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
+ #define CONFIG_ENV_SECT_SIZE 0x10000
#endif
#define CONFIG_SUPPORT_RAW_INITRD
#endif
/* Command line configuration */
-#define CONFIG_CMD_ENV
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581200000\0" \
+ "kernel_start=0x581000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"console=ttyAMA0,38400n8\0" \
- "mcinitcmd=fsl_mc start mc 0x580300000" \
- " 0x580800000 \0"
+ "mcinitcmd=fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
- #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
+ #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#endif /* __LS2_COMMON_H */
/*
+ * Copyright 2017 NXP
* Copyright 2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
- #if defined(CONFIG_QSPI_BOOT)
- #define CONFIG_SYS_TEXT_BASE 0x20010000
- #define CONFIG_ENV_IS_IN_SPI_FLASH
- #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
- #define CONFIG_ENV_SECT_SIZE 0x10000
- #else
+ #ifndef CONFIG_QSPI_BOOT
#define CONFIG_ENV_IS_IN_FLASH
- #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#endif
/* EEPROM */
#define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581100000\0" \
+ "kernel_start=0x581000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
- "mcinitcmd=esbc_validate 0x580c80000;" \
- "esbc_validate 0x580cc0000;" \
- "fsl_mc start mc 0x580300000" \
- " 0x580800000 \0"
+ "mcinitcmd=esbc_validate 0x580700000;" \
+ "esbc_validate 0x580740000;" \
+ "fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581100000\0" \
+ "kernel_start=0x581000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
- "mcinitcmd=fsl_mc start mc 0x580300000" \
- " 0x580800000 \0"
+ "mcinitcmd=fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0"
#endif /* CONFIG_SECURE_BOOT */
/*
+ * Copyright 2017 NXP
* Copyright 2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 2
+ #ifdef CONFIG_FSL_QSPI
+ #ifdef CONFIG_TARGET_LS2081ARDB
+ #define CONFIG_QIXIS_I2C_ACCESS
+ #endif
+ #define CONFIG_SYS_I2C_EARLY_INIT
+ #define CONFIG_DISPLAY_BOARDINFO_LATE
+ #endif
+
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_VOL_MONITOR_ADDR 0x38
#define CONFIG_VOL_MONITOR_IR36021_READ
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
+ #ifndef CONFIG_FSL_QSPI
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_ENV_IS_IN_FLASH
- #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#endif
/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
-
+ #endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+ #ifdef CONFIG_TARGET_LS2081ARDB
+ #define CONFIG_FSL_QIXIS /* use common QIXIS code */
+ #define QIXIS_QMAP_MASK 0x07
+ #define QIXIS_QMAP_SHIFT 5
+ #define QIXIS_LBMAP_DFLTBANK 0x00
+ #define QIXIS_LBMAP_QSPI 0x00
+ #define QIXIS_RCW_SRC_QSPI 0x62
+ #define QIXIS_LBMAP_ALTBANK 0x20
+ #define QIXIS_RST_CTL_RESET 0x31
+ #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+ #define QIXIS_LBMAP_MASK 0x0f
+ #define QIXIS_RST_CTL_RESET_EN 0x30
+ #endif
+
/*
* I2C
*/
+ #ifdef CONFIG_TARGET_LS2081ARDB
+ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+ #endif
#define I2C_MUX_PCA_ADDR 0x75
#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
- #ifdef CONFIG_FSL_DSPI
+ #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH
- #define CONFIG_SPI_FLASH_BAR
+ #ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
+ #ifdef CONFIG_FSL_QSPI
+ #ifdef CONFIG_TARGET_LS2081ARDB
+ #define CONFIG_SPI_FLASH_STMICRO
+ #else
+ #define CONFIG_SPI_FLASH_SPANSION
+ #endif
+ #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
+ #define FSL_QSPI_FLASH_NUM 2
+ #endif
+ #endif
/*
* RTC configuration
*/
#define RTC
+ #ifdef CONFIG_TARGET_LS2081ARDB
+ #define CONFIG_RTC_PCF8563 1
+ #define CONFIG_SYS_I2C_RTC_ADDR 0x51
+ #else
#define CONFIG_RTC_DS3231 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+ #endif
/* EEPROM */
#define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581100000\0" \
+ "kernel_start=0x581000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
"fdtfile=fsl-ls2080a-rdb.dtb\0" \
- "mcinitcmd=esbc_validate 0x580c80000;" \
- "esbc_validate 0x580cc0000;" \
- "fsl_mc start mc 0x580300000" \
- " 0x580800000 \0" \
+ "mcinitcmd=esbc_validate 0x580700000;" \
+ "esbc_validate 0x580740000;" \
+ "fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0" \
+ BOOTENV
+ #else
+ #ifdef CONFIG_QSPI_BOOT
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "scriptaddr=0x80800000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "pxefile_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "ramdisk_addr_r=0x89000000\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x21000000\0" \
+ "mcmemsize=0x40000000\0" \
+ "mcinitcmd=fsl_mc start mc 0x20a00000" \
+ " 0x20e00000 \0" \
BOOTENV
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581100000\0" \
+ "kernel_start=0x581000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
"fdtfile=fsl-ls2080a-rdb.dtb\0" \
- "mcinitcmd=fsl_mc start mc 0x580300000" \
- " 0x580800000 \0" \
+ "mcinitcmd=fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0" \
BOOTENV
#endif
+ #endif
#undef CONFIG_BOOTARGS
" hugepagesz=2m hugepages=256"
#undef CONFIG_BOOTCOMMAND
+ #ifdef CONFIG_QSPI_BOOT
+ /* Try to boot an on-QSPI kernel first, then do normal distro boot */
+ #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
+ " && bootm $kernel_start" \
+ " || run distro_bootcmd"
+ #else
/* Try to boot an on-NOR kernel first, then do normal distro boot */
- #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
+ #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \
" && cp.b $kernel_start $kernel_load $kernel_size" \
" && bootm $kernel_load" \
" || run distro_bootcmd"
+ #endif
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHY_CORTINA
#define CONFIG_PHYLIB
#define CONFIG_SYS_CORTINA_FW_IN_NOR
- #define CONFIG_CORTINA_FW_ADDR 0x581000000
+ #ifdef CONFIG_QSPI_BOOT
+ #define CONFIG_CORTINA_FW_ADDR 0x20980000
+ #else
+ #define CONFIG_CORTINA_FW_ADDR 0x580980000
+ #endif
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define CORTINA_PHY_ADDR1 0x10
projects / platform / kernel / u-boot.git / commitdiff