include/configs/tuxx1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2008
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  *
  15  * (C) Copyright 2010-2013
  16  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  17  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_KM_BOARD_NAME    "tuxx1"
  27 #define CONFIG_HOSTNAME         "tuxx1"
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_QE       /* Has QE */
  33 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  34
  35 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  36
  37 /* include common defines/options for all Keymile boards */
  38 #include "km/keymile-common.h"
  39 #include "km/km-powerpc.h"
  40
  41 /*
  42  * System Clock Setup
  43  */
  44 #define CONFIG_83XX_CLKIN               66000000
  45 #define CONFIG_SYS_CLK_FREQ             66000000
  46 #define CONFIG_83XX_PCICLK              66000000
  47
  48 /*
  49  * IMMR new address
  50  */
  51 #define CONFIG_SYS_IMMR         0xE0000000
  52
  53 /*
  54  * Bus Arbitration Configuration Register (ACR)
  55  */
  56 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  57 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  58 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  59 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  65 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  67
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  69 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  70                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  71
  72 #define CFG_83XX_DDR_USES_CS0
  73
  74 /*
  75  * Manually set up DDR parameters
  76  */
  77 #define CONFIG_DDR_II
  78 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  79
  80 /*
  81  * The reserved memory
  82  */
  83 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  84 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  85
  86 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  87 #define CONFIG_SYS_RAMBOOT
  88 #endif
  89
  90 /* Reserve 768 kB for Mon */
  91 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  92
  93 /*
  94  * Initial RAM Base Address Setup
  95  */
  96 #define CONFIG_SYS_INIT_RAM_LOCK
  97 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  98 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  99 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 100                                                 GENERATED_GBL_DATA_SIZE)
 101
 102 /*
 103  * Init Local Bus Memory Controller:
 104  *
 105  * Bank Bus     Machine PortSz  Size  Device
 106  * ---- ---     ------- ------  -----  ------
 107  *  0   Local   GPCM    16 bit  256MB FLASH
 108  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 109  *
 110  */
 111 /*
 112  * FLASH on the Local Bus
 113  */
 114 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 115
 116 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 117 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 118
 119 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 120                                 BR_PS_16 | /* 16 bit port size */ \
 121                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 122                                 BR_V)
 123
 124 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 125                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 126                                 OR_GPCM_SCY_5 | \
 127                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 128
 129 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 130 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 131 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 132
 133 /*
 134  * PRIO1/PIGGY on the local bus CS1
 135  */
 136 /* Window base at flash base */
 137 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 138 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 139
 140 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 141                                 BR_PS_8 | /* 8 bit port size */ \
 142                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 143                                 BR_V)
 144 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 145                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 146                                 OR_GPCM_SCY_2 | \
 147                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 148
 149 /*
 150  * Serial Port
 151  */
 152 #define CONFIG_SYS_NS16550_SERIAL
 153 #define CONFIG_SYS_NS16550_REG_SIZE     1
 154 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 155
 156 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 157 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 158
 159 /*
 160  * QE UEC ethernet configuration
 161  */
 162 #define CONFIG_UEC_ETH
 163 #define CONFIG_ETHPRIME         "UEC0"
 164
 165 #define CONFIG_UEC_ETH1         /* GETH1 */
 166 #define UEC_VERBOSE_DEBUG       1
 167
 168 #ifdef CONFIG_UEC_ETH1
 169 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 170 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 171 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 172 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 173 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 174 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 175 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 176 #endif
 177
 178 /*
 179  * Environment
 180  */
 181
 182 #ifndef CONFIG_SYS_RAMBOOT
 183 #ifndef CONFIG_ENV_ADDR
 184 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 185                                         CONFIG_SYS_MONITOR_LEN)
 186 #endif
 187 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 188 #ifndef CONFIG_ENV_OFFSET
 189 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 190 #endif
 191
 192 /* Address and size of Redundant Environment Sector     */
 193 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 194                                                 CONFIG_ENV_SECT_SIZE)
 195 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 196
 197 #else /* CFG_SYS_RAMBOOT */
 198 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 199 #define CONFIG_ENV_SIZE         0x2000
 200 #endif /* CFG_SYS_RAMBOOT */
 201
 202 /* I2C */
 203 #define CONFIG_SYS_I2C
 204 #define CONFIG_SYS_NUM_I2C_BUSES        4
 205 #define CONFIG_SYS_I2C_MAX_HOPS         1
 206 #define CONFIG_SYS_I2C_FSL
 207 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 208 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 209 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 210 #define CONFIG_SYS_I2C_OFFSET           0x3000
 211 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 212 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 213 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 214 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 215                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 216                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 217                 {1, {I2C_NULL_HOP} } }
 218
 219 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 220
 221 #if defined(CONFIG_CMD_NAND)
 222 #define CONFIG_NAND_KMETER1
 223 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 224 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 225 #endif
 226
 227 /*
 228  * For booting Linux, the board info and command line data
 229  * have to be in the first 8 MB of memory, since this is
 230  * the maximum mapped by the Linux kernel during initialization.
 231  */
 232 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 233
 234 /*
 235  * Core HID Setup
 236  */
 237 #define CONFIG_SYS_HID0_INIT            0x000000000
 238 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 239                                          HID0_ENABLE_INSTRUCTION_CACHE)
 240 #define CONFIG_SYS_HID2                 HID2_HBE
 241
 242 /*
 243  * MMU Setup
 244  */
 245
 246 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 247
 248 /* DDR: cache cacheable */
 249 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 250                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 251 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 252                                         BATU_VS | BATU_VP)
 253 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 254 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 255
 256 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 257 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 258                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 259 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 260                                         | BATU_VP)
 261 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 262 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 263
 264 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 265 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 266                                 BATL_MEMCOHERENCE)
 267 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 268                                 BATU_VS | BATU_VP)
 269 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 270                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 271 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 272
 273 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 274 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 275                                         BATL_MEMCOHERENCE)
 276 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 277                                         BATU_VS | BATU_VP)
 278 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 279                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 280 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 281
 282 /* Stack in dcache: cacheable, no memory coherence */
 283 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 284 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 285                                         BATU_VS | BATU_VP)
 286 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 287 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 288
 289 /*
 290  * Internal Definitions
 291  */
 292 #define BOOTFLASH_START 0xF0000000
 293
 294 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 295
 296 /*
 297  * Environment Configuration
 298  */
 299 #define CONFIG_ENV_OVERWRITE
 300 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 301 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 302 #endif
 303
 304 #ifndef CONFIG_KM_DEF_ARCH
 305 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 306 #endif
 307
 308 #define CONFIG_EXTRA_ENV_SETTINGS \
 309         CONFIG_KM_DEF_ENV                                               \
 310         CONFIG_KM_DEF_ARCH                                              \
 311         "newenv="                                                       \
 312                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 313                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 314         "unlock=yes\0"                                                  \
 315         ""
 316
 317 #if defined(CONFIG_UEC_ETH)
 318 #define CONFIG_HAS_ETH0
 319 #endif
 320
 321 /*
 322  * System IO Config
 323  */
 324 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 325
 326 #define CONFIG_SYS_DDRCDR (\
 327         DDRCDR_EN | \
 328         DDRCDR_PZ_MAXZ | \
 329         DDRCDR_NZ_MAXZ | \
 330         DDRCDR_M_ODR)
 331
 332 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 333 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 334                                          SDRAM_CFG_32_BE | \
 335                                          SDRAM_CFG_SREN | \
 336                                          SDRAM_CFG_HSE)
 337
 338 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 339 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 340 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 341                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 342
 343 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 344                                          CSCONFIG_ODT_WR_CFG | \
 345                                          CSCONFIG_ROW_BIT_13 | \
 346                                          CSCONFIG_COL_BIT_10)
 347
 348 #define CONFIG_SYS_DDR_MODE     0x47860242
 349 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 350
 351 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 352                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 353                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 354                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 355                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 356                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 357                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 358                                  (0 << TIMING_CFG0_RWT_SHIFT))
 359
 360 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 361                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 362                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 363                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 364                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 365                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 366                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 367                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 368
 369 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 370                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 371                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 372                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 373                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 374                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 375                                  (5 << TIMING_CFG2_CPO_SHIFT))
 376
 377 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 378
 379 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 380 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 381
 382 /* EEprom support */
 383 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 384
 385 /*
 386  * Local Bus Configuration & Clock Setup
 387  */
 388 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 389 #define CONFIG_SYS_LCRR_EADC    0x00010000
 390 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 391
 392 #define CONFIG_SYS_LBC_LBCR     0x00000000
 393
 394 /*
 395  * MMU Setup
 396  */
 397 #define CONFIG_SYS_IBAT7L       (0)
 398 #define CONFIG_SYS_IBAT7U       (0)
 399 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 400 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 401
 402 #define CONFIG_SYS_APP1_BASE    0xA0000000    /* PAXG */
 403 #define CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 404 #define CONFIG_SYS_APP2_BASE    0xB0000000    /* PINC3 */
 405 #define CONFIG_SYS_APP2_SIZE    256 /* Megabytes */
 406
 407 /*
 408  * Init Local Bus Memory Controller:
 409  *                                    Device on board
 410  * Bank Bus     Machine PortSz Size   TUDA1  TUXA1  TUGE1   KMSUPX4 KMOPTI2
 411  * -----------------------------------------------------------------------------
 412  *  2   Local   GPCM    8 bit  256MB  PAXG   LPXF   PAXI    LPXF    PAXE
 413  *  3   Local   GPCM    8 bit  256MB  PINC3  PINC2  unused  unused  OPI2(16 bit)
 414  *
 415  *                                    Device on board (continued)
 416  * Bank Bus     Machine PortSz Size   KMTEPR2
 417  * -----------------------------------------------------------------------------
 418  *  2   Local   GPCM    8 bit  256MB  NVRAM
 419  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
 420  */
 421
 422 /*
 423  * Configuration for C2 on the local bus
 424  */
 425 /* Window base at flash base */
 426 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
 427 /* Window size: 256 MB */
 428 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 429
 430 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 431                                  BR_PS_8 | \
 432                                  BR_MS_GPCM | \
 433                                  BR_V)
 434
 435 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
 436                                  OR_GPCM_CSNT | \
 437                                  OR_GPCM_ACS_DIV4 | \
 438                                  OR_GPCM_SCY_2 | \
 439                                  OR_GPCM_TRLX_SET | \
 440                                  OR_GPCM_EHTR_CLEAR | \
 441                                  OR_GPCM_EAD)
 442
 443 /*
 444  * Configuration for C3 on the local bus
 445  */
 446 /* Access window base at PINC3 base */
 447 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 448 /* Window size: 256 MB */
 449 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 450
 451 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 452                                  BR_PS_8 |              \
 453                                  BR_MS_GPCM |           \
 454                                  BR_V)
 455
 456 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 457                                  OR_GPCM_CSNT | \
 458                                  OR_GPCM_ACS_DIV2 | \
 459                                  OR_GPCM_SCY_2 | \
 460                                  OR_GPCM_TRLX_SET | \
 461                                  OR_GPCM_EHTR_CLEAR)
 462
 463 #define CONFIG_SYS_MAMR         (MxMR_GPL_x4DIS | \
 464                                  0x0000c000 | \
 465                                  MxMR_WLFx_2X)
 466
 467 /*
 468  * MMU Setup
 469  */
 470 /* APP1: icache cacheable, but dcache-inhibit and guarded */
 471 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | \
 472                                  BATL_PP_RW | \
 473                                  BATL_MEMCOHERENCE)
 474 /* 512M should also include APP2... */
 475 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | \
 476                                  BATU_BL_256M | \
 477                                  BATU_VS | \
 478                                  BATU_VP)
 479 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | \
 480                                  BATL_PP_RW | \
 481                                  BATL_CACHEINHIBIT | \
 482                                  BATL_GUARDEDSTORAGE)
 483 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 484
 485 /* APP2:  icache cacheable, but dcache-inhibit and guarded */
 486 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | \
 487                                  BATL_PP_RW | \
 488                                  BATL_MEMCOHERENCE)
 489 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | \
 490                                  BATU_BL_256M | \
 491                                  BATU_VS | \
 492                                  BATU_VP)
 493 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | \
 494                                  BATL_PP_RW | \
 495                                  BATL_CACHEINHIBIT | \
 496                                  BATL_GUARDEDSTORAGE)
 497 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 498
 499 #define CONFIG_SYS_IBAT7L       (0)
 500 #define CONFIG_SYS_IBAT7U       (0)
 501 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 502 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 503
 504 #endif /* __CONFIG_H */