include/configs/ls1046afrwy.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019-2020 NXP
   4  */
   5
   6 #ifndef __LS1046AFRWY_H__
   7 #define __LS1046AFRWY_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #define CONFIG_SYS_CLK_FREQ             100000000
  12
  13 #define CONFIG_LAYERSCAPE_NS_ACCESS
  14
  15 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
  16 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
  17
  18 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  19
  20 /* IFC */
  21 #define CONFIG_FSL_IFC
  22 /*
  23  * NAND Flash Definitions
  24  */
  25 #define CONFIG_NAND_FSL_IFC
  26
  27 #define CONFIG_SYS_NAND_BASE            0x7e800000
  28 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  29
  30 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  31 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  32                                 | CSPR_PORT_SIZE_8      \
  33                                 | CSPR_MSEL_NAND        \
  34                                 | CSPR_V)
  35 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  36 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  37                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  38                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  39                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  40                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  41                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
  42                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  43
  44 #define CONFIG_SYS_NAND_ONFI_DETECTION
  45
  46 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  47                                         FTIM0_NAND_TWP(0x18)   | \
  48                                         FTIM0_NAND_TWCHT(0x7) | \
  49                                         FTIM0_NAND_TWH(0xa))
  50 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  51                                         FTIM1_NAND_TWBE(0x39)  | \
  52                                         FTIM1_NAND_TRR(0xe)   | \
  53                                         FTIM1_NAND_TRP(0x18))
  54 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  55                                         FTIM2_NAND_TREH(0xa) | \
  56                                         FTIM2_NAND_TWHRE(0x1e))
  57 #define CONFIG_SYS_NAND_FTIM3           0x0
  58
  59 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  60 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  61 #define CONFIG_MTD_NAND_VERIFY_WRITE
  62
  63 /* IFC Timing Params */
  64 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
  65 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
  66 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
  67 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
  68 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
  69 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
  70 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
  71 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
  72
  73 /* EEPROM */
  74 #define CONFIG_SYS_I2C_EEPROM_NXID
  75 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  76 #define I2C_RETIMER_ADDR                        0x18
  77
  78 /* I2C bus multiplexer */
  79 #define I2C_MUX_PCA_ADDR_PRI                    0x77 /* Primary Mux*/
  80 #define I2C_MUX_CH_DEFAULT                      0x1 /* Channel 0*/
  81 #define I2C_MUX_CH_RTC                          0x1 /* Channel 0*/
  82
  83 /* RTC */
  84 #define RTC
  85 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 0 I2C bus 0*/
  86 #define CONFIG_SYS_RTC_BUS_NUM                  0
  87
  88 /*
  89  * Environment
  90  */
  91 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
  92
  93 #ifndef CONFIG_SPL_BUILD
  94 #undef BOOT_TARGET_DEVICES
  95 #define BOOT_TARGET_DEVICES(func) \
  96         func(MMC, mmc, 0) \
  97         func(USB, usb, 0) \
  98         func(DHCP, dhcp, na)
  99 #endif
 100
 101 /* FMan */
 102 #ifdef CONFIG_SYS_DPAA_FMAN
 103
 104 #define QSGMII_PORT1_PHY_ADDR           0x1c
 105 #define QSGMII_PORT2_PHY_ADDR           0x1d
 106 #define QSGMII_PORT3_PHY_ADDR           0x1e
 107 #define QSGMII_PORT4_PHY_ADDR           0x1f
 108
 109 #define FDT_SEQ_MACADDR_FROM_ENV
 110
 111 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 112
 113 #endif
 114
 115 #undef CONFIG_BOOTCOMMAND
 116 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 117                            "env exists secureboot && esbc_halt;;"
 118 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 119                            "env exists secureboot && esbc_halt;"
 120
 121 #include <asm/fsl_secure_boot.h>
 122
 123 #endif /* __LS1046AFRWY_H__ */