include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
  20 #define CFG_SYS_MMC_U_BOOT_DST  (0x11000000)
  21 #define CFG_SYS_MMC_U_BOOT_START        (0x11000000)
  22 #define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
  23 #endif
  24
  25 #ifdef CONFIG_SPIFLASH
  26 #ifdef CONFIG_NXP_ESBC
  27 #define CONFIG_RAMBOOT_SPIFLASH
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  29 #else
  30 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE   (512 << 10)
  31 #define CFG_SYS_SPI_FLASH_U_BOOT_DST            (0x11000000)
  32 #define CFG_SYS_SPI_FLASH_U_BOOT_START  (0x11000000)
  33 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS   (96 << 10)
  34 #endif
  35 #endif
  36
  37 #ifdef CONFIG_MTD_RAW_NAND
  38 #ifdef CONFIG_NXP_ESBC
  39 #define CFG_SYS_NAND_U_BOOT_SIZE        ((768 << 10) - 0x2000)
  40 #define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  41 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  42 #else
  43 #ifdef CONFIG_TPL_BUILD
  44 #define CFG_SYS_NAND_U_BOOT_SIZE        (576 << 10)
  45 #define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
  46 #define CFG_SYS_NAND_U_BOOT_START       (0x11000000)
  47 #elif defined(CONFIG_SPL_BUILD)
  48 #define CFG_SYS_NAND_U_BOOT_SIZE        (128 << 10)
  49 #define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
  50 #define CFG_SYS_NAND_U_BOOT_START       0xD0000000
  51 #endif
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  57 #endif
  58
  59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  61 #endif
  62
  63 /* High Level Configuration Options */
  64
  65 #if defined(CONFIG_PCI)
  66 /*
  67  * PCI Windows
  68  * Memory space is mapped 1-1, but I/O space must start from 0.
  69  */
  70 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  71 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
  72 #ifdef CONFIG_PHYS_64BIT
  73 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
  74 #else
  75 #define CFG_SYS_PCIE1_MEM_PHYS  0x80000000
  76 #endif
  77 #define CFG_SYS_PCIE1_IO_VIRT   0xffc00000
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CFG_SYS_PCIE1_IO_PHYS   0xfffc00000ull
  80 #else
  81 #define CFG_SYS_PCIE1_IO_PHYS   0xffc00000
  82 #endif
  83
  84 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  85 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
  88 #else
  89 #define CFG_SYS_PCIE2_MEM_PHYS  0xa0000000
  90 #endif
  91 #define CFG_SYS_PCIE2_IO_VIRT   0xffc10000
  92 #ifdef CONFIG_PHYS_64BIT
  93 #define CFG_SYS_PCIE2_IO_PHYS   0xfffc10000ull
  94 #else
  95 #define CFG_SYS_PCIE2_IO_PHYS   0xffc10000
  96 #endif
  97 #endif
  98
  99 /*
 100  * These can be toggled for performance analysis, otherwise use default.
 101  */
 102 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 103
 104 /* DDR Setup */
 105 #define SPD_EEPROM_ADDRESS              0x52
 106
 107 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 108
 109 #ifndef __ASSEMBLY__
 110 extern unsigned long get_sdram_size(void);
 111 #endif
 112 #define CFG_SYS_SDRAM_SIZE              get_sdram_size() /* DDR size */
 113 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
 114 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
 115
 116 #define CFG_SYS_CCSRBAR                 0xffe00000
 117 #define CFG_SYS_CCSRBAR_PHYS_LOW                CFG_SYS_CCSRBAR
 118
 119 /*
 120  * Memory map
 121  *
 122  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 123  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 124  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 125  *
 126  * Localbus non-cacheable
 127  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 128  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 129  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 130  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 131  */
 132
 133 /*
 134  * IFC Definitions
 135  */
 136 /* NOR Flash on IFC */
 137
 138 #define CFG_SYS_FLASH_BASE              0xee000000
 139
 140 #ifdef CONFIG_PHYS_64BIT
 141 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
 142 #else
 143 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
 144 #endif
 145
 146 #define CFG_SYS_NOR_CSPR        (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 147                                 CSPR_PORT_SIZE_16 | \
 148                                 CSPR_MSEL_NOR | \
 149                                 CSPR_V)
 150 #define CFG_SYS_NOR_AMASK       IFC_AMASK(32*1024*1024)
 151 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(7)
 152 /* NOR Flash Timing Params */
 153 #define CFG_SYS_NOR_FTIM0       FTIM0_NOR_TACSE(0x4) | \
 154                                 FTIM0_NOR_TEADC(0x5) | \
 155                                 FTIM0_NOR_TEAHC(0x5)
 156 #define CFG_SYS_NOR_FTIM1       FTIM1_NOR_TACO(0x1e) | \
 157                                 FTIM1_NOR_TRAD_NOR(0x0f)
 158 #define CFG_SYS_NOR_FTIM2       FTIM2_NOR_TCS(0x4) | \
 159                                 FTIM2_NOR_TCH(0x4) | \
 160                                 FTIM2_NOR_TWP(0x1c)
 161 #define CFG_SYS_NOR_FTIM3       0x0
 162
 163 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS}
 164 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 165
 166 /* CFI for NOR Flash */
 167
 168 /* NAND Flash on IFC */
 169 #define CFG_SYS_NAND_BASE               0xff800000
 170 #ifdef CONFIG_PHYS_64BIT
 171 #define CFG_SYS_NAND_BASE_PHYS  0xfff800000ull
 172 #else
 173 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
 174 #endif
 175
 176 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 177                                 | CSPR_PORT_SIZE_8      \
 178                                 | CSPR_MSEL_NAND        \
 179                                 | CSPR_V)
 180 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 181
 182 #if defined(CONFIG_TARGET_P1010RDB_PA)
 183 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 184                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 185                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 186                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 187                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 188                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 189                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 190
 191 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 192 #define CFG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 193                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 194                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 195                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 196                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 197                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 198                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 199 #endif
 200
 201 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 202
 203 #if defined(CONFIG_TARGET_P1010RDB_PA)
 204 /* NAND Flash Timing Params */
 205 #define CFG_SYS_NAND_FTIM0              FTIM0_NAND_TCCST(0x01) | \
 206                                         FTIM0_NAND_TWP(0x0C)   | \
 207                                         FTIM0_NAND_TWCHT(0x04) | \
 208                                         FTIM0_NAND_TWH(0x05)
 209 #define CFG_SYS_NAND_FTIM1              FTIM1_NAND_TADLE(0x1d) | \
 210                                         FTIM1_NAND_TWBE(0x1d)  | \
 211                                         FTIM1_NAND_TRR(0x07)   | \
 212                                         FTIM1_NAND_TRP(0x0c)
 213 #define CFG_SYS_NAND_FTIM2              FTIM2_NAND_TRAD(0x0c) | \
 214                                         FTIM2_NAND_TREH(0x05) | \
 215                                         FTIM2_NAND_TWHRE(0x0f)
 216 #define CFG_SYS_NAND_FTIM3              FTIM3_NAND_TWW(0x04)
 217
 218 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 219 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 220 /* ONFI NAND Flash mode0 Timing Params */
 221 #define CFG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 222                                         FTIM0_NAND_TWP(0x18)   | \
 223                                         FTIM0_NAND_TWCHT(0x07) | \
 224                                         FTIM0_NAND_TWH(0x0a))
 225 #define CFG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 226                                         FTIM1_NAND_TWBE(0x39)  | \
 227                                         FTIM1_NAND_TRR(0x0e)   | \
 228                                         FTIM1_NAND_TRP(0x18))
 229 #define CFG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 230                                         FTIM2_NAND_TREH(0x0a)  | \
 231                                         FTIM2_NAND_TWHRE(0x1e))
 232 #define CFG_SYS_NAND_FTIM3      0x0
 233 #endif
 234
 235 /* Set up IFC registers for boot location NOR/NAND */
 236 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 237 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 238 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 239 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 240 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 241 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 242 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 243 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 244 #define CFG_SYS_CSPR1           CFG_SYS_NOR_CSPR
 245 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 246 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 247 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 248 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 249 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 250 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 251 #else
 252 #define CFG_SYS_CSPR0           CFG_SYS_NOR_CSPR
 253 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 254 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 255 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 256 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 257 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 258 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 259 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 260 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 261 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 262 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 263 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 264 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 265 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 266 #endif
 267
 268 /* CPLD on IFC */
 269 #define CFG_SYS_CPLD_BASE               0xffb00000
 270
 271 #ifdef CONFIG_PHYS_64BIT
 272 #define CFG_SYS_CPLD_BASE_PHYS  0xfffb00000ull
 273 #else
 274 #define CFG_SYS_CPLD_BASE_PHYS  CFG_SYS_CPLD_BASE
 275 #endif
 276
 277 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 278                                 | CSPR_PORT_SIZE_8 \
 279                                 | CSPR_MSEL_GPCM \
 280                                 | CSPR_V)
 281 #define CFG_SYS_AMASK3          IFC_AMASK(64*1024)
 282 #define CFG_SYS_CSOR3           0x0
 283 /* CPLD Timing parameters for IFC CS3 */
 284 #define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 285                                         FTIM0_GPCM_TEADC(0x0e) | \
 286                                         FTIM0_GPCM_TEAHC(0x0e))
 287 #define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 288                                         FTIM1_GPCM_TRAD(0x1f))
 289 #define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 290                                         FTIM2_GPCM_TCH(0x8) | \
 291                                         FTIM2_GPCM_TWP(0x1f))
 292 #define CFG_SYS_CS3_FTIM3               0x0
 293
 294 #define CFG_SYS_INIT_RAM_ADDR   0xffd00000 /* stack in RAM */
 295 #define CFG_SYS_INIT_RAM_SIZE   0x00004000 /* End of used area in RAM */
 296
 297 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 298
 299 /*
 300  * Config the L2 Cache as L2 SRAM
 301  */
 302 #if defined(CONFIG_SPL_BUILD)
 303 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 304 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 305 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 306 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 307 #elif defined(CONFIG_MTD_RAW_NAND)
 308 #ifdef CONFIG_TPL_BUILD
 309 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 310 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 311 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 312 #else
 313 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 314 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 315 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 316 #endif
 317 #endif
 318 #endif
 319
 320 /* Serial Port */
 321 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 322 #define CFG_SYS_NS16550_CLK             get_bus_freq(0)
 323
 324 #define CFG_SYS_BAUDRATE_TABLE  \
 325         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 326
 327 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR+0x4500)
 328 #define CFG_SYS_NS16550_COM2    (CFG_SYS_CCSRBAR+0x4600)
 329
 330 /* I2C */
 331 #define I2C_PCA9557_ADDR1               0x18
 332 #define I2C_PCA9557_ADDR2               0x19
 333 #define I2C_PCA9557_BUS_NUM             0
 334
 335 /* I2C EEPROM */
 336 #if defined(CONFIG_TARGET_P1010RDB_PB)
 337 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 338 #endif
 339 /* enable read and write access to EEPROM */
 340
 341 /* RTC */
 342 #define CFG_SYS_I2C_RTC_ADDR    0x68
 343
 344 /*
 345  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 346  * used for SLIC
 347  */
 348 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 349 /* eSPI - Enhanced SPI */
 350 #endif
 351
 352 #ifdef CONFIG_MMC
 353 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 354 #endif
 355
 356 /*
 357  * Environment
 358  */
 359 #if defined(CONFIG_MTD_RAW_NAND)
 360 #ifdef CONFIG_TPL_BUILD
 361 #define SPL_ENV_ADDR            (CFG_SYS_INIT_L2_ADDR + (160 << 10))
 362 #endif
 363 #endif
 364
 365 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 366                  || defined(CONFIG_FSL_SATA)
 367 #endif
 368
 369 /*
 370  * Miscellaneous configurable options
 371  */
 372
 373 /*
 374  * For booting Linux, the board info and command line data
 375  * have to be in the first 64 MB of memory, since this is
 376  * the maximum mapped by the Linux kernel during initialization.
 377  */
 378 #define CFG_SYS_BOOTMAPSZ       (64 << 20) /* Initial Memory map for Linux */
 379
 380 /*
 381  * Environment Configuration
 382  */
 383
 384 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 385 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 386
 387 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 388         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 389         "netdev=eth0\0"                                         \
 390         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 391         "loadaddr=1000000\0"                    \
 392         "consoledev=ttyS0\0"                            \
 393         "ramdiskaddr=2000000\0"                 \
 394         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 395         "fdtaddr=1e00000\0"                             \
 396         "fdtfile=p1010rdb.dtb\0"                \
 397         "bdev=sda1\0"   \
 398         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 399         "othbootargs=ramdisk_size=600000\0" \
 400         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 401         "console=$consoledev,$baudrate $othbootargs; "  \
 402         "usb start;"                    \
 403         "fatload usb 0:2 $loadaddr $bootfile;"          \
 404         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 405         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 406         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 407         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 408         "console=$consoledev,$baudrate $othbootargs; "  \
 409         "usb start;"                    \
 410         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 411         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 412         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 413         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 414         BOOTMODE
 415
 416 #if defined(CONFIG_TARGET_P1010RDB_PA)
 417 #define BOOTMODE \
 418         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 419         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 420         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 421         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 422         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 423         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 424
 425 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 426 #define BOOTMODE \
 427         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 428         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 429         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 430         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 431         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 432         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 433         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 434         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 435         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 436         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 437 #endif
 438
 439 #include <asm/fsl_secure_boot.h>
 440
 441 #endif  /* __CONFIG_H */