include/configs/MPC8349ITX.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 /*
   7  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   8
   9  Memory map:
  10
  11  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  12  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  13  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  14  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  15  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  16  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  17  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  18  0xF001_0000-0xF001_FFFF Local bus expansion slot
  19  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  20  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  21  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  22
  23  I2C address list:
  24                                                 Align.  Board
  25  Bus    Addr    Part No.        Description     Length  Location
  26  ----------------------------------------------------------------
  27  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  28
  29  I2C1   0x20    PCF8574         I2C Expander    0       U8
  30  I2C1   0x21    PCF8574         I2C Expander    0       U10
  31  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  32  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  33  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  34  I2C1   0x68    DS1339          RTC             1       U68
  35
  36  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  37 */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 /*
  43  * High Level Configuration Options
  44  */
  45 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  46
  47 #define CONFIG_MISC_INIT_F
  48
  49 /*
  50  * On-board devices
  51  */
  52
  53 #ifdef CONFIG_TARGET_MPC8349ITX
  54 /* The CF card interface on the back of the board */
  55 #define CONFIG_COMPACT_FLASH
  56 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  57 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  58 #endif
  59
  60 #define CONFIG_RTC_DS1337
  61 #define CONFIG_SYS_I2C
  62
  63 /*
  64  * Device configurations
  65  */
  66
  67 /* I2C */
  68 #ifdef CONFIG_SYS_I2C
  69 #define CONFIG_SYS_I2C_FSL
  70 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  71 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  72 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  73 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  74 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  75 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  76
  77 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  78 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  79
  80 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  81 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  82 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  83 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
  84 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
  85 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
  86 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
  87
  88 /* Don't probe these addresses: */
  89 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  90                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  91                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  92                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
  93 /* Bit definitions for the 8574[A] I2C expander */
  94                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
  95 #define I2C_8574_REVISION       0x03
  96 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
  97 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
  98 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
  99 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 100
 101 #endif
 102
 103 /* Compact Flash */
 104 #ifdef CONFIG_COMPACT_FLASH
 105
 106 #define CONFIG_SYS_IDE_MAXBUS           1
 107 #define CONFIG_SYS_IDE_MAXDEVICE        1
 108
 109 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 110 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 111 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 112 #define CONFIG_SYS_ATA_REG_OFFSET       0
 113 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 114 #define CONFIG_SYS_ATA_STRIDE           2
 115
 116 /* If a CF card is not inserted, time out quickly */
 117 #define ATA_RESET_TIME  1
 118
 119 #endif
 120
 121 /*
 122  * SATA
 123  */
 124 #ifdef CONFIG_SATA_SIL3114
 125
 126 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 127 #define CONFIG_LBA48
 128
 129 #endif
 130
 131 #ifdef CONFIG_SYS_USB_HOST
 132 /*
 133  * Support USB
 134  */
 135 #define CONFIG_USB_EHCI_FSL
 136
 137 /* Current USB implementation supports the only USB controller,
 138  * so we have to choose between the MPH or the DR ones */
 139 #if 1
 140 #define CONFIG_HAS_FSL_MPH_USB
 141 #else
 142 #define CONFIG_HAS_FSL_DR_USB
 143 #endif
 144
 145 #endif
 146
 147 /*
 148  * DDR Setup
 149  */
 150 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 151 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 152 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 153 #define CONFIG_SYS_83XX_DDR_USES_CS0
 154 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 155 #define CONFIG_SYS_MEMTEST_END          0x2000
 156
 157 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 158                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 159
 160 #define CONFIG_VERY_BIG_RAM
 161 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 162
 163 #ifdef CONFIG_SYS_I2C
 164 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 165 #endif
 166
 167 /* No SPD? Then manually set up DDR parameters */
 168 #ifndef CONFIG_SPD_EEPROM
 169     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 170     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 171                                         | CSCONFIG_ROW_BIT_13 \
 172                                         | CSCONFIG_COL_BIT_10)
 173
 174     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 175     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 176 #endif
 177
 178 /*
 179  *Flash on the Local Bus
 180  */
 181
 182 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 183 #define CONFIG_SYS_FLASH_EMPTY_INFO
 184 /* 127 64KB sectors + 8 8KB sectors per device */
 185 #define CONFIG_SYS_MAX_FLASH_SECT       135
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 188 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 189
 190 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 191 boards, we say we have two, but don't display a message if we find only one. */
 192 #define CONFIG_SYS_FLASH_QUIET_TEST
 193 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 194 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 195                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 196 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 197
 198 /* Vitesse 7385 */
 199
 200 #ifdef CONFIG_VSC7385_ENET
 201
 202 #define CONFIG_TSEC2
 203
 204 /* The flash address and size of the VSC7385 firmware image */
 205 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 206 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 207
 208 #endif
 209
 210 /*
 211  * BRx, ORx, LBLAWBARx, and LBLAWARx
 212  */
 213
 214 /* Flash */
 215
 216 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 217                                 | BR_PS_16 \
 218                                 | BR_MS_GPCM \
 219                                 | BR_V)
 220 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 221                                 | OR_UPM_XAM \
 222                                 | OR_GPCM_CSNT \
 223                                 | OR_GPCM_ACS_DIV2 \
 224                                 | OR_GPCM_XACS \
 225                                 | OR_GPCM_SCY_15 \
 226                                 | OR_GPCM_TRLX_SET \
 227                                 | OR_GPCM_EHTR_SET \
 228                                 | OR_GPCM_EAD)
 229 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 230 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 231
 232 /* Vitesse 7385 */
 233
 234 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 235
 236 #ifdef CONFIG_VSC7385_ENET
 237
 238 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 239                                 | BR_PS_8 \
 240                                 | BR_MS_GPCM \
 241                                 | BR_V)
 242 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 243                                 | OR_GPCM_CSNT \
 244                                 | OR_GPCM_XACS \
 245                                 | OR_GPCM_SCY_15 \
 246                                 | OR_GPCM_SETA \
 247                                 | OR_GPCM_TRLX_SET \
 248                                 | OR_GPCM_EHTR_SET \
 249                                 | OR_GPCM_EAD)
 250
 251 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 252 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 253
 254 #endif
 255
 256 /* LED */
 257
 258 #define CONFIG_SYS_LED_BASE     0xF9000000
 259 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 260                                 | BR_PS_8 \
 261                                 | BR_MS_GPCM \
 262                                 | BR_V)
 263 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 264                                 | OR_GPCM_CSNT \
 265                                 | OR_GPCM_ACS_DIV2 \
 266                                 | OR_GPCM_XACS \
 267                                 | OR_GPCM_SCY_9 \
 268                                 | OR_GPCM_TRLX_SET \
 269                                 | OR_GPCM_EHTR_SET \
 270                                 | OR_GPCM_EAD)
 271
 272 /* Compact Flash */
 273
 274 #ifdef CONFIG_COMPACT_FLASH
 275
 276 #define CONFIG_SYS_CF_BASE      0xF0000000
 277
 278 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 279                                 | BR_PS_16 \
 280                                 | BR_MS_UPMA \
 281                                 | BR_V)
 282 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 283
 284 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 285 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 286
 287 #endif
 288
 289 /*
 290  * U-Boot memory configuration
 291  */
 292 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 293
 294 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 295 #define CONFIG_SYS_RAMBOOT
 296 #else
 297 #undef  CONFIG_SYS_RAMBOOT
 298 #endif
 299
 300 #define CONFIG_SYS_INIT_RAM_LOCK
 301 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 302 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 303
 304 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 305                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 306 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 307
 308 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 309 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 310 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 311
 312 /*
 313  * Local Bus LCRR and LBCR regs
 314  *    LCRR:  DLL bypass, Clock divider is 4
 315  * External Local Bus rate is
 316  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 317  */
 318 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 319 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 320 #define CONFIG_SYS_LBC_LBCR     0x00000000
 321
 322                                 /* LB sdram refresh timer, about 6us */
 323 #define CONFIG_SYS_LBC_LSRT     0x32000000
 324                                 /* LB refresh timer prescal, 266MHz/32*/
 325 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 326
 327 /*
 328  * Serial Port
 329  */
 330 #define CONFIG_SYS_NS16550_SERIAL
 331 #define CONFIG_SYS_NS16550_REG_SIZE     1
 332 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 333
 334 #define CONFIG_SYS_BAUDRATE_TABLE  \
 335                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 336
 337 #define CONSOLE                 ttyS0
 338
 339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 341
 342 /*
 343  * PCI
 344  */
 345 #ifdef CONFIG_PCI
 346 #define CONFIG_PCI_INDIRECT_BRIDGE
 347
 348 #define CONFIG_MPC83XX_PCI2
 349
 350 /*
 351  * General PCI
 352  * Addresses are mapped 1-1.
 353  */
 354 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 355 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 356 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 357 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 358                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 359 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 360 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 361 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 362 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 363 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 364
 365 #ifdef CONFIG_MPC83XX_PCI2
 366 #define CONFIG_SYS_PCI2_MEM_BASE        \
 367                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 368 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 369 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 370 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 371                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 372 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 373 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 374 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 375 #define CONFIG_SYS_PCI2_IO_PHYS         \
 376                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 377 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 378 #endif
 379
 380 #ifndef CONFIG_PCI_PNP
 381     #define PCI_ENET0_IOADDR    0x00000000
 382     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 383     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 384 #endif
 385
 386 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 387
 388 #endif
 389
 390 /* TSEC */
 391
 392 #ifdef CONFIG_TSEC_ENET
 393 #define CONFIG_TSEC1
 394
 395 #ifdef CONFIG_TSEC1
 396 #define CONFIG_HAS_ETH0
 397 #define CONFIG_TSEC1_NAME  "TSEC0"
 398 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 399 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 400 #define TSEC1_PHYIDX            0
 401 #define TSEC1_FLAGS             TSEC_GIGABIT
 402 #endif
 403
 404 #ifdef CONFIG_TSEC2
 405 #define CONFIG_HAS_ETH1
 406 #define CONFIG_TSEC2_NAME  "TSEC1"
 407 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 408
 409 #define TSEC2_PHY_ADDR          4
 410 #define TSEC2_PHYIDX            0
 411 #define TSEC2_FLAGS             TSEC_GIGABIT
 412 #endif
 413
 414 #define CONFIG_ETHPRIME         "Freescale TSEC"
 415
 416 #endif
 417
 418 /*
 419  * Environment
 420  */
 421 #define CONFIG_ENV_OVERWRITE
 422
 423 #ifndef CONFIG_SYS_RAMBOOT
 424   #define CONFIG_ENV_ADDR       \
 425                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 426   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 427   #define CONFIG_ENV_SIZE       0x2000
 428 #else
 429   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 430   #define CONFIG_ENV_SIZE       0x2000
 431 #endif
 432
 433 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 434 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 435
 436 /*
 437  * BOOTP options
 438  */
 439 #define CONFIG_BOOTP_BOOTFILESIZE
 440
 441 /* Watchdog */
 442 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 443
 444 /*
 445  * Miscellaneous configurable options
 446  */
 447
 448 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 449 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 450
 451 /*
 452  * For booting Linux, the board info and command line data
 453  * have to be in the first 256 MB of memory, since this is
 454  * the maximum mapped by the Linux kernel during initialization.
 455  */
 456                                 /* Initial Memory map for Linux*/
 457 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 458 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 459
 460 /*
 461  * System performance
 462  */
 463 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 464 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 465 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 466 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 467 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 468 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 469 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 470 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 471
 472 /*
 473  * System IO Config
 474  */
 475 /* Needed for gigabit to work on TSEC 1 */
 476 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 477                                 /* USB DR as device + USB MPH as host */
 478 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 479
 480 #define CONFIG_SYS_HID0_INIT    0x00000000
 481 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 482
 483 #define CONFIG_SYS_HID2 HID2_HBE
 484 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 485
 486 /* DDR  */
 487 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 488                                 | BATL_PP_RW \
 489                                 | BATL_MEMCOHERENCE)
 490 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 491                                 | BATU_BL_256M \
 492                                 | BATU_VS \
 493                                 | BATU_VP)
 494
 495 /* PCI  */
 496 #ifdef CONFIG_PCI
 497 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 498                                 | BATL_PP_RW \
 499                                 | BATL_MEMCOHERENCE)
 500 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 501                                 | BATU_BL_256M \
 502                                 | BATU_VS \
 503                                 | BATU_VP)
 504 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 505                                 | BATL_PP_RW \
 506                                 | BATL_CACHEINHIBIT \
 507                                 | BATL_GUARDEDSTORAGE)
 508 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 509                                 | BATU_BL_256M \
 510                                 | BATU_VS \
 511                                 | BATU_VP)
 512 #else
 513 #define CONFIG_SYS_IBAT1L       0
 514 #define CONFIG_SYS_IBAT1U       0
 515 #define CONFIG_SYS_IBAT2L       0
 516 #define CONFIG_SYS_IBAT2U       0
 517 #endif
 518
 519 #ifdef CONFIG_MPC83XX_PCI2
 520 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 521                                 | BATL_PP_RW \
 522                                 | BATL_MEMCOHERENCE)
 523 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 524                                 | BATU_BL_256M \
 525                                 | BATU_VS \
 526                                 | BATU_VP)
 527 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 528                                 | BATL_PP_RW \
 529                                 | BATL_CACHEINHIBIT \
 530                                 | BATL_GUARDEDSTORAGE)
 531 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 532                                 | BATU_BL_256M \
 533                                 | BATU_VS \
 534                                 | BATU_VP)
 535 #else
 536 #define CONFIG_SYS_IBAT3L       0
 537 #define CONFIG_SYS_IBAT3U       0
 538 #define CONFIG_SYS_IBAT4L       0
 539 #define CONFIG_SYS_IBAT4U       0
 540 #endif
 541
 542 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 543 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 544                                 | BATL_PP_RW \
 545                                 | BATL_CACHEINHIBIT \
 546                                 | BATL_GUARDEDSTORAGE)
 547 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 548                                 | BATU_BL_256M \
 549                                 | BATU_VS \
 550                                 | BATU_VP)
 551
 552 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 553 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 554                                 | BATL_PP_RW \
 555                                 | BATL_MEMCOHERENCE \
 556                                 | BATL_GUARDEDSTORAGE)
 557 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 558                                 | BATU_BL_256M \
 559                                 | BATU_VS \
 560                                 | BATU_VP)
 561
 562 #define CONFIG_SYS_IBAT7L       0
 563 #define CONFIG_SYS_IBAT7U       0
 564
 565 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 566 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 567 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 568 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 569 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 570 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 571 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 572 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 573 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 574 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 575 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 576 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 577 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 578 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 579 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 580 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 581
 582 #if defined(CONFIG_CMD_KGDB)
 583 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 584 #endif
 585
 586 /*
 587  * Environment Configuration
 588  */
 589 #define CONFIG_ENV_OVERWRITE
 590
 591 #define CONFIG_NETDEV           "eth0"
 592
 593 /* Default path and filenames */
 594 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 595 #define CONFIG_BOOTFILE         "uImage"
 596                                 /* U-Boot image on TFTP server */
 597 #define CONFIG_UBOOTPATH        "u-boot.bin"
 598
 599 #ifdef CONFIG_TARGET_MPC8349ITX
 600 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 601 #else
 602 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 603 #endif
 604
 605
 606 #define CONFIG_EXTRA_ENV_SETTINGS \
 607         "console=" __stringify(CONSOLE) "\0"                    \
 608         "netdev=" CONFIG_NETDEV "\0"                                    \
 609         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 610         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 611                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 612                         " +$filesize; " \
 613                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 614                         " +$filesize; " \
 615                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 616                         " $filesize; "  \
 617                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 618                         " +$filesize; " \
 619                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 620                         " $filesize\0"  \
 621         "fdtaddr=780000\0"                                              \
 622         "fdtfile=" CONFIG_FDTFILE "\0"
 623
 624 #define CONFIG_NFSBOOTCOMMAND                                           \
 625         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 626         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 627         " console=$console,$baudrate $othbootargs; "                    \
 628         "tftp $loadaddr $bootfile;"                                     \
 629         "tftp $fdtaddr $fdtfile;"                                       \
 630         "bootm $loadaddr - $fdtaddr"
 631
 632 #define CONFIG_RAMBOOTCOMMAND                                           \
 633         "setenv bootargs root=/dev/ram rw"                              \
 634         " console=$console,$baudrate $othbootargs; "                    \
 635         "tftp $ramdiskaddr $ramdiskfile;"                               \
 636         "tftp $loadaddr $bootfile;"                                     \
 637         "tftp $fdtaddr $fdtfile;"                                       \
 638         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 639
 640 #endif