1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
7 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
18 0xF001_0000-0xF001_FFFF Local bus expansion slot
19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
25 Bus Addr Part No. Description Length Location
26 ----------------------------------------------------------------
27 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
29 I2C1 0x20 PCF8574 I2C Expander 0 U8
30 I2C1 0x21 PCF8574 I2C Expander 0 U10
31 I2C1 0x38 PCF8574A I2C Expander 0 U8
32 I2C1 0x39 PCF8574A I2C Expander 0 U10
33 I2C1 0x51 (DDR) DDR EEPROM 1 U1
34 I2C1 0x68 DS1339 RTC 1 U68
36 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
42 #define CONFIG_MISC_INIT_F
48 #ifdef CONFIG_TARGET_MPC8349ITX
49 /* The CF card interface on the back of the board */
50 #define CONFIG_COMPACT_FLASH
51 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
52 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
55 #define CONFIG_RTC_DS1337
56 #define CONFIG_SYS_I2C
59 * Device configurations
64 #define CONFIG_SYS_I2C_FSL
65 #define CONFIG_SYS_FSL_I2C_SPEED 400000
66 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
67 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
68 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
69 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
70 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
72 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
73 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
75 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
76 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
77 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
78 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
79 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
80 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
81 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
83 /* Don't probe these addresses: */
84 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
85 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
86 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
87 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
88 /* Bit definitions for the 8574[A] I2C expander */
89 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
90 #define I2C_8574_REVISION 0x03
91 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
92 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
93 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
94 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
99 #ifdef CONFIG_COMPACT_FLASH
101 #define CONFIG_SYS_IDE_MAXBUS 1
102 #define CONFIG_SYS_IDE_MAXDEVICE 1
104 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
105 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
106 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
107 #define CONFIG_SYS_ATA_REG_OFFSET 0
108 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
109 #define CONFIG_SYS_ATA_STRIDE 2
111 /* If a CF card is not inserted, time out quickly */
112 #define ATA_RESET_TIME 1
119 #ifdef CONFIG_SATA_SIL3114
121 #define CONFIG_SYS_SATA_MAX_DEVICE 4
126 #ifdef CONFIG_SYS_USB_HOST
130 #define CONFIG_USB_EHCI_FSL
132 /* Current USB implementation supports the only USB controller,
133 * so we have to choose between the MPH or the DR ones */
135 #define CONFIG_HAS_FSL_MPH_USB
137 #define CONFIG_HAS_FSL_DR_USB
145 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
146 #define CONFIG_SYS_83XX_DDR_USES_CS0
147 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
148 #define CONFIG_SYS_MEMTEST_END 0x2000
150 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
151 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
153 #define CONFIG_VERY_BIG_RAM
154 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
156 #ifdef CONFIG_SYS_I2C
157 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
160 /* No SPD? Then manually set up DDR parameters */
161 #ifndef CONFIG_SPD_EEPROM
162 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
163 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
164 | CSCONFIG_ROW_BIT_13 \
165 | CSCONFIG_COL_BIT_10)
167 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
168 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
172 *Flash on the Local Bus
175 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
176 #define CONFIG_SYS_FLASH_EMPTY_INFO
177 /* 127 64KB sectors + 8 8KB sectors per device */
178 #define CONFIG_SYS_MAX_FLASH_SECT 135
179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
181 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
183 /* The ITX has two flash chips, but the ITX-GP has only one. To support both
184 boards, we say we have two, but don't display a message if we find only one. */
185 #define CONFIG_SYS_FLASH_QUIET_TEST
186 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
187 #define CONFIG_SYS_FLASH_BANKS_LIST \
188 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
189 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
193 #ifdef CONFIG_VSC7385_ENET
197 /* The flash address and size of the VSC7385 firmware image */
198 #define CONFIG_VSC7385_IMAGE 0xFEFFE000
199 #define CONFIG_VSC7385_IMAGE_SIZE 8192
204 * BRx, ORx, LBLAWBARx, and LBLAWARx
210 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
212 #ifdef CONFIG_VSC7385_ENET
218 #define CONFIG_SYS_LED_BASE 0xF9000000
223 #ifdef CONFIG_COMPACT_FLASH
225 #define CONFIG_SYS_CF_BASE 0xF0000000
231 * U-Boot memory configuration
233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
235 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
236 #define CONFIG_SYS_RAMBOOT
238 #undef CONFIG_SYS_RAMBOOT
241 #define CONFIG_SYS_INIT_RAM_LOCK
242 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
243 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
245 #define CONFIG_SYS_GBL_DATA_OFFSET \
246 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
247 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
249 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
250 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
251 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
254 * Local Bus LCRR and LBCR regs
255 * LCRR: DLL bypass, Clock divider is 4
256 * External Local Bus rate is
257 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
259 #define CONFIG_SYS_LBC_LBCR 0x00000000
261 /* LB sdram refresh timer, about 6us */
262 #define CONFIG_SYS_LBC_LSRT 0x32000000
263 /* LB refresh timer prescal, 266MHz/32*/
264 #define CONFIG_SYS_LBC_MRTPR 0x20000000
269 #define CONFIG_SYS_NS16550_SERIAL
270 #define CONFIG_SYS_NS16550_REG_SIZE 1
271 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
273 #define CONFIG_SYS_BAUDRATE_TABLE \
274 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
276 #define CONSOLE ttyS0
278 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
279 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
285 #define CONFIG_PCI_INDIRECT_BRIDGE
287 #define CONFIG_MPC83XX_PCI2
291 * Addresses are mapped 1-1.
293 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
294 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
295 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
296 #define CONFIG_SYS_PCI1_MMIO_BASE \
297 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
298 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
299 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
300 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
301 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
302 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
304 #ifdef CONFIG_MPC83XX_PCI2
305 #define CONFIG_SYS_PCI2_MEM_BASE \
306 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
307 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
308 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
309 #define CONFIG_SYS_PCI2_MMIO_BASE \
310 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
311 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
312 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
313 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
314 #define CONFIG_SYS_PCI2_IO_PHYS \
315 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
316 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
319 #ifndef CONFIG_PCI_PNP
320 #define PCI_ENET0_IOADDR 0x00000000
321 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
322 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
325 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
331 #ifdef CONFIG_TSEC_ENET
335 #define CONFIG_HAS_ETH0
336 #define CONFIG_TSEC1_NAME "TSEC0"
337 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
338 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
339 #define TSEC1_PHYIDX 0
340 #define TSEC1_FLAGS TSEC_GIGABIT
344 #define CONFIG_HAS_ETH1
345 #define CONFIG_TSEC2_NAME "TSEC1"
346 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
348 #define TSEC2_PHY_ADDR 4
349 #define TSEC2_PHYIDX 0
350 #define TSEC2_FLAGS TSEC_GIGABIT
353 #define CONFIG_ETHPRIME "Freescale TSEC"
360 #define CONFIG_ENV_OVERWRITE
362 #ifndef CONFIG_SYS_RAMBOOT
363 #define CONFIG_ENV_ADDR \
364 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
365 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
366 #define CONFIG_ENV_SIZE 0x2000
368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
369 #define CONFIG_ENV_SIZE 0x2000
372 #define CONFIG_LOADS_ECHO /* echo on for serial download */
373 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
378 #define CONFIG_BOOTP_BOOTFILESIZE
381 #undef CONFIG_WATCHDOG /* watchdog disabled */
384 * Miscellaneous configurable options
387 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
388 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
391 * For booting Linux, the board info and command line data
392 * have to be in the first 256 MB of memory, since this is
393 * the maximum mapped by the Linux kernel during initialization.
395 /* Initial Memory map for Linux*/
396 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
397 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
402 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
403 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
404 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
405 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
410 /* Needed for gigabit to work on TSEC 1 */
411 #define CONFIG_SYS_SICRH SICRH_TSOBI1
412 /* USB DR as device + USB MPH as host */
413 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
415 #if defined(CONFIG_CMD_KGDB)
416 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
420 * Environment Configuration
422 #define CONFIG_ENV_OVERWRITE
424 #define CONFIG_NETDEV "eth0"
426 /* Default path and filenames */
427 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
428 #define CONFIG_BOOTFILE "uImage"
429 /* U-Boot image on TFTP server */
430 #define CONFIG_UBOOTPATH "u-boot.bin"
432 #ifdef CONFIG_TARGET_MPC8349ITX
433 #define CONFIG_FDTFILE "mpc8349emitx.dtb"
435 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
439 #define CONFIG_EXTRA_ENV_SETTINGS \
440 "console=" __stringify(CONSOLE) "\0" \
441 "netdev=" CONFIG_NETDEV "\0" \
442 "uboot=" CONFIG_UBOOTPATH "\0" \
443 "tftpflash=tftpboot $loadaddr $uboot; " \
444 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
446 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
448 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
450 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
452 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
455 "fdtfile=" CONFIG_FDTFILE "\0"
457 #define CONFIG_NFSBOOTCOMMAND \
458 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
459 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
460 " console=$console,$baudrate $othbootargs; " \
461 "tftp $loadaddr $bootfile;" \
462 "tftp $fdtaddr $fdtfile;" \
463 "bootm $loadaddr - $fdtaddr"
465 #define CONFIG_RAMBOOTCOMMAND \
466 "setenv bootargs root=/dev/ram rw" \
467 " console=$console,$baudrate $othbootargs; " \
468 "tftp $ramdiskaddr $ramdiskfile;" \
469 "tftp $loadaddr $bootfile;" \
470 "tftp $fdtaddr $fdtfile;" \
471 "bootm $loadaddr $ramdiskaddr $fdtaddr"