clk: tegra: Initialize DSI low-power clocks

The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 2a1b0b8..29b9125 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1299,6 +1299,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
        {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
        {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
        {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
+       {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
+       {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
 
        /* This MUST be the last entry. */
        {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},