Fix the issue in i965_UnlockSurface to lock it next time

It uses the variable of locked_image_id to check whether one surface is locked
or not. But as the locked_image_id is not assigned correctly, it causes that
it can't lock one surface next time although it calls the vaUnlockSurfaces.
Then the libva trace log can't dump the content of decoded/
encoded surface even after adding LIBVA_TRACE_SURFACE=XXX.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Gwenole Beauchesne <gb.devel@gmail.com>

VPP: refine code to resolve building warnings

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: add vebox context init and deinit

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: Alloc I965 batch buffer before initialization

VPP: Fix the surface flags and type setting

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: fix the usage of pp_static_parameter

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: work around hw limitation(dword alignment)

work around for horizontal offset on dst surface
left edge for load/save procedure

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Remove useless shader and refine shader list

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: CSC on Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Build VPP shaders for Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: haswell: fix video post-processing setup.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

VPP: The block mask workaround is only available for Sandy bridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP:work around hw limitation(dword alignment)

work around for horizontal offset on dst surface left edge for nv12 scaling (not avs)

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: work around hw limitation(dword alignment)

work around for horizontal offset on dst surface left edge (nv12 avs)

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Enable horizontal and vertical mask for bottom/right boundary blocks

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
- usually it is 0xff/0xffff for common blocks in grf5
- one mask is setup in object_walker when the last group of blocks are met
- another mask should setup when the last block (in a group) is met.
  it will be done in asm code, we make it ready in grf6

VPP: Adjust vertical scaling step for AVS on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: AVS workaround on IVB

Update AVS shaders and add CURBE parameters for AVS workaround

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Update the shader for DI on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Add support DN on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: New combined shaders for Ivybridge

In addtion, add the license header.

You need the latest intel-gen4asm to build these shaders

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: distinguish first plane width in pixel or in byte

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Add support for UYVY in image process

Tested on SNB and IVB.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: color conversion between planar and packed formats on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: New shaders for color conversion between packed and planar YUV on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Support NV12/I420/YV12->I420/YV12 conversion

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: add YV12 to YUY2 conversion

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Fix the width of the UV surface for AVS on IVB

The width is specified in units of pixel.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Only update u/v offset for some video processes

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Fix the parameter initialization for IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Don't render the target surface with background if alpha value is 0

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: update image width of packed format

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Add yuyv->nv12 conversion in image processing

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: add NV12 to YUY2 color conversion for video process

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Update the PA shader for ILK/SNB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: fix a mistake in PA_Load_8x8.asm

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: add YUYV to NV12 conversion shaders for gen5_6

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: add pa_load_save_pl3 for YUY2-->YV12 conversion (SNB/ILK)

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: add pl3_load_save_pa.asm etc

Signed-off-by: Zhao, Halley <halley.zhao@intel.com>

VPP: add NV12 load save PA shader for gen5_6

Signed-off-by Zhao,Halley <halley.zhao@intel.com>

VPP: pass the origin of source region to vpp kernel

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Render target surface with background color

Currently ignore alpha value. We will fix it once the
alpha blend kernel is ready

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Don't use DNDI kernel on Ivybridge temporarily

We will integrate the right kernel for DN/DI on Ivybridge as soon as possible.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Use AVS kernel to implement normal scaling on Sandybridge

Set parameter nlas to 0 to disable NLAS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 0b38176cda6047b05cf0eacd913f57ce501f4fdf)

VPP: Fix map/unmap mismatches in video process

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 918f26fc0c5c38fb8c1002dd48c857897931c5d5)

VPP: Pixel format conversion for IMC1/IMC3

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Fix the base offset of cr(V) surface

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Reuse AVS kernel for pixel format conversion on Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Build new shaders for Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: use AM_V_GEN to generate files quietly on Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Add support for I420/YV12/IMC1/IMC3 input/output surface for AVS on Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Normal scaling on Ivybridge

Need to adjust parameters later

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Clear target surface with specified color

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Fix AVS parameters for Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Refine the Makefile.am in gen5_6

Signed-off-by: Xiang,Haihao <haihao.xiang@intel.com>

VPP: avoid depending on va_backend.h for some file

Signed-off-by: Xiang, Haihai <haihao.xiang@intel.com>

VPP: Fix parameters for SCALING & AVS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Fixed surface height for DN/DI

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Update DNDI kernel and DNDI states on Sandybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Update surface state, sampler state and kernel for AVS on Sandybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: update AVS kernel

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Support video process on Ivybridge

Only AVS enabled currently on Ivybridge.

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: Update the gen7 shader Makefile.am

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: Add support for field and frame mixed content

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: Support DN only on Ironlake and Sandybridge

signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Emit base address command before other commands

This fixes potential GPU hang issue on SandyBridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: set surface base address for post processing

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Add image format conversion function

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: code refine for video process

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: Add shaders for video process on Ivybridge.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Add NV12<->PL3 load and save shaders to gen5_6/

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: move all vpp shaders to new gen5_6/ directory.

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: Modify the definition for PP module number

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

Update the check for intel-gen4asm to support Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Remove the dependence of va_vpp.h

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Make it built against the current upstream libdrm

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VEBox: setup haswell vebox pipeline for video post process

Currently, deinterlacing, denoise, color balance, color space conversion
are supported by vebox pipeline, and only deinterlace is exposed to video
post process on haswell.

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VEBox: add special batch command and macro for VEBox command streamer

VEBox is a new feature introducted in haswell, which aims
to do video process through fixed functions, it also owns
one seperated command streamer.

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: enabling scaling function for post processing

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

Fix thread issue with AVC private surafce

https://bugs.freedesktop.org/show_bug.cgi?id=55282

Signed-off-by: Gautam <manamgautam@gmail.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Unify the code for xxx_free_avc_surface

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Haswell: Disable Picture ID Remapping for AVC decoding

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Handle the MFX change between A stepping and B-stepping for haswell

The A0-stepping is still covered.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the support of encoding P frame on haswell

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the Intra VME for I-frame on Haswell

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the seperated file for media decoding on Haswell

As the MFX involves quite a lot of changes between Ivy and Haswell,
the seperated file is added for the media decoding on haswell. This
can avoid the complex backward logic for Ivy.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the separated file for media encoding on haswell

There exist a lot of changes about the media encoder between Haswell
and IvyBridge. For example: the VME programming and the corresponding
general media command. To be simple, the separated files are added for Haswell.
Otherwise it has to consider the complex backward compatibility.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

haswell: fix render kernels.

Regenerate render kernels for Haswell because JMPI instruction semantics
changed there. In particular, the offset is now expressed in bytes instead
of 64-bit units.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

haswell: set "Shader Channel Select" fields in surface state.

For normal behaviour, each Shader Channel Select should be set to the
value indicating that same channel. i.e. Shader Channel Select Red is
set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

haswell: fix 3DSTATE_PS to fill in number of samples.

The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen7_emit_invarient_states().

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

haswell: fix max PS threads shift value.

The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

intel: fix max number of threads used on Ivy Bridge.

Fix the max number of threads to be used on Ivy Bridge. In particular,
the GEN7_PS_MAX_THREADS_SHIFT offset was wrong, thus causing the GPU
to use half of what was specified.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

haswell: use at least 64 URB entries for GT2+.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Add haswell PCI IDs

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix inconsistent surface dimension during allocating surface buffer object

When one surface is created, the height/width is aligned to 16 pixels.
But when trying to allocate the buffer object for it, the width is aligned
to 128 and height is aligned to 32. If the surface is mapped and accessed
before allocating the buffer object, the APP will get the incorrect dimension.

From: Zhao Yakui <yakui.zhao@intel.com>

Fix build with VA-API 0.32.0.

Really fix build back to VA-API 0.32.0, and not only VA-API 0.32.1,
thus checking for VA/JPEG decode API. VA-API 0.32.0 was provided by
libva 1.0.15 and earlier version, which is still available in
Ubuntu 12.04-LTS.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Add sysdeps.h for system-dependent definitions.

Add new "sysdeps.h" file for system-dependent definitions and common
include files. This will be helpful for Android support so that to
stack every definition useful to Android that could not be auto-generated
since configure script is not built there.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Fix build with VA-API 0.32.0.

Add new <va/va_backend_compat.h> glue file with various utility functions
and definitions to help building the driver against a previous version of
libva (1.0.x for VA-API 0.32.x in particular).

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

render: fix rotation vertices for Ironlake.

Ironlake requires the vertex buffer to be ordered in a particular way.
More specifically, the correct order is bottom-right, bottom-left and
top-left vertices in "output" view, i.e. transformed.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Fix make dist.

The recent changes for Wayland support broke make dist. This is due
to the fact that DIST_SUBDIRS requires all subdirectories needed to
complete make dist. i.e. the generated list of subdirectories used
for make dist is *not* an union of DIST_SUBDIRS and SUBDIRS.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

fix ttmbf/ttfrm when vstransform is 0