haswell: use at least 64 URB entries for GT2+.
authorGwenole Beauchesne <gwenole.beauchesne@intel.com>
Tue, 18 Sep 2012 13:40:02 +0000 (09:40 -0400)
committerXiang, Haihao <haihao.xiang@intel.com>
Tue, 23 Oct 2012 05:56:02 +0000 (13:56 +0800)
commit1663bbe66a922f26922a4e3bc49eeb3a32e09349
tree93115379214f671a11257e8677d2fe25753ab265
parent333e189ae496fed6af55e24d48ac4ad69bfe5a1f
haswell: use at least 64 URB entries for GT2+.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
src/i965_render.c