include/configs/ls1043aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1043AQDS_H__
   7 #define __LS1043AQDS_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  14 /* Physical Memory Map */
  15
  16 #define SPD_EEPROM_ADDRESS              0x51
  17 #define CONFIG_SYS_SPD_BUS_NUM          0
  18
  19 #ifdef CONFIG_DDR_ECC
  20 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  21 #endif
  22
  23 #ifdef CONFIG_SYS_DPAA_FMAN
  24 #define RGMII_PHY1_ADDR         0x1
  25 #define RGMII_PHY2_ADDR         0x2
  26 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  27 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  28 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  29 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  30 /* PHY address on QSGMII riser card on slot 1 */
  31 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  32 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  33 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  34 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  35 /* PHY address on QSGMII riser card on slot 2 */
  36 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  37 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  38 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  39 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  40 #endif
  41
  42 /* SATA */
  43
  44 /* EEPROM */
  45 #define CONFIG_SYS_I2C_EEPROM_NXID
  46 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  47
  48 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
  49
  50 /*
  51  * IFC Definitions
  52  */
  53 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  54 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  55 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  56                                 CSPR_PORT_SIZE_16 | \
  57                                 CSPR_MSEL_NOR | \
  58                                 CSPR_V)
  59 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  60 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  61                                 + 0x8000000) | \
  62                                 CSPR_PORT_SIZE_16 | \
  63                                 CSPR_MSEL_NOR | \
  64                                 CSPR_V)
  65 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  66
  67 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  68                                         CSOR_NOR_TRHZ_80)
  69 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  70                                         FTIM0_NOR_TEADC(0x5) | \
  71                                         FTIM0_NOR_TEAHC(0x5))
  72 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  73                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  74                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  75 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  76                                         FTIM2_NOR_TCH(0x4) | \
  77                                         FTIM2_NOR_TWPH(0xe) | \
  78                                         FTIM2_NOR_TWP(0x1c))
  79 #define CONFIG_SYS_NOR_FTIM3            0
  80
  81 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  82 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  83 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  84
  85 #define CONFIG_SYS_FLASH_EMPTY_INFO
  86 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  87                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  88
  89 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  90
  91 /*
  92  * NAND Flash Definitions
  93  */
  94
  95 #define CONFIG_SYS_NAND_BASE            0x7e800000
  96 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  97
  98 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  99
 100 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 101                                 | CSPR_PORT_SIZE_8      \
 102                                 | CSPR_MSEL_NAND        \
 103                                 | CSPR_V)
 104 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 105 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 106                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 107                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 108                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 109                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 110                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 111                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 112
 113 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 114                                         FTIM0_NAND_TWP(0x18)   | \
 115                                         FTIM0_NAND_TWCHT(0x7) | \
 116                                         FTIM0_NAND_TWH(0xa))
 117 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 118                                         FTIM1_NAND_TWBE(0x39)  | \
 119                                         FTIM1_NAND_TRR(0xe)   | \
 120                                         FTIM1_NAND_TRP(0x18))
 121 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 122                                         FTIM2_NAND_TREH(0xa) | \
 123                                         FTIM2_NAND_TWHRE(0x1e))
 124 #define CONFIG_SYS_NAND_FTIM3           0x0
 125
 126 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 127 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 128 #define CONFIG_MTD_NAND_VERIFY_WRITE
 129 #endif
 130
 131 #ifdef CONFIG_NAND_BOOT
 132 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 133 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 134 #endif
 135
 136 #if defined(CONFIG_TFABOOT) || \
 137         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 138 #define CONFIG_QIXIS_I2C_ACCESS
 139 #endif
 140
 141 /*
 142  * QIXIS Definitions
 143  */
 144 #define CONFIG_FSL_QIXIS
 145
 146 #ifdef CONFIG_FSL_QIXIS
 147 #define QIXIS_BASE                      0x7fb00000
 148 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 149 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 150 #define QIXIS_LBMAP_SWITCH              6
 151 #define QIXIS_LBMAP_MASK                0x0f
 152 #define QIXIS_LBMAP_SHIFT               0
 153 #define QIXIS_LBMAP_DFLTBANK            0x00
 154 #define QIXIS_LBMAP_ALTBANK             0x04
 155 #define QIXIS_LBMAP_NAND                0x09
 156 #define QIXIS_LBMAP_SD                  0x00
 157 #define QIXIS_LBMAP_SD_QSPI             0xff
 158 #define QIXIS_LBMAP_QSPI                0xff
 159 #define QIXIS_RCW_SRC_NAND              0x106
 160 #define QIXIS_RCW_SRC_SD                0x040
 161 #define QIXIS_RCW_SRC_QSPI              0x045
 162 #define QIXIS_RST_CTL_RESET             0x41
 163 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 164 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 165 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 166
 167 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 168 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 169                                         CSPR_PORT_SIZE_8 | \
 170                                         CSPR_MSEL_GPCM | \
 171                                         CSPR_V)
 172 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 173 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 174                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 175                                         CSOR_NOR_TRHZ_80)
 176
 177 /*
 178  * QIXIS Timing parameters for IFC GPCM
 179  */
 180 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 181                                         FTIM0_GPCM_TEADC(0x20) | \
 182                                         FTIM0_GPCM_TEAHC(0x10))
 183 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 184                                         FTIM1_GPCM_TRAD(0x1f))
 185 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 186                                         FTIM2_GPCM_TCH(0x8) | \
 187                                         FTIM2_GPCM_TWP(0xf0))
 188 #define CONFIG_SYS_FPGA_FTIM3           0x0
 189 #endif
 190
 191 #ifdef CONFIG_TFABOOT
 192 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 193 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 194 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 195 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 196 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 197 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 198 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 199 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 200 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 201 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 202 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 203 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 204 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 205 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 206 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 207 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 208 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 209 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 210 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 211 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 212 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 213 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 214 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 215 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 216 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 217 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 218 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 219 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 220 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 221 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 222 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 223 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 224 #else
 225 #ifdef CONFIG_NAND_BOOT
 226 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 227 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 228 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 229 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 230 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 231 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 232 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 233 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 234 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 235 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 236 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 237 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 238 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 239 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 240 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 241 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 242 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 243 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 244 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 245 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 246 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 247 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 248 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 249 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 250 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 251 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 252 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 253 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 254 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 255 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 256 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 257 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 258 #else
 259 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 260 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 261 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 262 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 263 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 264 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 265 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 266 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 267 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 268 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 269 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 270 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 271 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 272 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 273 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 274 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 275 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 276 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 277 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 278 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 279 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 280 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 281 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 282 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 283 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 284 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 285 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 286 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 287 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 288 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 289 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 290 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 291 #endif
 292 #endif
 293
 294 /*
 295  * I2C bus multiplexer
 296  */
 297 #define I2C_MUX_PCA_ADDR_PRI            0x77
 298 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 299 #define I2C_RETIMER_ADDR                0x18
 300 #define I2C_MUX_CH_DEFAULT              0x8
 301 #define I2C_MUX_CH_CH7301               0xC
 302 #define I2C_MUX_CH5                     0xD
 303 #define I2C_MUX_CH7                     0xF
 304
 305 #define I2C_MUX_CH_VOL_MONITOR 0xa
 306
 307 /* Voltage monitor on channel 2*/
 308 #define I2C_VOL_MONITOR_ADDR           0x40
 309 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 310 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 311 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 312
 313 /* The lowest and highest voltage allowed for LS1043AQDS */
 314 #define VDD_MV_MIN                      819
 315 #define VDD_MV_MAX                      1212
 316
 317 /*
 318  * Miscellaneous configurable options
 319  */
 320
 321 #define CONFIG_SYS_INIT_SP_OFFSET \
 322         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 323
 324 /*
 325  * Environment
 326  */
 327
 328 #include <asm/fsl_secure_boot.h>
 329
 330 #endif /* __LS1043AQDS_H__ */