include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_PAD_TO               0x40000
  20 #define CONFIG_SPL_MAX_SIZE             0x28000
  21 #ifdef CONFIG_SPL_BUILD
  22 #define CONFIG_SPL_SKIP_RELOCATE
  23 #define CONFIG_SPL_COMMON_INIT_DDR
  24 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  25 #endif
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef CONFIG_MTD_RAW_NAND
  30 #ifdef CONFIG_NXP_ESBC
  31 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  32 /*
  33  * HDR would be appended at end of image and copied to DDR along
  34  * with U-Boot image.
  35  */
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  37                                          CONFIG_U_BOOT_HDR_SIZE)
  38 #else
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  40 #endif
  41 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  42 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  43 #endif
  44
  45 #ifdef CONFIG_SPIFLASH
  46 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  47 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  52 #ifndef CONFIG_SPL_BUILD
  53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54 #endif
  55 #endif
  56
  57 #ifdef CONFIG_SDCARD
  58 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  59 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  60 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  61 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  62 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  63 #ifndef CONFIG_SPL_BUILD
  64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65 #endif
  66 #endif
  67
  68 #endif
  69
  70 /* High Level Configuration Options */
  71 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  72
  73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  74 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  75 #endif
  76
  77 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  78 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  79 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  80 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  81 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  82 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  83
  84 #if defined(CONFIG_SPIFLASH)
  85 #elif defined(CONFIG_MTD_RAW_NAND)
  86 #ifdef CONFIG_NXP_ESBC
  87 #define CONFIG_RAMBOOT_NAND
  88 #define CONFIG_BOOTSCRIPT_COPY_RAM
  89 #endif
  90 #endif
  91
  92 /*
  93  * These can be toggled for performance analysis, otherwise use default.
  94  */
  95 #define CONFIG_SYS_CACHE_STASHING
  96 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  97 #ifdef CONFIG_DDR_ECC
  98 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  99 #endif
 100
 101 #define CONFIG_ENABLE_36BIT_PHYS
 102
 103 /*
 104  *  Config the L3 Cache as L3 SRAM
 105  */
 106 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 107 /*
 108  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 109  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 110  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 111  */
 112 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 113 #define CONFIG_SYS_L3_SIZE              256 << 10
 114 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 115 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 116 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 117 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 118 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 119
 120 #define CONFIG_SYS_DCSRBAR              0xf0000000
 121 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 122
 123 /*
 124  * DDR Setup
 125  */
 126 #define CONFIG_VERY_BIG_RAM
 127 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 128 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 129
 130 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 131
 132 #define CONFIG_SYS_SPD_BUS_NUM  0
 133 #define SPD_EEPROM_ADDRESS      0x51
 134
 135 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 136
 137 /*
 138  * IFC Definitions
 139  */
 140 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 141 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 142
 143 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 144 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 145                                 CSPR_PORT_SIZE_16 | \
 146                                 CSPR_MSEL_NOR | \
 147                                 CSPR_V)
 148 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 149
 150 /*
 151  * TDM Definition
 152  */
 153 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 154
 155 /* NOR Flash Timing Params */
 156 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 157 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 158                                 FTIM0_NOR_TEADC(0x5) | \
 159                                 FTIM0_NOR_TEAHC(0x5))
 160 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 161                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 162                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 163 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 164                                 FTIM2_NOR_TCH(0x4) | \
 165                                 FTIM2_NOR_TWPH(0x0E) | \
 166                                 FTIM2_NOR_TWP(0x1c))
 167 #define CONFIG_SYS_NOR_FTIM3    0x0
 168
 169 #define CONFIG_SYS_FLASH_QUIET_TEST
 170 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 171
 172 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 173 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 174 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 175
 176 #define CONFIG_SYS_FLASH_EMPTY_INFO
 177 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 178
 179 /* CPLD on IFC */
 180 #define CPLD_LBMAP_MASK                 0x3F
 181 #define CPLD_BANK_SEL_MASK              0x07
 182 #define CPLD_BANK_OVERRIDE              0x40
 183 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 184 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 185 #define CPLD_LBMAP_RESET                0xFF
 186 #define CPLD_LBMAP_SHIFT                0x03
 187
 188 #if defined(CONFIG_TARGET_T1042RDB_PI)
 189 #define CPLD_DIU_SEL_DFP                0x80
 190 #elif defined(CONFIG_TARGET_T1042D4RDB)
 191 #define CPLD_DIU_SEL_DFP                0xc0
 192 #endif
 193
 194 #if defined(CONFIG_TARGET_T1040D4RDB)
 195 #define CPLD_INT_MASK_ALL               0xFF
 196 #define CPLD_INT_MASK_THERM             0x80
 197 #define CPLD_INT_MASK_DVI_DFP           0x40
 198 #define CPLD_INT_MASK_QSGMII1           0x20
 199 #define CPLD_INT_MASK_QSGMII2           0x10
 200 #define CPLD_INT_MASK_SGMI1             0x08
 201 #define CPLD_INT_MASK_SGMI2             0x04
 202 #define CPLD_INT_MASK_TDMR1             0x02
 203 #define CPLD_INT_MASK_TDMR2             0x01
 204 #endif
 205
 206 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 207 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 208 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 209 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 210                                 | CSPR_PORT_SIZE_8 \
 211                                 | CSPR_MSEL_GPCM \
 212                                 | CSPR_V)
 213 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 214 #define CONFIG_SYS_CSOR2        0x0
 215 /* CPLD Timing parameters for IFC CS2 */
 216 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 217                                         FTIM0_GPCM_TEADC(0x0e) | \
 218                                         FTIM0_GPCM_TEAHC(0x0e))
 219 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 220                                         FTIM1_GPCM_TRAD(0x1f))
 221 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 222                                         FTIM2_GPCM_TCH(0x8) | \
 223                                         FTIM2_GPCM_TWP(0x1f))
 224 #define CONFIG_SYS_CS2_FTIM3            0x0
 225
 226 /* NAND Flash on IFC */
 227 #define CONFIG_SYS_NAND_BASE            0xff800000
 228 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 229
 230 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 231 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 232                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 233                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 234                                 | CSPR_V)
 235 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 236
 237 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 238                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 239                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 240                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 241                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 242                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 243                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 244
 245 /* ONFI NAND Flash mode0 Timing Params */
 246 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 247                                         FTIM0_NAND_TWP(0x18)   | \
 248                                         FTIM0_NAND_TWCHT(0x07) | \
 249                                         FTIM0_NAND_TWH(0x0a))
 250 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 251                                         FTIM1_NAND_TWBE(0x39)  | \
 252                                         FTIM1_NAND_TRR(0x0e)   | \
 253                                         FTIM1_NAND_TRP(0x18))
 254 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 255                                         FTIM2_NAND_TREH(0x0a) | \
 256                                         FTIM2_NAND_TWHRE(0x1e))
 257 #define CONFIG_SYS_NAND_FTIM3           0x0
 258
 259 #define CONFIG_SYS_NAND_DDR_LAW         11
 260 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 261 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 262
 263 #if defined(CONFIG_MTD_RAW_NAND)
 264 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 265 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 266 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 267 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 268 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 269 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 270 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 271 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 272 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 273 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 274 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 275 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 276 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 277 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 278 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 279 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 280 #else
 281 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 282 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 283 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 284 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 285 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 286 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 287 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 288 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 289 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 290 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 291 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 292 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 293 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 294 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 295 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 296 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 297 #endif
 298
 299 #if defined(CONFIG_RAMBOOT_PBL)
 300 #define CONFIG_SYS_RAMBOOT
 301 #endif
 302
 303 #define CONFIG_HWCONFIG
 304
 305 /* define to use L1 as initial stack */
 306 #define CONFIG_L1_INIT_RAM
 307 #define CONFIG_SYS_INIT_RAM_LOCK
 308 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 311 /* The assembler doesn't like typecast */
 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 313         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 314           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 315 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 316
 317 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 318                                         GENERATED_GBL_DATA_SIZE)
 319 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 320
 321 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 322
 323 /* Serial Port - controlled on board with jumper J8
 324  * open - index 2
 325  * shorted - index 1
 326  */
 327 #define CONFIG_SYS_NS16550_SERIAL
 328 #define CONFIG_SYS_NS16550_REG_SIZE     1
 329 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 330
 331 #define CONFIG_SYS_BAUDRATE_TABLE       \
 332         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 333
 334 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 335 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 336 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 337 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 338
 339 /* I2C bus multiplexer */
 340 #define I2C_MUX_PCA_ADDR                0x70
 341 #define I2C_MUX_CH_DEFAULT      0x8
 342
 343 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 344         defined(CONFIG_TARGET_T1040D4RDB)       || \
 345         defined(CONFIG_TARGET_T1042D4RDB)
 346 /* LDI/DVI Encoder for display */
 347 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 348 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 349 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 350
 351 /*
 352  * RTC configuration
 353  */
 354 #define RTC
 355 #define CONFIG_RTC_DS1337               1
 356 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 357
 358 /*DVI encoder*/
 359 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 360 #endif
 361
 362 /*
 363  * eSPI - Enhanced SPI
 364  */
 365
 366 /*
 367  * General PCI
 368  * Memory space is mapped 1-1, but I/O space must start from 0.
 369  */
 370
 371 #ifdef CONFIG_PCI
 372 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 373 #ifdef CONFIG_PCIE1
 374 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 375 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 376 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 377 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 378 #endif
 379
 380 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 381 #ifdef CONFIG_PCIE2
 382 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 383 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 384 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 385 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 386 #endif
 387
 388 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 389 #ifdef CONFIG_PCIE3
 390 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 391 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 392 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 393 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 394 #endif
 395
 396 /* controller 4, Base address 203000 */
 397 #ifdef CONFIG_PCIE4
 398 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 399 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 400 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 401 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 402 #endif
 403
 404 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 405 #endif  /* CONFIG_PCI */
 406
 407 /* SATA */
 408 #define CONFIG_FSL_SATA_V2
 409 #ifdef CONFIG_FSL_SATA_V2
 410 #define CONFIG_SATA1
 411 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 412 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 413
 414 #define CONFIG_LBA48
 415 #endif
 416
 417 /*
 418 * USB
 419 */
 420 #define CONFIG_HAS_FSL_DR_USB
 421
 422 #ifdef CONFIG_HAS_FSL_DR_USB
 423 #ifdef CONFIG_USB_EHCI_HCD
 424 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 425 #endif
 426 #endif
 427
 428 #ifdef CONFIG_MMC
 429 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 430 #endif
 431
 432 /* Qman/Bman */
 433 #ifndef CONFIG_NOBQFMAN
 434 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 435 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 436 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 437 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 438 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 439 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 440 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 441 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 442 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 443                                         CONFIG_SYS_BMAN_CENA_SIZE)
 444 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 445 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 446 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 447 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 448 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 449 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 450 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 451 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 452 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 453 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 454 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 455                                         CONFIG_SYS_QMAN_CENA_SIZE)
 456 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 457 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 458
 459 #define CONFIG_SYS_DPAA_FMAN
 460 #define CONFIG_SYS_DPAA_PME
 461
 462 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 463 #endif /* CONFIG_NOBQFMAN */
 464
 465 #ifdef CONFIG_FMAN_ENET
 466 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 467 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 468 #elif defined(CONFIG_TARGET_T1040D4RDB)
 469 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 470 #elif defined(CONFIG_TARGET_T1042D4RDB)
 471 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 472 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 473 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 474 #endif
 475
 476 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 477 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 478 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 479 #else
 480 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 481 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 482 #endif
 483
 484 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 485 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 486 #define CONFIG_VSC9953
 487 #ifdef CONFIG_TARGET_T1040RDB
 488 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 489 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 490 #else
 491 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 492 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 493 #endif
 494 #endif
 495 #endif
 496
 497 /*
 498  * Environment
 499  */
 500 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 501 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 502
 503 /*
 504  * Miscellaneous configurable options
 505  */
 506
 507 /*
 508  * For booting Linux, the board info and command line data
 509  * have to be in the first 64 MB of memory, since this is
 510  * the maximum mapped by the Linux kernel during initialization.
 511  */
 512 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 513 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 514
 515 /*
 516  * Dynamic MTD Partition support with mtdparts
 517  */
 518
 519 /*
 520  * Environment Configuration
 521  */
 522 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 523 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 524
 525 #define __USB_PHY_TYPE  utmi
 526 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 527
 528 #ifdef CONFIG_TARGET_T1040RDB
 529 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 530 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 531 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 532 #elif defined(CONFIG_TARGET_T1042RDB)
 533 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 534 #elif defined(CONFIG_TARGET_T1040D4RDB)
 535 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 536 #elif defined(CONFIG_TARGET_T1042D4RDB)
 537 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 538 #endif
 539
 540 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 541         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 542         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 543         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 544         "netdev=eth0\0"                                         \
 545         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 546         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 547         "tftpflash=tftpboot $loadaddr $uboot && "               \
 548         "protect off $ubootaddr +$filesize && "                 \
 549         "erase $ubootaddr +$filesize && "                       \
 550         "cp.b $loadaddr $ubootaddr $filesize && "               \
 551         "protect on $ubootaddr +$filesize && "                  \
 552         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 553         "consoledev=ttyS0\0"                                    \
 554         "ramdiskaddr=2000000\0"                                 \
 555         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 556         "fdtaddr=1e00000\0"                                     \
 557         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 558         "bdev=sda3\0"
 559
 560 #include <asm/fsl_secure_boot.h>
 561
 562 #endif  /* __CONFIG_H */