4 * Copyright (c) 2011 Samsung Electronics Co., Ltd All Rights Reserved
7 * YeongKyoon Lee <yeongkyoon.lee@samsung.com>
8 * SeokYeon Hwang <syeon.hwang@samsung.com>
9 * SangJin Kim <sangjin3.kim@samsung.com>
10 * KiTae Kim <kt920.kim@samsung.com>
11 * JinHyung Jo <jinhyung.jo@samsung.com>
12 * SungMin Ha <sungmin82.ha@samsung.com>
13 * MunKyu Im <munkyu.im@samsung.com>
14 * JiHye Kim <jihye1128.kim@samsung.com>
15 * GiWoong Kim <giwoong.kim@samsung.com>
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version 2
23 * of the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
37 * x86 board from pc_piix.c...
38 * add some TIZEN-speciaized device...
53 #include "kvm/clock.h"
56 #include "arch_init.h"
61 #include "exec-memory.h"
63 # include <xen/hvm/hvm_info_table.h>
66 #include "maru_common.h"
67 #include "guest_debug.h"
70 int codec_init(PCIBus *bus);
75 static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
76 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
77 static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
79 static void kvm_piix3_setup_irq_routing(bool pci_enabled)
82 KVMState *s = kvm_state;
85 if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
86 for (i = 0; i < 8; ++i) {
90 kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
92 for (i = 8; i < 16; ++i) {
93 kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
96 for (i = 0; i < 24; ++i) {
98 kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
100 kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
105 #endif /* CONFIG_KVM */
108 static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
110 GSIState *s = opaque;
112 if (n < ISA_NUM_IRQS) {
113 /* Kernel will forward to both PIC and IOAPIC */
114 qemu_set_irq(s->i8259_irq[n], level);
116 qemu_set_irq(s->ioapic_irq[n], level);
120 static void ioapic_init(GSIState *gsi_state)
126 if (kvm_irqchip_in_kernel()) {
127 dev = qdev_create(NULL, "kvm-ioapic");
129 dev = qdev_create(NULL, "ioapic");
131 /* FIXME: this should be under the piix3. */
132 object_property_add_child(object_resolve_path("i440fx", NULL),
133 "ioapic", OBJECT(dev), NULL);
134 qdev_init_nofail(dev);
135 d = sysbus_from_qdev(dev);
136 sysbus_mmio_map(d, 0, 0xfec00000);
138 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
139 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
143 MemoryRegion *global_ram_memory;
145 MemoryRegion *get_ram_memory(void)
147 return global_ram_memory;
150 static void maru_x86_machine_init(MemoryRegion *system_memory,
151 MemoryRegion *system_io,
153 const char *boot_device,
154 const char *kernel_filename,
155 const char *kernel_cmdline,
156 const char *initrd_filename,
157 const char *cpu_model,
159 int kvmclock_enabled)
162 ram_addr_t below_4g_mem_size, above_4g_mem_size;
165 PCII440FXState *i440fx_state;
166 int piix3_devfn = -1;
172 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
173 BusState *idebus[MAX_IDE_BUS];
174 ISADevice *rtc_state;
176 MemoryRegion *ram_memory;
177 MemoryRegion *pci_memory;
178 MemoryRegion *rom_memory;
181 pc_cpus_init(cpu_model);
183 if (kvmclock_enabled) {
187 if (ram_size >= 0xe0000000 ) {
188 above_4g_mem_size = ram_size - 0xe0000000;
189 below_4g_mem_size = 0xe0000000;
191 above_4g_mem_size = 0;
192 below_4g_mem_size = ram_size;
196 pci_memory = g_new(MemoryRegion, 1);
197 memory_region_init(pci_memory, "pci", INT64_MAX);
198 rom_memory = pci_memory;
201 rom_memory = system_memory;
204 /* allocate ram and load rom/bios */
205 if (!xen_enabled()) {
206 // W/A for allocate larger continuous heap.
208 if(preallocated_ptr != NULL) {
209 qemu_vfree(preallocated_ptr);
212 fw_cfg = pc_memory_init(system_memory,
213 kernel_filename, kernel_cmdline, initrd_filename,
214 below_4g_mem_size, above_4g_mem_size,
215 pci_enabled ? rom_memory : system_memory, &ram_memory);
219 global_ram_memory = ram_memory;
221 gsi_state = g_malloc0(sizeof(*gsi_state));
222 if (kvm_irqchip_in_kernel()) {
223 kvm_piix3_setup_irq_routing(pci_enabled);
224 gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
227 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
231 pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
232 system_memory, system_io, ram_size,
234 0x100000000ULL - below_4g_mem_size,
235 0x100000000ULL + above_4g_mem_size,
236 (sizeof(target_phys_addr_t) == 4
238 : ((uint64_t)1 << 62)),
239 pci_memory, ram_memory);
243 isa_bus = isa_bus_new(NULL, system_io);
246 isa_bus_irqs(isa_bus, gsi);
248 if (kvm_irqchip_in_kernel()) {
249 i8259 = kvm_i8259_init(isa_bus);
250 } else if (xen_enabled()) {
251 i8259 = xen_interrupt_controller_init();
253 cpu_irq = pc_allocate_cpu_irq();
254 i8259 = i8259_init(isa_bus, cpu_irq[0]);
257 for (i = 0; i < ISA_NUM_IRQS; i++) {
258 gsi_state->i8259_irq[i] = i8259[i];
261 ioapic_init(gsi_state);
265 pc_register_ferr_irq(gsi[13]);
267 pc_vga_init(isa_bus, pci_enabled ? pci_bus : NULL);
269 pci_create_simple(pci_bus, -1, "xen-platform");
271 /* init basic PC hardware */
272 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
274 for(i = 0; i < nb_nics; i++) {
275 NICInfo *nd = &nd_table[i];
277 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
278 pc_init_ne2k_isa(isa_bus, nd);
280 pci_nic_init_nofail(nd, "e1000", NULL);
283 ide_drive_get(hd, MAX_IDE_BUS);
287 dev = pci_piix3_xen_ide_init(pci_bus, hd, piix3_devfn + 1);
289 dev = pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
291 idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
292 idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
294 for(i = 0; i < MAX_IDE_BUS; i++) {
296 dev = isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i],
298 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
299 idebus[i] = qdev_get_child_bus(&dev->qdev, "ide.0");
303 // commented out by caramis... for use 'tizen-ac97'...
304 // reopen for qemu 1.0 merging...
305 audio_init(isa_bus, pci_enabled ? pci_bus : NULL);
307 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
308 floppy, idebus[0], idebus[1], rtc_state);
310 if (pci_enabled && usb_enabled) {
311 pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
314 if (pci_enabled && acpi_enabled) {
317 smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
318 /* TODO: Populate SPD eeprom data. */
319 #if defined(__x86_64__)
320 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
321 gsi[9], *smi_irq, kvm_enabled(), fw_cfg);
324 smbus = maru_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
325 gsi[9], *smi_irq, kvm_enabled(), fw_cfg);
327 smbus_eeprom_init(smbus, 8, NULL, 0);
331 pc_pci_device_init(pci_bus);
334 // maru specialized device init...
339 pci_create_simple(pci_bus, -1, "yagl");
343 static void maru_x86_board_init(ram_addr_t ram_size,
344 const char *boot_device,
345 const char *kernel_filename,
346 const char *kernel_cmdline,
347 const char *initrd_filename,
348 const char *cpu_model)
350 maru_x86_machine_init(get_system_memory(),
352 ram_size, boot_device,
353 kernel_filename, kernel_cmdline,
354 initrd_filename, cpu_model, 1, 1);
357 static QEMUMachine maru_x86_machine = {
358 .name = "maru-x86-machine",
359 .desc = "maru board(x86)",
360 .init = maru_x86_board_init,
364 static void maru_machine_init(void)
366 qemu_register_machine(&maru_x86_machine);
369 machine_init(maru_machine_init);