2 * Microblaze helper routines.
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "dyngen-exec.h"
24 #include "host-utils.h"
28 #if !defined(CONFIG_USER_ONLY)
29 #include "softmmu_exec.h"
31 #define MMUSUFFIX _mmu
33 #include "softmmu_template.h"
35 #include "softmmu_template.h"
37 #include "softmmu_template.h"
39 #include "softmmu_template.h"
41 /* Try to fill the TLB and return an exception if error. If retaddr is
42 NULL, it means that the function was called in C code (i.e. not
43 from generated code or from helper.c) */
44 /* XXX: fix it to restore all registers */
45 void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
56 ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
59 /* now we have a real cpu fault */
60 pc = (unsigned long)retaddr;
63 /* the PC is inside the translated code. It means that we have
64 a virtual CPU fault */
65 cpu_restore_state(tb, env, pc);
74 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
76 int test = ctrl & STREAM_TEST;
77 int atomic = ctrl & STREAM_ATOMIC;
78 int control = ctrl & STREAM_CONTROL;
79 int nonblock = ctrl & STREAM_NONBLOCK;
80 int exception = ctrl & STREAM_EXCEPTION;
82 qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
91 uint32_t helper_get(uint32_t id, uint32_t ctrl)
93 int test = ctrl & STREAM_TEST;
94 int atomic = ctrl & STREAM_ATOMIC;
95 int control = ctrl & STREAM_CONTROL;
96 int nonblock = ctrl & STREAM_NONBLOCK;
97 int exception = ctrl & STREAM_EXCEPTION;
99 qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
103 exception ? "e" : "",
106 return 0xdead0000 | id;
109 void helper_raise_exception(uint32_t index)
111 env->exception_index = index;
115 void helper_debug(void)
119 qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
120 qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
121 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
122 env->debug, env->imm, env->iflags);
123 qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
124 env->btaken, env->btarget,
125 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
126 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
127 (env->sregs[SR_MSR] & MSR_EIP),
128 (env->sregs[SR_MSR] & MSR_IE));
129 for (i = 0; i < 32; i++) {
130 qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
131 if ((i + 1) % 4 == 0)
137 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
141 if ((b == ~0) && cin)
143 else if ((~0 - a) < (b + cin))
148 uint32_t helper_cmp(uint32_t a, uint32_t b)
153 if ((b & 0x80000000) ^ (a & 0x80000000))
154 t = (t & 0x7fffffff) | (b & 0x80000000);
158 uint32_t helper_cmpu(uint32_t a, uint32_t b)
163 if ((b & 0x80000000) ^ (a & 0x80000000))
164 t = (t & 0x7fffffff) | (a & 0x80000000);
168 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
171 ncf = compute_carry(a, b, cf);
175 static inline int div_prepare(uint32_t a, uint32_t b)
178 env->sregs[SR_MSR] |= MSR_DZ;
180 if ((env->sregs[SR_MSR] & MSR_EE)
181 && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
182 env->sregs[SR_ESR] = ESR_EC_DIVZERO;
183 helper_raise_exception(EXCP_HW_EXCP);
187 env->sregs[SR_MSR] &= ~MSR_DZ;
191 uint32_t helper_divs(uint32_t a, uint32_t b)
193 if (!div_prepare(a, b))
195 return (int32_t)a / (int32_t)b;
198 uint32_t helper_divu(uint32_t a, uint32_t b)
200 if (!div_prepare(a, b))
205 /* raise FPU exception. */
206 static void raise_fpu_exception(void)
208 env->sregs[SR_ESR] = ESR_EC_FPU;
209 helper_raise_exception(EXCP_HW_EXCP);
212 static void update_fpu_flags(int flags)
216 if (flags & float_flag_invalid) {
217 env->sregs[SR_FSR] |= FSR_IO;
220 if (flags & float_flag_divbyzero) {
221 env->sregs[SR_FSR] |= FSR_DZ;
224 if (flags & float_flag_overflow) {
225 env->sregs[SR_FSR] |= FSR_OF;
228 if (flags & float_flag_underflow) {
229 env->sregs[SR_FSR] |= FSR_UF;
233 && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
234 && (env->sregs[SR_MSR] & MSR_EE)) {
235 raise_fpu_exception();
239 uint32_t helper_fadd(uint32_t a, uint32_t b)
241 CPU_FloatU fd, fa, fb;
244 set_float_exception_flags(0, &env->fp_status);
247 fd.f = float32_add(fa.f, fb.f, &env->fp_status);
249 flags = get_float_exception_flags(&env->fp_status);
250 update_fpu_flags(flags);
254 uint32_t helper_frsub(uint32_t a, uint32_t b)
256 CPU_FloatU fd, fa, fb;
259 set_float_exception_flags(0, &env->fp_status);
262 fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
263 flags = get_float_exception_flags(&env->fp_status);
264 update_fpu_flags(flags);
268 uint32_t helper_fmul(uint32_t a, uint32_t b)
270 CPU_FloatU fd, fa, fb;
273 set_float_exception_flags(0, &env->fp_status);
276 fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
277 flags = get_float_exception_flags(&env->fp_status);
278 update_fpu_flags(flags);
283 uint32_t helper_fdiv(uint32_t a, uint32_t b)
285 CPU_FloatU fd, fa, fb;
288 set_float_exception_flags(0, &env->fp_status);
291 fd.f = float32_div(fb.f, fa.f, &env->fp_status);
292 flags = get_float_exception_flags(&env->fp_status);
293 update_fpu_flags(flags);
298 uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
306 if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
307 update_fpu_flags(float_flag_invalid);
311 if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
318 uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
324 set_float_exception_flags(0, &env->fp_status);
327 r = float32_lt(fb.f, fa.f, &env->fp_status);
328 flags = get_float_exception_flags(&env->fp_status);
329 update_fpu_flags(flags & float_flag_invalid);
334 uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
340 set_float_exception_flags(0, &env->fp_status);
343 r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
344 flags = get_float_exception_flags(&env->fp_status);
345 update_fpu_flags(flags & float_flag_invalid);
350 uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
358 set_float_exception_flags(0, &env->fp_status);
359 r = float32_le(fa.f, fb.f, &env->fp_status);
360 flags = get_float_exception_flags(&env->fp_status);
361 update_fpu_flags(flags & float_flag_invalid);
367 uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
374 set_float_exception_flags(0, &env->fp_status);
375 r = float32_lt(fa.f, fb.f, &env->fp_status);
376 flags = get_float_exception_flags(&env->fp_status);
377 update_fpu_flags(flags & float_flag_invalid);
381 uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
388 set_float_exception_flags(0, &env->fp_status);
389 r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
390 flags = get_float_exception_flags(&env->fp_status);
391 update_fpu_flags(flags & float_flag_invalid);
396 uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
403 set_float_exception_flags(0, &env->fp_status);
404 r = !float32_lt(fa.f, fb.f, &env->fp_status);
405 flags = get_float_exception_flags(&env->fp_status);
406 update_fpu_flags(flags & float_flag_invalid);
411 uint32_t helper_flt(uint32_t a)
416 fd.f = int32_to_float32(fa.l, &env->fp_status);
420 uint32_t helper_fint(uint32_t a)
426 set_float_exception_flags(0, &env->fp_status);
428 r = float32_to_int32(fa.f, &env->fp_status);
429 flags = get_float_exception_flags(&env->fp_status);
430 update_fpu_flags(flags);
435 uint32_t helper_fsqrt(uint32_t a)
440 set_float_exception_flags(0, &env->fp_status);
442 fd.l = float32_sqrt(fa.f, &env->fp_status);
443 flags = get_float_exception_flags(&env->fp_status);
444 update_fpu_flags(flags);
449 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
452 uint32_t mask = 0xff000000;
454 for (i = 0; i < 4; i++) {
455 if ((a & mask) == (b & mask))
462 void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
465 qemu_log_mask(CPU_LOG_INT,
466 "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
468 env->sregs[SR_EAR] = addr;
469 env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
472 env->sregs[SR_ESR] |= 1 << 11;
474 if (!(env->sregs[SR_MSR] & MSR_EE)) {
477 helper_raise_exception(EXCP_HW_EXCP);
481 #if !defined(CONFIG_USER_ONLY)
482 /* Writes/reads to the MMU's special regs end up here. */
483 uint32_t helper_mmu_read(uint32_t rn)
485 return mmu_read(env, rn);
488 void helper_mmu_write(uint32_t rn, uint32_t v)
490 mmu_write(env, rn, v);
493 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
494 int is_write, int is_exec, int is_asi, int size)
501 qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
502 addr, is_write, is_exec);
503 if (!(env->sregs[SR_MSR] & MSR_EE)) {
508 env->sregs[SR_EAR] = addr;
510 if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
511 env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
512 helper_raise_exception(EXCP_HW_EXCP);
515 if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
516 env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
517 helper_raise_exception(EXCP_HW_EXCP);