1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "pci.h" // pci_find_device
11 #include "biosvar.h" // GET_EBDA
12 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
15 #include "dev-i440fx.h" // piix4_fadt_init
17 /****************************************************/
18 /* ACPI tables init */
20 /* Table structure from Linux kernel (the ACPI tables are under the
23 struct acpi_table_header /* ACPI common table header */
29 * ACPI 1.0 Root System Description Table (RSDT)
31 #define RSDT_SIGNATURE 0x54445352 // RSDT
32 struct rsdt_descriptor_rev1
34 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
35 u32 table_offset_entry[0]; /* Array of pointers to other */
40 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
42 #define FACS_SIGNATURE 0x53434146 // FACS
43 struct facs_descriptor_rev1
45 u32 signature; /* ACPI Signature */
46 u32 length; /* Length of structure, in bytes */
47 u32 hardware_signature; /* Hardware configuration signature */
48 u32 firmware_waking_vector; /* ACPI OS waking vector */
49 u32 global_lock; /* Global Lock */
50 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
51 u32 reserved1 : 31; /* Must be 0 */
52 u8 resverved3 [40]; /* Reserved - must be zero */
57 * MADT values and structures
60 /* Values for MADT PCATCompat */
63 #define MULTIPLE_APIC 1
68 #define APIC_SIGNATURE 0x43495041 // APIC
69 struct multiple_apic_table
71 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
72 u32 local_apic_address; /* Physical address of local APIC */
74 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
82 /* Values for Type in APIC sub-headers */
84 #define APIC_PROCESSOR 0
86 #define APIC_XRUPT_OVERRIDE 2
88 #define APIC_LOCAL_NMI 4
89 #define APIC_ADDRESS_OVERRIDE 5
90 #define APIC_IO_SAPIC 6
91 #define APIC_LOCAL_SAPIC 7
92 #define APIC_XRUPT_SOURCE 8
93 #define APIC_RESERVED 9 /* 9 and greater are reserved */
96 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
98 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
102 /* Sub-structures for MADT */
104 struct madt_processor_apic
107 u8 processor_id; /* ACPI processor id */
108 u8 local_apic_id; /* Processor's local APIC id */
110 u32 processor_enabled: 1; /* Processor is usable if set */
111 u32 reserved2 : 31; /* Reserved, must be zero */
120 u8 io_apic_id; /* I/O APIC ID */
121 u8 reserved; /* Reserved - must be zero */
122 u32 address; /* APIC physical address */
123 u32 interrupt; /* Global system interrupt where INTI
128 #define PCI_ISA_IRQ_MASK 0x0e20
130 struct madt_intsrcovr {
139 * ACPI 2.0 Generic Address Space definition.
141 struct acpi_20_generic_address {
143 u8 register_bit_width;
144 u8 register_bit_offset;
150 * HPET Description Table
152 struct acpi_20_hpet {
153 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
155 struct acpi_20_generic_address addr;
160 #define ACPI_HPET_ADDRESS 0xFED00000UL
163 * SRAT (NUMA topology description) table
166 #define SRAT_PROCESSOR 0
167 #define SRAT_MEMORY 1
169 struct system_resource_affinity_table
171 ACPI_TABLE_HEADER_DEF
176 struct srat_processor_affinity
187 struct srat_memory_affinity
192 u32 base_addr_low,base_addr_high;
193 u32 length_low,length_high;
199 #include "acpi-dsdt.hex"
202 build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
205 h->length = cpu_to_le32(len);
207 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
208 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
209 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
210 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
211 h->oem_revision = cpu_to_le32(1);
212 h->asl_compiler_revision = cpu_to_le32(1);
213 h->checksum -= checksum(h, len);
216 static const struct pci_device_id fadt_init_tbl[] = {
217 /* PIIX4 Power Management device (for ACPI) */
218 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
227 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
228 struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
229 void *dsdt = malloc_high(sizeof(AmlCode));
231 if (!fadt || !facs || !dsdt) {
237 memset(facs, 0, sizeof(*facs));
238 facs->signature = FACS_SIGNATURE;
239 facs->length = cpu_to_le32(sizeof(*facs));
242 memcpy(dsdt, AmlCode, sizeof(AmlCode));
245 memset(fadt, 0, sizeof(*fadt));
246 fadt->firmware_ctrl = cpu_to_le32((u32)facs);
247 fadt->dsdt = cpu_to_le32((u32)dsdt);
250 int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
251 fadt->sci_int = cpu_to_le16(pm_sci_int);
252 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
253 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
254 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
255 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
256 fadt->pm1_evt_len = 4;
257 fadt->pm1_cnt_len = 2;
258 fadt->pm_tmr_len = 4;
259 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
260 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
261 pci_init_device(fadt_init_tbl, bdf, fadt);
262 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
263 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
265 build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
273 int madt_size = (sizeof(struct multiple_apic_table)
274 + sizeof(struct madt_processor_apic) * MaxCountCPUs
275 + sizeof(struct madt_io_apic)
276 + sizeof(struct madt_intsrcovr) * 16);
277 struct multiple_apic_table *madt = malloc_high(madt_size);
282 memset(madt, 0, madt_size);
283 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
284 madt->flags = cpu_to_le32(1);
285 struct madt_processor_apic *apic = (void*)&madt[1];
287 for (i=0; i<MaxCountCPUs; i++) {
288 apic->type = APIC_PROCESSOR;
289 apic->length = sizeof(*apic);
290 apic->processor_id = i;
291 apic->local_apic_id = i;
293 apic->flags = cpu_to_le32(1);
295 apic->flags = cpu_to_le32(0);
298 struct madt_io_apic *io_apic = (void*)apic;
299 io_apic->type = APIC_IO;
300 io_apic->length = sizeof(*io_apic);
301 io_apic->io_apic_id = CountCPUs;
302 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
303 io_apic->interrupt = cpu_to_le32(0);
305 struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
306 if (qemu_cfg_irq0_override()) {
307 memset(intsrcovr, 0, sizeof(*intsrcovr));
308 intsrcovr->type = APIC_XRUPT_OVERRIDE;
309 intsrcovr->length = sizeof(*intsrcovr);
310 intsrcovr->source = 0;
312 intsrcovr->flags = 0; /* conforms to bus specifications */
315 for (i = 1; i < 16; i++) {
316 if (!(PCI_ISA_IRQ_MASK & (1 << i)))
317 /* No need for a INT source override structure. */
319 memset(intsrcovr, 0, sizeof(*intsrcovr));
320 intsrcovr->type = APIC_XRUPT_OVERRIDE;
321 intsrcovr->length = sizeof(*intsrcovr);
322 intsrcovr->source = i;
324 intsrcovr->flags = 0xd; /* active high, level triggered */
328 build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
332 // Encode a hex value
333 static inline char getHex(u32 val) {
335 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
338 // Encode a length in an SSDT.
340 encodeLen(u8 *ssdt_ptr, int length, int bytes)
344 case 4: ssdt_ptr[3] = ((length >> 20) & 0xff);
345 case 3: ssdt_ptr[2] = ((length >> 12) & 0xff);
346 case 2: ssdt_ptr[1] = ((length >> 4) & 0xff);
347 ssdt_ptr[0] = (((bytes-1) & 0x3) << 6) | (length & 0x0f);
349 case 1: ssdt_ptr[0] = length & 0x3f;
351 return ssdt_ptr + bytes;
354 // AML Processor() object. See src/ssdt-proc.dsl for info.
355 static unsigned char ssdt_proc[] = {
356 0x5b,0x83,0x42,0x05,0x43,0x50,0x41,0x41,
357 0xaa,0x10,0xb0,0x00,0x00,0x06,0x08,0x49,
358 0x44,0x5f,0x5f,0x0a,0xaa,0x08,0x5f,0x48,
359 0x49,0x44,0x0d,0x41,0x43,0x50,0x49,0x30,
360 0x30,0x30,0x37,0x00,0x14,0x0f,0x5f,0x4d,
361 0x41,0x54,0x00,0xa4,0x43,0x50,0x4d,0x41,
362 0x49,0x44,0x5f,0x5f,0x14,0x0f,0x5f,0x53,
363 0x54,0x41,0x00,0xa4,0x43,0x50,0x53,0x54,
364 0x49,0x44,0x5f,0x5f,0x14,0x0f,0x5f,0x45,
365 0x4a,0x30,0x01,0x43,0x50,0x45,0x4a,0x49,
368 #define SD_OFFSET_CPUHEX 6
369 #define SD_OFFSET_CPUID1 8
370 #define SD_OFFSET_CPUID2 20
372 #define SSDT_SIGNATURE 0x54445353 // SSDT
376 int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
377 // length = ScopeOp + procs + NTYF method + CPON package
378 int length = ((1+3+4)
379 + (acpi_cpus * sizeof(ssdt_proc))
380 + (1+2+5+(12*acpi_cpus))
381 + (6+2+1+(1*acpi_cpus)));
382 u8 *ssdt = malloc_high(sizeof(struct acpi_table_header) + length);
387 u8 *ssdt_ptr = ssdt + sizeof(struct acpi_table_header);
389 // build Scope(_SB_) header
390 *(ssdt_ptr++) = 0x10; // ScopeOp
391 ssdt_ptr = encodeLen(ssdt_ptr, length-1, 3);
397 // build Processor object for each processor
399 for (i=0; i<acpi_cpus; i++) {
400 memcpy(ssdt_ptr, ssdt_proc, sizeof(ssdt_proc));
401 ssdt_ptr[SD_OFFSET_CPUHEX] = getHex(i >> 4);
402 ssdt_ptr[SD_OFFSET_CPUHEX+1] = getHex(i);
403 ssdt_ptr[SD_OFFSET_CPUID1] = i;
404 ssdt_ptr[SD_OFFSET_CPUID2] = i;
405 ssdt_ptr += sizeof(ssdt_proc);
408 // build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}"
409 *(ssdt_ptr++) = 0x14; // MethodOp
410 ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*acpi_cpus), 2);
415 *(ssdt_ptr++) = 0x02;
416 for (i=0; i<acpi_cpus; i++) {
417 *(ssdt_ptr++) = 0xA0; // IfOp
418 ssdt_ptr = encodeLen(ssdt_ptr, 11, 1);
419 *(ssdt_ptr++) = 0x93; // LEqualOp
420 *(ssdt_ptr++) = 0x68; // Arg0Op
421 *(ssdt_ptr++) = 0x0A; // BytePrefix
423 *(ssdt_ptr++) = 0x86; // NotifyOp
426 *(ssdt_ptr++) = getHex(i >> 4);
427 *(ssdt_ptr++) = getHex(i);
428 *(ssdt_ptr++) = 0x69; // Arg1Op
431 // build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
432 *(ssdt_ptr++) = 0x08; // NameOp
437 *(ssdt_ptr++) = 0x12; // PackageOp
438 ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*acpi_cpus), 2);
439 *(ssdt_ptr++) = acpi_cpus;
440 for (i=0; i<acpi_cpus; i++)
441 *(ssdt_ptr++) = (i < CountCPUs) ? 0x01 : 0x00;
443 build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
445 //hexdump(ssdt, ssdt_ptr - ssdt);
450 #define HPET_SIGNATURE 0x54455048 //HPET
454 struct acpi_20_hpet *hpet = malloc_high(sizeof(*hpet));
460 memset(hpet, 0, sizeof(*hpet));
461 /* Note timer_block_id value must be kept in sync with value advertised by
464 hpet->timer_block_id = cpu_to_le32(0x8086a201);
465 hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
466 build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
472 acpi_build_srat_memory(struct srat_memory_affinity *numamem,
473 u64 base, u64 len, int node, int enabled)
475 numamem->type = SRAT_MEMORY;
476 numamem->length = sizeof(*numamem);
477 memset (numamem->proximity, 0 ,4);
478 numamem->proximity[0] = node;
479 numamem->flags = cpu_to_le32(!!enabled);
480 numamem->base_addr_low = base & 0xFFFFFFFF;
481 numamem->base_addr_high = base >> 32;
482 numamem->length_low = len & 0xFFFFFFFF;
483 numamem->length_high = len >> 32;
486 #define SRAT_SIGNATURE 0x54415253 //HPET
490 int nb_numa_nodes = qemu_cfg_get_numa_nodes();
492 if (nb_numa_nodes == 0)
495 u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes));
501 qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes);
503 struct system_resource_affinity_table *srat;
504 int srat_size = sizeof(*srat) +
505 sizeof(struct srat_processor_affinity) * MaxCountCPUs +
506 sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
508 srat = malloc_high(srat_size);
515 memset(srat, 0, srat_size);
517 struct srat_processor_affinity *core = (void*)(srat + 1);
521 for (i = 0; i < MaxCountCPUs; ++i) {
522 core->type = SRAT_PROCESSOR;
523 core->length = sizeof(*core);
524 core->local_apic_id = i;
525 curnode = *numadata++;
526 core->proximity_lo = curnode;
527 memset(core->proximity_hi, 0, 3);
528 core->local_sapic_eid = 0;
530 core->flags = cpu_to_le32(1);
537 /* the memory map is a bit tricky, it contains at least one hole
538 * from 640k-1M and possibly another one from 3.5G-4G.
540 struct srat_memory_affinity *numamem = (void*)core;
542 u64 mem_len, mem_base, next_base = 0;
544 acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
545 next_base = 1024 * 1024;
548 for (i = 1; i < nb_numa_nodes + 1; ++i) {
549 mem_base = next_base;
550 mem_len = *numadata++;
552 mem_len -= 1024 * 1024;
553 next_base = mem_base + mem_len;
555 /* Cut out the PCI hole */
556 if (mem_base <= RamSize && next_base > RamSize) {
557 mem_len -= next_base - RamSize;
559 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
563 mem_base = 1ULL << 32;
564 mem_len = next_base - RamSize;
565 next_base += (1ULL << 32) - RamSize;
567 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
571 for (; slots < nb_numa_nodes + 2; slots++) {
572 acpi_build_srat_memory(numamem, 0, 0, 0, 0);
576 build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
582 static const struct pci_device_id acpi_find_tbl[] = {
583 /* PIIX4 Power Management device. */
584 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
589 struct rsdp_descriptor *RsdpAddr;
591 #define MAX_ACPI_TABLES 20
598 dprintf(3, "init ACPI tables\n");
600 // This code is hardcoded for PIIX4 Power Management device.
601 int bdf = pci_find_init_device(acpi_find_tbl, NULL);
606 // Create initial rsdt table
607 struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
613 u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
615 #define ACPI_INIT_TABLE(X) \
617 tables[tbl_idx] = (u32)(X); \
618 if (tables[tbl_idx]) \
623 ACPI_INIT_TABLE(build_fadt(bdf));
624 ACPI_INIT_TABLE(build_ssdt());
625 ACPI_INIT_TABLE(build_madt());
626 ACPI_INIT_TABLE(build_hpet());
627 ACPI_INIT_TABLE(build_srat());
629 u16 i, external_tables = qemu_cfg_acpi_additional_tables();
631 for(i = 0; i < external_tables; i++) {
632 u16 len = qemu_cfg_next_acpi_table_len();
633 void *addr = malloc_high(len);
638 ACPI_INIT_TABLE(qemu_cfg_next_acpi_table_load(addr, len));
639 if (tbl_idx == MAX_ACPI_TABLES) {
645 struct rsdt_descriptor_rev1 *rsdt;
646 size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
647 rsdt = malloc_high(rsdt_len);
653 memset(rsdt, 0, rsdt_len);
654 memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
656 build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
658 // Build rsdp pointer table
659 memset(rsdp, 0, sizeof(*rsdp));
660 rsdp->signature = RSDP_SIGNATURE;
661 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
662 rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
663 rsdp->checksum -= checksum(rsdp, 20);
665 dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
669 find_resume_vector(void)
671 dprintf(4, "rsdp=%p\n", RsdpAddr);
672 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
674 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
675 dprintf(4, "rsdt=%p\n", rsdt);
676 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
678 void *end = (void*)rsdt + rsdt->length;
680 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
681 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
682 if (!fadt || fadt->signature != FACP_SIGNATURE)
684 dprintf(4, "fadt=%p\n", fadt);
685 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
686 dprintf(4, "facs=%p\n", facs);
687 if (! facs || facs->signature != FACS_SIGNATURE)
690 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
691 return facs->firmware_waking_vector;