mips-dis.c

   1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003
   4    Free Software Foundation, Inc.
   5    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "dis-asm.h"
  23
  24 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
  25    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
  26    Free Software Foundation, Inc.
  27    Contributed by Ralph Campbell and OSF
  28    Commented and modified by Ian Lance Taylor, Cygnus Support
  29
  30 This file is part of GDB, GAS, and the GNU binutils.
  31
  32 GDB, GAS, and the GNU binutils are free software; you can redistribute
  33 them and/or modify them under the terms of the GNU General Public
  34 License as published by the Free Software Foundation; either version
  35 1, or (at your option) any later version.
  36
  37 GDB, GAS, and the GNU binutils are distributed in the hope that they
  38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  40 the GNU General Public License for more details.
  41
  42 You should have received a copy of the GNU General Public License
  43 along with this file; see the file COPYING.  If not,
  44 see <http://www.gnu.org/licenses/>.  */
  45
  46 /* These are bit masks and shift counts to use to access the various
  47    fields of an instruction.  To retrieve the X field of an
  48    instruction, use the expression
  49         (i >> OP_SH_X) & OP_MASK_X
  50    To set the same field (to j), use
  51         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  52
  53    Make sure you use fields that are appropriate for the instruction,
  54    of course.
  55
  56    The 'i' format uses OP, RS, RT and IMMEDIATE.
  57
  58    The 'j' format uses OP and TARGET.
  59
  60    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  61
  62    The 'b' format uses OP, RS, RT and DELTA.
  63
  64    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  65
  66    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  67
  68    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  69    breakpoint instruction are not defined; Kane says the breakpoint
  70    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  71    only use ten bits).  An optional two-operand form of break/sdbbp
  72    allows the lower ten bits to be set too, and MIPS32 and later
  73    architectures allow 20 bits to be set with a signal operand
  74    (using CODE20).
  75
  76    The syscall instruction uses CODE20.
  77
  78    The general coprocessor instructions use COPZ.  */
  79
  80 #define OP_MASK_OP              0x3f
  81 #define OP_SH_OP                26
  82 #define OP_MASK_RS              0x1f
  83 #define OP_SH_RS                21
  84 #define OP_MASK_FR              0x1f
  85 #define OP_SH_FR                21
  86 #define OP_MASK_FMT             0x1f
  87 #define OP_SH_FMT               21
  88 #define OP_MASK_BCC             0x7
  89 #define OP_SH_BCC               18
  90 #define OP_MASK_CODE            0x3ff
  91 #define OP_SH_CODE              16
  92 #define OP_MASK_CODE2           0x3ff
  93 #define OP_SH_CODE2             6
  94 #define OP_MASK_RT              0x1f
  95 #define OP_SH_RT                16
  96 #define OP_MASK_FT              0x1f
  97 #define OP_SH_FT                16
  98 #define OP_MASK_CACHE           0x1f
  99 #define OP_SH_CACHE             16
 100 #define OP_MASK_RD              0x1f
 101 #define OP_SH_RD                11
 102 #define OP_MASK_FS              0x1f
 103 #define OP_SH_FS                11
 104 #define OP_MASK_PREFX           0x1f
 105 #define OP_SH_PREFX             11
 106 #define OP_MASK_CCC             0x7
 107 #define OP_SH_CCC               8
 108 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
 109 #define OP_SH_CODE20            6
 110 #define OP_MASK_SHAMT           0x1f
 111 #define OP_SH_SHAMT             6
 112 #define OP_MASK_FD              0x1f
 113 #define OP_SH_FD                6
 114 #define OP_MASK_TARGET          0x3ffffff
 115 #define OP_SH_TARGET            0
 116 #define OP_MASK_COPZ            0x1ffffff
 117 #define OP_SH_COPZ              0
 118 #define OP_MASK_IMMEDIATE       0xffff
 119 #define OP_SH_IMMEDIATE         0
 120 #define OP_MASK_DELTA           0xffff
 121 #define OP_SH_DELTA             0
 122 #define OP_MASK_FUNCT           0x3f
 123 #define OP_SH_FUNCT             0
 124 #define OP_MASK_SPEC            0x3f
 125 #define OP_SH_SPEC              0
 126 #define OP_SH_LOCC              8       /* FP condition code.  */
 127 #define OP_SH_HICC              18      /* FP condition code.  */
 128 #define OP_MASK_CC              0x7
 129 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 130 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 131 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 132 #define OP_MASK_COP1SPEC        0xf
 133 #define OP_MASK_COP1SCLR        0x4
 134 #define OP_MASK_COP1CMP         0x3
 135 #define OP_SH_COP1CMP           4
 136 #define OP_SH_FORMAT            21      /* FP short format field.  */
 137 #define OP_MASK_FORMAT          0x7
 138 #define OP_SH_TRUE              16
 139 #define OP_MASK_TRUE            0x1
 140 #define OP_SH_GE                17
 141 #define OP_MASK_GE              0x01
 142 #define OP_SH_UNSIGNED          16
 143 #define OP_MASK_UNSIGNED        0x1
 144 #define OP_SH_HINT              16
 145 #define OP_MASK_HINT            0x1f
 146 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 147 #define OP_MASK_MMI             0x3f
 148 #define OP_SH_MMISUB            6
 149 #define OP_MASK_MMISUB          0x1f
 150 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 151 #define OP_SH_PERFREG           1
 152 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 153 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 154 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 155 #define OP_MASK_CODE19          0x7ffff
 156 #define OP_SH_ALN               21
 157 #define OP_MASK_ALN             0x7
 158 #define OP_SH_VSEL              21
 159 #define OP_MASK_VSEL            0x1f
 160 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 161                                            but 0x8-0xf don't select bytes.  */
 162 #define OP_SH_VECBYTE           22
 163 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 164 #define OP_SH_VECALIGN          21
 165 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 166 #define OP_SH_INSMSB            11
 167 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 168 #define OP_SH_EXTMSBD           11
 169
 170 #define OP_OP_COP0              0x10
 171 #define OP_OP_COP1              0x11
 172 #define OP_OP_COP2              0x12
 173 #define OP_OP_COP3              0x13
 174 #define OP_OP_LWC1              0x31
 175 #define OP_OP_LWC2              0x32
 176 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 177 #define OP_OP_LDC1              0x35
 178 #define OP_OP_LDC2              0x36
 179 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 180 #define OP_OP_SWC1              0x39
 181 #define OP_OP_SWC2              0x3a
 182 #define OP_OP_SWC3              0x3b
 183 #define OP_OP_SDC1              0x3d
 184 #define OP_OP_SDC2              0x3e
 185 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 186
 187 /* MIPS DSP ASE */
 188 #define OP_SH_DSPACC            11
 189 #define OP_MASK_DSPACC          0x3
 190 #define OP_SH_DSPACC_S          21
 191 #define OP_MASK_DSPACC_S        0x3
 192 #define OP_SH_DSPSFT            20
 193 #define OP_MASK_DSPSFT          0x3f
 194 #define OP_SH_DSPSFT_7          19
 195 #define OP_MASK_DSPSFT_7        0x7f
 196 #define OP_SH_SA3               21
 197 #define OP_MASK_SA3             0x7
 198 #define OP_SH_SA4               21
 199 #define OP_MASK_SA4             0xf
 200 #define OP_SH_IMM8              16
 201 #define OP_MASK_IMM8            0xff
 202 #define OP_SH_IMM10             16
 203 #define OP_MASK_IMM10           0x3ff
 204 #define OP_SH_WRDSP             11
 205 #define OP_MASK_WRDSP           0x3f
 206 #define OP_SH_RDDSP             16
 207 #define OP_MASK_RDDSP           0x3f
 208 #define OP_SH_BP                11
 209 #define OP_MASK_BP              0x3
 210
 211 /* MIPS MT ASE */
 212 #define OP_SH_MT_U              5
 213 #define OP_MASK_MT_U            0x1
 214 #define OP_SH_MT_H              4
 215 #define OP_MASK_MT_H            0x1
 216 #define OP_SH_MTACC_T           18
 217 #define OP_MASK_MTACC_T         0x3
 218 #define OP_SH_MTACC_D           13
 219 #define OP_MASK_MTACC_D         0x3
 220
 221 #define OP_OP_COP0              0x10
 222 #define OP_OP_COP1              0x11
 223 #define OP_OP_COP2              0x12
 224 #define OP_OP_COP3              0x13
 225 #define OP_OP_LWC1              0x31
 226 #define OP_OP_LWC2              0x32
 227 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 228 #define OP_OP_LDC1              0x35
 229 #define OP_OP_LDC2              0x36
 230 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 231 #define OP_OP_SWC1              0x39
 232 #define OP_OP_SWC2              0x3a
 233 #define OP_OP_SWC3              0x3b
 234 #define OP_OP_SDC1              0x3d
 235 #define OP_OP_SDC2              0x3e
 236 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 237
 238 /* Values in the 'VSEL' field.  */
 239 #define MDMX_FMTSEL_IMM_QH      0x1d
 240 #define MDMX_FMTSEL_IMM_OB      0x1e
 241 #define MDMX_FMTSEL_VEC_QH      0x15
 242 #define MDMX_FMTSEL_VEC_OB      0x16
 243
 244 /* UDI */
 245 #define OP_SH_UDI1              6
 246 #define OP_MASK_UDI1            0x1f
 247 #define OP_SH_UDI2              6
 248 #define OP_MASK_UDI2            0x3ff
 249 #define OP_SH_UDI3              6
 250 #define OP_MASK_UDI3            0x7fff
 251 #define OP_SH_UDI4              6
 252 #define OP_MASK_UDI4            0xfffff
 253 /* This structure holds information for a particular instruction.  */
 254
 255 struct mips_opcode
 256 {
 257   /* The name of the instruction.  */
 258   const char *name;
 259   /* A string describing the arguments for this instruction.  */
 260   const char *args;
 261   /* The basic opcode for the instruction.  When assembling, this
 262      opcode is modified by the arguments to produce the actual opcode
 263      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 264   unsigned long match;
 265   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 266      relevant portions of the opcode when disassembling.  If the
 267      actual opcode anded with the match field equals the opcode field,
 268      then we have found the correct instruction.  If pinfo is
 269      INSN_MACRO, then this field is the macro identifier.  */
 270   unsigned long mask;
 271   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 272      of bits describing the instruction, notably any relevant hazard
 273      information.  */
 274   unsigned long pinfo;
 275   /* A collection of additional bits describing the instruction. */
 276   unsigned long pinfo2;
 277   /* A collection of bits describing the instruction sets of which this
 278      instruction or macro is a member. */
 279   unsigned long membership;
 280 };
 281
 282 /* These are the characters which may appear in the args field of an
 283    instruction.  They appear in the order in which the fields appear
 284    when the instruction is used.  Commas and parentheses in the args
 285    string are ignored when assembling, and written into the output
 286    when disassembling.
 287
 288    Each of these characters corresponds to a mask field defined above.
 289
 290    "<" 5 bit shift amount (OP_*_SHAMT)
 291    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 292    "a" 26 bit target address (OP_*_TARGET)
 293    "b" 5 bit base register (OP_*_RS)
 294    "c" 10 bit breakpoint code (OP_*_CODE)
 295    "d" 5 bit destination register specifier (OP_*_RD)
 296    "h" 5 bit prefx hint (OP_*_PREFX)
 297    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 298    "j" 16 bit signed immediate (OP_*_DELTA)
 299    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 300        Also used for immediate operands in vr5400 vector insns.
 301    "o" 16 bit signed offset (OP_*_DELTA)
 302    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 303    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 304    "r" 5 bit same register used as both source and target (OP_*_RS)
 305    "s" 5 bit source register specifier (OP_*_RS)
 306    "t" 5 bit target register (OP_*_RT)
 307    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 308    "v" 5 bit same register used as both source and destination (OP_*_RS)
 309    "w" 5 bit same register used as both target and destination (OP_*_RT)
 310    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 311        (used by clo and clz)
 312    "C" 25 bit coprocessor function code (OP_*_COPZ)
 313    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 314    "J" 19 bit wait function code (OP_*_CODE19)
 315    "x" accept and ignore register name
 316    "z" must be zero register
 317    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 318    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 319         LSB (OP_*_SHAMT).
 320         Enforces: 0 <= pos < 32.
 321    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 322         Requires that "+A" or "+E" occur first to set position.
 323         Enforces: 0 < (pos+size) <= 32.
 324    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 325         Requires that "+A" or "+E" occur first to set position.
 326         Enforces: 0 < (pos+size) <= 32.
 327         (Also used by "dext" w/ different limits, but limits for
 328         that are checked by the M_DEXT macro.)
 329    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 330         Enforces: 32 <= pos < 64.
 331    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 332         Requires that "+A" or "+E" occur first to set position.
 333         Enforces: 32 < (pos+size) <= 64.
 334    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 335         Requires that "+A" or "+E" occur first to set position.
 336         Enforces: 32 < (pos+size) <= 64.
 337    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 338         Requires that "+A" or "+E" occur first to set position.
 339         Enforces: 32 < (pos+size) <= 64.
 340
 341    Floating point instructions:
 342    "D" 5 bit destination register (OP_*_FD)
 343    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 344    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 345    "S" 5 bit fs source 1 register (OP_*_FS)
 346    "T" 5 bit ft source 2 register (OP_*_FT)
 347    "R" 5 bit fr source 3 register (OP_*_FR)
 348    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 349    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 350
 351    Coprocessor instructions:
 352    "E" 5 bit target register (OP_*_RT)
 353    "G" 5 bit destination register (OP_*_RD)
 354    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 355    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 356    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 357    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 358    see also "k" above
 359    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 360         for pretty-printing in disassembly only.
 361
 362    Macro instructions:
 363    "A" General 32 bit expression
 364    "I" 32 bit immediate (value placed in imm_expr).
 365    "+I" 32 bit immediate (value placed in imm2_expr).
 366    "F" 64 bit floating point constant in .rdata
 367    "L" 64 bit floating point constant in .lit8
 368    "f" 32 bit floating point constant
 369    "l" 32 bit floating point constant in .lit4
 370
 371    MDMX instruction operands (note that while these use the FP register
 372    fields, they accept both $fN and $vN names for the registers):
 373    "O"  MDMX alignment offset (OP_*_ALN)
 374    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 375    "X"  MDMX destination register (OP_*_FD)
 376    "Y"  MDMX source register (OP_*_FS)
 377    "Z"  MDMX source register (OP_*_FT)
 378
 379    DSP ASE usage:
 380    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 381    "3" 3 bit unsigned immediate (OP_*_SA3)
 382    "4" 4 bit unsigned immediate (OP_*_SA4)
 383    "5" 8 bit unsigned immediate (OP_*_IMM8)
 384    "6" 5 bit unsigned immediate (OP_*_RS)
 385    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 386    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 387    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 388    "0" 6 bit signed immediate (OP_*_DSPSFT)
 389    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 390    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 391    "@" 10 bit signed immediate (OP_*_IMM10)
 392
 393    MT ASE usage:
 394    "!" 1 bit usermode flag (OP_*_MT_U)
 395    "$" 1 bit load high flag (OP_*_MT_H)
 396    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 397    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 398    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 399    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 400    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 401
 402    UDI immediates:
 403    "+1" UDI immediate bits 6-10
 404    "+2" UDI immediate bits 6-15
 405    "+3" UDI immediate bits 6-20
 406    "+4" UDI immediate bits 6-25
 407
 408    Other:
 409    "()" parens surrounding optional value
 410    ","  separates operands
 411    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 412    "+"  Start of extension sequence.
 413
 414    Characters used so far, for quick reference when adding more:
 415    "234567890"
 416    "%[]<>(),+:'@!$*&"
 417    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 418    "abcdefghijklopqrstuvwxz"
 419
 420    Extension character sequences used so far ("+" followed by the
 421    following), for quick reference when adding more:
 422    "1234"
 423    "ABCDEFGHIT"
 424    "t"
 425 */
 426
 427 /* These are the bits which may be set in the pinfo field of an
 428    instructions, if it is not equal to INSN_MACRO.  */
 429
 430 /* Modifies the general purpose register in OP_*_RD.  */
 431 #define INSN_WRITE_GPR_D            0x00000001
 432 /* Modifies the general purpose register in OP_*_RT.  */
 433 #define INSN_WRITE_GPR_T            0x00000002
 434 /* Modifies general purpose register 31.  */
 435 #define INSN_WRITE_GPR_31           0x00000004
 436 /* Modifies the floating point register in OP_*_FD.  */
 437 #define INSN_WRITE_FPR_D            0x00000008
 438 /* Modifies the floating point register in OP_*_FS.  */
 439 #define INSN_WRITE_FPR_S            0x00000010
 440 /* Modifies the floating point register in OP_*_FT.  */
 441 #define INSN_WRITE_FPR_T            0x00000020
 442 /* Reads the general purpose register in OP_*_RS.  */
 443 #define INSN_READ_GPR_S             0x00000040
 444 /* Reads the general purpose register in OP_*_RT.  */
 445 #define INSN_READ_GPR_T             0x00000080
 446 /* Reads the floating point register in OP_*_FS.  */
 447 #define INSN_READ_FPR_S             0x00000100
 448 /* Reads the floating point register in OP_*_FT.  */
 449 #define INSN_READ_FPR_T             0x00000200
 450 /* Reads the floating point register in OP_*_FR.  */
 451 #define INSN_READ_FPR_R             0x00000400
 452 /* Modifies coprocessor condition code.  */
 453 #define INSN_WRITE_COND_CODE        0x00000800
 454 /* Reads coprocessor condition code.  */
 455 #define INSN_READ_COND_CODE         0x00001000
 456 /* TLB operation.  */
 457 #define INSN_TLB                    0x00002000
 458 /* Reads coprocessor register other than floating point register.  */
 459 #define INSN_COP                    0x00004000
 460 /* Instruction loads value from memory, requiring delay.  */
 461 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 462 /* Instruction loads value from coprocessor, requiring delay.  */
 463 #define INSN_LOAD_COPROC_DELAY      0x00010000
 464 /* Instruction has unconditional branch delay slot.  */
 465 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 466 /* Instruction has conditional branch delay slot.  */
 467 #define INSN_COND_BRANCH_DELAY      0x00040000
 468 /* Conditional branch likely: if branch not taken, insn nullified.  */
 469 #define INSN_COND_BRANCH_LIKELY     0x00080000
 470 /* Moves to coprocessor register, requiring delay.  */
 471 #define INSN_COPROC_MOVE_DELAY      0x00100000
 472 /* Loads coprocessor register from memory, requiring delay.  */
 473 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 474 /* Reads the HI register.  */
 475 #define INSN_READ_HI                0x00400000
 476 /* Reads the LO register.  */
 477 #define INSN_READ_LO                0x00800000
 478 /* Modifies the HI register.  */
 479 #define INSN_WRITE_HI               0x01000000
 480 /* Modifies the LO register.  */
 481 #define INSN_WRITE_LO               0x02000000
 482 /* Takes a trap (easier to keep out of delay slot).  */
 483 #define INSN_TRAP                   0x04000000
 484 /* Instruction stores value into memory.  */
 485 #define INSN_STORE_MEMORY           0x08000000
 486 /* Instruction uses single precision floating point.  */
 487 #define FP_S                        0x10000000
 488 /* Instruction uses double precision floating point.  */
 489 #define FP_D                        0x20000000
 490 /* Instruction is part of the tx39's integer multiply family.    */
 491 #define INSN_MULT                   0x40000000
 492 /* Instruction synchronize shared memory.  */
 493 #define INSN_SYNC                   0x80000000
 494
 495 /* These are the bits which may be set in the pinfo2 field of an
 496    instruction. */
 497
 498 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 499 #define INSN2_ALIAS                 0x00000001
 500 /* Instruction reads MDMX accumulator. */
 501 #define INSN2_READ_MDMX_ACC         0x00000002
 502 /* Instruction writes MDMX accumulator. */
 503 #define INSN2_WRITE_MDMX_ACC        0x00000004
 504
 505 /* Instruction is actually a macro.  It should be ignored by the
 506    disassembler, and requires special treatment by the assembler.  */
 507 #define INSN_MACRO                  0xffffffff
 508
 509 /* Masks used to mark instructions to indicate which MIPS ISA level
 510    they were introduced in.  ISAs, as defined below, are logical
 511    ORs of these bits, indicating that they support the instructions
 512    defined at the given level.  */
 513
 514 #define INSN_ISA_MASK             0x00000fff
 515 #define INSN_ISA1                 0x00000001
 516 #define INSN_ISA2                 0x00000002
 517 #define INSN_ISA3                 0x00000004
 518 #define INSN_ISA4                 0x00000008
 519 #define INSN_ISA5                 0x00000010
 520 #define INSN_ISA32                0x00000020
 521 #define INSN_ISA64                0x00000040
 522 #define INSN_ISA32R2              0x00000080
 523 #define INSN_ISA64R2              0x00000100
 524
 525 /* Masks used for MIPS-defined ASEs.  */
 526 #define INSN_ASE_MASK             0x0000f000
 527
 528 /* DSP ASE */
 529 #define INSN_DSP                  0x00001000
 530 #define INSN_DSP64                0x00002000
 531 /* MIPS 16 ASE */
 532 #define INSN_MIPS16               0x00004000
 533 /* MIPS-3D ASE */
 534 #define INSN_MIPS3D               0x00008000
 535
 536 /* Chip specific instructions.  These are bitmasks.  */
 537
 538 /* MIPS R4650 instruction.  */
 539 #define INSN_4650                 0x00010000
 540 /* LSI R4010 instruction.  */
 541 #define INSN_4010                 0x00020000
 542 /* NEC VR4100 instruction.  */
 543 #define INSN_4100                 0x00040000
 544 /* Toshiba R3900 instruction.  */
 545 #define INSN_3900                 0x00080000
 546 /* MIPS R10000 instruction.  */
 547 #define INSN_10000                0x00100000
 548 /* Broadcom SB-1 instruction.  */
 549 #define INSN_SB1                  0x00200000
 550 /* NEC VR4111/VR4181 instruction.  */
 551 #define INSN_4111                 0x00400000
 552 /* NEC VR4120 instruction.  */
 553 #define INSN_4120                 0x00800000
 554 /* NEC VR5400 instruction.  */
 555 #define INSN_5400                 0x01000000
 556 /* NEC VR5500 instruction.  */
 557 #define INSN_5500                 0x02000000
 558
 559 /* MDMX ASE */
 560 #define INSN_MDMX                 0x04000000
 561 /* MT ASE */
 562 #define INSN_MT                   0x08000000
 563 /* SmartMIPS ASE  */
 564 #define INSN_SMARTMIPS            0x10000000
 565 /* DSP R2 ASE  */
 566 #define INSN_DSPR2                0x20000000
 567
 568 /* ST Microelectronics Loongson 2E.  */
 569 #define INSN_LOONGSON_2E          0x40000000
 570 /* ST Microelectronics Loongson 2F.  */
 571 #define INSN_LOONGSON_2F          0x80000000
 572
 573 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 574
 575 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 576 #define       ISA_MIPS1       (INSN_ISA1)
 577 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 578 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 579 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 580 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 581
 582 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 583 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 584
 585 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 586 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 587
 588
 589 /* CPU defines, use instead of hardcoding processor number. Keep this
 590    in sync with bfd/archures.c in order for machine selection to work.  */
 591 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 592 #define CPU_R3000       3000
 593 #define CPU_R3900       3900
 594 #define CPU_R4000       4000
 595 #define CPU_R4010       4010
 596 #define CPU_VR4100      4100
 597 #define CPU_R4111       4111
 598 #define CPU_VR4120      4120
 599 #define CPU_R4300       4300
 600 #define CPU_R4400       4400
 601 #define CPU_R4600       4600
 602 #define CPU_R4650       4650
 603 #define CPU_R5000       5000
 604 #define CPU_VR5400      5400
 605 #define CPU_VR5500      5500
 606 #define CPU_R6000       6000
 607 #define CPU_RM7000      7000
 608 #define CPU_R8000       8000
 609 #define CPU_R10000      10000
 610 #define CPU_R12000      12000
 611 #define CPU_MIPS16      16
 612 #define CPU_MIPS32      32
 613 #define CPU_MIPS32R2    33
 614 #define CPU_MIPS5       5
 615 #define CPU_MIPS64      64
 616 #define CPU_MIPS64R2    65
 617 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 618
 619 /* Test for membership in an ISA including chip specific ISAs.  INSN
 620    is pointer to an element of the opcode table; ISA is the specified
 621    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 622    test, or zero if no CPU specific ISA test is desired.  */
 623
 624 #if 0
 625 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 626     (((insn)->membership & isa) != 0                                    \
 627      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 628      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 629      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 630      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 631      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 632      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 633      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 634          && ((insn)->membership & INSN_10000) != 0)                     \
 635      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 636      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 637      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 638      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 639      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 640      || 0)      /* Please keep this term for easier source merging.  */
 641 #else
 642 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
 643     (1 != 0)
 644 #endif
 645
 646 /* This is a list of macro expanded instructions.
 647
 648    _I appended means immediate
 649    _A appended means address
 650    _AB appended means address with base register
 651    _D appended means 64 bit floating point constant
 652    _S appended means 32 bit floating point constant.  */
 653
 654 enum
 655 {
 656   M_ABS,
 657   M_ADD_I,
 658   M_ADDU_I,
 659   M_AND_I,
 660   M_BALIGN,
 661   M_BEQ,
 662   M_BEQ_I,
 663   M_BEQL_I,
 664   M_BGE,
 665   M_BGEL,
 666   M_BGE_I,
 667   M_BGEL_I,
 668   M_BGEU,
 669   M_BGEUL,
 670   M_BGEU_I,
 671   M_BGEUL_I,
 672   M_BGT,
 673   M_BGTL,
 674   M_BGT_I,
 675   M_BGTL_I,
 676   M_BGTU,
 677   M_BGTUL,
 678   M_BGTU_I,
 679   M_BGTUL_I,
 680   M_BLE,
 681   M_BLEL,
 682   M_BLE_I,
 683   M_BLEL_I,
 684   M_BLEU,
 685   M_BLEUL,
 686   M_BLEU_I,
 687   M_BLEUL_I,
 688   M_BLT,
 689   M_BLTL,
 690   M_BLT_I,
 691   M_BLTL_I,
 692   M_BLTU,
 693   M_BLTUL,
 694   M_BLTU_I,
 695   M_BLTUL_I,
 696   M_BNE,
 697   M_BNE_I,
 698   M_BNEL_I,
 699   M_CACHE_AB,
 700   M_DABS,
 701   M_DADD_I,
 702   M_DADDU_I,
 703   M_DDIV_3,
 704   M_DDIV_3I,
 705   M_DDIVU_3,
 706   M_DDIVU_3I,
 707   M_DEXT,
 708   M_DINS,
 709   M_DIV_3,
 710   M_DIV_3I,
 711   M_DIVU_3,
 712   M_DIVU_3I,
 713   M_DLA_AB,
 714   M_DLCA_AB,
 715   M_DLI,
 716   M_DMUL,
 717   M_DMUL_I,
 718   M_DMULO,
 719   M_DMULO_I,
 720   M_DMULOU,
 721   M_DMULOU_I,
 722   M_DREM_3,
 723   M_DREM_3I,
 724   M_DREMU_3,
 725   M_DREMU_3I,
 726   M_DSUB_I,
 727   M_DSUBU_I,
 728   M_DSUBU_I_2,
 729   M_J_A,
 730   M_JAL_1,
 731   M_JAL_2,
 732   M_JAL_A,
 733   M_L_DOB,
 734   M_L_DAB,
 735   M_LA_AB,
 736   M_LB_A,
 737   M_LB_AB,
 738   M_LBU_A,
 739   M_LBU_AB,
 740   M_LCA_AB,
 741   M_LD_A,
 742   M_LD_OB,
 743   M_LD_AB,
 744   M_LDC1_AB,
 745   M_LDC2_AB,
 746   M_LDC3_AB,
 747   M_LDL_AB,
 748   M_LDR_AB,
 749   M_LH_A,
 750   M_LH_AB,
 751   M_LHU_A,
 752   M_LHU_AB,
 753   M_LI,
 754   M_LI_D,
 755   M_LI_DD,
 756   M_LI_S,
 757   M_LI_SS,
 758   M_LL_AB,
 759   M_LLD_AB,
 760   M_LS_A,
 761   M_LW_A,
 762   M_LW_AB,
 763   M_LWC0_A,
 764   M_LWC0_AB,
 765   M_LWC1_A,
 766   M_LWC1_AB,
 767   M_LWC2_A,
 768   M_LWC2_AB,
 769   M_LWC3_A,
 770   M_LWC3_AB,
 771   M_LWL_A,
 772   M_LWL_AB,
 773   M_LWR_A,
 774   M_LWR_AB,
 775   M_LWU_AB,
 776   M_MOVE,
 777   M_MUL,
 778   M_MUL_I,
 779   M_MULO,
 780   M_MULO_I,
 781   M_MULOU,
 782   M_MULOU_I,
 783   M_NOR_I,
 784   M_OR_I,
 785   M_REM_3,
 786   M_REM_3I,
 787   M_REMU_3,
 788   M_REMU_3I,
 789   M_DROL,
 790   M_ROL,
 791   M_DROL_I,
 792   M_ROL_I,
 793   M_DROR,
 794   M_ROR,
 795   M_DROR_I,
 796   M_ROR_I,
 797   M_S_DA,
 798   M_S_DOB,
 799   M_S_DAB,
 800   M_S_S,
 801   M_SC_AB,
 802   M_SCD_AB,
 803   M_SD_A,
 804   M_SD_OB,
 805   M_SD_AB,
 806   M_SDC1_AB,
 807   M_SDC2_AB,
 808   M_SDC3_AB,
 809   M_SDL_AB,
 810   M_SDR_AB,
 811   M_SEQ,
 812   M_SEQ_I,
 813   M_SGE,
 814   M_SGE_I,
 815   M_SGEU,
 816   M_SGEU_I,
 817   M_SGT,
 818   M_SGT_I,
 819   M_SGTU,
 820   M_SGTU_I,
 821   M_SLE,
 822   M_SLE_I,
 823   M_SLEU,
 824   M_SLEU_I,
 825   M_SLT_I,
 826   M_SLTU_I,
 827   M_SNE,
 828   M_SNE_I,
 829   M_SB_A,
 830   M_SB_AB,
 831   M_SH_A,
 832   M_SH_AB,
 833   M_SW_A,
 834   M_SW_AB,
 835   M_SWC0_A,
 836   M_SWC0_AB,
 837   M_SWC1_A,
 838   M_SWC1_AB,
 839   M_SWC2_A,
 840   M_SWC2_AB,
 841   M_SWC3_A,
 842   M_SWC3_AB,
 843   M_SWL_A,
 844   M_SWL_AB,
 845   M_SWR_A,
 846   M_SWR_AB,
 847   M_SUB_I,
 848   M_SUBU_I,
 849   M_SUBU_I_2,
 850   M_TEQ_I,
 851   M_TGE_I,
 852   M_TGEU_I,
 853   M_TLT_I,
 854   M_TLTU_I,
 855   M_TNE_I,
 856   M_TRUNCWD,
 857   M_TRUNCWS,
 858   M_ULD,
 859   M_ULD_A,
 860   M_ULH,
 861   M_ULH_A,
 862   M_ULHU,
 863   M_ULHU_A,
 864   M_ULW,
 865   M_ULW_A,
 866   M_USH,
 867   M_USH_A,
 868   M_USW,
 869   M_USW_A,
 870   M_USD,
 871   M_USD_A,
 872   M_XOR_I,
 873   M_COP0,
 874   M_COP1,
 875   M_COP2,
 876   M_COP3,
 877   M_NUM_MACROS
 878 };
 879
 880
 881 /* The order of overloaded instructions matters.  Label arguments and
 882    register arguments look the same. Instructions that can have either
 883    for arguments must apear in the correct order in this table for the
 884    assembler to pick the right one. In other words, entries with
 885    immediate operands must apear after the same instruction with
 886    registers.
 887
 888    Many instructions are short hand for other instructions (i.e., The
 889    jal <register> instruction is short for jalr <register>).  */
 890
 891 extern const struct mips_opcode mips_builtin_opcodes[];
 892 extern const int bfd_mips_num_builtin_opcodes;
 893 extern struct mips_opcode *mips_opcodes;
 894 extern int bfd_mips_num_opcodes;
 895 #define NUMOPCODES bfd_mips_num_opcodes
 896
 897 \f
 898 /* The rest of this file adds definitions for the mips16 TinyRISC
 899    processor.  */
 900
 901 /* These are the bitmasks and shift counts used for the different
 902    fields in the instruction formats.  Other than OP, no masks are
 903    provided for the fixed portions of an instruction, since they are
 904    not needed.
 905
 906    The I format uses IMM11.
 907
 908    The RI format uses RX and IMM8.
 909
 910    The RR format uses RX, and RY.
 911
 912    The RRI format uses RX, RY, and IMM5.
 913
 914    The RRR format uses RX, RY, and RZ.
 915
 916    The RRI_A format uses RX, RY, and IMM4.
 917
 918    The SHIFT format uses RX, RY, and SHAMT.
 919
 920    The I8 format uses IMM8.
 921
 922    The I8_MOVR32 format uses RY and REGR32.
 923
 924    The IR_MOV32R format uses REG32R and MOV32Z.
 925
 926    The I64 format uses IMM8.
 927
 928    The RI64 format uses RY and IMM5.
 929    */
 930
 931 #define MIPS16OP_MASK_OP        0x1f
 932 #define MIPS16OP_SH_OP          11
 933 #define MIPS16OP_MASK_IMM11     0x7ff
 934 #define MIPS16OP_SH_IMM11       0
 935 #define MIPS16OP_MASK_RX        0x7
 936 #define MIPS16OP_SH_RX          8
 937 #define MIPS16OP_MASK_IMM8      0xff
 938 #define MIPS16OP_SH_IMM8        0
 939 #define MIPS16OP_MASK_RY        0x7
 940 #define MIPS16OP_SH_RY          5
 941 #define MIPS16OP_MASK_IMM5      0x1f
 942 #define MIPS16OP_SH_IMM5        0
 943 #define MIPS16OP_MASK_RZ        0x7
 944 #define MIPS16OP_SH_RZ          2
 945 #define MIPS16OP_MASK_IMM4      0xf
 946 #define MIPS16OP_SH_IMM4        0
 947 #define MIPS16OP_MASK_REGR32    0x1f
 948 #define MIPS16OP_SH_REGR32      0
 949 #define MIPS16OP_MASK_REG32R    0x1f
 950 #define MIPS16OP_SH_REG32R      3
 951 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 952 #define MIPS16OP_MASK_MOVE32Z   0x7
 953 #define MIPS16OP_SH_MOVE32Z     0
 954 #define MIPS16OP_MASK_IMM6      0x3f
 955 #define MIPS16OP_SH_IMM6        5
 956
 957 /* These are the characters which may appears in the args field of an
 958    instruction.  They appear in the order in which the fields appear
 959    when the instruction is used.  Commas and parentheses in the args
 960    string are ignored when assembling, and written into the output
 961    when disassembling.
 962
 963    "y" 3 bit register (MIPS16OP_*_RY)
 964    "x" 3 bit register (MIPS16OP_*_RX)
 965    "z" 3 bit register (MIPS16OP_*_RZ)
 966    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 967    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 968    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 969    "0" zero register ($0)
 970    "S" stack pointer ($sp or $29)
 971    "P" program counter
 972    "R" return address register ($ra or $31)
 973    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 974    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 975    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 976    "a" 26 bit jump address
 977    "e" 11 bit extension value
 978    "l" register list for entry instruction
 979    "L" register list for exit instruction
 980
 981    The remaining codes may be extended.  Except as otherwise noted,
 982    the full extended operand is a 16 bit signed value.
 983    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 984    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 985    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 986    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 987    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 988    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 989    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 990    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 991    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 992    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 993    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 994    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 995    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 996    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 997    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 998    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 999    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1000    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1001    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1002    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1003    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1004    */
1005
1006 /* Save/restore encoding for the args field when all 4 registers are
1007    either saved as arguments or saved/restored as statics.  */
1008 #define MIPS16_ALL_ARGS    0xe
1009 #define MIPS16_ALL_STATICS 0xb
1010
1011 /* For the mips16, we use the same opcode table format and a few of
1012    the same flags.  However, most of the flags are different.  */
1013
1014 /* Modifies the register in MIPS16OP_*_RX.  */
1015 #define MIPS16_INSN_WRITE_X                 0x00000001
1016 /* Modifies the register in MIPS16OP_*_RY.  */
1017 #define MIPS16_INSN_WRITE_Y                 0x00000002
1018 /* Modifies the register in MIPS16OP_*_RZ.  */
1019 #define MIPS16_INSN_WRITE_Z                 0x00000004
1020 /* Modifies the T ($24) register.  */
1021 #define MIPS16_INSN_WRITE_T                 0x00000008
1022 /* Modifies the SP ($29) register.  */
1023 #define MIPS16_INSN_WRITE_SP                0x00000010
1024 /* Modifies the RA ($31) register.  */
1025 #define MIPS16_INSN_WRITE_31                0x00000020
1026 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1027 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1028 /* Reads the register in MIPS16OP_*_RX.  */
1029 #define MIPS16_INSN_READ_X                  0x00000080
1030 /* Reads the register in MIPS16OP_*_RY.  */
1031 #define MIPS16_INSN_READ_Y                  0x00000100
1032 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1033 #define MIPS16_INSN_READ_Z                  0x00000200
1034 /* Reads the T ($24) register.  */
1035 #define MIPS16_INSN_READ_T                  0x00000400
1036 /* Reads the SP ($29) register.  */
1037 #define MIPS16_INSN_READ_SP                 0x00000800
1038 /* Reads the RA ($31) register.  */
1039 #define MIPS16_INSN_READ_31                 0x00001000
1040 /* Reads the program counter.  */
1041 #define MIPS16_INSN_READ_PC                 0x00002000
1042 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1043 #define MIPS16_INSN_READ_GPR_X              0x00004000
1044 /* Is a branch insn. */
1045 #define MIPS16_INSN_BRANCH                  0x00010000
1046
1047 /* The following flags have the same value for the mips16 opcode
1048    table:
1049    INSN_UNCOND_BRANCH_DELAY
1050    INSN_COND_BRANCH_DELAY
1051    INSN_COND_BRANCH_LIKELY (never used)
1052    INSN_READ_HI
1053    INSN_READ_LO
1054    INSN_WRITE_HI
1055    INSN_WRITE_LO
1056    INSN_TRAP
1057    INSN_ISA3
1058    */
1059
1060 extern const struct mips_opcode mips16_opcodes[];
1061 extern const int bfd_mips16_num_opcodes;
1062
1063 /* Short hand so the lines aren't too long.  */
1064
1065 #define LDD     INSN_LOAD_MEMORY_DELAY
1066 #define LCD     INSN_LOAD_COPROC_DELAY
1067 #define UBD     INSN_UNCOND_BRANCH_DELAY
1068 #define CBD     INSN_COND_BRANCH_DELAY
1069 #define COD     INSN_COPROC_MOVE_DELAY
1070 #define CLD     INSN_COPROC_MEMORY_DELAY
1071 #define CBL     INSN_COND_BRANCH_LIKELY
1072 #define TRAP    INSN_TRAP
1073 #define SM      INSN_STORE_MEMORY
1074
1075 #define WR_d    INSN_WRITE_GPR_D
1076 #define WR_t    INSN_WRITE_GPR_T
1077 #define WR_31   INSN_WRITE_GPR_31
1078 #define WR_D    INSN_WRITE_FPR_D
1079 #define WR_T    INSN_WRITE_FPR_T
1080 #define WR_S    INSN_WRITE_FPR_S
1081 #define RD_s    INSN_READ_GPR_S
1082 #define RD_b    INSN_READ_GPR_S
1083 #define RD_t    INSN_READ_GPR_T
1084 #define RD_S    INSN_READ_FPR_S
1085 #define RD_T    INSN_READ_FPR_T
1086 #define RD_R    INSN_READ_FPR_R
1087 #define WR_CC   INSN_WRITE_COND_CODE
1088 #define RD_CC   INSN_READ_COND_CODE
1089 #define RD_C0   INSN_COP
1090 #define RD_C1   INSN_COP
1091 #define RD_C2   INSN_COP
1092 #define RD_C3   INSN_COP
1093 #define WR_C0   INSN_COP
1094 #define WR_C1   INSN_COP
1095 #define WR_C2   INSN_COP
1096 #define WR_C3   INSN_COP
1097
1098 #define WR_HI   INSN_WRITE_HI
1099 #define RD_HI   INSN_READ_HI
1100 #define MOD_HI  WR_HI|RD_HI
1101
1102 #define WR_LO   INSN_WRITE_LO
1103 #define RD_LO   INSN_READ_LO
1104 #define MOD_LO  WR_LO|RD_LO
1105
1106 #define WR_HILO WR_HI|WR_LO
1107 #define RD_HILO RD_HI|RD_LO
1108 #define MOD_HILO WR_HILO|RD_HILO
1109
1110 #define IS_M    INSN_MULT
1111
1112 #define WR_MACC INSN2_WRITE_MDMX_ACC
1113 #define RD_MACC INSN2_READ_MDMX_ACC
1114
1115 #define I1      INSN_ISA1
1116 #define I2      INSN_ISA2
1117 #define I3      INSN_ISA3
1118 #define I4      INSN_ISA4
1119 #define I5      INSN_ISA5
1120 #define I32     INSN_ISA32
1121 #define I64     INSN_ISA64
1122 #define I33     INSN_ISA32R2
1123 #define I65     INSN_ISA64R2
1124
1125 /* MIPS64 MIPS-3D ASE support.  */
1126 #define I16     INSN_MIPS16
1127
1128 /* MIPS32 SmartMIPS ASE support.  */
1129 #define SMT     INSN_SMARTMIPS
1130
1131 /* MIPS64 MIPS-3D ASE support.  */
1132 #define M3D     INSN_MIPS3D
1133
1134 /* MIPS64 MDMX ASE support.  */
1135 #define MX      INSN_MDMX
1136
1137 #define IL2E    (INSN_LOONGSON_2E)
1138 #define IL2F    (INSN_LOONGSON_2F)
1139
1140 #define P3      INSN_4650
1141 #define L1      INSN_4010
1142 #define V1      (INSN_4100 | INSN_4111 | INSN_4120)
1143 #define T3      INSN_3900
1144 #define M1      INSN_10000
1145 #define SB1     INSN_SB1
1146 #define N411    INSN_4111
1147 #define N412    INSN_4120
1148 #define N5      (INSN_5400 | INSN_5500)
1149 #define N54     INSN_5400
1150 #define N55     INSN_5500
1151
1152 #define G1      (T3             \
1153                  )
1154
1155 #define G2      (T3             \
1156                  )
1157
1158 #define G3      (I4             \
1159                  )
1160
1161 /* MIPS DSP ASE support.
1162    NOTE:
1163    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1164    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1165    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1166    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1167    (RD_HILO) attributes, such that HILO dependencies are maintained
1168    conservatively.
1169
1170    2. For some mul. instructions that use integer registers as destinations
1171    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1172
1173    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1174    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1175    certain fields of the DSP control register.  For simplicity, we decide not
1176    to track dependencies of these fields.
1177    However, "bposge32" is a branch instruction that depends on the "pos"
1178    field.  In order to make sure that GAS does not reorder DSP instructions
1179    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1180    attribute to those instructions that write the "pos" field.  */
1181
1182 #define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */
1183 #define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
1184 #define MOD_a   WR_a|RD_a
1185 #define DSP_VOLA        INSN_TRAP
1186 #define D32     INSN_DSP
1187 #define D33     INSN_DSPR2
1188 #define D64     INSN_DSP64
1189
1190 /* MIPS MT ASE support.  */
1191 #define MT32    INSN_MT
1192
1193 /* The order of overloaded instructions matters.  Label arguments and
1194    register arguments look the same. Instructions that can have either
1195    for arguments must apear in the correct order in this table for the
1196    assembler to pick the right one. In other words, entries with
1197    immediate operands must apear after the same instruction with
1198    registers.
1199
1200    Because of the lookup algorithm used, entries with the same opcode
1201    name must be contiguous.
1202
1203    Many instructions are short hand for other instructions (i.e., The
1204    jal <register> instruction is short for jalr <register>).  */
1205
1206 const struct mips_opcode mips_builtin_opcodes[] =
1207 {
1208 /* These instructions appear first so that the disassembler will find
1209    them first.  The assemblers uses a hash table based on the
1210    instruction name anyhow.  */
1211 /* name,    args,       match,      mask,       pinfo,                  membership */
1212 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,              I4|I32|G3       },
1213 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
1214 {"nop",     "",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1      }, /* sll */
1215 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I32|N55 }, /* sll */
1216 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I33     }, /* sll */
1217 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */
1218 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
1219 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO,             0,              I1      },
1220 {"move",    "d,s",      0,    (int) M_MOVE,     INSN_MACRO,             0,              I1      },
1221 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */
1222 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */
1223 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */
1224 {"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */
1225 {"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */
1226 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/
1227
1228 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
1229 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1230 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1231 {"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1232 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1233 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
1234 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1235 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1236 {"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1237 {"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1238 {"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1239 {"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1240 {"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1241 {"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1242 {"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1243 {"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1244 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1245 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1246 {"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1247 {"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1248 {"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1249 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1250 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
1251 {"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1252 {"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
1253 {"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1254 {"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1255 {"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
1256 {"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
1257 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1258 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
1259 {"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1260 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1261 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1262 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1263 {"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1264 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1265 /* b is at the top of the table.  */
1266 /* bal is at the top of the table.  */
1267 /* bc0[tf]l? are at the bottom of the table.  */
1268 {"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1269 {"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1270 {"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1271 {"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1272 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
1273 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
1274 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
1275 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
1276 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
1277 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
1278 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
1279 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
1280 /* bc2* are at the bottom of the table.  */
1281 /* bc3* are at the bottom of the table.  */
1282 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1283 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1284 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
1285 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1      },
1286 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
1287 {"beql",    "s,I,p",    0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3   },
1288 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO,             0,              I1      },
1289 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO,             0,              I1      },
1290 {"bgel",    "s,t,p",    0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3   },
1291 {"bgel",    "s,I,p",    0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3   },
1292 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO,             0,              I1      },
1293 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO,             0,              I1      },
1294 {"bgeul",   "s,t,p",    0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3   },
1295 {"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3   },
1296 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1297 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1298 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
1299 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
1300 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO,             0,              I1      },
1301 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO,             0,              I1      },
1302 {"bgtl",    "s,t,p",    0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3   },
1303 {"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3   },
1304 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO,             0,              I1      },
1305 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO,             0,              I1      },
1306 {"bgtul",   "s,t,p",    0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3   },
1307 {"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3   },
1308 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1309 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1310 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO,             0,              I1      },
1311 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO,             0,              I1      },
1312 {"blel",    "s,t,p",    0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3   },
1313 {"blel",    "s,I,p",    0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3   },
1314 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO,             0,              I1      },
1315 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO,             0,              I1      },
1316 {"bleul",   "s,t,p",    0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3   },
1317 {"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3   },
1318 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1319 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1320 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO,             0,              I1      },
1321 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO,             0,              I1      },
1322 {"bltl",    "s,t,p",    0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3   },
1323 {"bltl",    "s,I,p",    0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3   },
1324 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO,             0,              I1      },
1325 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO,             0,              I1      },
1326 {"bltul",   "s,t,p",    0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3   },
1327 {"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3   },
1328 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1329 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1330 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
1331 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
1332 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1333 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1334 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
1335 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1      },
1336 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
1337 {"bnel",    "s,I,p",    0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3   },
1338 {"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,              I1      },
1339 {"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
1340 {"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
1341 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1342 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1343 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1344 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1345 {"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1346 {"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1347 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1348 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1349 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1350 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1351 {"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1352 {"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1353 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1354 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1355 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1356 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1357 {"c.eq.ob", "Y,Q",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1358 {"c.eq.ob", "S,T",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1359 {"c.eq.ob", "S,T[e]",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1360 {"c.eq.ob", "S,k",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1361 {"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1362 {"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1363 {"c.eq.qh", "Y,Q",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1364 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1365 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1366 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1367 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1368 {"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1369 {"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1370 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1371 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1372 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1373 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1374 {"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1375 {"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1376 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1377 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1378 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1379 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1380 {"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1381 {"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1382 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1383 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1384 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1385 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1386 {"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1387 {"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1388 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1389 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1390 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1391 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1392 {"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1393 {"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1394 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1395 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1396 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1397 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1398 {"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1399 {"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1400 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1401 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1402 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1403 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1404 {"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1405 {"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1406 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1407 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1408 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1409 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1410 {"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1411 {"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1412 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1413 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1414 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1415 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1416 {"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1417 {"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1418 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1419 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1420 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1421 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1422 {"c.lt.ob", "Y,Q",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1423 {"c.lt.ob", "S,T",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1424 {"c.lt.ob", "S,T[e]",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1425 {"c.lt.ob", "S,k",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1426 {"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1427 {"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1428 {"c.lt.qh", "Y,Q",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1429 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1430 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1431 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1432 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1433 {"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1434 {"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1435 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1436 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1437 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1438 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1439 {"c.le.ob", "Y,Q",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1440 {"c.le.ob", "S,T",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1441 {"c.le.ob", "S,T[e]",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1442 {"c.le.ob", "S,k",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1443 {"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1444 {"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1445 {"c.le.qh", "Y,Q",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1446 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1447 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1448 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1449 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1450 {"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1451 {"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1452 {"cabs.eq.d",  "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1453 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1454 {"cabs.eq.s",  "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1455 {"cabs.f.d",   "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1456 {"cabs.f.ps",  "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1457 {"cabs.f.s",   "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1458 {"cabs.le.d",  "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1459 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1460 {"cabs.le.s",  "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1461 {"cabs.lt.d",  "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1462 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1463 {"cabs.lt.s",  "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1464 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1465 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1466 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1467 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1468 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1469 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1470 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1471 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1472 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1473 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1474 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1475 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1476 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1477 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1478 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1479 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1480 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1481 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1482 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1483 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1484 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1485 {"cabs.sf.d",  "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1486 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1487 {"cabs.sf.s",  "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1488 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1489 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1490 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1491 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1492 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1493 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1494 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1495 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1496 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1497 {"cabs.un.d",  "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1498 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1499 {"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1500 /* CW4010 instructions which are aliases for the cache instruction.  */
1501 {"flushi",  "",         0xbc010000, 0xffffffff, 0,                      0,              L1      },
1502 {"flushd",  "",         0xbc020000, 0xffffffff, 0,                      0,              L1      },
1503 {"flushid", "",         0xbc030000, 0xffffffff, 0,                      0,              L1      },
1504 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,              L1      },
1505 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,              I3|I32|T3},
1506 {"cache",   "k,A(b)",   0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3|I32|T3},
1507 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1508 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1509 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
1510 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
1511 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
1512 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
1513 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
1514 /* cfc2 is at the bottom of the table.  */
1515 /* cfc3 is at the bottom of the table.  */
1516 {"cftc1",   "d,E",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
1517 {"cftc1",   "d,T",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
1518 {"cftc2",   "d,E",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1519 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
1520 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
1521 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
1522 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
1523 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
1524 /* ctc2 is at the bottom of the table.  */
1525 /* ctc3 is at the bottom of the table.  */
1526 {"cttc1",   "t,g",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
1527 {"cttc1",   "t,S",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
1528 {"cttc2",   "t,g",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
1529 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1530 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1531 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1532 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1533 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1534 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1535 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1536 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1537 {"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
1538 {"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
1539 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1540 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1541 {"cvt.ps.pw", "D,S",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
1542 {"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5|I33  },
1543 {"cvt.pw.ps", "D,S",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
1544 {"dabs",    "d,v",      0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
1545 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1546 {"dadd",    "t,r,I",    0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
1547 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
1548 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
1549 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1550 {"daddu",   "t,r,I",    0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3      },
1551 {"dbreak",  "",         0x7000003f, 0xffffffff, 0,                      0,              N5      },
1552 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
1553 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
1554 /* dctr and dctw are used on the r5000.  */
1555 {"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   0,              I3      },
1556 {"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   0,              I3      },
1557 {"deret",   "",         0x4200001f, 0xffffffff, 0,                      0,              I32|G2  },
1558 {"dext",    "t,r,I,+I", 0,    (int) M_DEXT,     INSN_MACRO,             0,              I65     },
1559 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1560 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1561 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1562 /* For ddiv, see the comments about div.  */
1563 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1564 {"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3      },
1565 {"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3      },
1566 /* For ddivu, see the comments about div.  */
1567 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1568 {"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
1569 {"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
1570 {"di",      "",         0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
1571 {"di",      "t",        0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
1572 {"dins",    "t,r,I,+I", 0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
1573 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1574 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1575 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1576 /* The MIPS assembler treats the div opcode with two operands as
1577    though the first operand appeared twice (the first operand is both
1578    a source and a destination).  To get the div machine instruction,
1579    you must use an explicit destination of $0.  */
1580 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1581 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1582 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1      },
1583 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1      },
1584 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1585 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1586 {"div.ps",  "D,V,T",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
1587 /* For divu, see the comments about div.  */
1588 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1589 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1590 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1      },
1591 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1      },
1592 {"dla",     "t,A(b)",   0,    (int) M_DLA_AB,   INSN_MACRO,             0,              I3      },
1593 {"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,  INSN_MACRO,             0,              I3      },
1594 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   0,              I3      }, /* addiu */
1595 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   0,              I3      }, /* ori */
1596 {"dli",     "t,I",      0,    (int) M_DLI,      INSN_MACRO,             0,              I3      },
1597 {"dmacc",   "d,s,t",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1598 {"dmacchi", "d,s,t",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1599 {"dmacchis", "d,s,t",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1600 {"dmacchiu", "d,s,t",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1601 {"dmacchius", "d,s,t",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1602 {"dmaccs",  "d,s,t",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1603 {"dmaccu",  "d,s,t",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1604 {"dmaccus", "d,s,t",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1605 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,              N411    },
1606 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
1607 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
1608 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
1609 {"dmt",     "",         0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
1610 {"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1611 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
1612 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
1613 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
1614 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
1615 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
1616 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
1617 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
1618 /* dmfc2 is at the bottom of the table.  */
1619 /* dmtc2 is at the bottom of the table.  */
1620 /* dmfc3 is at the bottom of the table.  */
1621 /* dmtc3 is at the bottom of the table.  */
1622 {"dmul",    "d,v,t",    0,    (int) M_DMUL,     INSN_MACRO,             0,              I3      },
1623 {"dmul",    "d,v,I",    0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3      },
1624 {"dmulo",   "d,v,t",    0,    (int) M_DMULO,    INSN_MACRO,             0,              I3      },
1625 {"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3      },
1626 {"dmulou",  "d,v,t",    0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3      },
1627 {"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3      },
1628 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1629 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1630 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
1631 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
1632 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1633 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
1634 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
1635 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1636 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
1637 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
1638 {"dret",    "",         0x7000003e, 0xffffffff, 0,                      0,              N5      },
1639 {"drol",    "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
1640 {"drol",    "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
1641 {"dror",    "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I3      },
1642 {"dror",    "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I3      },
1643 {"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
1644 {"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I65  },
1645 {"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
1646 {"drotl",   "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I65     },
1647 {"drotl",   "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I65     },
1648 {"drotr",   "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I65     },
1649 {"drotr",   "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I65     },
1650 {"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I65     },
1651 {"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              I65     },
1652 {"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,              0,              I65     },
1653 {"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,              0,              I65     },
1654 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1655 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1656 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
1657 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
1658 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1659 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1660 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1661 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
1662 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
1663 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1664 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1665 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1666 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
1667 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
1668 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1669 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1670 {"dsub",    "d,v,I",    0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
1671 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1672 {"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
1673 {"dvpe",    "",         0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
1674 {"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1675 {"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
1676 {"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
1677 {"emt",     "",         0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
1678 {"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1679 {"eret",    "",         0x42000018, 0xffffffff, 0,                      0,              I3|I32  },
1680 {"evpe",    "",         0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
1681 {"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1682 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,             0,              I33     },
1683 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1684 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1685 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
1686 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
1687 {"hibernate","",        0x42000023, 0xffffffff, 0,                      0,              V1      },
1688 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,             0,              I33     },
1689 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      },
1690 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1691    the same hazard barrier effect.  */
1692 {"jr.hb",   "s",        0x00000408, 0xfc1fffff, UBD|RD_s,               0,              I32     },
1693 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      }, /* jr */
1694 /* SVR4 PIC code requires special handling for j, so it must be a
1695    macro.  */
1696 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO,             0,              I1      },
1697 /* This form of j is used by the disassembler and internally by the
1698    assembler, but will never match user input (because the line above
1699    will match first).  */
1700 {"j",       "a",        0x08000000, 0xfc000000, UBD,                    0,              I1      },
1701 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I1      },
1702 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I1      },
1703 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1704    with the same hazard barrier effect.  */
1705 {"jalr.hb", "s",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I32     },
1706 {"jalr.hb", "d,s",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I32     },
1707 /* SVR4 PIC code requires special handling for jal, so it must be a
1708    macro.  */
1709 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO,             0,              I1      },
1710 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO,             0,              I1      },
1711 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO,             0,              I1      },
1712 /* This form of jal is used by the disassembler and internally by the
1713    assembler, but will never match user input (because the line above
1714    will match first).  */
1715 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              0,              I1      },
1716 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              0,              I16     },
1717 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1      },
1718 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1719 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1      },
1720 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1721 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1      },
1722 {"lca",     "t,A(b)",   0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1      },
1723 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,              I3      },
1724 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO,             0,              I1      },
1725 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1      },
1726 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
1727 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
1728 {"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
1729 {"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
1730 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
1731 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO,             0,              I1      },
1732 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO,             0,              I1      },
1733 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
1734 {"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
1735 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
1736 {"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2      },
1737 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
1738 {"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
1739 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
1740 {"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
1741 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
1742 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1743 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
1744 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1745 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
1746 /* li is at the start of the table.  */
1747 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO,             0,              I1      },
1748 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO,             0,              I1      },
1749 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO,             0,              I1      },
1750 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO,             0,              I1      },
1751 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      },
1752 {"ll",      "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2      },
1753 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
1754 {"lld",     "t,A(b)",   0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3      },
1755 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   0,              I1      },
1756 {"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5|I33|N55},
1757 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1758 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
1759 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1760 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
1761 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
1762 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
1763 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1764 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1765 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
1766 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1767 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1768 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
1769 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1770 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1      },
1771 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1772 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
1773 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
1774 {"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2      }, /* as lwl */
1775 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1776 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
1777 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
1778 {"flush",   "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2      }, /* as lwr */
1779 {"fork",    "d,s,t",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
1780 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
1781 {"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
1782 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
1783 {"lwxs",    "d,t(b)",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
1784 {"macc",    "d,s,t",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1785 {"macc",    "d,s,t",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1786 {"maccs",   "d,s,t",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1787 {"macchi",  "d,s,t",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1788 {"macchi",  "d,s,t",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1789 {"macchis", "d,s,t",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1790 {"macchiu", "d,s,t",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1791 {"macchiu", "d,s,t",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1792 {"macchius","d,s,t",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1793 {"maccu",   "d,s,t",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1794 {"maccu",   "d,s,t",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1795 {"maccus",  "d,s,t",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1796 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
1797 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
1798 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
1799 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
1800 {"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5|I33  },
1801 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
1802 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
1803 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
1804 {"madd",    "7,s,t",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
1805 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1806 {"maddp",   "s,t",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         SMT     },
1807 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
1808 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
1809 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
1810 {"maddu",   "7,s,t",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
1811 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1812 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              N411    },
1813 {"max.ob",  "X,Y,Q",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1814 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1815 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1816 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1817 {"max.qh",  "X,Y,Q",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1818 {"mfpc",    "t,P",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
1819 {"mfps",    "t,P",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
1820 {"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1821 {"mftacx",  "d,*",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1822 {"mftc0",   "d,+t",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1823 {"mftc0",   "d,+T",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1824 {"mftc0",   "d,E,H",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1825 {"mftc1",   "d,T",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
1826 {"mftc1",   "d,E",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
1827 {"mftc2",   "d,E",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1828 {"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
1829 {"mftgpr",  "d,t",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
1830 {"mfthc1",  "d,T",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
1831 {"mfthc1",  "d,E",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
1832 {"mfthc2",  "d,E",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1833 {"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1834 {"mfthi",   "d,*",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1835 {"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1836 {"mftlo",   "d,*",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1837 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,             0,              MT32    },
1838 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
1839 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
1840 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
1841 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
1842 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
1843 {"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
1844 {"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
1845 /* mfc2 is at the bottom of the table.  */
1846 /* mfhc2 is at the bottom of the table.  */
1847 /* mfc3 is at the bottom of the table.  */
1848 {"mfdr",    "t,G",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,              N5      },
1849 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             0,              I1      },
1850 {"mfhi",    "d,9",      0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              D32     },
1851 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
1852 {"mflo",    "d,9",      0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
1853 {"mflhxu",  "d",        0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
1854 {"min.ob",  "X,Y,Q",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1855 {"min.ob",  "D,S,T",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1856 {"min.ob",  "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1857 {"min.ob",  "D,S,k",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1858 {"min.qh",  "X,Y,Q",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1859 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1860 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1861 {"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1862 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
1863 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
1864 {"movf.l",  "D,S,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1865 {"movf.l",  "X,Y,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1866 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
1867 {"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
1868 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
1869 {"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
1870 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
1871 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1872 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1873 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
1874 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
1875 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
1876 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
1877 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1878 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1879 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
1880 {"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
1881 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
1882 {"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
1883 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
1884 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1885 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1886 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
1887 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
1888 {"msac",    "d,s,t",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1889 {"msacu",   "d,s,t",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1890 {"msachi",  "d,s,t",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1891 {"msachiu", "d,s,t",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1892 /* move is at the top of the table.  */
1893 {"msgn.qh", "X,Y,Q",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1894 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
1895 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
1896 {"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
1897 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
1898 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
1899 {"msub",    "7,s,t",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
1900 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
1901 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
1902 {"msubu",   "7,s,t",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
1903 {"mtpc",    "t,P",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
1904 {"mtps",    "t,P",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
1905 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
1906 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
1907 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
1908 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
1909 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
1910 {"mthc1",   "t,S",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
1911 {"mthc1",   "t,G",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
1912 /* mtc2 is at the bottom of the table.  */
1913 /* mthc2 is at the bottom of the table.  */
1914 /* mtc3 is at the bottom of the table.  */
1915 {"mtdr",    "t,G",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,              N5      },
1916 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,              I1      },
1917 {"mthi",    "s,7",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              D32     },
1918 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
1919 {"mtlo",    "s,7",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
1920 {"mtlhx",   "s",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
1921 {"mttc0",   "t,G",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1922 {"mttc0",   "t,+D",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1923 {"mttc0",   "t,G,H",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1924 {"mttc1",   "t,S",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
1925 {"mttc1",   "t,G",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
1926 {"mttc2",   "t,g",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
1927 {"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1928 {"mttacx",  "t,&",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1929 {"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
1930 {"mttgpr",  "t,d",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
1931 {"mtthc1",  "t,S",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
1932 {"mtthc1",  "t,G",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
1933 {"mtthc2",  "t,g",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
1934 {"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1935 {"mtthi",   "t,&",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1936 {"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1937 {"mttlo",   "t,&",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1938 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,             0,              MT32    },
1939 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1940 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1941 {"mul.ob",  "X,Y,Q",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1942 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1943 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1944 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1945 {"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1946 {"mul.qh",  "X,Y,Q",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1947 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              I32|P3|N55},
1948 {"mul",     "d,s,t",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
1949 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO,             0,              I1      },
1950 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
1951 {"mula.ob", "Y,Q",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1952 {"mula.ob", "S,T",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1953 {"mula.ob", "S,T[e]",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1954 {"mula.ob", "S,k",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1955 {"mula.qh", "Y,Q",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1956 {"mulhi",   "d,s,t",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1957 {"mulhiu",  "d,s,t",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1958 {"mull.ob", "Y,Q",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1959 {"mull.ob", "S,T",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1960 {"mull.ob", "S,T[e]",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1961 {"mull.ob", "S,k",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1962 {"mull.qh", "Y,Q",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1963 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO,             0,              I1      },
1964 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1      },
1965 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
1966 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
1967 {"mulr.ps", "D,S,T",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1968 {"muls",    "d,s,t",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1969 {"mulsu",   "d,s,t",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1970 {"mulshi",  "d,s,t",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1971 {"mulshiu", "d,s,t",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1972 {"muls.ob", "Y,Q",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1973 {"muls.ob", "S,T",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1974 {"muls.ob", "S,T[e]",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1975 {"muls.ob", "S,k",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1976 {"muls.qh", "Y,Q",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1977 {"mulsl.ob", "Y,Q",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1978 {"mulsl.ob", "S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1979 {"mulsl.ob", "S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1980 {"mulsl.ob", "S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1981 {"mulsl.qh", "Y,Q",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1982 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
1983 {"mult",    "7,s,t",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
1984 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1985 {"multp",   "s,t",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
1986 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
1987 {"multu",   "7,s,t",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
1988 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1989 {"mulu",    "d,s,t",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1990 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
1991 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
1992 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1993 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1994 {"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1995 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
1996 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
1997 {"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
1998 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
1999 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2000 {"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2001 /* nop is at the start of the table.  */
2002 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2003 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
2004 {"nor.ob",  "X,Y,Q",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2005 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2006 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2007 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2008 {"nor.qh",  "X,Y,Q",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2009 {"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
2010 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2011 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
2012 {"or.ob",   "X,Y,Q",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2013 {"or.ob",   "D,S,T",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2014 {"or.ob",   "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2015 {"or.ob",   "D,S,k",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2016 {"or.qh",   "X,Y,Q",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2017 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2018 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2019 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
2020 {"pavg.ob", "X,Y,Q",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2021 {"pickf.ob", "X,Y,Q",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2022 {"pickf.ob", "D,S,T",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2023 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2024 {"pickf.ob", "D,S,k",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2025 {"pickf.qh", "X,Y,Q",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2026 {"pickt.ob", "X,Y,Q",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2027 {"pickt.ob", "D,S,T",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2028 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2029 {"pickt.ob", "D,S,k",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2030 {"pickt.qh", "X,Y,Q",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2031 {"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2032 {"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2033   /* pref and prefx are at the start of the table.  */
2034 {"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2035 {"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2036 {"pperm",   "s,t",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
2037 {"rach.ob", "X",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2038 {"rach.ob", "D",        0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
2039 {"rach.qh", "X",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2040 {"racl.ob", "X",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2041 {"racl.ob", "D",        0x4800003f, 0xfffff83f, WR_D,                   0,              N54     },
2042 {"racl.qh", "X",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2043 {"racm.ob", "X",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2044 {"racm.ob", "D",        0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
2045 {"racm.qh", "X",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2046 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2047 {"recip.ps","D,S",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2048 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2049 {"recip1.d",  "D,S",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2050 {"recip1.ps", "D,S",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2051 {"recip1.s",  "D,S",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2052 {"recip2.d",  "D,S,T",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2053 {"recip2.ps", "D,S,T",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2054 {"recip2.s",  "D,S,T",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2055 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2056 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO,             0,              I1      },
2057 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1      },
2058 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2059 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1      },
2060 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1      },
2061 {"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,                   0,              I33     },
2062 {"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,                   0,              I33     },
2063 {"rfe",     "",         0x42000010, 0xffffffff, 0,                      0,              I1|T3   },
2064 {"rnas.qh", "X,Q",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2065 {"rnau.ob", "X,Q",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2066 {"rnau.qh", "X,Q",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2067 {"rnes.qh", "X,Q",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2068 {"rneu.ob", "X,Q",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2069 {"rneu.qh", "X,Q",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2070 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I1      },
2071 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1      },
2072 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I1      },
2073 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1      },
2074 {"ror",     "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33|SMT },
2075 {"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33|SMT },
2076 {"rotl",    "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I33|SMT },
2077 {"rotl",    "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|SMT },
2078 {"rotr",    "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
2079 {"rotr",    "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
2080 {"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
2081 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2082 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2083 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2084 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2085 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2086 {"rsqrt.ps","D,S",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2087 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2088 {"rsqrt1.d",  "D,S",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2089 {"rsqrt1.ps", "D,S",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2090 {"rsqrt1.s",  "D,S",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2091 {"rsqrt2.d",  "D,S,T",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2092 {"rsqrt2.ps", "D,S,T",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2093 {"rsqrt2.s",  "D,S,T",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2094 {"rzs.qh",  "X,Q",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2095 {"rzu.ob",  "X,Q",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2096 {"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,              N54     },
2097 {"rzu.qh",  "X,Q",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2098 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2099 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1      },
2100 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2      },
2101 {"sc",      "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2      },
2102 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3      },
2103 {"scd",     "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3      },
2104 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2105 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO,             0,              I1      },
2106 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1      },
2107 {"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   0,              G2      },
2108 {"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   0,              G2      },
2109 {"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   0,              G2      },
2110 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,              I32     },
2111 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,              I32     },
2112 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2113 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2114 {"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2115 {"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2116 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
2117 {"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
2118 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
2119 {"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
2120 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2121 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO,             0,              I1      },
2122 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO,             0,              I1      },
2123 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2124 {"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
2125 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2126 {"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
2127 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,              I4|I33  },
2128 {"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2129 {"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2130 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2131 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2132 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
2133 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
2134 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
2135 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
2136 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
2137 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO,             0,              I1      },
2138 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO,             0,              I1      },
2139 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO,             0,              I1      },
2140 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO,             0,              I1      },
2141 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO,             0,              I1      },
2142 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2143 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO,             0,              I1      },
2144 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2145 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2146 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2147 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2148 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2149 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2150 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2151 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2152 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2153 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2154 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2155 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2156 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2157 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2158 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
2159 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
2160 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
2161 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
2162 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2163 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
2164 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2165 {"sll.ob",  "X,Y,Q",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2166 {"sll.ob",  "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2167 {"sll.ob",  "D,S,k",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2168 {"sll.qh",  "X,Y,Q",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2169 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2170 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
2171 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2172 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2173 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2174 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
2175 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
2176 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
2177 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
2178 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2179 {"sqrt.ps", "D,S",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2180 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2181 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
2182 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2183 {"sra.qh",  "X,Y,Q",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2184 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2185 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
2186 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2187 {"srl.ob",  "X,Y,Q",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2188 {"srl.ob",  "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2189 {"srl.ob",  "D,S,k",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2190 {"srl.qh",  "X,Y,Q",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2191 /* ssnop is at the start of the table.  */
2192 {"standby", "",         0x42000021, 0xffffffff, 0,                      0,              V1      },
2193 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2194 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
2195 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2196 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2197 {"sub.ob",  "X,Y,Q",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2198 {"sub.ob",  "D,S,T",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2199 {"sub.ob",  "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2200 {"sub.ob",  "D,S,k",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2201 {"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2202 {"sub.qh",  "X,Y,Q",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2203 {"suba.ob", "Y,Q",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2204 {"suba.qh", "Y,Q",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2205 {"subl.ob", "Y,Q",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2206 {"subl.qh", "Y,Q",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2207 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2208 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
2209 {"suspend", "",         0x42000022, 0xffffffff, 0,                      0,              V1      },
2210 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      0,              I5|I33|N55},
2211 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2212 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1      },
2213 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
2214 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
2215 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2216 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2217 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2218 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2219 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
2220 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2221 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
2222 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
2223 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
2224 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1      },
2225 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2226 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
2227 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2228 {"scache",  "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2      }, /* as swl */
2229 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2230 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
2231 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2232 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2      }, /* as swr */
2233 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0,              I4|I33  },
2234 {"sync",    "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
2235 {"sync.p",  "",         0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
2236 {"sync.l",  "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
2237 {"synci",   "o(b)",     0x041f0000, 0xfc1f0000, SM|RD_b,                0,              I33     },
2238 {"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   0,              I1      },
2239 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   0,              I1      },
2240 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2241 {"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2242 {"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2243 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* teqi */
2244 {"teq",     "s,I",      0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2      },
2245 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2246 {"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2247 {"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2248 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgei */
2249 {"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2      },
2250 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2251 {"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2252 {"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2253 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
2254 {"tgeu",    "s,I",      0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },
2255 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,              I1      },
2256 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,              I1      },
2257 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,              I1      },
2258 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,              I1      },
2259 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2260 {"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2261 {"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2262 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tlti */
2263 {"tlt",     "s,I",      0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2      },
2264 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2265 {"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2266 {"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2267 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tltiu */
2268 {"tltu",    "s,I",      0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2      },
2269 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2270 {"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2271 {"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2272 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
2273 {"tne",     "s,I",      0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
2274 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2275 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2276 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2277 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2278 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
2279 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2280 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2281 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO,             0,              I1      },
2282 {"uld",     "t,o(b)",   0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
2283 {"uld",     "t,A(b)",   0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
2284 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
2285 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO,             0,              I1      },
2286 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO,             0,              I1      },
2287 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO,             0,              I1      },
2288 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO,             0,              I1      },
2289 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO,             0,              I1      },
2290 {"usd",     "t,o(b)",   0,    (int) M_USD,      INSN_MACRO,             0,              I3      },
2291 {"usd",     "t,A(b)",   0,    (int) M_USD_A,    INSN_MACRO,             0,              I3      },
2292 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO,             0,              I1      },
2293 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO,             0,              I1      },
2294 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO,             0,              I1      },
2295 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO,             0,              I1      },
2296 {"wach.ob", "Y",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
2297 {"wach.ob", "S",        0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
2298 {"wach.qh", "Y",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
2299 {"wacl.ob", "Y,Z",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2300 {"wacl.ob", "S,T",      0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
2301 {"wacl.qh", "Y,Z",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2302 {"wait",    "",         0x42000020, 0xffffffff, TRAP,                   0,              I3|I32  },
2303 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   0,              I32|N55 },
2304 {"waiti",   "",         0x42000020, 0xffffffff, TRAP,                   0,              L1      },
2305 {"wrpgpr",  "d,w",      0x41c00000, 0xffe007ff, RD_t,                   0,              I33     },
2306 {"wsbh",    "d,w",      0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2307 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2308 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
2309 {"xor.ob",  "X,Y,Q",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2310 {"xor.ob",  "D,S,T",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2311 {"xor.ob",  "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2312 {"xor.ob",  "D,S,k",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2313 {"xor.qh",  "X,Y,Q",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2314 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2315 {"yield",   "s",        0x7c000009, 0xfc1fffff, TRAP|RD_s,              0,              MT32    },
2316 {"yield",   "d,s",      0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,         0,              MT32    },
2317
2318 /* User Defined Instruction.  */
2319 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2320 {"udi0",     "s,t,+2",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2321 {"udi0",     "s,+3",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2322 {"udi0",     "+4",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2323 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2324 {"udi1",     "s,t,+2",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2325 {"udi1",     "s,+3",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2326 {"udi1",     "+4",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2327 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2328 {"udi2",     "s,t,+2",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2329 {"udi2",     "s,+3",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2330 {"udi2",     "+4",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2331 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2332 {"udi3",     "s,t,+2",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2333 {"udi3",     "s,+3",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2334 {"udi3",     "+4",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2335 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2336 {"udi4",     "s,t,+2",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2337 {"udi4",     "s,+3",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2338 {"udi4",     "+4",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2339 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2340 {"udi5",     "s,t,+2",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2341 {"udi5",     "s,+3",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2342 {"udi5",     "+4",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2343 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2344 {"udi6",     "s,t,+2",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2345 {"udi6",     "s,+3",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2346 {"udi6",     "+4",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2347 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2348 {"udi7",     "s,t,+2",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2349 {"udi7",     "s,+3",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2350 {"udi7",     "+4",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2351 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2352 {"udi8",     "s,t,+2",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2353 {"udi8",     "s,+3",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2354 {"udi8",     "+4",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2355 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2356 {"udi9",      "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2357 {"udi9",     "s,+3",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2358 {"udi9",     "+4",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2359 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2360 {"udi10",    "s,t,+2",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2361 {"udi10",    "s,+3",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2362 {"udi10",    "+4",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2363 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2364 {"udi11",    "s,t,+2",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2365 {"udi11",    "s,+3",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2366 {"udi11",    "+4",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2367 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2368 {"udi12",    "s,t,+2",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2369 {"udi12",    "s,+3",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2370 {"udi12",    "+4",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2371 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2372 {"udi13",    "s,t,+2",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2373 {"udi13",    "s,+3",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2374 {"udi13",    "+4",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2375 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2376 {"udi14",    "s,t,+2",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2377 {"udi14",    "s,+3",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2378 {"udi14",    "+4",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2379 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2380 {"udi15",    "s,t,+2",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2381 {"udi15",    "s,+3",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2382 {"udi15",    "+4",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2383
2384 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2385    instructions so they are here for the latters to take precedence.  */
2386 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2387 {"bc2f",    "N,p",      0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32     },
2388 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2389 {"bc2fl",   "N,p",      0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32     },
2390 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2391 {"bc2t",    "N,p",      0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32     },
2392 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2393 {"bc2tl",   "N,p",      0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
2394 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
2395 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2396 {"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
2397 {"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
2398 {"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
2399 {"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
2400 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
2401 {"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
2402 {"mfhc2",   "t,G",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
2403 {"mfhc2",   "t,G,H",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33     },
2404 {"mfhc2",   "t,i",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33     },
2405 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1      },
2406 {"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32     },
2407 {"mthc2",   "t,G",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2408 {"mthc2",   "t,G,H",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2409 {"mthc2",   "t,i",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2410
2411 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2412    instructions, so they are here for the latters to take precedence.  */
2413 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2414 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2415 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2416 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2417 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
2418 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2419 {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3      },
2420 {"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3      },
2421 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
2422 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32     },
2423 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
2424 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32     },
2425
2426 /* No hazard protection on coprocessor instructions--they shouldn't
2427    change the state of the processor and if they do it's up to the
2428    user to put in nops as necessary.  These are at the end so that the
2429    disassembler recognizes more specific versions first.  */
2430 {"c0",      "C",        0x42000000, 0xfe000000, 0,                      0,              I1      },
2431 {"c1",      "C",        0x46000000, 0xfe000000, 0,                      0,              I1      },
2432 {"c2",      "C",        0x4a000000, 0xfe000000, 0,                      0,              I1      },
2433 {"c3",      "C",        0x4e000000, 0xfe000000, 0,                      0,              I1      },
2434 {"cop0",     "C",       0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
2435 {"cop1",     "C",       0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
2436 {"cop2",     "C",       0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
2437 {"cop3",     "C",       0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
2438   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
2439      4010 any more, so move this insn out of the way.  If the object
2440      format gave us more info, we could do this right.  */
2441 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              0,              L1      },
2442 /* MIPS DSP ASE */
2443 {"absq_s.ph", "d,t",    0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2444 {"absq_s.pw", "d,t",    0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2445 {"absq_s.qh", "d,t",    0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2446 {"absq_s.w", "d,t",     0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2447 {"addq.ph", "d,s,t",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2448 {"addq.pw", "d,s,t",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2449 {"addq.qh", "d,s,t",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2450 {"addq_s.ph", "d,s,t",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2451 {"addq_s.pw", "d,s,t",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2452 {"addq_s.qh", "d,s,t",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2453 {"addq_s.w", "d,s,t",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2454 {"addsc",   "d,s,t",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2455 {"addu.ob", "d,s,t",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2456 {"addu.qb", "d,s,t",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2457 {"addu_s.ob", "d,s,t",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2458 {"addu_s.qb", "d,s,t",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2459 {"addwc",   "d,s,t",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2460 {"bitrev",  "d,t",      0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2461 {"bposge32", "p",       0x041c0000, 0xffff0000, CBD,                    0,              D32     },
2462 {"bposge64", "p",       0x041d0000, 0xffff0000, CBD,                    0,              D64     },
2463 {"cmp.eq.ph", "s,t",    0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2464 {"cmp.eq.pw", "s,t",    0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2465 {"cmp.eq.qh", "s,t",    0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2466 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2467 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2468 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2469 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2470 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2471 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2472 {"cmp.le.ph", "s,t",    0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2473 {"cmp.le.pw", "s,t",    0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2474 {"cmp.le.qh", "s,t",    0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2475 {"cmp.lt.ph", "s,t",    0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2476 {"cmp.lt.pw", "s,t",    0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2477 {"cmp.lt.qh", "s,t",    0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2478 {"cmpu.eq.ob", "s,t",   0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2479 {"cmpu.eq.qb", "s,t",   0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2480 {"cmpu.le.ob", "s,t",   0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2481 {"cmpu.le.qb", "s,t",   0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2482 {"cmpu.lt.ob", "s,t",   0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2483 {"cmpu.lt.qb", "s,t",   0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2484 {"dextpdp", "t,7,6",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D64     },
2485 {"dextpdpv", "t,7,s",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D64     },
2486 {"dextp",   "t,7,6",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2487 {"dextpv",  "t,7,s",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2488 {"dextr.l", "t,7,6",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2489 {"dextr_r.l", "t,7,6",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2490 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2491 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2492 {"dextr_r.w", "t,7,6",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2493 {"dextr_s.h", "t,7,6",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2494 {"dextrv.l", "t,7,s",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2495 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2496 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
2497 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
2498 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2499 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2500 {"dextrv.w", "t,7,s",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2501 {"dextr.w", "t,7,6",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2502 {"dinsv",   "t,s",      0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              D64     },
2503 {"dmadd",   "7,s,t",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2504 {"dmaddu",  "7,s,t",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2505 {"dmsub",   "7,s,t",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2506 {"dmsubu",  "7,s,t",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2507 {"dmthlip", "s,7",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D64     },
2508 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2509 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2510 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2511 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2512 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2513 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2514 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2515 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2516 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2517 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2518 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2519 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2520 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2521 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2522 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2523 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2524 {"dshilo",  "7,:",      0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              D64     },
2525 {"dshilov", "7,s",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              D64     },
2526 {"extpdp",  "t,7,6",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
2527 {"extpdpv", "t,7,s",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
2528 {"extp",    "t,7,6",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2529 {"extpv",   "t,7,s",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2530 {"extr_rs.w", "t,7,6",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2531 {"extr_r.w", "t,7,6",   0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2532 {"extr_s.h", "t,7,6",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2533 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2534 {"extrv_r.w", "t,7,s",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2535 {"extrv_s.h", "t,7,s",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2536 {"extrv.w", "t,7,s",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2537 {"extr.w",  "t,7,6",    0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2538 {"insv",    "t,s",      0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
2539 {"lbux",    "d,t(b)",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2540 {"ldx",     "d,t(b)",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D64     },
2541 {"lhx",     "d,t(b)",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2542 {"lwx",     "d,t(b)",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2543 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
2544 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
2545 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2546 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2547 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2548 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2549 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2550 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2551 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2552 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2553 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2554 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2555 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2556 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2557 {"modsub",  "d,s,t",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2558 {"mthlip",  "s,7",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
2559 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2560 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2561 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
2562 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
2563 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
2564 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
2565 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2566 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2567 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
2568 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D64     },
2569 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2570 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
2571 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2572 {"packrl.ph", "d,s,t",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2573 {"packrl.pw", "d,s,t",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2574 {"pick.ob", "d,s,t",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2575 {"pick.ph", "d,s,t",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2576 {"pick.pw", "d,s,t",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2577 {"pick.qb", "d,s,t",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2578 {"pick.qh", "d,s,t",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2579 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2580 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2581 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2582 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2583 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2584 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2585 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,           0,              D32     },
2586 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2587 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,           0,              D32     },
2588 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2589 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,           0,              D64     },
2590 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2591 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
2592 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2593 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2594 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2595 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2596 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,             0,              D32     },
2597 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2598 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,             0,              D32     },
2599 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2600 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2601 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2602 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2603 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
2604 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2605 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2606 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
2607 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
2608 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,     0,              D32     },
2609 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
2610 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
2611 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
2612 {"raddu.l.ob", "d,s",   0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              D64     },
2613 {"raddu.w.qb", "d,s",   0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              D32     },
2614 {"rddsp",   "d",        0x7fff04b8, 0xffff07ff, WR_d,                   0,              D32     },
2615 {"rddsp",   "d,'",      0x7c0004b8, 0xffc007ff, WR_d,                   0,              D32     },
2616 {"repl.ob", "d,5",      0x7c000096, 0xff0007ff, WR_d,                   0,              D64     },
2617 {"repl.ph", "d,@",      0x7c000292, 0xfc0007ff, WR_d,                   0,              D32     },
2618 {"repl.pw", "d,@",      0x7c000496, 0xfc0007ff, WR_d,                   0,              D64     },
2619 {"repl.qb", "d,5",      0x7c000092, 0xff0007ff, WR_d,                   0,              D32     },
2620 {"repl.qh", "d,@",      0x7c000296, 0xfc0007ff, WR_d,                   0,              D64     },
2621 {"replv.ob", "d,t",     0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2622 {"replv.ph", "d,t",     0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2623 {"replv.pw", "d,t",     0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2624 {"replv.qb", "d,t",     0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2625 {"replv.qh", "d,t",     0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2626 {"shilo",   "7,0",      0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              D32     },
2627 {"shilov",  "7,s",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              D32     },
2628 {"shll.ob", "d,t,3",    0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              D64     },
2629 {"shll.ph", "d,t,4",    0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2630 {"shll.pw", "d,t,6",    0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2631 {"shll.qb", "d,t,3",    0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              D32     },
2632 {"shll.qh", "d,t,4",    0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2633 {"shll_s.ph", "d,t,4",  0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2634 {"shll_s.pw", "d,t,6",  0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2635 {"shll_s.qh", "d,t,4",  0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2636 {"shll_s.w", "d,t,6",   0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
2637 {"shllv.ob", "d,t,s",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2638 {"shllv.ph", "d,t,s",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2639 {"shllv.pw", "d,t,s",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2640 {"shllv.qb", "d,t,s",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2641 {"shllv.qh", "d,t,s",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2642 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2643 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2644 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2645 {"shllv_s.w", "d,t,s",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2646 {"shra.ph", "d,t,4",    0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2647 {"shra.pw", "d,t,6",    0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2648 {"shra.qh", "d,t,4",    0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2649 {"shra_r.ph", "d,t,4",  0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2650 {"shra_r.pw", "d,t,6",  0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2651 {"shra_r.qh", "d,t,4",  0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2652 {"shra_r.w", "d,t,6",   0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
2653 {"shrav.ph", "d,t,s",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2654 {"shrav.pw", "d,t,s",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2655 {"shrav.qh", "d,t,s",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2656 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2657 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2658 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2659 {"shrav_r.w", "d,t,s",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2660 {"shrl.ob", "d,t,3",    0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              D64     },
2661 {"shrl.qb", "d,t,3",    0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              D32     },
2662 {"shrlv.ob", "d,t,s",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2663 {"shrlv.qb", "d,t,s",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2664 {"subq.ph", "d,s,t",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2665 {"subq.pw", "d,s,t",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2666 {"subq.qh", "d,s,t",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2667 {"subq_s.ph", "d,s,t",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2668 {"subq_s.pw", "d,s,t",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2669 {"subq_s.qh", "d,s,t",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2670 {"subq_s.w", "d,s,t",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2671 {"subu.ob", "d,s,t",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2672 {"subu.qb", "d,s,t",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2673 {"subu_s.ob", "d,s,t",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2674 {"subu_s.qb", "d,s,t",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2675 {"wrdsp",   "s",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              D32     },
2676 {"wrdsp",   "s,8",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              D32     },
2677 /* MIPS DSP ASE Rev2 */
2678 {"absq_s.qb", "d,t",    0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33     },
2679 {"addu.ph", "d,s,t",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2680 {"addu_s.ph", "d,s,t",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2681 {"adduh.qb", "d,s,t",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2682 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2683 {"append",  "t,s,h",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
2684 {"balign",  "t,s,I",    0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
2685 {"balign",  "t,s,2",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33     },
2686 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2687 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2688 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2689 {"dpa.w.ph", "7,s,t",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2690 {"dps.w.ph", "7,s,t",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2691 {"mul.ph",  "d,s,t",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2692 {"mul_s.ph", "d,s,t",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2693 {"mulq_rs.w", "d,s,t",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2694 {"mulq_s.ph", "d,s,t",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2695 {"mulq_s.w", "d,s,t",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2696 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2697 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33     },
2698 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33     },
2699 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33     },
2700 {"prepend", "t,s,h",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
2701 {"shra.qb", "d,t,3",    0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33     },
2702 {"shra_r.qb", "d,t,3",  0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33     },
2703 {"shrav.qb", "d,t,s",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2704 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2705 {"shrl.ph", "d,t,4",    0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33     },
2706 {"shrlv.ph", "d,t,s",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2707 {"subu.ph", "d,s,t",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2708 {"subu_s.ph", "d,s,t",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2709 {"subuh.qb", "d,s,t",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2710 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2711 {"addqh.ph", "d,s,t",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2712 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2713 {"addqh.w", "d,s,t",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2714 {"addqh_r.w", "d,s,t",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2715 {"subqh.ph", "d,s,t",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2716 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2717 {"subqh.w", "d,s,t",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2718 {"subqh_r.w", "d,s,t",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2719 {"dpax.w.ph", "7,s,t",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2720 {"dpsx.w.ph", "7,s,t",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2721 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
2722 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
2723 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
2724 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
2725 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
2726 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2727 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2728 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2729 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2730 /* ST Microelectronics Loongson-2E and -2F.  */
2731 {"mult.g",      "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2732 {"mult.g",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2733 {"multu.g",     "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2734 {"multu.g",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2735 {"dmult.g",     "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2736 {"dmult.g",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2737 {"dmultu.g",    "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2738 {"dmultu.g",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2739 {"div.g",       "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2740 {"div.g",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2741 {"divu.g",      "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2742 {"divu.g",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2743 {"ddiv.g",      "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2744 {"ddiv.g",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2745 {"ddivu.g",     "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2746 {"ddivu.g",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2747 {"mod.g",       "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2748 {"mod.g",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2749 {"modu.g",      "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2750 {"modu.g",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2751 {"dmod.g",      "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2752 {"dmod.g",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2753 {"dmodu.g",     "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2754 {"dmodu.g",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2755 };
2756
2757 #define MIPS_NUM_OPCODES \
2758         ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2759 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2760
2761 /* const removed from the following to allow for dynamic extensions to the
2762  * built-in instruction set. */
2763 struct mips_opcode *mips_opcodes =
2764   (struct mips_opcode *) mips_builtin_opcodes;
2765 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2766 #undef MIPS_NUM_OPCODES
2767
2768 /* Mips instructions are at maximum this many bytes long.  */
2769 #define INSNLEN 4
2770
2771 \f
2772 /* FIXME: These should be shared with gdb somehow.  */
2773
2774 struct mips_cp0sel_name
2775 {
2776   unsigned int cp0reg;
2777   unsigned int sel;
2778   const char * const name;
2779 };
2780
2781 /* The mips16 registers.  */
2782 static const unsigned int mips16_to_32_reg_map[] =
2783 {
2784   16, 17, 2, 3, 4, 5, 6, 7
2785 };
2786
2787 #define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
2788
2789
2790 static const char * const mips_gpr_names_numeric[32] =
2791 {
2792   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
2793   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
2794   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
2795   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
2796 };
2797
2798 static const char * const mips_gpr_names_oldabi[32] =
2799 {
2800   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2801   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
2802   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2803   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2804 };
2805
2806 static const char * const mips_gpr_names_newabi[32] =
2807 {
2808   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2809   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
2810   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2811   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2812 };
2813
2814 static const char * const mips_fpr_names_numeric[32] =
2815 {
2816   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
2817   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2818   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2819   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2820 };
2821
2822 static const char * const mips_fpr_names_32[32] =
2823 {
2824   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
2825   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
2826   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
2827   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
2828 };
2829
2830 static const char * const mips_fpr_names_n32[32] =
2831 {
2832   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
2833   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
2834   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
2835   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
2836 };
2837
2838 static const char * const mips_fpr_names_64[32] =
2839 {
2840   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
2841   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
2842   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
2843   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
2844 };
2845
2846 static const char * const mips_cp0_names_numeric[32] =
2847 {
2848   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
2849   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
2850   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
2851   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
2852 };
2853
2854 static const char * const mips_cp0_names_mips3264[32] =
2855 {
2856   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
2857   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
2858   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
2859   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
2860   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
2861   "c0_xcontext",  "$21",          "$22",          "c0_debug",
2862   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
2863   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
2864 };
2865
2866 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
2867 {
2868   {  4, 1, "c0_contextconfig"   },
2869   {  0, 1, "c0_mvpcontrol"      },
2870   {  0, 2, "c0_mvpconf0"        },
2871   {  0, 3, "c0_mvpconf1"        },
2872   {  1, 1, "c0_vpecontrol"      },
2873   {  1, 2, "c0_vpeconf0"        },
2874   {  1, 3, "c0_vpeconf1"        },
2875   {  1, 4, "c0_yqmask"          },
2876   {  1, 5, "c0_vpeschedule"     },
2877   {  1, 6, "c0_vpeschefback"    },
2878   {  2, 1, "c0_tcstatus"        },
2879   {  2, 2, "c0_tcbind"          },
2880   {  2, 3, "c0_tcrestart"       },
2881   {  2, 4, "c0_tchalt"          },
2882   {  2, 5, "c0_tccontext"       },
2883   {  2, 6, "c0_tcschedule"      },
2884   {  2, 7, "c0_tcschefback"     },
2885   {  5, 1, "c0_pagegrain"       },
2886   {  6, 1, "c0_srsconf0"        },
2887   {  6, 2, "c0_srsconf1"        },
2888   {  6, 3, "c0_srsconf2"        },
2889   {  6, 4, "c0_srsconf3"        },
2890   {  6, 5, "c0_srsconf4"        },
2891   { 12, 1, "c0_intctl"          },
2892   { 12, 2, "c0_srsctl"          },
2893   { 12, 3, "c0_srsmap"          },
2894   { 15, 1, "c0_ebase"           },
2895   { 16, 1, "c0_config1"         },
2896   { 16, 2, "c0_config2"         },
2897   { 16, 3, "c0_config3"         },
2898   { 18, 1, "c0_watchlo,1"       },
2899   { 18, 2, "c0_watchlo,2"       },
2900   { 18, 3, "c0_watchlo,3"       },
2901   { 18, 4, "c0_watchlo,4"       },
2902   { 18, 5, "c0_watchlo,5"       },
2903   { 18, 6, "c0_watchlo,6"       },
2904   { 18, 7, "c0_watchlo,7"       },
2905   { 19, 1, "c0_watchhi,1"       },
2906   { 19, 2, "c0_watchhi,2"       },
2907   { 19, 3, "c0_watchhi,3"       },
2908   { 19, 4, "c0_watchhi,4"       },
2909   { 19, 5, "c0_watchhi,5"       },
2910   { 19, 6, "c0_watchhi,6"       },
2911   { 19, 7, "c0_watchhi,7"       },
2912   { 23, 1, "c0_tracecontrol"    },
2913   { 23, 2, "c0_tracecontrol2"   },
2914   { 23, 3, "c0_usertracedata"   },
2915   { 23, 4, "c0_tracebpc"        },
2916   { 25, 1, "c0_perfcnt,1"       },
2917   { 25, 2, "c0_perfcnt,2"       },
2918   { 25, 3, "c0_perfcnt,3"       },
2919   { 25, 4, "c0_perfcnt,4"       },
2920   { 25, 5, "c0_perfcnt,5"       },
2921   { 25, 6, "c0_perfcnt,6"       },
2922   { 25, 7, "c0_perfcnt,7"       },
2923   { 27, 1, "c0_cacheerr,1"      },
2924   { 27, 2, "c0_cacheerr,2"      },
2925   { 27, 3, "c0_cacheerr,3"      },
2926   { 28, 1, "c0_datalo"          },
2927   { 28, 2, "c0_taglo1"          },
2928   { 28, 3, "c0_datalo1"         },
2929   { 28, 4, "c0_taglo2"          },
2930   { 28, 5, "c0_datalo2"         },
2931   { 28, 6, "c0_taglo3"          },
2932   { 28, 7, "c0_datalo3"         },
2933   { 29, 1, "c0_datahi"          },
2934   { 29, 2, "c0_taghi1"          },
2935   { 29, 3, "c0_datahi1"         },
2936   { 29, 4, "c0_taghi2"          },
2937   { 29, 5, "c0_datahi2"         },
2938   { 29, 6, "c0_taghi3"          },
2939   { 29, 7, "c0_datahi3"         },
2940 };
2941
2942 static const char * const mips_cp0_names_mips3264r2[32] =
2943 {
2944   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
2945   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
2946   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
2947   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
2948   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
2949   "c0_xcontext",  "$21",          "$22",          "c0_debug",
2950   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
2951   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
2952 };
2953
2954 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
2955 {
2956   {  4, 1, "c0_contextconfig"   },
2957   {  5, 1, "c0_pagegrain"       },
2958   { 12, 1, "c0_intctl"          },
2959   { 12, 2, "c0_srsctl"          },
2960   { 12, 3, "c0_srsmap"          },
2961   { 15, 1, "c0_ebase"           },
2962   { 16, 1, "c0_config1"         },
2963   { 16, 2, "c0_config2"         },
2964   { 16, 3, "c0_config3"         },
2965   { 18, 1, "c0_watchlo,1"       },
2966   { 18, 2, "c0_watchlo,2"       },
2967   { 18, 3, "c0_watchlo,3"       },
2968   { 18, 4, "c0_watchlo,4"       },
2969   { 18, 5, "c0_watchlo,5"       },
2970   { 18, 6, "c0_watchlo,6"       },
2971   { 18, 7, "c0_watchlo,7"       },
2972   { 19, 1, "c0_watchhi,1"       },
2973   { 19, 2, "c0_watchhi,2"       },
2974   { 19, 3, "c0_watchhi,3"       },
2975   { 19, 4, "c0_watchhi,4"       },
2976   { 19, 5, "c0_watchhi,5"       },
2977   { 19, 6, "c0_watchhi,6"       },
2978   { 19, 7, "c0_watchhi,7"       },
2979   { 23, 1, "c0_tracecontrol"    },
2980   { 23, 2, "c0_tracecontrol2"   },
2981   { 23, 3, "c0_usertracedata"   },
2982   { 23, 4, "c0_tracebpc"        },
2983   { 25, 1, "c0_perfcnt,1"       },
2984   { 25, 2, "c0_perfcnt,2"       },
2985   { 25, 3, "c0_perfcnt,3"       },
2986   { 25, 4, "c0_perfcnt,4"       },
2987   { 25, 5, "c0_perfcnt,5"       },
2988   { 25, 6, "c0_perfcnt,6"       },
2989   { 25, 7, "c0_perfcnt,7"       },
2990   { 27, 1, "c0_cacheerr,1"      },
2991   { 27, 2, "c0_cacheerr,2"      },
2992   { 27, 3, "c0_cacheerr,3"      },
2993   { 28, 1, "c0_datalo"          },
2994   { 28, 2, "c0_taglo1"          },
2995   { 28, 3, "c0_datalo1"         },
2996   { 28, 4, "c0_taglo2"          },
2997   { 28, 5, "c0_datalo2"         },
2998   { 28, 6, "c0_taglo3"          },
2999   { 28, 7, "c0_datalo3"         },
3000   { 29, 1, "c0_datahi"          },
3001   { 29, 2, "c0_taghi1"          },
3002   { 29, 3, "c0_datahi1"         },
3003   { 29, 4, "c0_taghi2"          },
3004   { 29, 5, "c0_datahi2"         },
3005   { 29, 6, "c0_taghi3"          },
3006   { 29, 7, "c0_datahi3"         },
3007 };
3008
3009 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
3010 static const char * const mips_cp0_names_sb1[32] =
3011 {
3012   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3013   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3014   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3015   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3016   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3017   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3018   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
3019   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
3020 };
3021
3022 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3023 {
3024   { 16, 1, "c0_config1"         },
3025   { 18, 1, "c0_watchlo,1"       },
3026   { 19, 1, "c0_watchhi,1"       },
3027   { 22, 0, "c0_perftrace"       },
3028   { 23, 3, "c0_edebug"          },
3029   { 25, 1, "c0_perfcnt,1"       },
3030   { 25, 2, "c0_perfcnt,2"       },
3031   { 25, 3, "c0_perfcnt,3"       },
3032   { 25, 4, "c0_perfcnt,4"       },
3033   { 25, 5, "c0_perfcnt,5"       },
3034   { 25, 6, "c0_perfcnt,6"       },
3035   { 25, 7, "c0_perfcnt,7"       },
3036   { 26, 1, "c0_buserr_pa"       },
3037   { 27, 1, "c0_cacheerr_d"      },
3038   { 27, 3, "c0_cacheerr_d_pa"   },
3039   { 28, 1, "c0_datalo_i"        },
3040   { 28, 2, "c0_taglo_d"         },
3041   { 28, 3, "c0_datalo_d"        },
3042   { 29, 1, "c0_datahi_i"        },
3043   { 29, 2, "c0_taghi_d"         },
3044   { 29, 3, "c0_datahi_d"        },
3045 };
3046
3047 static const char * const mips_hwr_names_numeric[32] =
3048 {
3049   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3050   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3051   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3052   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3053 };
3054
3055 static const char * const mips_hwr_names_mips3264r2[32] =
3056 {
3057   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
3058   "$4",          "$5",            "$6",           "$7",
3059   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3060   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3061   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3062 };
3063
3064 struct mips_abi_choice
3065 {
3066   const char *name;
3067   const char * const *gpr_names;
3068   const char * const *fpr_names;
3069 };
3070
3071 static struct mips_abi_choice mips_abi_choices[] =
3072 {
3073   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3074   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3075   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3076   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3077 };
3078
3079 struct mips_arch_choice
3080 {
3081   const char *name;
3082   int bfd_mach_valid;
3083   unsigned long bfd_mach;
3084   int processor;
3085   int isa;
3086   const char * const *cp0_names;
3087   const struct mips_cp0sel_name *cp0sel_names;
3088   unsigned int cp0sel_names_len;
3089   const char * const *hwr_names;
3090 };
3091
3092 #define bfd_mach_mips3000              3000
3093 #define bfd_mach_mips3900              3900
3094 #define bfd_mach_mips4000              4000
3095 #define bfd_mach_mips4010              4010
3096 #define bfd_mach_mips4100              4100
3097 #define bfd_mach_mips4111              4111
3098 #define bfd_mach_mips4120              4120
3099 #define bfd_mach_mips4300              4300
3100 #define bfd_mach_mips4400              4400
3101 #define bfd_mach_mips4600              4600
3102 #define bfd_mach_mips4650              4650
3103 #define bfd_mach_mips5000              5000
3104 #define bfd_mach_mips5400              5400
3105 #define bfd_mach_mips5500              5500
3106 #define bfd_mach_mips6000              6000
3107 #define bfd_mach_mips7000              7000
3108 #define bfd_mach_mips8000              8000
3109 #define bfd_mach_mips9000              9000
3110 #define bfd_mach_mips10000             10000
3111 #define bfd_mach_mips12000             12000
3112 #define bfd_mach_mips16                16
3113 #define bfd_mach_mips5                 5
3114 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
3115 #define bfd_mach_mipsisa32             32
3116 #define bfd_mach_mipsisa32r2           33
3117 #define bfd_mach_mipsisa64             64
3118 #define bfd_mach_mipsisa64r2           65
3119
3120 static const struct mips_arch_choice mips_arch_choices[] =
3121 {
3122   { "numeric",  0, 0, 0, 0,
3123     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3124
3125   { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3126     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3127   { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3128     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3129   { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3130     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3131   { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3132     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3133   { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3134     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3135   { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3136     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3137   { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3138     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3139   { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3140     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3141   { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3142     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3143   { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3144     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3145   { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3146     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3147   { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3148     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3149   { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3150     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3151   { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3152     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3153   { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3154     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3155   { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3156     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3157   { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3158     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3159   { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3160     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3161   { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3162     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3163   { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3164     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3165   { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3166     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3167
3168   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3169      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
3170      _MIPS32 Architecture For Programmers Volume I: Introduction to the
3171      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3172      page 1.  */
3173   { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
3174     ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3175     mips_cp0_names_mips3264,
3176     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3177     mips_hwr_names_numeric },
3178
3179   { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3180     (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3181      | INSN_MIPS3D | INSN_MT),
3182     mips_cp0_names_mips3264r2,
3183     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3184     mips_hwr_names_mips3264r2 },
3185
3186   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
3187   { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
3188     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3189     mips_cp0_names_mips3264,
3190     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3191     mips_hwr_names_numeric },
3192
3193   { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3194     (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3195      | INSN_DSP64 | INSN_MT | INSN_MDMX),
3196     mips_cp0_names_mips3264r2,
3197     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3198     mips_hwr_names_mips3264r2 },
3199
3200   { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
3201     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3202     mips_cp0_names_sb1,
3203     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3204     mips_hwr_names_numeric },
3205
3206   /* This entry, mips16, is here only for ISA/processor selection; do
3207      not print its name.  */
3208   { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3209     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3210 };
3211
3212 /* ISA and processor type to disassemble for, and register names to use.
3213    set_default_mips_dis_options and parse_mips_dis_options fill in these
3214    values.  */
3215 static int mips_processor;
3216 static int mips_isa;
3217 static const char * const *mips_gpr_names;
3218 static const char * const *mips_fpr_names;
3219 static const char * const *mips_cp0_names;
3220 static const struct mips_cp0sel_name *mips_cp0sel_names;
3221 static int mips_cp0sel_names_len;
3222 static const char * const *mips_hwr_names;
3223
3224 /* Other options */
3225 static int no_aliases;  /* If set disassemble as most general inst.  */
3226 \f
3227 static const struct mips_abi_choice *
3228 choose_abi_by_name (const char *name, unsigned int namelen)
3229 {
3230   const struct mips_abi_choice *c;
3231   unsigned int i;
3232
3233   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3234     if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3235         && strlen (mips_abi_choices[i].name) == namelen)
3236       c = &mips_abi_choices[i];
3237
3238   return c;
3239 }
3240
3241 static const struct mips_arch_choice *
3242 choose_arch_by_name (const char *name, unsigned int namelen)
3243 {
3244   const struct mips_arch_choice *c = NULL;
3245   unsigned int i;
3246
3247   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3248     if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3249         && strlen (mips_arch_choices[i].name) == namelen)
3250       c = &mips_arch_choices[i];
3251
3252   return c;
3253 }
3254
3255 static const struct mips_arch_choice *
3256 choose_arch_by_number (unsigned long mach)
3257 {
3258   static unsigned long hint_bfd_mach;
3259   static const struct mips_arch_choice *hint_arch_choice;
3260   const struct mips_arch_choice *c;
3261   unsigned int i;
3262
3263   /* We optimize this because even if the user specifies no
3264      flags, this will be done for every instruction!  */
3265   if (hint_bfd_mach == mach
3266       && hint_arch_choice != NULL
3267       && hint_arch_choice->bfd_mach == hint_bfd_mach)
3268     return hint_arch_choice;
3269
3270   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3271     {
3272       if (mips_arch_choices[i].bfd_mach_valid
3273           && mips_arch_choices[i].bfd_mach == mach)
3274         {
3275           c = &mips_arch_choices[i];
3276           hint_bfd_mach = mach;
3277           hint_arch_choice = c;
3278         }
3279     }
3280   return c;
3281 }
3282
3283 static void
3284 set_default_mips_dis_options (struct disassemble_info *info)
3285 {
3286   const struct mips_arch_choice *chosen_arch;
3287
3288   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
3289      and numeric FPR, CP0 register, and HWR names.  */
3290   mips_isa = ISA_MIPS3;
3291   mips_processor =  CPU_R3000;
3292   mips_gpr_names = mips_gpr_names_oldabi;
3293   mips_fpr_names = mips_fpr_names_numeric;
3294   mips_cp0_names = mips_cp0_names_numeric;
3295   mips_cp0sel_names = NULL;
3296   mips_cp0sel_names_len = 0;
3297   mips_hwr_names = mips_hwr_names_numeric;
3298   no_aliases = 0;
3299
3300   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
3301 #if 0
3302   if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
3303     {
3304       Elf_Internal_Ehdr *header;
3305
3306       header = elf_elfheader (info->section->owner);
3307       if (is_newabi (header))
3308         mips_gpr_names = mips_gpr_names_newabi;
3309     }
3310 #endif
3311
3312   /* Set ISA, architecture, and cp0 register names as best we can.  */
3313 #if !defined(SYMTAB_AVAILABLE) && 0
3314   /* This is running out on a target machine, not in a host tool.
3315      FIXME: Where does mips_target_info come from?  */
3316   target_processor = mips_target_info.processor;
3317   mips_isa = mips_target_info.isa;
3318 #else
3319   chosen_arch = choose_arch_by_number (info->mach);
3320   if (chosen_arch != NULL)
3321     {
3322       mips_processor = chosen_arch->processor;
3323       mips_isa = chosen_arch->isa;
3324       mips_cp0_names = chosen_arch->cp0_names;
3325       mips_cp0sel_names = chosen_arch->cp0sel_names;
3326       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3327       mips_hwr_names = chosen_arch->hwr_names;
3328     }
3329 #endif
3330 }
3331
3332 static void
3333 parse_mips_dis_option (const char *option, unsigned int len)
3334 {
3335   unsigned int i, optionlen, vallen;
3336   const char *val;
3337   const struct mips_abi_choice *chosen_abi;
3338   const struct mips_arch_choice *chosen_arch;
3339
3340   /* Look for the = that delimits the end of the option name.  */
3341   for (i = 0; i < len; i++)
3342     {
3343       if (option[i] == '=')
3344         break;
3345     }
3346   if (i == 0)           /* Invalid option: no name before '='.  */
3347     return;
3348   if (i == len)         /* Invalid option: no '='.  */
3349     return;
3350   if (i == (len - 1))   /* Invalid option: no value after '='.  */
3351     return;
3352
3353   optionlen = i;
3354   val = option + (optionlen + 1);
3355   vallen = len - (optionlen + 1);
3356
3357   if (strncmp("gpr-names", option, optionlen) == 0
3358       && strlen("gpr-names") == optionlen)
3359     {
3360       chosen_abi = choose_abi_by_name (val, vallen);
3361       if (chosen_abi != NULL)
3362         mips_gpr_names = chosen_abi->gpr_names;
3363       return;
3364     }
3365
3366   if (strncmp("fpr-names", option, optionlen) == 0
3367       && strlen("fpr-names") == optionlen)
3368     {
3369       chosen_abi = choose_abi_by_name (val, vallen);
3370       if (chosen_abi != NULL)
3371         mips_fpr_names = chosen_abi->fpr_names;
3372       return;
3373     }
3374
3375   if (strncmp("cp0-names", option, optionlen) == 0
3376       && strlen("cp0-names") == optionlen)
3377     {
3378       chosen_arch = choose_arch_by_name (val, vallen);
3379       if (chosen_arch != NULL)
3380         {
3381           mips_cp0_names = chosen_arch->cp0_names;
3382           mips_cp0sel_names = chosen_arch->cp0sel_names;
3383           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3384         }
3385       return;
3386     }
3387
3388   if (strncmp("hwr-names", option, optionlen) == 0
3389       && strlen("hwr-names") == optionlen)
3390     {
3391       chosen_arch = choose_arch_by_name (val, vallen);
3392       if (chosen_arch != NULL)
3393         mips_hwr_names = chosen_arch->hwr_names;
3394       return;
3395     }
3396
3397   if (strncmp("reg-names", option, optionlen) == 0
3398       && strlen("reg-names") == optionlen)
3399     {
3400       /* We check both ABI and ARCH here unconditionally, so
3401          that "numeric" will do the desirable thing: select
3402          numeric register names for all registers.  Other than
3403          that, a given name probably won't match both.  */
3404       chosen_abi = choose_abi_by_name (val, vallen);
3405       if (chosen_abi != NULL)
3406         {
3407           mips_gpr_names = chosen_abi->gpr_names;
3408           mips_fpr_names = chosen_abi->fpr_names;
3409         }
3410       chosen_arch = choose_arch_by_name (val, vallen);
3411       if (chosen_arch != NULL)
3412         {
3413           mips_cp0_names = chosen_arch->cp0_names;
3414           mips_cp0sel_names = chosen_arch->cp0sel_names;
3415           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3416           mips_hwr_names = chosen_arch->hwr_names;
3417         }
3418       return;
3419     }
3420
3421   /* Invalid option.  */
3422 }
3423
3424 static void
3425 parse_mips_dis_options (const char *options)
3426 {
3427   const char *option_end;
3428
3429   if (options == NULL)
3430     return;
3431
3432   while (*options != '\0')
3433     {
3434       /* Skip empty options.  */
3435       if (*options == ',')
3436         {
3437           options++;
3438           continue;
3439         }
3440
3441       /* We know that *options is neither NUL or a comma.  */
3442       option_end = options + 1;
3443       while (*option_end != ',' && *option_end != '\0')
3444         option_end++;
3445
3446       parse_mips_dis_option (options, option_end - options);
3447
3448       /* Go on to the next one.  If option_end points to a comma, it
3449          will be skipped above.  */
3450       options = option_end;
3451     }
3452 }
3453
3454 static const struct mips_cp0sel_name *
3455 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
3456                          unsigned int len,
3457                          unsigned int cp0reg,
3458                          unsigned int sel)
3459 {
3460   unsigned int i;
3461
3462   for (i = 0; i < len; i++)
3463     if (names[i].cp0reg == cp0reg && names[i].sel == sel)
3464       return &names[i];
3465   return NULL;
3466 }
3467 \f
3468 /* Print insn arguments for 32/64-bit code.  */
3469
3470 static void
3471 print_insn_args (const char *d,
3472                  register unsigned long int l,
3473                  bfd_vma pc,
3474                  struct disassemble_info *info,
3475                  const struct mips_opcode *opp)
3476 {
3477   int op, delta;
3478   unsigned int lsb, msb, msbd;
3479
3480   lsb = 0;
3481
3482   for (; *d != '\0'; d++)
3483     {
3484       switch (*d)
3485         {
3486         case ',':
3487         case '(':
3488         case ')':
3489         case '[':
3490         case ']':
3491           (*info->fprintf_func) (info->stream, "%c", *d);
3492           break;
3493
3494         case '+':
3495           /* Extension character; switch for second char.  */
3496           d++;
3497           switch (*d)
3498             {
3499             case '\0':
3500               /* xgettext:c-format */
3501               (*info->fprintf_func) (info->stream,
3502                                      _("# internal error, incomplete extension sequence (+)"));
3503               return;
3504
3505             case 'A':
3506               lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
3507               (*info->fprintf_func) (info->stream, "0x%x", lsb);
3508               break;
3509
3510             case 'B':
3511               msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
3512               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3513               break;
3514
3515             case '1':
3516               (*info->fprintf_func) (info->stream, "0x%lx",
3517                                      (l >> OP_SH_UDI1) & OP_MASK_UDI1);
3518               break;
3519
3520             case '2':
3521               (*info->fprintf_func) (info->stream, "0x%lx",
3522                                      (l >> OP_SH_UDI2) & OP_MASK_UDI2);
3523               break;
3524
3525             case '3':
3526               (*info->fprintf_func) (info->stream, "0x%lx",
3527                                      (l >> OP_SH_UDI3) & OP_MASK_UDI3);
3528               break;
3529
3530             case '4':
3531               (*info->fprintf_func) (info->stream, "0x%lx",
3532                                      (l >> OP_SH_UDI4) & OP_MASK_UDI4);
3533               break;
3534
3535             case 'C':
3536             case 'H':
3537               msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
3538               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3539               break;
3540
3541             case 'D':
3542               {
3543                 const struct mips_cp0sel_name *n;
3544                 unsigned int cp0reg, sel;
3545
3546                 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
3547                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3548
3549                 /* CP0 register including 'sel' code for mtcN (et al.), to be
3550                    printed textually if known.  If not known, print both
3551                    CP0 register name and sel numerically since CP0 register
3552                    with sel 0 may have a name unrelated to register being
3553                    printed.  */
3554                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3555                                             mips_cp0sel_names_len, cp0reg, sel);
3556                 if (n != NULL)
3557                   (*info->fprintf_func) (info->stream, "%s", n->name);
3558                 else
3559                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3560                 break;
3561               }
3562
3563             case 'E':
3564               lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
3565               (*info->fprintf_func) (info->stream, "0x%x", lsb);
3566               break;
3567
3568             case 'F':
3569               msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
3570               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3571               break;
3572
3573             case 'G':
3574               msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
3575               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3576               break;
3577
3578             case 't': /* Coprocessor 0 reg name */
3579               (*info->fprintf_func) (info->stream, "%s",
3580                                      mips_cp0_names[(l >> OP_SH_RT) &
3581                                                      OP_MASK_RT]);
3582               break;
3583
3584             case 'T': /* Coprocessor 0 reg name */
3585               {
3586                 const struct mips_cp0sel_name *n;
3587                 unsigned int cp0reg, sel;
3588
3589                 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
3590                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3591
3592                 /* CP0 register including 'sel' code for mftc0, to be
3593                    printed textually if known.  If not known, print both
3594                    CP0 register name and sel numerically since CP0 register
3595                    with sel 0 may have a name unrelated to register being
3596                    printed.  */
3597                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3598                                             mips_cp0sel_names_len, cp0reg, sel);
3599                 if (n != NULL)
3600                   (*info->fprintf_func) (info->stream, "%s", n->name);
3601                 else
3602                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3603                 break;
3604               }
3605
3606             default:
3607               /* xgettext:c-format */
3608               (*info->fprintf_func) (info->stream,
3609                                      _("# internal error, undefined extension sequence (+%c)"),
3610                                      *d);
3611               return;
3612             }
3613           break;
3614
3615         case '2':
3616           (*info->fprintf_func) (info->stream, "0x%lx",
3617                                  (l >> OP_SH_BP) & OP_MASK_BP);
3618           break;
3619
3620         case '3':
3621           (*info->fprintf_func) (info->stream, "0x%lx",
3622                                  (l >> OP_SH_SA3) & OP_MASK_SA3);
3623           break;
3624
3625         case '4':
3626           (*info->fprintf_func) (info->stream, "0x%lx",
3627                                  (l >> OP_SH_SA4) & OP_MASK_SA4);
3628           break;
3629
3630         case '5':
3631           (*info->fprintf_func) (info->stream, "0x%lx",
3632                                  (l >> OP_SH_IMM8) & OP_MASK_IMM8);
3633           break;
3634
3635         case '6':
3636           (*info->fprintf_func) (info->stream, "0x%lx",
3637                                  (l >> OP_SH_RS) & OP_MASK_RS);
3638           break;
3639
3640         case '7':
3641           (*info->fprintf_func) (info->stream, "$ac%ld",
3642                                  (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
3643           break;
3644
3645         case '8':
3646           (*info->fprintf_func) (info->stream, "0x%lx",
3647                                  (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
3648           break;
3649
3650         case '9':
3651           (*info->fprintf_func) (info->stream, "$ac%ld",
3652                                  (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
3653           break;
3654
3655         case '0': /* dsp 6-bit signed immediate in bit 20 */
3656           delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
3657           if (delta & 0x20) /* test sign bit */
3658             delta |= ~OP_MASK_DSPSFT;
3659           (*info->fprintf_func) (info->stream, "%d", delta);
3660           break;
3661
3662         case ':': /* dsp 7-bit signed immediate in bit 19 */
3663           delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
3664           if (delta & 0x40) /* test sign bit */
3665             delta |= ~OP_MASK_DSPSFT_7;
3666           (*info->fprintf_func) (info->stream, "%d", delta);
3667           break;
3668
3669         case '\'':
3670           (*info->fprintf_func) (info->stream, "0x%lx",
3671                                  (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
3672           break;
3673
3674         case '@': /* dsp 10-bit signed immediate in bit 16 */
3675           delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
3676           if (delta & 0x200) /* test sign bit */
3677             delta |= ~OP_MASK_IMM10;
3678           (*info->fprintf_func) (info->stream, "%d", delta);
3679           break;
3680
3681         case '!':
3682           (*info->fprintf_func) (info->stream, "%ld",
3683                                  (l >> OP_SH_MT_U) & OP_MASK_MT_U);
3684           break;
3685
3686         case '$':
3687           (*info->fprintf_func) (info->stream, "%ld",
3688                                  (l >> OP_SH_MT_H) & OP_MASK_MT_H);
3689           break;
3690
3691         case '*':
3692           (*info->fprintf_func) (info->stream, "$ac%ld",
3693                                  (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
3694           break;
3695
3696         case '&':
3697           (*info->fprintf_func) (info->stream, "$ac%ld",
3698                                  (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
3699           break;
3700
3701         case 'g':
3702           /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
3703           (*info->fprintf_func) (info->stream, "$%ld",
3704                                  (l >> OP_SH_RD) & OP_MASK_RD);
3705           break;
3706
3707         case 's':
3708         case 'b':
3709         case 'r':
3710         case 'v':
3711           (*info->fprintf_func) (info->stream, "%s",
3712                                  mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
3713           break;
3714
3715         case 't':
3716         case 'w':
3717           (*info->fprintf_func) (info->stream, "%s",
3718                                  mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3719           break;
3720
3721         case 'i':
3722         case 'u':
3723           (*info->fprintf_func) (info->stream, "0x%lx",
3724                                  (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
3725           break;
3726
3727         case 'j': /* Same as i, but sign-extended.  */
3728         case 'o':
3729           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3730           if (delta & 0x8000)
3731             delta |= ~0xffff;
3732           (*info->fprintf_func) (info->stream, "%d",
3733                                  delta);
3734           break;
3735
3736         case 'h':
3737           (*info->fprintf_func) (info->stream, "0x%x",
3738                                  (unsigned int) ((l >> OP_SH_PREFX)
3739                                                  & OP_MASK_PREFX));
3740           break;
3741
3742         case 'k':
3743           (*info->fprintf_func) (info->stream, "0x%x",
3744                                  (unsigned int) ((l >> OP_SH_CACHE)
3745                                                  & OP_MASK_CACHE));
3746           break;
3747
3748         case 'a':
3749           info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
3750                           | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
3751           /* For gdb disassembler, force odd address on jalx.  */
3752           if (info->flavour == bfd_target_unknown_flavour
3753               && strcmp (opp->name, "jalx") == 0)
3754             info->target |= 1;
3755           (*info->print_address_func) (info->target, info);
3756           break;
3757
3758         case 'p':
3759           /* Sign extend the displacement.  */
3760           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3761           if (delta & 0x8000)
3762             delta |= ~0xffff;
3763           info->target = (delta << 2) + pc + INSNLEN;
3764           (*info->print_address_func) (info->target, info);
3765           break;
3766
3767         case 'd':
3768           (*info->fprintf_func) (info->stream, "%s",
3769                                  mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3770           break;
3771
3772         case 'U':
3773           {
3774             /* First check for both rd and rt being equal.  */
3775             unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
3776             if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
3777               (*info->fprintf_func) (info->stream, "%s",
3778                                      mips_gpr_names[reg]);
3779             else
3780               {
3781                 /* If one is zero use the other.  */
3782                 if (reg == 0)
3783                   (*info->fprintf_func) (info->stream, "%s",
3784                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3785                 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
3786                   (*info->fprintf_func) (info->stream, "%s",
3787                                          mips_gpr_names[reg]);
3788                 else /* Bogus, result depends on processor.  */
3789                   (*info->fprintf_func) (info->stream, "%s or %s",
3790                                          mips_gpr_names[reg],
3791                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3792               }
3793           }
3794           break;
3795
3796         case 'z':
3797           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3798           break;
3799
3800         case '<':
3801           (*info->fprintf_func) (info->stream, "0x%lx",
3802                                  (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3803           break;
3804
3805         case 'c':
3806           (*info->fprintf_func) (info->stream, "0x%lx",
3807                                  (l >> OP_SH_CODE) & OP_MASK_CODE);
3808           break;
3809
3810         case 'q':
3811           (*info->fprintf_func) (info->stream, "0x%lx",
3812                                  (l >> OP_SH_CODE2) & OP_MASK_CODE2);
3813           break;
3814
3815         case 'C':
3816           (*info->fprintf_func) (info->stream, "0x%lx",
3817                                  (l >> OP_SH_COPZ) & OP_MASK_COPZ);
3818           break;
3819
3820         case 'B':
3821           (*info->fprintf_func) (info->stream, "0x%lx",
3822
3823                                  (l >> OP_SH_CODE20) & OP_MASK_CODE20);
3824           break;
3825
3826         case 'J':
3827           (*info->fprintf_func) (info->stream, "0x%lx",
3828                                  (l >> OP_SH_CODE19) & OP_MASK_CODE19);
3829           break;
3830
3831         case 'S':
3832         case 'V':
3833           (*info->fprintf_func) (info->stream, "%s",
3834                                  mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
3835           break;
3836
3837         case 'T':
3838         case 'W':
3839           (*info->fprintf_func) (info->stream, "%s",
3840                                  mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
3841           break;
3842
3843         case 'D':
3844           (*info->fprintf_func) (info->stream, "%s",
3845                                  mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
3846           break;
3847
3848         case 'R':
3849           (*info->fprintf_func) (info->stream, "%s",
3850                                  mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
3851           break;
3852
3853         case 'E':
3854           /* Coprocessor register for lwcN instructions, et al.
3855
3856              Note that there is no load/store cp0 instructions, and
3857              that FPU (cp1) instructions disassemble this field using
3858              'T' format.  Therefore, until we gain understanding of
3859              cp2 register names, we can simply print the register
3860              numbers.  */
3861           (*info->fprintf_func) (info->stream, "$%ld",
3862                                  (l >> OP_SH_RT) & OP_MASK_RT);
3863           break;
3864
3865         case 'G':
3866           /* Coprocessor register for mtcN instructions, et al.  Note
3867              that FPU (cp1) instructions disassemble this field using
3868              'S' format.  Therefore, we only need to worry about cp0,
3869              cp2, and cp3.  */
3870           op = (l >> OP_SH_OP) & OP_MASK_OP;
3871           if (op == OP_OP_COP0)
3872             (*info->fprintf_func) (info->stream, "%s",
3873                                    mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3874           else
3875             (*info->fprintf_func) (info->stream, "$%ld",
3876                                    (l >> OP_SH_RD) & OP_MASK_RD);
3877           break;
3878
3879         case 'K':
3880           (*info->fprintf_func) (info->stream, "%s",
3881                                  mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3882           break;
3883
3884         case 'N':
3885           (*info->fprintf_func) (info->stream,
3886                                  ((opp->pinfo & (FP_D | FP_S)) != 0
3887                                   ? "$fcc%ld" : "$cc%ld"),
3888                                  (l >> OP_SH_BCC) & OP_MASK_BCC);
3889           break;
3890
3891         case 'M':
3892           (*info->fprintf_func) (info->stream, "$fcc%ld",
3893                                  (l >> OP_SH_CCC) & OP_MASK_CCC);
3894           break;
3895
3896         case 'P':
3897           (*info->fprintf_func) (info->stream, "%ld",
3898                                  (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
3899           break;
3900
3901         case 'e':
3902           (*info->fprintf_func) (info->stream, "%ld",
3903                                  (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
3904           break;
3905
3906         case '%':
3907           (*info->fprintf_func) (info->stream, "%ld",
3908                                  (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
3909           break;
3910
3911         case 'H':
3912           (*info->fprintf_func) (info->stream, "%ld",
3913                                  (l >> OP_SH_SEL) & OP_MASK_SEL);
3914           break;
3915
3916         case 'O':
3917           (*info->fprintf_func) (info->stream, "%ld",
3918                                  (l >> OP_SH_ALN) & OP_MASK_ALN);
3919           break;
3920
3921         case 'Q':
3922           {
3923             unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
3924
3925             if ((vsel & 0x10) == 0)
3926               {
3927                 int fmt;
3928
3929                 vsel &= 0x0f;
3930                 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
3931                   if ((vsel & 1) == 0)
3932                     break;
3933                 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
3934                                        (l >> OP_SH_FT) & OP_MASK_FT,
3935                                        vsel >> 1);
3936               }
3937             else if ((vsel & 0x08) == 0)
3938               {
3939                 (*info->fprintf_func) (info->stream, "$v%ld",
3940                                        (l >> OP_SH_FT) & OP_MASK_FT);
3941               }
3942             else
3943               {
3944                 (*info->fprintf_func) (info->stream, "0x%lx",
3945                                        (l >> OP_SH_FT) & OP_MASK_FT);
3946               }
3947           }
3948           break;
3949
3950         case 'X':
3951           (*info->fprintf_func) (info->stream, "$v%ld",
3952                                  (l >> OP_SH_FD) & OP_MASK_FD);
3953           break;
3954
3955         case 'Y':
3956           (*info->fprintf_func) (info->stream, "$v%ld",
3957                                  (l >> OP_SH_FS) & OP_MASK_FS);
3958           break;
3959
3960         case 'Z':
3961           (*info->fprintf_func) (info->stream, "$v%ld",
3962                                  (l >> OP_SH_FT) & OP_MASK_FT);
3963           break;
3964
3965         default:
3966           /* xgettext:c-format */
3967           (*info->fprintf_func) (info->stream,
3968                                  _("# internal error, undefined modifier(%c)"),
3969                                  *d);
3970           return;
3971         }
3972     }
3973 }
3974 \f
3975 /* Check if the object uses NewABI conventions.  */
3976 #if 0
3977 static int
3978 is_newabi (header)
3979      Elf_Internal_Ehdr *header;
3980 {
3981   /* There are no old-style ABIs which use 64-bit ELF.  */
3982   if (header->e_ident[EI_CLASS] == ELFCLASS64)
3983     return 1;
3984
3985   /* If a 32-bit ELF file, n32 is a new-style ABI.  */
3986   if ((header->e_flags & EF_MIPS_ABI2) != 0)
3987     return 1;
3988
3989   return 0;
3990 }
3991 #endif
3992 \f
3993 /* Print the mips instruction at address MEMADDR in debugged memory,
3994    on using INFO.  Returns length of the instruction, in bytes, which is
3995    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
3996    this is little-endian code.  */
3997
3998 static int
3999 print_insn_mips (bfd_vma memaddr,
4000                  unsigned long int word,
4001                  struct disassemble_info *info)
4002 {
4003   const struct mips_opcode *op;
4004   static bfd_boolean init = 0;
4005   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4006
4007   /* Build a hash table to shorten the search time.  */
4008   if (! init)
4009     {
4010       unsigned int i;
4011
4012       for (i = 0; i <= OP_MASK_OP; i++)
4013         {
4014           for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4015             {
4016               if (op->pinfo == INSN_MACRO
4017                   || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
4018                 continue;
4019               if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4020                 {
4021                   mips_hash[i] = op;
4022                   break;
4023                 }
4024             }
4025         }
4026
4027       init = 1;
4028     }
4029
4030   info->bytes_per_chunk = INSNLEN;
4031   info->display_endian = info->endian;
4032   info->insn_info_valid = 1;
4033   info->branch_delay_insns = 0;
4034   info->data_size = 0;
4035   info->insn_type = dis_nonbranch;
4036   info->target = 0;
4037   info->target2 = 0;
4038
4039   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4040   if (op != NULL)
4041     {
4042       for (; op < &mips_opcodes[NUMOPCODES]; op++)
4043         {
4044           if (op->pinfo != INSN_MACRO
4045               && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4046               && (word & op->mask) == op->match)
4047             {
4048               const char *d;
4049
4050               /* We always allow to disassemble the jalx instruction.  */
4051               if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4052                   && strcmp (op->name, "jalx"))
4053                 continue;
4054
4055               /* Figure out instruction type and branch delay information.  */
4056               if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4057                 {
4058                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4059                     info->insn_type = dis_jsr;
4060                   else
4061                     info->insn_type = dis_branch;
4062                   info->branch_delay_insns = 1;
4063                 }
4064               else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4065                                      | INSN_COND_BRANCH_LIKELY)) != 0)
4066                 {
4067                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4068                     info->insn_type = dis_condjsr;
4069                   else
4070                     info->insn_type = dis_condbranch;
4071                   info->branch_delay_insns = 1;
4072                 }
4073               else if ((op->pinfo & (INSN_STORE_MEMORY
4074                                      | INSN_LOAD_MEMORY_DELAY)) != 0)
4075                 info->insn_type = dis_dref;
4076
4077               (*info->fprintf_func) (info->stream, "%s", op->name);
4078
4079               d = op->args;
4080               if (d != NULL && *d != '\0')
4081                 {
4082                   (*info->fprintf_func) (info->stream, "\t");
4083                   print_insn_args (d, word, memaddr, info, op);
4084                 }
4085
4086               return INSNLEN;
4087             }
4088         }
4089     }
4090
4091   /* Handle undefined instructions.  */
4092   info->insn_type = dis_noninsn;
4093   (*info->fprintf_func) (info->stream, "0x%lx", word);
4094   return INSNLEN;
4095 }
4096 \f
4097 /* In an environment where we do not know the symbol type of the
4098    instruction we are forced to assume that the low order bit of the
4099    instructions' address may mark it as a mips16 instruction.  If we
4100    are single stepping, or the pc is within the disassembled function,
4101    this works.  Otherwise, we need a clue.  Sometimes.  */
4102
4103 static int
4104 _print_insn_mips (bfd_vma memaddr,
4105                   struct disassemble_info *info,
4106                   enum bfd_endian endianness)
4107 {
4108   bfd_byte buffer[INSNLEN];
4109   int status;
4110
4111   set_default_mips_dis_options (info);
4112   parse_mips_dis_options (info->disassembler_options);
4113
4114 #if 0
4115 #if 1
4116   /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
4117   /* Only a few tools will work this way.  */
4118   if (memaddr & 0x01)
4119     return print_insn_mips16 (memaddr, info);
4120 #endif
4121
4122 #if SYMTAB_AVAILABLE
4123   if (info->mach == bfd_mach_mips16
4124       || (info->flavour == bfd_target_elf_flavour
4125           && info->symbols != NULL
4126           && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
4127               == STO_MIPS16)))
4128     return print_insn_mips16 (memaddr, info);
4129 #endif
4130 #endif
4131
4132   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
4133   if (status == 0)
4134     {
4135       unsigned long insn;
4136
4137       if (endianness == BFD_ENDIAN_BIG)
4138         insn = (unsigned long) bfd_getb32 (buffer);
4139       else
4140         insn = (unsigned long) bfd_getl32 (buffer);
4141
4142       return print_insn_mips (memaddr, insn, info);
4143     }
4144   else
4145     {
4146       (*info->memory_error_func) (status, memaddr, info);
4147       return -1;
4148     }
4149 }
4150
4151 int
4152 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
4153 {
4154   return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
4155 }
4156
4157 int
4158 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
4159 {
4160   return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
4161 }
4162 \f
4163 /* Disassemble mips16 instructions.  */
4164 #if 0
4165 static int
4166 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
4167 {
4168   int status;
4169   bfd_byte buffer[2];
4170   int length;
4171   int insn;
4172   bfd_boolean use_extend;
4173   int extend = 0;
4174   const struct mips_opcode *op, *opend;
4175
4176   info->bytes_per_chunk = 2;
4177   info->display_endian = info->endian;
4178   info->insn_info_valid = 1;
4179   info->branch_delay_insns = 0;
4180   info->data_size = 0;
4181   info->insn_type = dis_nonbranch;
4182   info->target = 0;
4183   info->target2 = 0;
4184
4185   status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4186   if (status != 0)
4187     {
4188       (*info->memory_error_func) (status, memaddr, info);
4189       return -1;
4190     }
4191
4192   length = 2;
4193
4194   if (info->endian == BFD_ENDIAN_BIG)
4195     insn = bfd_getb16 (buffer);
4196   else
4197     insn = bfd_getl16 (buffer);
4198
4199   /* Handle the extend opcode specially.  */
4200   use_extend = FALSE;
4201   if ((insn & 0xf800) == 0xf000)
4202     {
4203       use_extend = TRUE;
4204       extend = insn & 0x7ff;
4205
4206       memaddr += 2;
4207
4208       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4209       if (status != 0)
4210         {
4211           (*info->fprintf_func) (info->stream, "extend 0x%x",
4212                                  (unsigned int) extend);
4213           (*info->memory_error_func) (status, memaddr, info);
4214           return -1;
4215         }
4216
4217       if (info->endian == BFD_ENDIAN_BIG)
4218         insn = bfd_getb16 (buffer);
4219       else
4220         insn = bfd_getl16 (buffer);
4221
4222       /* Check for an extend opcode followed by an extend opcode.  */
4223       if ((insn & 0xf800) == 0xf000)
4224         {
4225           (*info->fprintf_func) (info->stream, "extend 0x%x",
4226                                  (unsigned int) extend);
4227           info->insn_type = dis_noninsn;
4228           return length;
4229         }
4230
4231       length += 2;
4232     }
4233
4234   /* FIXME: Should probably use a hash table on the major opcode here.  */
4235
4236   opend = mips16_opcodes + bfd_mips16_num_opcodes;
4237   for (op = mips16_opcodes; op < opend; op++)
4238     {
4239       if (op->pinfo != INSN_MACRO
4240           && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4241           && (insn & op->mask) == op->match)
4242         {
4243           const char *s;
4244
4245           if (strchr (op->args, 'a') != NULL)
4246             {
4247               if (use_extend)
4248                 {
4249                   (*info->fprintf_func) (info->stream, "extend 0x%x",
4250                                          (unsigned int) extend);
4251                   info->insn_type = dis_noninsn;
4252                   return length - 2;
4253                 }
4254
4255               use_extend = FALSE;
4256
4257               memaddr += 2;
4258
4259               status = (*info->read_memory_func) (memaddr, buffer, 2,
4260                                                   info);
4261               if (status == 0)
4262                 {
4263                   use_extend = TRUE;
4264                   if (info->endian == BFD_ENDIAN_BIG)
4265                     extend = bfd_getb16 (buffer);
4266                   else
4267                     extend = bfd_getl16 (buffer);
4268                   length += 2;
4269                 }
4270             }
4271
4272           (*info->fprintf_func) (info->stream, "%s", op->name);
4273           if (op->args[0] != '\0')
4274             (*info->fprintf_func) (info->stream, "\t");
4275
4276           for (s = op->args; *s != '\0'; s++)
4277             {
4278               if (*s == ','
4279                   && s[1] == 'w'
4280                   && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
4281                       == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
4282                 {
4283                   /* Skip the register and the comma.  */
4284                   ++s;
4285                   continue;
4286                 }
4287               if (*s == ','
4288                   && s[1] == 'v'
4289                   && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
4290                       == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
4291                 {
4292                   /* Skip the register and the comma.  */
4293                   ++s;
4294                   continue;
4295                 }
4296               print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
4297                                      info);
4298             }
4299
4300           if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4301             {
4302               info->branch_delay_insns = 1;
4303               if (info->insn_type != dis_jsr)
4304                 info->insn_type = dis_branch;
4305             }
4306
4307           return length;
4308         }
4309     }
4310
4311   if (use_extend)
4312     (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
4313   (*info->fprintf_func) (info->stream, "0x%x", insn);
4314   info->insn_type = dis_noninsn;
4315
4316   return length;
4317 }
4318
4319 /* Disassemble an operand for a mips16 instruction.  */
4320
4321 static void
4322 print_mips16_insn_arg (char type,
4323                        const struct mips_opcode *op,
4324                        int l,
4325                        bfd_boolean use_extend,
4326                        int extend,
4327                        bfd_vma memaddr,
4328                        struct disassemble_info *info)
4329 {
4330   switch (type)
4331     {
4332     case ',':
4333     case '(':
4334     case ')':
4335       (*info->fprintf_func) (info->stream, "%c", type);
4336       break;
4337
4338     case 'y':
4339     case 'w':
4340       (*info->fprintf_func) (info->stream, "%s",
4341                              mips16_reg_names(((l >> MIPS16OP_SH_RY)
4342                                                & MIPS16OP_MASK_RY)));
4343       break;
4344
4345     case 'x':
4346     case 'v':
4347       (*info->fprintf_func) (info->stream, "%s",
4348                              mips16_reg_names(((l >> MIPS16OP_SH_RX)
4349                                                & MIPS16OP_MASK_RX)));
4350       break;
4351
4352     case 'z':
4353       (*info->fprintf_func) (info->stream, "%s",
4354                              mips16_reg_names(((l >> MIPS16OP_SH_RZ)
4355                                                & MIPS16OP_MASK_RZ)));
4356       break;
4357
4358     case 'Z':
4359       (*info->fprintf_func) (info->stream, "%s",
4360                              mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
4361                                                & MIPS16OP_MASK_MOVE32Z)));
4362       break;
4363
4364     case '0':
4365       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4366       break;
4367
4368     case 'S':
4369       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
4370       break;
4371
4372     case 'P':
4373       (*info->fprintf_func) (info->stream, "$pc");
4374       break;
4375
4376     case 'R':
4377       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
4378       break;
4379
4380     case 'X':
4381       (*info->fprintf_func) (info->stream, "%s",
4382                              mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
4383                                             & MIPS16OP_MASK_REGR32)]);
4384       break;
4385
4386     case 'Y':
4387       (*info->fprintf_func) (info->stream, "%s",
4388                              mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
4389       break;
4390
4391     case '<':
4392     case '>':
4393     case '[':
4394     case ']':
4395     case '4':
4396     case '5':
4397     case 'H':
4398     case 'W':
4399     case 'D':
4400     case 'j':
4401     case '6':
4402     case '8':
4403     case 'V':
4404     case 'C':
4405     case 'U':
4406     case 'k':
4407     case 'K':
4408     case 'p':
4409     case 'q':
4410     case 'A':
4411     case 'B':
4412     case 'E':
4413       {
4414         int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
4415
4416         shift = 0;
4417         signedp = 0;
4418         extbits = 16;
4419         pcrel = 0;
4420         extu = 0;
4421         branch = 0;
4422         switch (type)
4423           {
4424           case '<':
4425             nbits = 3;
4426             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4427             extbits = 5;
4428             extu = 1;
4429             break;
4430           case '>':
4431             nbits = 3;
4432             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4433             extbits = 5;
4434             extu = 1;
4435             break;
4436           case '[':
4437             nbits = 3;
4438             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4439             extbits = 6;
4440             extu = 1;
4441             break;
4442           case ']':
4443             nbits = 3;
4444             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4445             extbits = 6;
4446             extu = 1;
4447             break;
4448           case '4':
4449             nbits = 4;
4450             immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
4451             signedp = 1;
4452             extbits = 15;
4453             break;
4454           case '5':
4455             nbits = 5;
4456             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4457             info->insn_type = dis_dref;
4458             info->data_size = 1;
4459             break;
4460           case 'H':
4461             nbits = 5;
4462             shift = 1;
4463             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4464             info->insn_type = dis_dref;
4465             info->data_size = 2;
4466             break;
4467           case 'W':
4468             nbits = 5;
4469             shift = 2;
4470             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4471             if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
4472                 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
4473               {
4474                 info->insn_type = dis_dref;
4475                 info->data_size = 4;
4476               }
4477             break;
4478           case 'D':
4479             nbits = 5;
4480             shift = 3;
4481             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4482             info->insn_type = dis_dref;
4483             info->data_size = 8;
4484             break;
4485           case 'j':
4486             nbits = 5;
4487             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4488             signedp = 1;
4489             break;
4490           case '6':
4491             nbits = 6;
4492             immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4493             break;
4494           case '8':
4495             nbits = 8;
4496             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4497             break;
4498           case 'V':
4499             nbits = 8;
4500             shift = 2;
4501             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4502             /* FIXME: This might be lw, or it might be addiu to $sp or
4503                $pc.  We assume it's load.  */
4504             info->insn_type = dis_dref;
4505             info->data_size = 4;
4506             break;
4507           case 'C':
4508             nbits = 8;
4509             shift = 3;
4510             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4511             info->insn_type = dis_dref;
4512             info->data_size = 8;
4513             break;
4514           case 'U':
4515             nbits = 8;
4516             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4517             extu = 1;
4518             break;
4519           case 'k':
4520             nbits = 8;
4521             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4522             signedp = 1;
4523             break;
4524           case 'K':
4525             nbits = 8;
4526             shift = 3;
4527             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4528             signedp = 1;
4529             break;
4530           case 'p':
4531             nbits = 8;
4532             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4533             signedp = 1;
4534             pcrel = 1;
4535             branch = 1;
4536             info->insn_type = dis_condbranch;
4537             break;
4538           case 'q':
4539             nbits = 11;
4540             immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
4541             signedp = 1;
4542             pcrel = 1;
4543             branch = 1;
4544             info->insn_type = dis_branch;
4545             break;
4546           case 'A':
4547             nbits = 8;
4548             shift = 2;
4549             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4550             pcrel = 1;
4551             /* FIXME: This can be lw or la.  We assume it is lw.  */
4552             info->insn_type = dis_dref;
4553             info->data_size = 4;
4554             break;
4555           case 'B':
4556             nbits = 5;
4557             shift = 3;
4558             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4559             pcrel = 1;
4560             info->insn_type = dis_dref;
4561             info->data_size = 8;
4562             break;
4563           case 'E':
4564             nbits = 5;
4565             shift = 2;
4566             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4567             pcrel = 1;
4568             break;
4569           default:
4570             abort ();
4571           }
4572
4573         if (! use_extend)
4574           {
4575             if (signedp && immed >= (1 << (nbits - 1)))
4576               immed -= 1 << nbits;
4577             immed <<= shift;
4578             if ((type == '<' || type == '>' || type == '[' || type == ']')
4579                 && immed == 0)
4580               immed = 8;
4581           }
4582         else
4583           {
4584             if (extbits == 16)
4585               immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
4586             else if (extbits == 15)
4587               immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
4588             else
4589               immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
4590             immed &= (1 << extbits) - 1;
4591             if (! extu && immed >= (1 << (extbits - 1)))
4592               immed -= 1 << extbits;
4593           }
4594
4595         if (! pcrel)
4596           (*info->fprintf_func) (info->stream, "%d", immed);
4597         else
4598           {
4599             bfd_vma baseaddr;
4600
4601             if (branch)
4602               {
4603                 immed *= 2;
4604                 baseaddr = memaddr + 2;
4605               }
4606             else if (use_extend)
4607               baseaddr = memaddr - 2;
4608             else
4609               {
4610                 int status;
4611                 bfd_byte buffer[2];
4612
4613                 baseaddr = memaddr;
4614
4615                 /* If this instruction is in the delay slot of a jr
4616                    instruction, the base address is the address of the
4617                    jr instruction.  If it is in the delay slot of jalr
4618                    instruction, the base address is the address of the
4619                    jalr instruction.  This test is unreliable: we have
4620                    no way of knowing whether the previous word is
4621                    instruction or data.  */
4622                 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
4623                                                     info);
4624                 if (status == 0
4625                     && (((info->endian == BFD_ENDIAN_BIG
4626                           ? bfd_getb16 (buffer)
4627                           : bfd_getl16 (buffer))
4628                          & 0xf800) == 0x1800))
4629                   baseaddr = memaddr - 4;
4630                 else
4631                   {
4632                     status = (*info->read_memory_func) (memaddr - 2, buffer,
4633                                                         2, info);
4634                     if (status == 0
4635                         && (((info->endian == BFD_ENDIAN_BIG
4636                               ? bfd_getb16 (buffer)
4637                               : bfd_getl16 (buffer))
4638                              & 0xf81f) == 0xe800))
4639                       baseaddr = memaddr - 2;
4640                   }
4641               }
4642             info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
4643             if (pcrel && branch
4644                 && info->flavour == bfd_target_unknown_flavour)
4645               /* For gdb disassembler, maintain odd address.  */
4646               info->target |= 1;
4647             (*info->print_address_func) (info->target, info);
4648           }
4649       }
4650       break;
4651
4652     case 'a':
4653       {
4654         int jalx = l & 0x400;
4655
4656         if (! use_extend)
4657           extend = 0;
4658         l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4659         if (!jalx && info->flavour == bfd_target_unknown_flavour)
4660           /* For gdb disassembler, maintain odd address.  */
4661           l |= 1;
4662       }
4663       info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
4664       (*info->print_address_func) (info->target, info);
4665       info->insn_type = dis_jsr;
4666       info->branch_delay_insns = 1;
4667       break;
4668
4669     case 'l':
4670     case 'L':
4671       {
4672         int need_comma, amask, smask;
4673
4674         need_comma = 0;
4675
4676         l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4677
4678         amask = (l >> 3) & 7;
4679
4680         if (amask > 0 && amask < 5)
4681           {
4682             (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4683             if (amask > 1)
4684               (*info->fprintf_func) (info->stream, "-%s",
4685                                      mips_gpr_names[amask + 3]);
4686             need_comma = 1;
4687           }
4688
4689         smask = (l >> 1) & 3;
4690         if (smask == 3)
4691           {
4692             (*info->fprintf_func) (info->stream, "%s??",
4693                                    need_comma ? "," : "");
4694             need_comma = 1;
4695           }
4696         else if (smask > 0)
4697           {
4698             (*info->fprintf_func) (info->stream, "%s%s",
4699                                    need_comma ? "," : "",
4700                                    mips_gpr_names[16]);
4701             if (smask > 1)
4702               (*info->fprintf_func) (info->stream, "-%s",
4703                                      mips_gpr_names[smask + 15]);
4704             need_comma = 1;
4705           }
4706
4707         if (l & 1)
4708           {
4709             (*info->fprintf_func) (info->stream, "%s%s",
4710                                    need_comma ? "," : "",
4711                                    mips_gpr_names[31]);
4712             need_comma = 1;
4713           }
4714
4715         if (amask == 5 || amask == 6)
4716           {
4717             (*info->fprintf_func) (info->stream, "%s$f0",
4718                                    need_comma ? "," : "");
4719             if (amask == 6)
4720               (*info->fprintf_func) (info->stream, "-$f1");
4721           }
4722       }
4723       break;
4724
4725     case 'm':
4726     case 'M':
4727       /* MIPS16e save/restore.  */
4728       {
4729       int need_comma = 0;
4730       int amask, args, statics;
4731       int nsreg, smask;
4732       int framesz;
4733       int i, j;
4734
4735       l = l & 0x7f;
4736       if (use_extend)
4737         l |= extend << 16;
4738
4739       amask = (l >> 16) & 0xf;
4740       if (amask == MIPS16_ALL_ARGS)
4741         {
4742           args = 4;
4743           statics = 0;
4744         }
4745       else if (amask == MIPS16_ALL_STATICS)
4746         {
4747           args = 0;
4748           statics = 4;
4749         }
4750       else
4751         {
4752           args = amask >> 2;
4753           statics = amask & 3;
4754         }
4755
4756       if (args > 0) {
4757           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4758           if (args > 1)
4759             (*info->fprintf_func) (info->stream, "-%s",
4760                                    mips_gpr_names[4 + args - 1]);
4761           need_comma = 1;
4762       }
4763
4764       framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
4765       if (framesz == 0 && !use_extend)
4766         framesz = 128;
4767
4768       (*info->fprintf_func) (info->stream, "%s%d",
4769                              need_comma ? "," : "",
4770                              framesz);
4771
4772       if (l & 0x40)                   /* $ra */
4773         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
4774
4775       nsreg = (l >> 24) & 0x7;
4776       smask = 0;
4777       if (l & 0x20)                   /* $s0 */
4778         smask |= 1 << 0;
4779       if (l & 0x10)                   /* $s1 */
4780         smask |= 1 << 1;
4781       if (nsreg > 0)                  /* $s2-$s8 */
4782         smask |= ((1 << nsreg) - 1) << 2;
4783
4784       /* Find first set static reg bit.  */
4785       for (i = 0; i < 9; i++)
4786         {
4787           if (smask & (1 << i))
4788             {
4789               (*info->fprintf_func) (info->stream, ",%s",
4790                                      mips_gpr_names[i == 8 ? 30 : (16 + i)]);
4791               /* Skip over string of set bits.  */
4792               for (j = i; smask & (2 << j); j++)
4793                 continue;
4794               if (j > i)
4795                 (*info->fprintf_func) (info->stream, "-%s",
4796                                        mips_gpr_names[j == 8 ? 30 : (16 + j)]);
4797               i = j + 1;
4798             }
4799         }
4800
4801       /* Statics $ax - $a3.  */
4802       if (statics == 1)
4803         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
4804       else if (statics > 0)
4805         (*info->fprintf_func) (info->stream, ",%s-%s",
4806                                mips_gpr_names[7 - statics + 1],
4807                                mips_gpr_names[7]);
4808       }
4809       break;
4810
4811     default:
4812       /* xgettext:c-format */
4813       (*info->fprintf_func)
4814         (info->stream,
4815          _("# internal disassembler error, unrecognised modifier (%c)"),
4816          type);
4817       abort ();
4818     }
4819 }
4820
4821 void
4822 print_mips_disassembler_options (FILE *stream)
4823 {
4824   unsigned int i;
4825
4826   fprintf (stream, _("\n\
4827 The following MIPS specific disassembler options are supported for use\n\
4828 with the -M switch (multiple options should be separated by commas):\n"));
4829
4830   fprintf (stream, _("\n\
4831   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
4832                            Default: based on binary being disassembled.\n"));
4833
4834   fprintf (stream, _("\n\
4835   fpr-names=ABI            Print FPR names according to specified ABI.\n\
4836                            Default: numeric.\n"));
4837
4838   fprintf (stream, _("\n\
4839   cp0-names=ARCH           Print CP0 register names according to\n\
4840                            specified architecture.\n\
4841                            Default: based on binary being disassembled.\n"));
4842
4843   fprintf (stream, _("\n\
4844   hwr-names=ARCH           Print HWR names according to specified \n\
4845                            architecture.\n\
4846                            Default: based on binary being disassembled.\n"));
4847
4848   fprintf (stream, _("\n\
4849   reg-names=ABI            Print GPR and FPR names according to\n\
4850                            specified ABI.\n"));
4851
4852   fprintf (stream, _("\n\
4853   reg-names=ARCH           Print CP0 register and HWR names according to\n\
4854                            specified architecture.\n"));
4855
4856   fprintf (stream, _("\n\
4857   For the options above, the following values are supported for \"ABI\":\n\
4858    "));
4859   for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
4860     fprintf (stream, " %s", mips_abi_choices[i].name);
4861   fprintf (stream, _("\n"));
4862
4863   fprintf (stream, _("\n\
4864   For the options above, The following values are supported for \"ARCH\":\n\
4865    "));
4866   for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
4867     if (*mips_arch_choices[i].name != '\0')
4868       fprintf (stream, " %s", mips_arch_choices[i].name);
4869   fprintf (stream, _("\n"));
4870
4871   fprintf (stream, _("\n"));
4872 }
4873 #endif