hw/s5pc1xx_onedram.h

   1 #ifndef __S5PC1XX_ONEDRAM_H__
   2 #define __S5PC1XX_ONEDRAM_H__
   3
   4 #include "sysbus.h"
   5 #include "console.h"
   6 #include "s5pc1xx.h"
   7 #include "qemu-timer.h"
   8
   9 #define TRUE     1
  10 #define FALSE    0
  11
  12 #define SUCCESS  1
  13 #define FAIL    -1
  14
  15 #define SZ_4K                           0x00001000
  16 #define SZ_1K                           0x00000400
  17 #define SZ_16M                          0x01000000
  18
  19 /* SDRAM */
  20 #define S5PC11X_PA_SDRAM                (0x30000000)
  21
  22 /*
  23  * OneDRAM memory map specific definitions
  24  */
  25 #define ONEDRAM_BASE                    0x30000000
  26 #define ONEDRAM_AP_BASE                 (ONEDRAM_BASE)
  27 #define ONEDRAM_AP_SIZE                 0x05000000      /* 80MB */
  28 #define ONEDRAM_SHARED_BASE             (ONEDRAM_BASE + ONEDRAM_AP_SIZE)
  29 #define ONEDRAM_SHARED_SIZE             0x00500000      /* 0x400000*/
  30                                                         /* 0xFFF800*/
  31                                                         /* 16382KB */
  32 #define ONEDRAM_REGISTER_SIZE           0x800
  33
  34 /*
  35  * OneDRAM Interrupt related definitions
  36  */
  37 #define ONEDRAM_SFR                     0xFFF800
  38 #define ONEDRAM_IO_BASE                 (ONEDRAM_SHARED_BASE + ONEDRAM_SFR)
  39
  40 /* A is Modem, B is Application Processor */
  41 #define ONEDRAM_SEM                     0x00            /* semaphore */
  42 #define ONEDRAM_MBX_AB                  0x20            /* mailbox AtoB */
  43 #define ONEDRAM_MBX_BA                  0x40            /* mailbox BtoA */
  44 #define ONEDRAM_CHECK_AB                0xa0            /* check AtoB */
  45 #define ONEDRAM_CHECK_BA                0xc0            /* check BtoA */
  46
  47 #define IPC_MAGIC_PTR                   0x0
  48 #define IPC_ACCESS_PTR                  0x4
  49
  50 #define ONEDRAM_START_ADDRESS           0
  51 #define ONEDRAM_MAGIC_CODE_ADDRESS      (ONEDRAM_START_ADDRESS + IPC_MAGIC_PTR)
  52 #define ONEDRAM_ACCESS_ENABLE_ADDRESS   (ONEDRAM_START_ADDRESS + IPC_ACCESS_PTR)
  53
  54 #define IPC_PART_PTR_SIZE               0x4
  55
  56 /* formatted region */
  57 #define FMT_OUT_HEAD_PTR                0x10
  58 #define FMT_OUT_TAIL_PTR                (FMT_OUT_HEAD_PTR + IPC_PART_PTR_SIZE)
  59 #define FMT_IN_HEAD_PTR                 0x18
  60 #define FMT_IN_TAIL_PTR                 (FMT_IN_HEAD_PTR + IPC_PART_PTR_SIZE)
  61
  62 /*raw region */
  63 #define RAW_OUT_HEAD_PTR                0x20
  64 #define RAW_OUT_TAIL_PTR                (RAW_OUT_HEAD_PTR + IPC_PART_PTR_SIZE)
  65 #define RAW_IN_HEAD_PTR                 0x28
  66 #define RAW_IN_TAIL_PTR                 (RAW_IN_HEAD_PTR + IPC_PART_PTR_SIZE)
  67
  68 /* remote file system region */
  69 #define RFS_OUT_HEAD_PTR                0x30
  70 #define RFS_OUT_TAIL_PTR                (RFS_OUT_HEAD_PTR + IPC_PART_PTR_SIZE)
  71 #define RFS_IN_HEAD_PTR                 0x38
  72 #define RFS_IN_TAIL_PTR                 (RFS_IN_HEAD_PTR + IPC_PART_PTR_SIZE)
  73
  74 #define CP_FATAL_DISP_SIZE              0xA0
  75 #define CP_FATAL_DISP_PTR               0x1000
  76
  77 #define FMT_BUF_SIZE                    0x1000
  78 #define FMT_OUT_BUF_PTR                 0xFE000
  79 #define FMT_IN_BUF_PTR                  0xFF000
  80
  81 #define RAW_BUF_SIZE                    0x100000
  82 #define RAW_OUT_BUF_PTR                 0x100000
  83 #define RAW_IN_BUF_PTR                  0x200000
  84
  85 #define RFS_BUF_SIZE                    0x100000
  86 #define RFS_OUT_BUF_PTR                 0x300000
  87 #define RFS_IN_BUF_PTR                  0x400000
  88
  89 #define IPC_PART_SIZE                   0x500000
  90
  91 #define ONEDRAM_OUT_FMT_BASE            FMT_OUT_BUF_PTR
  92 #define ONEDRAM_OUT_FMT_SIZE            FMT_BUF_SIZE
  93
  94 #define ONEDRAM_OUT_RAW_BASE            RAW_OUT_BUF_PTR
  95 #define ONEDRAM_OUT_RAW_SIZE            RAW_BUF_SIZE
  96
  97 #define ONEDRAM_OUT_RFS_BASE            RFS_OUT_BUF_PTR
  98 #define ONEDRAM_OUT_RFS_SIZE            RFS_BUF_SIZE
  99
 100 #define ONEDRAM_IN_FMT_BASE             FMT_IN_BUF_PTR
 101 #define ONEDRAM_IN_FMT_SIZE             FMT_BUF_SIZE
 102
 103 #define ONEDRAM_IN_RAW_BASE             RAW_IN_BUF_PTR
 104 #define ONEDRAM_IN_RAW_SIZE             RAW_BUF_SIZE
 105
 106 #define ONEDRAM_IN_RFS_BASE             RFS_IN_BUF_PTR
 107 #define ONEDRAM_IN_RFS_SIZE             RFS_BUF_SIZE
 108
 109
 110 #define MAGIC_CODE                      0x00aa
 111 #define ACCESS_ENABLE                   0x0001
 112
 113 #define IRQ_ONEDRAM_INT_AP              11
 114 #define IRQ_PHONE_ACTIVE                15
 115
 116 #define MAX_BUFFER                      1024
 117
 118 #define CONNECT_LENGTH                  4
 119
 120 #define TCP_CMD_LENGTH                  2
 121
 122
 123 /* AP IPC define */
 124 #define IPC_AP_CONNECT_ACK              0xABCD1234
 125 #define IPC_AP_SEND_FMT_ACK             0xCDAB1234
 126
 127
 128 /* CP IPC define */
 129 #define IPC_CP_CONNECT_APP              0x1234ABCD
 130 #define IPC_CP_READY_FOR_LOADING        0x12341234
 131 #define IPC_CP_IMG_LOADED               0x45674567
 132 #define IPC_CP_READY                    0xABCDABCD
 133
 134 /*
 135  * IPC 4.0 specific definitions
 136  */
 137 #define INT_MASK_VALID                  0x0080
 138 #define INT_MASK_COMMAND                0x0040
 139     /* If not command */
 140     #define INT_MASK_REQ_ACK_RFS        0x0400
 141     #define INT_MASK_RES_ACK_RFS        0x0200
 142     #define INT_MASK_SEND_RFS           0x0100
 143     #define INT_MASK_REQ_ACK_FMT        0x0020
 144     #define INT_MASK_REQ_ACK_RAW        0x0010
 145     #define INT_MASK_RES_ACK_FMT        0x0008
 146     #define INT_MASK_RES_ACK_RAW        0x0004
 147     #define INT_MASK_SEND_FMT           0x0002
 148     #define INT_MASK_SEND_RAW           0x0001
 149
 150 #define INT_MASK_CMD_NONE               0x0000
 151 #define INT_MASK_CMD_INIT_START         0x0001
 152 #define INT_MASK_CMD_INIT_END           0x0002
 153     /* CMD_INIT_END extended bit */
 154     /* CP boot state */
 155     #define REQ_ONLINE_BOOT             0x0000
 156     #define REQ_AIRPLANE_BOOT           0x1000
 157     /* AP OS type */
 158     #define AP_OS_ANDROID               0x0100
 159     #define AP_OS_WINMOBILE             0x0200
 160     #define AP_OS_LINUX                 0x0300
 161     #define AP_OS_SYMBIAN               0x0400
 162 #define INT_MASK_CMD_REQ_ACTIVE         0x0003
 163 #define INT_MASK_CMD_RES_ACTIVE         0x0004
 164 #define INT_MASK_CMD_REQ_TIME_SYNC      0x0005
 165 #define INT_MASK_CMD_PHONE_START        0x0008
 166     /* CMD_PHONE_START extended bit */
 167     /* CP chip type */
 168     #define CP_CHIP_QUALCOMM            0x0100
 169     #define CP_CHIP_INFINEON            0x0200
 170     #define CP_CHIP_BROADCOM            0x0300
 171 #define INT_MASK_CMD_ERR_DISPLAY        0x0009
 172 #define INT_MASK_CMD_PHONE_DEEP_SLEEP   0x000A
 173 #define INT_MASK_CMD_NV_REBUILDING      0x000B
 174 #define INT_MASK_CMD_EMER_DOWN          0x000C
 175 #define INT_MASK_CMD_SMP_REQ            0x000D
 176 #define INT_MASK_CMD_SMP_REP            0x000E
 177 #define INT_MASK_CMD_MAX                0x000F
 178
 179 #define INT_COMMAND(x)                  (INT_MASK_VALID | INT_MASK_COMMAND | x)
 180 #define INT_NON_COMMAND(x)              (INT_MASK_VALID | x)
 181
 182 #define BIT_INT_MASK_CMD_REQ_ACTIVE       0x001
 183 #define BIT_INT_MASK_CMD_ERR_DISPLAY      0x002
 184 #define BIT_INT_MASK_CMD_PHONE_START      0x004
 185 #define BIT_INT_MASK_CMD_REQ_TIME_SYNC    0x008
 186 #define BIT_INT_MASK_CMD_PHONE_DEEP_SLEEP 0x010
 187 #define BIT_INT_MASK_CMD_NV_REBUILDING    0x020
 188 #define BIT_INT_MASK_CMD_EMER_DOWN        0x040
 189 #define BIT_INT_MASK_CMD_SMP_REQ          0x080
 190 #define BIT_INT_MASK_CMD_SMP_REP          0x100
 191 #define BIT_MAX                           0x200
 192
 193 #define FMT_SERVICE     0
 194 #define RAW_SERVICE     1
 195 #define RFS_SERVICE     2
 196
 197 /* IRQ definition */
 198 #define IRQ_NONE                        (0)
 199 #define IRQ_HANDLED                     (1)
 200 #define IRQ_RETVAL(x)                   ((x) != 0)
 201
 202 /*
 203  * Modem deivce partitions.
 204  */
 205 #define FMT_INDEX                       0
 206 #define RAW_INDEX                       1
 207 #define RFS_INDEX                       2
 208 #define MAX_INDEX                       3
 209
 210 #define MESG_PHONE_OFF                  1
 211 #define MESG_PHONE_RESET                2
 212
 213 #define RETRY                           50
 214 #define TIME_RESOLUTION                 10
 215
 216 #define COMMAND_SUCCESS                 0x00
 217 #define COMMAND_GET_AUTHORITY_FAIL      0x01
 218 #define COMMAND_FAIL                    0x02
 219
 220 #define CONFIG_MODEM_CORE_FMT_SERVICE
 221
 222 typedef struct ModemServiceOps {
 223     int (*send_cmd_handler)(uint16_t);
 224     void (*resp_cmd_handler)(void);
 225 } ModemServiceOps;
 226
 227 typedef struct ModemInfo {
 228     /* DPRAM memory addresses */
 229     uint32_t in_head_addr;
 230     uint32_t in_tail_addr;
 231     uint32_t in_buff_addr;
 232     uint32_t in_buff_size;
 233
 234     uint32_t out_head_addr;
 235     uint32_t out_tail_addr;
 236     uint32_t out_buff_addr;
 237     uint32_t out_buff_size;
 238
 239     int ptr_size;
 240
 241     uint16_t mask_req_ack;
 242     uint16_t mask_res_ack;
 243     uint16_t mask_send;
 244 } ModemInfo;
 245
 246 typedef struct ModemPlatformData {
 247     const char *name;
 248     uint32_t booting_type;
 249     uint32_t irq_onedram_int_ap;
 250     uint32_t out_fmt_base;
 251     uint32_t out_fmt_size;
 252
 253     uint32_t in_fmt_base;
 254     uint32_t in_fmt_size;
 255
 256     int ptr_fmt_size;
 257 } ModemPlatformData;
 258
 259 /* Booting type definitions */
 260 #define XMM                             1
 261 #define MSM                             2
 262 #define QSC                             3
 263
 264 #define QEMU_MODEM                      XMM
 265
 266 #define SOCKET_BUFFER_MAX_SIZE          SZ_1K
 267
 268 typedef struct OneDRAMState {
 269     uint16_t waiting_authority;
 270     uint16_t waiting_sem_rep;
 271     uint16_t waiting_check;
 272     uint16_t non_cmd;
 273     uint16_t send_cmd;
 274     uint16_t interruptable;
 275     uint16_t writable;
 276
 277     uint8_t  *send_buf;
 278     uint8_t  send_size;
 279 } OneDRAMState;
 280
 281 typedef struct S5pc1xxOneDRAMState {
 282     SysBusDevice busdev;
 283
 284     uint32_t magic_code;
 285     uint32_t sem;
 286     uint32_t mbx_ab;
 287     uint32_t mbx_ba;
 288     uint32_t check_ab;
 289     uint32_t check_ba;
 290
 291     qemu_irq irq_onedram_int_ap;
 292     uint32_t irq_onedram_int_ap_pending;
 293     uint32_t irq_onedram_int_cp_pending;
 294
 295     CharDriverState *socket;
 296     uint32_t vmodem_connected;
 297     uint32_t vmodem_bootup;
 298     QEMUTimer *bootup_timer;
 299     QEMUTimer *sem_timer;
 300
 301     /* OneDRAM memory addresses */
 302     ModemInfo* fmt_info;
 303
 304     uint8_t *socket_buffer;
 305     uint32_t socket_len;
 306
 307     OneDRAMState onedram_state;
 308 } S5pc1xxOneDRAMState;
 309
 310 /* OneDRAM */
 311 static struct ModemPlatformData aquila_xmm_modem_data = {
 312     .name               = "aquila-XMM6160",
 313     .booting_type       = XMM,
 314     .irq_onedram_int_ap = 11,
 315
 316      /* Memory map */
 317     .out_fmt_base       = FMT_OUT_HEAD_PTR,
 318     .out_fmt_size       = FMT_BUF_SIZE,
 319     .in_fmt_base        = FMT_IN_HEAD_PTR,
 320     .in_fmt_size        = FMT_BUF_SIZE,
 321     .ptr_fmt_size       = IPC_PART_PTR_SIZE,
 322
 323 };
 324
 325 /* Command handler */
 326 static int onedram_req_active_handler(S5pc1xxOneDRAMState *s);
 327 static int onedram_smp_req_handler(S5pc1xxOneDRAMState *s);
 328 static int onedram_fmt_try_send_cmd(S5pc1xxOneDRAMState *s);
 329 static int onedram_fmt_send_cmd(S5pc1xxOneDRAMState *s);
 330 static void onedram_data_handler_fmt_autonomous(S5pc1xxOneDRAMState *s);
 331 /*static*/ void onedram_command_handler(S5pc1xxOneDRAMState *s,
 332                                         uint32_t data);
 333 /*static*/ void onedram_data_handler(S5pc1xxOneDRAMState *s,
 334                                      uint16_t non_cmd);
 335 static uint32_t onedram_can_access_shm(S5pc1xxOneDRAMState *s);
 336 static int onedram_read_shm(S5pc1xxOneDRAMState *s, uint8_t *buf,
 337                             uint32_t offset, uint32_t size);
 338 static int onedram_write_shm(S5pc1xxOneDRAMState *s,
 339                              const uint8_t *buf, uint32_t offset,
 340                              uint32_t size);
 341 /*static*/ uint32_t onedram_read_outhead(S5pc1xxOneDRAMState *s);
 342 /*static*/ uint32_t onedram_read_inhead(S5pc1xxOneDRAMState *s);
 343 /*static*/ uint32_t onedram_read_outtail(S5pc1xxOneDRAMState *s);
 344 /*static*/ uint32_t onedram_read_intail(S5pc1xxOneDRAMState *s);
 345 /*static*/ uint32_t onedram_write_outhead(S5pc1xxOneDRAMState *s,
 346                                           uint32_t head);
 347 /*static*/ uint32_t onedram_write_inhead(S5pc1xxOneDRAMState *s,
 348                                          uint32_t head);
 349 /*static*/ uint32_t onedram_write_outtail(S5pc1xxOneDRAMState *s,
 350                                           uint32_t tail);
 351 /*static*/ uint32_t onedram_write_intail(S5pc1xxOneDRAMState *s,
 352                                          uint32_t tail);
 353 /*static*/ int onedram_read_fmt(S5pc1xxOneDRAMState *s,
 354                                 uint32_t *len);
 355 /*static*/ void onedram_read_fmt_wrapup(S5pc1xxOneDRAMState *s,
 356                                         const uint16_t non_cmd);
 357 static int onedram_insert_socket(S5pc1xxOneDRAMState *s,
 358                                  uint32_t psrc, uint16_t size);
 359 void onedram_socket_push(S5pc1xxOneDRAMState *s);
 360 int onedram_write_fmt(S5pc1xxOneDRAMState *s, const uint8_t *buf,
 361                       uint32_t len);
 362 static uint32_t onedram_irq_cp_raise_32(S5pc1xxOneDRAMState *s);
 363 static uint32_t onedram_irq_cp_raise_16(S5pc1xxOneDRAMState *s);
 364 void onedram_disable_interrupt(S5pc1xxOneDRAMState *s);
 365 void onedram_enable_interrupt(S5pc1xxOneDRAMState *s);
 366 uint16_t onedram_interruptable(S5pc1xxOneDRAMState *s);
 367 static void onedram_irq_cp_lower(S5pc1xxOneDRAMState *s);
 368 static uint32_t onedram_irq_cp_pending(S5pc1xxOneDRAMState *s);
 369 static void onedram_irq_ap_raise(S5pc1xxOneDRAMState *s);
 370 static void onedram_irq_ap_lower(S5pc1xxOneDRAMState *s);
 371 static uint32_t onedram_irq_ap_pending(S5pc1xxOneDRAMState *s);
 372 unsigned int onedram_read_sem(S5pc1xxOneDRAMState *s);
 373 static void onedram_put_authority(S5pc1xxOneDRAMState *s);
 374 int onedram_try_get_authority(S5pc1xxOneDRAMState *s);
 375 void onedram_disable_write(S5pc1xxOneDRAMState *s);
 376 void onedram_enable_write(S5pc1xxOneDRAMState *s);
 377 uint16_t onedram_writable(S5pc1xxOneDRAMState *s);
 378 void onedram_send_cmd_to_pda(S5pc1xxOneDRAMState *s, uint16_t val);
 379 static void onedram_bootup(void *opaque);
 380 static void onedram_register_modem(S5pc1xxOneDRAMState *s,
 381                                    ModemPlatformData *mp);
 382 static uint32_t onedram_io_readb(void *opaque,
 383                                  target_phys_addr_t offset);
 384 static uint32_t onedram_io_readl(void *opaque,
 385                                  target_phys_addr_t offset);
 386 static void onedram_io_writeb(void *opaque, target_phys_addr_t offset,
 387                               uint32_t val);
 388 static void onedram_io_writel(void *opaque, target_phys_addr_t offset,
 389                               uint32_t val);
 390 static int onedram_tcp_can_read(void *opaque);
 391 static void onedram_tcp_read(void *opaque, const uint8_t *buf,
 392                              int size);
 393 void onedram_tcp_write(void *opaque, const uint8_t *buf, uint32_t size);
 394 static void onedram_tcp_event(void *opaque, int event);
 395 static void onedram_tcp_init(void *opaque);
 396
 397 #endif