2 * Qemu PowerPC MPC8544DS board emualtion
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
18 #include "qemu-common.h"
27 #include "device_tree.h"
33 #include "exec-memory.h"
35 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
36 #define UIMAGE_LOAD_BASE 0
37 #define DTC_LOAD_PAD 0x500000
38 #define DTC_PAD_MASK 0xFFFFF
39 #define INITRD_LOAD_PAD 0x2000000
40 #define INITRD_PAD_MASK 0xFFFFFF
42 #define RAM_SIZES_ALIGN (64UL << 20)
44 #define MPC8544_CCSRBAR_BASE 0xE0000000
45 #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000)
46 #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500)
47 #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600)
48 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000)
49 #define MPC8544_PCI_REGS_SIZE 0x1000
50 #define MPC8544_PCI_IO 0xE1000000
51 #define MPC8544_PCI_IOLEN 0x10000
52 #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000)
53 #define MPC8544_SPIN_BASE 0xEF000000
61 static int mpc8544_load_device_tree(CPUState *env,
62 target_phys_addr_t addr,
64 target_phys_addr_t initrd_base,
65 target_phys_addr_t initrd_size,
66 const char *kernel_cmdline)
70 uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
74 uint8_t hypercall[16];
75 uint32_t clock_freq = 400000000;
76 uint32_t tb_freq = 400000000;
79 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
83 fdt = load_device_tree(filename, &fdt_size);
89 /* Manipulate device tree in memory. */
90 ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
91 sizeof(mem_reg_property));
93 fprintf(stderr, "couldn't set /memory/reg\n");
96 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
99 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
102 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
103 (initrd_base + initrd_size));
105 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
109 ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
112 fprintf(stderr, "couldn't set /chosen/bootargs\n");
115 /* Read out host's frequencies */
116 clock_freq = kvmppc_get_clockfreq();
117 tb_freq = kvmppc_get_tbfreq();
119 /* indicate KVM hypercall interface */
120 qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
122 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
123 qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
124 hypercall, sizeof(hypercall));
127 /* We need to generate the cpu nodes in reverse order, so Linux can pick
128 the first node as boot node and be happy */
129 for (i = smp_cpus - 1; i >= 0; i--) {
131 uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20));
133 for (env = first_cpu; env != NULL; env = env->next_cpu) {
134 if (env->cpu_index == i) {
143 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
144 qemu_devtree_add_subnode(fdt, cpu_name);
145 qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
146 qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
147 qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
148 qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
149 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
150 env->dcache_line_size);
151 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
152 env->icache_line_size);
153 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
154 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
155 qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
156 if (env->cpu_index) {
157 qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
158 qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
159 qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
160 &cpu_release_addr, sizeof(cpu_release_addr));
162 qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
166 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
175 /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
176 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
178 return ffs(size >> 10) - 1;
181 static void mmubooke_create_initial_mapping(CPUState *env,
183 target_phys_addr_t pa)
185 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
186 target_phys_addr_t size;
188 size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT);
189 tlb->mas1 = MAS1_VALID | size;
190 tlb->mas2 = va & TARGET_PAGE_MASK;
191 tlb->mas7_3 = pa & TARGET_PAGE_MASK;
192 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
194 env->tlb_dirty = true;
197 static void mpc8544ds_cpu_reset_sec(void *opaque)
199 CPUState *env = opaque;
203 /* Secondary CPU starts in halted state for now. Needs to change when
204 implementing non-kernel boot. */
206 env->exception_index = EXCP_HLT;
209 static void mpc8544ds_cpu_reset(void *opaque)
211 CPUState *env = opaque;
212 struct boot_info *bi = env->load_info;
216 /* Set initial guest state. */
218 env->gpr[1] = (16<<20) - 8;
219 env->gpr[3] = bi->dt_base;
220 env->nip = bi->entry;
221 mmubooke_create_initial_mapping(env, 0, 0);
224 static void mpc8544ds_init(ram_addr_t ram_size,
225 const char *boot_device,
226 const char *kernel_filename,
227 const char *kernel_cmdline,
228 const char *initrd_filename,
229 const char *cpu_model)
231 MemoryRegion *address_space_mem = get_system_memory();
232 MemoryRegion *ram = g_new(MemoryRegion, 1);
234 CPUState *env = NULL;
236 uint64_t elf_lowaddr;
237 target_phys_addr_t entry=0;
238 target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
239 target_long kernel_size=0;
240 target_ulong dt_base = 0;
241 target_ulong initrd_base = 0;
242 target_long initrd_size=0;
244 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
245 qemu_irq **irqs, *mpic;
247 CPUState *firstenv = NULL;
250 if (cpu_model == NULL) {
251 cpu_model = "e500v2_v30";
254 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
255 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
256 for (i = 0; i < smp_cpus; i++) {
258 env = cpu_ppc_init(cpu_model);
260 fprintf(stderr, "Unable to initialize CPU!\n");
268 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
269 input = (qemu_irq *)env->irq_inputs;
270 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
271 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
272 env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
274 ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
276 /* Register reset handler */
279 struct boot_info *boot_info;
280 boot_info = g_malloc0(sizeof(struct boot_info));
281 qemu_register_reset(mpc8544ds_cpu_reset, env);
282 env->load_info = boot_info;
285 qemu_register_reset(mpc8544ds_cpu_reset_sec, env);
291 /* Fixup Memory size on a alignment boundary */
292 ram_size &= ~(RAM_SIZES_ALIGN - 1);
294 /* Register Memory */
295 memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size);
296 memory_region_add_subregion(address_space_mem, 0, ram);
299 mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
300 smp_cpus, irqs, NULL);
303 cpu_abort(env, "MPIC failed to initialize\n");
308 serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
309 0, mpic[12+26], 399193,
310 serial_hds[0], DEVICE_BIG_ENDIAN);
314 serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
315 0, mpic[12+26], 399193,
316 serial_hds[0], DEVICE_BIG_ENDIAN);
319 /* General Utility device */
320 sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
323 dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
324 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
325 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
327 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
329 printf("couldn't create PCI controller!\n");
331 isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
334 /* Register network interfaces. */
335 for (i = 0; i < nb_nics; i++) {
336 pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
340 /* Register spinning region */
341 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
344 if (kernel_filename) {
345 kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
346 if (kernel_size < 0) {
347 kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
348 &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
350 loadaddr = elf_lowaddr;
352 /* XXX try again as binary */
353 if (kernel_size < 0) {
354 fprintf(stderr, "qemu: could not load kernel '%s'\n",
361 if (initrd_filename) {
362 initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
363 initrd_size = load_image_targphys(initrd_filename, initrd_base,
364 ram_size - initrd_base);
366 if (initrd_size < 0) {
367 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
373 /* If we're loading a kernel directly, we must load the device tree too. */
374 if (kernel_filename) {
375 struct boot_info *boot_info;
378 cpu_abort(env, "Compiled without FDT support - can't load kernel\n");
380 dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
381 if (mpc8544_load_device_tree(env, dt_base, ram_size,
382 initrd_base, initrd_size, kernel_cmdline) < 0) {
383 fprintf(stderr, "couldn't load device tree\n");
387 boot_info = env->load_info;
388 boot_info->entry = entry;
389 boot_info->dt_base = dt_base;
397 static QEMUMachine mpc8544ds_machine = {
400 .init = mpc8544ds_init,
404 static void mpc8544ds_machine_init(void)
406 qemu_register_machine(&mpc8544ds_machine);
409 machine_init(mpc8544ds_machine_init);