hw/milkymist-hpdmc.c

   1 /*
   2  *  QEMU model of the Milkymist High Performance Dynamic Memory Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.milkymist.org/socdoc/hpdmc.pdf
  22  */
  23
  24 #include "hw.h"
  25 #include "sysbus.h"
  26 #include "trace.h"
  27 #include "qemu-error.h"
  28
  29 enum {
  30     R_SYSTEM = 0,
  31     R_BYPASS,
  32     R_TIMING,
  33     R_IODELAY,
  34     R_MAX
  35 };
  36
  37 enum {
  38     IODELAY_DQSDELAY_RDY = (1<<5),
  39     IODELAY_PLL1_LOCKED  = (1<<6),
  40     IODELAY_PLL2_LOCKED  = (1<<7),
  41 };
  42
  43 struct MilkymistHpdmcState {
  44     SysBusDevice busdev;
  45     MemoryRegion regs_region;
  46
  47     uint32_t regs[R_MAX];
  48 };
  49 typedef struct MilkymistHpdmcState MilkymistHpdmcState;
  50
  51 static uint64_t hpdmc_read(void *opaque, target_phys_addr_t addr,
  52                            unsigned size)
  53 {
  54     MilkymistHpdmcState *s = opaque;
  55     uint32_t r = 0;
  56
  57     addr >>= 2;
  58     switch (addr) {
  59     case R_SYSTEM:
  60     case R_BYPASS:
  61     case R_TIMING:
  62     case R_IODELAY:
  63         r = s->regs[addr];
  64         break;
  65
  66     default:
  67         error_report("milkymist_hpdmc: read access to unknown register 0x"
  68                 TARGET_FMT_plx, addr << 2);
  69         break;
  70     }
  71
  72     trace_milkymist_hpdmc_memory_read(addr << 2, r);
  73
  74     return r;
  75 }
  76
  77 static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint64_t value,
  78                         unsigned size)
  79 {
  80     MilkymistHpdmcState *s = opaque;
  81
  82     trace_milkymist_hpdmc_memory_write(addr, value);
  83
  84     addr >>= 2;
  85     switch (addr) {
  86     case R_SYSTEM:
  87     case R_BYPASS:
  88     case R_TIMING:
  89         s->regs[addr] = value;
  90         break;
  91     case R_IODELAY:
  92         /* ignore writes */
  93         break;
  94
  95     default:
  96         error_report("milkymist_hpdmc: write access to unknown register 0x"
  97                 TARGET_FMT_plx, addr << 2);
  98         break;
  99     }
 100 }
 101
 102 static const MemoryRegionOps hpdmc_mmio_ops = {
 103     .read = hpdmc_read,
 104     .write = hpdmc_write,
 105     .valid = {
 106         .min_access_size = 4,
 107         .max_access_size = 4,
 108     },
 109     .endianness = DEVICE_NATIVE_ENDIAN,
 110 };
 111
 112 static void milkymist_hpdmc_reset(DeviceState *d)
 113 {
 114     MilkymistHpdmcState *s = container_of(d, MilkymistHpdmcState, busdev.qdev);
 115     int i;
 116
 117     for (i = 0; i < R_MAX; i++) {
 118         s->regs[i] = 0;
 119     }
 120
 121     /* defaults */
 122     s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED
 123                          | IODELAY_PLL2_LOCKED;
 124 }
 125
 126 static int milkymist_hpdmc_init(SysBusDevice *dev)
 127 {
 128     MilkymistHpdmcState *s = FROM_SYSBUS(typeof(*s), dev);
 129
 130     memory_region_init_io(&s->regs_region, &hpdmc_mmio_ops, s,
 131             "milkymist-hpdmc", R_MAX * 4);
 132     sysbus_init_mmio(dev, &s->regs_region);
 133
 134     return 0;
 135 }
 136
 137 static const VMStateDescription vmstate_milkymist_hpdmc = {
 138     .name = "milkymist-hpdmc",
 139     .version_id = 1,
 140     .minimum_version_id = 1,
 141     .minimum_version_id_old = 1,
 142     .fields      = (VMStateField[]) {
 143         VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX),
 144         VMSTATE_END_OF_LIST()
 145     }
 146 };
 147
 148 static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data)
 149 {
 150     DeviceClass *dc = DEVICE_CLASS(klass);
 151     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 152
 153     k->init = milkymist_hpdmc_init;
 154     dc->reset = milkymist_hpdmc_reset;
 155     dc->vmsd = &vmstate_milkymist_hpdmc;
 156 }
 157
 158 static TypeInfo milkymist_hpdmc_info = {
 159     .name          = "milkymist-hpdmc",
 160     .parent        = TYPE_SYS_BUS_DEVICE,
 161     .instance_size = sizeof(MilkymistHpdmcState),
 162     .class_init    = milkymist_hpdmc_class_init,
 163 };
 164
 165 static void milkymist_hpdmc_register_types(void)
 166 {
 167     type_register_static(&milkymist_hpdmc_info);
 168 }
 169
 170 type_init(milkymist_hpdmc_register_types)