4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
31 #include "cpu-common.h"
33 #include <hw/ide/pci.h>
34 #include <hw/ide/ahci.h>
36 /* #define DEBUG_AHCI */
39 #define DPRINTF(port, fmt, ...) \
40 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \
41 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
43 #define DPRINTF(port, fmt, ...) do {} while(0)
46 static void check_cmd(AHCIState *s, int port);
47 static int handle_cmd(AHCIState *s,int port,int slot);
48 static void ahci_reset_port(AHCIState *s, int port);
49 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);
50 static void ahci_init_d2h(AHCIDevice *ad);
52 static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
56 pr = &s->dev[port].port_regs;
62 case PORT_LST_ADDR_HI:
63 val = pr->lst_addr_hi;
68 case PORT_FIS_ADDR_HI:
69 val = pr->fis_addr_hi;
81 val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) |
82 s->dev[port].port.ifs[0].status;
88 if (s->dev[port].port.ifs[0].bs) {
89 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
90 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
92 val = SATA_SCR_SSTATUS_DET_NODEV;
102 pr->scr_act &= ~s->dev[port].finished;
103 s->dev[port].finished = 0;
113 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
118 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
120 struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
122 DPRINTF(0, "raise irq\n");
124 if (msi_enabled(&d->card)) {
125 msi_notify(&d->card, 0);
127 qemu_irq_raise(s->irq);
131 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
133 struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
135 DPRINTF(0, "lower irq\n");
137 if (!msi_enabled(&d->card)) {
138 qemu_irq_lower(s->irq);
142 static void ahci_check_irq(AHCIState *s)
146 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus);
148 for (i = 0; i < s->ports; i++) {
149 AHCIPortRegs *pr = &s->dev[i].port_regs;
150 if (pr->irq_stat & pr->irq_mask) {
151 s->control_regs.irqstatus |= (1 << i);
155 if (s->control_regs.irqstatus &&
156 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
157 ahci_irq_raise(s, NULL);
159 ahci_irq_lower(s, NULL);
163 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
166 DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
167 irq_type, d->port_regs.irq_mask & irq_type);
169 d->port_regs.irq_stat |= irq_type;
173 static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted)
175 target_phys_addr_t len = wanted;
178 cpu_physical_memory_unmap(*ptr, len, 1, len);
181 *ptr = cpu_physical_memory_map(addr, &len, 1);
183 cpu_physical_memory_unmap(*ptr, len, 1, len);
188 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
190 AHCIPortRegs *pr = &s->dev[port].port_regs;
192 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
196 map_page(&s->dev[port].lst,
197 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
198 s->dev[port].cur_cmd = NULL;
200 case PORT_LST_ADDR_HI:
201 pr->lst_addr_hi = val;
202 map_page(&s->dev[port].lst,
203 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
204 s->dev[port].cur_cmd = NULL;
208 map_page(&s->dev[port].res_fis,
209 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
211 case PORT_FIS_ADDR_HI:
212 pr->fis_addr_hi = val;
213 map_page(&s->dev[port].res_fis,
214 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
217 pr->irq_stat &= ~val;
220 pr->irq_mask = val & 0xfdc000ff;
224 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
226 if (pr->cmd & PORT_CMD_START) {
227 pr->cmd |= PORT_CMD_LIST_ON;
230 if (pr->cmd & PORT_CMD_FIS_RX) {
231 pr->cmd |= PORT_CMD_FIS_ON;
234 /* XXX usually the FIS would be pending on the bus here and
235 issuing deferred until the OS enables FIS receival.
236 Instead, we only submit it once - which works in most
237 cases, but is a hack. */
238 if ((pr->cmd & PORT_CMD_FIS_ON) &&
239 !s->dev[port].init_d2h_sent) {
240 ahci_init_d2h(&s->dev[port]);
241 s->dev[port].init_d2h_sent = 1;
247 s->dev[port].port.ifs[0].error = (val >> 8) & 0xff;
248 s->dev[port].port.ifs[0].status = val & 0xff;
257 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
258 ((val & AHCI_SCR_SCTL_DET) == 0)) {
259 ahci_reset_port(s, port);
271 pr->cmd_issue |= val;
279 static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr)
285 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
288 val = s->control_regs.cap;
291 val = s->control_regs.ghc;
294 val = s->control_regs.irqstatus;
296 case HOST_PORTS_IMPL:
297 val = s->control_regs.impl;
300 val = s->control_regs.version;
304 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
305 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
306 (addr < (AHCI_PORT_REGS_START_ADDR +
307 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
308 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
309 addr & AHCI_PORT_ADDR_OFFSET_MASK);
317 static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
322 /* Only aligned reads are allowed on AHCI */
324 fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
325 TARGET_FMT_plx "\n", addr);
329 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
330 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
333 case HOST_CAP: /* R/WO, RO */
334 /* FIXME handle R/WO */
336 case HOST_CTL: /* R/W */
337 if (val & HOST_CTL_RESET) {
338 DPRINTF(-1, "HBA Reset\n");
339 ahci_reset(container_of(s, AHCIPCIState, ahci));
341 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
345 case HOST_IRQ_STAT: /* R/WC, RO */
346 s->control_regs.irqstatus &= ~val;
349 case HOST_PORTS_IMPL: /* R/WO, RO */
350 /* FIXME handle R/WO */
352 case HOST_VERSION: /* RO */
353 /* FIXME report write? */
356 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr);
358 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
359 (addr < (AHCI_PORT_REGS_START_ADDR +
360 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
361 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
362 addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
367 static CPUReadMemoryFunc * const ahci_readfn[3]={
373 static CPUWriteMemoryFunc * const ahci_writefn[3]={
379 static void ahci_reg_init(AHCIState *s)
383 s->control_regs.cap = (s->ports - 1) |
384 (AHCI_NUM_COMMAND_SLOTS << 8) |
385 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
386 HOST_CAP_NCQ | HOST_CAP_AHCI;
388 s->control_regs.impl = (1 << s->ports) - 1;
390 s->control_regs.version = AHCI_VERSION_1_0;
392 for (i = 0; i < s->ports; i++) {
393 s->dev[i].port_state = STATE_RUN;
397 static uint32_t read_from_sglist(uint8_t *buffer, uint32_t len,
401 uint32_t total = 0, once;
402 ScatterGatherEntry *cur_prd;
405 cur_prd = sglist->sg;
406 sgcount = sglist->nsg;
407 for (i = 0; len && sgcount; i++) {
408 once = MIN(cur_prd->len, len);
409 cpu_physical_memory_read(cur_prd->base, buffer, once);
420 static uint32_t write_to_sglist(uint8_t *buffer, uint32_t len,
424 uint32_t total = 0, once;
425 ScatterGatherEntry *cur_prd;
428 DPRINTF(-1, "total: 0x%x bytes\n", len);
430 cur_prd = sglist->sg;
431 sgcount = sglist->nsg;
432 for (i = 0; len && sgcount; i++) {
433 once = MIN(cur_prd->len, len);
434 DPRINTF(-1, "write 0x%x bytes to 0x%lx\n", once, (long)cur_prd->base);
435 cpu_physical_memory_write(cur_prd->base, buffer, once);
446 static void check_cmd(AHCIState *s, int port)
448 AHCIPortRegs *pr = &s->dev[port].port_regs;
451 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {
452 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
453 if ((pr->cmd_issue & (1 << slot)) &&
454 !handle_cmd(s, port, slot)) {
455 pr->cmd_issue &= ~(1 << slot);
461 static void ahci_check_cmd_bh(void *opaque)
463 AHCIDevice *ad = opaque;
465 qemu_bh_delete(ad->check_bh);
468 if ((ad->busy_slot != -1) &&
469 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) {
471 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
475 check_cmd(ad->hba, ad->port_no);
478 static void ahci_init_d2h(AHCIDevice *ad)
480 uint8_t init_fis[0x20];
481 IDEState *ide_state = &ad->port.ifs[0];
483 memset(init_fis, 0, sizeof(init_fis));
488 if (ide_state->drive_kind == IDE_CD) {
489 init_fis[5] = ide_state->lcyl;
490 init_fis[6] = ide_state->hcyl;
493 ahci_write_fis_d2h(ad, init_fis);
496 static void ahci_reset_port(AHCIState *s, int port)
498 AHCIDevice *d = &s->dev[port];
499 AHCIPortRegs *pr = &d->port_regs;
500 IDEState *ide_state = &d->port.ifs[0];
503 DPRINTF(port, "reset port\n");
505 ide_bus_reset(&d->port);
506 ide_state->ncq_queues = AHCI_MAX_CMDS;
515 d->init_d2h_sent = 0;
517 ide_state = &s->dev[port].port.ifs[0];
518 if (!ide_state->bs) {
522 /* reset ncq queue */
523 for (i = 0; i < AHCI_MAX_CMDS; i++) {
524 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];
525 if (!ncq_tfs->used) {
529 if (ncq_tfs->aiocb) {
530 bdrv_aio_cancel(ncq_tfs->aiocb);
531 ncq_tfs->aiocb = NULL;
534 qemu_sglist_destroy(&ncq_tfs->sglist);
538 s->dev[port].port_state = STATE_RUN;
539 if (!ide_state->bs) {
540 s->dev[port].port_regs.sig = 0;
541 ide_state->status = SEEK_STAT | WRERR_STAT;
542 } else if (ide_state->drive_kind == IDE_CD) {
543 s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM;
544 ide_state->lcyl = 0x14;
545 ide_state->hcyl = 0xeb;
546 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl);
547 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
549 s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK;
550 ide_state->status = SEEK_STAT | WRERR_STAT;
553 ide_state->error = 1;
557 static void debug_print_fis(uint8_t *fis, int cmd_len)
562 fprintf(stderr, "fis:");
563 for (i = 0; i < cmd_len; i++) {
564 if ((i & 0xf) == 0) {
565 fprintf(stderr, "\n%02x:",i);
567 fprintf(stderr, "%02x ",fis[i]);
569 fprintf(stderr, "\n");
573 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
575 AHCIPortRegs *pr = &s->dev[port].port_regs;
579 if (!s->dev[port].res_fis ||
580 !(pr->cmd & PORT_CMD_FIS_RX)) {
584 sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS];
585 ide_state = &s->dev[port].port.ifs[0];
588 *(uint32_t*)sdb_fis = 0;
591 sdb_fis[0] = ide_state->error;
592 sdb_fis[2] = ide_state->status & 0x77;
593 s->dev[port].finished |= finished;
594 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished);
596 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS);
599 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis)
601 AHCIPortRegs *pr = &ad->port_regs;
604 target_phys_addr_t cmd_len = 0x80;
607 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
613 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);
614 cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 0);
618 d2h_fis = &ad->res_fis[RES_FIS_RFIS];
621 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
622 d2h_fis[2] = ad->port.ifs[0].status;
623 d2h_fis[3] = ad->port.ifs[0].error;
625 d2h_fis[4] = cmd_fis[4];
626 d2h_fis[5] = cmd_fis[5];
627 d2h_fis[6] = cmd_fis[6];
628 d2h_fis[7] = cmd_fis[7];
629 d2h_fis[8] = cmd_fis[8];
630 d2h_fis[9] = cmd_fis[9];
631 d2h_fis[10] = cmd_fis[10];
632 d2h_fis[11] = cmd_fis[11];
633 d2h_fis[12] = cmd_fis[12];
634 d2h_fis[13] = cmd_fis[13];
635 for (i = 14; i < 0x20; i++) {
639 if (d2h_fis[2] & ERR_STAT) {
640 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_TFES);
643 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);
646 cpu_physical_memory_unmap(cmd_fis, cmd_len, 0, cmd_len);
650 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist)
652 AHCICmdHdr *cmd = ad->cur_cmd;
653 uint32_t opts = le32_to_cpu(cmd->opts);
654 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80;
655 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN;
656 target_phys_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG));
657 target_phys_addr_t real_prdt_len = prdt_len;
662 if (!sglist_alloc_hint) {
663 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);
668 if (!(prdt = cpu_physical_memory_map(prdt_addr, &prdt_len, 0))){
669 DPRINTF(ad->port_no, "map failed\n");
673 if (prdt_len < real_prdt_len) {
674 DPRINTF(ad->port_no, "mapped less than expected\n");
679 /* Get entries in the PRDT, init a qemu sglist accordingly */
680 if (sglist_alloc_hint > 0) {
681 AHCI_SG *tbl = (AHCI_SG *)prdt;
683 qemu_sglist_init(sglist, sglist_alloc_hint);
684 for (i = 0; i < sglist_alloc_hint; i++) {
685 /* flags_size is zero-based */
686 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
687 le32_to_cpu(tbl[i].flags_size) + 1);
692 cpu_physical_memory_unmap(prdt, prdt_len, 0, prdt_len);
696 static void ncq_cb(void *opaque, int ret)
698 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
699 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
701 /* Clear bit for this tag in SActive */
702 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag);
706 ide_state->error = ABRT_ERR;
707 ide_state->status = READY_STAT | ERR_STAT;
708 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag);
710 ide_state->status = READY_STAT | SEEK_STAT;
713 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
714 (1 << ncq_tfs->tag));
716 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n",
719 qemu_sglist_destroy(&ncq_tfs->sglist);
723 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,
726 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;
727 uint8_t tag = ncq_fis->tag >> 3;
728 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag];
731 /* error - already in use */
732 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag);
737 ncq_tfs->drive = &s->dev[port];
738 ncq_tfs->slot = slot;
739 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
740 ((uint64_t)ncq_fis->lba4 << 32) |
741 ((uint64_t)ncq_fis->lba3 << 24) |
742 ((uint64_t)ncq_fis->lba2 << 16) |
743 ((uint64_t)ncq_fis->lba1 << 8) |
744 (uint64_t)ncq_fis->lba0;
746 /* Note: We calculate the sector count, but don't currently rely on it.
747 * The total size of the DMA buffer tells us the transfer size instead. */
748 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) |
749 ncq_fis->sector_count_low;
751 DPRINTF(port, "NCQ transfer LBA from %ld to %ld, drive max %ld\n",
752 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2,
753 s->dev[port].port.ifs[0].nb_sectors - 1);
755 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist);
758 switch(ncq_fis->command) {
759 case READ_FPDMA_QUEUED:
760 DPRINTF(port, "NCQ reading %d sectors from LBA %ld, tag %d\n",
761 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
762 ncq_tfs->is_read = 1;
764 DPRINTF(port, "tag %d aio read %ld\n", ncq_tfs->tag, ncq_tfs->lba);
765 ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs,
766 &ncq_tfs->sglist, ncq_tfs->lba,
769 case WRITE_FPDMA_QUEUED:
770 DPRINTF(port, "NCQ writing %d sectors to LBA %ld, tag %d\n",
771 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
772 ncq_tfs->is_read = 0;
774 DPRINTF(port, "tag %d aio write %ld\n", ncq_tfs->tag, ncq_tfs->lba);
775 ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs,
776 &ncq_tfs->sglist, ncq_tfs->lba,
780 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n");
781 qemu_sglist_destroy(&ncq_tfs->sglist);
786 static int handle_cmd(AHCIState *s, int port, int slot)
793 target_phys_addr_t cmd_len;
795 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
796 /* Engine currently busy, try again later */
797 DPRINTF(port, "engine busy\n");
801 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot];
803 if (!s->dev[port].lst) {
804 DPRINTF(port, "error: lst not given but cmd handled");
808 /* remember current slot handle for later */
809 s->dev[port].cur_cmd = cmd;
811 opts = le32_to_cpu(cmd->opts);
812 tbl_addr = le64_to_cpu(cmd->tbl_addr);
815 cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 1);
818 DPRINTF(port, "error: guest passed us an invalid cmd fis\n");
822 /* The device we are working for */
823 ide_state = &s->dev[port].port.ifs[0];
825 if (!ide_state->bs) {
826 DPRINTF(port, "error: guest accessed unused port");
830 debug_print_fis(cmd_fis, 0x90);
831 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4);
833 switch (cmd_fis[0]) {
834 case SATA_FIS_TYPE_REGISTER_H2D:
837 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
838 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
844 switch (cmd_fis[1]) {
845 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER:
850 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
851 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
857 switch (s->dev[port].port_state) {
859 if (cmd_fis[15] & ATA_SRST) {
860 s->dev[port].port_state = STATE_RESET;
864 if (!(cmd_fis[15] & ATA_SRST)) {
865 ahci_reset_port(s, port);
870 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) {
872 /* Check for NCQ command */
873 if ((cmd_fis[2] == READ_FPDMA_QUEUED) ||
874 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) {
875 process_ncq_command(s, port, cmd_fis, slot);
879 /* Decompose the FIS */
880 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
881 ide_state->feature = cmd_fis[3];
882 if (!ide_state->nsector) {
883 ide_state->nsector = 256;
886 if (ide_state->drive_kind != IDE_CD) {
887 ide_set_sector(ide_state, (cmd_fis[6] << 16) | (cmd_fis[5] << 8) |
891 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
892 * table to ide_state->io_buffer
894 if (opts & AHCI_CMD_ATAPI) {
895 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
896 ide_state->lcyl = 0x14;
897 ide_state->hcyl = 0xeb;
898 debug_print_fis(ide_state->io_buffer, 0x10);
899 ide_state->feature = IDE_FEATURE_DMA;
900 s->dev[port].done_atapi_packet = 0;
901 /* XXX send PIO setup FIS */
904 ide_state->error = 0;
906 /* Reset transferred byte counter */
909 /* We're ready to process the command in FIS byte 2. */
910 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
912 if (s->dev[port].port.ifs[0].status & READY_STAT) {
913 ahci_write_fis_d2h(&s->dev[port], cmd_fis);
918 cpu_physical_memory_unmap(cmd_fis, cmd_len, 1, cmd_len);
920 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
921 /* async command, complete later */
922 s->dev[port].busy_slot = slot;
926 /* done handling the command */
930 /* DMA dev <-> ram */
931 static int ahci_start_transfer(IDEDMA *dma)
933 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
934 IDEState *s = &ad->port.ifs[0];
935 uint32_t size = (uint32_t)(s->data_end - s->data_ptr);
936 /* write == ram -> device */
937 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts);
938 int is_write = opts & AHCI_CMD_WRITE;
939 int is_atapi = opts & AHCI_CMD_ATAPI;
942 if (is_atapi && !ad->done_atapi_packet) {
943 /* already prepopulated iobuffer */
944 ad->done_atapi_packet = 1;
948 if (!ahci_populate_sglist(ad, &s->sg)) {
952 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n",
953 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata",
954 has_sglist ? "" : "o");
956 if (is_write && has_sglist && (s->data_ptr < s->data_end)) {
957 read_from_sglist(s->data_ptr, size, &s->sg);
960 if (!is_write && has_sglist && (s->data_ptr < s->data_end)) {
961 write_to_sglist(s->data_ptr, size, &s->sg);
964 /* update number of transferred bytes */
965 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size);
968 /* declare that we processed everything */
969 s->data_ptr = s->data_end;
972 qemu_sglist_destroy(&s->sg);
975 s->end_transfer_func(s);
977 if (!(s->status & DRQ_STAT)) {
979 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS);
985 static void ahci_start_dma(IDEDMA *dma, IDEState *s,
986 BlockDriverCompletionFunc *dma_cb)
988 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
990 DPRINTF(ad->port_no, "\n");
992 ad->dma_status |= BM_STATUS_DMAING;
996 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write)
998 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
999 IDEState *s = &ad->port.ifs[0];
1002 ahci_populate_sglist(ad, &s->sg);
1004 s->io_buffer_size = 0;
1005 for (i = 0; i < s->sg.nsg; i++) {
1006 s->io_buffer_size += s->sg.sg[i].len;
1009 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size);
1010 return s->io_buffer_size != 0;
1013 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write)
1015 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1016 IDEState *s = &ad->port.ifs[0];
1017 uint8_t *p = s->io_buffer + s->io_buffer_index;
1018 int l = s->io_buffer_size - s->io_buffer_index;
1020 if (ahci_populate_sglist(ad, &s->sg)) {
1025 write_to_sglist(p, l, &s->sg);
1027 read_from_sglist(p, l, &s->sg);
1030 /* update number of transferred bytes */
1031 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l);
1032 s->io_buffer_index += l;
1034 DPRINTF(ad->port_no, "len=%#x\n", l);
1039 static int ahci_dma_set_unit(IDEDMA *dma, int unit)
1041 /* only a single unit per link */
1045 static int ahci_dma_add_status(IDEDMA *dma, int status)
1047 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1048 ad->dma_status |= status;
1049 DPRINTF(ad->port_no, "set status: %x\n", status);
1051 if (status & BM_STATUS_INT) {
1052 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS);
1058 static int ahci_dma_set_inactive(IDEDMA *dma)
1060 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1062 DPRINTF(ad->port_no, "dma done\n");
1064 /* update d2h status */
1065 ahci_write_fis_d2h(ad, NULL);
1069 /* maybe we still have something to process, check later */
1070 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad);
1071 qemu_bh_schedule(ad->check_bh);
1076 static void ahci_irq_set(void *opaque, int n, int level)
1080 static void ahci_dma_restart_cb(void *opaque, int running, int reason)
1084 static int ahci_dma_reset(IDEDMA *dma)
1089 static const IDEDMAOps ahci_dma_ops = {
1090 .start_dma = ahci_start_dma,
1091 .start_transfer = ahci_start_transfer,
1092 .prepare_buf = ahci_dma_prepare_buf,
1093 .rw_buf = ahci_dma_rw_buf,
1094 .set_unit = ahci_dma_set_unit,
1095 .add_status = ahci_dma_add_status,
1096 .set_inactive = ahci_dma_set_inactive,
1097 .restart_cb = ahci_dma_restart_cb,
1098 .reset = ahci_dma_reset,
1101 void ahci_init(AHCIState *s, DeviceState *qdev, int ports)
1107 s->dev = qemu_mallocz(sizeof(AHCIDevice) * ports);
1109 s->mem = cpu_register_io_memory(ahci_readfn, ahci_writefn, s,
1110 DEVICE_LITTLE_ENDIAN);
1111 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1113 for (i = 0; i < s->ports; i++) {
1114 AHCIDevice *ad = &s->dev[i];
1116 ide_bus_new(&ad->port, qdev, i);
1117 ide_init2(&ad->port, irqs[i]);
1121 ad->port.dma = &ad->dma;
1122 ad->port.dma->ops = &ahci_dma_ops;
1123 ad->port_regs.cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
1127 void ahci_uninit(AHCIState *s)
1132 void ahci_pci_map(PCIDevice *pci_dev, int region_num,
1133 pcibus_t addr, pcibus_t size, int type)
1135 struct AHCIPCIState *d = (struct AHCIPCIState *)pci_dev;
1136 AHCIState *s = &d->ahci;
1138 cpu_register_physical_memory(addr, size, s->mem);
1141 void ahci_reset(void *opaque)
1143 struct AHCIPCIState *d = opaque;
1146 d->ahci.control_regs.irqstatus = 0;
1147 d->ahci.control_regs.ghc = 0;
1149 for (i = 0; i < d->ahci.ports; i++) {
1150 ahci_reset_port(&d->ahci, i);