arm: sc8830: remove the unused defined values 69/153269/3
authorJaehoon Chung <jh80.chung@samsung.com>
Thu, 28 Sep 2017 06:18:27 +0000 (15:18 +0900)
committerSeung-Woo Kim <sw0312.kim@samsung.com>
Fri, 29 Sep 2017 09:58:06 +0000 (18:58 +0900)
Remove the unused defined values for fixing compiler warning.
BIT_GPU_SOFT_RST doesn't use anywhere.

Change-Id: I17102a64b4cb61d32f155bf697f325cb537f912f
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
arch/arm/include/asm/arch-sc8830/chip_x30g/__regs_gpu_apb_rf.h
arch/arm/include/asm/arch-sc8830/chip_x30g/__regs_pmu_apb.h
arch/arm/include/asm/arch-sc8830/chip_x30g/__regs_pmu_apb_tshark2.h
arch/arm/include/asm/arch-sc8830/chip_x35/sprd_reg_gpu_apb.h
arch/arm/include/asm/arch-sc8830/chip_x35/sprd_reg_pmu_apb.h

index dd4983b..15bb144 100644 (file)
@@ -24,9 +24,6 @@
 \r
 \r
 \r
-/* bits definitions for register REG_GPU_APB_RF_APB_RST */\r
-#define BIT_GPU_SOFT_RST                                  ( BIT(0) )\r
-\r
 /* bits definitions for register REG_GPU_APB_RF_APB_CLK_CTRL */\r
 #define BITS_CLK_GPU_DIV(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)) )\r
 #define BITS_CLK_GPU_SEL(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )\r
index 5275918..e2ef94f 100644 (file)
 /* bits definitions for register REG_PMU_APB_CP_SOFT_RST */\r
 #define BIT_PUB_SOFT_RST                                  ( BIT(6) )\r
 #define BIT_AP_SOFT_RST                                   ( BIT(5) )\r
-#define BIT_GPU_SOFT_RST                                  ( BIT(4) )\r
 #define BIT_MM_SOFT_RST                                   ( BIT(3) )\r
 #define BIT_CP2_SOFT_RST                                  ( BIT(2) )\r
 #define BIT_CP1_SOFT_RST                                  ( BIT(1) )\r
index b957621..e11a4b9 100644 (file)
 #define BIT_CODEC_SOFT_RST                                     (BIT(7))
 #define BIT_PUB_SOFT_RST                                       (BIT(6))
 #define BIT_AP_SOFT_RST                                                (BIT(5))
-#define BIT_GPU_SOFT_RST                                       (BIT(4))
 #define BIT_MM_SOFT_RST                                                (BIT(3))
 #define BIT_CP2_SOFT_RST                                       (BIT(2))
 #define BIT_CP1_SOFT_RST                                       (BIT(1))
index 22dbd30..7ead4fd 100644 (file)
@@ -17,9 +17,6 @@
 #define REG_GPU_APB_APB_RST             SCI_ADDR(REGS_GPU_APB_BASE, 0x0000)
 #define REG_GPU_APB_APB_CLK_CTRL        SCI_ADDR(REGS_GPU_APB_BASE, 0x0004)
 
-/* bits definitions for register REG_GPU_APB_APB_RST */
-#define BIT_GPU_SOFT_RST                ( BIT(0) )
-
 /* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */
 #define BITS_CLK_GPU_DIV(_x_)           ( (_x_) << 2 & (BIT(2)|BIT(3)) )
 #define BITS_CLK_GPU_SEL(_x_)           ( (_x_) << 0 & (BIT(0)|BIT(1)) )
index aa24a24..2dbc0e8 100644 (file)
 /* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
 #define BIT_PUB_SOFT_RST                ( BIT(6) )
 #define BIT_AP_SOFT_RST                 ( BIT(5) )
-#define BIT_GPU_SOFT_RST                ( BIT(4) )
 #define BIT_MM_SOFT_RST                 ( BIT(3) )
 #define BIT_CP2_SOFT_RST                ( BIT(2) )
 #define BIT_CP1_SOFT_RST                ( BIT(1) )