2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
24 #define CONFIG_FDL2_PRINT 0
25 #define BOOT_NATIVE_LINUX 1
26 #define BOOT_NATIVE_LINUX_MODEM 1
27 #define CALIBRATION_FLAG 0x89FFFC00
28 #define CALIBRATION_FLAG_WCDMA 0x89FFFC00
29 #define CONFIG_SILENT_CONSOLE
30 #define CONFIG_GPIOLIB 1
33 #define CONFIG_SDRAMDISK
35 #define U_BOOT_SPRD_VER 1
36 /*#define SPRD_EVM_TAG_ON 1*/
37 #ifdef SPRD_EVM_TAG_ON
38 #define SPRD_EVM_ADDR_START 0x00026000
39 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
41 #define CONFIG_L2_OFF 1
45 #define CONFIG_YAFFS2 1
47 #define BOOT_PART "boot"
48 //#define BOOT_PART "kernel"
49 #define RECOVERY_PART "recovery"
50 #define UBIPAC_PART "ubipac"
53 * SPREADTRUM BIGPHONE board - SoC Configuration
56 #define CONFIG_SPX15_WCDMA
59 #define CONFIG_AUTODLOADER
60 #define CONFIG_SP8830WCN
62 #define CHIP_ENDIAN_LITTLE
63 #define _LITTLE_ENDIAN 1
65 #define CONFIG_RAM512M
67 //#define CONFIG_EMMC_BOOT
69 #ifdef CONFIG_EMMC_BOOT
70 #define EMMC_SECTOR_SIZE 512
73 #define CONFIG_FS_EXT4
74 #define CONFIG_EXT4_WRITE
75 #define CONFIG_CMD_EXT4
76 #define CONFIG_CMD_EXT4_WRITE
78 //#define CONFIG_TIGER_MMC
79 #define CONFIG_UEFI_PARTITION
80 #define CONFIG_EFI_PARTITION
81 #define CONFIG_EXT4_SPARSE_DOWNLOAD
82 //#define CONFIG_EMMC_SPL
83 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
89 #define CONFIG_CMD_MMC
91 #define CONFIG_CMD_FAT 1
92 #define CONFIG_FAT_WRITE 1
94 #define CONFIG_GENERIC_MMC 1
95 #define CONFIG_SDHCI 1
96 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
97 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
98 #define CONFIG_MMC_SDMA 1
99 #define CONFIG_MV_SDHCI 1
100 #define CONFIG_DOS_PARTITION 1
101 #define CONFIG_EFI_PARTITION 1
102 #define CONFIG_SYS_MMC_NUM 1
103 #define CONFIG_SYS_MMC_BASE {0x20600000}
104 #define CONFIG_SYS_SD_BASE 0x20300000
107 #define BB_DRAM_TYPE_256MB_32BIT
109 #define CONFIG_SYS_HZ 1000
110 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
112 //#define CONFIG_SYS_HUSH_PARSER
114 #ifdef CONFIG_SYS_HUSH_PARSER
115 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
118 #define FIXNV_SIZE (256 * 1024)
119 #define MODEM_SIZE (0x800000)
120 #define DSP_SIZE (0x200000) /* 3968K */
121 #define WCNMODEM_SIZE (0x100000)
122 #define VMJALUNA_SIZE (0x64000) /* 400K */
123 #define RUNTIMENV_SIZE (384 * 1024)
124 #define CONFIG_SPL_LOAD_LEN (0x6000)
127 /*#define CMDLINE_NEED_CONV */
129 #define WATCHDOG_LOAD_VALUE 0x4000
130 #define CONFIG_SYS_STACK_SIZE 0x400
131 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
133 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
135 /* NAND BOOT is the only boot method */
136 #define CONFIG_NAND_U_BOOT
137 #define DYNAMIC_CRC_TABLE
138 /* Start copying real U-boot from the second page */
139 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
140 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x8A000
141 #define RAM_TYPPE_IS_SDRAM 0
142 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
144 /* Load U-Boot to this address */
145 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
146 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
147 #define CONFIG_SYS_SDRAM_BASE 0x80000000
148 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
150 #ifdef CONFIG_NAND_SPL
151 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
154 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
155 #define CONFIG_SYS_INIT_SP_ADDR \
156 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
158 #define CONFIG_SKIP_LOWLEVEL_INIT
161 #define CONFIG_HW_WATCHDOG
162 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
163 //#define CONFIG_DISPLAY_CPUINFO
165 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
166 #define CONFIG_SETUP_MEMORY_TAGS 1
167 #define CONFIG_INITRD_TAG 1
173 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
175 * Board has 2 32MB banks of DRAM but there is a bug when using
176 * both so only the first is configured
178 #define CONFIG_NR_DRAM_BANKS 1
180 #define PHYS_SDRAM_1 0x80000000
181 #define PHYS_SDRAM_1_SIZE 0x10000000
182 #if (CONFIG_NR_DRAM_BANKS == 2)
183 #define PHYS_SDRAM_2 0x90000000
184 #define PHYS_SDRAM_2_SIZE 0x10000000
187 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
188 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
189 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
194 #define CONFIG_SPRD_UART 1
195 #define CONFIG_SYS_SC8800X_UART1 1
196 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
197 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
198 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
199 #define CONFIG_SPRD_SPI
200 #define CONFIG_SPRD_I2C
201 #define CONFIG_SC8830_I2C
203 * Flash & Environment
205 /* No NOR flash present */
206 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
207 #define CONFIG_SYS_NO_FLASH 1
208 #define CONFIG_ENV_IS_NOWHERE
209 #define CONFIG_ENV_SIZE (128 * 1024)
211 #define CONFIG_ENV_IS_IN_NAND
212 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
213 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
217 #define CONFIG_CLK_PARA
218 //#define CONFIG_FPGA
220 #ifndef CONFIG_CLK_PARA
223 #define MAGIC_HEADER 0x5555AAAA
224 #define MAGIC_END 0xAAAA5555
225 #define CONFIG_PARA_VERSION 1
226 #define CLK_CA7_CORE ARM_CLK_1000M
227 #define CLK_CA7_AXI ARM_CLK_500M
228 #define CLK_CA7_DGB ARM_CLK_200M
229 #define CLK_CA7_AHB AHB_CLK_192M
230 #define CLK_CA7_APB APB_CLK_64M
231 #define CLK_PUB_AHB PUB_AHB_CLK_153_6M
232 #define CLK_AON_APB AON_APB_CLK_128M
233 #define DDR_FREQ 333000000
234 #define DCDC_ARM 1200
235 #define DCDC_CORE 1100
236 #define CONFIG_VOL_PARA
238 //---these three macro below,only one can be open
243 //#define DDR_TYPE DRAM_LPDDR2_2CS_8G_X32
244 #define DDR_TYPE DRAM_LPDDR2_1CS_4G_X32
245 //#define DDR_TYPE DRAM_LPDDR2_1CS_8G_X32
246 //#define DDR_TYPE DRAM_LPDDR2_2CS_16G_X32
247 //#define DDR_TYPE DRAM_DDR3_1CS_2G_X8_4P
248 //#define DDR_TYPE DRAM_DDR3_1CS_4G_X16_2P
250 #define DDR3_DLL_ON TRUE
252 #define DDR_APB_CLK 128
253 //#define DDR_DFS_SUPPORT
254 #define DDR_DFS_VAL_BASE 0X1c00
256 //#define DDR_SCAN_SUPPORT
257 #define MEM_IO_DS LPDDR2_DS_40R
259 #define PUBL_LPDDR1_DS PUBL_LPDDR1_DS_48OHM
260 #define PUBL_LPDDR2_DS PUBL_LPDDR2_DS_40OHM
261 #define PUBL_DDR3_DS PUBL_DDR3_DS_34OHM
264 #define CONFIG_NAND_DOLPHIN
265 #define CONFIG_SPRD_NAND_REGS_BASE (0x20B00000)
266 #define CONFIG_SYS_MAX_NAND_DEVICE 1
267 #define CONFIG_SYS_NAND_BASE (0x20B00000)
268 //#define CONFIG_JFFS2_NAND
269 //#define CONFIG_SPRD_NAND_HWECC
270 #define CONFIG_SYS_NAND_HW_ECC
271 #define CONFIG_SYS_NAND_LARGEPAGE
272 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
274 #define CONFIG_SYS_64BIT_VSPRINTF
276 #define CONFIG_CMD_MTDPARTS
277 #define CONFIG_MTD_PARTITIONS
278 #define CONFIG_MTD_DEVICE
279 #define CONFIG_CMD_UBI
280 #define CONFIG_RBTREE
281 #define CONFIG_CMD_UBIFS
283 #ifdef CONFIG_CMD_UBIFS
284 #define CONFIG_FS_UBIFS
286 /* U-Boot general configuration */
287 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
288 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
289 /* Print buffer sz */
290 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
291 sizeof(CONFIG_SYS_PROMPT) + 16)
292 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
293 /* Boot Argument Buffer Size */
294 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
295 #define CONFIG_CMDLINE_EDITING
296 #define CONFIG_SYS_LONGHELP
298 /* support OS choose */
299 #undef CONFIG_BOOTM_NETBSD
300 #undef CONFIG_BOOTM_RTEMS
302 /* U-Boot commands */
303 #include <config_cmd_default.h>
304 #define CONFIG_CMD_NAND
305 #undef CONFIG_CMD_FPGA
306 #undef CONFIG_CMD_LOADS
307 #undef CONFIG_CMD_NET
308 #undef CONFIG_CMD_NFS
309 #undef CONFIG_CMD_SETGETDCR
311 #define CONFIG_ENV_OVERWRITE
313 #ifdef SPRD_EVM_TAG_ON
314 #define CONFIG_BOOTDELAY 0
316 #define CONFIG_BOOTDELAY 0
317 #define CONFIG_ZERO_BOOTDELAY_CHECK
320 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
321 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
323 #define xstr(s) str(s)
326 #define MTDIDS_DEFAULT "nand0=sprd-nand"
327 //#define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),2m(2ndbl),256k(tdmodem),256k(tddsp),256k(tdfixnv1),256k(tdruntimenv),256k(wmodem),256k(wdsp),256k(wfixnv1),256k(wruntimenv1),256k(prodinfo1),256k(prodinfo3),1024k(logo),1024k(fastbootlogo),10m(boot),300m(system),150m(cache),10m(recovery),256k(misc),256k(sd),512k(userdata)"
328 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),768k(2ndbl),512k(kpanic),-(ubipac)"
329 #define CONFIG_BOOTARGS "mem=512M loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
330 #define COPY_LINUX_KERNEL_SIZE (0x600000)
331 #define LINUX_INITRD_NAME "modem"
333 #define CONFIG_BOOTCOMMAND "cboot normal"
334 #define CONFIG_EXTRA_ENV_SETTINGS ""
336 #ifdef CONFIG_CMD_NET
337 #define CONFIG_IPADDR 192.168.10.2
338 #define CONFIG_SERVERIP 192.168.10.5
339 #define CONFIG_NETMASK 255.255.255.0
340 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
341 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
344 #define CONFIG_NET_MULTI
345 #define CONFIG_CMD_DNS
346 #define CONFIG_CMD_NFS
347 #define CONFIG_CMD_RARP
348 #define CONFIG_CMD_PING
349 /*#define CONFIG_CMD_SNTP */
352 #define CONFIG_USB_CORE_IP_293A
353 #define CONFIG_USB_GADGET_SC8800G
354 #define CONFIG_USB_DWC
355 #define CONFIG_USB_GADGET_DUALSPEED
356 //#define CONFIG_USB_ETHER
357 #define CONFIG_CMD_FASTBOOT
358 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
359 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
360 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
361 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
363 #define CONFIG_MODEM_CALIBERATE
367 #define CONFIG_SPLASH_SCREEN
368 #define LCD_BPP LCD_COLOR16
369 //#define CONFIG_LCD_HVGA 1
370 //#define CONFIG_LCD_QVGA 1
371 //#define CONFIG_LCD_QHD 1
372 //#define CONFIG_LCD_720P 1
373 #define CONFIG_LCD_FWVGA 1
375 //#define CONFIG_LCD_INFO
376 //#define LCD_TEST_PATTERN
377 //#define CONFIG_LCD_LOGO
378 //#define CONFIG_FB_LCD_S6D0139
379 //#define CONFIG_FB_LCD_SSD2075_MIPI
380 //#define CONFIG_FB_LCD_NT35516_MIPI
381 #define CONFIG_FB_LCD_HX8363_RGB_SPI
382 //#define CONFIG_FB_LCD_HX8363_MCU
384 #define CONFIG_SYS_WHITE_ON_BLACK
385 #ifdef LCD_TEST_PATTERN
386 #define CONSOLE_COLOR_RED 0xf800
387 #define CONSOLE_COLOR_GREEN 0x07e0
388 #define CONSOLE_COLOR_YELLOW 0x07e0
389 #define CONSOLE_COLOR_BLUE 0x001f
390 #define CONSOLE_COLOR_MAGENTA 0x001f
391 #define CONSOLE_COLOR_CYAN 0x001f
395 #define CONFIG_SPRD_SYSDUMP
396 #include <asm/sizes.h>
397 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
398 #define CALIBRATE_ENUM_MS 3000
399 #define CALIBRATE_IO_MS 2000
401 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
402 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
403 #define LOW_BAT_VOL_CHG 3200 //3.3V charger connect
405 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
406 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
408 #define PHYS_OFFSET_ADDR 0x80000000
409 #define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
410 #define TD_CP_SDRAM_SIZE 0x1800000 /*24M*/
411 #define WCDMA_CP_OFFSET_ADDR 0x8000000 /*128M*/
412 #define WCDMA_CP_SDRAM_SIZE 0x2000000 /*32M*/
414 #define WCN_CP_OFFSET_ADDR 0xa800000 /*168M*/
415 #define WCN_CP_SDRAM_SIZE 0x500000 /*5M*/
417 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
418 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
419 #define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE)
420 #define SIPC_WCN_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCN_CP_OFFSET_ADDR + WCN_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE)
422 //#define CALIBRATION_FLAG 0x89700000
424 #define CONFIG_CMD_SOUND 1
425 #define CONFIG_CMD_FOR_HTC 1
426 #define CONFIG_SOUND_CODEC_SPRD_V3 1
427 #define CONFIG_SOUND_DAI_VBC_R2P0 1
428 /* #define CONFIG_SPRD_AUDIO_DEBUG */
430 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
432 #define CONFIG_PBINT_7S_RESET_V1
433 /* short reset when power key reset trigged */
434 #define CONFIG_PBINT_7S_RST_SW_SHORT 1
435 /* reset then release the power key when reset trigged */
436 /* #define CONFIG_PBINT_7S_RST_SW_LONG 1 */
437 /* reset then release the power key when reset trigged */
438 /* #define CONFIG_PBINT_7S_RST_HW_LONG 1 */
439 /* rang:2-16 unit: s */
440 /* #define CONFIG_PBINT_7S_RST_THRESHOLD 7 */
442 /* #define CONFIG_SMPL_MODE */
443 /* rang:0(0.5s) - 7(4s) unit: s step: 0.5s */
444 /* #define CONFIG_SMPL_THRESHOLD 0 */
446 #endif /* __CONFIG_H */