drivers/yp_mmc/sdio_sc8830.h

   1 /*********************************************************************\r
   2  ** File Name:          sdio_phy.h\r
   3  ** Author:                     yanping.xie\r
   4  ** DATE:                       09/05/2013\r
   5  ** Copyright:                  2004 Spreadtrum, Incoporated. All Rights Reserved.\r
   6  ** Description:                This file describe operation of sdio host.\r
   7  *********************************************************************\r
   8
   9  *********************************************************************\r
  10  **                               Edit History                                                                                   **\r
  11  ** ------------------------------------------------------------------------- **\r
  12  ** DATE                                NAME                            DESCRIPTION\r
  13  ** 09/09/2013          ypxie                           Create.\r
  14  ********************************************************************/\r
  15 #ifndef __SDIO_CHIP_H_\r
  16 #define __SDIO_CHIP_H_\r
  17 \r
  18 /* sdio register base address */\r
  19 #define SLOT0_BASE_ADDR                                 CTL_BASE_SDIO0\r
  20 #define SLOT1_BASE_ADDR                                 (CTL_BASE_SDIO0 + 0x0100)\r
  21 #define SLOT2_BASE_ADDR                                 0                                       /* not support */\r
  22 #define SLOT3_BASE_ADDR                                 CTL_BASE_SDIO1\r
  23 #define SLOT4_BASE_ADDR                                 (CTL_BASE_SDIO1 + 0x0100)\r
  24 #define SLOT5_BASE_ADDR                                 (CTL_BASE_SDIO1 + 0x0200)\r
  25 #define SLOT6_BASE_ADDR                                 CTL_BASE_SDIO2\r
  26 #define SLOT7_BASE_ADDR                                 (CTL_BASE_SDIO2 + 0x0100)\r
  27 #define SLOT8_BASE_ADDR                                 (CTL_BASE_SDIO2 + 0x0200)\r
  28 #define SLOT9_BASE_ADDR                                 CTL_BASE_EMMC\r
  29 #define SLOT10_BASE_ADDR                                (CTL_BASE_SDIO2 + 0x0100)\r
  30 #define SLOT11_BASE_ADDR                                0                                       /* not support */\r
  31 \r
  32 /* sdio controller version information */\r
  33 #define SDIO_20                                                 20\r
  34 #define SDIO_30                                                 30\r
  35 \r
  36 #define SDIO0_VER                                               SDIO_30\r
  37 #define SDIO1_VER                                               SDIO_20\r
  38 #define SDIO2_VER                                               SDIO_20\r
  39 #define SDIO3_VER                                               SDIO_30\r
  40 \r
  41 /* sdio slot register */\r
  42 #define AHB_SDIO_CTRL                                   (SPRD_AHB_PHYS + 0x0018)\r
  43 \r
  44 #define SLOT0_SEL                                               & (~BIT_16)\r
  45 #define SLOT1_SEL                                               | BIT_16\r
  46 #define SLOT2_SEL                                               & 0                                     /* not support */\r
  47 #define SLOT3_SEL                                               & (~(BIT_1 | BIT_0))\r
  48 #define SLOT4_SEL                                               (REG32(AHB_SDIO_CTRL) & (~BIT_1)) | BIT_0\r
  49 #define SLOT5_SEL                                               (REG32(AHB_SDIO_CTRL) & (~BIT_0)) | BIT_1\r
  50 #define SLOT6_SEL                                               & (~(BIT_3 | BIT_2))\r
  51 #define SLOT7_SEL                                               (REG32(AHB_SDIO_CTRL) & (~BIT_3)) | BIT_2\r
  52 #define SLOT8_SEL                                               (REG32(AHB_SDIO_CTRL) & (~BIT_2)) | BIT_3\r
  53 #define SLOT9_SEL                                               & (~BIT_17)\r
  54 #define SLOT10_SEL                                              | BIT_17\r
  55 #define SLOT11_SEL                                              & 0                                     /* not support */\r
  56 \r
  57 /* sdio ahb clock enable : 0x20D00000*/\r
  58 /* AHB_EB */\r
  59 /* AHB_SOFT_RST */\r
  60 /* sdio ahb base clock select */\r
  61 /* REG_AP_CLK_SDIO0_CFG */\r
  62 /* REG_AP_CLK_SDIO1_CFG */\r
  63 /* REG_AP_CLK_SDIO2_CFG */\r
  64 /* REG_AP_CLK_EMMC_CFG */\r
  65 /* sdio ahb power on or off */\r
  66 /* sdio ahb power sel */\r
  67 typedef struct\r
  68 {\r
  69         uint32                                                          val;\r
  70         uint32                                                          set_val;\r
  71 } sel_info_t;\r
  72 \r
  73 typedef struct\r
  74 {\r
  75 /* power enable info */\r
  76         uint32                                                          pd_set;\r
  77         uint32                                                          pd_set_bit;\r
  78         uint32                                                          pd_clr;\r
  79         uint32                                                          pd_clr_bit;\r
  80 /* power select info */\r
  81         uint32                                                          pwr_sel_reg;\r
  82         uint32                                                          pwr_mask;\r
  83         uint32                                                          pwr_shft;\r
  84         sel_info_t                                                              pwr_sel[4];\r
  85 } sdio_pwr_info_t;\r
  86 \r
  87 typedef struct\r
  88 {\r
  89         uint32                                                          sdio_index;\r
  90 /* enable clock reigster info */\r
  91         uint32                                                          ahb_en;\r
  92         uint32                                                          ahb_en_bit;\r
  93 /* reset clock reigster info */\r
  94         uint32                                                          ahb_rst;\r
  95         uint32                                                          ahb_rst_bit;\r
  96 /* base clock reigster info */\r
  97         uint32                                                          clk_reg;\r
  98         uint32                                                          clk_mask;\r
  99         uint32                                                          clk_shft;\r
 100         sel_info_t                                                              clk_sel[4];\r
 101 \r
 102         sdio_pwr_info_t                                         pwr_io;\r
 103         sdio_pwr_info_t                                         pwr_core;\r
 104 } sdio_base_info_t;\r
 105 \r
 106 LOCAL const sdio_base_info_t sdio_resource_detail[]=\r
 107 {\r
 108 /*\r
 109         {sdio_index, ahb_en, ahb_en_bit, ahb_rst, ahb_rst_bit, clk_reg, clk_mask\r
 110                 , clk_shft, val, step, val, step, val, step, val, step\r
 111                 , pd_set, pd_set_bit\r
 112                 , pd_clr, pd_clr_bit\r
 113                 , pwr_sel_reg, pwr_mask\r
 114                 , pwr_shft, val, step, val, step, val, step, val, step\r
 115                 , pd_set, pd_set_bit\r
 116                 , pd_clr, pd_clr_bit\r
 117                 , pwr_sel, pwr_mask\r
 118                 , pwr_shft, val, step, val, step, val, step, val, step },\r
 119 */\r
 120         {0, AHB_EB, BIT_8, AHB_SOFT_RST, BIT_11,REG_AP_CLK_SDIO0_CFG, (BIT_1 | BIT_0)\r
 121                 , 0, 26000000, 0x00, 192000000, 0x01, 256000000, 0x02, 312000000, 0x03\r
 122                 , ANA_REG_GLB_LDO_PD_CTRL, BIT_1\r
 123                 , 0, 0\r
 124                 , ANA_REG_GLB_LDO_V_CTRL1, (BIT_3 | BIT_2)\r
 125                 , 2, 2800, 0x00, 3000, 0x01, 2500, 0x02, 1800, 0x03\r
 126                 , 0, 0\r
 127                 , 0, 0\r
 128                 , 0, 0\r
 129                 , 0, 0, 0, 0, 0, 0, 0, 0, 0 },\r
 130 \r
 131         {1, AHB_EB, BIT_9, AHB_SOFT_RST, BIT_12,REG_AP_CLK_SDIO1_CFG, (BIT_1 | BIT_0)\r
 132                 , 0, 48000000, 0x00, 76800000, 0x01, 96000000, 0x02, 128000000, 0x03\r
 133                 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_1                 /* used vdd18 */\r
 134                 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_1\r
 135                 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_1 | BIT_0)\r
 136                 , 0x00, 1500, 0x00, 1800, 0x01, 1300, 0x02, 1200, 0x03\r
 137                 , 0, 0\r
 138                 , 0, 0\r
 139                 , 0, 0\r
 140                 , 0, 0, 0, 0, 0, 0, 0, 0, 0 },\r
 141         {2, AHB_EB, BIT_10, AHB_SOFT_RST, BIT_13,REG_AP_CLK_SDIO2_CFG, (BIT_1 | BIT_0)\r
 142                 , 0, 48000000, 0x00, 76800000, 0x01, 96000000, 0x02, 128000000, 0x03\r
 143                 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_1                 /* used vdd18 */\r
 144                 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_1\r
 145                 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_1 | BIT_0)\r
 146                 , 0x00, 1500, 0x00, 1800, 0x01, 1300, 0x02, 1200, 0x03\r
 147                 , 0, 0\r
 148                 , 0, 0\r
 149                 , 0, 0\r
 150                 , 0, 0, 0, 0, 0, 0, 0, 0, 0 },\r
 151         {3, AHB_EB, BIT_11, AHB_SOFT_RST, BIT_14,REG_AP_CLK_EMMC_CFG, (BIT_1 | BIT_0)\r
 152                 , 0, 26000000, 0x00, 192000000, 0x01, 256000000, 0x02, 312000000, 0x03\r
 153                 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_7\r
 154                 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_7\r
 155                 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_13 | BIT_12)\r
 156                 , 12, 1500, 0x00, 1800, 0x01, 1300, 0x02, 1200, 0x03\r
 157                 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_8\r
 158                 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_8\r
 159                 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_15 | BIT_14)\r
 160                 , 14, 2800, 0x00, 3000, 0x01, 2500, 0x02, 1800, 0x03 },\r
 161 };\r
 162 \r
 163 #endif /* __SDIO_CHIP_H_ */