2 * drivers/video/sprdfb/lcd/lcd_ili6150_lvds.c
4 * Copyright (C) 2014 Spreadtrum Communications Inc.
6 * Author: Haibing.Yang <haibing.yang@spreadtrum.com>
12 #include <asm/arch/sprd_lcd.h>
13 #include <asm/arch/dispc_reg.h>
17 #define GPIO_BASE_ADDR 0x40280000
18 #define GPIO_LVDSCHIP_OFFSET 0x480
24 #define GPIO_SCK_BIT BIT(6)
25 #define GPIO_CS_BIT BIT(7)
26 #define GPIO_SDI_BIT BIT(8)
28 #define GPIO_SPI_SCK_PIN 6
29 #define GPIO_SPI_CS_PIN 7
30 #define GPIO_SPI_SDI_PIN 8
34 struct gpio_ctrl_reg {
35 volatile uint32 data; /* bits data */
36 volatile uint32 msk; /* bits data mask */
37 volatile uint32 dir; /* bits data direction */
38 volatile uint32 is; /* bits interrupt sense */
39 volatile uint32 ibe; /* bits both edges interrupt */
40 volatile uint32 iev; /* bits interrupt event */
41 volatile uint32 ie; /* bits interrupt enable */
42 volatile uint32 ris; /* bits raw interrupt status */
43 volatile uint32 mis; /* bits masked interrupt status */
44 volatile uint32 inen; /* input enable */
47 static int gpio_spi_write(uint32 index, uint8 len_i, uint32 data, uint8 len_d)
50 volatile struct gpio_ctrl_reg *regs =
51 (volatile struct gpio_ctrl_reg *)
52 (GPIO_BASE_ADDR + GPIO_LVDSCHIP_OFFSET);
55 regs->msk = GPIO_SCK_BIT | GPIO_CS_BIT | GPIO_SDI_BIT;
56 regs->dir = GPIO_SCK_BIT | GPIO_CS_BIT | GPIO_SDI_BIT;
57 regs->data = GPIO_SCK_BIT | GPIO_CS_BIT;
59 /* Bit[7] output 1, CS Enable */
60 reg_val = GPIO_CS_BIT;
68 for (i = 0; i < len_d; ++i) {
71 reg_val = ((data >> (len_d - i -1)) << GPIO_SPI_SDI_PIN) & GPIO_SDI_BIT;
74 /* High clock to set bit */
75 regs->data |= GPIO_SCK_BIT;
80 for (i = 0; i < len_i; ++i) {
83 reg_val = ((index >> (len_i - i -1)) << GPIO_SPI_SDI_PIN) & GPIO_SDI_BIT;
86 /* High clock to set bit */
87 regs->data |= GPIO_SCK_BIT;
93 regs->data |= GPIO_CS_BIT;
95 regs->data |= GPIO_SCK_BIT;
96 udelay(DELAY_CNT * 20);
101 static int gpio_spi_read(uint32 index, uint8 len_i, uint32 data, uint8 len_d)
103 uint32 i, reg_val = 0, rd_val = 0;
104 uint32 rd_reg[16] = { 0 };
105 uint32 rd_reg1[16] = { 0 };
106 uint32 rd_reg2[16] = { 0 };
107 volatile struct gpio_ctrl_reg *regs =
108 (volatile struct gpio_ctrl_reg *)
109 (GPIO_BASE_ADDR + GPIO_LVDSCHIP_OFFSET);
112 regs->msk = GPIO_SCK_BIT | GPIO_CS_BIT | GPIO_SDI_BIT;
113 regs->dir = GPIO_SCK_BIT | GPIO_CS_BIT | GPIO_SDI_BIT;
114 regs->data = GPIO_SCK_BIT | GPIO_CS_BIT;
116 /* Bit[7] output 1 */
117 reg_val = GPIO_CS_BIT;
118 regs->data = reg_val;
123 regs->data = reg_val;
125 for (i = 0; i < len_d; ++i) {
127 reg_val = ((data >> (len_d - i -1)) << GPIO_SPI_SDI_PIN) & GPIO_SDI_BIT;
128 regs->data = reg_val;
131 regs->data |= GPIO_SCK_BIT;
135 for (i = 0; i < len_i; ++i) {
137 reg_val = ((index >> (len_i - i -1)) << GPIO_SPI_SDI_PIN) & GPIO_SDI_BIT;
138 regs->data = reg_val;
141 regs->data |= GPIO_SCK_BIT;
147 regs->data |= GPIO_CS_BIT;
149 regs->inen |= GPIO_SDI_BIT;
150 regs->dir &= ~GPIO_SDI_BIT;
151 regs->data |= GPIO_SCK_BIT;
153 regs->data &= ~GPIO_SCK_BIT;
155 for (i = 0; i < 16; ++i) {
157 regs->data |= GPIO_SCK_BIT;
158 rd_reg[i] = regs->data & GPIO_SDI_BIT;
159 rd_reg1[i] = rd_reg[i] >> 10;
160 rd_reg2[i] = rd_reg1[i] << (15 - i);
161 rd_val |= rd_reg2[i];
163 regs->data &= ~GPIO_SCK_BIT;
167 regs->data |= GPIO_CS_BIT;
169 regs->data |= GPIO_SCK_BIT;
170 regs->data |= GPIO_SDI_BIT;
171 udelay(DELAY_CNT * 50);
176 int sprdchip_lvds_init(void)
178 uint32 i, rd_val1, rd_val2;
179 for (i = 0; i < 50; ++i) {
180 gpio_spi_write(27, 18, 0, 16);
181 rd_val1 = gpio_spi_read(63, 18, 27, 16);
184 for (i = 0; i < 50; ++i) {
185 gpio_spi_write(28, 18, 10240, 16);
186 gpio_spi_write(27, 18, 16, 16);
187 rd_val1 = gpio_spi_read(63, 18, 27, 16);
188 rd_val2 = gpio_spi_read(63, 18, 28, 16);