1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
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30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
36 * The Core Interface Layer provides basic services for accessing and
37 * managing the DWC_otg hardware. These services are used by both the
38 * Host Controller Driver and the Peripheral Controller Driver.
40 * This file contains the Common Interrupt handlers.
43 #include "dwc_otg_regs.h"
44 #include "dwc_otg_cil.h"
47 inline const char *op_state_str(dwc_otg_core_if_t * core_if)
49 return (core_if->op_state == A_HOST ? "a_host" :
50 (core_if->op_state == A_SUSPEND ? "a_suspend" :
51 (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
52 (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
53 (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
57 /** This function will log a debug message
59 * @param core_if Programming view of DWC_otg controller.
61 int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
63 gintsts_data_t gintsts;
64 DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
65 dwc_otg_mode(core_if) ? "Host" : "Device");
69 gintsts.b.modemismatch = 1;
70 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
74 /** Start the HCD. Helper function for using the HCD callbacks.
76 * @param core_if Programming view of DWC_otg controller.
78 static inline void hcd_start(dwc_otg_core_if_t * core_if)
80 if (core_if->hcd_cb && core_if->hcd_cb->start) {
81 core_if->hcd_cb->start(core_if->hcd_cb->p);
85 /** Stop the HCD. Helper function for using the HCD callbacks.
87 * @param core_if Programming view of DWC_otg controller.
89 static inline void hcd_stop(dwc_otg_core_if_t * core_if)
91 if (core_if->hcd_cb && core_if->hcd_cb->stop) {
92 core_if->hcd_cb->stop(core_if->hcd_cb->p);
96 /** Disconnect the HCD. Helper function for using the HCD callbacks.
98 * @param core_if Programming view of DWC_otg controller.
100 static inline void hcd_disconnect(dwc_otg_core_if_t * core_if)
102 if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
103 core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
107 /** Inform the HCD the a New Session has begun. Helper function for
108 * using the HCD callbacks.
110 * @param core_if Programming view of DWC_otg controller.
112 static inline void hcd_session_start(dwc_otg_core_if_t * core_if)
114 if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
115 core_if->hcd_cb->session_start(core_if->hcd_cb->p);
119 #ifdef CONFIG_USB_DWC_OTG_LPM
121 * Inform the HCD about LPM sleep.
122 * Helper function for using the HCD callbacks.
124 * @param core_if Programming view of DWC_otg controller.
126 static inline void hcd_sleep(dwc_otg_core_if_t * core_if)
128 if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
129 core_if->hcd_cb->sleep(core_if->hcd_cb->p);
134 /** Resume the HCD. Helper function for using the HCD callbacks.
136 * @param core_if Programming view of DWC_otg controller.
138 static inline void hcd_resume(dwc_otg_core_if_t * core_if)
140 if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
141 core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
145 /** Start the PCD. Helper function for using the PCD callbacks.
147 * @param core_if Programming view of DWC_otg controller.
149 static inline void pcd_start(dwc_otg_core_if_t * core_if)
151 if (core_if->pcd_cb && core_if->pcd_cb->start) {
152 core_if->pcd_cb->start(core_if->pcd_cb->p);
156 /** Stop the PCD. Helper function for using the PCD callbacks.
158 * @param core_if Programming view of DWC_otg controller.
160 static inline void pcd_stop(dwc_otg_core_if_t * core_if)
162 if (core_if->pcd_cb && core_if->pcd_cb->stop) {
163 core_if->pcd_cb->stop(core_if->pcd_cb->p);
167 /** Suspend the PCD. Helper function for using the PCD callbacks.
169 * @param core_if Programming view of DWC_otg controller.
171 static inline void pcd_suspend(dwc_otg_core_if_t * core_if)
173 if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
174 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
178 /** Resume the PCD. Helper function for using the PCD callbacks.
180 * @param core_if Programming view of DWC_otg controller.
182 static inline void pcd_resume(dwc_otg_core_if_t * core_if)
184 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
185 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
190 * This function handles the OTG Interrupts. It reads the OTG
191 * Interrupt Register (GOTGINT) to determine what interrupt has
194 * @param core_if Programming view of DWC_otg controller.
196 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
198 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
199 gotgint_data_t gotgint;
200 gotgctl_data_t gotgctl;
201 gintmsk_data_t gintmsk;
203 gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
204 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
205 DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
206 op_state_str(core_if));
208 if (gotgint.b.sesenddet) {
209 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
210 "Session End Detected++ (%s)\n",
211 op_state_str(core_if));
212 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
214 if (core_if->op_state == B_HOST) {
216 core_if->op_state = B_PERIPHERAL;
218 /* If not B_HOST and Device HNP still set. HNP
220 if (gotgctl.b.devhnpen) {
221 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
222 DWC_ERROR("Device Not Connected/Responding!\n");
225 /* If Session End Detected the B-Cable has
226 * been disconnected. */
227 /* Reset PCD and Gadget driver to a
229 core_if->lx_state = DWC_OTG_L0;
233 gotgctl.b.devhnpen = 1;
234 dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
236 if (gotgint.b.sesreqsucstschng) {
237 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
238 "Session Reqeust Success Status Change++\n");
239 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
240 if (gotgctl.b.sesreqscs) {
241 if ((core_if->core_params->phy_type ==
242 DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
243 core_if->srp_success = 1;
246 /* Clear Session Request */
248 gotgctl.b.sesreq = 1;
249 dwc_modify_reg32(&global_regs->gotgctl,
254 if (gotgint.b.hstnegsucstschng) {
255 /* Print statements during the HNP interrupt handling
256 * can cause it to fail.*/
257 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
258 if (gotgctl.b.hstnegscs) {
259 if (dwc_otg_is_host_mode(core_if)) {
260 core_if->op_state = B_HOST;
262 * Need to disable SOF interrupt immediately.
263 * When switching from device to host, the PCD
264 * interrupt handler won't handle the
265 * interrupt if host mode is already set. The
266 * HCD interrupt handler won't get called if
267 * the HCD state is HALT. This means that the
268 * interrupt does not get handled and Linux
272 gintmsk.b.sofintr = 1;
273 dwc_modify_reg32(&global_regs->gintmsk,
277 * Initialize the Core for Host mode.
280 core_if->op_state = B_HOST;
284 gotgctl.b.hnpreq = 1;
285 gotgctl.b.devhnpen = 1;
286 dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
287 DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
288 DWC_ERROR("Device Not Connected/Responding\n");
291 if (gotgint.b.hstnegdet) {
292 /* The disconnect interrupt is set at the same time as
293 * Host Negotiation Detected. During the mode
294 * switch all interrupts are cleared so the disconnect
295 * interrupt handler will not get executed.
297 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
298 "Host Negotiation Detected++ (%s)\n",
299 (dwc_otg_is_host_mode(core_if) ? "Host" :
301 if (dwc_otg_is_device_mode(core_if)) {
302 DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
304 hcd_disconnect(core_if);
306 core_if->op_state = A_PERIPHERAL;
309 * Need to disable SOF interrupt immediately. When
310 * switching from device to host, the PCD interrupt
311 * handler won't handle the interrupt if host mode is
312 * already set. The HCD interrupt handler won't get
313 * called if the HCD state is HALT. This means that
314 * the interrupt does not get handled and Linux
318 gintmsk.b.sofintr = 1;
319 dwc_modify_reg32(&global_regs->gintmsk, gintmsk.d32, 0);
322 core_if->op_state = A_HOST;
325 if (gotgint.b.adevtoutchng) {
326 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
327 "A-Device Timeout Change++\n");
329 if (gotgint.b.debdone) {
330 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
334 dwc_write_reg32(&core_if->core_global_regs->gotgint, gotgint.d32);
339 void w_conn_id_status_change(void *p)
341 dwc_otg_core_if_t *core_if = p;
343 gotgctl_data_t gotgctl = {.d32 = 0 };
345 gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
346 DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
347 DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
349 /* B-Device connector (Device Mode) */
350 if (gotgctl.b.conidsts) {
351 /* Wait for switch to device mode. */
352 while (!dwc_otg_is_device_mode(core_if)) {
353 DWC_DEBUGPL(DBG_CIL,"Waiting for Peripheral Mode, Mode=%s\n",
354 (dwc_otg_is_host_mode(core_if) ? "Host" :
360 DWC_ASSERT(++count < 10000,
361 "Connection id status change timed out");
362 core_if->op_state = B_PERIPHERAL;
363 dwc_otg_core_init(core_if);
364 dwc_otg_enable_global_interrupts(core_if);
367 /* A-Device connector (Host Mode) */
368 while (!dwc_otg_is_host_mode(core_if)) {
369 DWC_DEBUGPL(DBG_CIL,"Waiting for Host Mode, Mode=%s\n",
370 (dwc_otg_is_host_mode(core_if) ? "Host" :
376 DWC_ASSERT(++count < 10000,
377 "Connection id status change timed out");
378 core_if->op_state = A_HOST;
380 * Initialize the Core for Host mode.
382 dwc_otg_core_init(core_if);
383 dwc_otg_enable_global_interrupts(core_if);
389 * This function handles the Connector ID Status Change Interrupt. It
390 * reads the OTG Interrupt Register (GOTCTL) to determine whether this
391 * is a Device to Host Mode transition or a Host Mode to Device
394 * This only occurs when the cable is connected/removed from the PHY
397 * @param core_if Programming view of DWC_otg controller.
399 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
403 * Need to disable SOF interrupt immediately. If switching from device
404 * to host, the PCD interrupt handler won't handle the interrupt if
405 * host mode is already set. The HCD interrupt handler won't get
406 * called if the HCD state is HALT. This means that the interrupt does
407 * not get handled and Linux complains loudly.
409 gintmsk_data_t gintmsk = {.d32 = 0 };
410 gintsts_data_t gintsts = {.d32 = 0 };
412 gintmsk.b.sofintr = 1;
413 dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
416 " ++Connector ID Status Change Interrupt++ (%s)\n",
417 (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
420 * Need to schedule a work, as there are possible DELAY function calls
422 DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
423 core_if, "connection id status change");
425 /* Set flag and clear interrupt */
426 gintsts.b.conidstschng = 1;
427 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
433 * This interrupt indicates that a device is initiating the Session
434 * Request Protocol to request the host to turn on bus power so a new
435 * session can begin. The handler responds by turning on bus power. If
436 * the DWC_otg controller is in low power mode, the handler brings the
437 * controller out of low power mode before turning on bus power.
439 * @param core_if Programming view of DWC_otg controller.
441 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
444 gintsts_data_t gintsts;
446 #ifndef DWC_HOST_ONLY
447 DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
449 if (dwc_otg_is_device_mode(core_if)) {
450 DWC_DEBUGPL(DBG_CIL,"SRP: Device mode\n");
452 DWC_DEBUGPL(DBG_CIL,"SRP: Host mode\n");
454 /* Turn on the port power bit. */
455 hprt0.d32 = dwc_otg_read_hprt0(core_if);
457 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
459 /* Start the Connection timer. So a message can be displayed
460 * if connect does not occur within 10 seconds. */
461 hcd_session_start(core_if);
465 /* Clear interrupt */
467 gintsts.b.sessreqintr = 1;
468 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
473 void w_wakeup_detected(void *p)
475 dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
477 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
478 * so that OPT tests pass with all PHYs).
480 hprt0_data_t hprt0 = {.d32 = 0 };
482 pcgcctl_data_t pcgcctl = {.d32 = 0 };
483 /* Restart the Phy Clock */
484 pcgcctl.b.stoppclk = 1;
485 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
488 hprt0.d32 = dwc_otg_read_hprt0(core_if);
489 DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
491 hprt0.b.prtres = 0; /* Resume */
492 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
493 DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
494 dwc_read_reg32(core_if->host_if->hprt0));
498 /** Change to L0 state*/
499 core_if->lx_state = DWC_OTG_L0;
504 * This interrupt indicates that the DWC_otg controller has detected a
505 * resume or remote wakeup sequence. If the DWC_otg controller is in
506 * low power mode, the handler must brings the controller out of low
507 * power mode. The controller automatically begins resume
508 * signaling. The handler schedules a time to stop resume signaling.
510 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
512 gintsts_data_t gintsts;
515 "++Resume and Remote Wakeup Detected Interrupt++\n");
517 DWC_DEBUGPL(DBG_CIL,"%s lxstate = %d\n", __func__, core_if->lx_state);
519 if (dwc_otg_is_device_mode(core_if)) {
520 dctl_data_t dctl = {.d32 = 0 };
521 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
522 dwc_read_reg32(&core_if->dev_if->dev_global_regs->
524 if (core_if->lx_state == DWC_OTG_L2) {
525 #ifdef PARTIAL_POWER_DOWN
526 if (core_if->hwcfg4.b.power_optimiz) {
527 pcgcctl_data_t power = {.d32 = 0 };
529 power.d32 = dwc_read_reg32(core_if->pcgcctl);
530 DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
533 power.b.stoppclk = 0;
534 dwc_write_reg32(core_if->pcgcctl, power.d32);
537 dwc_write_reg32(core_if->pcgcctl, power.d32);
539 power.b.rstpdwnmodule = 0;
540 dwc_write_reg32(core_if->pcgcctl, power.d32);
543 /* Clear the Remote Wakeup Signalling */
544 dctl.b.rmtwkupsig = 1;
545 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
548 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
549 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->
553 glpmcfg_data_t lpmcfg;
555 dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
556 lpmcfg.b.hird_thres &= (~(1 << 4));
557 dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
560 /** Change to L0 state*/
561 core_if->lx_state = DWC_OTG_L0;
563 if (core_if->lx_state != DWC_OTG_L1) {
564 pcgcctl_data_t pcgcctl = {.d32 = 0 };
566 /* Restart the Phy Clock */
567 pcgcctl.b.stoppclk = 1;
568 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
570 DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
572 /** Change to L0 state*/
573 core_if->lx_state = DWC_OTG_L0;
577 /* Clear interrupt */
579 gintsts.b.wkupintr = 1;
580 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
586 * This interrupt indicates that a device has been disconnected from
589 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
591 gintsts_data_t gintsts;
593 DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
594 (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
595 op_state_str(core_if));
597 /** @todo Consolidate this if statement. */
598 #ifndef DWC_HOST_ONLY
599 if (core_if->op_state == B_HOST) {
600 /* If in device mode Disconnect and stop the HCD, then
602 hcd_disconnect(core_if);
604 core_if->op_state = B_PERIPHERAL;
605 } else if (dwc_otg_is_device_mode(core_if)) {
606 gotgctl_data_t gotgctl = {.d32 = 0 };
608 dwc_read_reg32(&core_if->core_global_regs->gotgctl);
609 if (gotgctl.b.hstsethnpen == 1) {
610 /* Do nothing, if HNP in process the OTG
611 * interrupt "Host Negotiation Detected"
612 * interrupt will do the mode switch.
614 } else if (gotgctl.b.devhnpen == 0) {
615 /* If in device mode Disconnect and stop the HCD, then
617 hcd_disconnect(core_if);
619 core_if->op_state = B_PERIPHERAL;
621 DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
624 if (core_if->op_state == A_HOST) {
625 /* A-Cable still connected but device disconnected. */
626 hcd_disconnect(core_if);
630 /* Change to L3(OFF) state */
631 core_if->lx_state = DWC_OTG_L3;
634 gintsts.b.disconnect = 1;
635 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
640 * This interrupt indicates that SUSPEND state has been detected on
643 * For HNP the USB Suspend interrupt signals the change from
644 * "a_peripheral" to "a_host".
646 * When power management is enabled the core will be put in low power
649 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
652 gintsts_data_t gintsts;
654 DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
656 if (dwc_otg_is_device_mode(core_if)) {
657 /* Check the Device status register to determine if the Suspend
658 * state is active. */
660 dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
661 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
662 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
663 "HWCFG4.power Optimize=%d\n",
664 dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
666 #ifdef PARTIAL_POWER_DOWN
667 /** @todo Add a module parameter for power management. */
669 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
670 pcgcctl_data_t power = {.d32 = 0 };
671 DWC_DEBUGPL(DBG_CIL, "suspend\n");
674 dwc_write_reg32(core_if->pcgcctl, power.d32);
676 power.b.rstpdwnmodule = 1;
677 dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
679 power.b.stoppclk = 1;
680 dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
683 DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
686 /* PCD callback for suspend. */
687 pcd_suspend(core_if);
689 if (core_if->op_state == A_PERIPHERAL) {
690 DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
691 /* Clear the a_peripheral flag, back to a_host. */
694 core_if->op_state = A_HOST;
698 /* Change to L2(suspend) state */
699 core_if->lx_state = DWC_OTG_L2;
701 /* Clear interrupt */
703 gintsts.b.usbsuspend = 1;
704 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
709 #ifdef CONFIG_USB_DWC_OTG_LPM
711 * This function hadles LPM transaction received interrupt.
713 static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
715 glpmcfg_data_t lpmcfg;
716 gintsts_data_t gintsts;
718 if (!core_if->core_params->lpm_enable) {
719 DWC_DEBUGPL(DBG_CIL,"Unexpected LPM interrupt\n");
722 lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
723 DWC_DEBUGPL(DBG_CIL,"LPM config register = 0x%08x\n", lpmcfg.d32);
725 if (dwc_otg_is_host_mode(core_if)) {
728 lpmcfg.b.hird_thres |= (1 << 4);
729 dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
733 if (lpmcfg.b.prt_sleep_sts) {
734 /* Save the current state */
735 core_if->lx_state = DWC_OTG_L1;
738 /* Clear interrupt */
740 gintsts.b.lpmtranrcvd = 1;
741 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
744 #endif /* CONFIG_USB_DWC_OTG_LPM */
747 * This function returns the Core Interrupt register.
749 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
751 gintsts_data_t gintsts;
752 gintmsk_data_t gintmsk;
753 gintmsk_data_t gintmsk_common = {.d32 = 0 };
754 gintmsk_common.b.wkupintr = 1;
755 gintmsk_common.b.sessreqintr = 1;
756 gintmsk_common.b.conidstschng = 1;
757 gintmsk_common.b.otgintr = 1;
758 gintmsk_common.b.modemismatch = 1;
759 gintmsk_common.b.disconnect = 1;
760 gintmsk_common.b.usbsuspend = 1;
761 #ifdef CONFIG_USB_DWC_OTG_LPM
762 gintmsk_common.b.lpmtranrcvd = 1;
764 /** @todo: The port interrupt occurs while in device
765 * mode. Added code to CIL to clear the interrupt for now!
767 gintmsk_common.b.portintr = 1;
769 gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
770 gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
772 /* if any common interrupts set */
773 if (gintsts.d32 & gintmsk_common.d32) {
774 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
775 gintsts.d32, gintmsk.d32);
779 return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
784 * Common interrupt handler.
786 * The common interrupts are those that occur in both Host and Device mode.
787 * This handler handles the following interrupts:
788 * - Mode Mismatch Interrupt
789 * - Disconnect Interrupt
791 * - Connector ID Status Change Interrupt
792 * - Session Request Interrupt.
793 * - Resume / Remote Wakeup Detected Interrupt.
794 * - LPM Transaction Received Interrutp
797 int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * core_if)
800 gintsts_data_t gintsts;
802 gintsts.d32 = dwc_otg_read_common_intr(core_if);
804 if (gintsts.b.modemismatch) {
805 retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
807 if (gintsts.b.otgintr) {
808 retval |= dwc_otg_handle_otg_intr(core_if);
810 if (gintsts.b.conidstschng) {
811 retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
813 if (gintsts.b.disconnect) {
814 retval |= dwc_otg_handle_disconnect_intr(core_if);
816 if (gintsts.b.sessreqintr) {
817 retval |= dwc_otg_handle_session_req_intr(core_if);
819 if (gintsts.b.wkupintr) {
820 retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
822 if (gintsts.b.usbsuspend) {
823 retval |= dwc_otg_handle_usb_suspend_intr(core_if);
825 #ifdef CONFIG_USB_DWC_OTG_LPM
826 if (gintsts.b.lpmtranrcvd) {
827 retval |= dwc_otg_handle_lpm_intr(core_if);
831 if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
832 /* The port interrupt occurs while in device mode with HPRT0
833 * Port Enable/Disable.
836 gintsts.b.portintr = 1;
837 dwc_write_reg32(&core_if->core_global_regs->gintsts,