drivers/mmc/sdhost_phy.c

   1 /******************************************************************************
   2  ** File Name:      sdhost_drv.c
   3  ** Author:         Jason.wu
   4  ** DATE:           09/17/2007
   5  ** Copyright:      2004 Spreadtrum, Incoporated. All Rights Reserved.
   6  ** Description:    This file describe operation of SD host.
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION
  13  ** 09/17/2007     Jason.wu        Create.
  14  ******************************************************************************/
  15
  16 /**---------------------------------------------------------------------------*
  17  **                         Dependencies                                      *
  18  **---------------------------------------------------------------------------*/
  19 #include "asm/arch/sci_types.h"
  20 #include "asm/arch/os_api.h"
  21 #include "asm/arch/chip_plf_export.h"
  22 #include "sdhost_drv.h"
  23
  24 #if   defined(CONFIG_SC8825) || defined (CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
  25 #include <asm/arch/sdio_reg_v3.h>
  26 //#include <asm/arch/int_reg_v3.h>
  27 #include <asm/arch/sys_timer_reg_v0.h>
  28 #endif
  29
  30 #if   defined(CONFIG_SC8825) || defined (CONFIG_SC7710G2)
  31 #include <asm/arch/sc8810_module_config.h>
  32 #elif defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
  33 #include <asm/arch/sprd_module_config.h>
  34 #include <asm/arch/regs_ahb.h>
  35 #include <asm/arch/isr_drvapi.h>
  36 #include <asm/arch/pinmap.h>
  37 #endif
  38
  39 #include "asm/arch/ldo.h"
  40
  41 #ifdef CONFIG_SC8825
  42 #include <asm/arch/pin_reg_v3.h>
  43 #endif
  44
  45 #if defined (CONFIG_SC8810) || defined (CONFIG_SC8825) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
  46 #define PLATFORM_SC8800G
  47 #endif
  48 #if defined CONFIG_SC8825 && defined CONFIG_UBOOT_DEBUG
  49 #define SDHOST_PRINT(x) printf x
  50 #else
  51 #define SDHOST_PRINT(x) SCI_TRACE_LOW x
  52 #endif
  53 /*****************************************************************************/
  54 //  Description:   Handle of sdhost
  55 //  Author: Jason.wu
  56 //  Param
  57 //      host_cfg: start register of host controller
  58 //      open_flag: Indicate whether this port has be used by other application
  59 //      baseClock: the basic frequence that host work on
  60 //      sdClock: the frequence that card work on
  61 //      capbility: the function that canbe supported by host
  62 //      err_filter: the error code that application want to watched
  63 //      sigCallBack: the point of application that used to anounce that some signal happened
  64 //  Note:
  65 /*****************************************************************************/
  66 typedef struct SDHOST_PORT_T_TAG
  67 {
  68     volatile SDIO_REG_CFG *host_cfg;
  69     BOOLEAN open_flag;
  70         uint32 slotNo;
  71     uint32 baseClock;
  72     uint32 sdClock;
  73     SDHOST_CAPBILIT_T capbility;
  74     uint32 err_filter;
  75     SDIO_CALLBACK sigCallBack;
  76     uint32 IntEnabled;
  77     uint32 SigEnabled;
  78 } SDHOST_PORT_T;
  79
  80 typedef struct
  81 {
  82     uint32 msg;
  83     uint32 errCode;
  84     SDHOST_SLOT_NO slotNum;
  85     SDHOST_HANDLE pSdhost_handler;
  86
  87 } ISR_Buffer_T;
  88
  89 //INPUT_BUFFER_INIT (ISR_Buffer_T, SDHOST_SLOT_MAX_NUM)
  90
  91 LOCAL SDHOST_PORT_T sdio_port_ctl[SDHOST_SLOT_MAX_NUM];
  92 #ifndef OS_NONE
  93 LOCAL DEVICE_HANDLE s_dev_sdio = SCI_NULL;
  94 #endif
  95
  96 PUBLIC ISR_EXE_T _SDHOST_IrqHandle (uint32 isrnum);
  97 LOCAL void  SdhostHisrFunc (uint32 cnt, void *pData);
  98
  99 PUBLIC void SDHOST_Delayus(uint32 usec)
 100 {
 101         volatile uint32 i;
 102         /* current is 800MHZ, when usec =1, the mean is delay 1 us */
 103         for (i = 0; i < (usec << 1); i++);
 104 }
 105 /*****************************************************************************/
 106 //  Description:  To confirm whether the handle is valid
 107 //  Author: Jason.wu
 108 //  Param
 109 //      sdhost_handler: the handle of host driver
 110 //  Return:
 111 //      TRUE the handle is valid
 112 //      FALSE:the handle is not valid
 113 //  Note:
 114 /*****************************************************************************/
 115 LOCAL BOOLEAN _RegisterVerifyHOST (SDHOST_HANDLE sdhost_handler)
 116 {
 117     uint32 index;
 118
 119     for (index = 0; index < SDHOST_SLOT_MAX_NUM; index++)
 120     {
 121         if ( (sdhost_handler == &sdio_port_ctl[index]) && (TRUE == sdio_port_ctl[index].open_flag))
 122         {
 123             return TRUE;
 124         }
 125     }
 126
 127     return FALSE;
 128 }
 129
 130 PUBLIC uint32 SDHOST_GetPinState (SDHOST_HANDLE sdhost_handler)
 131 {
 132     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 133
 134     return sdhost_handler->host_cfg->PRESENT_STAT;
 135 }
 136
 137 //---Power Control Register---
 138 /*****************************************************************************/
 139 //  Description:  power on/off led
 140 //  Author: Jason.wu
 141 //  Param
 142 //      sdhost_handler: the handle of host driver
 143 //      onoff:
 144 //  Return:
 145 //      NONE
 146 //  Note:
 147 /*****************************************************************************/
 148 PUBLIC void SDHOST_Led (SDHOST_HANDLE sdhost_handler,SDHOST_LED_ONOFF_E onoff)
 149 {
 150     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 151
 152     //===
 153     switch (onoff)
 154     {
 155         case SDIO_LED_ON:
 156             {
 157                 sdhost_handler->host_cfg->HOST_CTL0 |= 0x1;
 158             }
 159             break;
 160
 161         case SDIO_LED_OFF:
 162             {
 163                 sdhost_handler->host_cfg->HOST_CTL0 &= (~0x1);
 164             }
 165             break;
 166
 167         default:
 168             {
 169                 SCI_ASSERT (0);/*assert verified*/
 170             }
 171             break;
 172     }
 173
 174     //===
 175 }
 176
 177 /*****************************************************************************/
 178 //  Description:  set data bus width
 179 //  Author: Jason.wu
 180 //  Param
 181 //      sdhost_handler: the handle of host driver
 182 //      width: data bus width,only 1bit ,4bit and 8bit canbe used
 183 //  Return:
 184 //      NONE
 185 //  Note:
 186 /*****************************************************************************/
 187 PUBLIC void SDHOST_Cfg_BusWidth (SDHOST_HANDLE sdhost_handler,SDHOST_BIT_WIDTH_E width)
 188 {
 189     uint32 tmpReg =  sdhost_handler->host_cfg->HOST_CTL0;
 190
 191     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 192
 193     tmpReg &= (~ (0x1<<5));
 194     tmpReg &= (~ (0x1<<1));
 195
 196     switch (width)
 197     {
 198         case SDIO_1BIT_WIDTH:
 199             {
 200                 //do nothing
 201             }
 202             break;
 203
 204         case SDIO_4BIT_WIDTH:
 205             {
 206                 tmpReg |= (0x1<<1);
 207             }
 208             break;
 209
 210         case SDIO_8BIT_WIDTH:
 211             {
 212                 tmpReg |= (0x1<<5);
 213             }
 214             break;
 215
 216         default:
 217             {
 218                 SCI_ASSERT (0);/*assert verified*/
 219             }
 220             break;
 221     }
 222
 223     sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
 224 }
 225
 226 /*****************************************************************************/
 227 //  Description:  set bus speed mode
 228 //  Author: Jason.wu
 229 //  Param
 230 //      sdhost_handler: the handle of host driver
 231 //      speed: speed mode ,only low speed mode and high speed mode canbe used
 232 //  Return:
 233 //      NONE
 234 //  Note:
 235 /*****************************************************************************/
 236 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
 237 PUBLIC void SDHOST_Cfg_SpeedMode (SDHOST_HANDLE sdhost_handler,SDHOST_SPEED_E speed)
 238 {
 239         uint32 tmpReg = sdhost_handler->host_cfg->HOST_CTL2;
 240         SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 241         tmpReg &= ~(7<<16);
 242         switch (speed)
 243         {
 244         case EMMC_SDR12:
 245                 break;
 246         case EMMC_SDR25:
 247                 tmpReg |= 1<<16;
 248                 break;
 249         case EMMC_SDR50:
 250                 REG32(EMMC_CLK_WR_DL)     = 0x33;
 251                 REG32(EMMC_CLK_RD_POS_DL) = 0x08;
 252                 REG32(EMMC_CLK_RD_NEG_DL) = 0x08;
 253                 tmpReg |= 2<<16;
 254                 break;
 255         case EMMC_SDR104:
 256                 tmpReg |= 3<<16;
 257                 break;
 258         case EMMC_DDR50:
 259                 tmpReg |= 4<<16;
 260                 break;
 261         default:
 262                 return;
 263         }
 264         sdhost_handler->host_cfg->HOST_CTL2 = tmpReg;
 265 }
 266 #else
 267 PUBLIC void SDHOST_Cfg_SpeedMode (SDHOST_HANDLE sdhost_handler,SDHOST_SPEED_E speed)
 268 {
 269     uint32 tmpReg =  sdhost_handler->host_cfg->HOST_CTL0;
 270
 271     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 272
 273     tmpReg &= (~ (0x1 <<2));
 274
 275     switch (speed)
 276     {
 277         case SDIO_HIGHSPEED:
 278             {
 279                 tmpReg |= (0x1<<2);
 280             }
 281             break;
 282
 283         case SDIO_LOWSPEED:
 284             {
 285                 //do nothing
 286             }
 287             break;
 288
 289         default:
 290             {
 291                 SCI_ASSERT (0);/*assert verified*/
 292             }
 293             break;
 294     }
 295
 296     sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
 297 }
 298 #endif
 299
 300 /*
 301 typedef enum
 302 {
 303         LDO_VOLT_LEVEL0=0,
 304         LDO_VOLT_LEVEL1,
 305         LDO_VOLT_LEVEL2,
 306         LDO_VOLT_LEVEL3,
 307         LDO_VOLT_LEVEL_MAX
 308 }LDO_VOLT_LEVEL_E;
 309
 310 #define LDO_LDO_SDIO 29 */
 311
 312 /*****************************************************************************/
 313 //  Description:  Set operation voltage of card(mmc \sd\sdio card.etc.)
 314 //  Author: Jason.wu
 315 //  Param
 316 //      sdhost_handler: the handle of host driver
 317 //      voltage:
 318 //  Return:
 319 //      NONE
 320 //  Note:
 321 /*****************************************************************************/
 322 PUBLIC void SDHOST_Cfg_Voltage (SDHOST_HANDLE sdhost_handler,SDHOST_VOL_RANGE_E voltage)
 323 {
 324 #if defined (CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 325     /*<CR:MS00234475 modify for SPI smartphone 30/03/2011 by shengyanxin bagin*/
 326 #if defined (MODEM_CONTROL_SUPPORT_SPI)
 327     return;
 328 #else
 329 #ifdef PLATFORM_SC8800G
 330     LDO_VOLT_LEVEL_E ldo_volt_level;
 331     u32 tempreg;
 332     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 333
 334     switch (voltage)
 335     {
 336         case VOL_1_8:
 337             {
 338                 ldo_volt_level = LDO_VOLT_LEVEL3;
 339             }
 340             break;
 341
 342         case VOL_2_65:
 343             {
 344                 ldo_volt_level = LDO_VOLT_LEVEL2;   ///it is 2.5V in sc8800g spec.
 345             }
 346             break;
 347
 348         case VOL_2_8:
 349             {
 350                 ldo_volt_level = LDO_VOLT_LEVEL0;
 351             }
 352             break;
 353
 354         case VOL_3_0:
 355             {
 356                 ldo_volt_level = LDO_VOLT_LEVEL1;
 357             }
 358             break;
 359
 360         default:
 361             {
 362                 SCI_ASSERT (0);/*assert verified*/
 363             }
 364             break;
 365     }
 366
 367 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 368     LDO_SetVoltLevel (LDO_LDO_SDIO3, LDO_VOLT_LEVEL3);
 369     LDO_SetVoltLevel (LDO_LDO_VDD30, LDO_VOLT_LEVEL1);
 370 #else
 371     if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
 372         LDO_SetVoltLevel (LDO_LDO_SDIO0, LDO_VOLT_LEVEL3);
 373     }
 374         else
 375         {
 376             LDO_SetVoltLevel (LDO_LDO_SDIO1, LDO_VOLT_LEVEL3);
 377             LDO_SetVoltLevel (LDO_LDO_SIM2, LDO_VOLT_LEVEL1);
 378         }
 379 #endif
 380
 381     //__udelay(20*1000);
 382     //gpio_direction_output(139, 1);
 383     //gpio_set_value(139, 1);
 384    //control gpio 139 emmc reset pin
 385     /*
 386     *(volatile u32 *)0x8B000008 = 1<<5;
 387     *(volatile u32 *)0x8A000384 = 1<<15;
 388     *(volatile u32 *)0x8A000388 = 1<<15;
 389     *(volatile u32 *)0x8A000380 = 1<<15;
 390   */
 391     tempreg = *(volatile u32 *)0x8B000008;
 392     *(volatile u32 *)0x8B000008 = tempreg | (1<<5);
 393
 394     //*(volatile u32 *)0x8C0003D0 = 0;
 395
 396 #ifdef CONFIG_SC8810_OPENPHONE
 397             tempreg = *(volatile unsigned int  *)0x8A000384;
 398             *(volatile unsigned int  *)0x8A000384 = tempreg | (1<<11);
 399             tempreg = *(volatile unsigned int  *)0x8A000388;
 400             *(volatile unsigned int  *)0x8A000388 = tempreg | (1<<11);
 401             tempreg = *(volatile unsigned int  *)0x8A000380;
 402             *(volatile unsigned int  *)0x8A000380 = tempreg | (1<<11);
 403 #else
 404            tempreg = *(volatile unsigned int  *)0x8A000184;
 405             *(volatile unsigned int  *)0x8A000184 = tempreg | (1<<7);
 406             tempreg = *(volatile unsigned int  *)0x8A000188;
 407             *(volatile unsigned int  *)0x8A000188 = tempreg | (1<<7);
 408             tempreg = *(volatile unsigned int  *)0x8A000180;
 409             *(volatile unsigned int  *)0x8A000180 = tempreg | (1<<7);
 410 #endif
 411
 412 #else
 413
 414     uint32 tmpReg =  sdhost_handler->host_cfg->HOST_CTL0;
 415
 416     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 417
 418     tmpReg &= (~ (0x7<<9));
 419
 420     switch (voltage)
 421     {
 422         case VOL_1_8:
 423             {
 424                 tmpReg |= (0x05<<9);
 425             }
 426             break;
 427
 428         case VOL_2_65:
 429             {
 430                 tmpReg |= (0x01<<9);
 431             }
 432             break;
 433
 434         case VOL_2_8:
 435             {
 436                 tmpReg |= (0x04<<9);
 437             }
 438             break;
 439
 440         case VOL_3_0:
 441             {
 442                 tmpReg |= (0x07<<9);
 443             }
 444             break;
 445
 446         default:
 447             {
 448                 SCI_ASSERT (0);/*assert verified*/
 449             }
 450             break;
 451     }
 452
 453     sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
 454 #endif
 455 #endif
 456 #endif
 457 }
 458
 459 /*****************************************************************************/
 460 //  Description:  Open or close power supply of card(mmc \sd\sdio card.etc.)
 461 //  Author: Jason.wu
 462 //  Param
 463 //      sdhost_handler: the handle of host driver
 464 //      on_off:
 465 //  Return:
 466 //      NONE
 467 //  Note:
 468 /*****************************************************************************/
 469 PUBLIC void SDHOST_SD_POWER (SDHOST_HANDLE sdhost_handler,SDHOST_PWR_ONOFF_E on_off)
 470 {
 471     /*<CR:MS00234475 modify for SPI smartphone 30/03/2011 by shengyanxin bagin*/
 472 #if defined (MODEM_CONTROL_SUPPORT_SPI) && defined (AP_SOLUTION_INGENIC)
 473     return;
 474 #else
 475     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 476
 477 #if defined(PLATFORM_SC8800G)
 478
 479     ///added by mingwei, Andy need to check again.
 480     if (POWR_ON == on_off)
 481     {
 482         //LDO_TurnOnLDO (LDO_LDO_SDIO);
 483 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 484                 LDO_TurnOnLDO(LDO_LDO_SDIO3);
 485                 LDO_TurnOnLDO(LDO_LDO_VDD30);
 486 #elif (defined CONFIG_SC8830)
 487         #if defined(CONFIG_SPX30G2)
 488                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 489                 {
 490                         LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 491                         LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 492                 }
 493                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 494                 {
 495                 /*
 496                         for 2723
 497                         .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 498                         .id = LDO_LDO_SDIO1, .name = "vddsdio",
 499                         sharkl no need open vddsdio.
 500                         if need,turn on vddsdio
 501                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 502                 */
 503                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 504                         LDO_TurnOnLDO(LDO_LDO_SDIO0);
 505                 }
 506
 507         #elif (defined CONFIG_SPX20)
 508                         if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 509                         {
 510                                 LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 511                                 LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 512                         }
 513                         else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 514                         {
 515                                 printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
 516                                 LDO_TurnOnLDO(LDO_LDO_SDIO0);
 517                                 LDO_TurnOnLDO(LDO_LDO_SDIO1);
 518                         }
 519         #else
 520                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 521                 {
 522                         LDO_TurnOnLDO(LDO_LDO_SDIO3);
 523                 }
 524                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 525                 {
 526                         printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
 527                         LDO_TurnOnLDO(LDO_LDO_SDIO0);
 528                 }
 529         #endif
 530 #elif (defined CONFIG_SC9630)
 531                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 532                 {
 533                         LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 534                         LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 535                 }
 536                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 537                 {
 538
 539                 /*
 540                         for 2723
 541                         .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 542                         .id = LDO_LDO_SDIO1, .name = "vddsdio",
 543                         sharkl no need open vddsdio.
 544                         if need,turn on vddsdio
 545                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 546                 */
 547                         #if defined(CONFIG_SP9830IEA_5M_H100)
 548                                 LDO_TurnOnLDO(LDO_LDO_SDIO1);
 549                                 LDO_TurnOnLDO(LDO_LDO_SDIO0);
 550                         #else
 551                                 LDO_TurnOnLDO(LDO_LDO_SDIO0);
 552                         #endif
 553                 }
 554 #else
 555                 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler)
 556                 {
 557                         LDO_TurnOnLDO(LDO_LDO_SDIO0);
 558                 }else
 559                 {
 560                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 561                         LDO_TurnOnLDO(LDO_LDO_SIM2);
 562                 }
 563 #endif
 564     }
 565     else  // power off
 566     {
 567 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 568                 LDO_TurnOffLDO(LDO_LDO_SDIO3);
 569                 LDO_TurnOffLDO(LDO_LDO_VDD30);
 570 #elif defined (CONFIG_SC8830)
 571         #if defined(CONFIG_SPX30G2)
 572                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 573                 {
 574                         LDO_TurnOffLDO(LDO_LDO_EMMCCORE);
 575                         LDO_TurnOffLDO(LDO_LDO_EMMCIO);
 576                 }
 577                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 578                 {
 579                         LDO_TurnOffLDO(LDO_LDO_SDIO0);
 580                         LDO_TurnOffLDO(LDO_LDO_SDIO1);
 581                         /*
 582                                 for 2723
 583                                 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 584                                 .id = LDO_LDO_SDIO1, .name = "vddsdio",
 585                                 sharkl no need open vddsdio.
 586                                 if need,turn off vddsdio
 587                                 LDO_TurnOffLDO(LDO_LDO_SDIO1);
 588                         */
 589                 }
 590
 591         #elif (defined CONFIG_SPX20)
 592                          if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 593                          {
 594                                  LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 595                                  LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 596                          }
 597                       else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 598                          {
 599                                   printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
 600                                   LDO_TurnOnLDO(LDO_LDO_SDIO0);
 601                                   LDO_TurnOnLDO(LDO_LDO_SDIO1);
 602                          }
 603
 604
 605         #else
 606                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 607                 {
 608                         LDO_TurnOffLDO(LDO_LDO_SDIO3);
 609                 }
 610                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 611                 {
 612                         LDO_TurnOffLDO(LDO_LDO_SDIO0);
 613                 }
 614         #endif
 615 #elif (defined CONFIG_SC9630)
 616                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 617                 {
 618                         LDO_TurnOffLDO(LDO_LDO_EMMCCORE);
 619                         LDO_TurnOffLDO(LDO_LDO_EMMCIO);
 620                 }
 621                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 622                 {
 623                         LDO_TurnOffLDO(LDO_LDO_SDIO0);
 624                         /*
 625                                 for 2723
 626                                 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 627                                 .id = LDO_LDO_SDIO1, .name = "vddsdio",
 628                                 sharkl no need open vddsdio.
 629                                 if need,turn off vddsdio
 630                                 LDO_TurnOffLDO(LDO_LDO_SDIO1);
 631                         */
 632                 }
 633 #else
 634                 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
 635                         LDO_TurnOffLDO (LDO_LDO_SDIO0);
 636                 }else
 637                 {
 638                 LDO_TurnOffLDO (LDO_LDO_SDIO1);
 639                 LDO_TurnOffLDO (LDO_LDO_SIM2);
 640                 }
 641 #endif
 642     }
 643
 644 #else // no defined(PLATFORM_SC8800G)
 645
 646     switch (on_off)
 647     {
 648         case POWR_ON:
 649             {
 650                 sdhost_handler->host_cfg->HOST_CTL0 |= (0x1<<8);
 651             }
 652             break;
 653
 654         case POWR_OFF:
 655             {
 656                 sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x1<<8));
 657             }
 658             break;
 659
 660         default:
 661             {
 662                 SCI_ASSERT (0);/*assert verified*/
 663             }
 664             break;
 665     }
 666
 667 #endif
 668 #endif
 669 }
 670 //---Block Gap Control Register---
 671 /*****************************************************************************/
 672 //  Description:  Set the position of break point
 673 //  Author: Jason.wu
 674 //  Param
 675 //      sdhost_handler: the handle of host driver
 676 //  Return:
 677 //      NONE
 678 //  Note:
 679 /*****************************************************************************/
 680 PUBLIC void SDHOST_BlkGapIntPosSet (SDHOST_HANDLE sdhost_handler)
 681 {
 682     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 683
 684 }
 685
 686 /*****************************************************************************/
 687 //  Description:  Enable pause function of host. the card must support this function,then this function can be worked
 688 //  Author: Jason.wu
 689 //  Param
 690 //      sdhost_handler: the handle of host driver
 691 //  Return:
 692 //      NONE
 693 //  Note:
 694 /*****************************************************************************/
 695 PUBLIC void SDHOST_EnableReadWaitCtl (SDHOST_HANDLE sdhost_handler)
 696 {
 697     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 698
 699     sdhost_handler->host_cfg->HOST_CTL0 |= BIT_18;
 700 }
 701
 702 /*****************************************************************************/
 703 //  Description:  Set break point during the transmition
 704 //  Author: Jason.wu
 705 //  Param
 706 //      sdhost_handler: the handle of host driver
 707 //  Return:
 708 //      NONE
 709 //  Note:
 710 /*****************************************************************************/
 711 PUBLIC void SDHOST_StopAtBlkGap (SDHOST_HANDLE sdhost_handler)
 712 {
 713     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 714
 715     sdhost_handler->host_cfg->HOST_CTL0 |= (BIT_16);
 716 }
 717 PUBLIC void SDHOST_ClearBlkGap (SDHOST_HANDLE sdhost_handler)
 718 {
 719     sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x01<<16));
 720 }
 721 PUBLIC void SDHOST_BlkGapIntEn (SDHOST_HANDLE sdhost_handler)
 722 {
 723     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler)); /*assert verified*/
 724
 725     sdhost_handler->host_cfg->HOST_CTL0 |= (BIT_19);
 726 }
 727 PUBLIC uint32 SDHOST_GetTransStat (SDHOST_HANDLE sdhost_handler)
 728 {
 729     return (sdhost_handler->host_cfg->PRESENT_STAT & (BIT_8|BIT_9));
 730 }
 731
 732 /*****************************************************************************/
 733 //  Description:  When transmission is paused ,this function can resume the transmission
 734 //  Author: Jason.wu
 735 //  Param
 736 //      sdhost_handler: the handle of host driver
 737 //  Return:
 738 //      NONE
 739 //  Note:
 740 /*****************************************************************************/
 741 PUBLIC void SDHOST_Continue (SDHOST_HANDLE sdhost_handler)
 742 {
 743     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 744
 745     sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x03<<16));
 746     sdhost_handler->host_cfg->HOST_CTL0 |= BIT_17;
 747
 748 }
 749
 750
 751
 752 //----Clock Control Register---
 753 /*****************************************************************************/
 754 //  Description:  Open or close internal clk.when this clk is disable ,the host will enter in sleep mode
 755 //  Author: Jason.wu
 756 //  Param
 757 //      sdhost_handler: the handle of host driver
 758 //      onoff:
 759 //  Return:
 760 //      NONE
 761 //  Note:
 762 /*****************************************************************************/
 763 PUBLIC void SDHOST_internalClk_OnOff (SDHOST_HANDLE sdhost_handler,SDHOST_CLK_ONOFF_E onoff)
 764 {
 765     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 766
 767     switch (onoff)
 768     {
 769         case CLK_ON:
 770             {
 771                 uint32 timeout;
 772                 //Enable internal clock
 773                 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_0;
 774                 timeout = 30;
 775                 while ((0 == (sdhost_handler->host_cfg->HOST_CTL1 & BIT_1)) && timeout)
 776                 {
 777                    SDHOST_Delayus(100);
 778                     timeout--;
 779                 }
 780             }
 781             break;
 782
 783         case CLK_OFF:
 784             {
 785                 sdhost_handler->host_cfg->HOST_CTL1 &= (~BIT_0);
 786                 SDHOST_Delayus(200);
 787             }
 788             break;
 789
 790         default:
 791             {
 792                 SCI_ASSERT (0);/*assert verified*/
 793             }
 794             break;
 795     }
 796 }
 797
 798 /*****************************************************************************/
 799 //  Description:  Open or close card clk.
 800 //  Author: Jason.wu
 801 //  Param
 802 //      sdhost_handler: the handle of host driver
 803 //      onoff:
 804 //  Return:
 805 //      NONE
 806 //  Note:
 807 /*****************************************************************************/
 808 PUBLIC void SDHOST_SD_clk_OnOff (SDHOST_HANDLE sdhost_handler,SDHOST_CLK_ONOFF_E onoff)
 809 {
 810     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 811
 812     switch (onoff)
 813     {
 814         case CLK_ON:
 815             {
 816                 //Enable internal clock
 817                 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_2;
 818             }
 819             break;
 820
 821         case CLK_OFF:
 822             {
 823                 if ((sdhost_handler->host_cfg->HOST_CTL1 & BIT_2) != 0) {
 824                     sdhost_handler->host_cfg->HOST_CTL1 &= (~BIT_2);
 825                     SDHOST_Delayus(200);
 826                 }
 827             }
 828             break;
 829
 830         default:
 831             {
 832                 SCI_ASSERT (0);/*assert verified*/
 833             }
 834             break;
 835     }
 836 }
 837
 838 /*****************************************************************************/
 839 //  Description:  Set the frequence of Card clock
 840 //  Author: Jason.wu
 841 //  Param
 842 //      sdhost_handler: the handle of host driver
 843 //      sdio_clk: the frequence of card working clock
 844 //  Return:
 845 //      uint32 value : the frequency that be used acctually
 846 //  Note:
 847 /*****************************************************************************/
 848 PUBLIC uint32 SDHOST_SD_Clk_Freq_Set (SDHOST_HANDLE sdhost_handler,uint32 sdio_clk)
 849 {
 850     volatile uint32 tmpReg;
 851     uint32 clkDiv;
 852
 853     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 854     SCI_ASSERT (0 != sdio_clk);/*assert verified*/
 855
 856     sdio_clk = (sdio_clk > SDIO_SD_MAX_CLK) ? (SDIO_SD_MAX_CLK) : (sdio_clk);
 857
 858     //SDCLK Frequency Select ,Configure SDCLK select
 859     clkDiv = sdhost_handler->baseClock/sdio_clk;
 860 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
 861     clkDiv /= 2;
 862 #endif
 863     if (0 != sdhost_handler->baseClock%sdio_clk)
 864     {
 865         clkDiv++;
 866     }
 867
 868     SDHOST_PRINT ( ("   clkDiv: %d, sdio_clk:%d, baseClock:%d\n",clkDiv, sdio_clk, sdhost_handler->baseClock));
 869
 870     tmpReg = sdhost_handler->host_cfg->HOST_CTL1;
 871 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
 872     clkDiv--;
 873     tmpReg &= (~ (0x3ff<<6));
 874     tmpReg |= ((clkDiv>>8)&0x3)<<6;
 875     tmpReg |= (clkDiv&0xff)<<8;
 876     sdhost_handler->sdClock = sdhost_handler->baseClock/(2*(clkDiv+1));
 877 #else
 878     tmpReg &= (~ (0xff<<8));
 879     if (256 < clkDiv)
 880     {
 881         SDHOST_PRINT ( ("   clkDiv: %d is too big!!!!!",clkDiv));
 882         SCI_ASSERT (0);/*assert to do*/
 883     }
 884     else if (128 < clkDiv)
 885     {
 886         clkDiv = 256;
 887         tmpReg |= (0x80 << 8);
 888     }
 889     else if (64 < clkDiv)
 890     {
 891         clkDiv = 128;
 892         tmpReg |= (0x40<<8);
 893     }
 894     else if (32 < clkDiv)
 895     {
 896         clkDiv = 64;
 897         tmpReg |= (0x20<<8);
 898     }
 899     else if (16 < clkDiv)
 900     {
 901         clkDiv = 32;
 902         tmpReg |= (0x10<<8);
 903     }
 904     else if (8 < clkDiv)
 905     {
 906         clkDiv = 16;
 907         tmpReg |= (0x8<<8);
 908     }
 909     else if (4 < clkDiv)
 910     {
 911         clkDiv = 8;
 912         tmpReg |= (0x4<<8);
 913     }
 914     else if (2 < clkDiv)
 915     {
 916         clkDiv = 4;
 917         tmpReg |= (0x2<<8);
 918     }
 919     else if (1 < clkDiv)
 920     {
 921         clkDiv = 2;
 922         tmpReg |= (0x1<<8);
 923     }
 924     else if (0 < clkDiv)
 925     {
 926         clkDiv = 1;
 927         //nothing
 928     }
 929     else //if (0 == clkDiv)
 930     {
 931         SCI_ASSERT (0);/*assert to do*/
 932     }
 933     sdhost_handler->sdClock = sdhost_handler->baseClock/clkDiv;
 934 #endif
 935
 936     sdhost_handler->host_cfg->HOST_CTL1 = tmpReg;
 937     SDHOST_PRINT ( ("sd clk: %d KHz.",sdhost_handler->sdClock/1000));
 938
 939     return sdhost_handler->sdClock;
 940 }
 941
 942 //---Timeout Control Register--
 943 /*****************************************************************************/
 944 //  Description:  Set timeout value ,this value is used during the data transmission
 945 //  Author: Jason.wu
 946 //  Param
 947 //      sdhost_handler: the handle of host driver
 948 //      clk_cnt: the value is (2 ^ (clkcnt+13))*T_BSCLK,T_BSCLK is working frequence of host
 949 //  Return:
 950 //      NONE
 951 //  Note:
 952 /*****************************************************************************/
 953 PUBLIC void SDHOST_SetDataTimeOutValue (SDHOST_HANDLE sdhost_handler,uint8 clk_cnt) // (2 ^ (clkcnt+13))*T_BSCLK
 954 {
 955     volatile uint32 tmpReg,tmpIntReg;
 956
 957     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 958
 959     tmpIntReg = sdhost_handler->host_cfg->INT_STA_EN;
 960     // cfg the data timeout clk----------
 961     sdhost_handler->host_cfg->INT_STA_EN &= ~BIT_20;
 962
 963     tmpReg = sdhost_handler->host_cfg->HOST_CTL1;
 964     tmpReg &= ~ (0xF << 16);
 965     tmpReg |= (clk_cnt << 16);
 966     sdhost_handler->host_cfg->HOST_CTL1 = tmpReg;
 967
 968     sdhost_handler->host_cfg->INT_STA_EN = tmpIntReg;
 969 }
 970
 971 //---Software Reset Register---
 972 /*****************************************************************************/
 973 //  Description: Reset data line of host
 974 //  Author: Jason.wu
 975 //  Param
 976 //      sdhost_handler: the handle of host driver
 977 //  Return:
 978 //      NONE
 979 //  Note:
 980 /*****************************************************************************/
 981 LOCAL void _Reset_DAT (SDHOST_HANDLE sdhost_handler)
 982 {
 983     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 984
 985     sdhost_handler->host_cfg->HOST_CTL1 |= BIT_26;
 986
 987     while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & BIT_26)) {}
 988 }
 989 /*****************************************************************************/
 990 //  Description: Reset command line of host
 991 //  Author: Jason.wu
 992 //  Param
 993 //      sdhost_handler: the handle of host driver
 994 //  Return:
 995 //      NONE
 996 //  Note:
 997 /*****************************************************************************/
 998 LOCAL void _Reset_CMD (SDHOST_HANDLE sdhost_handler)
 999 {
1000     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1001
1002     sdhost_handler->host_cfg->HOST_CTL1 |= BIT_25;
1003
1004     while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & BIT_25)) {}
1005 }
1006
1007 /*****************************************************************************/
1008 //  Description: Reset command line and data line of host
1009 //  Author: Jason.wu
1010 //  Param
1011 //      sdhost_handler: the handle of host driver
1012 //  Return:
1013 //      NONE
1014 //  Note:
1015 /*****************************************************************************/
1016 LOCAL void _Reset_DAT_CMD (SDHOST_HANDLE sdhost_handler)
1017 {
1018     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1019
1020     sdhost_handler->host_cfg->HOST_CTL1 |= (BIT_25|BIT_26);
1021
1022     while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & (BIT_25|BIT_26))) {}
1023
1024
1025 }
1026
1027 /*****************************************************************************/
1028 //  Description: Reset all the module of host
1029 //  Author: Jason.wu
1030 //  Param
1031 //      sdhost_handler: the handle of host driver
1032 //  Return:
1033 //      NONE
1034 //  Note:
1035 /*****************************************************************************/
1036 LOCAL void _Reset_ALL (SDHOST_HANDLE sdhost_handler)
1037 {
1038     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1039
1040     sdhost_handler->host_cfg->HOST_CTL1 |= BIT_24;
1041
1042     while (0 != (sdhost_handler->host_cfg->HOST_CTL1 & BIT_24)) {}
1043
1044 }
1045
1046 /*****************************************************************************/
1047 //  Description: Reset  module of host
1048 //  Author: Wenjun.Shi
1049 //  Param
1050 //      sdhost_handler: the handle of host driver
1051 //  Return:
1052 //      NONE
1053 //  Note:
1054 /*****************************************************************************/
1055 LOCAL  void SDHOST_Reset_Controller(SDHOST_SLOT_NO slot_NO)
1056 {
1057 #if   defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
1058         if (slot_NO == SDHOST_SLOT_6)
1059         {
1060                 REG32 (AHB_CTL0)     |= BIT_8;
1061                 REG32 (AHB_SOFT_RST) |= BIT_11;
1062                 SDHOST_Delayus(200);
1063                 REG32 (AHB_SOFT_RST) &=~BIT_11;
1064         }
1065         else if (slot_NO == SDHOST_SLOT_7)
1066         {
1067                 REG32 (AHB_CTL0)     |= BIT_11;
1068                 REG32 (AHB_SOFT_RST) |= BIT_14;
1069                 SDHOST_Delayus(200);
1070                 REG32 (AHB_SOFT_RST) &=~BIT_14;
1071         }
1072 #elif defined (CONFIG_SC8825)
1073         if (slot_NO == SDHOST_SLOT_6)
1074         {
1075                 REG32 (AHB_CTL0)     |= BIT_4;
1076                 REG32 (AHB_SOFT_RST) |= BIT_12;
1077                 REG32 (AHB_SOFT_RST) &= ~BIT_12;
1078         }
1079         else if (slot_NO == SDHOST_SLOT_7)
1080         {
1081                 REG32 (AHB_CTL0)     |= BIT_23;
1082                 REG32 (AHB_SOFT_RST) |= BIT_21;
1083                 REG32 (AHB_SOFT_RST) &= ~BIT_21;
1084         }
1085 #elif defined(CONFIG_SC7710G2)
1086         REG32 (AHB_CTL6)          |= BIT_2;
1087         REG32 (AHB_SOFT2_RST) |= BIT_0;
1088         REG32 (AHB_SOFT2_RST) &= ~BIT_0;
1089 #else
1090 #define AHB_CTL0_SDIO0_EN       (BIT_4)
1091 #define AHB_CTL0_SDIO1_EN       (BIT_19)
1092
1093 #define AHB_CTL0_SDIO0_RST      (BIT_12)
1094 #define AHB_CTL0_SDIO1_RST      (BIT_16)
1095
1096         if(slot_NO == SDHOST_SLOT_0)
1097         {
1098                 REG32 (AHB_CTL0) |= AHB_CTL0_SDIO0_EN;
1099                 REG32 (AHB_SOFT_RST) |= AHB_CTL0_SDIO0_RST;
1100                 REG32 (AHB_SOFT_RST) &= ~AHB_CTL0_SDIO0_RST;
1101         }else if(slot_NO == SDHOST_SLOT_1)
1102         {
1103                 REG32 (AHB_CTL0) |= AHB_CTL0_SDIO1_EN;
1104                 REG32 (AHB_SOFT_RST) |= AHB_CTL0_SDIO1_RST;
1105                 REG32 (AHB_SOFT_RST) &= ~AHB_CTL0_SDIO1_RST;
1106         }
1107                 // select slot 0
1108 #endif
1109
1110
1111 }
1112
1113 LOCAL void _Reset_MODULE (SDHOST_HANDLE sdhost_handler)
1114 {
1115     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1116
1117     if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
1118                 SDHOST_Reset_Controller(SDHOST_SLOT_0);
1119     } else if(&sdio_port_ctl[SDHOST_SLOT_1] == sdhost_handler){
1120                 SDHOST_Reset_Controller(SDHOST_SLOT_1);
1121     }
1122     else if(&sdio_port_ctl[SDHOST_SLOT_6] == sdhost_handler){
1123                 SDHOST_Reset_Controller(SDHOST_SLOT_6);
1124     }
1125     else if(&sdio_port_ctl[SDHOST_SLOT_7] == sdhost_handler){
1126                 SDHOST_Reset_Controller(SDHOST_SLOT_7);
1127     }
1128
1129 }
1130
1131 /*****************************************************************************/
1132 //  Description: Reset the specify module of host
1133 //  Author: Jason.wu
1134 //  Param
1135 //      sdhost_handler: the handle of host driver
1136 //      rst_type: indicate which module will be reset(command lin\data line\all the module)
1137 //  Return:
1138 //      NONE
1139 //  Note:
1140 /*****************************************************************************/
1141 PUBLIC void SDHOST_RST (SDHOST_HANDLE sdhost_handler,SDHOST_RST_TYPE_E rst_type)
1142 {
1143     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1144
1145     switch (rst_type)
1146     {
1147         case RST_CMD_LINE:
1148             {
1149                 _Reset_CMD (sdhost_handler);
1150             }
1151             break;
1152
1153         case RST_DAT_LINE:
1154             {
1155                 _Reset_DAT (sdhost_handler);
1156             }
1157             break;
1158
1159         case RST_CMD_DAT_LINE:
1160             {
1161                 _Reset_DAT_CMD (sdhost_handler);
1162             }
1163             break;
1164
1165         case RST_ALL:
1166             {
1167                 SDHOST_SD_clk_OnOff(sdhost_handler, CLK_OFF);
1168                 _Reset_ALL (sdhost_handler);
1169             }
1170             break;
1171
1172         case RST_MODULE:
1173             {
1174                 SDHOST_SD_clk_OnOff(sdhost_handler, CLK_OFF);
1175                 _Reset_MODULE (sdhost_handler);
1176             }
1177             break;
1178         default:
1179             {
1180                 SCI_ASSERT (0);/*assert verified*/
1181             }
1182             break;
1183     }
1184 }
1185
1186 /*****************************************************************************/
1187 //  Description: Set block size \count of block\and Dma Buffer size
1188 //  Author: Jason.wu
1189 //  Param
1190 //      sdhost_handler: the handle of host driver
1191 //      block_size: size of block( 0 <= block size <=0x0800)
1192 //      block_cnt: the count of block(0 <= block_cnt <= 0xFFFF)
1193 //      DMAsize:buffer size of DMA(4K,8K,16K,32K,64K,128K,256K,512K)
1194 //  Return:
1195 //      NONE
1196 //  Note:
1197 /*****************************************************************************/
1198 PUBLIC void SDHOST_SetDataParam (SDHOST_HANDLE sdhost_handler,uint32 block_size,uint32 block_cnt,SDHOST_DMA_BUF_SIZE_E DMAsize)
1199 {
1200     volatile uint32 tmpReg;
1201
1202     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1203     SCI_ASSERT (0x1000 >= block_size);/*assert verified*/
1204     SCI_ASSERT (0xFFFF >= block_cnt);/*assert verified*/
1205
1206     tmpReg = sdhost_handler->host_cfg->BLK_SIZE_COUNT;
1207
1208     // Set Block Size
1209     tmpReg &= (~BIT_15);
1210     tmpReg &= (~ (0xFFF));
1211     if (0x1000 == block_size)
1212     {
1213         tmpReg |= BIT_15;
1214     }
1215     else
1216     {
1217         tmpReg |= block_size;
1218     }
1219
1220     // Set Block Cnt
1221     tmpReg &= (~0xFFFF0000);
1222     tmpReg |= (block_cnt << 16);
1223
1224     // Set DMA Buf Size
1225     tmpReg &= (~ (0x07<<12));
1226
1227     switch (DMAsize)
1228     {
1229         case SDIO_DMA_4K:
1230             {
1231                 //do nothing
1232             }
1233             break;
1234
1235         case SDIO_DMA_8K:
1236             {
1237                 tmpReg |= (0x01<<12);
1238             }
1239             break;
1240
1241         case SDIO_DMA_16K:
1242             {
1243                 tmpReg |= (0x02<<12);
1244             }
1245             break;
1246
1247         case SDIO_DMA_32K:
1248             {
1249                 tmpReg |= (0x03<<12);
1250             }
1251             break;
1252
1253         case SDIO_DMA_64K:
1254             {
1255                 tmpReg |= (0x04<<12);
1256             }
1257             break;
1258
1259         case SDIO_DMA_128K:
1260             {
1261                 tmpReg |= (0x05<<12);
1262             }
1263             break;
1264
1265         case SDIO_DMA_256K:
1266             {
1267                 tmpReg |= (0x06<<12);
1268             }
1269             break;
1270
1271         case SDIO_DMA_512K:
1272             {
1273                 tmpReg |= (0x07<<12);
1274             }
1275             break;
1276
1277         default:
1278             {
1279                 SCI_ASSERT (0);/*assert verified*/
1280             }
1281             break;
1282
1283     }
1284     sdhost_handler->host_cfg->BLK_SIZE_COUNT = tmpReg;
1285 }
1286
1287 PUBLIC void SDHOST_GetDataParam (SDHOST_HANDLE sdhost_handler,uint32 *block_size,uint32 *block_cnt, uint32 *dmaAddr)
1288 {
1289     uint32 sizecnt;
1290
1291     sizecnt = sdhost_handler->host_cfg->BLK_SIZE_COUNT;
1292     *block_size = sizecnt&0xFFF;
1293     *block_cnt  = ( (sizecnt&0xFFFF0000) >>16);
1294     *dmaAddr    = sdhost_handler->host_cfg->DMA_SYS_ADD;
1295 }
1296
1297 /*****************************************************************************/
1298 //  Description: Set start address of DMA buffer
1299 //  Author: Jason.wu
1300 //  Param
1301 //      sdhost_handler: the handle of host driver
1302 //      dmaAddr: start address of DMA buffer
1303 //  Return:
1304 //      NONE
1305 //  Note:
1306 /*****************************************************************************/
1307 PUBLIC void SDHOST_SetDmaAddr (SDHOST_HANDLE sdhost_handler, uint32 dmaAddr)
1308 {
1309     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1310
1311     sdhost_handler->host_cfg->DMA_SYS_ADD = dmaAddr;
1312
1313 }
1314
1315 /*****************************************************************************/
1316 //  Description: Get stop address of DMA buffer,when buffer is used ,the dma will stop at last address of buffer.this function will get this address
1317 //  Author: Jason.wu
1318 //  Param
1319 //      sdhost_handler: the handle of host driver
1320 //  Return:
1321 //      uint32 value: address that DMA stoped at
1322 //  Note:
1323 /*****************************************************************************/
1324 PUBLIC uint32 SDHOST_GetDmaAddr (SDHOST_HANDLE sdhost_handler)
1325 {
1326     uint32 dmaAddr;
1327
1328     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1329
1330     dmaAddr = sdhost_handler->host_cfg->DMA_SYS_ADD;
1331     return dmaAddr;
1332 }
1333 //---Argument Register---
1334 /*****************************************************************************/
1335 //  Description: Set the argument of command
1336 //  Author: Jason.wu
1337 //  Param
1338 //      sdhost_handler: the handle of host driver
1339 //      argument
1340 //  Return:
1341 //      NONE
1342 //  Note:
1343 /*****************************************************************************/
1344 PUBLIC void SDHOST_SetCmdArg (SDHOST_HANDLE sdhost_handler,uint32 argument)
1345 {
1346     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1347
1348     sdhost_handler->host_cfg->CMD_ARGUMENT = argument;
1349 }
1350
1351 //---CMD Register---
1352 /*****************************************************************************/
1353 //  Description: Set the mode of command
1354 //  Author: Jason.wu
1355 //  Param
1356 //      sdhost_handler: the handle of host driver
1357 //      cmdIndex:   command
1358 //      transmode:  transfer mode
1359 //      cmd_type:   comand type ,it may be normal comman ,resume comman etc.
1360 //      Response:   the inspect response from card. if this comman is performed by card successly ,this response will be return by card
1361 //  Return:
1362 //      NONE
1363 //  Note:
1364 /*****************************************************************************/
1365 PUBLIC void SDHOST_SetCmd (SDHOST_HANDLE sdhost_handler,uint32 cmdIndex,uint32 transmode,SDHOST_CMD_TYPE_E cmd_type,CMD_RSP_TYPE_E Response)
1366 {
1367     volatile uint32 tmpReg;
1368
1369     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1370
1371     tmpReg = sdhost_handler->host_cfg->CMD_TRANSMODE;
1372     tmpReg &= (~ (0x7F|0x30000|0x3FF80000));
1373
1374     if (0 != (TRANS_MODE_ATA_CMPLETE_SIG_EN&transmode))
1375     {
1376         tmpReg |= SDIO_TRANS_COMP_ATA;
1377     }
1378
1379     if (0 != (TRANS_MODE_MULTI_BLOCK&transmode))
1380     {
1381         tmpReg |= SDIO_TRANS_MULTIBLK;
1382     }
1383
1384     if (0 != (TRANS_MODE_READ&transmode))
1385     {
1386         tmpReg |= SDIO_TRANS_DIR_READ;
1387     }
1388
1389     if (0 != (TRANS_MODE_CMD12_EN&transmode))
1390     {
1391         tmpReg |= SDIO_TRANS_AUTO_CMD12_EN;
1392     }
1393
1394     if (0 != (TRANS_MODE_BLOCK_COUNT_EN&transmode))
1395     {
1396         tmpReg |= SDIO_TRANS_BLK_CNT_EN;
1397     }
1398
1399     if (0 != (TRANS_MODE_DMA_EN&transmode))
1400     {
1401         tmpReg |= SDIO_TRANS_DMA_EN;
1402     }
1403
1404     if (0 != (CMD_HAVE_DATA&transmode))
1405     {
1406         tmpReg |= SDIO_CMD_DATA_PRESENT;
1407     }
1408
1409     switch (cmd_type)
1410     {
1411         case CMD_TYPE_NORMAL:
1412             {
1413                 tmpReg |= SDIO_CMD_TYPE_NML;
1414             }
1415             break;
1416
1417         case CMD_TYPE_SUSPEND:
1418             {
1419                 tmpReg |= SDIO_CMD_TYPE_SUSPEND;
1420             }
1421             break;
1422
1423         case CMD_TYPE_RESUME:
1424             {
1425                 tmpReg |= SDIO_CMD_TYPE_RESUME;
1426             }
1427             break;
1428
1429         case CMD_TYPE_ABORT:
1430             {
1431                 tmpReg |= SDIO_CMD_TYPE_ABORT;
1432             }
1433             break;
1434
1435         default:
1436             {
1437                 SCI_ASSERT (0);/*assert verified*/
1438             }
1439             break;
1440     }
1441
1442     switch (Response)
1443     {
1444         case CMD_NO_RSP:
1445             {
1446                 tmpReg |= SDIO_NO_RSP;
1447             }
1448             break;
1449
1450         case CMD_RSP_R1:
1451             {
1452                 tmpReg |= SDIO_R1;
1453             }
1454             break;
1455
1456         case CMD_RSP_R2:
1457             {
1458                 tmpReg |= SDIO_R2;
1459             }
1460             break;
1461
1462         case CMD_RSP_R3:
1463             {
1464                 tmpReg |= SDIO_R3;
1465             }
1466             break;
1467
1468         case CMD_RSP_R4:
1469             {
1470                 tmpReg |= SDIO_R4;
1471             }
1472             break;
1473
1474         case CMD_RSP_R5:
1475             {
1476                 tmpReg |= SDIO_R5;
1477             }
1478             break;
1479
1480         case CMD_RSP_R6:
1481             {
1482                 tmpReg |= SDIO_R6;
1483             }
1484             break;
1485
1486         case CMD_RSP_R7:
1487             {
1488                 tmpReg |= SDIO_R7;
1489             }
1490             break;
1491
1492         case CMD_RSP_R1B:
1493             {
1494                 tmpReg |= SDIO_R1B;
1495             }
1496             break;
1497
1498         case CMD_RSP_R5B:
1499             {
1500                 tmpReg |= SDIO_R5B;
1501             }
1502             break;
1503
1504         default:
1505             {
1506                 SCI_ASSERT (0);/*assert verified*/
1507             }
1508             break;
1509
1510     }
1511     tmpReg &= ~(0x7<<8);
1512     tmpReg |= (cmdIndex<<24);
1513
1514     sdhost_handler->host_cfg->CMD_TRANSMODE = tmpReg;
1515
1516 }
1517
1518
1519 //==
1520 /*****************************************************************************/
1521 //  Description: Get content from host response register
1522 //  Author: Jason.wu
1523 //  Param
1524 //      sdhost_handler: the handle of host driver
1525 //      Response:   the type of response
1526 //      rspBuf:     the content will be stored in this place
1527 //  Return:
1528 //      NONE
1529 //  Note:
1530 /*****************************************************************************/
1531 PUBLIC void SDHOST_GetRspFromBuf (SDHOST_HANDLE sdhost_handler,CMD_RSP_TYPE_E Response,uint8 *rspBuf)
1532 {
1533     uint32 tmpRspBuf[4];
1534     uint32 i;
1535
1536     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1537
1538     tmpRspBuf[0] = sdhost_handler->host_cfg->RSP0;
1539     tmpRspBuf[1] = sdhost_handler->host_cfg->RSP1;
1540     tmpRspBuf[2] = sdhost_handler->host_cfg->RSP2;
1541     tmpRspBuf[3] = sdhost_handler->host_cfg->RSP3;
1542
1543     //  SDHOST_PRINT(("RSP %x %x %x %x",tmpRspBuf[0],tmpRspBuf[1],tmpRspBuf[2],tmpRspBuf[3]));
1544
1545     for (i = 0; i < 4; i++)
1546     {
1547         rspBuf[0+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>24) &0xFF);
1548         rspBuf[1+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>16) &0xFF);
1549         rspBuf[2+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>8) &0xFF);
1550         rspBuf[3+ (i<<2) ] = (uint8) (tmpRspBuf[i]&0xFF);
1551     }
1552
1553     switch (Response)
1554     {
1555         case CMD_NO_RSP:
1556             break;
1557
1558         case CMD_RSP_R1:
1559         case CMD_RSP_R1B:
1560         case CMD_RSP_R3:
1561         case CMD_RSP_R4:
1562         case CMD_RSP_R5:
1563         case CMD_RSP_R6:
1564         case CMD_RSP_R7:
1565         case CMD_RSP_R5B:
1566             {
1567                 rspBuf[0] = (uint8) ( (tmpRspBuf[0]>>24) &0xFF);
1568                 rspBuf[1] = (uint8) ( (tmpRspBuf[0]>>16) &0xFF);
1569                 rspBuf[2] = (uint8) ( (tmpRspBuf[0]>>8) &0xFF);
1570                 rspBuf[3] = (uint8) (tmpRspBuf[0]&0xFF);
1571             }
1572             break;
1573
1574         case CMD_RSP_R2:
1575             {
1576                 rspBuf[0] = (uint8) ( (tmpRspBuf[3]>>16) &0xFF);
1577                 rspBuf[1] = (uint8) ( (tmpRspBuf[3]>>8) &0xFF);
1578                 rspBuf[2] = (uint8) (tmpRspBuf[3]&0xFF);
1579
1580                 rspBuf[3] = (uint8) ( (tmpRspBuf[2]>>24) &0xFF);
1581                 rspBuf[4] = (uint8) ( (tmpRspBuf[2]>>16) &0xFF);
1582                 rspBuf[5] = (uint8) ( (tmpRspBuf[2]>>8) &0xFF);
1583                 rspBuf[6] = (uint8) (tmpRspBuf[2]&0xFF);
1584
1585                 rspBuf[7] = (uint8) ( (tmpRspBuf[1]>>24) &0xFF);
1586                 rspBuf[8] = (uint8) ( (tmpRspBuf[1]>>16) &0xFF);
1587                 rspBuf[9] = (uint8) ( (tmpRspBuf[1]>>8) &0xFF);
1588                 rspBuf[10] = (uint8) (tmpRspBuf[1]&0xFF);
1589
1590                 rspBuf[11] = (uint8) ( (tmpRspBuf[0]>>24) &0xFF);
1591                 rspBuf[12] = (uint8) ( (tmpRspBuf[0]>>16) &0xFF);
1592                 rspBuf[13] = (uint8) ( (tmpRspBuf[0]>>8) &0xFF);
1593                 rspBuf[14] = (uint8) (tmpRspBuf[0]&0xFF);
1594             }
1595             break;
1596
1597         default:
1598             {
1599                 SCI_ASSERT (0);/*assert verified*/
1600             }
1601             break;
1602     }
1603
1604     return;
1605 }
1606
1607
1608 //====
1609
1610 //----
1611 /*****************************************************************************/
1612 //  Description: Get function that host can be support
1613 //  Author: Jason.wu
1614 //  Param
1615 //      sdhost_handler: the handle of host driver
1616 //      capbility
1617 //  Return:
1618 //      NONE
1619 //  Note:
1620 /*****************************************************************************/
1621 LOCAL void _GetSDHOSTCapbility (SDHOST_HANDLE sdhost_handler,SDHOST_CAPBILIT_T *capbility)
1622 {
1623     volatile uint32 tmpReg;
1624     SCI_MEMSET (capbility,0,sizeof (SDHOST_CAPBILIT_T));
1625
1626     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1627
1628     tmpReg = sdhost_handler->host_cfg->CAPBILITY;
1629
1630     if (0 != (tmpReg &  BIT_26))
1631     {
1632         capbility->capbility_function |= CAP_VOL_1_8V;
1633     }
1634
1635     if (0 != (tmpReg &  BIT_25))
1636     {
1637         capbility->capbility_function |= CAP_VOL_3_0V;
1638     }
1639
1640     if (0 != (tmpReg &  BIT_24))
1641     {
1642         capbility->capbility_function |= CAP_VOL_3_3V;
1643     }
1644
1645     if (0 != (tmpReg &  BIT_23))
1646     {
1647         capbility->capbility_function |= SPD_RESU;
1648     }
1649
1650     if (0 != (tmpReg &  BIT_22))
1651     {
1652         capbility->capbility_function |= DMA_SPT;
1653     }
1654
1655     if (0 != (tmpReg &  BIT_21))
1656     {
1657         capbility->capbility_function |= HIGH_SPEED;
1658     }
1659
1660     switch (tmpReg & (0x3<<16))
1661     {
1662         case (0x00<<16) :
1663             capbility->cability_Max_BlkLen = 512;
1664             break;
1665
1666         case (0x01<<16) :
1667             capbility->cability_Max_BlkLen = 1024;
1668             break;
1669
1670         case (0x02<<16) :
1671             capbility->cability_Max_BlkLen = 2048;
1672             break;
1673
1674         case (0x03<<16) :
1675             capbility->cability_Max_BlkLen = 4096;
1676             break;
1677
1678         default:
1679             SCI_ASSERT (0);/*assert verified*/
1680             break;
1681     }
1682
1683     capbility->sd_Base_Max_Clk = ( (tmpReg & (0x3F<<8)) >>8) * 1000000;
1684
1685     if (0!= (tmpReg & BIT_7))
1686     {
1687         capbility->timeOut_Clk_unit = 1000000;
1688     }
1689     else
1690     {
1691         capbility->timeOut_Clk_unit = 1000;
1692     }
1693
1694     capbility->timeOut_Base_Clk = (tmpReg & 0x3F) *capbility->timeOut_Clk_unit;
1695
1696     tmpReg = sdhost_handler->host_cfg->CURR_CAPBILITY;
1697     capbility->max_current_for_1_8 = ( (tmpReg & (0xFF<<16)) >>16);
1698     capbility->max_current_for_3_0 = ( (tmpReg & (0xFF<<8)) >>8);
1699     capbility->max_current_for_3_3 = (tmpReg & 0xFF);
1700
1701     SDHOST_PRINT ( ("capbility_function = %x",sdhost_handler->capbility.capbility_function));
1702     SDHOST_PRINT ( ("cability_Max_BlkLen = %x",sdhost_handler->capbility.cability_Max_BlkLen));
1703     SDHOST_PRINT ( ("sd_Base_Max_Clk = %x",sdhost_handler->capbility.sd_Base_Max_Clk));
1704     SDHOST_PRINT ( ("timeOut_Clk_unit = %x",sdhost_handler->capbility.timeOut_Clk_unit));
1705     SDHOST_PRINT ( ("timeOut_Base_Clk = %x",sdhost_handler->capbility.timeOut_Base_Clk));
1706     SDHOST_PRINT ( ("max_current_for_1_8 = %x",sdhost_handler->capbility.max_current_for_1_8));
1707     SDHOST_PRINT ( ("max_current_for_3_0 = %x",sdhost_handler->capbility.max_current_for_3_0));
1708     SDHOST_PRINT ( ("max_current_for_3_3 = %x",sdhost_handler->capbility.max_current_for_3_3));
1709 }
1710
1711
1712 /*****************************************************************************/
1713 //  Description: Clear Normal int Status register ,if event is happed ,host will Set status in register
1714 //  Author: Jason.wu
1715 //  Param
1716 //      sdhost_handler: the handle of host driver
1717 //      err_msg:        that int you want to clear
1718 //  Return:
1719 //      NONE
1720 //  Note:
1721 /*****************************************************************************/
1722 PUBLIC void SDHOST_NML_IntStatus_Clr (SDHOST_HANDLE sdhost_handler,uint32 msg)
1723 {
1724     volatile uint32 tmpReg = 0;
1725     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1726
1727     if (0 != (msg&SIG_ERR))
1728     {
1729         //_ERR_IntStatus_Clr (sdhost_handler,ERR_ALL);
1730         tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
1731                    BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
1732
1733     }
1734
1735     if (0 != (msg&SIG_CARD_IN))
1736     {
1737         //sdhost_handler->host_cfg->INT_STA =BIT_8;
1738     }
1739
1740     if (0 != (msg&SIG_CARD_INSERT))
1741     {
1742                 tmpReg |= BIT_6;
1743     }
1744
1745     if (0 != (msg&SIG_CARD_REMOVE))
1746     {
1747                 tmpReg |= BIT_7;
1748     }
1749
1750     if (0 != (msg&SIG_BUF_RD_RDY))
1751     {
1752                 tmpReg |= BIT_5;
1753     }
1754
1755     if (0 != (msg&SIG_BUF_WD_RDY))
1756     {
1757                 tmpReg |= BIT_4;
1758     }
1759
1760     if (0 != (msg&SIG_DMA_INT))
1761     {
1762                 tmpReg |= BIT_3;
1763     }
1764
1765     if (0 != (msg&SIG_BLK_CAP))
1766     {
1767                 tmpReg |= BIT_2;
1768     }
1769
1770     if (0 != (msg&SIG_TRANS_CMP))
1771     {
1772                 tmpReg |= BIT_1;
1773     }
1774
1775     if (0 != (msg&SIG_CMD_CMP))
1776     {
1777                 tmpReg |= BIT_0;
1778     }
1779     sdhost_handler->host_cfg->INT_STA = tmpReg;
1780 }
1781
1782 /*****************************************************************************/
1783 //  Description: Enable Normal int Signal register ,
1784 //  Author: Jason.wu
1785 //  Param
1786 //      sdhost_handler: the handle of host driver
1787 //      err_msg:        that int you want to Enable
1788 //  Return:
1789 //      NONE
1790 //  Note:
1791 /*****************************************************************************/
1792 PUBLIC void SDHOST_NML_IntStatus_En (SDHOST_HANDLE sdhost_handler,uint32 msg)
1793 {
1794     volatile uint32 tmpReg = 0;
1795     uint32 err_msg;
1796     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1797
1798     if (0 != (msg&SIG_ERR))
1799     {
1800         //_ERR_IntStatus_En (sdhost_handler,sdhost_handler->err_filter);
1801         err_msg = sdhost_handler->err_filter;
1802         if (0 != (err_msg&ERR_RSP))
1803         {
1804                 tmpReg |= BIT_28;
1805         }
1806
1807         if (0 != (err_msg&ERR_CMD12))
1808         {
1809                 tmpReg |= BIT_24;
1810         }
1811
1812         if (0 != (err_msg&ERR_CUR_LIMIT))
1813         {
1814                 tmpReg |= BIT_23;
1815         }
1816
1817         if (0 != (err_msg&ERR_DATA_END))
1818         {
1819                 tmpReg |= BIT_22;
1820         }
1821
1822         if (0 != (err_msg&ERR_DATA_CRC))
1823         {
1824                 tmpReg |= BIT_21;
1825         }
1826
1827         if (0 != (err_msg&ERR_DATA_TIMEOUT))
1828         {
1829                 tmpReg |= BIT_20;
1830         }
1831
1832         if (0 != (err_msg&ERR_CMD_INDEX))
1833         {
1834                 tmpReg |= BIT_19;
1835         }
1836
1837         if (0 != (err_msg&ERR_CMD_END))
1838         {
1839                 tmpReg |= BIT_18;
1840         }
1841
1842         if (0 != (err_msg&ERR_CMD_CRC))
1843         {
1844                 tmpReg |= BIT_17;
1845         }
1846
1847         if (0 != (err_msg&ERR_CMD_TIMEOUT))
1848         {
1849                 tmpReg |= BIT_16;
1850         }
1851
1852     }
1853
1854     if (0 != (msg&SIG_CARD_IN))
1855     {
1856                 tmpReg |= BIT_8;
1857     }
1858
1859     if (0 != (msg&SIG_CARD_INSERT))
1860     {
1861                 tmpReg |= BIT_6;
1862     }
1863
1864     if (0 != (msg&SIG_CARD_REMOVE))
1865     {
1866                 tmpReg |= BIT_7;
1867     }
1868
1869     if (0 != (msg&SIG_BUF_RD_RDY))
1870     {
1871                 tmpReg |= BIT_5;
1872     }
1873
1874     if (0 != (msg&SIG_BUF_WD_RDY))
1875     {
1876                 tmpReg |= BIT_4;
1877     }
1878
1879     if (0 != (msg&SIG_DMA_INT))
1880     {
1881                 tmpReg |= BIT_3;
1882     }
1883
1884     if (0 != (msg&SIG_BLK_CAP))
1885     {
1886                 tmpReg |= BIT_2;
1887     }
1888
1889     if (0 != (msg&SIG_TRANS_CMP))
1890     {
1891                 tmpReg |= BIT_1;
1892     }
1893
1894     if (0 != (msg&SIG_CMD_CMP))
1895     {
1896                 tmpReg |= BIT_0;
1897     }
1898     sdhost_handler->host_cfg->INT_STA_EN |= tmpReg;
1899     sdhost_handler->IntEnabled = sdhost_handler->host_cfg->INT_STA_EN;
1900
1901 }
1902
1903 /*****************************************************************************/
1904 //  Description: Disable Normal int Signal register
1905 //  Author: Jason.wu
1906 //  Param
1907 //      sdhost_handler: the handle of host driver
1908 //      err_msg:        that int you want to Disable
1909 //  Return:
1910 //      NONE
1911 //  Note:
1912 /*****************************************************************************/
1913 PUBLIC void SDHOST_NML_IntStatus_Dis (SDHOST_HANDLE sdhost_handler,uint32 msg)
1914 {
1915     volatile uint32 tmpReg = 0;
1916     uint32 reg_value = sdhost_handler->IntEnabled;
1917     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1918
1919     if (0 != (msg&SIG_ERR))
1920     {
1921         //_ERR_IntStatus_Dis (sdhost_handler,ERR_ALL);
1922         tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
1923                    BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
1924
1925     }
1926
1927     if (0 != (msg&SIG_CARD_IN))
1928     {
1929                 tmpReg |= BIT_8;
1930     }
1931
1932     if (0 != (msg&SIG_CARD_INSERT))
1933     {
1934                 tmpReg |= BIT_6;
1935     }
1936
1937     if (0 != (msg&SIG_CARD_REMOVE))
1938     {
1939                 tmpReg |= BIT_7;
1940     }
1941
1942     if (0 != (msg&SIG_BUF_RD_RDY))
1943     {
1944                 tmpReg |= BIT_5;
1945     }
1946
1947     if (0 != (msg&SIG_BUF_WD_RDY))
1948     {
1949                 tmpReg |= BIT_4;
1950     }
1951
1952     if (0 != (msg&SIG_DMA_INT))
1953     {
1954                 tmpReg |= BIT_3;
1955     }
1956
1957     if (0 != (msg&SIG_BLK_CAP))
1958     {
1959                 tmpReg |= BIT_2;
1960     }
1961
1962     if (0 != (msg&SIG_TRANS_CMP))
1963     {
1964                 tmpReg |= BIT_1;
1965     }
1966
1967     if (0 != (msg&SIG_CMD_CMP))
1968     {
1969                 tmpReg |= BIT_0;
1970     }
1971     reg_value &= ~tmpReg;
1972     sdhost_handler->host_cfg->INT_STA_EN = reg_value;
1973     sdhost_handler->IntEnabled = reg_value;
1974
1975 }
1976
1977 /*****************************************************************************/
1978 //  Description: Enable Normal int Signal register ,if normal event  is happed ,host will send interrupt to Arm
1979 //  Author: Jason.wu
1980 //  Param
1981 //      sdhost_handler: the handle of host driver
1982 //      err_msg:        that int you want to Enable
1983 //  Return:
1984 //      NONE
1985 //  Note:
1986 /*****************************************************************************/
1987 PUBLIC void SDHOST_NML_IntSig_En (SDHOST_HANDLE sdhost_handler,uint32 msg)
1988 {
1989     volatile uint32 tmpReg = 0;
1990     uint32 err_msg;
1991     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1992
1993     if (0 != (msg&SIG_ERR))
1994     {
1995         //_ERR_IntSig_En (sdhost_handler,sdhost_handler->err_filter);
1996         err_msg = sdhost_handler->err_filter;
1997         if (0 != (err_msg&ERR_RSP))
1998         {
1999                 tmpReg |= BIT_28;
2000         }
2001
2002         if (0 != (err_msg&ERR_CMD12))
2003         {
2004                 tmpReg |= BIT_24;
2005         }
2006
2007         if (0 != (err_msg&ERR_CUR_LIMIT))
2008         {
2009                 tmpReg |= BIT_23;
2010         }
2011
2012         if (0 != (err_msg&ERR_DATA_END))
2013         {
2014                 tmpReg |= BIT_22;
2015         }
2016
2017         if (0 != (err_msg&ERR_DATA_CRC))
2018         {
2019                 tmpReg |= BIT_21;
2020         }
2021
2022         if (0 != (err_msg&ERR_DATA_TIMEOUT))
2023         {
2024                 tmpReg |= BIT_20;
2025         }
2026
2027         if (0 != (err_msg&ERR_CMD_INDEX))
2028         {
2029                 tmpReg |= BIT_19;
2030         }
2031
2032         if (0 != (err_msg&ERR_CMD_END))
2033         {
2034                 tmpReg |= BIT_18;
2035         }
2036
2037         if (0 != (err_msg&ERR_CMD_CRC))
2038         {
2039                 tmpReg |= BIT_17;
2040         }
2041
2042         if (0 != (err_msg&ERR_CMD_TIMEOUT))
2043         {
2044                 tmpReg |= BIT_16;
2045         }
2046
2047     }
2048
2049     if (0 != (msg&SIG_CARD_IN))
2050     {
2051                 tmpReg |= BIT_8;
2052     }
2053
2054     if (0 != (msg&SIG_CARD_INSERT))
2055     {
2056                 tmpReg |= BIT_6;
2057     }
2058
2059     if (0 != (msg&SIG_CARD_REMOVE))
2060     {
2061                 tmpReg |= BIT_7;
2062     }
2063
2064     if (0 != (msg&SIG_BUF_RD_RDY))
2065     {
2066                 tmpReg |= BIT_5;
2067     }
2068
2069     if (0 != (msg&SIG_BUF_WD_RDY))
2070     {
2071                 tmpReg |= BIT_4;
2072     }
2073
2074     if (0 != (msg&SIG_DMA_INT))
2075     {
2076                 tmpReg |= BIT_3;
2077     }
2078
2079     if (0 != (msg&SIG_BLK_CAP))
2080     {
2081                 tmpReg |= BIT_2;
2082     }
2083
2084     if (0 != (msg&SIG_TRANS_CMP))
2085     {
2086                 tmpReg |= BIT_1;
2087     }
2088
2089     if (0 != (msg&SIG_CMD_CMP))
2090     {
2091                 tmpReg |= BIT_0;
2092     }
2093         sdhost_handler->host_cfg->INT_SIG_EN |= tmpReg;
2094
2095 }
2096
2097 /*****************************************************************************/
2098 //  Description: Disable Normal int Signal register ,if normal event  is happed ,host will not send interrupt to Arm
2099 //  Author: Jason.wu
2100 //  Param
2101 //      sdhost_handler: the handle of host driver
2102 //      err_msg:        that int you want to Disable
2103 //  Return:
2104 //      NONE
2105 //  Note:
2106 /*****************************************************************************/
2107 PUBLIC void SDHOST_NML_IntSig_Dis (SDHOST_HANDLE sdhost_handler,uint32 msg)
2108 {
2109     volatile uint32 tmpReg = 0;
2110     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2111
2112     if (0 != (msg&SIG_ERR))
2113     {
2114         //_ERR_IntSig_Dis (sdhost_handler,ERR_ALL);
2115         tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
2116                    BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
2117
2118     }
2119
2120     if (0 != (msg&SIG_CARD_IN))
2121     {
2122                 tmpReg |= BIT_8;
2123     }
2124
2125     if (0 != (msg&SIG_CARD_INSERT))
2126     {
2127                 tmpReg |= BIT_6;
2128     }
2129
2130     if (0 != (msg&SIG_CARD_REMOVE))
2131     {
2132                 tmpReg |= BIT_7;
2133     }
2134
2135     if (0 != (msg&SIG_BUF_RD_RDY))
2136     {
2137                 tmpReg |= BIT_5;
2138     }
2139
2140     if (0 != (msg&SIG_BUF_WD_RDY))
2141     {
2142                 tmpReg |= BIT_4;
2143     }
2144
2145     if (0 != (msg&SIG_DMA_INT))
2146     {
2147                 tmpReg |= BIT_3;
2148     }
2149
2150     if (0 != (msg&SIG_BLK_CAP))
2151     {
2152                 tmpReg |= BIT_2;
2153     }
2154
2155     if (0 != (msg&SIG_TRANS_CMP))
2156     {
2157                 tmpReg |= BIT_1;
2158     }
2159
2160     if (0 != (msg&SIG_CMD_CMP))
2161     {
2162                 tmpReg |= BIT_0;
2163     }
2164         sdhost_handler->host_cfg->INT_SIG_EN &= ~tmpReg;
2165
2166 }
2167
2168 /*****************************************************************************/
2169 //  Description: Get normal int status register ,to confirm which normal event has happened
2170 //  Author: Jason.wu
2171 //  Param
2172 //      sdhost_handler: the handle of host driver
2173 //  Return:
2174 //      uint32 value: indicate which event happened
2175 //  Note:
2176 /*****************************************************************************/
2177 PUBLIC uint32 SDHOST_GetNMLIntStatus (SDHOST_HANDLE sdhost_handler)
2178 {
2179     volatile uint32 tmpReg;
2180     uint32 msg;
2181
2182     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2183
2184     tmpReg = sdhost_handler->host_cfg->INT_STA;
2185     msg = 0;
2186
2187     if (0 != (tmpReg & BIT_15))
2188     {
2189         msg |= SIG_ERR;
2190     }
2191
2192     if (0 != (tmpReg & BIT_8))
2193     {
2194         msg |= SIG_CARD_IN;
2195     }
2196
2197     if (0 != (tmpReg & BIT_6))
2198     {
2199         msg |= SIG_CARD_INSERT;
2200     }
2201
2202     if (0 != (tmpReg & BIT_7))
2203     {
2204         msg |= SIG_CARD_REMOVE;
2205     }
2206
2207     if (0 != (tmpReg & BIT_5))
2208     {
2209         msg |= SIG_BUF_RD_RDY;
2210     }
2211
2212     if (0 != (tmpReg & BIT_4))
2213     {
2214         msg |= SIG_BUF_WD_RDY;
2215     }
2216
2217     if (0 != (tmpReg & BIT_3))
2218     {
2219         msg |= SIG_DMA_INT;
2220     }
2221
2222     if (0 != (tmpReg & BIT_2))
2223     {
2224         msg |= SIG_BLK_CAP;
2225     }
2226
2227     if (0 != (tmpReg & BIT_1))
2228     {
2229         msg |= SIG_TRANS_CMP;
2230     }
2231
2232     if (0 != (tmpReg & BIT_0))
2233     {
2234         msg |= SIG_CMD_CMP;
2235     }
2236
2237     return msg;
2238 }
2239
2240
2241 /*****************************************************************************/
2242 //  Description: if error interrupt happened ,this function is used to confirm which error event happened
2243 //  Author: Jason.wu
2244 //  Param
2245 //      sdhost_handler: the handle of host driver
2246 //  Return:
2247 //      uint32 value: indicate which error event happened
2248 //  Note:
2249 /*****************************************************************************/
2250 PUBLIC uint32 SDHOST_GetErrCode (SDHOST_HANDLE sdhost_handler)
2251 {
2252     volatile uint32 tmpReg;
2253     uint32 err_msg;
2254
2255     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2256
2257     tmpReg = sdhost_handler->host_cfg->INT_STA;
2258     err_msg = 0;
2259
2260     if (0 != (tmpReg & BIT_28))
2261     {
2262         err_msg |= ERR_RSP;
2263     }
2264
2265     if (0 != (tmpReg & BIT_24))
2266     {
2267         err_msg |= ERR_CMD12;
2268     }
2269
2270     if (0 != (tmpReg & BIT_23))
2271     {
2272         err_msg |= ERR_CUR_LIMIT;
2273     }
2274
2275     if (0 != (tmpReg & BIT_22))
2276     {
2277         err_msg |= ERR_DATA_END;
2278     }
2279
2280     if (0 != (tmpReg & BIT_21))
2281     {
2282         err_msg |= ERR_DATA_CRC;
2283     }
2284
2285     if (0 != (tmpReg & BIT_20))
2286     {
2287         err_msg |= ERR_DATA_TIMEOUT;
2288     }
2289
2290     if (0 != (tmpReg & BIT_19))
2291     {
2292         err_msg |= ERR_CMD_INDEX;
2293     }
2294
2295     if (0 != (tmpReg & BIT_18))
2296     {
2297         err_msg |= ERR_CMD_END;
2298     }
2299
2300     if (0 != (tmpReg & BIT_17))
2301     {
2302         err_msg |= ERR_CMD_CRC;
2303     }
2304
2305     if (0 != (tmpReg & BIT_16))
2306     {
2307         err_msg |= ERR_CMD_TIMEOUT;
2308     }
2309
2310     return err_msg;
2311 }
2312
2313 /*****************************************************************************/
2314 //  Description: this function is used to set which error event you want to watched ,other error event will be ignored if happened
2315 //  Author: Jason.wu
2316 //  Param
2317 //      sdhost_handler: the handle of host driver
2318 //      err_msg:        the event you want to watched
2319 //  Return:
2320 //      NONE
2321 //  Note:
2322 /*****************************************************************************/
2323 PUBLIC void SDHOST_SetErrCodeFilter (SDHOST_HANDLE sdhost_handler,uint32 err_msg)
2324 {
2325     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2326
2327     sdhost_handler->err_filter = err_msg;
2328 }
2329
2330 /*****************************************************************************/
2331 //  Description: To indicate event that happened from which slot
2332 //  Author: Jason.wu
2333 //  Param
2334 //      sdhost_handler: the handle of host driver
2335 //  Return:
2336 //      uint32 value: indicate which slot event happened
2337 //  Note:
2338 /*****************************************************************************/
2339 LOCAL SDHOST_SLOT_NO _GetIntSDHOSTSlotNum (uint32 port)
2340 {
2341     uint32 tmpReg;
2342     SDHOST_SLOT_NO ret;
2343 #if defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2344     ret = SDHOST_SLOT_7;
2345 #else
2346 #if defined(CONFIG_TIGER)|| defined (CONFIG_SC7710G2)
2347     if(SDHOST_SLOT_6 == port){
2348         tmpReg = REG32 (SDIO2_NML_INT_SIG_EN);
2349         if(tmpReg == 0)
2350                 REG32 (SDIO2_NML_INT_SIG_EN) = BIT_1;
2351         tmpReg = REG32 (SDIO2_SLOT_INT_STS);
2352         tmpReg &= 0x01;
2353     }
2354     else
2355         tmpReg = REG32 (EMMC_SLOT_INT_STS);
2356 #else
2357     if(port == 0){
2358         tmpReg = REG32 (SDIO0_SLOT_INT_STS);
2359     }
2360     else
2361     {
2362         tmpReg = REG32 (SDIO1_SLOT_INT_STS);
2363     }
2364 #endif
2365
2366     if ( (tmpReg& (0x01<<0)))
2367     {
2368 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
2369         if(SDHOST_SLOT_6 == port)
2370                 ret = SDHOST_SLOT_6;
2371         else
2372                 ret = SDHOST_SLOT_7;
2373 #else
2374                 if(port == 0){
2375                         ret = SDHOST_SLOT_0;
2376                 }else{
2377                 ret = SDHOST_SLOT_1;
2378                 }
2379 #endif
2380     }
2381     else if ( (tmpReg& (0x01<<1)))
2382     {
2383         ret = SDHOST_SLOT_1;
2384     }
2385     else if ( (tmpReg& (0x01<<2)))
2386     {
2387         ret = SDHOST_SLOT_2;
2388     }
2389     else if ( (tmpReg& (0x01<<3)))
2390     {
2391         ret = SDHOST_SLOT_3;
2392     }
2393     else if ( (tmpReg& (0x01<<4)))
2394     {
2395         ret = SDHOST_SLOT_4;
2396     }
2397     else if ( (tmpReg& (0x01<<5)))
2398     {
2399         ret = SDHOST_SLOT_5;
2400     }
2401     else if ( (tmpReg& (0x01<<6)))
2402     {
2403         ret = SDHOST_SLOT_6;
2404     }
2405     else if ( (tmpReg& (0x01<<7)))
2406     {
2407         ret = SDHOST_SLOT_7;
2408     }
2409     else
2410     {
2411         ret = SDHOST_SLOT_MAX_NUM;
2412         SCI_ASSERT (0);/*assert to do*/
2413     }
2414 #endif
2415     return ret;
2416 }
2417
2418 /*****************************************************************************/
2419 //  Description: This function is called by interrupt service .is event happened ,this funtion will
2420 //  clear the event and call the callback of application
2421 //  Author: Jason.wu
2422 //  Param
2423 //      isrnum: the number of arm interrupt
2424 //  Return:
2425 //      NONE
2426 //  Note:
2427 /*****************************************************************************/
2428 PUBLIC ISR_EXE_T _SDHOST_IrqHandle (uint32 isrnum)
2429 {
2430     ISR_Buffer_T buffer;
2431     SDHOST_HANDLE sdhost_handler;
2432
2433     buffer.slotNum = isrnum;
2434     if(buffer.slotNum == SDHOST_SLOT_MAX_NUM){
2435         return ISR_DONE;
2436     }
2437     sdhost_handler = &sdio_port_ctl[buffer.slotNum];
2438     buffer.pSdhost_handler = &sdio_port_ctl[buffer.slotNum];
2439
2440     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2441
2442     if (FALSE == sdhost_handler->open_flag)
2443     {
2444         SDHOST_NML_IntSig_Dis (sdhost_handler, SIG_ALL);
2445         SDHOST_NML_IntStatus_Dis (sdhost_handler, SIG_ALL);
2446         SDHOST_NML_IntStatus_Clr (sdhost_handler, SIG_ALL);
2447         return ISR_DONE;
2448     }
2449
2450     if (NULL == sdhost_handler->sigCallBack)
2451     {
2452         SDHOST_NML_IntSig_Dis (sdhost_handler, SIG_ALL);
2453         SDHOST_NML_IntStatus_Dis (sdhost_handler, SIG_ALL);
2454         SDHOST_NML_IntStatus_Clr (sdhost_handler, SIG_ALL);
2455         return ISR_DONE;
2456     }
2457
2458     buffer.msg = SDHOST_GetNMLIntStatus (sdhost_handler);
2459     buffer.errCode = SDHOST_GetErrCode (sdhost_handler);
2460
2461     SDHOST_NML_IntSig_Dis (sdhost_handler, buffer.msg);
2462     SDHOST_NML_IntStatus_Dis (sdhost_handler, buffer.msg);
2463     SDHOST_NML_IntStatus_Clr (sdhost_handler, buffer.msg);
2464 #ifndef OS_NONE
2465     IsrWriteBuffer (buffer);
2466 #else
2467         sdhost_handler->sigCallBack (buffer.msg, buffer.errCode, buffer.slotNum);
2468 #endif
2469
2470     return CALL_HISR;
2471 }
2472
2473 /*****************************************************************************/
2474 //  Description:    This function is SDIO 's HISR.
2475 //                  1. THE priority is higher than normal task.
2476 //                  2. Is not real ISR.
2477 //  Author:         steve.zhan
2478 //  Note:
2479 /*****************************************************************************/
2480 LOCAL void  SdhostHisrFunc (uint32 cnt, void *pData)
2481 {
2482     ISR_Buffer_T buffer;
2483
2484     while (!threadReadBuffer (&buffer))
2485     {
2486         buffer.pSdhost_handler->sigCallBack (buffer.msg, buffer.errCode, buffer.slotNum);
2487     }
2488 }
2489
2490 LOCAL void _SDHOST_Pin_select(SDHOST_SLOT_NO slot_NO)
2491 {
2492     if(slot_NO == SDHOST_SLOT_1){
2493         *(volatile uint32*)(0x8c0003e8) = 0x280;    //SD1 CMD pullup drv3, strongest strength
2494         *(volatile uint32*)(0x8c0003ec) = 0x280;    //SD1 D0 pullup drv3, strongest strength
2495         *(volatile uint32*)(0x8c0003f0) = 0x280;    //SD1 D1 pullup drv3, strongest strength
2496         *(volatile uint32*)(0x8c0003f4) = 0x280;    //SD1 D2 pullup drv3, strongest strength
2497         *(volatile uint32*)(0x8c0003f8) = 0x280;    //SD1 D3 pullup drv3, strongest strength
2498         *(volatile uint32*)(0x8c0003fc) = 0x280;    //SD1 D3 pullup drv3, strongest strength
2499     }
2500 }
2501
2502 /*****************************************************************************/
2503 //  Description: Regist host slot
2504 //  Author: Jason.wu
2505 //  Param
2506 //      slot_NO:    which slot you want to used
2507 //      fun:        this function will be called when event happened
2508 //  Return:
2509 //      Not zero: succes
2510 //      zeror: fail
2511 //  Note:
2512 /*****************************************************************************/
2513 PUBLIC SDHOST_HANDLE SDHOST_Register (SDHOST_SLOT_NO slot_NO,SDIO_CALLBACK fun)
2514 {
2515     uint32 status = 0, i = 0;
2516
2517     SCI_ASSERT (slot_NO < SDHOST_SLOT_MAX_NUM);/*assert verified*/
2518
2519     if (TRUE == sdio_port_ctl[slot_NO].open_flag)
2520     {
2521         return NULL;
2522     }
2523         if (slot_NO == SDHOST_SLOT_7)
2524         {
2525                 sdio_port_ctl[slot_NO].host_cfg =
2526                                                         (SDIO_REG_CFG *) ( (volatile uint32 *) EMMC_BASE_ADDR);
2527                 SDHOST_SD_clk_OnOff(&sdio_port_ctl[slot_NO], CLK_OFF);
2528         }
2529         SDHOST_Reset_Controller(slot_NO);
2530         sdio_port_ctl[slot_NO].slotNo = slot_NO;
2531     // select slot 0
2532 #if defined (CONFIG_SC8825) || defined(CONFIG_SPX15)||defined(CONFIG_SPX30G) || (defined CONFIG_SC9630)/*CONFIG_SPX15 must be before CONFIG_SC8830*/
2533         sdio_port_ctl[slot_NO].open_flag = TRUE;
2534         #if defined(CONFIG_ARCH_SCX20L) || defined(CONFIG_SPX20)
2535         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_192M);
2536         #else
2537         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_384M);
2538         #endif
2539 #elif defined (CONFIG_SC8830)
2540         sdio_port_ctl[slot_NO].open_flag = TRUE;
2541         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_192M);
2542 #elif defined(CONFIG_SC7710G2)
2543 //    SDHOST_Slot_select(slot_NO); if necessary
2544         sdio_port_ctl[slot_NO].open_flag = TRUE;
2545         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_96M);
2546 #else
2547         _SDHOST_Pin_select(slot_NO);
2548         sdio_port_ctl[slot_NO].open_flag = TRUE;
2549         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_48M);
2550 #endif
2551
2552 #if defined(CONFIG_FPGA)
2553         sdio_port_ctl[slot_NO].baseClock = 36000000;
2554 #endif
2555
2556     switch (slot_NO)
2557     {
2558         case SDHOST_SLOT_0:
2559             {
2560                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR);
2561             }
2562             break;
2563
2564         case SDHOST_SLOT_1:
2565             {
2566 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
2567                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO0_BASE_ADDR+0x100) );
2568 #else
2569                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO1_BASE_ADDR);
2570 #endif
2571             }
2572             break;
2573
2574         case SDHOST_SLOT_2:
2575 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2576             {
2577                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO2_BASE_ADDR) );
2578             }
2579             break;
2580 #endif
2581         case SDHOST_SLOT_3:
2582 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2583             {
2584                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO1_BASE_ADDR );
2585             }
2586             break;
2587 #endif
2588         case SDHOST_SLOT_4:
2589 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2590             {
2591                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO1_BASE_ADDR+0x100) );
2592             }
2593             break;
2594 #endif
2595         case SDHOST_SLOT_5:
2596 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2597             {
2598                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO1_BASE_ADDR+0x200) );
2599             }
2600             break;
2601 #endif
2602         case SDHOST_SLOT_6:
2603                         REG32(REG_PIN_SD0_CLK0)= 0x300;
2604                         REG32(REG_PIN_SD0_CLK1)= 0x300;
2605                         REG32(REG_PIN_SD0_CMD) = 0x280;
2606                         REG32(REG_PIN_SD0_D0)  = 0x280;
2607                         REG32(REG_PIN_SD0_D0)  = 0x280;
2608                         REG32(REG_PIN_SD0_D1)  = 0x280;
2609                         REG32(REG_PIN_SD0_D2)  = 0x280;
2610                         sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR );
2611             break;
2612         case SDHOST_SLOT_7:
2613 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
2614 #ifdef CONFIG_SC8825
2615                         REG32(PIN_CTL3_REG)  |= (0x1ff<<8);//  set emmc data line, cmd line pull up resistor 4.7k
2616                         REG32(PIN_SD3CLK_REG) = 0x200;
2617                         REG32(PIN_SD3CMD_REG)= 0x280;
2618                         REG32(PIN_SD3D0_REG) = 0x280;
2619                         REG32(PIN_SD3D1_REG) = 0x280;
2620                         REG32(PIN_SD3D2_REG) = 0x280;
2621                         REG32(PIN_SD3D3_REG) = 0x280;
2622                         REG32(PIN_SD3D4_REG) = 0x280;
2623                         REG32(PIN_SD3D5_REG) = 0x280;
2624                         REG32(PIN_SD3D6_REG) = 0x280;
2625                         REG32(PIN_SD3D7_REG) = 0x280;
2626 #elif defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2627 #ifndef CONFIG_FPGA
2628 #ifdef CONFIG_SPX15
2629 #define REG_PIN_EMMC_CLK     REG_PIN_NFREN
2630 #define REG_PIN_EMMC_CMD     REG_PIN_NFRB
2631 #define REG_PIN_EMMC_D0      REG_PIN_NFWPN
2632 #define REG_PIN_EMMC_D1      REG_PIN_NFD11
2633 #define REG_PIN_EMMC_D2      REG_PIN_NFD14
2634 #define REG_PIN_EMMC_D3      REG_PIN_NFD7
2635 #define REG_PIN_EMMC_D4      REG_PIN_NFD5
2636 #define REG_PIN_EMMC_D5      REG_PIN_NFD4
2637 #define REG_PIN_EMMC_D6      REG_PIN_NFCLE
2638 #define REG_PIN_EMMC_D7      REG_PIN_NFALE
2639                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x210;
2640                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x1198;
2641                         REG32(CTL_PIN_BASE+REG_PIN_NFD10)   = 0x198;
2642                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x198;
2643                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x198;
2644                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x198;
2645                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x198;
2646                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x198;
2647                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x198;
2648                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x198;
2649                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x198;
2650 #elif defined(CONFIG_SPX30G)
2651 #if defined(CONFIG_SPX20)
2652 #define REG_PIN_EMMC_CLK     REG_PIN_NFREN
2653 #define REG_PIN_EMMC_CMD     REG_PIN_NFRBN
2654 #define REG_PIN_EMMC_D0      REG_PIN_NFWPN
2655 #define REG_PIN_EMMC_D1      REG_PIN_NFD11
2656 #define REG_PIN_EMMC_D2      REG_PIN_NFD14
2657 #define REG_PIN_EMMC_D3      REG_PIN_NFD7
2658 #define REG_PIN_EMMC_D4      REG_PIN_NFD5
2659 #define REG_PIN_EMMC_D5      REG_PIN_NFD4
2660 #define REG_PIN_EMMC_D6      REG_PIN_NFCLE
2661 #define REG_PIN_EMMC_D7      REG_PIN_NFALE
2662                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x80010;
2663                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80090;
2664                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80090;
2665                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80090;
2666                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80090;
2667                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80090;
2668                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80090;
2669                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80090;
2670                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80090;
2671                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80090;
2672 #else   /* TIZEN */
2673                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x00;
2674                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80;
2675                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80;
2676                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80;
2677                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80;
2678                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80;
2679                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80;
2680                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80;
2681                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80;
2682                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80;
2683 #if 0
2684                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x80000;
2685                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80080;
2686                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80080;
2687                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80080;
2688                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80080;
2689                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80080;
2690                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80080;
2691                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80080;
2692                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80080;
2693                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80080;
2694 #endif
2695 #endif
2696 #elif defined(CONFIG_SC9630)
2697 #define REG_PIN_EMMC_CLK   REG_PIN_NFREN
2698 #define REG_PIN_EMMC_CMD  REG_PIN_NFRB
2699 #define REG_PIN_EMMC_D0      REG_PIN_NFWPN
2700 #define REG_PIN_EMMC_D1      REG_PIN_NFD11
2701 #define REG_PIN_EMMC_D2      REG_PIN_NFD14
2702 #define REG_PIN_EMMC_D3      REG_PIN_NFD7
2703 #define REG_PIN_EMMC_D4      REG_PIN_NFD5
2704 #define REG_PIN_EMMC_D5      REG_PIN_NFD4
2705 #define REG_PIN_EMMC_D6      REG_PIN_NFCLE
2706 #define REG_PIN_EMMC_D7      REG_PIN_NFALE
2707                         sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR );
2708
2709                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x82011;
2710                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x83094;
2711                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x3094;
2712                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x3094;
2713                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x3094;
2714                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x3094;
2715                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x3094;
2716                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x3094;
2717                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x3094;
2718                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x3094;
2719 #else
2720         /* Other chip,do nothing*/
2721 #endif
2722 #endif /* CONFIG_FPGA */
2723 #endif
2724             {
2725                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) EMMC_BASE_ADDR);
2726             }
2727             break;
2728 #endif
2729         default:
2730             {
2731                 SCI_ASSERT (0);/*assert to do*/
2732             }
2733             break;
2734     }
2735     sdio_port_ctl[slot_NO].sigCallBack = fun;
2736     sdio_port_ctl[slot_NO].err_filter = 0;
2737
2738 #ifndef OS_NONE
2739     status = ISR_RegHandler_Ex (TB_SDIO_INT, (TB_ISR) _SDHOST_IrqHandle, SdhostHisrFunc, CHIPDRV_HISR_PRIO_1, NULL);
2740     if (TB_SUCCESS == status)
2741     {
2742         CHIPDRV_EnableIRQINT (TB_SDIO_INT);
2743     }
2744 #endif
2745     return &sdio_port_ctl[slot_NO];
2746 }
2747
2748 /*****************************************************************************/
2749 //  Description: Free the slot resource
2750 //  Author: Jason.wu
2751 //  Param
2752 //      sdhost_handler: the handler of host driver ,this is returned by SDHOST_Register
2753 //  Return:
2754 //      Not zero: succes
2755 //      zeror: fail
2756 //  Note:
2757 /*****************************************************************************/
2758 PUBLIC BOOLEAN SDHOST_UnRegister (SDHOST_HANDLE sdhost_handler)
2759 {
2760     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2761
2762     SDHOST_SD_POWER (sdhost_handler,POWR_OFF);
2763     SDHOST_RST (sdhost_handler,RST_ALL);
2764     SDHOST_SD_clk_OnOff (sdhost_handler,CLK_OFF);
2765     SDHOST_internalClk_OnOff (sdhost_handler,CLK_OFF);
2766     sdhost_handler->sigCallBack = NULL;
2767     sdhost_handler->open_flag = FALSE;
2768     return TRUE;
2769 }
2770
2771 //====================
2772 //---External function---
2773 //====================
2774 /*****************************************************************************/
2775 //  Description: Set basic clk of host,card clk will divided from this clk
2776 //  Author: Jason.wu
2777 //  Param
2778 //      sdhost_handler: the handler of host driver ,this is returned by SDHOST_Register
2779 //      sdio_base_clk: the frequecy that you want to set
2780 //  Return:
2781 //      uint32 value :the frequency that be used acctually
2782 //  Note: This function must be applied according different platform
2783 /*****************************************************************************/
2784 #ifndef OS_NONE
2785 #if 0
2786 PUBLIC uint32 SDHOST_BaseClk_Set (uint32 sdio_base_clk)
2787 {
2788 #ifdef  PLATFORM_SC8800G
2789     uint32 clk = 0;
2790
2791     //Select the clk source of SDIO
2792     if (sdio_base_clk >= SDIO_BASE_CLK_96M)
2793     {
2794         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_96M);
2795         clk = SDIO_BASE_CLK_96M;
2796     }
2797     else if (sdio_base_clk >= SDIO_BASE_CLK_64M)
2798     {
2799         clk = SDIO_BASE_CLK_64M;
2800         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_64M);
2801
2802     }
2803     else if (sdio_base_clk >= SDIO_BASE_CLK_48M)
2804     {
2805         clk = SDIO_BASE_CLK_48M;
2806         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_48M);
2807     }
2808     else
2809     {
2810         clk = SDIO_BASE_CLK_26M;
2811         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_26M);
2812     }
2813
2814     return clk;
2815 #endif
2816 }
2817 #endif
2818 #else
2819 PUBLIC uint32 SDHOST_BaseClk_Set(SDHOST_SLOT_NO slot_NO,uint32 sdio_base_clk)
2820 {
2821     uint32 clk = 0;
2822
2823 #if defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2824
2825
2826 #if defined(CONFIG_SPX15)|| (defined CONFIG_SC9630)
2827         #if defined (CONFIG_ARCH_SCX20L)
2828                         if (slot_NO == SDHOST_SLOT_6)
2829                         {
2830                                 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2831
2832                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2833                                 {
2834                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2835                                         clk = SDIO_BASE_CLK_384M;
2836                                 }
2837                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2838                                 {
2839                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2840                                         clk = SDIO_BASE_CLK_312M;
2841                                 }
2842                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2843                                 {
2844                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2845                                         clk = SDIO_BASE_CLK_256M;
2846                                 }
2847                                 else
2848                                 {
2849                                         clk = SDIO_BASE_CLK_26M;
2850                                 }
2851 #if 0
2852                                 if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2853                                 {
2854                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2855                                         clk = SDIO_BASE_CLK_256M;
2856                                 }
2857                                 else if (sdio_base_clk >= SDIO_BASE_CLK_192M)
2858                                 {
2859                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2860                                         clk = SDIO_BASE_CLK_192M;
2861                                 }
2862                                 else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
2863                                 {
2864                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2865                                         clk = SDIO_BASE_CLK_256M;
2866                                 }
2867                                 else
2868                                 {
2869                                         clk = SDIO_BASE_CLK_26M;
2870                                 }
2871 #endif
2872                         }
2873                         else
2874                         {
2875                                 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2876
2877                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2878                                 {
2879                                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
2880                                         clk = SDIO_BASE_CLK_384M;
2881                                 }
2882                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2883                                 {
2884                                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
2885                                         clk = SDIO_BASE_CLK_312M;
2886                                 }
2887                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2888                                 {
2889                                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
2890                                         clk = SDIO_BASE_CLK_256M;
2891                                 }
2892                                 else
2893                                 {
2894                                         clk = SDIO_BASE_CLK_26M;
2895                                 }
2896 #if 0
2897                                 if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2898                                 {
2899                                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
2900                                         clk = SDIO_BASE_CLK_256M;
2901                                 }
2902                                 else if (sdio_base_clk >= SDIO_BASE_CLK_192M)
2903                                 {
2904                                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
2905                                         clk = SDIO_BASE_CLK_192M;
2906                                 }
2907                                 else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
2908                                 {
2909                                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
2910                                         clk = SDIO_BASE_CLK_153M;
2911                                 }
2912                                 else
2913                                 {
2914                                         clk = SDIO_BASE_CLK_26M;
2915                                 }
2916 #endif
2917                         }
2918         #elif defined(CONFIG_SPX20)
2919                 if (slot_NO == SDHOST_SLOT_6)
2920                 {
2921                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2922
2923                         if (sdio_base_clk == SDIO_BASE_CLK_192M)
2924                         {
2925                                 REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2926                                 clk = SDIO_BASE_CLK_192M;
2927                         }
2928                         else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2929                         {
2930                                 REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2931                                 clk = SDIO_BASE_CLK_312M;
2932                         }
2933                         else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2934                         {
2935                                 REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2936                                 clk = SDIO_BASE_CLK_256M;
2937                         }
2938                         else
2939                         {
2940                                 clk = SDIO_BASE_CLK_26M;
2941                         }
2942                 }
2943                 else
2944                 {
2945                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2946
2947                         if (sdio_base_clk == SDIO_BASE_CLK_192M)
2948                         {
2949                                 REG32(REG_AP_CLK_EMMC_CFG) |=  3;
2950                                 clk = SDIO_BASE_CLK_192M;
2951                         }
2952                         else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2953                         {
2954                                 REG32(REG_AP_CLK_EMMC_CFG) |=  2;
2955                                 clk = SDIO_BASE_CLK_312M;
2956                         }
2957                         else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2958                         {
2959                                 REG32(REG_AP_CLK_EMMC_CFG) |=  1;
2960                                 clk = SDIO_BASE_CLK_256M;
2961                         }
2962                         else
2963                         {
2964                                 clk = SDIO_BASE_CLK_26M;
2965                         }
2966                 }
2967         #else
2968                 if (slot_NO == SDHOST_SLOT_6)
2969                         {
2970                                 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2971
2972                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2973                                 {
2974                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2975                                         clk = SDIO_BASE_CLK_384M;
2976                                 }
2977                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2978                                 {
2979                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2980                                         clk = SDIO_BASE_CLK_312M;
2981                                 }
2982                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2983                                 {
2984                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2985                                         clk = SDIO_BASE_CLK_256M;
2986                                 }
2987                                 else
2988                                 {
2989                                         clk = SDIO_BASE_CLK_26M;
2990                                 }
2991                         }
2992                         else
2993                         {
2994                                 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2995
2996                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2997                                 {
2998                                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
2999                                         clk = SDIO_BASE_CLK_384M;
3000                                 }
3001                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3002                                 {
3003                                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
3004                                         clk = SDIO_BASE_CLK_312M;
3005                                 }
3006                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3007                                 {
3008                                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
3009                                         clk = SDIO_BASE_CLK_256M;
3010                                 }
3011                                 else
3012                                 {
3013                                         clk = SDIO_BASE_CLK_26M;
3014                                 }
3015                         }
3016         #endif
3017 #else   /* TIZEN */
3018         if (slot_NO == SDHOST_SLOT_6)
3019         {
3020                 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3021
3022                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3023                 {
3024                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
3025                         clk = SDIO_BASE_CLK_384M;
3026                 }
3027                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3028                 {
3029                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
3030                         clk = SDIO_BASE_CLK_312M;
3031                 }
3032                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3033                 {
3034                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
3035                         clk = SDIO_BASE_CLK_256M;
3036                 }
3037                 else
3038                 {
3039                         clk = SDIO_BASE_CLK_26M;
3040                 }
3041         }
3042         else
3043         {
3044                 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3045
3046                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3047                 {
3048                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
3049                         clk = SDIO_BASE_CLK_384M;
3050                 }
3051                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3052                 {
3053                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
3054                         clk = SDIO_BASE_CLK_312M;
3055                 }
3056                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3057                 {
3058                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
3059                         clk = SDIO_BASE_CLK_256M;
3060                 }
3061                 else
3062                 {
3063                         clk = SDIO_BASE_CLK_26M;
3064                 }
3065         }
3066
3067 #if 0
3068         if (slot_NO == SDHOST_SLOT_6)
3069         {
3070                 if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3071                 {
3072                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
3073                         clk = SDIO_BASE_CLK_312M;
3074                 }
3075                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3076                 {
3077                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3078                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
3079                         clk = SDIO_BASE_CLK_256M;
3080                 }
3081                 if (sdio_base_clk >= SDIO_BASE_CLK_192M)
3082                 {
3083                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3084                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
3085                         clk = SDIO_BASE_CLK_192M;
3086                 }
3087                 else
3088                 {
3089                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3090                         clk = SDIO_BASE_CLK_26M;
3091                 }
3092         }
3093         else
3094         {
3095                 if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3096                 {
3097                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
3098                         clk = SDIO_BASE_CLK_312M;
3099                 }
3100                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3101                 {
3102                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3103                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
3104                         clk = SDIO_BASE_CLK_256M;
3105                 }
3106                 if (sdio_base_clk >= SDIO_BASE_CLK_192M)
3107                 {
3108                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3109                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
3110                         clk = SDIO_BASE_CLK_192M;
3111                 }
3112                 else
3113                 {
3114                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3115                         clk = SDIO_BASE_CLK_26M;
3116                 }
3117         }
3118 #endif
3119 #endif
3120 #elif defined(CONFIG_TIGER)
3121     REG32 (GR_CLK_GEN5) &= ~ (BIT_23|BIT_24);
3122     //Select the clk source of SDIO
3123     if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3124     {
3125         clk = SDIO_BASE_CLK_384M;
3126     }
3127     else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3128     {
3129         clk = SDIO_BASE_CLK_256M;
3130         REG32 (GR_CLK_GEN5) |= (1<<23);
3131     }
3132     else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
3133     {
3134         clk = SDIO_BASE_CLK_153M;
3135         REG32 (GR_CLK_GEN5) |= (2<<23);
3136     }
3137     else
3138     {
3139         clk = SDIO_BASE_CLK_26M;
3140         REG32 (GR_CLK_GEN5) |= (3<<23);
3141     }
3142 #elif defined(CONFIG_SC7710G2)
3143     if(SDHOST_SLOT_6 == slot_NO){
3144         REG32 (GR_CLK_GEN7) &= ~ (BIT_21|BIT_22);
3145         //Select the clk source of SDIO
3146         if (sdio_base_clk >= SDIO_BASE_CLK_96M) {
3147                 clk = SDIO_BASE_CLK_96M;
3148         } else if (sdio_base_clk >= SDIO_BASE_CLK_64M) {
3149                 clk = SDIO_BASE_CLK_64M;
3150                 REG32 (GR_CLK_GEN7) |= (1<<21);
3151         } else if (sdio_base_clk >= SDIO_BASE_CLK_48M) {
3152                 clk = SDIO_BASE_CLK_48M;
3153                 REG32 (GR_CLK_GEN7) |= (2<<21);
3154         } else {
3155                 clk = SDIO_BASE_CLK_26M;
3156                 REG32 (GR_CLK_GEN7) |= (3<<21);
3157         }
3158     } else {
3159         REG32 (GR_CLK_GEN7) &= ~ (BIT_23|BIT_24);
3160         //Select the clk source of SDIO
3161         if (sdio_base_clk >= SDIO_BASE_CLK_384M){
3162                 clk = SDIO_BASE_CLK_384M;
3163                 REG32 (GR_CLK_GEN7) |= (1<<23);
3164         } else if (sdio_base_clk >= SDIO_BASE_CLK_256M){
3165                 clk = SDIO_BASE_CLK_256M;
3166                 REG32 (GR_CLK_GEN7) |= (2<<23);
3167         } else if (sdio_base_clk >= SDIO_BASE_CLK_153M){
3168                 clk = SDIO_BASE_CLK_153M;
3169                 REG32 (GR_CLK_GEN7) |= (3<<23);
3170         }else
3171                 clk = SDIO_BASE_CLK_26M;
3172     }
3173 #elif defined(PLATFORM_SC8800G)
3174     //Select the clk source of SDIO1
3175     if(SDHOST_SLOT_1 == slot_NO){
3176         *(volatile uint32 *)GR_CLK_GEN5 &= ~(BIT_19|BIT_20);
3177         if(sdio_base_clk >= SDIO_BASE_CLK_96M)
3178                 clk = SDIO_BASE_CLK_96M;
3179         else if(sdio_base_clk >= SDIO_BASE_CLK_64M){
3180                 clk = SDIO_BASE_CLK_64M;
3181                 *(volatile uint32 *)GR_CLK_GEN5 |= (1<<19);
3182         } else if(sdio_base_clk >= SDIO_BASE_CLK_48M) {
3183                 clk = SDIO_BASE_CLK_48M;
3184                 *(volatile uint32 *)GR_CLK_GEN5 |= (2<<19);
3185         } else {
3186                 clk = SDIO_BASE_CLK_26M;
3187                 *(volatile uint32 *)GR_CLK_GEN5 |= (3<<19);
3188         }
3189     } else if(SDHOST_SLOT_0 == slot_NO){
3190         *(volatile uint32 *)GR_CLK_GEN5 &= ~(BIT_17|BIT_18);
3191         if(sdio_base_clk >= SDIO_BASE_CLK_96M)
3192                 clk = SDIO_BASE_CLK_96M;
3193         else if(sdio_base_clk >= SDIO_BASE_CLK_64M){
3194                 clk = SDIO_BASE_CLK_64M;
3195                 *(volatile uint32 *)GR_CLK_GEN5 |= (1<<17);
3196         } else if(sdio_base_clk >= SDIO_BASE_CLK_48M) {
3197                 clk = SDIO_BASE_CLK_48M;
3198                 *(volatile uint32 *)GR_CLK_GEN5 |= (2<<17);
3199         } else {
3200                 clk = SDIO_BASE_CLK_26M;
3201                 *(volatile uint32 *)GR_CLK_GEN5 |= (3<<17);
3202         }
3203     }
3204 #endif
3205     return clk;
3206 }
3207
3208 #endif
3209
3210 /*****************************************************************************/
3211 //  Description: select witch slot to work
3212 //  Author: Jason.wu
3213 //  Param
3214 //      slot_NO: slot number
3215 //  Return:
3216 //      NONE
3217 //  Note: This function must be applied according different platform
3218 /*****************************************************************************/
3219 PUBLIC void SDHOST_Slot_select (SDHOST_SLOT_NO slot_NO)
3220 {
3221         SCI_ASSERT (slot_NO < SDHOST_SLOT_MAX_NUM);/*assert verified*/
3222 #if !(defined(CONFIG_SC8830) || defined(CONFIG_SC9630) )
3223         * (volatile uint32 *) AHB_SDIO_CTL = (AHB_SDIO_CTRL_SLOT0); //select master0
3224 #endif
3225 }
3226
3227 //===end===
3228