2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Back ported to the 8xx platform (from the 8260 platform) by
24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
33 void sdhci_dumpregs(struct sdhci_host *host);
35 static void sdhci_reset(struct sdhci_host *host, u8 mask)
37 unsigned long timeout;
41 sdhci_writeb(host, mask|SDHCI_HW_RST, SDHCI_SOFTWARE_RESET);
42 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
44 printf("Reset 0x%x never completed.\n", (int)mask);
52 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
55 if (cmd->resp_type & MMC_RSP_136) {
56 /* CRC is stripped so we need to do some shifting. */
57 for (i = 0; i < 4; i++) {
58 cmd->response[i] = sdhci_readl(host,
59 SDHCI_RESPONSE + (3-i)*4) << 8;
61 cmd->response[i] |= sdhci_readb(host,
62 SDHCI_RESPONSE + (3-i)*4-1);
65 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
69 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
73 for (i = 0; i < data->blocksize; i += 4) {
74 offs = data->dest + i;
75 if (data->flags == MMC_DATA_READ) {
76 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
79 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
84 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
85 unsigned int start_addr)
87 unsigned int stat, rdy, mask, timeout, block = 0;
90 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
91 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
94 stat = sdhci_readl(host, SDHCI_INT_STATUS);
95 if (stat & SDHCI_INT_ERROR) {
96 printf("Error detected in status(0x%X)!\n", stat);
100 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
102 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
103 printf("%s start pio\n", __func__);
104 sdhci_transfer_pio(host, data);
105 data->dest += data->blocksize;
106 if (++block >= data->blocks)
109 #ifdef CONFIG_MMC_SDMA
110 if (stat & SDHCI_INT_DMA_END) {
111 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
112 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
113 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
114 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
120 printf("Transfer data timeout\n");
123 } while (!(stat & SDHCI_INT_DATA_END));
127 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
128 struct mmc_data *data)
130 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
131 unsigned int stat = 0;
133 int trans_bytes = 0, is_aligned = 1;
134 u32 mask, flags, mode;
135 unsigned int timeout, start_addr = 0;
140 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
141 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
143 /* We shouldn't wait for data inihibit for stop commands, even
144 though they might use busy signaling */
145 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
146 mask &= ~SDHCI_DATA_INHIBIT;
148 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
150 printf("Controller never released inhibit bit(s).\n");
157 mask = SDHCI_INT_RESPONSE;
158 if (!(cmd->resp_type & MMC_RSP_PRESENT))
159 flags = SDHCI_CMD_RESP_NONE;
160 else if (cmd->resp_type & MMC_RSP_136)
161 flags = SDHCI_CMD_RESP_LONG;
162 else if (cmd->resp_type & MMC_RSP_BUSY) {
163 flags = SDHCI_CMD_RESP_SHORT_BUSY;
164 mask |= SDHCI_INT_DATA_END;
166 flags = SDHCI_CMD_RESP_SHORT;
168 if (cmd->resp_type & MMC_RSP_CRC)
169 flags |= SDHCI_CMD_CRC;
170 if (cmd->resp_type & MMC_RSP_OPCODE)
171 flags |= SDHCI_CMD_INDEX;
173 flags |= SDHCI_CMD_DATA;
175 /*Set Transfer mode regarding to data flag*/
177 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
178 mode = SDHCI_TRNS_BLK_CNT_EN;
179 trans_bytes = data->blocks * data->blocksize;
180 if (data->blocks > 1)
181 mode |= SDHCI_TRNS_MULTI;
183 if (data->flags == MMC_DATA_READ)
184 mode |= SDHCI_TRNS_READ;
186 #ifdef CONFIG_MMC_SDMA
187 if (data->flags == MMC_DATA_READ)
188 start_addr = (unsigned int)data->dest;
190 start_addr = (unsigned int)data->src;
191 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
192 (start_addr & 0x7) != 0x0) {
194 start_addr = (unsigned int)aligned_buffer;
195 if (data->flags != MMC_DATA_READ)
196 memcpy(aligned_buffer, data->src, trans_bytes);
198 Dcache_CleanRegion(start_addr, trans_bytes);
199 Dcache_InvalRegion(start_addr, trans_bytes);
200 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
201 mode |= SDHCI_TRNS_DMA;
203 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
206 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
207 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
210 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
211 #ifdef CONFIG_MMC_SDMA
212 //flush_cache(start_addr, trans_bytes);
214 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
216 stat = sdhci_readl(host, SDHCI_INT_STATUS);
217 if (stat & SDHCI_INT_ERROR)
219 } while ((stat & mask) != mask);
221 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
222 sdhci_cmd_done(host, cmd);
223 sdhci_writel(host, mask, SDHCI_INT_STATUS);
228 ret = sdhci_transfer_data(host, data, start_addr);
230 stat = sdhci_readl(host, SDHCI_INT_STATUS);
231 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
233 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
234 !is_aligned && (data->flags == MMC_DATA_READ))
235 memcpy(data->dest, aligned_buffer, trans_bytes);
239 sdhci_reset(host, SDHCI_RESET_CMD);
240 sdhci_reset(host, SDHCI_RESET_DATA);
241 if (stat & SDHCI_INT_TIMEOUT)
247 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
249 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
250 unsigned int div, clk, timeout;
252 sdhci_sdclk_enable(host, 0);
258 /* Version 2.00 divisors must be a power of 2. */
259 #if defined(CONFIG_TIGER) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
260 for (div = 1; div < 2046; div *= 2)
262 for (div = 1; div < 256; div *= 2)
265 if ((mmc->f_max / div) <= clock)
270 #if defined(CONFIG_TIGER) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
274 #if defined (CONFIG_SPX30G)
278 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
279 clk |= SDHCI_CLOCK_INT_EN;
280 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
284 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
285 & SDHCI_CLOCK_INT_STABLE)) {
287 printf("Internal clock never stabilised.\n");
294 clk |= SDHCI_CLOCK_CARD_EN;
295 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
299 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
303 if (power != (unsigned short)-1) {
304 switch (1 << power) {
305 case MMC_VDD_165_195:
306 pwr = SDHCI_POWER_180;
310 pwr = SDHCI_POWER_300;
314 pwr = SDHCI_POWER_330;
320 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
324 pwr |= SDHCI_POWER_ON;
326 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
329 void sdhci_set_ios(struct mmc *mmc)
332 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
334 if (mmc->clock != host->clock)
335 sdhci_set_clock(mmc, mmc->clock);
338 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
339 if (mmc->bus_width == 8) {
340 ctrl &= ~SDHCI_CTRL_4BITBUS;
342 if (mmc->bus_width == 4)
343 ctrl |= SDHCI_CTRL_4BITBUS;
345 ctrl &= ~SDHCI_CTRL_4BITBUS;
348 /* high speed config is not supported on sp8830 */
349 #ifndef CONFIG_SDHCI_CTRL_NO_HISPD
350 if (mmc->clock > 26000000)
351 ctrl |= SDHCI_CTRL_HISPD;
354 ctrl &= ~SDHCI_CTRL_HISPD;
356 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
360 int sdhci_init(struct mmc *mmc)
362 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
364 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
365 aligned_buffer = memalign(8, 512*1024);
366 if (!aligned_buffer) {
367 printf("Aligned buffer alloc failed!!!");
373 /* Eable all state */
374 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
375 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
377 sdhci_set_power(host, fls(mmc->voltages) - 1);
382 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
387 mmc = malloc(sizeof(struct mmc));
389 printf("mmc malloc fail!\n");
396 sprintf(mmc->name, "%s", host->name);
397 mmc->send_cmd = sdhci_send_command;
398 mmc->set_ios = sdhci_set_ios;
399 mmc->init = sdhci_init;
401 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
402 #ifdef CONFIG_MMC_SDMA
403 if (!(caps & SDHCI_CAN_DO_SDMA)) {
404 printf("Your controller don't support sdma!!\n");
410 mmc->f_max = max_clk;
412 mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
413 >> SDHCI_CLOCK_BASE_SHIFT;
414 mmc->f_max *= 1000000;
416 if (mmc->f_max == 0) {
417 printf("Hardware doesn't specify base clock frequency\n");
421 mmc->f_min = min_clk;
424 if (caps & SDHCI_CAN_VDD_330)
425 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
426 if (caps & SDHCI_CAN_VDD_300)
427 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
428 if (caps & SDHCI_CAN_VDD_180)
429 mmc->voltages |= MMC_VDD_165_195;
430 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
431 sdhci_sdclk_enable(host, 0);
433 sdhci_reset(host, SDHCI_RESET_ALL);