1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
28 void init_ldo_sleep_gr(void)
31 #if defined(CONFIG_FPGA)
34 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x5e6f);
36 while( (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & 0x8000) != 0x8000 );
39 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
41 //BIT_DCDC_TOPCLK6M_PD |
48 //BIT_LDO_EMMCCORE_PD |
58 ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
76 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x0000);
78 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
79 BITS_SLP_IN_WAIT_DCDCARM(7) |
80 BITS_SLP_OUT_WAIT_DCDCARM(8) |
84 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
86 BIT_SLP_DCDCRF_PD_EN |
87 //BIT_SLP_DCDCCON_PD_EN |
88 //BIT_SLP_DCDCGEN_PD_EN |
89 //BIT_SLP_DCDCWPA_PD_EN |
90 BIT_SLP_DCDCARM_PD_EN |
91 BIT_SLP_LDOVDD25_PD_EN |
92 BIT_SLP_LDORF0_PD_EN |
93 BIT_SLP_LDOEMMCCORE_PD_EN |
94 BIT_SLP_LDOGEN0_PD_EN |
95 BIT_SLP_LDODCXO_PD_EN |
96 BIT_SLP_LDOGEN1_PD_EN |
97 BIT_SLP_LDOWIFIPA_PD_EN |
98 //BIT_SLP_LDOVDD28_PD_EN |
99 //BIT_SLP_LDOVDD18_PD_EN |
102 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
104 BIT_SLP_LDOLPREF_PD_EN |
105 BIT_SLP_LDOSDCORE_PD_EN |
106 BIT_SLP_LDOUSB_PD_EN |
107 BIT_SLP_LDOCAMMOT_PD_EN |
108 BIT_SLP_LDOCAMIO_PD_EN |
109 BIT_SLP_LDOCAMD_PD_EN |
110 BIT_SLP_LDOCAMA_PD_EN |
111 BIT_SLP_LDOSIM2_PD_EN |
112 //BIT_SLP_LDOSIM1_PD_EN |
113 //BIT_SLP_LDOSIM0_PD_EN |
114 //BIT_SLP_LDOSDIO_PD_EN |
118 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
119 //BIT_SLP_DCDCRF_LP_EN |
120 //BIT_SLP_DCDCCON_LP_EN |
121 BIT_SLP_DCDCCORE_LP_EN |
122 BIT_SLP_DCDCMEM_LP_EN |
123 //BIT_SLP_DCDCARM_LP_EN |
124 BIT_SLP_DCDCGEN_LP_EN |
125 //BIT_SLP_DCDCWPA_LP_EN |
126 //BIT_SLP_LDORF0_LP_EN |
127 //BIT_SLP_LDOEMMCCORE_LP_EN |
128 //BIT_SLP_LDOGEN0_LP_EN |
129 //BIT_SLP_LDODCXO_LP_EN |
130 //BIT_SLP_LDOGEN1_LP_EN |
131 //BIT_SLP_LDOWIFIPA_LP_EN |
132 //BIT_SLP_LDOVDD28_LP_EN |
133 //BIT_SLP_LDOVDD18_LP_EN |
137 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
139 //BIT_LDOVDD25_LP_EN_SW |
140 //BIT_LDOSDCORE_LP_EN_SW |
141 //BIT_LDOUSB_LP_EN_SW |
142 //BIT_SLP_LDOVDD25_LP_EN |
143 //BIT_SLP_LDOSDCORE_LP_EN |
144 //BIT_SLP_LDOUSB_LP_EN |
145 //BIT_SLP_LDOCAMMOT_LP_EN |
146 //BIT_SLP_LDOCAMIO_LP_EN |
147 //BIT_SLP_LDOCAMD_LP_EN |
148 //BIT_SLP_LDOCAMA_LP_EN |
149 //BIT_SLP_LDOSIM2_LP_EN |
150 //BIT_SLP_LDOSIM1_LP_EN |
151 //BIT_SLP_LDOSIM0_LP_EN |
152 //BIT_SLP_LDOSDIO_LP_EN |
156 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
157 //BIT_LDOCAMIO_LP_EN_SW |
158 //BIT_LDOCAMMOT_LP_EN_SW |
159 //BIT_LDOCAMD_LP_EN_SW |
160 //BIT_LDOCAMA_LP_EN_SW |
161 //BIT_LDOSIM2_LP_EN_SW |
162 //BIT_LDOSIM1_LP_EN_SW |
163 //BIT_LDOSIM0_LP_EN_SW |
164 //BIT_LDOSDIO_LP_EN_SW |
165 //BIT_LDORF0_LP_EN_SW |
166 //BIT_LDOEMMCCORE_LP_EN_SW |
167 //BIT_LDOGEN0_LP_EN_SW |
168 //BIT_LDODCXO_LP_EN_SW |
169 //BIT_LDOGEN1_LP_EN_SW |
170 //BIT_LDOWIFIPA_LP_EN_SW |
171 //BIT_LDOVDD28_LP_EN_SW |
172 //BIT_LDOVDD18_LP_EN_SW |
176 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
178 BIT_LDO_GEN0_EXT_XTL0_EN |
179 BIT_LDO_GEN0_XTL1_EN |
180 BIT_LDO_GEN0_XTL0_EN |
181 //BIT_LDO_GEN1_EXT_XTL0_EN |
182 //BIT_LDO_GEN1_XTL1_EN |
183 //BIT_LDO_GEN1_XTL0_EN |
184 BIT_LDO_DCXO_EXT_XTL0_EN |
185 BIT_LDO_DCXO_XTL1_EN |
186 BIT_LDO_DCXO_XTL0_EN |
187 //BIT_LDO_VDD18_EXT_XTL0_EN |
188 //BIT_LDO_VDD18_XTL1_EN |
189 //BIT_LDO_VDD18_XTL0_EN |
190 //BIT_LDO_VDD28_EXT_XTL0_EN |
191 //BIT_LDO_VDD28_XTL1_EN |
192 //BIT_LDO_VDD28_XTL0_EN |
196 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
197 BIT_LDO_RF0_EXT_XTL0_EN |
198 BIT_LDO_RF0_XTL1_EN |
199 BIT_LDO_RF0_XTL0_EN |
200 BIT_LDO_WIFIPA_EXT_XTL0_EN |
201 //BIT_LDO_WIFIPA_XTL1_EN |
202 //BIT_LDO_WIFIPA_XTL0_EN |
203 //BIT_LDO_SIM2_EXT_XTL0_EN |
204 //BIT_LDO_SIM2_XTL1_EN |
205 //BIT_LDO_SIM2_XTL0_EN |
206 //BIT_LDO_SIM1_EXT_XTL0_EN |
207 //BIT_LDO_SIM1_XTL1_EN |
208 //BIT_LDO_SIM1_XTL0_EN |
209 //BIT_LDO_SIM0_EXT_XTL0_EN |
210 //BIT_LDO_SIM0_XTL1_EN |
211 //BIT_LDO_SIM0_XTL0_EN |
215 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
216 BIT_LDO_VDD25_EXT_XTL0_EN |
217 BIT_LDO_VDD25_XTL1_EN |
218 BIT_LDO_VDD25_XTL0_EN |
219 BIT_DCDC_RF_EXT_XTL0_EN |
220 BIT_DCDC_RF_XTL1_EN |
221 BIT_DCDC_RF_XTL0_EN |
231 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
232 //BIT_DCDC_CON_EXT_XTL0_EN |
233 //BIT_DCDC_CON_XTL1_EN |
234 //BIT_DCDC_CON_XTL0_EN |
235 //BIT_DCDC_WPA_EXT_XTL0_EN |
236 //BIT_DCDC_WPA_XTL1_EN |
237 //BIT_DCDC_WPA_XTL0_EN |
238 BIT_DCDC_MEM_EXT_XTL0_EN |
239 BIT_DCDC_MEM_XTL1_EN |
240 BIT_DCDC_MEM_XTL0_EN |
241 BIT_DCDC_GEN_EXT_XTL0_EN |
242 BIT_DCDC_GEN_XTL1_EN |
243 BIT_DCDC_GEN_XTL0_EN |
244 BIT_DCDC_CORE_EXT_XTL0_EN |
245 BIT_DCDC_CORE_XTL1_EN |
246 BIT_DCDC_CORE_XTL0_EN |
250 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
251 BIT_SLP_XTLBUF_PD_EN |
253 BITS_XTL_WAIT(0x32) |
258 /************************************************
259 * Following is AP/CP LDO D DIE Sleep Control *
260 *************************************************/
262 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
272 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
282 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
283 BIT_XTLBUF0_ARM7_SEL |
284 BIT_XTLBUF0_VCP1_SEL |
285 BIT_XTLBUF0_VCP0_SEL |
286 BIT_XTLBUF0_CP1_SEL |
287 BIT_XTLBUF0_CP0_SEL |
292 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
293 BIT_XTLBUF1_ARM7_SEL |
294 BIT_XTLBUF1_VCP1_SEL |
295 BIT_XTLBUF1_VCP0_SEL |
296 BIT_XTLBUF1_CP1_SEL |
297 BIT_XTLBUF1_CP0_SEL |
302 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
304 //BIT_MPLL_ARM7_SEL |
305 //BIT_MPLL_VCP1_SEL |
306 //BIT_MPLL_VCP0_SEL |
313 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
315 //BIT_DPLL_ARM7_SEL |
317 //BIT_DPLL_VCP0_SEL |
324 CHIP_REG_SET(REG_PMU_APB_LTEPLL_REL_CFG,
325 //BIT_LTEPLL_REF_SEL |
326 //BIT_LTEPLL_ARM7_SEL |
327 BIT_LTEPLL_VCP1_SEL |
328 //BIT_LTEPLL_VCP0_SEL |
329 //BIT_LTEPLL_CP1_SEL |
330 //BIT_LTEPLL_CP0_SEL |
331 //BIT_LTEPLL_AP_SEL |
335 CHIP_REG_SET(REG_PMU_APB_TWPLL_REL_CFG,
336 //BIT_TWPLL_REF_SEL |
339 //BIT_TWPLL_VCP0_SEL |
340 //BIT_TWPLL_CP1_SEL |
341 //BIT_TWPLL_CP0_SEL |
346 CHIP_REG_SET(REG_PMU_APB_LVDSDIS_PLL_REL_CFG,
347 BIT_LVDSDIS_PLL_REF_SEL |
348 //BIT_LVDSDIS_PLL_ARM7_SEL |
349 //BIT_LVDSDIS_PLL_VCP1_SEL |
350 //BIT_LVDSDIS_PLL_VCP0_SEL |
351 //BIT_LVDSDIS_PLL_CP1_SEL |
352 //BIT_LVDSDIS_PLL_CP0_SEL |
353 //BIT_LVDSDIS_PLL_AP_SEL |
357 CSP_Init(0x50001800);