board/spreadtrum/sp9630fpga/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30         unsigned int reg_val;
  31 #if defined(CONFIG_FPGA)
  32         return;
  33 #endif
  34         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x5e6f);
  35 #ifndef CONFIG_FPGA
  36         while( (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & 0x8000) != 0x8000 );
  37 #endif
  38
  39         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  40                 //BIT_LDO_EMM_PD |
  41                 //BIT_DCDC_TOPCLK6M_PD |
  42                 //BIT_DCDC_RF_PD |
  43                 //BIT_DCDC_GEN_PD |
  44                 //BIT_DCDC_MEM_PD |
  45                 //BIT_DCDC_ARM_PD |
  46                 //BIT_DCDC_CORE_PD |
  47                 //BIT_LDO_RF0_PD |
  48                 //BIT_LDO_EMMCCORE_PD |
  49                 //BIT_LDO_GEN1_PD |
  50                 //BIT_LDO_DCXO_PD |
  51                 //BIT_LDO_GEN0_PD |
  52                 //BIT_LDO_VDD25_PD |
  53                 //BIT_LDO_VDD28_PD |
  54                 //BIT_LDO_VDD18_PD |
  55                 //BIT_BG_PD |
  56                 0
  57         );
  58         ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
  59                 //BIT_LDO_LPREF_PD_SW |
  60                 //BIT_DCDC_WPA_PD |
  61                 //BIT_DCDC_CON_PD |
  62                 //BIT_LDO_WIFIPA_PD |
  63                 //BIT_LDO_SDCORE_PD |
  64                 //BIT_LDO_USB_PD |
  65                 //BIT_LDO_CAMMOT_PD |
  66                 //BIT_LDO_CAMIO_PD |
  67                 //BIT_LDO_CAMD_PD |
  68                 //BIT_LDO_CAMA_PD |
  69                 //BIT_LDO_SIM2_PD |
  70                 //BIT_LDO_SIM1_PD |
  71                 //BIT_LDO_SIM0_PD |
  72                 //BIT_LDO_SDIO_PD |
  73                 0
  74         );
  75
  76         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x0000);
  77
  78         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
  79                 BITS_SLP_IN_WAIT_DCDCARM(7) |
  80                 BITS_SLP_OUT_WAIT_DCDCARM(8) |
  81                 0
  82         );
  83
  84         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  85                 BIT_SLP_IO_EN |
  86                 BIT_SLP_DCDCRF_PD_EN |
  87                 BIT_SLP_DCDCCON_PD_EN |
  88                 //BIT_SLP_DCDCGEN_PD_EN |
  89                 BIT_SLP_DCDCWPA_PD_EN |
  90                 BIT_SLP_DCDCARM_PD_EN |
  91                 BIT_SLP_LDOVDD25_PD_EN |
  92                 BIT_SLP_LDORF0_PD_EN |
  93                 BIT_SLP_LDOEMMCCORE_PD_EN |
  94                 //BIT_SLP_LDOGEN0_PD_EN |
  95                 BIT_SLP_LDODCXO_PD_EN |
  96                 //BIT_SLP_LDOGEN1_PD_EN |
  97                 BIT_SLP_LDOWIFIPA_PD_EN |
  98                 //BIT_SLP_LDOVDD28_PD_EN |
  99                 //BIT_SLP_LDOVDD18_PD_EN |
 100                 0
 101         );
 102
 103         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
 104                 BIT_SLP_LDO_PD_EN |
 105                 BIT_SLP_LDOLPREF_PD_EN |
 106                 BIT_SLP_LDOSDCORE_PD_EN |
 107                 BIT_SLP_LDOUSB_PD_EN |
 108                 BIT_SLP_LDOCAMMOT_PD_EN |
 109                 BIT_SLP_LDOCAMIO_PD_EN |
 110                 BIT_SLP_LDOCAMD_PD_EN |
 111                 BIT_SLP_LDOCAMA_PD_EN |
 112                 BIT_SLP_LDOSIM2_PD_EN |
 113                 BIT_SLP_LDOSIM1_PD_EN |
 114                 //BIT_SLP_LDOSIM0_PD_EN |
 115                 //BIT_SLP_LDOSDIO_PD_EN |
 116                 0
 117         );
 118
 119         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
 120                 //BIT_SLP_DCDCRF_LP_EN |
 121                 //BIT_SLP_DCDCCON_LP_EN |
 122                 //BIT_SLP_DCDCCORE_LP_EN |
 123                 //BIT_SLP_DCDCMEM_LP_EN |
 124                 //BIT_SLP_DCDCARM_LP_EN |
 125                 //BIT_SLP_DCDCGEN_LP_EN |
 126                 //BIT_SLP_DCDCWPA_LP_EN |
 127                 //BIT_SLP_LDORF0_LP_EN  |
 128                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 129                 //BIT_SLP_LDOGEN0_LP_EN |
 130                 //BIT_SLP_LDODCXO_LP_EN |
 131                 //BIT_SLP_LDOGEN1_LP_EN |
 132                 //BIT_SLP_LDOWIFIPA_LP_EN |
 133                 //BIT_SLP_LDOVDD28_LP_EN |
 134                 //BIT_SLP_LDOVDD18_LP_EN |
 135                 0
 136         );
 137
 138         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 139                 //BIT_SLP_BG_LP_EN |
 140                 //BIT_LDOVDD25_LP_EN_SW |
 141                 //BIT_LDOSDCORE_LP_EN_SW |
 142                 //BIT_LDOUSB_LP_EN_SW |
 143                 //BIT_SLP_LDOVDD25_LP_EN |
 144                 //BIT_SLP_LDOSDCORE_LP_EN |
 145                 //BIT_SLP_LDOUSB_LP_EN |
 146                 //BIT_SLP_LDOCAMMOT_LP_EN |
 147                 //BIT_SLP_LDOCAMIO_LP_EN |
 148                 //BIT_SLP_LDOCAMD_LP_EN |
 149                 //BIT_SLP_LDOCAMA_LP_EN |
 150                 //BIT_SLP_LDOSIM2_LP_EN |
 151                 //BIT_SLP_LDOSIM1_LP_EN |
 152                 //BIT_SLP_LDOSIM0_LP_EN |
 153                 //BIT_SLP_LDOSDIO_LP_EN |
 154                 0
 155         );
 156
 157         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
 158                 //BIT_LDOCAMIO_LP_EN_SW |
 159                 //BIT_LDOCAMMOT_LP_EN_SW |
 160                 //BIT_LDOCAMD_LP_EN_SW |
 161                 //BIT_LDOCAMA_LP_EN_SW |
 162                 //BIT_LDOSIM2_LP_EN_SW |
 163                 //BIT_LDOSIM1_LP_EN_SW |
 164                 //BIT_LDOSIM0_LP_EN_SW |
 165                 //BIT_LDOSDIO_LP_EN_SW |
 166                 //BIT_LDORF0_LP_EN_SW |
 167                 //BIT_LDOEMMCCORE_LP_EN_SW |
 168                 //BIT_LDOGEN0_LP_EN_SW |
 169                 //BIT_LDODCXO_LP_EN_SW |
 170                 //BIT_LDOGEN1_LP_EN_SW |
 171                 //BIT_LDOWIFIPA_LP_EN_SW |
 172                 //BIT_LDOVDD28_LP_EN_SW |
 173                 //BIT_LDOVDD18_LP_EN_SW |
 174                 0
 175         );
 176
 177         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 178                 BIT_LDO_XTL_EN |
 179                 //BIT_LDO_GEN0_EXT_XTL0_EN |
 180                 //BIT_LDO_GEN0_XTL1_EN |
 181                 //BIT_LDO_GEN0_XTL0_EN |
 182                 //BIT_LDO_GEN1_EXT_XTL0_EN |
 183                 //BIT_LDO_GEN1_XTL1_EN |
 184                 //BIT_LDO_GEN1_XTL0_EN |
 185                 BIT_LDO_DCXO_EXT_XTL0_EN |
 186                 BIT_LDO_DCXO_XTL1_EN |
 187                 BIT_LDO_DCXO_XTL0_EN |
 188                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 189                 //BIT_LDO_VDD18_XTL1_EN |
 190                 //BIT_LDO_VDD18_XTL0_EN |
 191                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 192                 //BIT_LDO_VDD28_XTL1_EN |
 193                 //BIT_LDO_VDD28_XTL0_EN |
 194                 0
 195         );
 196
 197         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 198                 BIT_LDO_RF0_EXT_XTL0_EN |
 199                 BIT_LDO_RF0_XTL1_EN |
 200                 BIT_LDO_RF0_XTL0_EN |
 201                 BIT_LDO_WIFIPA_EXT_XTL0_EN |
 202                 BIT_LDO_WIFIPA_XTL1_EN |
 203                 BIT_LDO_WIFIPA_XTL0_EN |
 204                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 205                 //BIT_LDO_SIM2_XTL1_EN |
 206                 //BIT_LDO_SIM2_XTL0_EN |
 207                 //BIT_LDO_SIM1_EXT_XTL0_EN |
 208                 //BIT_LDO_SIM1_XTL1_EN |
 209                 //BIT_LDO_SIM1_XTL0_EN |
 210                 //BIT_LDO_SIM0_EXT_XTL0_EN |
 211                 //BIT_LDO_SIM0_XTL1_EN |
 212                 //BIT_LDO_SIM0_XTL0_EN |
 213                 0
 214         );
 215
 216         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 217                 BIT_LDO_VDD25_EXT_XTL0_EN |
 218                 BIT_LDO_VDD25_XTL1_EN |
 219                 BIT_LDO_VDD25_XTL0_EN |
 220                 BIT_DCDC_RF_EXT_XTL0_EN |
 221                 BIT_DCDC_RF_XTL1_EN |
 222                 BIT_DCDC_RF_XTL0_EN |
 223                 BIT_XO_EXT_XTL0_EN |
 224                 BIT_XO_XTL1_EN |
 225                 BIT_XO_XTL0_EN |
 226                 BIT_BG_EXT_XTL0_EN |
 227                 BIT_BG_XTL1_EN |
 228                 BIT_BG_XTL0_EN |
 229                 0
 230         );
 231
 232         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 233                 BIT_DCDC_CON_EXT_XTL0_EN |
 234                 BIT_DCDC_CON_XTL1_EN |
 235                 BIT_DCDC_CON_XTL0_EN |
 236                 BIT_DCDC_WPA_EXT_XTL0_EN |
 237                 BIT_DCDC_WPA_XTL1_EN |
 238                 BIT_DCDC_WPA_XTL0_EN |
 239                 BIT_DCDC_MEM_EXT_XTL0_EN |
 240                 BIT_DCDC_MEM_XTL1_EN |
 241                 BIT_DCDC_MEM_XTL0_EN |
 242                 BIT_DCDC_GEN_EXT_XTL0_EN |
 243                 BIT_DCDC_GEN_XTL1_EN |
 244                 BIT_DCDC_GEN_XTL0_EN |
 245                 BIT_DCDC_CORE_EXT_XTL0_EN |
 246                 BIT_DCDC_CORE_XTL1_EN |
 247                 BIT_DCDC_CORE_XTL0_EN |
 248                 0
 249         );
 250
 251         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 252                 BIT_SLP_XTLBUF_PD_EN |
 253                 BIT_XTL_EN |
 254                 BITS_XTL_WAIT(0x32) |
 255                 0
 256         );
 257
 258
 259         /************************************************
 260         *   Following is AP/CP LDO D DIE Sleep Control   *
 261         *************************************************/
 262
 263         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 264                 BIT_XTL0_ARM7_SEL |
 265                 BIT_XTL0_VCP1_SEL |
 266                 BIT_XTL0_VCP0_SEL |
 267                 BIT_XTL0_CP1_SEL |
 268                 BIT_XTL0_CP0_SEL |
 269                 BIT_XTL0_AP_SEL |
 270                 0
 271         );
 272
 273         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 274                 BIT_XTL1_ARM7_SEL |
 275                 BIT_XTL1_VCP1_SEL |
 276                 BIT_XTL1_VCP0_SEL |
 277                 BIT_XTL1_CP1_SEL |
 278                 BIT_XTL1_CP0_SEL |
 279                 BIT_XTL1_AP_SEL |
 280                 0
 281         );
 282
 283         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 284                 BIT_XTLBUF0_ARM7_SEL |
 285                 BIT_XTLBUF0_VCP1_SEL |
 286                 BIT_XTLBUF0_VCP0_SEL |
 287                 BIT_XTLBUF0_CP1_SEL |
 288                 BIT_XTLBUF0_CP0_SEL |
 289                 BIT_XTLBUF0_AP_SEL |
 290                 0
 291         );
 292
 293         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 294                 BIT_XTLBUF1_ARM7_SEL |
 295                 BIT_XTLBUF1_VCP1_SEL |
 296                 BIT_XTLBUF1_VCP0_SEL |
 297                 BIT_XTLBUF1_CP1_SEL |
 298                 BIT_XTLBUF1_CP0_SEL |
 299                 BIT_XTLBUF1_AP_SEL |
 300                 0
 301         );
 302
 303         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 304                 //BIT_MPLL_REF_SEL |
 305                 BIT_MPLL_ARM7_SEL |
 306                 BIT_MPLL_VCP1_SEL |
 307                 BIT_MPLL_VCP0_SEL |
 308                 BIT_MPLL_CP1_SEL |
 309                 BIT_MPLL_CP0_SEL |
 310                 BIT_MPLL_AP_SEL |
 311                 0
 312         );
 313
 314         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 315                 //BIT_DPLL_REF_SEL |
 316                 BIT_DPLL_ARM7_SEL |
 317                 BIT_DPLL_VCP1_SEL |
 318                 BIT_DPLL_VCP0_SEL |
 319                 BIT_DPLL_CP1_SEL |
 320                 BIT_DPLL_CP0_SEL |
 321                 BIT_DPLL_AP_SEL |
 322                 0
 323         );
 324
 325         CHIP_REG_SET(REG_PMU_APB_LTEPLL_REL_CFG,
 326                 //BIT_LTEPLL_REF_SEL |
 327                 BIT_LTEPLL_ARM7_SEL |
 328                 BIT_LTEPLL_VCP1_SEL |
 329                 BIT_LTEPLL_VCP0_SEL |
 330                 BIT_LTEPLL_CP1_SEL |
 331                 BIT_LTEPLL_CP0_SEL |
 332                 BIT_LTEPLL_AP_SEL |
 333                 0
 334         );
 335
 336         CHIP_REG_SET(REG_PMU_APB_TWPLL_REL_CFG,
 337                 //BIT_TWPLL_REF_SEL |
 338                 BIT_TWPLL_ARM7_SEL |
 339                 BIT_TWPLL_VCP1_SEL |
 340                 BIT_TWPLL_VCP0_SEL |
 341                 BIT_TWPLL_CP1_SEL |
 342                 BIT_TWPLL_CP0_SEL |
 343                 BIT_TWPLL_AP_SEL |
 344                 0
 345         );
 346
 347         CHIP_REG_SET(REG_PMU_APB_LVDSDIS_PLL_REL_CFG,
 348                 BIT_LVDSDIS_PLL_REF_SEL |
 349                 BIT_LVDSDIS_PLL_ARM7_SEL |
 350                 BIT_LVDSDIS_PLL_VCP1_SEL |
 351                 BIT_LVDSDIS_PLL_VCP0_SEL |
 352                 BIT_LVDSDIS_PLL_CP1_SEL |
 353                 BIT_LVDSDIS_PLL_CP0_SEL |
 354                 BIT_LVDSDIS_PLL_AP_SEL |
 355                 0
 356         );
 357
 358 }