board/spreadtrum/sp7731gea_fwvga/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30         unsigned int reg_val;
  31 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
  32         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  33                 //BIT_LDO_EMM_PD |
  34                 //BIT_DCDC_TOPCLK6M_PD |
  35                 //BIT_DCDC_RF_PD |
  36                 //BIT_DCDC_GEN_PD |
  37                 //BIT_DCDC_MEM_PD |
  38                 //BIT_DCDC_ARM_PD |
  39                 //BIT_DCDC_CORE_PD |
  40                 //BIT_LDO_RF0_PD |
  41                 //BIT_LDO_EMMCCORE_PD |
  42                 //BIT_LDO_GEN1_PD |
  43                 //BIT_LDO_DCXO_PD |
  44                 //BIT_LDO_GEN0_PD |
  45                 //BIT_LDO_VDD25_PD |
  46                 //BIT_LDO_VDD28_PD |
  47                 //BIT_LDO_VDD18_PD |
  48                 //BIT_BG_PD |
  49                 0
  50         );
  51         ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
  52                 //BIT_LDO_LPREF_PD_SW |
  53                 //BIT_DCDC_WPA_PD |
  54                 //BIT_DCDC_CON_PD |
  55                 //BIT_LDO_WIFIPA_PD |
  56                 //BIT_LDO_SDCORE_PD |
  57                 //BIT_LDO_USB_PD |
  58                 //BIT_LDO_CAMMOT_PD |
  59                 //BIT_LDO_CAMIO_PD |
  60                 //BIT_LDO_CAMD_PD |
  61                 //BIT_LDO_CAMA_PD |
  62                 //BIT_LDO_SIM2_PD |
  63                 //BIT_LDO_SIM1_PD |
  64                 //BIT_LDO_SIM0_PD |
  65                 //BIT_LDO_SDIO_PD |
  66                 0
  67         );
  68         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  69                 BIT_SLP_IO_EN |
  70                 BIT_SLP_DCDCRF_PD_EN |
  71                 BIT_SLP_DCDCCON_PD_EN |
  72                 //BIT_SLP_DCDCGEN_PD_EN |
  73                 BIT_SLP_DCDCWPA_PD_EN |
  74                 BIT_SLP_DCDCARM_PD_EN |
  75                 BIT_SLP_LDOVDD25_PD_EN |
  76                 BIT_SLP_LDORF0_PD_EN |
  77                 BIT_SLP_LDOEMMCCORE_PD_EN |
  78                 //BIT_SLP_LDOGEN0_PD_EN |
  79                 BIT_SLP_LDODCXO_PD_EN |
  80                 //BIT_SLP_LDOGEN1_PD_EN |
  81                 BIT_SLP_LDOWIFIPA_PD_EN |
  82                 //BIT_SLP_LDOVDD28_PD_EN |
  83                 //BIT_SLP_LDOVDD18_PD_EN |
  84                 0
  85         );
  86         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
  87                 BIT_SLP_LDO_PD_EN |
  88                 BIT_SLP_LDOLPREF_PD_EN |
  89                 BIT_SLP_LDOSDCORE_PD_EN |
  90                 BIT_SLP_LDOUSB_PD_EN |
  91                 BIT_SLP_LDOCAMMOT_PD_EN |
  92                 BIT_SLP_LDOCAMIO_PD_EN |
  93                 BIT_SLP_LDOCAMD_PD_EN |
  94                 BIT_SLP_LDOCAMA_PD_EN |
  95                 BIT_SLP_LDOSIM2_PD_EN |
  96                 //BIT_SLP_LDOSIM1_PD_EN |
  97                 //BIT_SLP_LDOSIM0_PD_EN |
  98                 BIT_SLP_LDOSDIO_PD_EN |
  99                 0
 100         );
 101         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
 102                 //BIT_SLP_DCDCRF_LP_EN |
 103                 //BIT_SLP_DCDCCON_LP_EN |
 104                 //BIT_SLP_DCDCCORE_LP_EN |
 105                 //BIT_SLP_DCDCMEM_LP_EN |
 106                 //BIT_SLP_DCDCARM_LP_EN |
 107                 //BIT_SLP_DCDCGEN_LP_EN |
 108                 //BIT_SLP_DCDCWPA_LP_EN |
 109                 //BIT_SLP_LDORF0_LP_EN |
 110                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 111                 //BIT_SLP_LDOGEN0_LP_EN |
 112                 //BIT_SLP_LDODCXO_LP_EN |
 113                 //BIT_SLP_LDOGEN1_LP_EN |
 114                 //BIT_SLP_LDOWIFIPA_LP_EN |
 115                 //BIT_SLP_LDOVDD28_LP_EN |
 116                 //BIT_SLP_LDOVDD18_LP_EN |
 117                 0
 118         );
 119         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 120                 //BIT_SLP_BG_LP_EN |
 121                 //BIT_LDOVDD25_LP_EN_SW |
 122                 //BIT_LDOSDCORE_LP_EN_SW |
 123                 //BIT_LDOUSB_LP_EN_SW |
 124                 //BIT_SLP_LDOVDD25_LP_EN |
 125                 //BIT_SLP_LDOSDCORE_LP_EN |
 126                 //BIT_SLP_LDOUSB_LP_EN |
 127                 //BIT_SLP_LDOCAMMOT_LP_EN |
 128                 //BIT_SLP_LDOCAMIO_LP_EN |
 129                 //BIT_SLP_LDOCAMD_LP_EN |
 130                 //BIT_SLP_LDOCAMA_LP_EN |
 131                 //BIT_SLP_LDOSIM2_LP_EN |
 132                 //BIT_SLP_LDOSIM1_LP_EN |
 133                 //BIT_SLP_LDOSIM0_LP_EN |
 134                 //BIT_SLP_LDOSDIO_LP_EN |
 135                 0
 136         );
 137         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
 138                 //BIT_LDOCAMIO_LP_EN_SW |
 139                 //BIT_LDOCAMMOT_LP_EN_SW |
 140                 //BIT_LDOCAMD_LP_EN_SW |
 141                 //BIT_LDOCAMA_LP_EN_SW |
 142                 //BIT_LDOSIM2_LP_EN_SW |
 143                 //BIT_LDOSIM1_LP_EN_SW |
 144                 //BIT_LDOSIM0_LP_EN_SW |
 145                 //BIT_LDOSDIO_LP_EN_SW |
 146                 //BIT_LDORF0_LP_EN_SW |
 147                 //BIT_LDOEMMCCORE_LP_EN_SW |
 148                 //BIT_LDOGEN0_LP_EN_SW |
 149                 //BIT_LDODCXO_LP_EN_SW |
 150                 //BIT_LDOGEN1_LP_EN_SW |
 151                 //BIT_LDOWIFIPA_LP_EN_SW |
 152                 //BIT_LDOVDD28_LP_EN_SW |
 153                 //BIT_LDOVDD18_LP_EN_SW |
 154                 0
 155         );
 156         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 157                 BIT_SLP_XTLBUF_PD_EN |
 158                 BIT_XTL_EN |
 159                 BITS_XTL_WAIT(0x32) |
 160                 0
 161         );
 162
 163         /****************************************
 164         *   Following is CP LDO Sleep Control  *
 165         ****************************************/
 166         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 167                 BIT_LDO_XTL_EN |
 168                 //BIT_LDO_GEN0_EXT_XTL0_EN |
 169                 //BIT_LDO_GEN0_XTL1_EN |
 170                 //BIT_LDO_GEN0_XTL0_EN |
 171                 //BIT_LDO_GEN1_EXT_XTL0_EN |
 172                 //BIT_LDO_GEN1_XTL1_EN |
 173                 //BIT_LDO_GEN1_XTL0_EN |
 174                 BIT_LDO_DCXO_EXT_XTL0_EN |
 175                 BIT_LDO_DCXO_XTL1_EN |
 176                 BIT_LDO_DCXO_XTL0_EN |
 177                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 178                 //BIT_LDO_VDD18_XTL1_EN |
 179                 //BIT_LDO_VDD18_XTL0_EN |
 180                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 181                 //BIT_LDO_VDD28_XTL1_EN |
 182                 //BIT_LDO_VDD28_XTL0_EN |
 183                 0
 184         );
 185         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 186                 BIT_LDO_RF0_EXT_XTL0_EN |
 187                 BIT_LDO_RF0_XTL1_EN |
 188                 BIT_LDO_RF0_XTL0_EN |
 189                 BIT_LDO_WIFIPA_EXT_XTL0_EN |
 190                 BIT_LDO_WIFIPA_XTL1_EN |
 191                 BIT_LDO_WIFIPA_XTL0_EN |
 192                 BIT_LDO_SIM2_EXT_XTL0_EN |
 193                 BIT_LDO_SIM2_XTL1_EN |
 194                 BIT_LDO_SIM2_XTL0_EN |
 195                 BIT_LDO_SIM1_EXT_XTL0_EN |
 196                 BIT_LDO_SIM1_XTL1_EN |
 197                 BIT_LDO_SIM1_XTL0_EN |
 198                 BIT_LDO_SIM0_EXT_XTL0_EN |
 199                 BIT_LDO_SIM0_XTL1_EN |
 200                 BIT_LDO_SIM0_XTL0_EN |
 201                 0
 202         );
 203         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 204                 BIT_LDO_VDD25_EXT_XTL0_EN |
 205                 BIT_LDO_VDD25_XTL1_EN |
 206                 BIT_LDO_VDD25_XTL0_EN |
 207                 BIT_DCDC_RF_EXT_XTL0_EN |
 208                 BIT_DCDC_RF_XTL1_EN |
 209                 BIT_DCDC_RF_XTL0_EN |
 210                 BIT_XO_EXT_XTL0_EN |
 211                 BIT_XO_XTL1_EN |
 212                 BIT_XO_XTL0_EN |
 213                 BIT_BG_EXT_XTL0_EN |
 214                 BIT_BG_XTL1_EN |
 215                 BIT_BG_XTL0_EN |
 216                 0
 217         );
 218         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 219                 BIT_DCDC_CON_EXT_XTL0_EN |
 220                 BIT_DCDC_CON_XTL1_EN |
 221                 BIT_DCDC_CON_XTL0_EN |
 222                 BIT_DCDC_WPA_EXT_XTL0_EN |
 223                 BIT_DCDC_WPA_XTL1_EN |
 224                 BIT_DCDC_WPA_XTL0_EN |
 225                 BIT_DCDC_MEM_EXT_XTL0_EN |
 226                 BIT_DCDC_MEM_XTL1_EN |
 227                 BIT_DCDC_MEM_XTL0_EN |
 228                 BIT_DCDC_GEN_EXT_XTL0_EN |
 229                 BIT_DCDC_GEN_XTL1_EN |
 230                 BIT_DCDC_GEN_XTL0_EN |
 231                 BIT_DCDC_CORE_EXT_XTL0_EN |
 232                 BIT_DCDC_CORE_XTL1_EN |
 233                 BIT_DCDC_CORE_XTL0_EN |
 234                 0
 235         );
 236
 237
 238 #else
 239         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
 240                 //BIT_LDO_AVDD18_PD_RTCCLR |
 241                 BIT_DCDC_OTP_PD_RTCCLR |
 242                 //BIT_DCDC_WRF_PD_RTCCLR |
 243                 BIT_DCDC_GEN_PD_RTCCLR |
 244                 BIT_DCDC_MEM_PD_RTCCLR |
 245                 BIT_DCDC_ARM_PD_RTCCLR |
 246                 BIT_DCDC_CORE_PD_RTCCLR|
 247                 BIT_LDO_EMMCCORE_PD_RTCCLR |
 248                 BIT_LDO_EMMCIO_PD_RTCCLR |
 249                 BIT_LDO_RF2_PD_RTCCLR |
 250                 //BIT_LDO_RF1_PD_RTCCLR |
 251                 BIT_LDO_RF0_PD_RTCCLR |
 252                 BIT_LDO_VDD25_PD_RTCCLR |
 253                 BIT_LDO_VDD28_PD_RTCCLR |
 254                 BIT_LDO_VDD18_PD_RTCCLR |
 255                 BIT_BG_PD_RTCCLR |
 256                 0
 257         );
 258
 259         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
 260                 BIT_LDO_AVDD18_PD_RTCSET |
 261                 //BIT_DCDC_OTP_PD_RTCSET |
 262                 BIT_DCDC_WRF_PD_RTCSET |
 263                 //BIT_DCDC_GEN_PD_RTCSET |
 264                 //BIT_DCDC_MEM_PD_RTCSET |
 265                 //BIT_DCDC_ARM_PD_RTCSET |
 266                 //BIT_DCDC_CORE_PD_RTCSET|
 267                 //BIT_LDO_EMMCCORE_PD_RTCSET |
 268                 //BIT_LDO_EMMCIO_PD_RTCSET |
 269                 //BIT_LDO_RF2_PD_RTCSET |
 270                 BIT_LDO_RF1_PD_RTCSET |
 271                 //BIT_LDO_RF0_PD_RTCSET |
 272                 //BIT_LDO_VDD25_PD_RTCSET |
 273                 //BIT_LDO_VDD28_PD_RTCSET |
 274                 //BIT_LDO_VDD18_PD_RTCSET |
 275                 //BIT_BG_PD_RTCSET |
 276                 0
 277         );
 278
 279         /**********************************************
 280          *   Following is AP LDO A DIE Sleep Control  *
 281          *********************************************/
 282         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
 283                 BIT_SLP_IO_EN |
 284                 BIT_SLP_DCDC_OTP_PD_EN |
 285                 //BIT_SLP_DCDCGEN_PD_EN |
 286                 BIT_SLP_DCDCWPA_PD_EN |
 287                 //BIT_SLP_DCDCWRF_PD_EN |
 288                 BIT_SLP_DCDCARM_PD_EN |
 289                 BIT_SLP_LDOEMMCCORE_PD_EN |
 290                 BIT_SLP_LDOEMMCIO_PD_EN |
 291                 BIT_SLP_LDORF2_PD_EN |
 292                 //BIT_SLP_LDORF1_PD_EN |
 293                 BIT_SLP_LDORF0_PD_EN |
 294                 BIT_SLP_LDOVDD25_PD_EN |
 295                 //BIT_SLP_LDOVDD28_PD_EN |
 296                 //BIT_SLP_LDOVDD18_PD_EN |
 297                 0
 298         );
 299
 300         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
 301                 BIT_SLP_LDO_PD_EN |
 302                 BIT_SLP_LDOLPREF_PD_EN |
 303                 BIT_SLP_LDOCLSG_PD_EN |
 304                 BIT_SLP_LDOUSB_PD_EN |
 305                 BIT_SLP_LDOCAMMOT_PD_EN |
 306                 BIT_SLP_LDOCAMIO_PD_EN |
 307                 BIT_SLP_LDOCAMD_PD_EN |
 308                 BIT_SLP_LDOCAMA_PD_EN |
 309                 BIT_SLP_LDOSIM2_PD_EN |
 310                 //BIT_SLP_LDOSIM1_PD_EN |
 311                 //BIT_SLP_LDOSIM0_PD_EN |
 312                 BIT_SLP_LDOSD_PD_EN |
 313                 BIT_SLP_LDOAVDD18_PD_EN |
 314                 0
 315         );
 316
 317         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
 318                 //BIT_SLP_DCDC_BG_LP_EN |
 319                 //BIT_SLP_DCDCCORE_LP_EN |
 320                 //BIT_SLP_DCDCMEM_LP_EN |
 321                 //BIT_SLP_DCDCARM_LP_EN |
 322                 //BIT_SLP_DCDCGEN_LP_EN |
 323                 //BIT_SLP_DCDCWPA_LP_EN |
 324                 //BIT_SLP_DCDCWRF_LP_EN |
 325                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 326                 //BIT_SLP_LDOEMMCIO_LP_EN |
 327                 //BIT_SLP_LDORF2_LP_EN |
 328                 //BIT_SLP_LDORF1_LP_EN |
 329                 //BIT_SLP_LDORF0_LP_EN |
 330                 0
 331         );
 332
 333         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
 334                 //BIT_SLP_BG_LP_EN |
 335                 //BIT_SLP_LDOVDD25_LP_EN |
 336                 //BIT_SLP_LDOVDD28_LP_EN |
 337                 //BIT_SLP_LDOVDD18_LP_EN |
 338                 //BIT_SLP_LDOCLSG_LP_EN |
 339                 //BIT_SLP_LDOUSB_LP_EN |
 340                 //BIT_SLP_LDOCAMMOT_LP_EN |
 341                 //BIT_SLP_LDOCAMIO_LP_EN |
 342                 //BIT_SLP_LDOCAMD_LP_EN |
 343                 //BIT_SLP_LDOCAMA_LP_EN |
 344                 //BIT_SLP_LDOSIM2_LP_EN |
 345                 //BIT_SLP_LDOSIM1_LP_EN |
 346                 //BIT_SLP_LDOSIM0_LP_EN |
 347                 //BIT_SLP_LDOSD_LP_EN |
 348                 //BIT_SLP_LDOAVDD18_LP_EN |
 349                 0
 350         );
 351
 352         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 353                 BIT_SLP_XTLBUF_PD_EN |
 354                 BIT_XTL_EN |
 355                 BITS_XTL_WAIT(0x32)|
 356                 0
 357         );
 358
 359         ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
 360                 BIT_DDR2_BUF_PD_HW |
 361                 BITS_DDR2_BUF_S_DS(0x0) |
 362                 BITS_DDR2_BUF_CHNS_DS(0x0) |
 363                 //BIT_DDR2_BUF_PD |
 364                 BITS_DDR2_BUF_S(0x3) |
 365                 BITS_DDR2_BUF_CHNS(0x0) |
 366                 0
 367         );
 368
 369         /****************************************
 370         *   Following is CP LDO Sleep Control  *
 371         ****************************************/
 372
 373         ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
 374                 //BIT_LDO_VDD18_EXT_XTL2_EN |
 375                 //BIT_LDO_VDD18_EXT_XTL1_EN |
 376                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 377                 //BIT_LDO_VDD18_XTL2_EN     |
 378                 //BIT_LDO_VDD18_XTL1_EN     |
 379                 //BIT_LDO_VDD18_XTL0_EN     |
 380                 //BIT_LDO_VDD28_EXT_XTL2_EN |
 381                 //BIT_LDO_VDD28_EXT_XTL1_EN |
 382                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 383                 //BIT_LDO_VDD28_XTL2_EN     |
 384                 //BIT_LDO_VDD28_XTL1_EN     |
 385                 //BIT_LDO_VDD28_XTL0_EN     |
 386                 0
 387         );
 388
 389         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 390                 BIT_LDO_XTL_EN |
 391                 //BIT_LDO_RF1_EXT_XTL2_EN |
 392                 //BIT_LDO_RF1_EXT_XTL1_EN |
 393                 //BIT_LDO_RF1_EXT_XTL0_EN |
 394                 //BIT_LDO_RF1_XTL2_EN |
 395                 //BIT_LDO_RF1_XTL1_EN |
 396                 //BIT_LDO_RF1_XTL0_EN |
 397                 //BIT_LDO_RF0_EXT_XTL2_EN |
 398                 //BIT_LDO_RF0_EXT_XTL1_EN |
 399                 //BIT_LDO_RF0_EXT_XTL0_EN |
 400                 BIT_LDO_RF0_XTL2_EN |
 401                 BIT_LDO_RF0_XTL1_EN |
 402                 BIT_LDO_RF0_XTL0_EN |
 403                 0
 404         );
 405
 406         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 407                 //BIT_LDO_VDD25_EXT_XTL2_EN |
 408                 //BIT_LDO_VDD25_EXT_XTL1_EN |
 409                 //BIT_LDO_VDD25_EXT_XTL0_EN |
 410                 BIT_LDO_VDD25_XTL2_EN |
 411                 BIT_LDO_VDD25_XTL1_EN |
 412                 BIT_LDO_VDD25_XTL0_EN |
 413                 //BIT_LDO_RF2_EXT_XTL2_EN |
 414                 //BIT_LDO_RF2_EXT_XTL1_EN |
 415                 //BIT_LDO_RF2_EXT_XTL0_EN |
 416                 BIT_LDO_RF2_XTL2_EN |
 417                 BIT_LDO_RF2_XTL1_EN |
 418                 //BIT_LDO_RF2_XTL0_EN |
 419                 0
 420         );
 421
 422         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 423                 //BIT_LDO_AVDD18_EXT_XTL2_EN |
 424                 //BIT_LDO_AVDD18_EXT_XTL1_EN |
 425                 //BIT_LDO_AVDD18_EXT_XTL0_EN |
 426                 //BIT_LDO_AVDD18_XTL2_EN |
 427                 //BIT_LDO_AVDD18_XTL1_EN |
 428                 //BIT_LDO_AVDD18_XTL0_EN |
 429                 //BIT_LDO_SIM2_EXT_XTL2_EN |
 430                 //BIT_LDO_SIM2_EXT_XTL1_EN |
 431                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 432                 //BIT_LDO_SIM2_XTL2_EN |
 433                 //BIT_LDO_SIM2_XTL1_EN |
 434                 //BIT_LDO_SIM2_XTL0_EN |
 435                 0
 436         );
 437
 438         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 439                 //BIT_DCDC_BG_EXT_XTL2_EN |
 440                 //BIT_DCDC_BG_EXT_XTL1_EN |
 441                 //BIT_DCDC_BG_EXT_XTL0_EN |
 442                 BIT_DCDC_BG_XTL2_EN |
 443                 BIT_DCDC_BG_XTL1_EN |
 444                 BIT_DCDC_BG_XTL0_EN |
 445                 //BIT_BG_EXT_XTL2_EN |
 446                 //BIT_BG_EXT_XTL1_EN |
 447                 //BIT_BG_EXT_XTL0_EN |
 448                 //BIT_BG_XTL2_EN |
 449                 //BIT_BG_XTL1_EN |
 450                 //BIT_BG_XTL0_EN |
 451                 0
 452         );
 453
 454         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 455                 //BIT_DCDC_WRF_XTL2_EN |
 456                 //BIT_DCDC_WRF_XTL1_EN |
 457                 //BIT_DCDC_WRF_XTL0_EN |
 458                 BIT_DCDC_WPA_XTL2_EN |
 459                 //BIT_DCDC_WPA_XTL1_EN |
 460                 //BIT_DCDC_WPA_XTL0_EN |
 461                 BIT_DCDC_MEM_XTL2_EN |
 462                 BIT_DCDC_MEM_XTL1_EN |
 463                 BIT_DCDC_MEM_XTL0_EN |
 464                 BIT_DCDC_GEN_XTL2_EN |
 465                 BIT_DCDC_GEN_XTL1_EN |
 466                 BIT_DCDC_GEN_XTL0_EN |
 467                 BIT_DCDC_CORE_XTL2_EN |
 468                 BIT_DCDC_CORE_XTL1_EN |
 469                 BIT_DCDC_CORE_XTL0_EN |
 470                 0
 471         );
 472
 473         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
 474                 //BIT_DCDC_WRF_EXT_XTL2_EN |
 475                 //BIT_DCDC_WRF_EXT_XTL1_EN |
 476                 //BIT_DCDC_WRF_EXT_XTL0_EN |
 477                 //BIT_DCDC_WPA_EXT_XTL2_EN |
 478                 //BIT_DCDC_WPA_EXT_XTL1_EN |
 479                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 480                 //BIT_DCDC_MEM_EXT_XTL2_EN |
 481                 //BIT_DCDC_MEM_EXT_XTL1_EN |
 482                 //BIT_DCDC_MEM_EXT_XTL0_EN |
 483                 //BIT_DCDC_GEN_EXT_XTL2_EN |
 484                 //BIT_DCDC_GEN_EXT_XTL1_EN |
 485                 //BIT_DCDC_GEN_EXT_XTL0_EN |
 486                 //BIT_DCDC_CORE_EXT_XTL2_EN |
 487                 //BIT_DCDC_CORE_EXT_XTL1_EN |
 488                 //BIT_DCDC_CORE_EXT_XTL0_EN |
 489                 0
 490         );
 491
 492 #endif
 493         /************************************************
 494         *   Following is AP/CP LDO D DIE Sleep Control   *
 495         *************************************************/
 496
 497         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 498                 BIT_XTL0_AP_SEL |
 499                 BIT_XTL0_CP0_SEL |
 500                 BIT_XTL0_CP1_SEL |
 501                 BIT_XTL0_CP2_SEL |
 502                 0
 503         );
 504
 505         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 506                 BIT_XTL1_AP_SEL |
 507                 //BIT_XTL1_CP0_SEL |
 508                 BIT_XTL1_CP1_SEL |
 509                 BIT_XTL1_CP2_SEL |
 510                 0
 511         );
 512
 513         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 514                 //BIT_XTL2_AP_SEL |
 515                 //BIT_XTL2_CP0_SEL |
 516                 //BIT_XTL2_CP1_SEL |
 517                 BIT_XTL2_CP2_SEL |
 518                 0
 519         );
 520
 521         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 522                 BIT_XTLBUF0_CP2_SEL |
 523                 BIT_XTLBUF0_CP1_SEL |
 524                 BIT_XTLBUF0_CP0_SEL |
 525                 BIT_XTLBUF0_AP_SEL  |
 526                 0
 527         );
 528
 529         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 530                 BIT_XTLBUF1_CP2_SEL |
 531                 BIT_XTLBUF1_CP1_SEL |
 532                 BIT_XTLBUF1_CP0_SEL |
 533                 BIT_XTLBUF1_AP_SEL  |
 534                 0
 535         );
 536
 537         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 538                 //BIT_MPLL_REF_SEL |
 539                 //BIT_MPLL_CP2_SEL |
 540                 //BIT_MPLL_CP1_SEL |
 541                 //BIT_MPLL_CP0_SEL |
 542                 BIT_MPLL_AP_SEL  |
 543                 0
 544         );
 545
 546         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 547                 //BIT_DPLL_REF_SEL |
 548                 BIT_DPLL_CP2_SEL |
 549                 BIT_DPLL_CP1_SEL |
 550                 BIT_DPLL_CP0_SEL |
 551                 BIT_DPLL_AP_SEL  |
 552                 0
 553         );
 554         /*caution tdpll & wpll sel config in spl*/
 555         reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
 556         reg_val &= ~0xF;
 557         reg_val |= (
 558                    BIT_TDPLL_CP2_SEL|
 559                    BIT_TDPLL_CP1_SEL|
 560                    BIT_TDPLL_CP0_SEL|
 561                    BIT_TDPLL_AP_SEL |
 562                    0);
 563         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
 564
 565         reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
 566         reg_val &= ~0xF;
 567         reg_val |= (
 568                    //BIT_WPLL_CP2_SEL|
 569                    //BIT_WPLL_CP1_SEL|
 570                    BIT_WPLL_CP0_SEL|
 571                    //BIT_WPLL_AP_SEL |
 572                    0);
 573         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
 574
 575         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 576                 //BIT_CPLL_REF_SEL |
 577                 BIT_CPLL_CP2_SEL |
 578                 //BIT_CPLL_CP1_SEL |
 579                 //BIT_CPLL_CP0_SEL |
 580                 //BIT_CPLL_AP_SEL  |
 581                 0
 582         );
 583
 584         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 585                 BIT_WIFIPLL1_REF_SEL |
 586                 BIT_WIFIPLL1_CP2_SEL |
 587                 //BIT_WIFIPLL1_CP1_SEL |
 588                 //BIT_WIFIPLL1_CP0_SEL |
 589                 //BIT_WIFIPLL1_AP_SEL |
 590                 0
 591         );
 592
 593         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 594                 BIT_WIFIPLL2_REF_SEL |
 595                 BIT_WIFIPLL2_CP2_SEL |
 596                 //BIT_WIFIPLL2_CP1_SEL |
 597                 //BIT_WIFIPLL2_CP0_SEL |
 598                 //BIT_WIFIPLL2_AP_SEL |
 599                 0
 600         );
 601
 602         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 603                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 604                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 605                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 606                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 607                 0
 608         );
 609
 610         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 611                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 612                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 613                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 614                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 615                 0
 616         );
 617
 618         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 619                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 620                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 621                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 622                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 623                 0
 624         );
 625
 626         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 627                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 628                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 629                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 630                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 631                 0
 632         );
 633
 634         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 635                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 636                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 637                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 638                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 639                 0
 640         );
 641
 642         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 643                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 644                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 645                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 646                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 647                 0
 648         );
 649
 650         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 651                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 652                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 653                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 654                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 655                 0
 656         );
 657
 658         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 659                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 660                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 661                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 662                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 663                 0
 664         );
 665
 666         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 667                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 668                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 669                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 670                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 671                 0
 672         );
 673
 674         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
 675                 BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN        |
 676                 BITS_PD_DDR_PUBL_PWR_ON_DLY(8)          |
 677                 BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0)      |
 678                 BITS_PD_DDR_PUBL_ISO_ON_DLY(6)          |
 679                 0
 680         );
 681
 682         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
 683                 BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN         |
 684                 BITS_PD_DDR_PHY_PWR_ON_DLY(8)           |
 685                 BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0)       |
 686                 BITS_PD_DDR_PHY_ISO_ON_DLY(6)           |
 687                 0
 688         );
 689
 690         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 691                 BITS_XTL1_WAIT_CNT(0x39)                |
 692                 BITS_XTL0_WAIT_CNT(0x39)                |
 693                 0
 694         );
 695
 696         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 697                 BITS_XTLBUF1_WAIT_CNT(7)                |
 698                 BITS_XTLBUF0_WAIT_CNT(7)                |
 699                 0
 700         );
 701
 702         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 703                 BITS_WPLL_WAIT_CNT(7)                   |
 704                 BITS_TDPLL_WAIT_CNT(7)                  |
 705                 BITS_DPLL_WAIT_CNT(7)                   |
 706                 BITS_MPLL_WAIT_CNT(7)                   |
 707                 0
 708         );
 709
 710         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 711                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 712                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 713                 BITS_CPLL_WAIT_CNT(7)                   |
 714                 0
 715         );
 716
 717         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 718                 BITS_SLP_IN_WAIT_DCDCARM(7)             |
 719                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 720                 0
 721         );
 722         /*chip service package init*/
 723         CSP_Init(0);
 724 }