adade453253f84cce7bc401bbbf248a83ba4e536
[profile/mobile/platform/kernel/u-boot-tm1.git] / board / spreadtrum / sp7730ectrisim / ldo_sleep.c
1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
5
6 /***************************************************************************************************************************/
7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
15 /***************************************************************************************************************************/
16
17 /***************************************************************************************************************************/
18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
26 /***************************************************************************************************************************/
27
28 void init_ldo_sleep_gr(void)
29 {
30         /**********************************************
31          *   Following is AP LDO A DIE Sleep Control  *
32          *********************************************/
33         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
34                 BIT_SLP_IO_EN |
35                 BIT_SLP_DCDC_OTP_PD_EN |
36                 //BIT_SLP_DCDCGEN_PD_EN |
37                 BIT_SLP_DCDCWPA_PD_EN |
38                 BIT_SLP_DCDCWRF_PD_EN |
39                 BIT_SLP_DCDCARM_PD_EN |
40                 BIT_SLP_LDOEMMCCORE_PD_EN |
41                 BIT_SLP_LDOEMMCIO_PD_EN |
42                 BIT_SLP_LDORF2_PD_EN |
43                 BIT_SLP_LDORF1_PD_EN |
44                 BIT_SLP_LDORF0_PD_EN |
45                 BIT_SLP_LDOVDD25_PD_EN |
46                 //BIT_SLP_LDOVDD28_PD_EN |
47                 //BIT_SLP_LDOVDD18_PD_EN |
48                 0
49         );
50
51         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
52                 BIT_SLP_LDO_PD_EN |
53                 BIT_SLP_LDOLPREF_PD_EN |
54                 BIT_SLP_LDOCLSG_PD_EN |
55                 BIT_SLP_LDOUSB_PD_EN |
56                 BIT_SLP_LDOCAMMOT_PD_EN |
57                 BIT_SLP_LDOCAMIO_PD_EN |
58                 BIT_SLP_LDOCAMD_PD_EN |
59                 BIT_SLP_LDOCAMA_PD_EN |
60                 //BIT_SLP_LDOSIM2_PD_EN |
61                 //BIT_SLP_LDOSIM1_PD_EN |
62                 //BIT_SLP_LDOSIM0_PD_EN |
63                 BIT_SLP_LDOSD_PD_EN |
64                 BIT_SLP_LDOAVDD18_PD_EN |
65                 0
66         );
67
68         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
69                 //BIT_SLP_DCDC_BG_LP_EN |
70                 //BIT_SLP_DCDCCORE_LP_EN |
71                 //BIT_SLP_DCDCMEM_LP_EN |
72                 //BIT_SLP_DCDCARM_LP_EN |
73                 //BIT_SLP_DCDCGEN_LP_EN |
74                 //BIT_SLP_DCDCWPA_LP_EN |
75                 //BIT_SLP_DCDCWRF_LP_EN |
76                 //BIT_SLP_LDOEMMCCORE_LP_EN |
77                 //BIT_SLP_LDOEMMCIO_LP_EN |
78                 //BIT_SLP_LDORF2_LP_EN |
79                 //BIT_SLP_LDORF1_LP_EN |
80                 //BIT_SLP_LDORF0_LP_EN |
81                 0
82         );
83
84         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
85                 //BIT_SLP_BG_LP_EN |
86                 //BIT_SLP_LDOVDD25_LP_EN |
87                 //BIT_SLP_LDOVDD28_LP_EN |
88                 //BIT_SLP_LDOVDD18_LP_EN |
89                 //BIT_SLP_LDOCLSG_LP_EN |
90                 //BIT_SLP_LDOUSB_LP_EN |
91                 //BIT_SLP_LDOCAMMOT_LP_EN |
92                 //BIT_SLP_LDOCAMIO_LP_EN |
93                 //BIT_SLP_LDOCAMD_LP_EN |
94                 //BIT_SLP_LDOCAMA_LP_EN |
95                 //BIT_SLP_LDOSIM2_LP_EN |
96                 //BIT_SLP_LDOSIM1_LP_EN |
97                 //BIT_SLP_LDOSIM0_LP_EN |
98                 //BIT_SLP_LDOSD_LP_EN |
99                 //BIT_SLP_LDOAVDD18_LP_EN |
100                 0
101         );
102
103         /****************************************
104         *   Following is CP LDO Sleep Control  *
105         ****************************************/
106
107         ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
108                 //BIT_LDO_VDD18_EXT_XTL2_EN |
109                 //BIT_LDO_VDD18_EXT_XTL1_EN |
110                 //BIT_LDO_VDD18_EXT_XTL0_EN |  
111                 //BIT_LDO_VDD18_XTL2_EN     |
112                 //BIT_LDO_VDD18_XTL1_EN     |
113                 //BIT_LDO_VDD18_XTL0_EN     |
114                 //BIT_LDO_VDD28_EXT_XTL2_EN |
115                 //BIT_LDO_VDD28_EXT_XTL1_EN |
116                 //BIT_LDO_VDD28_EXT_XTL0_EN |
117                 //BIT_LDO_VDD28_XTL2_EN     |
118                 //BIT_LDO_VDD28_XTL1_EN     |
119                 //BIT_LDO_VDD28_XTL0_EN     |
120                 0
121         ); 
122
123         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
124                 BIT_LDO_XTL_EN |
125                 //BIT_LDO_RF1_EXT_XTL2_EN |
126                 //BIT_LDO_RF1_EXT_XTL1_EN |
127                 //BIT_LDO_RF1_EXT_XTL0_EN |
128                 BIT_LDO_RF1_XTL2_EN |
129                 BIT_LDO_RF1_XTL1_EN |
130                 BIT_LDO_RF1_XTL0_EN |
131                 //BIT_LDO_RF0_EXT_XTL2_EN |
132                 //BIT_LDO_RF0_EXT_XTL1_EN |
133                 //BIT_LDO_RF0_EXT_XTL0_EN |
134                 BIT_LDO_RF0_XTL2_EN |
135                 BIT_LDO_RF0_XTL1_EN |
136                 BIT_LDO_RF0_XTL0_EN |
137                 0
138         );
139
140         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
141                 //BIT_LDO_VDD25_EXT_XTL2_EN |
142                 //BIT_LDO_VDD25_EXT_XTL1_EN |
143                 //BIT_LDO_VDD25_EXT_XTL0_EN |
144                 BIT_LDO_VDD25_XTL2_EN |
145                 BIT_LDO_VDD25_XTL1_EN |
146                 BIT_LDO_VDD25_XTL0_EN |
147                 //BIT_LDO_RF2_EXT_XTL2_EN |
148                 //BIT_LDO_RF2_EXT_XTL1_EN |
149                 //BIT_LDO_RF2_EXT_XTL0_EN |
150                 BIT_LDO_RF2_XTL2_EN |
151                 BIT_LDO_RF2_XTL1_EN |
152                 BIT_LDO_RF2_XTL0_EN |
153                 0
154         );
155
156         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
157                 //BIT_LDO_AVDD18_EXT_XTL2_EN |
158                 //BIT_LDO_AVDD18_EXT_XTL1_EN |
159                 //BIT_LDO_AVDD18_EXT_XTL0_EN |
160                 //BIT_LDO_AVDD18_XTL2_EN |
161                 //BIT_LDO_AVDD18_XTL1_EN |
162                 //BIT_LDO_AVDD18_XTL0_EN |
163                 //BIT_LDO_SIM2_EXT_XTL2_EN |
164                 //BIT_LDO_SIM2_EXT_XTL1_EN |
165                 //BIT_LDO_SIM2_EXT_XTL0_EN |
166                 //BIT_LDO_SIM2_XTL2_EN |
167                 //BIT_LDO_SIM2_XTL1_EN |
168                 //BIT_LDO_SIM2_XTL0_EN |
169                 0
170         );
171
172         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
173                 //BIT_DCDC_BG_EXT_XTL2_EN |
174                 //BIT_DCDC_BG_EXT_XTL1_EN |
175                 //BIT_DCDC_BG_EXT_XTL0_EN |
176                 BIT_DCDC_BG_XTL2_EN |
177                 BIT_DCDC_BG_XTL1_EN |
178                 BIT_DCDC_BG_XTL0_EN |
179                 //BIT_BG_EXT_XTL2_EN |
180                 //BIT_BG_EXT_XTL1_EN |
181                 //BIT_BG_EXT_XTL0_EN |
182                 //BIT_BG_XTL2_EN |
183                 //BIT_BG_XTL1_EN |
184                 //BIT_BG_XTL0_EN |
185                 0
186         );
187
188         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
189                 BIT_DCDC_WRF_XTL2_EN |
190                 //BIT_DCDC_WRF_XTL1_EN |
191                 BIT_DCDC_WRF_XTL0_EN |
192                 //BIT_DCDC_WPA_XTL2_EN |
193                 //BIT_DCDC_WPA_XTL1_EN |
194                 BIT_DCDC_WPA_XTL0_EN |
195                 BIT_DCDC_MEM_XTL2_EN |
196                 BIT_DCDC_MEM_XTL1_EN |
197                 BIT_DCDC_MEM_XTL0_EN |
198                 BIT_DCDC_GEN_XTL2_EN |
199                 BIT_DCDC_GEN_XTL1_EN |
200                 BIT_DCDC_GEN_XTL0_EN |
201                 BIT_DCDC_CORE_XTL2_EN |
202                 BIT_DCDC_CORE_XTL1_EN |
203                 BIT_DCDC_CORE_XTL0_EN |
204                 0
205         );
206
207         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
208                 //BIT_DCDC_WRF_EXT_XTL2_EN |
209                 //BIT_DCDC_WRF_EXT_XTL1_EN |
210                 //BIT_DCDC_WRF_EXT_XTL0_EN |
211                 //BIT_DCDC_WPA_EXT_XTL2_EN |
212                 //BIT_DCDC_WPA_EXT_XTL1_EN |
213                 //BIT_DCDC_WPA_EXT_XTL0_EN |
214                 //BIT_DCDC_MEM_EXT_XTL2_EN |
215                 //BIT_DCDC_MEM_EXT_XTL1_EN |
216                 //BIT_DCDC_MEM_EXT_XTL0_EN |
217                 //BIT_DCDC_GEN_EXT_XTL2_EN |
218                 //BIT_DCDC_GEN_EXT_XTL1_EN |
219                 //BIT_DCDC_GEN_EXT_XTL0_EN |
220                 //BIT_DCDC_CORE_EXT_XTL2_EN |
221                 //BIT_DCDC_CORE_EXT_XTL1_EN |
222                 //BIT_DCDC_CORE_EXT_XTL0_EN |
223                 0
224         );
225
226         /************************************************
227         *   Following is AP/CP LDO D DIE Sleep Control   *
228         *************************************************/
229
230         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
231                 BIT_XTL0_AP_SEL |
232                 BIT_XTL0_CP0_SEL |
233                 BIT_XTL0_CP1_SEL |
234                 BIT_XTL0_CP2_SEL |
235                 0
236         );
237
238         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
239                 BIT_XTL1_AP_SEL |
240                 BIT_XTL1_CP0_SEL |
241                 BIT_XTL1_CP1_SEL |
242                 BIT_XTL1_CP2_SEL |
243                 0
244         );
245
246         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
247                 BIT_XTL2_AP_SEL |
248                 BIT_XTL2_CP0_SEL |
249                 BIT_XTL2_CP1_SEL |
250                 BIT_XTL2_CP2_SEL |
251                 0
252         );
253
254         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
255                 BIT_XTLBUF0_CP2_SEL |
256                 BIT_XTLBUF0_CP1_SEL |
257                 BIT_XTLBUF0_CP0_SEL |
258                 BIT_XTLBUF0_AP_SEL  |
259                 0
260         );
261
262         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
263                 BIT_XTLBUF1_CP2_SEL |
264                 BIT_XTLBUF1_CP1_SEL |
265                 BIT_XTLBUF1_CP0_SEL |
266                 BIT_XTLBUF1_AP_SEL  |
267                 0
268         );
269
270         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
271                 //BIT_MPLL_REF_SEL |
272                 //BIT_MPLL_CP2_SEL |
273                 //BIT_MPLL_CP1_SEL |
274                 //BIT_MPLL_CP0_SEL |
275                 BIT_MPLL_AP_SEL  |
276                 0
277         );
278
279         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
280                 //BIT_DPLL_REF_SEL |
281                 BIT_DPLL_CP2_SEL |
282                 BIT_DPLL_CP1_SEL |
283                 BIT_DPLL_CP0_SEL |
284                 BIT_DPLL_AP_SEL  |
285                 0
286         );
287
288         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
289                 //BIT_TDPLL_REF_SEL |
290                 BIT_TDPLL_CP2_SEL |
291                 BIT_TDPLL_CP1_SEL |
292                 BIT_TDPLL_CP0_SEL |
293                 BIT_TDPLL_AP_SEL  |
294                 0
295         );
296
297         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
298                 //BIT_WPLL_REF_SEL |
299                 //BIT_WPLL_CP2_SEL |
300                 //BIT_WPLL_CP1_SEL |
301                 BIT_WPLL_CP0_SEL |
302                 //BIT_WPLL_AP_SEL  |
303                 0
304         );
305
306         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
307                 //BIT_CPLL_REF_SEL |
308                 BIT_CPLL_CP2_SEL |
309                 BIT_CPLL_CP1_SEL |
310                 //BIT_CPLL_CP0_SEL |
311                 BIT_CPLL_AP_SEL  |
312                 0
313         );
314
315         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
316                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
317                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
318                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
319                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
320                 0
321         );
322
323         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
324                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
325                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
326                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
327                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
328                 0
329         );
330
331         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
332                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
333                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
334                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
335                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
336                 0
337         );
338
339         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
340                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
341                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
342                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
343                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
344                 0
345         );
346
347         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
348                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
349                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
350                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
351                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
352                 0
353         );
354
355         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
356                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
357                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
358                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
359                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
360                 0
361         );
362
363         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
364                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
365                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
366                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
367                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
368                 0
369         );
370
371         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
372                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
373                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
374                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
375                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
376                 0
377         );
378
379         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
380                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
381                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
382                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
383                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
384                 0
385         );
386
387         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
388                 BITS_XTL1_WAIT_CNT(0x39)                |
389                 BITS_XTL0_WAIT_CNT(0x39)                |
390                 0
391         );
392
393         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
394                 BITS_XTLBUF1_WAIT_CNT(7)                |
395                 BITS_XTLBUF0_WAIT_CNT(7)                |
396                 0
397         );
398
399         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
400                 BITS_WPLL_WAIT_CNT(7)                   |
401                 BITS_TDPLL_WAIT_CNT(7)                  |
402                 BITS_DPLL_WAIT_CNT(7)                   |
403                 BITS_MPLL_WAIT_CNT(7)                   |
404                 0
405         );
406
407         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
408                 BITS_WIFIPLL2_WAIT_CNT(7)               |
409                 BITS_WIFIPLL1_WAIT_CNT(7)               |
410                 BITS_CPLL_WAIT_CNT(7)                   |
411                 0
412         );
413
414         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
415                 BITS_SLP_IN_WAIT_DCDCARM(9)             |
416                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
417                 0
418         );
419 }