board/spreadtrum/pocket2/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30         u32 reg_val;
  31
  32         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f));
  33
  34         do{
  35                 reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT);
  36         }while(reg_val == 0);
  37
  38         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  39         BIT_DCDC_TOP_CLKF_EN|
  40         BIT_DCDC_TOP_OSC_EN|
  41         //BIT_DCDC_GEN_PD|
  42         //BIT_DCDC_MEM_PD|
  43         //BIT_DCDC_ARM_PD|
  44         //BIT_DCDC_CORE_PD|
  45         //BIT_LDO_RF0_PD|
  46         //BIT_LDO_EMMCCORE_PD|
  47         //BIT_LDO_EMMCIO_PD|
  48         //BIT_LDO_DCXO_PD|
  49         BIT_LDO_CON_PD|
  50         //BIT_LDO_VDD25_PD|
  51         //BIT_LDO_VDD28_PD|
  52         //BIT_LDO_VDD18_PD|
  53         //BIT_BG_PD|
  54         0
  55         );
  56
  57         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0));
  58
  59         /**********************************************
  60          *   Following is AP LDO A DIE Sleep Control  *
  61          *********************************************/
  62         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  63         BIT_SLP_IO_EN |
  64         //BIT_SLP_DCDCGEN_PD_EN |
  65         BIT_SLP_DCDCWPA_PD_EN |
  66         BIT_SLP_DCDCARM_PD_EN |
  67         BIT_SLP_LDORF0_PD_EN |
  68         BIT_SLP_LDOEMMCCORE_PD_EN |
  69         BIT_SLP_LDOEMMCIO_PD_EN |
  70         BIT_SLP_LDODCXO_PD_EN |
  71         BIT_SLP_LDOCON_PD_EN |
  72         BIT_SLP_LDOVDD25_PD_EN |
  73         //BIT_SLP_LDOVDD28_PD_EN |
  74         //BIT_SLP_LODVDD18_PD_EN |
  75         0
  76         );
  77
  78         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
  79         BIT_SLP_LDO_PD_EN |
  80         BIT_SLP_LDOLPREF_PD_EN |
  81         BIT_SLP_LDOCLSG_PD_EN |
  82         BIT_SLP_LDOUSB_PD_EN |
  83         BIT_SLP_LDOCAMMOT_PD_EN |
  84         BIT_SLP_LDOCAMIO_PD_EN |
  85         BIT_SLP_LDOCAMD_PD_EN |
  86         BIT_SLP_LDOCAMA_PD_EN |
  87         BIT_SLP_LDOSIM2_PD_EN |
  88         //BIT_SLP_LDOSIM1_PD_EN |
  89         //BIT_SLP_LDOSIM0_PD_EN |
  90         BIT_SLP_LDOSD_PD_EN |
  91         0);
  92
  93         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
  94         BIT_SLP_DCDCCORE_LP_EN |
  95         BIT_SLP_DCDCMEM_LP_EN |
  96         //BIT_SLP_DCDCARM_LP_EN |
  97         //BIT_SLP_DCDCGEN_LP_EN |
  98         //BIT_SLP_DCDCWPA_LP_EN |
  99         //BIT_SLP_LDORF0_LP_EN |
 100         //BIT_SLP_LDOEMMCCORE_LP_EN |
 101         //BIT_SLP_LDOEMMCIO_LP_EN |
 102         //BIT_SLP_LDODCXO_LP_EN |
 103         //BIT_SLP_LDOCON_LP_EN |
 104         //BIT_SLP_LDOVDD25_LP_EN |
 105         //BIT_SLP_LDOVDD28_LP_EN |
 106         //BIT_SLP_LDOVDD18_LP_EN |
 107         0);
 108
 109         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 110         BIT_SLP_BG_LP_EN|
 111         //BIT_SLP_LDOCLSG_LP_EN |
 112         //BIT_SLP_LDOUSB_LP_EN |
 113         //BIT_SLP_LDOCAMMOT_LP_EN |
 114         //BIT_SLP_LDOCAMIO_LP_EN |
 115         //BIT_SLP_LDOCAMD_LP_EN |
 116         //BIT_SLP_LDOCAMA_LP_EN |
 117         //BIT_SLP_LDOSIM2_LP_EN |
 118         //BIT_SLP_LDOSIM1_LP_EN |
 119         //BIT_SLP_LDOSIM0_LP_EN |
 120         //BIT_SLP_LDOSD_LP_EN |
 121         0);
 122         /****************************************
 123         *   Following is CP LDO Sleep Control  *
 124         ****************************************/
 125         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 126         BIT_LDO_XTL_EN |
 127         BIT_LDO_DCXO_EXT_XTL1_EN |
 128         BIT_LDO_DCXO_EXT_XTL0_EN |
 129         BIT_LDO_DCXO_XTL2_EN |
 130         BIT_LDO_DCXO_XTL0_EN |
 131         //BIT_LDO_VDD18_EXT_XTL1_EN |
 132         //BIT_LDO_VDD18_EXT_XTL0_EN |
 133         //BIT_LDO_VDD18_XTL2_EN |
 134         //BIT_LDO_VDD18_XTL0_EN |
 135         //BIT_LDO_VDD28_EXT_XTL1_EN |
 136         //BIT_LDO_VDD28_EXT_XTL0_EN |
 137         //BIT_LDO_VDD28_XTL2_EN |
 138         //BIT_LDO_VDD28_XTL0_EN |
 139         0);
 140
 141         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 142         BIT_LDO_RF0_EXT_XTL1_EN |
 143         BIT_LDO_RF0_EXT_XTL0_EN |
 144         BIT_LDO_RF0_XTL2_EN |
 145         BIT_LDO_RF0_XTL0_EN |
 146         //BIT_LDO_VDD25_EXT_XTL1_EN |
 147         //BIT_LDO_VDD25_EXT_XTL0_EN |
 148         BIT_LDO_VDD25_XTL2_EN |
 149         BIT_LDO_VDD25_XTL0_EN |
 150         //BIT_LDO_CON_EXT_XTL1_EN |
 151         //BIT_LDO_CON_EXT_XTL0_EN |
 152         //BIT_LDO_CON_XTL2_EN |
 153         //BIT_LDO_CON_XTL0_EN |
 154         0);
 155
 156         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 157         //BIT_LDO_SIM2_EXT_XTL1_EN |
 158         //BIT_LDO_SIM2_EXT_XTL0_EN |
 159         //BIT_LDO_SIM2_XTL2_EN |
 160         //BIT_LDO_SIM2_XTL0_EN |
 161         //BIT_LDO_SIM1_EXT_XTL1_EN |
 162         //BIT_LDO_SIM1_EXT_XTL0_EN |
 163         //BIT_LDO_SIM1_XTL2_EN |
 164         //BIT_LDO_SIM1_XTL0_EN |
 165         //BIT_LDO_SIM0_EXT_XTL1_EN |
 166         //BIT_LDO_SIM0_EXT_XTL0_EN |
 167         //BIT_LDO_SIM0_XTL2_EN |
 168         //BIT_LDO_SIM0_XTL0_EN |
 169         0);
 170
 171         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 172         //BIT_XO_EXT_XTL1_EN |
 173         //BIT_XO_EXT_XTL0_EN |
 174         //BIT_XO_XTL2_EN |
 175         //BIT_XO_XTL0_EN |
 176         //BIT_BG_EXT_XTL1_EN |
 177         //BIT_BG_EXT_XTL0_EN |
 178         BIT_BG_XTL2_EN |
 179         BIT_BG_XTL0_EN |
 180         0);
 181
 182         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 183         //BIT_DCDC_WPA_EXT_XTL1_EN |
 184         //BIT_DCDC_WPA_EXT_XTL0_EN |
 185         //BIT_DCDC_WPA_XTL2_EN |
 186         BIT_DCDC_WPA_XTL0_EN |
 187         //BIT_DCDC_MEM_EXT_XTL1_EN |
 188         //BIT_DCDC_MEM_EXT_XTL0_EN |
 189         //BIT_DCDC_MEM_XTL2_EN |
 190         //BIT_DCDC_MEM_XTL0_EN |
 191         //BIT_DCDC_GEN_EXT_XTL1_EN |
 192         //BIT_DCDC_GEN_EXT_XTL0_EN |
 193         //BIT_DCDC_GEN_XTL2_EN |
 194         //BIT_DCDC_GEN_XTL0_EN |
 195         //BIT_DCDC_CORE_EXT_XTL1_EN |
 196         //BIT_DCDC_CORE_EXT_XTL0_EN |
 197         BIT_DCDC_CORE_XTL2_EN |
 198         BIT_DCDC_CORE_XTL0_EN |
 199         0);
 200         /************************************************
 201         *   Following is AP/CP LDO D DIE Sleep Control   *
 202         *************************************************/
 203         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 204                 BIT_XTL0_AP_SEL |
 205                 BIT_XTL0_CP0_SEL |
 206                 //BIT_XTL0_CP1_SEL |
 207                 BIT_XTL0_CP2_SEL |
 208                 0
 209         );
 210
 211         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 212                 BIT_XTL1_AP_SEL |
 213                 BIT_XTL1_CP0_SEL |
 214                 //BIT_XTL1_CP1_SEL |
 215                 BIT_XTL1_CP2_SEL |
 216                 0
 217         );
 218
 219         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 220                 //BIT_XTL2_AP_SEL |
 221                 //BIT_XTL2_CP0_SEL |
 222                 //BIT_XTL2_CP1_SEL |
 223                 BIT_XTL2_CP2_SEL |
 224                 0
 225         );
 226
 227         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 228                 BIT_XTLBUF0_CP2_SEL |
 229                 BIT_XTLBUF0_CP1_SEL |
 230                 BIT_XTLBUF0_CP0_SEL |
 231                 BIT_XTLBUF0_AP_SEL  |
 232                 0
 233         );
 234
 235         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 236                 BIT_XTLBUF1_CP2_SEL |
 237                 //BIT_XTLBUF1_CP1_SEL |
 238                 BIT_XTLBUF1_CP0_SEL |
 239                 BIT_XTLBUF1_AP_SEL  |
 240                 0
 241         );
 242
 243         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 244                 //BIT_MPLL_REF_SEL |
 245                 //BIT_MPLL_CP2_SEL |
 246                 //BIT_MPLL_CP1_SEL |
 247                 //BIT_MPLL_CP0_SEL |
 248                 BIT_MPLL_AP_SEL  |
 249                 0
 250         );
 251
 252         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 253                 //BIT_DPLL_REF_SEL |
 254                 BIT_DPLL_CP2_SEL |
 255                 //BIT_DPLL_CP1_SEL |
 256                 BIT_DPLL_CP0_SEL |
 257                 BIT_DPLL_AP_SEL  |
 258                 0
 259         );
 260
 261         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
 262                 //BIT_TDPLL_REF_SEL |
 263                 BIT_TDPLL_CP2_SEL |
 264                 //BIT_TDPLL_CP1_SEL |
 265                 BIT_TDPLL_CP0_SEL |
 266                 BIT_TDPLL_AP_SEL  |
 267                 0
 268         );
 269
 270         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 271                 //BIT_WPLL_REF_SEL |
 272                 //BIT_WPLL_CP2_SEL |
 273                 //BIT_WPLL_CP1_SEL |
 274                 BIT_WPLL_CP0_SEL |
 275                 //BIT_WPLL_AP_SEL  |
 276                 0
 277         );
 278
 279         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 280                 //BIT_CPLL_REF_SEL |
 281                 BIT_CPLL_CP2_SEL |
 282                 //BIT_CPLL_CP1_SEL |
 283                 //BIT_CPLL_CP0_SEL |
 284                 //BIT_CPLL_AP_SEL  |
 285                 0
 286         );
 287
 288         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 289                 //BIT_WIFIPLL1_REF_SEL |
 290                 BIT_WIFIPLL1_CP2_SEL |
 291                 //BIT_WIFIPLL1_CP1_SEL |
 292                 //BIT_WIFIPLL1_CP0_SEL |
 293                 //BIT_WIFIPLL1_AP_SEL |
 294                 0
 295         );
 296
 297         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 298                 //BIT_WIFIPLL2_REF_SEL |
 299                 BIT_WIFIPLL2_CP2_SEL |
 300                 //BIT_WIFIPLL2_CP1_SEL |
 301                 //BIT_WIFIPLL2_CP0_SEL |
 302                 //BIT_WIFIPLL2_AP_SEL |
 303                 0
 304         );
 305
 306         CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,
 307                 BIT_CGM_208M_AP_EN |
 308                 BIT_CGM_12M_AP_EN |
 309                 BIT_CGM_24M_AP_EN |
 310                 BIT_CGM_48M_AP_EN |
 311                 BIT_CGM_51M2_AP_EN |
 312                 BIT_CGM_64M_AP_EN |
 313                 BIT_CGM_76M8_AP_EN |
 314                 BIT_CGM_96M_AP_EN |
 315                 BIT_CGM_128M_AP_EN |
 316                 BIT_CGM_153M6_AP_EN |
 317                 BIT_CGM_192M_AP_EN |
 318                 BIT_CGM_256M_AP_EN |
 319                 BIT_CGM_384M_AP_EN |
 320                 BIT_CGM_312M_AP_EN |
 321                 BIT_CGM_MPLL_AP_EN |
 322                 //BIT_CGM_WPLL_AP_EN |
 323                 //BIT_CGM_WIFIPLL1_AP_EN |
 324                 BIT_CGM_TDPLL_AP_EN |
 325                 //BIT_CGM_CPLL_AP_EN |
 326                 BIT_CGM_DPLL_AP_EN |
 327                 BIT_CGM_26M_AP_EN |
 328                 0
 329         );
 330
 331         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 332                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 333                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 334                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 335                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 336                 0
 337         );
 338
 339         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 340                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 341                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 342                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 343                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 344                 0
 345         );
 346
 347         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 348                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 349                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 350                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 351                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 352                 0
 353         );
 354
 355         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 356                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 357                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 358                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 359                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 360                 0
 361         );
 362
 363         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 364                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 365                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 366                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 367                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 368                 0
 369         );
 370
 371         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 372                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 373                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 374                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 375                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 376                 0
 377         );
 378
 379         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 380                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 381                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 382                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 383                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 384                 0
 385         );
 386
 387         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 388                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 389                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 390                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 391                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 392                 0
 393         );
 394
 395         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 396                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 397                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 398                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 399                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 400                 0
 401         );
 402
 403         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 404                 BITS_XTL1_WAIT_CNT(0x39)                |
 405                 BITS_XTL0_WAIT_CNT(0x39)                |
 406                 0
 407         );
 408
 409         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 410                 BITS_XTLBUF1_WAIT_CNT(7)                |
 411                 BITS_XTLBUF0_WAIT_CNT(7)                |
 412                 0
 413         );
 414
 415         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 416                 BITS_WPLL_WAIT_CNT(7)                   |
 417                 BITS_TDPLL_WAIT_CNT(7)                  |
 418                 BITS_DPLL_WAIT_CNT(7)                   |
 419                 BITS_MPLL_WAIT_CNT(7)                   |
 420                 0
 421         );
 422
 423         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 424                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 425                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 426                 BITS_CPLL_WAIT_CNT(7)                   |
 427                 0
 428         );
 429
 430         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 431                 BITS_SLP_IN_WAIT_DCDCARM(9)             |
 432                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 433                 0
 434         );
 435
 436         /*work round sin0 disconnect*/
 437         reg_val = CHIP_REG_GET(REG_AON_APB_SINDRV_CTRL);
 438         reg_val |= BIT_SINDRV_ENA_SQUARE;
 439         CHIP_REG_SET(REG_AON_APB_SINDRV_CTRL, reg_val);
 440 }