1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
28 #ifdef CONFIG_HARDWARE_VERSION
29 extern unsigned int get_hw_version();
32 void init_ldo_sleep_gr(void)
35 unsigned int hw_version = 0;
36 int enable_ldo_camd = 0;
39 #ifdef CONFIG_HARDWARE_VERSION
40 hw_version = get_hw_version();
44 * hardware version table
54 // enable ldocamd to prevent leakage, because gps module is changed
60 // enable ldocamd to prevent leakage, because gps module is changed
62 // use TCXO intead of VC-TCXO, so cp PLL should be changed to sine1
67 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x6e7f);
68 while( (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & 0x8000) != 0x8000 );
70 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
72 //BIT_DCDC_TOPCLK6M_PD |
79 //BIT_LDO_EMMCCORE_PD |
89 ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
98 (enable_ldo_camd ? 0 : BIT_LDO_CAMD_PD) |
107 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x0000);
109 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
110 BITS_SLP_IN_WAIT_DCDCARM(7) |
111 BITS_SLP_OUT_WAIT_DCDCARM(8) |
115 reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_SHPT_PD2);
117 ANA_REG_SET(ANA_REG_GLB_LDO_SHPT_PD2,reg_val);
119 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
121 BIT_SLP_DCDCRF_PD_EN |
122 BIT_SLP_DCDCCON_PD_EN |
123 //BIT_SLP_DCDCGEN_PD_EN |
124 //BIT_SLP_DCDCWPA_PD_EN |
125 BIT_SLP_DCDCARM_PD_EN |
126 BIT_SLP_LDOVDD25_PD_EN |
127 BIT_SLP_LDORF0_PD_EN |
128 BIT_SLP_LDOEMMCCORE_PD_EN |
129 BIT_SLP_LDOGEN0_PD_EN |
130 BIT_SLP_LDODCXO_PD_EN |
131 BIT_SLP_LDOGEN1_PD_EN |
132 BIT_SLP_LDOWIFIPA_PD_EN |
133 //BIT_SLP_LDOVDD28_PD_EN |
134 //BIT_SLP_LDOVDD18_PD_EN |
137 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
139 BIT_SLP_LDOLPREF_PD_EN |
140 BIT_SLP_LDOSDCORE_PD_EN |
141 BIT_SLP_LDOUSB_PD_EN |
142 BIT_SLP_LDOCAMMOT_PD_EN |
143 BIT_SLP_LDOCAMIO_PD_EN |
144 (enable_ldo_camd ? 0 : BIT_SLP_LDOCAMD_PD_EN) |
145 BIT_SLP_LDOCAMA_PD_EN |
146 BIT_SLP_LDOSIM2_PD_EN |
147 //BIT_SLP_LDOSIM1_PD_EN |
148 //BIT_SLP_LDOSIM0_PD_EN |
149 //BIT_SLP_LDOSDIO_PD_EN |
153 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
154 //BIT_SLP_DCDCRF_LP_EN |
155 //BIT_SLP_DCDCCON_LP_EN |
156 BIT_SLP_DCDCCORE_LP_EN |
157 BIT_SLP_DCDCMEM_LP_EN |
158 //BIT_SLP_DCDCARM_LP_EN |
159 BIT_SLP_DCDCGEN_LP_EN |
160 //BIT_SLP_DCDCWPA_LP_EN |
161 //BIT_SLP_LDORF0_LP_EN |
162 //BIT_SLP_LDOEMMCCORE_LP_EN |
163 //BIT_SLP_LDOGEN0_LP_EN |
164 //BIT_SLP_LDODCXO_LP_EN |
165 //BIT_SLP_LDOGEN1_LP_EN |
166 //BIT_SLP_LDOWIFIPA_LP_EN |
167 //BIT_SLP_LDOVDD28_LP_EN |
168 //BIT_SLP_LDOVDD18_LP_EN |
172 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
174 //BIT_LDOVDD25_LP_EN_SW |
175 //BIT_LDOSDCORE_LP_EN_SW |
176 //BIT_LDOUSB_LP_EN_SW |
177 //BIT_SLP_LDOVDD25_LP_EN |
178 //BIT_SLP_LDOSDCORE_LP_EN |
179 //BIT_SLP_LDOUSB_LP_EN |
180 //BIT_SLP_LDOCAMMOT_LP_EN |
181 //BIT_SLP_LDOCAMIO_LP_EN |
182 //BIT_SLP_LDOCAMD_LP_EN |
183 //BIT_SLP_LDOCAMA_LP_EN |
184 //BIT_SLP_LDOSIM2_LP_EN |
185 //BIT_SLP_LDOSIM1_LP_EN |
186 //BIT_SLP_LDOSIM0_LP_EN |
187 //BIT_SLP_LDOSDIO_LP_EN |
191 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
192 //BIT_LDOCAMIO_LP_EN_SW |
193 //BIT_LDOCAMMOT_LP_EN_SW |
194 //BIT_LDOCAMD_LP_EN_SW |
195 //BIT_LDOCAMA_LP_EN_SW |
196 //BIT_LDOSIM2_LP_EN_SW |
197 //BIT_LDOSIM1_LP_EN_SW |
198 //BIT_LDOSIM0_LP_EN_SW |
199 //BIT_LDOSDIO_LP_EN_SW |
200 //BIT_LDORF0_LP_EN_SW |
201 //BIT_LDOEMMCCORE_LP_EN_SW |
202 //BIT_LDOGEN0_LP_EN_SW |
203 //BIT_LDODCXO_LP_EN_SW |
204 //BIT_LDOGEN1_LP_EN_SW |
205 //BIT_LDOWIFIPA_LP_EN_SW |
206 //BIT_LDOVDD28_LP_EN_SW |
207 //BIT_LDOVDD18_LP_EN_SW |
211 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
213 BIT_LDO_GEN0_EXT_XTL0_EN |
214 BIT_LDO_GEN0_XTL1_EN |
215 BIT_LDO_GEN0_XTL0_EN |
216 //BIT_LDO_GEN1_EXT_XTL0_EN |
217 //BIT_LDO_GEN1_XTL1_EN |
218 //BIT_LDO_GEN1_XTL0_EN |
219 BIT_LDO_DCXO_EXT_XTL0_EN |
220 BIT_LDO_DCXO_XTL1_EN |
221 BIT_LDO_DCXO_XTL0_EN |
222 //BIT_LDO_VDD18_EXT_XTL0_EN |
223 //BIT_LDO_VDD18_XTL1_EN |
224 //BIT_LDO_VDD18_XTL0_EN |
225 //BIT_LDO_VDD28_EXT_XTL0_EN |
226 //BIT_LDO_VDD28_XTL1_EN |
227 //BIT_LDO_VDD28_XTL0_EN |
231 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
232 BIT_LDO_RF0_EXT_XTL0_EN |
233 BIT_LDO_RF0_XTL1_EN |
234 BIT_LDO_RF0_XTL0_EN |
235 //BIT_LDO_WIFIPA_EXT_XTL0_EN |
236 //BIT_LDO_WIFIPA_XTL1_EN |
237 //BIT_LDO_WIFIPA_XTL0_EN |
238 //BIT_LDO_SIM2_EXT_XTL0_EN |
239 //BIT_LDO_SIM2_XTL1_EN |
240 //BIT_LDO_SIM2_XTL0_EN |
241 //BIT_LDO_SIM1_EXT_XTL0_EN |
242 //BIT_LDO_SIM1_XTL1_EN |
243 //BIT_LDO_SIM1_XTL0_EN |
244 //BIT_LDO_SIM0_EXT_XTL0_EN |
245 //BIT_LDO_SIM0_XTL1_EN |
246 //BIT_LDO_SIM0_XTL0_EN |
250 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
251 BIT_LDO_VDD25_EXT_XTL0_EN |
252 BIT_LDO_VDD25_XTL1_EN |
253 BIT_LDO_VDD25_XTL0_EN |
254 BIT_DCDC_RF_EXT_XTL0_EN |
255 BIT_DCDC_RF_XTL1_EN |
256 BIT_DCDC_RF_XTL0_EN |
266 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
267 //BIT_DCDC_CON_EXT_XTL0_EN |
268 //BIT_DCDC_CON_XTL1_EN |
269 //BIT_DCDC_CON_XTL0_EN |
270 //BIT_DCDC_WPA_EXT_XTL0_EN |
271 //BIT_DCDC_WPA_XTL1_EN |
272 //BIT_DCDC_WPA_XTL0_EN |
273 BIT_DCDC_MEM_EXT_XTL0_EN |
274 BIT_DCDC_MEM_XTL1_EN |
275 BIT_DCDC_MEM_XTL0_EN |
276 BIT_DCDC_GEN_EXT_XTL0_EN |
277 BIT_DCDC_GEN_XTL1_EN |
278 BIT_DCDC_GEN_XTL0_EN |
279 BIT_DCDC_CORE_EXT_XTL0_EN |
280 BIT_DCDC_CORE_XTL1_EN |
281 BIT_DCDC_CORE_XTL0_EN |
285 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
286 BIT_SLP_XTLBUF_PD_EN |
288 BITS_XTL_WAIT(0x32) |
293 /************************************************
294 * Following is AP/CP LDO D DIE Sleep Control *
295 *************************************************/
298 REG32(REG_PMU_APB_26M_SEL_CFG) |= (BIT_CP1_26M_SEL | BIT_CP0_26M_SEL);
300 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
310 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
320 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
321 BIT_XTLBUF0_ARM7_SEL |
322 BIT_XTLBUF0_VCP1_SEL |
323 BIT_XTLBUF0_VCP0_SEL |
324 BIT_XTLBUF0_CP1_SEL |
325 BIT_XTLBUF0_CP0_SEL |
330 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
331 BIT_XTLBUF1_ARM7_SEL |
332 BIT_XTLBUF1_VCP1_SEL |
333 BIT_XTLBUF1_VCP0_SEL |
334 BIT_XTLBUF1_CP1_SEL |
335 BIT_XTLBUF1_CP0_SEL |
340 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
342 //BIT_MPLL_ARM7_SEL |
343 //BIT_MPLL_VCP1_SEL |
344 //BIT_MPLL_VCP0_SEL |
351 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
353 //BIT_DPLL_ARM7_SEL |
355 //BIT_DPLL_VCP0_SEL |
362 CHIP_REG_SET(REG_PMU_APB_LTEPLL_REL_CFG,
363 (cp_on_sine1 ? BIT_LTEPLL_REF_SEL : 0) |
364 //BIT_LTEPLL_ARM7_SEL |
365 BIT_LTEPLL_VCP1_SEL |
366 //BIT_LTEPLL_VCP0_SEL |
367 //BIT_LTEPLL_CP1_SEL |
368 //BIT_LTEPLL_CP0_SEL |
369 //BIT_LTEPLL_AP_SEL |
373 CHIP_REG_SET(REG_PMU_APB_TWPLL_REL_CFG,
374 (cp_on_sine1 ? BIT_TWPLL_REF_SEL : 0) |
377 //BIT_TWPLL_VCP0_SEL |
378 //BIT_TWPLL_CP1_SEL |
379 //BIT_TWPLL_CP0_SEL |
384 CHIP_REG_SET(REG_PMU_APB_LVDSDIS_PLL_REL_CFG,
385 BIT_LVDSDIS_PLL_REF_SEL |
386 //BIT_LVDSDIS_PLL_ARM7_SEL |
387 //BIT_LVDSDIS_PLL_VCP1_SEL |
388 //BIT_LVDSDIS_PLL_VCP0_SEL |
389 //BIT_LVDSDIS_PLL_CP1_SEL |
390 //BIT_LVDSDIS_PLL_CP0_SEL |
391 //BIT_LVDSDIS_PLL_AP_SEL |
395 CSP_Init(0x50001800);