board/samsung/goni/mem_setup.S

   1 /*
   2  * Copyright (C) 2009 Samsung Electrnoics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26
  27         .globl mem_ctrl_asm_init
  28 mem_ctrl_asm_init:
  29         cmp     r7, r8
  30
  31         ldreq   r0, =S5PC100_DMC_BASE                   @ 0xE6000000
  32         ldrne   r0, =S5PC110_DMC0_BASE                  @ 0xF0000000
  33         ldrne   r6, =S5PC110_DMC1_BASE                  @ 0xF1400000
  34
  35         /* DLL parameter setting */
  36         ldr     r1, =0x50101000
  37         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  38         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  39         ldr     r1, =0x000000f4
  40         str     r1, [r0, #0x01C]                        @ PHYCONTROL1_OFFSET
  41         strne   r1, [r6, #0x01C]                        @ PHYCONTROL1_OFFSET
  42         ldreq   r1, =0x0
  43         streq   r1, [r0, #0x020]                        @ PHYCONTROL2_OFFSET
  44
  45         /* DLL on */
  46         ldr     r1, =0x50101002
  47         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  48         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  49
  50         /* DLL start */
  51         ldr     r1, =0x50101003
  52         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  53         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  54
  55         mov     r2, #0x4000
  56 wait:   subs    r2, r2, #0x1
  57         cmp     r2, #0x0
  58         bne     wait
  59
  60         cmp     r7, r8
  61         /* Force value locking for DLL off */
  62         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  63         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  64
  65         /* DLL off */
  66         ldr     r1, =0x50101009
  67         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  68         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  69
  70         /* auto refresh off */
  71         ldr     r1, =0xff001010 | (1 << 7)
  72         ldr     r2, =0xff001010 | (1 << 7)
  73         str     r1, [r0, #0x000]                        @ CONCONTROL_OFFSET
  74         strne   r2, [r6, #0x000]                        @ CONCONTROL_OFFSET
  75
  76         /*
  77          * Burst Length 4, 2 chips, 32-bit, LPDDR
  78          * OFF: dynamic self refresh, force precharge, dynamic power down off
  79          */
  80         ldr     r1, =0x00212100
  81         ldr     r2, =0x00212100
  82         str     r1, [r0, #0x004]                        @ MEMCONTROL_OFFSET
  83         strne   r2, [r6, #0x004]                        @ MEMCONTROL_OFFSET
  84
  85         /*
  86          * Note:
  87          * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
  88          * So finally Bank1 OneDRAM should address start at at 0x3000'0000
  89          */
  90
  91         /*
  92          * DMC0: CS0 : S5PC100/S5PC110
  93          * 0x30 -> 0x30000000
  94          * 0xf8 -> 0x37FFFFFF
  95          * [15:12] 0: Linear
  96          * [11:8 ] 2: 9 bits
  97          * [ 7:4 ] 2: 14 bits
  98          * [ 3:0 ] 2: 4 banks
  99          */
 100         ldr     r3, =0x30f80222
 101         ldr     r4, =0x40f00222
 102 swap_memory:
 103         str     r3, [r0, #0x008]                        @ MEMCONFIG0_OFFSET
 104         str     r4, [r0, #0x00C]                        @ dummy write
 105
 106         /*
 107          * DMC1: CS0 : S5PC110
 108          * 0x40 -> 0x40000000
 109          * 0xf8 -> 0x47FFFFFF (1Gib)
 110          * 0x40 -> 0x40000000
 111          * 0xf0 -> 0x4FFFFFFF (2Gib)
 112          * [15:12] 0: Linear
 113          * [11:8 ] 2: 9 bits  - Col (1Gib)
 114          * [11:8 ] 3: 10 bits - Col (2Gib)
 115          * [ 7:4 ] 2: 14 bits - Row
 116          * [ 3:0 ] 2: 4 banks
 117          */
 118         /* Default : 2GiB */
 119         ldr     r4, =0x40f01322                         @ 2Gib: MCP B
 120         ldr     r5, =0x50f81312                         @ dummy: MCP D
 121         cmp     r9, #1
 122         ldreq   r4, =0x40f81222                         @ 1Gib: MCP A
 123         cmp     r9, #3
 124         ldreq   r5, =0x50f81312                         @ 2Gib + 1Gib: MCP D
 125         cmp     r9, #4
 126         ldreq   r5, =0x50f01312                         @ 2Gib + 2Gib: MCP E
 127
 128         cmp     r7, r8
 129         strne   r4, [r6, #0x008]                        @ MEMCONFIG0_OFFSET
 130         strne   r5, [r6, #0x00C]                        @ MEMCONFIG1_OFFSET
 131
 132         /*
 133          * DMC0: CS1: S5PC100
 134          * 0x38 -> 0x38000000
 135          * 0xf8 -> 0x3fFFFFFF
 136          * [15:12] 0: Linear
 137          * [11:8 ] 2: 9 bits
 138          * [ 7:4 ] 2: 14 bits
 139          * [ 3:0 ] 2: 4 banks
 140          */
 141         eoreq   r3, r3, #0x08000000
 142         streq   r3, [r0, #0xc]                          @ MEMCONFIG1_OFFSET
 143
 144         ldr     r1, =0x20000000
 145         str     r1, [r0, #0x014]                        @ PRECHCONFIG_OFFSET
 146         strne   r1, [r0, #0x014]                        @ PRECHCONFIG_OFFSET
 147         strne   r1, [r6, #0x014]                        @ PRECHCONFIG_OFFSET
 148
 149         /*
 150          * S5PC100:
 151          * DMC:  CS0: 166MHz
 152          *       CS1: 166MHz
 153          * S5PC110:
 154          * DMC0: CS0: 166MHz
 155          * DMC1: CS0: 200MHz
 156          *
 157          * 7.8us * 200MHz %LE %LONG1560(0x618)
 158          * 7.8us * 166MHz %LE %LONG1294(0x50E)
 159          * 7.8us * 133MHz %LE %LONG1038(0x40E),
 160          * 7.8us * 100MHz %LE %LONG780(0x30C),
 161          */
 162         ldr     r1, =0x0000050E
 163         str     r1, [r0, #0x030]                        @ TIMINGAREF_OFFSET
 164         ldrne   r1, =0x00000618
 165         strne   r1, [r6, #0x030]                        @ TIMINGAREF_OFFSET
 166
 167         ldr     r1, =0x14233287
 168         str     r1, [r0, #0x034]                        @ TIMINGROW_OFFSET
 169         ldrne   r1, =0x182332c8
 170         strne   r1, [r6, #0x034]                        @ TIMINGROW_OFFSET
 171
 172         ldr     r1, =0x12130005
 173         str     r1, [r0, #0x038]                        @ TIMINGDATA_OFFSET
 174         ldrne   r1, =0x13130005
 175         strne   r1, [r6, #0x038]                        @ TIMINGDATA_OFFSET
 176
 177         ldr     r1, =0x0E140222
 178         str     r1, [r0, #0x03C]                        @ TIMINGPOWER_OFFSET
 179         ldrne   r1, =0x0E180222
 180         strne   r1, [r6, #0x03C]                        @ TIMINGPOWER_OFFSET
 181
 182         /* chip0 Deselect */
 183         ldr     r1, =0x07000000
 184         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 185         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 186
 187         /* chip0 PALL */
 188         ldr     r1, =0x01000000
 189         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 190         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 191
 192         /* chip0 REFA */
 193         ldr     r1, =0x05000000
 194         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 195         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 196         /* chip0 REFA */
 197         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 198         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 199
 200         /* chip0 MRS */
 201         ldr     r1, =0x00000032
 202         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 203         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 204
 205         /* chip0 EMRS */
 206         ldr     r1, =0x00020020
 207         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 208         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 209
 210         /* chip1 Deselect */
 211         ldr     r1, =0x07100000
 212         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 213         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 214
 215         /* chip1 PALL */
 216         ldr     r1, =0x01100000
 217         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 218         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 219
 220         /* chip1 REFA */
 221         ldr     r1, =0x05100000
 222         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 223         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 224         /* chip1 REFA */
 225         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 226         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 227
 228         /* chip1 MRS */
 229         ldr     r1, =0x00100032
 230         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 231         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 232
 233         /* chip1 EMRS */
 234         ldr     r1, =0x00120020
 235         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 236         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 237
 238         /* auto refresh on */
 239         ldr     r1, =0xFF002030 | (1 << 7)
 240         str     r1, [r0, #0x000]                        @ CONCONTROL_OFFSET
 241         strne   r1, [r6, #0x000]                        @ CONCONTROL_OFFSET
 242
 243         /* PwrdnConfig */
 244         ldr     r1, =0x00100002
 245         str     r1, [r0, #0x028]                        @ PWRDNCONFIG_OFFSET
 246         strne   r1, [r6, #0x028]                        @ PWRDNCONFIG_OFFSET
 247
 248         ldr     r1, =0x00212113
 249         str     r1, [r0, #0x004]                        @ MEMCONTROL_OFFSET
 250         strne   r1, [r6, #0x004]                        @ MEMCONTROL_OFFSET
 251
 252         /* Skip when S5PC110 */
 253         bne     1f
 254
 255         /* Check OneDRAM access area at s5pc100 */
 256         ldreq   r3, =0x38f80222
 257         ldreq   r1, =0x37ffff00
 258         str     r3, [r1]
 259         ldr     r2, [r1]
 260         cmp     r2, r3
 261         beq     swap_memory
 262 1:
 263         mov     pc, lr
 264
 265         .ltorg