board/etin/kvme080/multiverse.c

   1 /*
   2  * multiverse.c
   3  *
   4  * VME driver for Multiverse
   5  *
   6  * Author : Sangmoon Kim
   7  *          dogoil@etinsys.com
   8  *
   9  * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #include <common.h>
  18 #include <asm/io.h>
  19 #include <pci.h>
  20
  21 #include "multiverse.h"
  22
  23 static unsigned long vme_asi_addr;
  24 static unsigned long vme_iack_addr;
  25 static unsigned long pci_reg_addr;
  26 static unsigned long vme_reg_addr;
  27
  28 int multiv_reset(unsigned long base)
  29 {
  30         writeb(0x09, base + VME_SLAVE32_AM);
  31         writeb(0x39, base + VME_SLAVE24_AM);
  32         writeb(0x29, base + VME_SLAVE16_AM);
  33         writeb(0x2f, base + VME_SLAVE_REG_AM);
  34         writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
  35         writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
  36         writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
  37 #ifdef A32_SLV_WINDOW
  38         if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
  39                 writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
  40                                 base + VME_SLAVE32_MASK);
  41                 writeb(0x01, base + VME_SLAVE32_EN);
  42         } else {
  43                 writeb(0xff, base + VME_SLAVE32_MASK);
  44                 writeb(0x00, base + VME_SLAVE32_EN);
  45         }
  46 #else
  47         writeb(0xff, base + VME_SLAVE32_MASK);
  48         writeb(0x00, base + VME_SLAVE32_EN);
  49 #endif
  50 #ifdef A24_SLV_WINDOW
  51         if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
  52                 writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
  53                                 base + VME_SLAVE24_MASK);
  54                 writeb(0x01, base + VME_SLAVE24_EN);
  55         } else {
  56                 writeb(0xff, base + VME_SLAVE24_MASK);
  57                 writeb(0x00, base + VME_SLAVE24_EN);
  58         }
  59 #else
  60         writeb(0xff, base + VME_SLAVE24_MASK);
  61         writeb(0x00, base + VME_SLAVE24_EN);
  62 #endif
  63 #ifdef A16_SLV_WINDOW
  64         if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
  65                 writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
  66                                 base + VME_SLAVE16_MASK);
  67                 writeb(0x01, base + VME_SLAVE16_EN);
  68         } else {
  69                 writeb(0xff, base + VME_SLAVE16_MASK);
  70                 writeb(0x00, base + VME_SLAVE16_EN);
  71         }
  72 #else
  73         writeb(0xff, base + VME_SLAVE16_MASK);
  74         writeb(0x00, base + VME_SLAVE16_EN);
  75 #endif
  76 #ifdef REG_SLV_WINDOW
  77         if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
  78                 writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
  79                                 base + VME_SLAVE_REG_MASK);
  80                 writeb(0x01, base + VME_SLAVE_REG_EN);
  81         } else {
  82                 writeb(0xf8, base + VME_SLAVE_REG_MASK);
  83         }
  84 #else
  85         writeb(0xf8, base + VME_SLAVE_REG_MASK);
  86 #endif
  87         writeb(0x09, base + VME_MASTER32_AM);
  88         writeb(0x39, base + VME_MASTER24_AM);
  89         writeb(0x29, base + VME_MASTER16_AM);
  90         writeb(0x2f, base + VME_MASTER_REG_AM);
  91         writel(0x00000000, base + VME_RMW_ADRS);
  92         writeb(0x00, base + VME_IRQ);
  93         writeb(0x00, base + VME_INT_EN);
  94         writel(0x00000000, base + VME_IRQ1_REG);
  95         writel(0x00000000, base + VME_IRQ2_REG);
  96         writel(0x00000000, base + VME_IRQ3_REG);
  97         writel(0x00000000, base + VME_IRQ4_REG);
  98         writel(0x00000000, base + VME_IRQ5_REG);
  99         writel(0x00000000, base + VME_IRQ6_REG);
 100         writel(0x00000000, base + VME_IRQ7_REG);
 101         return 0;
 102 }
 103
 104 void multiv_auto_slot_id(unsigned long base)
 105 {
 106         unsigned int vector;
 107         int slot_id = 1;
 108         if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
 109                 *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
 110                 writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
 111                 writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
 112                                 base + VME_CTRL);
 113                 while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
 114                 if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
 115                         while (readb(base + VME_INT) & 0x04) {
 116                                 vector = *(volatile unsigned int*)
 117                                         (vme_iack_addr + VME_IACK2);
 118                                 *(unsigned char*)(vme_asi_addr + 0x7ffff)
 119                                         = (slot_id << 3) & 0xff;
 120                                 slot_id ++;
 121                                 if (slot_id > 31)
 122                                         break;
 123                         }
 124                 }
 125         }
 126 }
 127
 128 int multiverse_init(void)
 129 {
 130         int i;
 131         pci_dev_t pdev;
 132         unsigned int bar[6];
 133
 134         pdev = pci_find_device(0x1895, 0x0001, 0);
 135
 136         if (pdev == 0)
 137                 return -1;
 138
 139         for (i = 0; i < 6; i++)
 140                 pci_read_config_dword (pdev,
 141                                 PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
 142
 143         pci_reg_addr = bar[0];
 144         vme_reg_addr = bar[1] + 0x00F00000;
 145         vme_iack_addr = bar[1] + 0x00200000;
 146         vme_asi_addr = bar[3];
 147
 148         pci_write_config_dword (pdev, PCI_COMMAND,
 149                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 150
 151         writel(0xFF000000, pci_reg_addr + P_TA1);
 152         writel(0x04, pci_reg_addr + P_IMG_CTRL1);
 153         writel(0xf0000000, pci_reg_addr + P_TA2);
 154         writel(0x04, pci_reg_addr + P_IMG_CTRL2);
 155         writel(0xF1000000, pci_reg_addr + P_TA3);
 156         writel(0x04, pci_reg_addr + P_IMG_CTRL3);
 157         writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
 158         writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
 159         writel(0x04, pci_reg_addr + P_IMG_CTRL5);
 160
 161         writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
 162         writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
 163         writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
 164         writel(0x04, pci_reg_addr + W_IMG_CTRL1);
 165
 166         writel(0xF0000000, pci_reg_addr + W_BA2);
 167         writel(0xFF000000, pci_reg_addr + W_AM2);
 168         writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
 169         writel(0x04, pci_reg_addr + W_IMG_CTRL2);
 170
 171         writel(0xFF000000, pci_reg_addr + W_BA3);
 172         writel(0xFF000000, pci_reg_addr + W_AM3);
 173         writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
 174         writel(0x04, pci_reg_addr + W_IMG_CTRL3);
 175
 176         writel(0x00000001, pci_reg_addr + W_ERR_CS);
 177         writel(0x00000001, pci_reg_addr + P_ERR_CS);
 178
 179         multiv_reset(vme_reg_addr);
 180         writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
 181                 vme_reg_addr + VME_CTRL);
 182
 183         multiv_auto_slot_id(vme_reg_addr);
 184
 185         return 0;
 186 }