arch/arm/include/asm/arch-tiger/sc8810_reg_base.h

   1 /******************************************************************************
   2  ** File Name:      sc8810_reg_base.h                                            *
   3  ** Author:         Tim.Luo                                                   *
   4  ** DATE:           07/08/2010                                                *
   5  ** Copyright:      2010 Spreadtrum, Incoporated. All Rights Reserved.        *
   6  ** Description:                                                              *
   7  **                                                                           *
   8  ******************************************************************************
   9
  10  ******************************************************************************
  11  **                        Edit History                                       *
  12  ** ------------------------------------------------------------------------- *
  13  ** DATE           NAME             DESCRIPTION                               *
  14  ** 07/08/2010     Tim.Luo          Create.                                   *
  15   ******************************************************************************/
  16
  17 #ifndef _SC8810_REG_BASE_H_
  18 #define _SC8810_REG_BASE_H_
  19
  20 #ifdef   __cplusplus
  21 extern   "C"
  22 {
  23 #endif
  24 /**---------------------------------------------------------------------------*
  25  **                         Constant Variables                                *
  26  **---------------------------------------------------------------------------*/
  27 /*----------memory map address----------*/
  28 //Memory Address Map.
  29
  30 #define SHARE_MEM_BEGIN                 0x50000000    //Internal Shared Memory.
  31 #define SHARE_MEM_END                   0x50000fff    //The address of the last byte
  32
  33 #define INTER_RAM_BEGIN                 0x00020000    //Internal ram
  34 #define INTER_RAM_END                   0x0002A7FF    //The address of the last byte
  35
  36 #define DSP_MEM_BEGIN                   0x00400000    //DSP memory base address.
  37 #define DSP_MEM_LEN                     0x00400000    //length unit:byte.
  38
  39
  40 //CONTROL REGISTER
  41 #define EXTERNAL_MEM_CTL_BEGIN          0x20000000    //External Memory Control registers.
  42 #define EXTERNAL_MEM_CTL_END            0x200001FC
  43
  44 #define DMA_GEN_CTL_BEGIN               0x20100000    //DMA General Control registers.
  45 #define DMA_GEN_CTL_END                 0x201000C4
  46
  47 #define DMA_CHA_CTL_BEGIN               0x20100400    //DMA Channel Control registers.
  48 #define DMA_CHA_CTL_END                 0x201007FC
  49
  50 #define DCAM_CTL_BEGIN                  0x20200000    //DCAM Control registers.
  51 #define DCAM_CTL_END                    0x202027FF    //the begin address of the last word
  52
  53 #define ROTATION_CTL_BEGIN              0x20800200    //ROTATION Device Space.
  54 #define ROTATION_CTL_END                0x2080022C    //length unit:word.
  55
  56 #define USB_CTL_BEGIN                   0x20300000    //USB Device Space.
  57 #define USB_CTL_END                     0x20300E00    //the begin address of the last word
  58
  59 #define BUS_MON0_CTL_BEGIN              0x20400000    //Bus Monitor 0 Control registers.
  60 #define BUS_MON0_CTL_END                0x20400024    //The address of the last byte
  61
  62 #define BUS_MON1_CTL_BEGIN              0x20401000    //Bus Monitor 1 Control registers.
  63 #define BUS_MON1_CTL_END                0x20401024    //The address of the last byte
  64
  65
  66 #define AHB_GEN_CTL_BEGIN               0x20900200    //Bus Monitor Control registers.
  67 #define AHB_GEN_CTL_END                 0x209002A0
  68
  69 #define CHIP_ID_BEGIN                   0x209003FC    //CHIP ID registers.
  70 #define CHIP_ID_END                     0x209003FC
  71
  72 #define NAND_LCM_CTL_BEGIN              0x60001C00    //NAND Flash and LCM Control Registers
  73 #define NAND_LCM_CTL_END                0x60001D44
  74
  75 #define LCDC_CTL_BEGIN                  0x20700000    //LCDC Control Registers
  76 #define LCDC_CTL_END                    0x2070017C    //length unit:word.
  77
  78 #define DISPC_CTL_BEGIN          0x21000000   //DISPC Registers
  79 #define DISPC_CTL_END              0x21000110 //length unit: word.
  80
  81 #define DSI_CTL_BEGIN  0x60100000   //DSI Registers
  82 #define DSI_CTL_END  0x60100070   //length unit:word
  83
  84 #define LCDC_LCM_CTL_BEGIN              0x20700180    //LCDC/LCM Control Registers
  85 #define LCDC_LCM_CTL_END                0x207001a4    //length unit:word.
  86
  87 #define INT_CTL_BEGIN                   0x40003000    //Interrupt Control Registers
  88 #define INT_CTL_END                     0x40000040    //the begin address of the last word
  89
  90 #define TIMER_CNT_BEGIN                 0x41000000    //tiemr counter Registers
  91 #define TIMER_CNT_END                   0x4100004C    //the begin address of the last word
  92
  93 #define ADI_CTL_BEGAIN                  0x42000000  //adi master control registers
  94 #define ADI_CTL_END                     0x42000034
  95
  96 #define UART0_CTL_BEGIN                 0x43000000    //UART0,SPI0 Control Registers
  97 #define UART0_CTL_END                   0x4300002C    //the begin address of the last word
  98
  99 #define UART1_CTL_BEGIN                 0x44000000    //UART1,SPI1 Control Registers
 100 #define UART1_CTL_END                   0x4400002C    //the begin address of the last word
 101
 102 #define UART2_CTL_BEGIN                 0x4E000000    //UART2,SPI2 Control Registers
 103 #define UART2_CTL_END                   0x4E00002C    //the begin address of the last word
 104
 105 #define SIM0_CTL_BEGIN                  0x85000000    //SIMCARD Control Registers
 106 #define SIM0_CTL_END                    0x85000038    //the begin address of the last word
 107
 108 #define SIM1_CTL_BEGIN                  0x85003000    //SIMCARD Control Registers
 109 #define SIM1_CTL_END                    0x85003038    //the begin address of the last word
 110
 111
 112 #define I2C_CTL_BEGIN                   0x86000000    //I2C Control Registers
 113 #define I2C_CTL_END                     0x86000014    //the begin address of the last word
 114
 115 #define KEYPAD_CTL_BEGIN                0x87000000    //Keypad Control Registers
 116 #define KEYPAD_CTL_END                  0x87000038    //the begin address of the last word
 117
 118 #define SYS_CNT_BEGIN                   0x47003000    //system counter Registers
 119 #define SYS_CNT_END                     0x47003008    //the begin address of the last word
 120
 121 #define PWM_CTL_BEGIN                   0x88000000    //Keypad Control Registers
 122 #define PWM_CTL_END                     0x88000070    //the begin address of the last word
 123
 124 #define RTC_CTL_BEGIN                   0x82000080    //RTC Control Registers
 125 #define RTC_CTL_END                     0x820000BC    //the begin address of the last word
 126
 127 #define WATDOG_CTL_BEGIN                0x82000040    //watchdog Control Registers
 128 #define WATDOG_CTL_END                  0x82000060    //the begin address of the last word
 129
 130 #define GPIO_CTL_BEGIN                  0x8A000000    //GPIO Control Registers              ///digital die
 131 #define GPIO_CTL_END                    0x8A0004A4
 132
 133 #define GLOBAL_CTL_BEGIN                0x4B000000    //GLOBAL Control Registers
 134 #define GLOBAL_CTL_END                  0x4B000080    //the begin address of the last word
 135
 136 #define CHIPPIN_CTL_BEGIN               0x8C000000    //ChipPin Control Registers
 137 #define CHIPPIN_CTL_END                 0x8C0003EC
 138
 139 #define VOICE_BAND_CODEC_BEGIN          0x82000100    //Voice Band Codec register       ///digital die
 140 #define VOICE_BAND_CODEC_END            0x82000154
 141
 142
 143 /*----------Peripheral Address Space------------*/
 144 #define INTC_BASE                       0x40003000
 145 #define TIMER_CTL_BASE                  0x41000000  //Timer0 (RTC)
 146 #define ADI_BASE                        0x42000000  //ADI master
 147 #define WDG_BASE                        0x42000040  //Analog die register
 148 #define RTC_BASE                        0x42000080
 149 #define ANA_DOLPHIN_BASE                0x42000100  //Analog die register
 150 #define ANA_PINMAP_BASE                 0x42000180
 151 #define TPC_BASE                        0x42000280
 152 #define ADC_BASE                        0x42000300
 153 #define ANA_INTC_BASE                   0x42000380
 154 #define ANA_REG_BASE                    0x42000600
 155 #define ANA_GPIO_BASE                   0x42000600
 156 #define ARM_VBC_BASE                    0x42003000
 157 #define ARM_UART0_BASE                  0x43000000
 158 #define ARM_UART1_BASE                  0x44000000
 159 #define ARM_UART2_BASE                  0x4E000000
 160 #define SIM0_BASE                       0x45000000  //SIM0
 161 #define SIM1_BASE                       0x45003000  //SIM1
 162 #define I2C_BASE                        0x46000000
 163 #define KPD_BASE                        0x47000000
 164 #define SYSTIMER_BASE                   0x47003000  //System timer
 165 #define PWM_BASE                        0x48000000
 166 #define EFUSE_BASE                      0x49000000  //efuse
 167 #define GPIO_BASE                       0x4A000000
 168 #define GREG_BASE                       0x4B000000  //Global Registers
 169 #define PIN_CTL_BASE                    0x4C000000
 170 #define ANA_PIN_CTL_BASE                0x42000180
 171 #define EPT_BASE                        0x4D000000
 172 #define PCM_CTL_BASE                    0x4E001000
 173 #define SPI_BASE                        0x4E002000
 174
 175
 176 #define INT_REG_BASE                    INTC_BASE
 177 #define EXT_MEM_CTL_BASE                0x20000000
 178 #define DMA_REG_BASE                    0x20100000
 179 #define DCAM_BASE                       0x20200000
 180 #define USB_REG_BASE                    0x20300000
 181 #define BUS_MONx_CTL_BASE               0x20400000
 182 #define BUS_MON0_CTL_BASE               0x20400000
 183 #define BUS_MON1_CTL_BASE               0x20401000
 184 #define BUS_MON2_CTL_BASE               0x20402000
 185 #define BUS_MON_CTL_BASE                BUS_MON0_CTL_BASE
 186
 187 #define SDIO0_BASE_ADDR                 0x20500000
 188 #define SDIO1_BASE_ADDR                 0x20600000
 189 #define SDIO2_BASE_ADDR                 0x20E00000
 190 #ifdef CONFIG_EMMC_BOOT
 191 #define EMMC_BASE_ADDR                  0x20F00000
 192 #else
 193 #define SDIO1_BASE_ADDR                 0x20500100
 194 #endif
 195 #define ROT_REG_BASE                    0x20800200
 196 #define NAND_CTL_BASE                   0x60001c00
 197 #define NF_LCM_CTL_BEGIN                0x60000000      //NAND Flash and LCM Control Registers
 198
 199
 200
 201 #define GEA_BASE    EPT_BASE
 202 #ifdef   __cplusplus
 203 }
 204 #endif
 205
 206 #endif  //_SC8810_REG_BASE_H_
 207