arch/arm/include/asm/arch-sc9630/sprd_reg_global.h

   1 /******************************************************************************
   2  ** File Name:    sprd_reg_global.h                                        *
   3  ** Author:       Daniel.Ding                                                 *
   4  ** DATE:         11/13/2005                                                  *
   5  ** Copyright:    2005 Spreatrum, Incoporated. All Rights Reserved.           *
   6  ** Description:                                                              *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                                         *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                                 *
  12  ** 11/13/2005    Daniel.Ding     Create.                                     *
  13  ** 05/05/2010    Mingwei.Zhang   Modified for SC8800G                        *
  14  ******************************************************************************/
  15 #ifndef _SPRD_REG_GLOBAL_H_
  16 #define _SPRD_REG_GLOBAL_H_
  17 /*----------------------------------------------------------------------------*
  18  **                         Dependencies                                      *
  19  **-------------------------------------------------------------------------- */
  20 #define APB_EB                   (CTL_BASE_APB+0x00)
  21 #define APB_RST                  (CTL_BASE_APB+0x04)
  22 #define USB_PHY_TUNE             (CTL_BASE_APB+0x08)
  23 #define USB_PHY_TEST             (CTL_BASE_APB+0x0C)
  24 #define USB_PHY_CTRL             (CTL_BASE_APB+0x10)
  25 #define APB_MISC_CTRL            (CTL_BASE_APB+0x14)
  26
  27 #define AONAPB_EB0               (CTL_BASE_AON_APB+0x00)
  28 #define AONAPB_EB1               (CTL_BASE_AON_APB+0x04)
  29 #define AONAPB_RST0              (CTL_BASE_AON_APB+0x08)
  30 #define AONAPB_RST1              (CTL_BASE_AON_APB+0x0C)
  31 #define AONAPB_RTC_EB            (CTL_BASE_AON_APB+0x10)
  32 #define AONAPB_MPLL              (CTL_BASE_AON_APB+0x14)
  33 #define AONAPB_DPLL              (CTL_BASE_AON_APB+0x18)
  34 #define AONAPB_TDPLL             (CTL_BASE_AON_APB+0x1C)
  35 #define AONAPB_CPLL              (CTL_BASE_AON_APB+0x20)
  36 #define AONAPB_WIFIPLL0          (CTL_BASE_AON_APB+0x24)
  37 #define AONAPB_WIFIPLL1          (CTL_BASE_AON_APB+0x28)
  38 #define AONAPB_WPLL0             (CTL_BASE_AON_APB+0x2C)
  39 #define AONAPB_WPLL1             (CTL_BASE_AON_APB+0x30)
  40 #define AONAPB_CGM               (CTL_BASE_AON_APB+0x34)
  41 #define AONAPB_RST_MONITOR       (CTL_BASE_AON_APB+0xAC)
  42 #define AONAPB_BOND0             (CTL_BASE_AON_APB+0xB4)
  43 #define AONAPB_BOND1             (CTL_BASE_AON_APB+0xB8)
  44
  45 #define INTC3_EB                 BIT_22
  46 #define INTC2_EB                 BIT_21
  47 #define INTC1_EB                 BIT_20
  48 #define INTC0_EB                 BIT_19
  49 #define APB_CKG_EB               BIT_18
  50 #define UART4_EB                 BIT_17
  51 #define UART3_EB                 BIT_16
  52 #define UART2_EB                 BIT_15
  53 #define UART1_EB                 BIT_14
  54 #define UART0_EB                 BIT_13
  55 #define I2C4_EB                  BIT_12
  56 #define I2C3_EB                  BIT_11
  57 #define I2C2_EB                  BIT_10
  58 #define I2C1_EB                  BIT_9
  59 #define I2C0_EB                  BIT_8
  60 #define SPI2_EB                  BIT_7
  61 #define SPI1_EB                  BIT_6
  62 #define SPI0_EB                  BIT_5
  63 #define IIS3_EB                  BIT_4
  64 #define IIS2_EB                  BIT_3
  65 #define IIS1_EB                  BIT_2
  66 #define IIS0_EB                  BIT_1
  67 #define SIM0_EB                  BIT_0
  68
  69 #define INTC3_RST                 BIT_22
  70 #define INTC2_RST                 BIT_21
  71 #define INTC1_RST                 BIT_20
  72 #define INTC0_RST                 BIT_19
  73 #define APB_CKG_RST               BIT_18
  74 #define UART4_RST                 BIT_17
  75 #define UART3_RST                 BIT_16
  76 #define UART2_RST                 BIT_15
  77 #define UART1_RST                 BIT_14
  78 #define UART0_RST                 BIT_13
  79 #define I2C4_RST                  BIT_12
  80 #define I2C3_RST                  BIT_11
  81 #define I2C2_RST                  BIT_10
  82 #define I2C1_RST                  BIT_9
  83 #define I2C0_RST                  BIT_8
  84 #define SPI2_RST                  BIT_7
  85 #define SPI1_RST                  BIT_6
  86 #define SPI0_RST                  BIT_5
  87 #define IIS3_RST                  BIT_4
  88 #define IIS2_RST                  BIT_3
  89 #define IIS1_RST                  BIT_2
  90 #define IIS0_RST                  BIT_1
  91 #define SIM0_RST                  BIT_0
  92
  93 /**---------------------------------------------------------------------------*
  94  **                             Compiler Flag                                 *
  95  **---------------------------------------------------------------------------*/
  96 #ifdef   __cplusplus
  97 extern   "C"
  98 {
  99 #endif
 100 /**----------------------------------------------------------------------------*
 101 **                               Micro Define                                 **
 102 **----------------------------------------------------------------------------*/
 103
 104 #ifdef   __cplusplus
 105 }
 106 #endif
 107 /**---------------------------------------------------------------------------*/
 108 #endif //_SPRD_REG_GLOBAL_H_
 109 // End
 110
 111