1ff93a318855b4031613cdb4497853437a9f199d
[profile/mobile/platform/kernel/u-boot-tm1.git] / arch / arm / include / asm / arch-sc9630 / regs_ahb.h
1 /*
2  * arch/arm/mach-sc8800s/include/mach/regs_ahb.h
3  *
4  * Chip AHB  registers Definitions
5  *
6  * Copyright (C) 2010 Spreadtrum International Ltd.
7  *
8  * 2010-05-25: yingchun li <yingchun.li@spreadtrum.com>
9  *            initial version
10  *
11  *  This program is free software; you can redistribute it and/or modify
12  *  it under the terms of the GNU General Public License version 2 as
13  *  published by the Free Software Foundation.
14  */
15
16 #ifndef _SC8800H_REG_AHB_H_
17 #define _SC8800H_REG_AHB_H_
18
19 #include <asm/arch/bits.h>
20 #include <asm/arch/sprd_reg_base.h>
21
22 #define AHB_REG_BASE             CTL_BASE_AHB
23 #define CHIP_TYPE                    0x209003FC
24
25 #define AHB_CTL0                (AHB_REG_BASE + 0x00)
26 #define AHB_SOFT_RST            (AHB_REG_BASE + 0x04)
27 #define AHB_PAUSE               (AHB_REG_BASE + 0x14)
28 #define AHB_REMAP               (AHB_REG_BASE + 0x18)
29 #define AHB_ARM_CLK             (AHB_REG_BASE + 0x24)
30 #define AHB_SDIO_CTL            (AHB_REG_BASE + 0x28)
31 #define AHB_CTL4                (AHB_REG_BASE + 0x2C)
32 #define AHB_ENDIAN_SEL          (AHB_REG_BASE + 0x30)
33 #define AHB_STS                 (AHB_REG_BASE + 0x34)
34 #define DSP_BOOT_EN             (AHB_REG_BASE + 0x84)
35 #define DSP_BOOT_VEC            (AHB_REG_BASE + 0x88)
36 #define DSP_RST                 (AHB_REG_BASE + 0x8C)
37 #define AHB_ENDIAN_EN           (AHB_REG_BASE + 0x90)
38 #define USB_PHY_CTRL            (AHB_REG_BASE + 0xA0)
39 #define USB_SPR_REG             (AHB_REG_BASE + 0xC0)
40
41 #define CHIP_ID                 (AHB_REG_BASE + 0x1FC)
42
43 #define AHB_DSP_BOOT_EN             (AHB_REG_BASE + 0x84)
44 #define AHB_DSP_BOOT_VECTOR         (AHB_REG_BASE + 0x88)
45 #define AHB_DSP_RESET               (AHB_REG_BASE + 0x8C)
46 #define AHB_BIGEND_PROT_REG    (AHB_REG_BASE + 0x90)
47
48 #define AHB_CTL0_DCAM_EN   BIT_1
49 #define AHB_CTL0_CCIR_EN    BIT_2
50 #define AHB_CTL0_LCDC_EN    BIT_3
51 #define AHB_CTL0_SDIO_EN    BIT_4
52 #define AHB_CTL0_USBD_EN    BIT_5
53 #define AHB_CTL0_DMA_EN     BIT_6
54 #define AHB_CTL0_BM0_EN     (BIT_7)
55 #define AHB_CTL0_NFC_EN      BIT_8
56 #define AHB_CTL0_BM1_EN     (BIT_11)
57 #define AHB_CTL0_VSP_EN      BIT_13
58 #define AHB_CTL0_ROT_EN      BIT_14
59 #define AHB_CTL0_DRM_EN     BIT_18
60 #define AHB_CTL0_AHB_ARCH_EB   BIT_15
61 #define AHB_CTL0_EMC_EN   BIT_28
62
63 #define AHB_BIGENDIAN_DMA           BIT_0
64 #define AHB_BIGENDIAN_NFC                                               BIT_1
65 #define AHB_BIGENDIAN_LCDC                                      BIT_2
66 #define AHB_BIGENDIAN_SDIO                                      BIT_3
67 #define AHB_BIGENDIAN_DCAM                                      BIT_4
68 #define AHB_BIGENDIAN_VSP                                               BIT_5
69 #define AHB_BIGENDIAN_ROT                                               BIT_6
70 #define AHB_BIGENDIAN_BM0                                               BIT_7
71 #define AHB_BIGENDIAN_BM1                                               BIT_8
72 #define AHB_BIGENDIAN_SHARM                                     BIT_9
73
74 #define AHB_ENDIAN_OPEN             0xC3D4
75 // Bit define AHB_CTRL1
76 #define AHB_CTRL1_EMC_AUTO_GATE_EN BIT_8
77 #define AHB_CTRL1_EMC_CH_AUTO_GATE_EN  BIT_9
78 #define AHB_CTRL1_ARM_AUTO_GATE_EN  BIT_11
79 #define AHB_CTRL1_AHB_AUTO_GATE_EN  BIT_12
80 #define AHB_CTRL1_MCU_AUTO_GATE_EN  BIT_13
81 #define AHB_CTRL1_MSTMTX_AUTO_GATE_EN  BIT_14
82 #define AHB_CTRL1_ARMMTX_AUTO_GATE_EN  BIT_15
83 #define AHB_CTRL1_ARM_DAHB_SLEEP_EN  BIT_16
84
85 ///USB_PHY_CTRL
86 #define USB_DM_PULLUP_BIT       BIT_19
87 #define USB_DP_PULLDOWN_BIT     BIT_20
88 #define USB_DM_PULLDOWN_BIT     BIT_21
89
90
91
92 #endif 
93