2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
21 #ifndef CONFIG_NKERNEL
22 #define debug(format, arg...) printf("clk: " "@@@%s: " format, __func__, ## arg)
23 #define debug0(format, arg...)
31 struct list_head node;
47 int (*notifier_call)(struct notifier_block, unsigned long, void*);
48 struct notifier_block *next;
52 #define debug(format, arg...) pr_debug("clk: " "@@@%s: " format, __func__, ## arg)
53 #define debug0(format, arg...)
56 * struct clk_sel - list of sources for a given clock (pll)
57 * @sources: array of pointers to clocks
58 * @nr_sources: The size of @sources
66 * struct clk_reg - register definition for clock control bits
67 * @reg: pointer to the register in virtual memory.
68 * @shift: the shift in bits to where the bitfield is.
69 * @size: the size in bits of the bitfield.
70 * @mask: the mask of the bitfield.
72 * This specifies the size and position of the bits we are interested
73 * in within the register specified by @reg.
77 //unsigned short shift, size;
84 struct clk_reg enb, div, sel;
88 struct clk *sources[10];
92 * struct clk_ops - standard clock operations
93 * @set_rate: set the clock rate, see clk_set_rate().
94 * @get_rate: get the clock rate, see clk_get_rate().
95 * @round_rate: round a given clock rate, see clk_round_rate().
96 * @set_parent: set the clock's parent, see clk_set_parent().
98 * Group the common clock implementations together so that we
99 * don't have to keep setting the same fields again. We leave
100 * enable in struct clk.
102 * Adding an extra layer of indirection into the process should
103 * not be a problem as it is unlikely these operations are going
104 * to need to be called quickly.
107 int (*set_rate) (struct clk * c, unsigned long rate);
108 unsigned long (*get_rate) (struct clk * c);
109 unsigned long (*round_rate) (struct clk * c, unsigned long rate);
110 int (*set_parent) (struct clk * c, struct clk * parent);
114 * struct clk - class of clock for newer style spreadtrum devices.
115 * @clk: the standard clock representation
116 * @sel: the parent sources select for this clock
117 * @reg_sel: the register definition for selecting the pll clock's source
118 * @reg_div: the register definition for the clock's output divisor
119 * @reg_enb: the register definition for enable or disable the clock's source
121 * This clock implements the features required by the newer SoCs where
122 * the standard clock block provides an input mux and a post-mux divisor
123 * to provide the periperhal's clock.
125 * The array of @sel provides the mapping of mux position to the
126 * clock, and @reg_sel shows the code where to modify to change the mux
127 * position. The @reg_div defines how to change the divider settings on
132 struct module *owner;
137 int (*enable) (struct clk *, int enable, unsigned long *);
139 const struct clk_regs *regs;
140 #if defined(CONFIG_DEBUG_FS)
141 struct dentry *dent; /* For visible tree hierarchy */
145 #define MAX_DIV (1000)
147 #define SCI_CLK_ADD(ID, RATE, ENB, ENB_BIT, DIV, DIV_MSK, SEL, SEL_MSK, NR_CLKS, ...) \
148 static const struct clk_regs REGS_##ID = { \
152 .reg = (u32)ENB,.mask = ENB_BIT, \
155 .reg = (u32)DIV,.mask = DIV_MSK, \
158 .reg = (u32)SEL,.mask = SEL_MSK, \
160 .nr_sources = NR_CLKS, \
161 .sources = {__VA_ARGS__}, \
163 static struct clk ID = { \
164 .owner = THIS_MODULE, \
168 .regs = ®S_##ID, \
172 const struct clk_lookup __clkinit1 CLK_LK_##ID = { \
178 int __init sci_clk_register(struct clk_lookup *cl);
180 #define __clkinit0 __section(.rodata.clkinit0)
181 #define __clkinit1 __section(.rodata.clkinit1)
182 #define __clkinit2 __section(.rodata.clkinit2)