2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
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4 * This file is dual-licensed: you can use it either under the terms
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5 * of the GPL or the X11 license, at your option. Note that this dual
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6 * licensing only applies to this file, and not this project as a
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11 #ifndef __H_REGS_AP_AHB_RF_HEADFILE_H__
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12 #define __H_REGS_AP_AHB_RF_HEADFILE_H__ __FILE__
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14 #define REGS_AP_AHB_RF
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16 /* registers definitions for controller REGS_AP_AHB */
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17 #define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)
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18 #define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)
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19 #define REG_AP_AHB_CA7_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)
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20 #define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)
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21 #define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)
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22 #define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)
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23 #define REG_AP_AHB_JMP_ADDR_CA7_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)
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24 #define REG_AP_AHB_JMP_ADDR_CA7_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)
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25 #define REG_AP_AHB_JMP_ADDR_CA7_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)
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26 #define REG_AP_AHB_JMP_ADDR_CA7_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)
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27 #define REG_AP_AHB_CA7_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)
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28 #define REG_AP_AHB_CA7_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)
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29 #define REG_AP_AHB_CA7_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)
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30 #define REG_AP_AHB_CA7_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)
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31 #define REG_AP_AHB_CA7_CKG_DIV_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0038)
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32 #define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x003C)
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33 #define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0040)
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34 #define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0044)
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35 #define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0048)
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36 #define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x004C)
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37 #define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0050)
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38 #define REG_AP_AHB_CA7_CKG_SEL_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0054)
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39 #define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)
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40 #define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)
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41 #define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)
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42 #define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)
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43 #define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)
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44 #define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)
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45 #define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)
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46 #define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)
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47 #define REG_AP_AHB_OTG_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)
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48 #define REG_AP_AHB_OTG_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)
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49 #define REG_AP_AHB_OTG_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)
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50 #define REG_AP_AHB_HSIC_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)
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51 #define REG_AP_AHB_HSIC_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)
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52 #define REG_AP_AHB_HSIC_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)
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53 #define REG_AP_AHB_ZIP_MTX_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)
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54 #define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)
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56 /* bits definitions for register REG_AP_AHB_AHB_EB */
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57 #define BIT_ZIPMTX_EB ( BIT(23) )
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58 #define BIT_LVDS_EB ( BIT(22) )
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59 #define BIT_ZIPDEC_EB ( BIT(21) )
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60 #define BIT_ZIPENC_EB ( BIT(20) )
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61 #define BIT_NANDC_ECC_EB ( BIT(19) )
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62 #define BIT_NANDC_2X_EB ( BIT(18) )
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63 #define BIT_NANDC_EB ( BIT(17) )
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64 #define BIT_BUSMON2_EB ( BIT(16) )
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65 #define BIT_BUSMON1_EB ( BIT(15) )
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66 #define BIT_BUSMON0_EB ( BIT(14) )
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67 #define BIT_SPINLOCK_EB ( BIT(13) )
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68 #define BIT_EMMC_EB ( BIT(11) )
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69 #define BIT_SDIO2_EB ( BIT(10) )
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70 #define BIT_SDIO1_EB ( BIT(9) )
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71 #define BIT_SDIO0_EB ( BIT(8) )
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72 #define BIT_DRM_EB ( BIT(7) )
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73 #define BIT_NFC_EB ( BIT(6) )
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74 #define BIT_DMA_EB ( BIT(5) )
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75 #define BIT_OTG_EB ( BIT(4) )
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76 #define BIT_GSP_EB ( BIT(3) )
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77 #define BIT_HSIC_EB ( BIT(2) )
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78 #define BIT_DISPC_EB ( BIT(1) )
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79 #define BIT_DSI_EB ( BIT(0) )
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81 /* bits definitions for register REG_AP_AHB_AHB_RST */
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82 #define BIT_HSIC_PHY_SOFT_RST ( BIT(30) )
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83 #define BIT_HSIC_UTMI_SOFT_RST ( BIT(29) )
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84 #define BIT_HSIC_SOFT_RST ( BIT(28) )
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85 #define BIT_LVDS_SOFT_RST ( BIT(25) )
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86 #define BIT_ZIP_MTX_SOFT_RST ( BIT(24) )
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87 #define BIT_ZIPDEC_SOFT_RST ( BIT(23) )
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88 #define BIT_ZIPENC_SOFT_RST ( BIT(22) )
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89 #define BIT_NANDC_SOFT_RST ( BIT(20) )
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90 #define BIT_BUSMON2_SOFT_RST ( BIT(19) )
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91 #define BIT_BUSMON1_SOFT_RST ( BIT(18) )
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92 #define BIT_BUSMON0_SOFT_RST ( BIT(17) )
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93 #define BIT_SPINLOCK_SOFT_RST ( BIT(16) )
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94 #define BIT_EMMC_SOFT_RST ( BIT(14) )
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95 #define BIT_SDIO2_SOFT_RST ( BIT(13) )
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96 #define BIT_SDIO1_SOFT_RST ( BIT(12) )
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97 #define BIT_SDIO0_SOFT_RST ( BIT(11) )
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98 #define BIT_DRM_SOFT_RST ( BIT(10) )
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99 #define BIT_NFC_SOFT_RST ( BIT(9) )
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100 #define BIT_DMA_SOFT_RST ( BIT(8) )
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101 #define BIT_OTG_PHY_SOFT_RST ( BIT(6) )
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102 #define BIT_OTG_UTMI_SOFT_RST ( BIT(5) )
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103 #define BIT_OTG_SOFT_RST ( BIT(4) )
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104 #define BIT_GSP_SOFT_RST ( BIT(3) )
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105 #define BIT_DISP_MTX_SOFT_RST ( BIT(2) )
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106 #define BIT_DISPC_SOFT_RST ( BIT(1) )
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107 #define BIT_DSI_SOFT_RST ( BIT(0) )
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109 /* bits definitions for register REG_AP_AHB_CA7_RST_SET */
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110 #define BIT_CA7_CS_DBG_SOFT_RST ( BIT(14) )
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111 #define BIT_CA7_L2_SOFT_RST ( BIT(13) )
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112 #define BIT_CA7_SOCDBG_SOFT_RST ( BIT(12) )
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113 #define BITS_CA7_ETM_SOFT_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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114 #define BITS_CA7_DBG_SOFT_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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115 #define BITS_CA7_CORE_SOFT_RST(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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117 /* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */
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118 #define BIT_CA7_C3_AUTO_SLP_EN ( BIT(15) )
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119 #define BIT_CA7_C2_AUTO_SLP_EN ( BIT(14) )
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120 #define BIT_CA7_C1_AUTO_SLP_EN ( BIT(13) )
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121 #define BIT_CA7_C0_AUTO_SLP_EN ( BIT(12) )
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122 #define BIT_CA7_C3_WFI_SHUTDOWN_EN ( BIT(11) )
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123 #define BIT_CA7_C2_WFI_SHUTDOWN_EN ( BIT(10) )
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124 #define BIT_CA7_C1_WFI_SHUTDOWN_EN ( BIT(9) )
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125 #define BIT_CA7_C0_WFI_SHUTDOWN_EN ( BIT(8) )
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126 #define BIT_MCU_CA7_C3_SLEEP ( BIT(7) )
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127 #define BIT_MCU_CA7_C2_SLEEP ( BIT(6) )
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128 #define BIT_MCU_CA7_C1_SLEEP ( BIT(5) )
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129 #define BIT_MCU_CA7_C0_SLEEP ( BIT(4) )
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130 #define BIT_AP_PERI_FORCE_ON ( BIT(2) )
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131 #define BIT_AP_PERI_FORCE_SLP ( BIT(1) )
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132 #define BIT_AP_APB_SLEEP ( BIT(0) )
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134 /* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */
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135 #define BIT_GSP_CKG_FORCE_EN ( BIT(9) )
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136 #define BIT_GSP_AUTO_GATE_EN ( BIT(8) )
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137 #define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) )
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138 #define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) )
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139 #define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(3) )
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140 #define BIT_CA7_DBG_FORCE_SLEEP ( BIT(2) )
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141 #define BIT_CA7_DBG_AUTO_GATE_EN ( BIT(1) )
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142 #define BIT_CA7_CORE_AUTO_GATE_EN ( BIT(0) )
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144 /* bits definitions for register REG_AP_AHB_HOLDING_PEN */
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145 #define BITS_HOLDING_PEN(_x_) ( (_x_) << 0 )
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147 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */
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148 #define BITS_JMP_ADDR_CA7_C0(_x_) ( (_x_) << 0 )
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150 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */
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151 #define BITS_JMP_ADDR_CA7_C1(_x_) ( (_x_) << 0 )
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153 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */
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154 #define BITS_JMP_ADDR_CA7_C2(_x_) ( (_x_) << 0 )
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156 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */
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157 #define BITS_JMP_ADDR_CA7_C3(_x_) ( (_x_) << 0 )
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159 /* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */
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160 #define BIT_CA7_C0_PU_LOCK ( BIT(0) )
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162 /* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */
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163 #define BIT_CA7_C1_PU_LOCK ( BIT(0) )
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165 /* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */
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166 #define BIT_CA7_C2_PU_LOCK ( BIT(0) )
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168 /* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */
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169 #define BIT_CA7_C3_PU_LOCK ( BIT(0) )
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171 /* bits definitions for register REG_AP_AHB_CA7_CKG_DIV_CFG */
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172 #define BITS_CA7_DBG_CKG_DIV(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)) )
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173 #define BITS_CA7_AXI_CKG_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
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174 #define BITS_CA7_MCU_CKG_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
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176 /* bits definitions for register REG_AP_AHB_MCU_PAUSE */
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177 #define BIT_DMA_ACT_LIGHT_EN ( BIT(5) )
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178 #define BIT_MCU_SLEEP_FOLLOW_CA7_EN ( BIT(4) )
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179 #define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) )
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180 #define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) )
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181 #define BIT_MCU_SYS_SLEEP_EN ( BIT(1) )
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182 #define BIT_MCU_CORE_SLEEP ( BIT(0) )
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184 /* bits definitions for register REG_AP_AHB_MISC_CKG_EN */
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185 #define BIT_ASHB_CA7_DBG_VLD ( BIT(9) )
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186 #define BIT_ASHB_CA7_DBG_EN ( BIT(8) )
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187 #define BIT_DISP_TMC_CKG_EN ( BIT(4) )
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188 #define BIT_DPHY_REF_CKG_EN ( BIT(1) )
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189 #define BIT_DPHY_CFG_CKG_EN ( BIT(0) )
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191 /* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */
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192 #define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
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194 /* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */
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195 #define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
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197 /* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */
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198 #define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
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200 /* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */
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201 #define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
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203 /* bits definitions for register REG_AP_AHB_CA7_CKG_SEL_CFG */
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204 #define BITS_CA7_MCU_CKG_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
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206 /* bits definitions for register REG_AP_AHB_MISC_CFG */
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207 #define BITS_EMMC_SLOT_SEL(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) )
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208 #define BITS_SDIO0_SLOT_SEL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
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209 #define BITS_BUSMON2_CHN_SEL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
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210 #define BITS_BUSMON1_CHN_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
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211 #define BITS_BUSMON0_CHN_SEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
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212 #define BITS_SDIO2_SLOT_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
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213 #define BITS_SDIO1_SLOT_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
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215 /* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */
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216 #define BITS_HPROT_NFC(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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217 #define BITS_HPROT_EMMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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218 #define BITS_HPROT_SDIO2(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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219 #define BITS_HPROT_SDIO1(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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220 #define BITS_HPROT_SDIO0(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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221 #define BITS_HPROT_DMAW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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222 #define BITS_HPROT_DMAR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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224 /* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */
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225 #define BIT_CA7_STANDBYWFIL2 ( BIT(12) )
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226 #define BITS_CA7_ETMSTANDBYWFX(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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227 #define BITS_CA7_STANDBYWFE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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228 #define BITS_CA7_STANDBYWFI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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230 /* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */
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231 #define BITS_CLK_NANDC2X_DIV(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
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232 #define BITS_CLK_NANDC2X_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
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234 /* bits definitions for register REG_AP_AHB_LVDS_CFG */
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235 #define BITS_LVDS_TXCLKDATA(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
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236 #define BITS_LVDS_TXCOM(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
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237 #define BITS_LVDS_TXSLEW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
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238 #define BITS_LVDS_TXSW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
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239 #define BITS_LVDS_TXRERSER(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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240 #define BITS_LVDS_PRE_EMP(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) )
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241 #define BIT_LVDS_TXPD ( BIT(0) )
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243 /* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */
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244 #define BIT_LVDS_PLL_LOCK_DET ( BIT(31) )
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245 #define BITS_LVDS_PLL_REFIN(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)) )
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246 #define BITS_LVDS_PLL_LPF(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
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247 #define BIT_LVDS_PLL_DIV_S ( BIT(18) )
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248 #define BITS_LVDS_PLL_IBIAS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
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249 #define BITS_LVDS_PLLN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
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251 /* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */
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252 #define BITS_LVDS_PLL_KINT(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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253 #define BITS_LVDS_PLL_RSV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
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254 #define BIT_LVDS_PLL_MOD_EN ( BIT(7) )
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255 #define BIT_LVDS_PLL_SDM_EN ( BIT(6) )
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256 #define BITS_LVDS_PLL_NINT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
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258 /* bits definitions for register REG_AP_AHB_AP_QOS_CFG */
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259 #define BITS_QOS_R_TMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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260 #define BITS_QOS_W_TMC(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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261 #define BITS_QOS_R_DISPC(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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262 #define BITS_QOS_W_DISPC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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264 /* bits definitions for register REG_AP_AHB_OTG_PHY_TUNE */
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265 #define BIT_OTG_TXPREEMPPULSETUNE ( BIT(20) )
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266 #define BITS_OTG_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) )
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267 #define BITS_OTG_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
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268 #define BITS_OTG_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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269 #define BITS_OTG_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
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270 #define BITS_OTG_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
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271 #define BITS_OTG_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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272 #define BITS_OTG_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
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274 /* bits definitions for register REG_AP_AHB_OTG_PHY_TEST */
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275 #define BIT_OTG_ATERESET ( BIT(31) )
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276 #define BIT_OTG_VBUS_VALID_EXT_SEL ( BIT(26) )
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277 #define BIT_OTG_VBUS_VALID_EXT ( BIT(25) )
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278 #define BIT_OTG_OTGDISABLE ( BIT(24) )
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279 #define BIT_OTG_TESTBURNIN ( BIT(21) )
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280 #define BIT_OTG_LOOPBACKENB ( BIT(20) )
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281 #define BITS_OTG_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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282 #define BITS_OTG_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
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283 #define BIT_OTG_TESTCLK ( BIT(13) )
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284 #define BIT_OTG_TESTDATAOUTSEL ( BIT(12) )
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285 #define BITS_OTG_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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286 #define BITS_OTG_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
288 /* bits definitions for register REG_AP_AHB_OTG_PHY_CTRL */
\r
289 #define BITS_OTG_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) )
\r
290 #define BIT_OTG_TXBITSTUFFENH ( BIT(23) )
\r
291 #define BIT_OTG_TXBITSTUFFEN ( BIT(22) )
\r
292 #define BIT_OTG_DMPULLDOWN ( BIT(21) )
\r
293 #define BIT_OTG_DPPULLDOWN ( BIT(20) )
\r
294 #define BIT_OTG_DMPULLUP ( BIT(9) )
\r
295 #define BIT_OTG_COMMONONN ( BIT(8) )
\r
296 #define BITS_OTG_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
\r
297 #define BITS_OTG_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
\r
299 /* bits definitions for register REG_AP_AHB_HSIC_PHY_TUNE */
\r
300 #define BITS_HSIC_REFCLK_DIV(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
\r
301 #define BIT_HSIC_TXPREEMPPULSETUNE ( BIT(20) )
\r
302 #define BITS_HSIC_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) )
\r
303 #define BITS_HSIC_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
\r
304 #define BITS_HSIC_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
305 #define BITS_HSIC_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
\r
306 #define BITS_HSIC_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
\r
307 #define BITS_HSIC_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
308 #define BITS_HSIC_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
\r
310 /* bits definitions for register REG_AP_AHB_HSIC_PHY_TEST */
\r
311 #define BIT_HSIC_ATERESET ( BIT(31) )
\r
312 #define BIT_HSIC_VBUS_VALID_EXT_SEL ( BIT(26) )
\r
313 #define BIT_HSIC_VBUS_VALID_EXT ( BIT(25) )
\r
314 #define BIT_HSIC_OTGDISABLE ( BIT(24) )
\r
315 #define BIT_HSIC_TESTBURNIN ( BIT(21) )
\r
316 #define BIT_HSIC_LOOPBACKENB ( BIT(20) )
\r
317 #define BITS_HSIC_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
318 #define BITS_HSIC_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
\r
319 #define BIT_HSIC_TESTCLK ( BIT(13) )
\r
320 #define BIT_HSIC_TESTDATAOUTSEL ( BIT(12) )
\r
321 #define BITS_HSIC_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
322 #define BITS_HSIC_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
324 /* bits definitions for register REG_AP_AHB_HSIC_PHY_CTRL */
\r
325 #define BITS_HSIC_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) )
\r
326 #define BIT_HSIC_TXBITSTUFFENH ( BIT(23) )
\r
327 #define BIT_HSIC_TXBITSTUFFEN ( BIT(22) )
\r
328 #define BIT_HSIC_DMPULLDOWN ( BIT(21) )
\r
329 #define BIT_HSIC_DPPULLDOWN ( BIT(20) )
\r
330 #define BIT_HSIC_IF_MODE ( BIT(16) )
\r
331 #define BIT_IF_SELECT_HSIC ( BIT(13) )
\r
332 #define BIT_HSIC_DBNCE_FLTR_BYPASS ( BIT(12) )
\r
333 #define BIT_HSIC_DMPULLUP ( BIT(9) )
\r
334 #define BIT_HSIC_COMMONONN ( BIT(8) )
\r
335 #define BITS_HSIC_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
\r
336 #define BITS_HSIC_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
\r
338 /* bits definitions for register REG_AP_AHB_ZIP_MTX_QOS_CFG */
\r
339 #define BITS_ZIPMTX_S0_ARQOS(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
340 #define BITS_ZIPMTX_S0_AWQOS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
341 #define BITS_ZIPDEC_ARQOS(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
342 #define BITS_ZIPDEC_AWQOS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
343 #define BITS_ZIPENC_ARQOS(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
344 #define BITS_ZIPENC_AWQOS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
346 /* bits definitions for register REG_AP_AHB_CHIP_ID */
\r
347 #define BITS_CHIP_ID(_x_) ( (_x_) << 0 )
\r
349 /* vars definitions for controller REGS_AP_AHB */
\r
351 #endif /* __REGS_AP_AHB_H__ */
\r