2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
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4 * This file is dual-licensed: you can use it either under the terms
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5 * of the GPL or the X11 license, at your option. Note that this dual
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6 * licensing only applies to this file, and not this project as a
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11 #ifndef __H_REGS_AON_APB_RF_HEADFILE_H__
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12 #define __H_REGS_AON_APB_RF_HEADFILE_H__ __FILE__
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14 #define REGS_AON_APB_RF
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16 /* registers definitions for AON_APB_RF */
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17 #define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)
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18 #define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)
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19 #define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)
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20 #define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)
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21 #define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)
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22 #define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)
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23 #define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)
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24 #define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)
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25 #define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)
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26 #define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)
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27 #define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)
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28 #define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)
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29 #define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)
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30 #define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)
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31 #define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)
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32 #define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)
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33 #define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)
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34 #define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044)
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35 #define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048)
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36 #define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C)
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37 #define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050)
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38 #define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054)
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39 #define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058)
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40 #define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C)
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41 #define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060)
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42 #define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064)
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43 #define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068)
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44 #define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*Big endian protect register*/
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45 #define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*DSP boot enable*/
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46 #define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*DSP boot vector*/
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47 #define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*DSP reset*/
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48 #define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C)
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49 #define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080)
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50 #define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084)
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51 #define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088)
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52 #define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C)
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53 #define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090)
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54 #define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094)
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55 #define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*DSP reset*/
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56 #define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*APB clock control*/
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57 #define REG_AON_APB_AON_CHIP_ID_H SCI_ADDR(REGS_AON_APB_BASE, 0x00F8)/*CHIP_ID_H*/
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58 #define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*CHIP_ID_L*/
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59 #define REG_AON_APB_AON_CHIP_ID_L REG_AON_APB_AON_CHIP_ID
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60 #define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*APB clock control*/
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61 #define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108)
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62 #define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C)
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63 #define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110)
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64 #define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114)
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65 #define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118)
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66 #define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C)
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67 #define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120)
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68 #define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124)
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69 #define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128)
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70 #define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C)
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71 #define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130)
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72 #define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004)
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73 #define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008)
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74 #define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C)
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75 #define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014)
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76 #define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)
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77 #define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020)
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78 #define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)
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79 #define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C)
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80 #define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030)
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81 #define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034)
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82 #define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038)
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83 #define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C)
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84 #define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040)
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85 #define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044)
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86 #define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048)
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87 #define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C)
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88 #define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050)
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89 #define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058)
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90 #define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060)
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91 #define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064)
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92 #define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068)
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93 #define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0)
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97 /* bits definitions for register REG_AON_APB_RF_APB_EB0 */
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98 #define BIT_I2C_EB ( BIT(31) )
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99 #define BIT_CA7_DAP_EB ( BIT(30) )
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100 #define BIT_CA7_TS1_EB ( BIT(29) )
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101 #define BIT_CA7_TS0_EB ( BIT(28) )
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102 #define BIT_GPU_EB ( BIT(27) )
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103 #define BIT_CKG_EB ( BIT(26) )
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104 #define BIT_MM_EB ( BIT(25) )
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105 #define BIT_AP_WDG_EB ( BIT(24) )
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106 #define BIT_MSPI_EB ( BIT(23) )
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107 #define BIT_SPLK_EB ( BIT(22) )
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108 #define BIT_IPI_EB ( BIT(21) )
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109 #define BIT_PIN_EB ( BIT(20) )
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110 #define BIT_VBC_EB ( BIT(19) )
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111 #define BIT_AUD_EB ( BIT(18) )
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112 #define BIT_AUDIF_EB ( BIT(17) )
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113 #define BIT_ADI_EB ( BIT(16) )
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114 #define BIT_INTC_EB ( BIT(15) )
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115 #define BIT_EIC_EB ( BIT(14) )
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116 #define BIT_EFUSE_EB ( BIT(13) )
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117 #define BIT_AP_TMR0_EB ( BIT(12) )
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118 #define BIT_AON_TMR_EB ( BIT(11) )
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119 #define BIT_AP_SYST_EB ( BIT(10) )
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120 #define BIT_AON_SYST_EB ( BIT(9) )
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121 #define BIT_KPD_EB ( BIT(8) )
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122 #define BIT_PWM3_EB ( BIT(7) )
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123 #define BIT_PWM2_EB ( BIT(6) )
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124 #define BIT_PWM1_EB ( BIT(5) )
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125 #define BIT_PWM0_EB ( BIT(4) )
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126 #define BIT_GPIO_EB ( BIT(3) )
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127 #define BIT_AON_GPIO_EB (BIT_GPIO_EB)
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128 #define BIT_TPC_EB ( BIT(2) )
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129 #define BIT_FM_EB ( BIT(1) )
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130 #define BIT_ADC_EB ( BIT(0) )
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132 /* bits definitions for register REG_AON_APB_APB_EB1 */
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133 #define BIT_ORP_JTAG_EB ( BIT(27) )
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134 #define BIT_CA5_TS0_EB ( BIT(26) )
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135 #define BIT_DEF_EB ( BIT(25) )
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136 #define BIT_LVDS_PLL_DIV_EN ( BIT(24) )
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137 #define BIT_ARM7_JTAG_EB ( BIT(23) )
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138 #define BIT_AON_DMA_EB ( BIT(22) )
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139 #define BIT_MBOX_EB ( BIT(21) )
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140 #define BIT_DJTAG_EB ( BIT(20) )
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141 #define BIT_RTC4M1_CAL_EB ( BIT(19) )
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142 #define BIT_RTC4M0_CAL_EB ( BIT(18) )
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143 #define BIT_MDAR_EB ( BIT(17) )
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144 #define BIT_LVDS_TCXO_EB ( BIT(16) )
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145 #define BIT_LVDS_TRX_EB ( BIT(15) )
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146 #define BIT_CA5_DAP_EB ( BIT(14) )
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147 #define BIT_GSP_EMC_EB ( BIT(13) )
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148 #define BIT_ZIP_EMC_EB ( BIT(12) )
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149 #define BIT_DISP_EMC_EB ( BIT(11) )
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150 #define BIT_AP_TMR2_EB ( BIT(10) )
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151 #define BIT_AP_TMR1_EB ( BIT(9) )
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152 #define BIT_CA7_WDG_EB ( BIT(8) )
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153 #define BIT_AVS_EB ( BIT(6) )
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154 #define BIT_PROBE_EB ( BIT(5) )
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155 #define BIT_AUX2_EB ( BIT(4) )
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156 #define BIT_AUX1_EB ( BIT(3) )
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157 #define BIT_AUX0_EB ( BIT(2) )
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158 #define BIT_THM_EB ( BIT(1) )
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159 #define BIT_PMU_EB ( BIT(0) )
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161 /* bits definitions for register REG_AON_APB_RF_APB_RST0 */
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162 #define BIT_CA5_TS0_SOFT_RST ( BIT(31) )
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163 #define BIT_I2C_SOFT_RST ( BIT(30) )
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164 #define BIT_CA7_TS1_SOFT_RST ( BIT(29) )
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165 #define BIT_CA7_TS0_SOFT_RST ( BIT(28) )
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166 #define BIT_DAP_MTX_SOFT_RST ( BIT(27) )
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167 #define BIT_MSPI1_SOFT_RST ( BIT(26) )
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168 #define BIT_MSPI0_SOFT_RST ( BIT(25) )
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169 #define BIT_SPLK_SOFT_RST ( BIT(24) )
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170 #define BIT_IPI_SOFT_RST ( BIT(23) )
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171 #define BIT_CKG_SOFT_RST ( BIT(22) )
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172 #define BIT_PIN_SOFT_RST ( BIT(21) )
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173 #define BIT_VBC_SOFT_RST ( BIT(20) )
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174 #define BIT_AUD_SOFT_RST ( BIT(19) )
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175 #define BIT_AUDIF_SOFT_RST ( BIT(18) )
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176 #define BIT_ADI_SOFT_RST ( BIT(17) )
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177 #define BIT_INTC_SOFT_RST ( BIT(16) )
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178 #define BIT_EIC_SOFT_RST ( BIT(15) )
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179 #define BIT_EFUSE_SOFT_RST ( BIT(14) )
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180 #define BIT_AP_WDG_SOFT_RST ( BIT(13) )
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181 #define BIT_AP_TMR0_SOFT_RST ( BIT(12) )
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182 #define BIT_AON_TMR_SOFT_RST ( BIT(11) )
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183 #define BIT_AP_SYST_SOFT_RST ( BIT(10) )
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184 #define BIT_AON_SYST_SOFT_RST ( BIT(9) )
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185 #define BIT_KPD_SOFT_RST ( BIT(8) )
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186 #define BIT_PWM3_SOFT_RST ( BIT(7) )
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187 #define BIT_PWM2_SOFT_RST ( BIT(6) )
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188 #define BIT_PWM1_SOFT_RST ( BIT(5) )
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189 #define BIT_PWM0_SOFT_RST ( BIT(4) )
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190 #define BIT_GPIO_SOFT_RST ( BIT(3) )
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191 #define BIT_TPC_SOFT_RST ( BIT(2) )
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192 #define BIT_FM_SOFT_RST ( BIT(1) )
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193 #define BIT_ADC_SOFT_RST ( BIT(0) )
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195 /* bits definitions for register REG_AON_APB_RF_APB_RST1 */
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196 #define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) )
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197 #define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) )
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198 #define BIT_DEF_SOFT_RST ( BIT(29) )
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199 #define BIT_ADC3_SOFT_RST ( BIT(28) )
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200 #define BIT_ADC2_SOFT_RST ( BIT(27) )
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201 #define BIT_ADC1_SOFT_RST ( BIT(26) )
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202 #define BIT_MBOX_SOFT_RST ( BIT(25) )
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203 #define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) )
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204 #define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) )
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205 #define BIT_LDSP_SYS_SOFT_RST ( BIT(21) )
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206 #define BIT_LCP_SYS_SOFT_RST ( BIT(20) )
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207 #define BIT_DAC3_SOFT_RST ( BIT(19) )
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208 #define BIT_DAC2_SOFT_RST ( BIT(18) )
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209 #define BIT_DAC1_SOFT_RST ( BIT(17) )
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210 #define BIT_ADC3_CAL_SOFT_RST ( BIT(16) )
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211 #define BIT_ADC2_CAL_SOFT_RST ( BIT(15) )
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212 #define BIT_ADC1_CAL_SOFT_RST ( BIT(14) )
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213 #define BIT_MDAR_SOFT_RST ( BIT(13) )
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214 #define BIT_LVDSDIS_SOFT_RST ( BIT(12) )
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215 #define BIT_BB_CAL_SOFT_RST ( BIT(11) )
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216 #define BIT_DCXO_LC_SOFT_RST ( BIT(10) )
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217 #define BIT_AP_TMR2_SOFT_RST ( BIT(9) )
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218 #define BIT_AP_TMR1_SOFT_RST ( BIT(8) )
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219 #define BIT_CA7_WDG_SOFT_RST ( BIT(7) )
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220 #define BIT_AON_DMA_SOFT_RST ( BIT(6) )
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221 #define BIT_AVS_SOFT_RST ( BIT(5) )
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222 #define BIT_DMC_PHY_SOFT_RST ( BIT(4) )
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223 #define BIT_GPU_THMA_SOFT_RST ( BIT(3) )
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224 #define BIT_ARM_THMA_SOFT_RST ( BIT(2) )
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225 #define BIT_THM_SOFT_RST ( BIT(1) )
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226 #define BIT_PMU_SOFT_RST ( BIT(0) )
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228 /* bits definitions for register REG_AON_APB_RF_APB_RTC_EB */
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229 #define BIT_CP0_LTE_EB ( BIT(19) )
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230 #define BIT_BB_CAL_RTC_EB ( BIT(18) )
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231 #define BIT_DCXO_LC_RTC_EB ( BIT(17) )
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232 #define BIT_AP_TMR2_RTC_EB ( BIT(16) )
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233 #define BIT_AP_TMR1_RTC_EB ( BIT(15) )
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234 #define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) )
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235 #define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) )
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236 #define BIT_GPU_THMA_RTC_EB ( BIT(12) )
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237 #define BIT_ARM_THMA_RTC_EB ( BIT(11) )
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238 #define BIT_THM_RTC_EB ( BIT(10) )
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239 #define BIT_CA7_WDG_RTC_EB ( BIT(9) )
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240 #define BIT_AP_WDG_RTC_EB ( BIT(8) )
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241 #define BIT_EIC_RTCDV5_EB ( BIT(7) )
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242 #define BIT_EIC_RTC_EB ( BIT(6) )
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243 #define BIT_AP_TMR0_RTC_EB ( BIT(5) )
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244 #define BIT_AON_TMR_RTC_EB ( BIT(4) )
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245 #define BIT_AP_SYST_RTC_EB ( BIT(3) )
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246 #define BIT_AON_SYST_RTC_EB ( BIT(2) )
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247 #define BIT_KPD_RTC_EB ( BIT(1) )
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248 #define BIT_ARCH_RTC_EB ( BIT(0) )
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250 /* bits definitions for register REG_AON_APB_RF_REC_26MHZ_BUF_CFG */
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251 #define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
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252 #define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) )
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253 #define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) )
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255 /* bits definitions for register REG_AON_APB_RF_SINDRV_CTRL */
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256 #define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
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257 #define BIT_SINDRV_CLIP_MODE ( BIT(2) )
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258 #define BIT_SINDRV_ENA_SQUARE ( BIT(1) )
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259 #define BIT_SINDRV_ENA ( BIT(0) )
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261 /* bits definitions for register REG_AON_APB_RF_ADA_SEL_CTRL */
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262 #define BIT_TW_MODE_SEL ( BIT(3) )
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263 #define BIT_WGADC_DIV_EN ( BIT(2) )
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264 #define BIT_AFCDAC_SYS_SEL ( BIT(1) )
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265 #define BIT_APCDAC_SYS_SEL ( BIT(0) )
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267 /* bits definitions for register REG_AON_APB_RF_VBC_CTRL */
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268 #define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) )
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269 #define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
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270 #define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
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271 #define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
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272 #define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
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273 #define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
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274 #define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
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275 #define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
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276 #define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
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277 #define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) )
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278 #define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) )
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279 #define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) )
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280 #define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) )
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282 /* bits definitions for register REG_AON_APB_RF_PWR_CTRL */
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283 #define BIT_HSIC_PLL_EN ( BIT(19) )
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284 #define BIT_HSIC_PHY_PD ( BIT(18) )
\r
285 #define BIT_HSIC_PS_PD_S ( BIT(17) )
\r
286 #define BIT_HSIC_PS_PD_L ( BIT(16) )
\r
287 #define BIT_MIPI_DSI_PS_PD_S ( BIT(15) )
\r
288 #define BIT_MIPI_DSI_PS_PD_L ( BIT(14) )
\r
289 #define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) )
\r
290 #define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) )
\r
291 #define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) )
\r
292 #define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) )
\r
293 #define BIT_CA7_TS1_STOP ( BIT(9) )
\r
294 #define BIT_CA7_TS0_STOP ( BIT(8) )
\r
295 #define BIT_EFUSE_BIST_PWR_ON ( BIT(3) )
\r
296 #define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) )
\r
297 #define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) )
\r
298 #define BIT_USB_PHY_PD ( BIT(0) )
\r
300 /* bits definitions for register REG_AON_APB_RF_TS_CFG */
\r
301 #define BIT_CSYSACK_TS_LP_2 ( BIT(13) )
\r
302 #define BIT_CSYSREQ_TS_LP_2 ( BIT(12) )
\r
303 #define BIT_CSYSACK_TS_LP_1 ( BIT(11) )
\r
304 #define BIT_CSYSREQ_TS_LP_1 ( BIT(10) )
\r
305 #define BIT_CSYSACK_TS_LP_0 ( BIT(9) )
\r
306 #define BIT_CSYSREQ_TS_LP_0 ( BIT(8) )
\r
307 #define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) )
\r
308 #define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) )
\r
309 #define BIT_EVENT_HALTREQ_TS01 ( BIT(0) )
\r
311 /* bits definitions for register REG_AON_APB_RF_BOOT_MODE */
\r
312 #define BIT_ARM_JTAG_EN ( BIT(13) )
\r
313 #define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) )
\r
314 #define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) )
\r
315 #define BIT_PTEST_FUNC_MODE ( BIT(7) )
\r
316 #define BIT_USB_DLOAD_EN ( BIT(4) )
\r
317 #define BIT_ARM_BOOT_MD3 ( BIT(3) )
\r
318 #define BIT_ARM_BOOT_MD2 ( BIT(2) )
\r
319 #define BIT_ARM_BOOT_MD1 ( BIT(1) )
\r
320 #define BIT_ARM_BOOT_MD0 ( BIT(0) )
\r
322 /* bits definitions for register REG_AON_APB_RF_BB_BG_CTRL */
\r
323 #define BIT_BB_CON_BG ( BIT(22) )
\r
324 #define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
\r
325 #define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
326 #define BIT_BB_BG_RBIAS_EN ( BIT(15) )
\r
327 #define BIT_BB_BG_IEXT_IB_EN ( BIT(14) )
\r
328 #define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
\r
329 #define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) )
\r
330 #define BIT_BB_LDO_SLP_PD_EN ( BIT(10) )
\r
331 #define BIT_BB_LDO_FORCE_ON ( BIT(9) )
\r
332 #define BIT_BB_LDO_FORCE_PD ( BIT(8) )
\r
333 #define BIT_BB_BG_AUTO_PD_EN ( BIT(3) )
\r
334 #define BIT_BB_BG_SLP_PD_EN ( BIT(2) )
\r
335 #define BIT_BB_BG_FORCE_ON ( BIT(1) )
\r
336 #define BIT_BB_BG_FORCE_PD ( BIT(0) )
\r
338 /* bits definitions for register REG_AON_APB_RF_CP_ARM_JTAG_CTRL */
\r
339 #define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
\r
341 /* bits definitions for register REG_AON_APB_RF_PLL_SOFT_CNT_DONE */
\r
342 #define BIT_RC1_SOFT_CNT_DONE ( BIT(13) )
\r
343 #define BIT_RC0_SOFT_CNT_DONE ( BIT(12) )
\r
344 #define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) )
\r
345 #define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) )
\r
346 #define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) )
\r
347 #define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) )
\r
348 #define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) )
\r
349 #define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) )
\r
350 #define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) )
\r
352 /* bits definitions for register REG_AON_APB_RF_DCXO_LC_REG0 */
\r
353 #define BIT_DCXO_LC_FLAG ( BIT(8) )
\r
354 #define BIT_DCXO_LC_FLAG_CLR ( BIT(1) )
\r
355 #define BIT_DCXO_LC_CNT_CLR ( BIT(0) )
\r
357 /* bits definitions for register REG_AON_APB_RF_DCXO_LC_REG1 */
\r
358 #define BITS_DCXO_LC_CNT(_X_) (_X_)
\r
360 /* bits definitions for register REG_AON_APB_RF_MPLL_CFG1 */
\r
361 #define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
\r
362 #define BIT_MPLL_LOCK_DONE ( BIT(27) )
\r
363 #define BIT_MPLL_DIV_S ( BIT(26) )
\r
364 #define BIT_MPLL_MOD_EN ( BIT(25) )
\r
365 #define BIT_MPLL_SDM_EN ( BIT(24) )
\r
366 #define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
367 #define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
368 #define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
369 #define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
371 /* bits definitions for register REG_AON_APB_RF_MPLL_CFG2 */
\r
372 #define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
\r
373 #define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
375 /* bits definitions for register REG_AON_APB_RF_DPLL_CFG1 */
\r
376 #define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
\r
377 #define BIT_DPLL_LOCK_DONE ( BIT(27) )
\r
378 #define BIT_DPLL_DIV_S ( BIT(26) )
\r
379 #define BIT_DPLL_MOD_EN ( BIT(25) )
\r
380 #define BIT_DPLL_SDM_EN ( BIT(24) )
\r
381 #define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
382 #define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
383 #define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
384 #define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
386 /* bits definitions for register REG_AON_APB_RF_DPLL_CFG2 */
\r
387 #define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
\r
388 #define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
390 /* bits definitions for register REG_AON_APB_RF_TWPLL_CFG1 */
\r
391 #define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
\r
392 #define BIT_TWPLL_LOCK_DONE ( BIT(27) )
\r
393 #define BIT_TWPLL_DIV_S ( BIT(26) )
\r
394 #define BIT_TWPLL_MOD_EN ( BIT(25) )
\r
395 #define BIT_TWPLL_SDM_EN ( BIT(24) )
\r
396 #define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
397 #define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
398 #define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
399 #define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
401 /* bits definitions for register REG_AON_APB_RF_TWPLL_CFG2 */
\r
402 #define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
\r
403 #define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
405 /* bits definitions for register REG_AON_APB_RF_LTEPLL_CFG1 */
\r
406 #define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
\r
407 #define BIT_LTEPLL_LOCK_DONE ( BIT(27) )
\r
408 #define BIT_LTEPLL_DIV_S ( BIT(26) )
\r
409 #define BIT_LTEPLL_MOD_EN ( BIT(25) )
\r
410 #define BIT_LTEPLL_SDM_EN ( BIT(24) )
\r
411 #define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
412 #define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
413 #define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
414 #define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
416 /* bits definitions for register REG_AON_APB_RF_LTEPLL_CFG2 */
\r
417 #define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
\r
418 #define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
420 /* bits definitions for register REG_AON_APB_RF_LVDSDISPLL_CFG1 */
\r
421 #define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
422 #define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) )
\r
423 #define BIT_LVDSDISPLL_DIV_S ( BIT(26) )
\r
424 #define BIT_LVDSDISPLL_MOD_EN ( BIT(25) )
\r
425 #define BIT_LVDSDISPLL_SDM_EN ( BIT(24) )
\r
426 #define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
427 #define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
428 #define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
429 #define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
431 /* bits definitions for register REG_AON_APB_RF_LVDSDISPLL_CFG2 */
\r
432 #define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
\r
433 #define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
435 /* bits definitions for register REG_AON_APB_RF_AON_REG_PROT */
\r
436 #define BIT_LDSP_CTRL_PROT ( BIT(31) )
\r
437 #define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
439 /* bits definitions for register REG_AON_APB_RF_LDSP_BOOT_EN */
\r
440 #define BIT_FRC_CLK_LDSP_EN ( BIT(1) )
\r
441 #define BIT_LDSP_BOOT_EN ( BIT(0) )
\r
443 /* bits definitions for register REG_AON_APB_RF_LDSP_BOOT_VEC */
\r
444 #define BITS_LDSP_BOOT_VECTOR(_X_) (_X_)
\r
446 /* bits definitions for register REG_AON_APB_RF_LDSP_RST */
\r
447 #define BIT_LDSP_SYS_SRST ( BIT(1) )
\r
448 #define BIT_LDSP_CORE_SRST_N ( BIT(0) )
\r
450 /* bits definitions for register REG_AON_APB_RF_LDSP_MTX_CTRL1 */
\r
451 #define BITS_LDSP_MTX_CTRL1(_X_) (_X_)
\r
453 /* bits definitions for register REG_AON_APB_RF_LDSP_MTX_CTRL2 */
\r
454 #define BITS_LDSP_MTX_CTRL2(_X_) (_X_)
\r
456 /* bits definitions for register REG_AON_APB_RF_LDSP_MTX_CTRL3 */
\r
457 #define BITS_LDSP_MTX_CTRL3(_X_) (_X_)
\r
459 /* bits definitions for register REG_AON_APB_RF_AON_CGM_CFG */
\r
460 #define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
461 #define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
462 #define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
463 #define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
464 #define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
465 #define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
466 #define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
467 #define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
469 /* bits definitions for register REG_AON_APB_RF_LACC_MTX_CTRL */
\r
470 #define BITS_LACC_MTX_CTRL(_X_) (_X_)
\r
472 /* bits definitions for register REG_AON_APB_RF_CORTEX_MTX_CTRL1 */
\r
473 #define BITS_CORTEX_MTX_CTRL1(_X_) (_X_)
\r
475 /* bits definitions for register REG_AON_APB_RF_CORTEX_MTX_CTRL2 */
\r
476 #define BITS_CORTEX_MTX_CTRL2(_X_) (_X_)
\r
478 /* bits definitions for register REG_AON_APB_RF_CORTEX_MTX_CTRL3 */
\r
479 #define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
481 /* bits definitions for register REG_AON_APB_RF_CA5_TCLK_DLY_LEN */
\r
482 #define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
484 /* bits definitions for register REG_AON_APB_RF_CCIR_RCVR_CFG */
\r
485 #define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
486 #define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
487 #define BIT_CCIR_SE ( BIT(1) )
\r
488 #define BIT_CCIR_IE ( BIT(0) )
\r
490 /* bits definitions for register REG_AON_APB_PLL_BG_CFG */
\r
491 #define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
\r
492 #define BIT_PLL_BG_RBIAS_EN ( BIT(3) )
\r
493 #define BIT_PLL_BG_PD ( BIT(2) )
\r
494 #define BIT_PLL_BG_IEXT_IBEN ( BIT(1) )
\r
495 #define BIT_PLL_CON_BG ( BIT(0) )
\r
497 /* bits definitions for register REG_AON_APB_RF_LVDSDIS_SEL */
\r
498 #define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
\r
499 #define BIT_LVDSDIS_DBG_SEL ( BIT(0) )
\r
501 /* bits definitions for register REG_AON_APB_RF_DJTAG_MUX_SEL */
\r
502 #define BIT_DJTAG_AON_SEL ( BIT(6) )
\r
503 #define BIT_DJTAG_PUB_SEL ( BIT(5) )
\r
504 #define BIT_DJTAG_CP1_SEL ( BIT(4) )
\r
505 #define BIT_DJTAG_CP0_SEL ( BIT(3) )
\r
506 #define BIT_DJTAG_GPU_SEL ( BIT(2) )
\r
507 #define BIT_DJTAG_MM_SEL ( BIT(1) )
\r
508 #define BIT_DJTAG_AP_SEL ( BIT(0) )
\r
510 /* bits definitions for register REG_AON_APB_RF_ARM7_SYS_SOFT_RST */
\r
511 #define BIT_ARM7_SYS_SOFT_RST ( BIT(4) )
\r
512 #define BIT_ARM7_CORE_SOFT_RST ( BIT(0) )
\r
514 /* bits definitions for register REG_AON_APB_RF_CP1_CP0_ADDR_MSB */
\r
515 #define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
517 /* bits definitions for register REG_AON_APB_RF_AON_DMA_INT_EN */
\r
518 #define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) )
\r
519 #define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) )
\r
520 #define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) )
\r
521 #define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) )
\r
522 #define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) )
\r
523 #define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) )
\r
524 #define BIT_AON_DMA_INT_AP_EN ( BIT(0) )
\r
526 /* bits definitions for register REG_AON_APB_RF_CP0_ADDR_REMAP_CTRL0 */
\r
527 #define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) )
\r
528 #define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) )
\r
529 #define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) )
\r
530 #define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) )
\r
531 #define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) )
\r
532 #define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) )
\r
533 #define BIT_AP_EMC_AUTO_GATE_EN ( BIT(1) )
\r
534 #define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(0) )
\r
536 /* bits definitions for register REG_AON_APB_ARM7_CFG_BUS */
\r
537 #define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) )
\r
539 /* bits definitions for register REG_AON_APB_RF_CP1_ADDR_REMAP_CTRL0 */
\r
540 #define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
541 #define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
542 #define BIT_RTC4M0_CAL_DONE ( BIT(6) )
\r
543 #define BIT_RTC4M0_CAL_START ( BIT(5) )
\r
544 #define BIT_RTC4M0_CHOP_EN ( BIT(4) )
\r
545 #define BIT_RTC4M0_FORCE_EN ( BIT(1) )
\r
546 #define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) )
\r
548 /* bits definitions for register REG_AON_APB_RTC4M_1_CFG */
\r
549 #define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
550 #define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
551 #define BIT_RTC4M1_CAL_DONE ( BIT(6) )
\r
552 #define BIT_RTC4M1_CAL_START ( BIT(5) )
\r
553 #define BIT_RTC4M1_CHOP_EN ( BIT(4) )
\r
554 #define BIT_RTC4M1_FORCE_EN ( BIT(1) )
\r
555 #define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) )
\r
557 /* bits definitions for register REG_AON_APB_RF_CP1_ADDR_REMAP_CTRL1 */
\r
558 #define BIT_AON_DJTAG_SOFT_RST ( BIT(6) )
\r
559 #define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) )
\r
560 #define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) )
\r
561 #define BIT_MM_DJTAG_SOFT_RST ( BIT(3) )
\r
562 #define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) )
\r
563 #define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) )
\r
564 #define BIT_AP_DJTAG_SOFT_RST ( BIT(0) )
\r
566 /* bits definitions for register REG_AON_APB_AP_WPROT_EN1 */
\r
567 #define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_)
\r
569 /* bits definitions for register REG_AON_APB_CP0_WPROT_EN1 */
\r
570 #define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_)
\r
572 /* bits definitions for register REG_AON_APB_CP1_WPROT_EN1 */
\r
573 #define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_)
\r
575 /* bits definitions for register REG_AON_APB_RF_IO_DLY_CTRL */
\r
576 #define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
577 #define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
578 #define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
580 /* bits definitions for register REG_AON_APB_RF_AP_WPROT_EN */
\r
581 #define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_)
\r
583 /* bits definitions for register REG_AON_APB_RF_CP0_WPROT_EN */
\r
584 #define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_)
\r
586 /* bits definitions for register REG_AON_APB_RF_CP1_WPROT_EN */
\r
587 #define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_)
\r
589 /* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
\r
590 #define BITS_PMU_RST_MONITOR(_X_) (_X_)
\r
592 /* bits definitions for register REG_AON_APB_RF_THM_RST_MONITOR */
\r
593 #define BITS_THM_RST_MONITOR(_X_) (_X_)
\r
595 /* bits definitions for register REG_AON_APB_RF_AP_RST_MONITOR */
\r
596 #define BITS_AP_RST_MONITOR(_X_) (_X_)
\r
598 /* bits definitions for register REG_AON_APB_RF_CA7_RST_MONITOR */
\r
599 #define BITS_CA7_RST_MONITOR(_X_) (_X_)
\r
601 /* bits definitions for register REG_AON_APB_RF_BOND_OPT0 */
\r
602 #define BITS_BOND_OPTION0(_X_) (_X_)
\r
604 /* bits definitions for register REG_AON_APB_RF_BOND_OPT1 */
\r
605 #define BITS_BOND_OPTION1(_X_) (_X_)
\r
607 /* bits definitions for register REG_AON_APB_RF_RES_REG0 */
\r
608 #define BITS_RES_REG0(_X_) (_X_)
\r
610 /* bits definitions for register REG_AON_APB_RF_RES_REG1 */
\r
611 #define BITS_RES_REG1(_X_) (_X_)
\r
613 /* bits definitions for register REG_AON_APB_RF_AON_QOS_CFG */
\r
614 #define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
615 #define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
616 #define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
617 #define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
619 /* bits definitions for register REG_AON_APB_RF_BB_LDO_CAL_START */
\r
620 #define BIT_BB_LDO_CAL_START ( BIT(0) )
\r
622 /* bits definitions for register REG_AON_APB_RF_AON_MTX_PROT_CFG */
\r
623 #define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
624 #define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
626 /* bits definitions for register REG_AON_APB_RF_LVDS_CFG */
\r
627 #define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
\r
628 #define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
\r
629 #define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
630 #define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
631 #define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
632 #define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
\r
633 #define BIT_LVDSDIS_TXPD ( BIT(0) )
\r
635 #define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) )
\r
636 #define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
\r
637 #define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
639 /* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */
\r
640 #define BIT_RTC4M1_RC_SEL ( BIT(31) )
\r
641 #define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
\r
642 #define BIT_RTC4M0_RC_SEL ( BIT(15) )
\r
643 #define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
\r
645 /* bits definitions for register REG_AON_APB_AON_APB_RSV */
\r
646 #define BITS_AON_APB_RSV(_X_) (_X_)
\r
648 /* bits definitions for register REG_AON_APB_RF_AON_CHIP_ID */
\r
649 #define BITS_AON_CHIP_ID(_X_) (_X_)
\r
651 #define BIT_MIPI_DSI_PS_PD_S BIT(15)
\r
652 #define BIT_MIPI_DSI_PS_PD_L BIT(14)
\r
653 #define BIT_MIPI_CSI_4LANE_PS_PD_S BIT(13)
\r
654 #define BIT_MIPI_CSI_4LANE_PS_PD_L BIT(12)
\r
655 #define BIT_MIPI_CSI_2LANE_PS_PD_S BIT(11)
\r
656 #define BIT_MIPI_CSI_2LANE_PS_PD_L BIT(10)
\r
projects / profile / mobile / platform / kernel / u-boot-tm1.git / blob