2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
10 #ifndef __SC2723_ANA_REGS_GLB_H__
11 #define __SC2723_ANA_REGS_GLB_H__
14 /* registers definitions for controller ANA_REGS_GLB */
15 #define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000)
16 #define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004)
17 #define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008)
18 #define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C)
19 #define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010)
20 #define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014)
21 #define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018)
22 #define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C)
23 #define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020)
24 #define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024)
25 #define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028)
26 #define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C)
27 #define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030)
28 #define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034)
29 #define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038)
30 #define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C)
31 #define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040)
32 #define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044)
33 #define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048)
34 #define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C)
35 #define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050)
36 #define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054)
37 #define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058)
38 #define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C)
39 #define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060)
40 #define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064)
41 #define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068)
42 #define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C)
43 #define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070)
44 #define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074)
45 #define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078)
46 #define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C)
47 #define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080)
48 #define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084)
49 #define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088)
50 #define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C)
51 #define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090)
52 #define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094)
53 #define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098)
54 #define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C)
55 #define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0)
56 #define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4)
57 #define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8)
58 #define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC)
59 #define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0)
60 #define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4)
61 #define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8)
62 #define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC)
63 #define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0)
64 #define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4)
65 #define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8)
66 #define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC)
67 #define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0)
68 #define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4)
69 #define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8)
70 #define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC)
71 #define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0)
72 #define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4)
73 #define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8)
74 #define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC)
75 #define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0)
76 #define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4)
77 #define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8)
78 #define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC)
79 #define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100)
80 #define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104)
81 #define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108)
82 #define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C)
83 #define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110)
84 #define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114)
85 #define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118)
86 #define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C)
87 #define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120)
88 #define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124)
89 #define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128)
90 #define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C)
91 #define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130)
92 #define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134)
93 #define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138)
94 #define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C)
95 #define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140)
96 #define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144)
97 #define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148)
98 #define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C)
99 #define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150)
100 #define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154)
101 #define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158)
102 #define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C)
103 #define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160)
104 #define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164)
105 #define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188)
106 #define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C)
107 #define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190)
108 #define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194)
109 #define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198)
110 #define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C)
111 #define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200)
112 #define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204)
113 #define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208)
114 #define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C)
115 #define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210)
116 #define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214)
117 #define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218)
118 #define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C)
120 /* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */
121 #define BIT_ANA_IMPD_ADC_EN ( BIT(12) )
122 #define BIT_ANA_THM_EN ( BIT(11) )
123 #define BIT_ANA_BLTC_EN ( BIT(10) )
124 #define BIT_ANA_PINREG_EN ( BIT(9) )
125 #define BIT_ANA_FGU_EN ( BIT(8) )
126 #define BIT_ANA_EFS_EN ( BIT(7) )
127 #define BIT_ANA_ADC_EN ( BIT(6) )
128 #define BIT_ANA_HDT_EN ( BIT(5) )
129 #define BIT_ANA_AUD_EN ( BIT(4) )
130 #define BIT_ANA_EIC_EN ( BIT(3) )
131 #define BIT_ANA_WDG_EN ( BIT(2) )
132 #define BIT_ANA_RTC_EN ( BIT(1) )
133 #define BIT_ANA_CAL_EN ( BIT(0) )
135 /* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */
136 #define BIT_CLK_IMPD_ADC_EN ( BIT(10) )
137 #define BIT_CLK_AUXAD_EN ( BIT(9) )
138 #define BIT_CLK_AUXADC_EN ( BIT(8) )
139 #define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) )
140 #define BIT_CLK_CAL_EN ( BIT(5) )
141 #define BIT_CLK_AUD_HID_EN ( BIT(4) )
142 #define BIT_CLK_AUD_HBD_EN ( BIT(3) )
143 #define BIT_CLK_AUD_LOOP_EN ( BIT(2) )
144 #define BIT_CLK_AUD_6P5M_EN ( BIT(1) )
145 #define BIT_CLK_AUDIF_EN ( BIT(0) )
147 /* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */
148 #define BIT_RTC_EFS_EN ( BIT(12) )
149 #define BIT_RTC_THMA_AUTO_EN ( BIT(11) )
150 #define BIT_RTC_THMA_EN ( BIT(10) )
151 #define BIT_RTC_THM_EN ( BIT(9) )
152 #define BIT_RTC_BLTC_EN ( BIT(8) )
153 #define BIT_RTC_FGU_EN ( BIT(7) )
154 #define BIT_RTC_FGUA_EN ( BIT(6) )
155 #define BIT_RTC_VIBR_EN ( BIT(5) )
156 #define BIT_RTC_AUD_EN ( BIT(4) )
157 #define BIT_RTC_EIC_EN ( BIT(3) )
158 #define BIT_RTC_WDG_EN ( BIT(2) )
159 #define BIT_RTC_RTC_EN ( BIT(1) )
160 #define BIT_RTC_ARCH_EN ( BIT(0) )
162 /* bits definitions for register ANA_REG_GLB_ARM_RST */
163 #define BIT_ANA_THMA_SOFT_RST ( BIT(15) )
164 #define BIT_ANA_THM_SOFT_RST ( BIT(14) )
165 #define BIT_ANA_BLTC_SOFT_RST ( BIT(13) )
166 #define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) )
167 #define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) )
168 #define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) )
169 #define BIT_ANA_AUD_SOFT_RST ( BIT(9) )
170 #define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) )
171 #define BIT_ANA_EFS_SOFT_RST ( BIT(7) )
172 #define BIT_ANA_ADC_SOFT_RST ( BIT(6) )
173 #define BIT_ANA_PWM0_SOFT_RST ( BIT(5) )
174 #define BIT_ANA_FGU_SOFT_RST ( BIT(4) )
175 #define BIT_ANA_EIC_SOFT_RST ( BIT(3) )
176 #define BIT_ANA_WDG_SOFT_RST ( BIT(2) )
177 #define BIT_ANA_RTC_SOFT_RST ( BIT(1) )
178 #define BIT_ANA_CAL_SOFT_RST ( BIT(0) )
180 /* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */
181 #define BIT_LDO_EMM_PD ( BIT(15) )
182 #define BIT_DCDC_TOPCLK6M_PD ( BIT(14) )
183 #define BIT_DCDC_RF_PD ( BIT(13) )
184 #define BIT_DCDC_GEN_PD ( BIT(12) )
185 #define BIT_DCDC_MEM_PD ( BIT(11) )
186 #define BIT_DCDC_ARM_PD ( BIT(10) )
187 #define BIT_DCDC_CORE_PD ( BIT(9) )
188 #define BIT_LDO_RF0_PD ( BIT(8) )
189 #define BIT_LDO_EMMCCORE_PD ( BIT(7) )
190 #define BIT_LDO_GEN1_PD ( BIT(6) )
191 #define BIT_LDO_DCXO_PD ( BIT(5) )
192 #define BIT_LDO_GEN0_PD ( BIT(4) )
193 #define BIT_LDO_VDD25_PD ( BIT(3) )
194 #define BIT_LDO_VDD28_PD ( BIT(2) )
195 #define BIT_LDO_VDD18_PD ( BIT(1) )
196 #define BIT_BG_PD ( BIT(0) )
198 /* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */
199 #define BIT_LDO_LPREF_PD_SW ( BIT(15) )
200 #define BIT_DCDC_WPA_PD ( BIT(14) )
201 #define BIT_DCDC_CON_PD ( BIT(13) )
202 #define BIT_LDO_WIFIPA_PD ( BIT(11) )
203 #define BIT_LDO_SDCORE_PD ( BIT(10) )
204 #define BIT_LDO_USB_PD ( BIT(8) )
205 #define BIT_LDO_CAMMOT_PD ( BIT(7) )
206 #define BIT_LDO_CAMIO_PD ( BIT(6) )
207 #define BIT_LDO_CAMD_PD ( BIT(5) )
208 #define BIT_LDO_CAMA_PD ( BIT(4) )
209 #define BIT_LDO_SIM2_PD ( BIT(3) )
210 #define BIT_LDO_SIM1_PD ( BIT(2) )
211 #define BIT_LDO_SIM0_PD ( BIT(1) )
212 #define BIT_LDO_SDIO_PD ( BIT(0) )
214 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */
215 #define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
216 #define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
218 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */
219 #define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
220 #define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
222 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */
223 #define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
225 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */
226 #define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
227 #define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
229 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */
230 #define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
231 #define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
233 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */
234 #define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
235 #define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
237 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */
238 #define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
239 #define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
241 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */
242 #define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
243 #define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
245 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */
246 #define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
247 #define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
249 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */
250 #define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
251 #define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
253 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */
254 #define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
256 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */
257 #define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
258 #define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
259 #define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
260 #define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) )
261 #define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
263 /* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */
264 #define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
265 #define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
266 #define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
268 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */
269 #define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
270 #define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
271 #define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
272 #define BIT_DCDC_CORE_QKRSPS ( BIT(3) )
273 #define BIT_DCDC_CORE_PFM ( BIT(2) )
274 #define BIT_DCDC_CORE_DCM ( BIT(1) )
275 #define BIT_DCDC_CORE_LP_EN ( BIT(0) )
277 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */
278 #define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
279 #define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
280 #define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
281 #define BIT_DCDC_MEM_QKRSPS ( BIT(3) )
282 #define BIT_DCDC_MEM_PFM ( BIT(2) )
283 #define BIT_DCDC_MEM_DCM ( BIT(1) )
284 #define BIT_DCDC_MEM_LP_EN ( BIT(0) )
286 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */
287 #define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
288 #define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
289 #define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
290 #define BIT_DCDC_GEN_QKRSPS ( BIT(3) )
291 #define BIT_DCDC_GEN_PFM ( BIT(2) )
292 #define BIT_DCDC_GEN_DCM ( BIT(1) )
293 #define BIT_DCDC_GEN_LP_EN ( BIT(0) )
295 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */
296 #define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
297 #define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
298 #define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
299 #define BIT_DCDC_ARM_QKRSPS ( BIT(3) )
300 #define BIT_DCDC_ARM_PFM ( BIT(2) )
301 #define BIT_DCDC_ARM_DCM ( BIT(1) )
302 #define BIT_DCDC_ARM_LP_EN ( BIT(0) )
304 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */
305 #define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
306 #define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
307 #define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
308 #define BIT_DCDC_WPA_QKRSPS ( BIT(3) )
309 #define BIT_DCDC_WPA_PFM ( BIT(2) )
310 #define BIT_DCDC_WPA_LP_EN ( BIT(0) )
312 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */
313 #define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
314 #define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
315 #define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
316 #define BIT_DCDC_RF_QKRSPS ( BIT(3) )
317 #define BIT_DCDC_RF_PFM ( BIT(2) )
318 #define BIT_DCDC_RF_DCM ( BIT(1) )
319 #define BIT_DCDC_RF_LP_EN ( BIT(0) )
321 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */
322 #define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
323 #define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
324 #define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
325 #define BIT_DCDC_CON_QKRSPS ( BIT(3) )
326 #define BIT_DCDC_CON_PFM ( BIT(2) )
327 #define BIT_DCDC_CON_DCM ( BIT(1) )
328 #define BIT_DCDC_CON_LP_EN ( BIT(0) )
330 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */
331 #define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
332 #define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
333 #define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
334 #define BIT_DCDC_CORE_DUALSEL ( BIT(7) )
335 #define BIT_DCDC_CORE_MERGEEN ( BIT(6) )
336 #define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
337 #define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
338 #define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
340 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */
341 #define BIT_DCDC_ARM_DUALSEL ( BIT(15) )
342 #define BIT_DCDC_ARM_MERGEEN ( BIT(14) )
343 #define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
344 #define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
345 #define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
346 #define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
347 #define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
348 #define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
350 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */
351 #define BIT_DCDC_CON_MERGEEN ( BIT(14) )
352 #define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
353 #define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
354 #define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
355 #define BIT_DCDC_RF_MERGEEN ( BIT(6) )
356 #define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
357 #define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
358 #define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
360 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */
361 #define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) )
362 #define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
363 #define BIT_DCDC_WPA_BPEN ( BIT(11) )
364 #define BIT_DCDC_WPA_BPMODE ( BIT(10) )
365 #define BIT_DCDC_WPA_DEGEN ( BIT(9) )
366 #define BIT_DCDC_WPA_APTEN ( BIT(8) )
367 #define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) )
368 #define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
369 #define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
370 #define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
372 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */
373 #define BIT_DCDC_3MCLKCAL_EN ( BIT(13) )
374 #define BIT_DCDC_2MCLKCAL_EN ( BIT(12) )
375 #define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
376 #define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
377 #define BIT_DCDC_CLK_SP_SEL ( BIT(1) )
378 #define BIT_DCDC_CLK_SP_EN ( BIT(0) )
380 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */
381 #define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) )
382 #define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) )
383 #define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) )
384 #define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
385 #define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) )
386 #define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) )
387 #define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) )
388 #define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
390 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */
391 #define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) )
392 #define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) )
393 #define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) )
394 #define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
395 #define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) )
396 #define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) )
397 #define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) )
398 #define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
400 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */
401 #define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) )
402 #define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) )
403 #define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) )
404 #define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
405 #define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) )
406 #define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) )
407 #define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) )
408 #define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
410 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */
411 #define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) )
412 #define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) )
413 #define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) )
414 #define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) )
415 #define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
417 /* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */
418 #define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
419 #define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
421 /* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */
422 #define BIT_SLP_IO_EN ( BIT(15) )
423 #define BIT_SLP_DCDCRF_PD_EN ( BIT(13) )
424 #define BIT_SLP_DCDCCON_PD_EN ( BIT(12) )
425 #define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) )
426 #define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) )
427 #define BIT_SLP_DCDCARM_PD_EN ( BIT(9) )
428 #define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) )
429 #define BIT_SLP_LDORF0_PD_EN ( BIT(7) )
430 #define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) )
431 #define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) )
432 #define BIT_SLP_LDODCXO_PD_EN ( BIT(4) )
433 #define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) )
434 #define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) )
435 #define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) )
436 #define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) )
438 /* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */
439 #define BIT_SLP_LDO_PD_EN ( BIT(15) )
440 #define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) )
441 #define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) )
442 #define BIT_SLP_LDOUSB_PD_EN ( BIT(8) )
443 #define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) )
444 #define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) )
445 #define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) )
446 #define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) )
447 #define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) )
448 #define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) )
449 #define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) )
450 #define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) )
452 /* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */
453 #define BIT_SLP_DCDCRF_LP_EN ( BIT(14) )
454 #define BIT_SLP_DCDCCON_LP_EN ( BIT(13) )
455 #define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) )
456 #define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) )
457 #define BIT_SLP_DCDCARM_LP_EN ( BIT(10) )
458 #define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) )
459 #define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) )
460 #define BIT_SLP_LDORF0_LP_EN ( BIT(7) )
461 #define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) )
462 #define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) )
463 #define BIT_SLP_LDODCXO_LP_EN ( BIT(4) )
464 #define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) )
465 #define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) )
466 #define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) )
467 #define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) )
469 /* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */
470 #define BIT_SLP_BG_LP_EN ( BIT(15) )
471 #define BIT_LDOVDD25_LP_EN_SW ( BIT(14) )
472 #define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) )
473 #define BIT_LDOUSB_LP_EN_SW ( BIT(12) )
474 #define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) )
475 #define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) )
476 #define BIT_SLP_LDOUSB_LP_EN ( BIT(8) )
477 #define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) )
478 #define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) )
479 #define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) )
480 #define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) )
481 #define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) )
482 #define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) )
483 #define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) )
484 #define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) )
486 /* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */
487 #define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) )
488 #define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) )
489 #define BIT_LDOCAMD_LP_EN_SW ( BIT(13) )
490 #define BIT_LDOCAMA_LP_EN_SW ( BIT(12) )
491 #define BIT_LDOSIM2_LP_EN_SW ( BIT(11) )
492 #define BIT_LDOSIM1_LP_EN_SW ( BIT(10) )
493 #define BIT_LDOSIM0_LP_EN_SW ( BIT(9) )
494 #define BIT_LDOSDIO_LP_EN_SW ( BIT(8) )
495 #define BIT_LDORF0_LP_EN_SW ( BIT(7) )
496 #define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) )
497 #define BIT_LDOGEN0_LP_EN_SW ( BIT(5) )
498 #define BIT_LDODCXO_LP_EN_SW ( BIT(4) )
499 #define BIT_LDOGEN1_LP_EN_SW ( BIT(3) )
500 #define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) )
501 #define BIT_LDOVDD28_LP_EN_SW ( BIT(1) )
502 #define BIT_LDOVDD18_LP_EN_SW ( BIT(0) )
504 /* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */
505 #define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) )
506 #define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) )
507 #define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) )
508 #define BIT_SLP_AUD_PA_PD_EN ( BIT(11) )
509 #define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) )
510 #define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) )
511 #define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) )
512 #define BIT_SLP_AUD_VB_PD_EN ( BIT(7) )
513 #define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) )
514 #define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) )
515 #define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) )
516 #define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) )
517 #define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) )
518 #define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
520 /* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */
521 #define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
522 #define BIT_PWR_OFF_SEQ_EN ( BIT(2) )
523 #define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) )
524 #define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) )
526 /* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */
527 #define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
528 #define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
530 /* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */
531 #define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
532 #define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
533 #define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
535 /* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */
536 #define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
537 #define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
539 /* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */
540 #define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
541 #define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
542 #define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
544 /* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */
545 #define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
546 #define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
548 /* bits definitions for register ANA_REG_GLB_PWR_SEL */
549 #define BIT_LDO_GEN0_SW_SEL ( BIT(13) )
550 #define BIT_LDO_GEN1_SW_SEL ( BIT(12) )
551 #define BIT_LDO_RF0_SW_SEL ( BIT(11) )
552 #define BIT_LDO_VDD18_SW_SEL ( BIT(10) )
553 #define BIT_LDO_VDD28_SW_SEL ( BIT(9) )
554 #define BIT_LDO_DCXO_SW_SEL ( BIT(8) )
555 #define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) )
556 #define BIT_LDO_VDD25_SW_SEL ( BIT(6) )
557 #define BIT_DCDC_RF_SW_SEL ( BIT(5) )
558 #define BIT_DCDC_GEN_SW_SEL ( BIT(4) )
559 #define BIT_DCDC_MEM_SW_SEL ( BIT(3) )
560 #define BIT_DCDC_ARM_SW_SEL ( BIT(2) )
561 #define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) )
562 #define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) )
564 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */
565 #define BIT_LDO_XTL_EN ( BIT(15) )
566 #define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) )
567 #define BIT_LDO_GEN0_XTL1_EN ( BIT(13) )
568 #define BIT_LDO_GEN0_XTL0_EN ( BIT(12) )
569 #define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) )
570 #define BIT_LDO_GEN1_XTL1_EN ( BIT(10) )
571 #define BIT_LDO_GEN1_XTL0_EN ( BIT(9) )
572 #define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) )
573 #define BIT_LDO_DCXO_XTL1_EN ( BIT(7) )
574 #define BIT_LDO_DCXO_XTL0_EN ( BIT(6) )
575 #define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) )
576 #define BIT_LDO_VDD18_XTL1_EN ( BIT(4) )
577 #define BIT_LDO_VDD18_XTL0_EN ( BIT(3) )
578 #define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) )
579 #define BIT_LDO_VDD28_XTL1_EN ( BIT(1) )
580 #define BIT_LDO_VDD28_XTL0_EN ( BIT(0) )
582 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */
583 #define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) )
584 #define BIT_LDO_RF0_XTL1_EN ( BIT(13) )
585 #define BIT_LDO_RF0_XTL0_EN ( BIT(12) )
586 #define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) )
587 #define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) )
588 #define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) )
589 #define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) )
590 #define BIT_LDO_SIM2_XTL1_EN ( BIT(7) )
591 #define BIT_LDO_SIM2_XTL0_EN ( BIT(6) )
592 #define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) )
593 #define BIT_LDO_SIM1_XTL1_EN ( BIT(4) )
594 #define BIT_LDO_SIM1_XTL0_EN ( BIT(3) )
595 #define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) )
596 #define BIT_LDO_SIM0_XTL1_EN ( BIT(1) )
597 #define BIT_LDO_SIM0_XTL0_EN ( BIT(0) )
599 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */
600 #define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) )
601 #define BIT_LDO_VDD25_XTL1_EN ( BIT(10) )
602 #define BIT_LDO_VDD25_XTL0_EN ( BIT(9) )
603 #define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) )
604 #define BIT_DCDC_RF_XTL1_EN ( BIT(7) )
605 #define BIT_DCDC_RF_XTL0_EN ( BIT(6) )
606 #define BIT_XO_EXT_XTL0_EN ( BIT(5) )
607 #define BIT_XO_XTL1_EN ( BIT(4) )
608 #define BIT_XO_XTL0_EN ( BIT(3) )
609 #define BIT_BG_EXT_XTL0_EN ( BIT(2) )
610 #define BIT_BG_XTL1_EN ( BIT(1) )
611 #define BIT_BG_XTL0_EN ( BIT(0) )
613 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */
614 #define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) )
615 #define BIT_DCDC_CON_XTL1_EN ( BIT(13) )
616 #define BIT_DCDC_CON_XTL0_EN ( BIT(12) )
617 #define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) )
618 #define BIT_DCDC_WPA_XTL1_EN ( BIT(10) )
619 #define BIT_DCDC_WPA_XTL0_EN ( BIT(9) )
620 #define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) )
621 #define BIT_DCDC_MEM_XTL1_EN ( BIT(7) )
622 #define BIT_DCDC_MEM_XTL0_EN ( BIT(6) )
623 #define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) )
624 #define BIT_DCDC_GEN_XTL1_EN ( BIT(4) )
625 #define BIT_DCDC_GEN_XTL0_EN ( BIT(3) )
626 #define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) )
627 #define BIT_DCDC_CORE_XTL1_EN ( BIT(1) )
628 #define BIT_DCDC_CORE_XTL0_EN ( BIT(0) )
630 /* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */
631 #define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) )
632 #define BIT_XO_LOW_CUR_FLAG ( BIT(13) )
633 #define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) )
634 #define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) )
635 #define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) )
636 #define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) )
637 #define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) )
638 #define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) )
639 #define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) )
640 #define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) )
641 #define BIT_XO_LOW_CUR_EN ( BIT(3) )
642 #define BIT_EXT_32K_PD ( BIT(2) )
643 #define BIT_RC_32K_SEL ( BIT(1) )
644 #define BIT_RC_32K_EN ( BIT(0) )
646 /* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */
647 #define BITS_RC_MODE(_x_) ( (_x_) << 0 )
649 /* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */
650 #define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 )
652 /* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */
653 #define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 )
655 /* bits definitions for register ANA_REG_GLB_AUXAD_CTL */
656 #define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) )
657 #define BIT_AUXAD_CURRENTSEL ( BIT(5) )
658 #define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
660 /* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */
661 #define BIT_SLP_XTLBUF_PD_EN ( BIT(9) )
662 #define BIT_XTL_EN ( BIT(8) )
663 #define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
665 /* bits definitions for register ANA_REG_GLB_RGB_CTRL */
666 #define BIT_RTC_PWM0_EN ( BIT(15) )
667 #define BIT_PWM0_EN ( BIT(14) )
668 #define BIT_IB_REX_EN ( BIT(12) )
669 #define BIT_IB_TRIM_EM_SEL ( BIT(11) )
670 #define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
671 #define BIT_SLP_RGB_PD_EN ( BIT(2) )
672 #define BIT_RGB_PD_HW_EN ( BIT(1) )
673 #define BIT_RGB_PD_SW ( BIT(0) )
675 /* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */
676 #define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
677 #define BIT_WHTLED_SERIES_EN ( BIT(8) )
678 #define BIT_WHTLED_PD_SEL ( BIT(7) )
679 #define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
680 #define BIT_WHTLED_PD ( BIT(0) )
682 /* bits definitions for register ANA_REG_GLB_KPLED_CTRL */
683 #define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
684 #define BIT_KPLED_PD ( BIT(11) )
685 #define BIT_KPLED_PULLDOWN_EN ( BIT(10) )
686 #define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) )
687 #define BIT_LDO_KPLED_PD ( BIT(8) )
688 #define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
690 /* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */
691 #define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
692 #define BIT_VIBR_PULLDOWN_EN ( BIT(11) )
693 #define BIT_VIBR_PULLUP_EN ( BIT(10) )
694 #define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) )
695 #define BIT_LDO_VIBR_PD ( BIT(8) )
696 #define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
698 /* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */
699 #define BIT_AUD_SLP_APP_RST_EN ( BIT(15) )
700 #define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
701 #define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) )
702 #define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) )
703 #define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) )
704 #define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) )
705 #define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) )
707 /* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */
708 #define BIT_IMPD_ADC_SOFT_RST ( BIT(7) )
709 #define BIT_HEAD_INSERT_EIC_EN ( BIT(6) )
710 #define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) )
711 #define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
713 /* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */
714 #define BIT_CHGLDO_DIS ( BIT(15) )
715 #define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
716 #define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
717 #define BIT_CHGR_PD ( BIT(0) )
719 /* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */
720 #define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
721 #define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
722 #define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
724 /* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */
725 #define BIT_CHGR_INT_EN ( BIT(15) )
726 #define BIT_CHGR_DRV ( BIT(7) )
727 #define BIT_CHGR_OSC ( BIT(6) )
728 #define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
729 #define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
730 #define BIT_CHGR_CC_EN ( BIT(1) )
731 #define BIT_RECHG ( BIT(0) )
733 /* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */
734 #define BIT_FGUA_SOFT_RST ( BIT(13) )
735 #define BIT_LDO_FGU_PD ( BIT(12) )
736 #define BIT_SD_CHOP_CAP_EN ( BIT(8) )
737 #define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) )
738 #define BIT_SD_DCOFFSET_EN ( BIT(5) )
739 #define BIT_SD_CHOP_EN ( BIT(4) )
740 #define BIT_CHOP_EN (BIT_SD_CHOP_EN)
741 #define BIT_DP_DM_AUX_EN ( BIT(1) )
742 #define BIT_DP_DM_SW_EN ( BIT(0) )
744 /* bits definitions for register ANA_REG_GLB_CHGR_STATUS */
745 #define BIT_CHG_DET_DONE ( BIT(11) )
746 #define BIT_DP_LOW ( BIT(10) )
747 #define BIT_DCP_DET ( BIT(9) )
748 #define BIT_CHG_DET ( BIT(8) )
749 #define BIT_SDP_INT ( BIT(7) )
750 #define BIT_DCP_INT ( BIT(6) )
751 #define BIT_CDP_INT ( BIT(5) )
752 #define BIT_CHGR_CV_STATUS ( BIT(4) )
753 #define BIT_CHGR_ON ( BIT(3) )
754 #define BIT_CHGR_INT ( BIT(2) )
755 #define BIT_VBAT_OVI ( BIT(1) )
756 #define BIT_VCHG_OVI ( BIT(0) )
758 /* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */
759 #define BIT_PTEST_PD_RTCSET ( BIT(15) )
760 #define BIT_DCDC_V_CTRL_MODE ( BIT(14) )
761 #define BIT_LDO_RAMP_EN ( BIT(13) )
762 #define BIT_BG_LP_EN ( BIT(12) )
763 #define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
764 #define BIT_OVLO_EN ( BIT(9) )
765 #define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
766 #define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
767 #define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
769 /* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */
770 #define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
771 #define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
772 #define BIT_BATDET_LDO_SEL ( BIT(9) )
773 #define BIT_THM_CHIP_PD_FLAG ( BIT(8) )
774 #define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) )
775 #define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) )
776 #define BIT_THM_AUTO_PD_EN ( BIT(4) )
777 #define BIT_ALL_GPI_DEB ( BIT(3) )
778 #define BIT_GPI_DEBUG_EN ( BIT(2) )
779 #define BIT_ALL_INT_DEB ( BIT(1) )
780 #define BIT_INT_DEBUG_EN ( BIT(0) )
782 /* bits definitions for register ANA_REG_GLB_SWRST_CTRL */
783 #define BIT_POR_RTC_PD ( BIT(15) )
784 #define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) )
785 #define BIT_SW_RST_GEN1_PD_EN ( BIT(12) )
786 #define BIT_SW_RST_GEN0_PD_EN ( BIT(11) )
787 #define BIT_EXT_RSTN_PD_EN ( BIT(10) )
788 #define BIT_PB_7S_RST_PD_EN ( BIT(9) )
789 #define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) )
790 #define BIT_KEY2_7S_RST_EN ( BIT(7) )
791 #define BIT_WDG_RST_PD_EN ( BIT(6) )
792 #define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
794 /* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */
795 #define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 )
797 /* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */
798 #define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 )
800 /* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */
801 #define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 )
803 /* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */
804 #define BIT_POR_SW_FORCE_ON ( BIT(15) )
805 #define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
807 /* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */
808 #define BIT_PBINT_7S_FLAG_CLR ( BIT(15) )
809 #define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) )
810 #define BIT_CHGR_INT_FLAG_CLR ( BIT(13) )
811 #define BIT_PBINT2_FLAG_CLR ( BIT(12) )
812 #define BIT_PBINT_FLAG_CLR ( BIT(11) )
813 #define BIT_PBINT_7S_RST_SWMODE ( BIT(8) )
814 #define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
815 #define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) )
816 #define BIT_PBINT_7S_RST_DISABLE ( BIT(1) )
817 #define BIT_PBINT_7S_RST_MODE ( BIT(0) )
819 /* bits definitions for register ANA_REG_GLB_HWRST_RTC */
820 #define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
821 #define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
823 /* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */
824 #define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 )
826 /* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */
827 #define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 )
829 /* bits definitions for register ANA_REG_GLB_ARM_MF_REG */
830 #define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 )
832 /* bits definitions for register ANA_REG_GLB_ARCH_EN */
833 #define BIT_ARCH_EN ( BIT(0) )
835 /* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */
836 #define BIT_MCU_WR_PROT ( BIT(15) )
837 #define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
839 /* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */
840 #define BIT_PWR_WR_PROT ( BIT(15) )
841 #define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
843 /* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */
844 #define BITS_SMPL_MODE(_x_) ( (_x_) << 0 )
846 /* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */
847 #define BIT_SMPL_PWR_ON_FLAG ( BIT(15) )
848 #define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) )
849 #define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) )
850 #define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) )
851 #define BIT_SMPL_PWR_ON_SET ( BIT(11) )
852 #define BIT_SMPL_EN ( BIT(0) )
854 /* bits definitions for register ANA_REG_GLB_RTC_RST0 */
855 #define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) )
857 /* bits definitions for register ANA_REG_GLB_RTC_RST1 */
858 #define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) )
860 /* bits definitions for register ANA_REG_GLB_RTC_RST2 */
861 #define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) )
863 /* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */
864 #define BIT_LDO_USB_SHPT_PD ( BIT(12) )
865 #define BIT_LDO_DCXO_SHPT_PD ( BIT(11) )
866 #define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) )
867 #define BIT_LDO_VDD25_SHPT_PD ( BIT(9) )
868 #define BIT_LDO_VDD28_SHPT_PD ( BIT(8) )
869 #define BIT_LDO_SDIO_SHPT_PD ( BIT(7) )
870 #define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) )
871 #define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) )
872 #define BIT_LDO_SIM2_SHPT_PD ( BIT(4) )
873 #define BIT_LDO_SIM1_SHPT_PD ( BIT(3) )
874 #define BIT_LDO_SIM0_SHPT_PD ( BIT(2) )
875 #define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) )
876 #define BIT_LDO_CAMA_SHPT_PD ( BIT(0) )
878 /* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */
879 #define BIT_LDO_RF0_SHPT_PD ( BIT(7) )
880 #define BIT_LDO_GEN1_SHPT_PD ( BIT(6) )
881 #define BIT_LDO_GEN0_SHPT_PD ( BIT(5) )
882 #define BIT_LDO_CAMD_SHPT_PD ( BIT(4) )
883 #define BIT_LDO_VDD18_SHPT_PD ( BIT(3) )
884 #define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) )
885 #define BIT_LDO_KPLED_SHPT_PD ( BIT(1) )
886 #define BIT_LDO_VIBR_SHPT_PD ( BIT(0) )
888 /* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */
889 #define BIT_BATDET_CUR_EN ( BIT(4) )
890 #define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
892 /* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */
893 #define BIT_RTC_CLK_STOP_FLAG ( BIT(7) )
894 #define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
896 /* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */
897 #define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
899 /* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */
900 #define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
901 #define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
902 #define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
903 #define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) )
904 #define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
905 #define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
906 #define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
908 /* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */
909 #define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
910 #define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
912 /* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */
913 #define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
914 #define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
916 /* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */
917 #define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
918 #define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
920 /* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */
921 #define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
922 #define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
924 /* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */
925 #define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
927 /* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */
928 #define BIT_DCDC_WPA_DCM_ADI ( BIT(0) )
930 /* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */
931 #define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
932 #define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
934 /* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */
935 #define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
936 #define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
938 /* vars definitions for controller ANA_REGS_GLB */
940 #endif /* __SC2723_ANA_REGS_GLB_H__ */