arch/arm/include/asm/arch-sc9630/chip_x20l/__regs_mm_clk.h

   1 /*
   2  * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  */
  10
  11 #ifndef __REGS_MM_CLK_H__
  12 #define __REGS_MM_CLK_H__
  13
  14 #define REGS_MM_CLK
  15
  16 /* registers definitions for controller REGS_MM_CLK */
  17 #define REG_MM_CLK_MM_AHB_CFG           SCI_ADDR(REGS_MM_CLK_BASE, 0x0020)
  18 #define REG_MM_CLK_SENSOR_CFG           SCI_ADDR(REGS_MM_CLK_BASE, 0x0024)
  19 #define REG_MM_CLK_CCIR_CFG             SCI_ADDR(REGS_MM_CLK_BASE, 0x0028)
  20 #define REG_MM_CLK_DCAM_CFG             SCI_ADDR(REGS_MM_CLK_BASE, 0x002c)
  21 #define REG_MM_CLK_VSP_CFG              SCI_ADDR(REGS_MM_CLK_BASE, 0x0030)
  22 #define REG_MM_CLK_ISP_CFG              SCI_ADDR(REGS_MM_CLK_BASE, 0x0034)
  23 #define REG_MM_CLK_JPG_CFG              SCI_ADDR(REGS_MM_CLK_BASE, 0x0038)
  24 #define REG_MM_CLK_MIPI_CSI_CFG         SCI_ADDR(REGS_MM_CLK_BASE, 0x003c)
  25 #define REG_MM_CLK_CPHY_CFG_CFG         SCI_ADDR(REGS_MM_CLK_BASE, 0x0040)
  26 #define REG_MM_CLK_ORP_TCK_CFG          SCI_ADDR(REGS_MM_CLK_BASE, 0x0044)
  27
  28 /* vars definitions for controller REGS_MM_CLK */
  29
  30 #endif //__REGS_MM_CLK_H__