2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 #ifndef __H_REGS_AON_APB_RF_HEADFILE_H__
12 #define __H_REGS_AON_APB_RF_HEADFILE_H__ __FILE__
14 #define REGS_AON_APB_RF
16 /* registers definitions for AON_APB_RF */
17 #define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/
18 #define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/
19 #define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/
20 #define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/
21 #define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/
22 #define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/
23 #define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/
24 #define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/
25 #define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/
26 #define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/
27 #define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/
28 #define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/
29 #define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/
30 #define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/
31 #define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/
32 #define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/
33 #define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/
34 #define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044)/*MPLL_CFG1*/
35 #define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048)/*MPLL_CFG2*/
36 #define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C)/*DPLL_CFG1*/
37 #define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050)/*DPLL_CFG2*/
38 #define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054)/*TWPLL_CFG1*/
39 #define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058)/*TWPLL_CFG2*/
40 #define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C)/*LTEPLL_CFG1*/
41 #define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060)/*LTEPLL_CFG2*/
42 #define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064)/*LVDSDISPLL_CFG1*/
43 #define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068)/*LVDSDISPLL_CFG2*/
44 #define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*AON_REG_PROT*/
45 #define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*LDSP_BOOT_EN*/
46 #define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*LDSP_BOOT_VEC*/
47 #define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*LDSP_RST*/
48 #define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C)/*LDSP_MTX_CT1RL1*/
49 #define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080)/*LDSP_MTX_CTRL2*/
50 #define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084)/*LDSP_MTX_CTRL3*/
51 #define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088)/*AON_CGM_CFG*/
52 #define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C)/*LACC_MTX_CTRL*/
53 #define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090)/*CORTEX_MTX_CTRL1*/
54 #define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094)/*CORTEX_MTX_CTRL2*/
55 #define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*CORTEX_MTX_CTRL3*/
56 #define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*CA5_TCLK_DLY_LEN*/
57 #define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*CCIR_RCVR_CFG*/
58 #define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108)/*PLL_BG_CFG*/
59 #define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C)/*LVDSDIS_SEL*/
60 #define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110)/*DJTAG_MUX_SEL*/
61 #define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114)/*ARM7_SYS_SOFT_RST*/
62 #define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118)/*CP1_CP0_ADDR_MSB*/
63 #define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C)/*AON_DMA_INT_EN*/
64 #define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120)/*EMC_AUTO_GATE_EN*/
65 #define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124)/*ARM7_CFG_BUS*/
66 #define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128)/*RTC4M_0_CFG*/
67 #define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C)/*RTC4M_1_CFG*/
68 #define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130)/*AHB_RST2*/
69 #define REG_AON_APB_TGDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0134)/*TGDSP_BOOT_EN*/
70 #define REG_AON_APB_TGDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0138)/*TGDSP_BOOT_VEC*/
71 #define REG_AON_APB_TGDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x013C)/*TGDSP_RST*/
72 #define REG_AON_APB_RFFE_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0140)/*RFFE_CFG*/
73 #define REG_AON_APB_osc_ctrl SCI_ADDR(REGS_AON_APB_BASE, 0x0144)/*osc_ctrl*/
74 #define REG_AON_APB_OSC_OBS SCI_ADDR(REGS_AON_APB_BASE, 0x0148)/*CA53_OSC_OBS*/
75 #define REG_AON_APB_CA7_SDISABLE SCI_ADDR(REGS_AON_APB_BASE, 0x014C)/*CA7_SDISABLE*/
76 #define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*AP_WPROT_EN1*/
77 #define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*CP0_WPROT_EN1*/
78 #define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CP1_WPROT_EN1*/
79 #define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*IO_DLY_CTRL*/
80 #define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*AP_WPROT_EN0*/
81 #define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*CP0_WPROT_EN0*/
82 #define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP1_WPROT_EN0*/
83 #define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*PMU_RST_MONITOR*/
84 #define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*THM_RST_MONITOR*/
85 #define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*AP_RST_MONITOR*/
86 #define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*CA7_RST_MONITOR*/
87 #define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*BOND_OPT0*/
88 #define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*BOND_OPT1*/
89 #define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*RES_REG0*/
90 #define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*RES_REG1*/
91 #define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*AON_QOS_CFG*/
92 #define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*BB_LDO_CAL_START*/
93 #define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AON_MTX_PROT_CFG*/
94 #define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*LVDS_CFG*/
95 #define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*PLL_LOCK_OUT_SEL*/
96 #define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RTC4M_RC_VAL*/
97 #define REG_AON_APB_CP0_MISC_CTL0 SCI_ADDR(REGS_AON_APB_BASE, 0x306C)/*CP0_MISC_CTL0*/
98 #define REG_AON_APB_CP0_MCU_C2C_SEMA SCI_ADDR(REGS_AON_APB_BASE, 0x3070)/*CP0_MCU_C2C_SEMA*/
99 #define REG_AON_APB_CP0_MCU_CLK_CTL SCI_ADDR(REGS_AON_APB_BASE, 0x3074)/*CP0_MCU_CLK_CTL*/
100 #define REG_AON_APB_PROT_BUS_SECURE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*PROT_BUS_SECURE_EN*/
101 #define REG_AON_APB_PROT_ARM7_SPACE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*PROT_ARM7_SPACE_EN*/
102 #define REG_AON_APB_APB_ROM_PD_CTL SCI_ADDR(REGS_AON_APB_BASE, 0x3088)/*APB_ROM_PD_CTL*/
103 #define REG_AON_APB_CP0_SLP_STS SCI_ADDR(REGS_AON_APB_BASE, 0x308C)/*CP0_SLP_STS*/
104 #define REG_AON_APB_CP0_DSP_JTAG_CTL SCI_ADDR(REGS_AON_APB_BASE, 0x3090)/*CP0_DSP_JTAG_CTL*/
105 #define REG_AON_APB_ANA_PD_STS SCI_ADDR(REGS_AON_APB_BASE, 0x3094)/*ANA_PD_STS*/
106 #define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0)/*AON_APB_RSV*/
107 #define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*AON_CHIP_ID*/
108 #define REG_AON_APB_AON_CHIP_ID_DIG SCI_ADDR(REGS_AON_APB_BASE, 0x00F8)/*AON_DCHIP_ID_DIG*/
112 /* bits definitions for register REG_AON_APB_RF_APB_EB0 */
113 #define BIT_I2C_EB ( BIT(31) )
114 #define BIT_CA7_DAP_EB ( BIT(30) )
115 #define BIT_CA7_TS1_EB ( BIT(29) )
116 #define BIT_CA7_TS0_EB ( BIT(28) )
117 #define BIT_GPU_EB ( BIT(27) )
118 #define BIT_CKG_EB ( BIT(26) )
119 #define BIT_MM_EB ( BIT(25) )
120 #define BIT_AP_WDG_EB ( BIT(24) )
121 #define BIT_MSPI_EB ( BIT(23) )
122 #define BIT_SPLK_EB ( BIT(22) )
123 #define BIT_IPI_EB ( BIT(21) )
124 #define BIT_PIN_EB ( BIT(20) )
125 #define BIT_VBC_EB ( BIT(19) )
126 #define BIT_AUD_EB ( BIT(18) )
127 #define BIT_AUDIF_EB ( BIT(17) )
128 #define BIT_ADI_EB ( BIT(16) )
129 #define BIT_INTC_EB ( BIT(15) )
130 #define BIT_EIC_EB ( BIT(14) )
131 #define BIT_EFUSE_EB ( BIT(13) )
132 #define BIT_AP_TMR0_EB ( BIT(12) )
133 #define BIT_AON_TMR_EB ( BIT(11) )
134 #define BIT_AP_SYST_EB ( BIT(10) )
135 #define BIT_AON_SYST_EB ( BIT(9) )
136 #define BIT_KPD_EB ( BIT(8) )
137 #define BIT_PWM3_EB ( BIT(7) )
138 #define BIT_PWM2_EB ( BIT(6) )
139 #define BIT_PWM1_EB ( BIT(5) )
140 #define BIT_PWM0_EB ( BIT(4) )
141 #define BIT_GPIO_EB ( BIT(3) )
142 #define BIT_AON_GPIO_EB (BIT_GPIO_EB)
143 #define BIT_TPC_EB ( BIT(2) )
144 #define BIT_FM_EB ( BIT(1) )
145 #define BIT_ADC_EB ( BIT(0) )
147 /* bits definitions for register REG_AON_APB_RF_APB_EB1 */
148 #define BIT_MIPI_DSI_TXCLKHSSRC_DIV_EN ( BIT(28) )
149 #define BIT_ORP_JTAG_EB ( BIT(27) )
150 #define BIT_CA5_TS0_EB ( BIT(26) )
151 #define BIT_DEF_EB ( BIT(25) )
152 #define BIT_LVDS_PLL_DIV_EN ( BIT(24) )
153 #define BIT_ARM7_JTAG_EB ( BIT(23) )
154 #define BIT_AON_DMA_EB ( BIT(22) )
155 #define BIT_MBOX_EB ( BIT(21) )
156 #define BIT_DJTAG_EB ( BIT(20) )
157 #define BIT_RTC4M1_CAL_EB ( BIT(19) )
158 #define BIT_RTC4M0_CAL_EB ( BIT(18) )
159 #define BIT_MDAR_EB ( BIT(17) )
160 #define BIT_LVDS_TCXO_EB ( BIT(16) )
161 #define BIT_LVDS_TRX_EB ( BIT(15) )
162 #define BIT_CA5_DAP_EB ( BIT(14) )
163 #define BIT_GSP_EMC_EB ( BIT(13) )
164 #define BIT_ZIP_EMC_EB ( BIT(12) )
165 #define BIT_DISP_EMC_EB ( BIT(11) )
166 #define BIT_AP_TMR2_EB ( BIT(10) )
167 #define BIT_AP_TMR1_EB ( BIT(9) )
168 #define BIT_CA7_WDG_EB ( BIT(8) )
169 #define BIT_AVS_EB ( BIT(6) )
170 #define BIT_PROBE_EB ( BIT(5) )
171 #define BIT_AUX2_EB ( BIT(4) )
172 #define BIT_AUX1_EB ( BIT(3) )
173 #define BIT_AUX0_EB ( BIT(2) )
174 #define BIT_THM_EB ( BIT(1) )
175 #define BIT_PMU_EB ( BIT(0) )
177 /* bits definitions for register REG_AON_APB_RF_APB_RST0 */
178 #define BIT_CA5_TS0_SOFT_RST ( BIT(31) )
179 #define BIT_I2C_SOFT_RST ( BIT(30) )
180 #define BIT_CA7_TS1_SOFT_RST ( BIT(29) )
181 #define BIT_CA7_TS0_SOFT_RST ( BIT(28) )
182 #define BIT_DAP_MTX_SOFT_RST ( BIT(27) )
183 #define BIT_MSPI1_SOFT_RST ( BIT(26) )
184 #define BIT_MSPI0_SOFT_RST ( BIT(25) )
185 #define BIT_SPLK_SOFT_RST ( BIT(24) )
186 #define BIT_IPI_SOFT_RST ( BIT(23) )
187 #define BIT_CKG_SOFT_RST ( BIT(22) )
188 #define BIT_PIN_SOFT_RST ( BIT(21) )
189 #define BIT_VBC_SOFT_RST ( BIT(20) )
190 #define BIT_AUD_SOFT_RST ( BIT(19) )
191 #define BIT_AUDIF_SOFT_RST ( BIT(18) )
192 #define BIT_ADI_SOFT_RST ( BIT(17) )
193 #define BIT_INTC_SOFT_RST ( BIT(16) )
194 #define BIT_EIC_SOFT_RST ( BIT(15) )
195 #define BIT_EFUSE_SOFT_RST ( BIT(14) )
196 #define BIT_AP_WDG_SOFT_RST ( BIT(13) )
197 #define BIT_AP_TMR0_SOFT_RST ( BIT(12) )
198 #define BIT_AON_TMR_SOFT_RST ( BIT(11) )
199 #define BIT_AP_SYST_SOFT_RST ( BIT(10) )
200 #define BIT_AON_SYST_SOFT_RST ( BIT(9) )
201 #define BIT_KPD_SOFT_RST ( BIT(8) )
202 #define BIT_PWM3_SOFT_RST ( BIT(7) )
203 #define BIT_PWM2_SOFT_RST ( BIT(6) )
204 #define BIT_PWM1_SOFT_RST ( BIT(5) )
205 #define BIT_PWM0_SOFT_RST ( BIT(4) )
206 #define BIT_GPIO_SOFT_RST ( BIT(3) )
207 #define BIT_TPC_SOFT_RST ( BIT(2) )
208 #define BIT_FM_SOFT_RST ( BIT(1) )
209 #define BIT_ADC_SOFT_RST ( BIT(0) )
211 /* bits definitions for register REG_AON_APB_RF_APB_RST1 */
212 #define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) )
213 #define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) )
214 #define BIT_DEF_SOFT_RST ( BIT(29) )
215 #define BIT_ADC3_SOFT_RST ( BIT(28) )
216 #define BIT_ADC2_SOFT_RST ( BIT(27) )
217 #define BIT_ADC1_SOFT_RST ( BIT(26) )
218 #define BIT_MBOX_SOFT_RST ( BIT(25) )
219 #define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) )
220 #define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) )
221 #define BIT_LDSP_SYS_SOFT_RST ( BIT(21) )
222 #define BIT_LCP_SYS_SOFT_RST ( BIT(20) )
223 #define BIT_DAC3_SOFT_RST ( BIT(19) )
224 #define BIT_DAC2_SOFT_RST ( BIT(18) )
225 #define BIT_DAC1_SOFT_RST ( BIT(17) )
226 #define BIT_ADC3_CAL_SOFT_RST ( BIT(16) )
227 #define BIT_ADC2_CAL_SOFT_RST ( BIT(15) )
228 #define BIT_ADC1_CAL_SOFT_RST ( BIT(14) )
229 #define BIT_MDAR_SOFT_RST ( BIT(13) )
230 #define BIT_LVDSDIS_SOFT_RST ( BIT(12) )
231 #define BIT_BB_CAL_SOFT_RST ( BIT(11) )
232 #define BIT_DCXO_LC_SOFT_RST ( BIT(10) )
233 #define BIT_AP_TMR2_SOFT_RST ( BIT(9) )
234 #define BIT_AP_TMR1_SOFT_RST ( BIT(8) )
235 #define BIT_CA7_WDG_SOFT_RST ( BIT(7) )
236 #define BIT_AON_DMA_SOFT_RST ( BIT(6) )
237 #define BIT_AVS_SOFT_RST ( BIT(5) )
238 #define BIT_DMC_PHY_SOFT_RST ( BIT(4) )
239 #define BIT_GPU_THMA_SOFT_RST ( BIT(3) )
240 #define BIT_ARM_THMA_SOFT_RST ( BIT(2) )
241 #define BIT_THM_SOFT_RST ( BIT(1) )
242 #define BIT_PMU_SOFT_RST ( BIT(0) )
244 /* bits definitions for register REG_AON_APB_RF_APB_RTC_EB */
245 #define BIT_CP0_LTE_EB ( BIT(19) )
246 #define BIT_BB_CAL_RTC_EB ( BIT(18) )
247 #define BIT_DCXO_LC_RTC_EB ( BIT(17) )
248 #define BIT_AP_TMR2_RTC_EB ( BIT(16) )
249 #define BIT_AP_TMR1_RTC_EB ( BIT(15) )
250 #define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) )
251 #define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) )
252 #define BIT_GPU_THMA_RTC_EB ( BIT(12) )
253 #define BIT_ARM_THMA_RTC_EB ( BIT(11) )
254 #define BIT_THM_RTC_EB ( BIT(10) )
255 #define BIT_CA7_WDG_RTC_EB ( BIT(9) )
256 #define BIT_AP_WDG_RTC_EB ( BIT(8) )
257 #define BIT_EIC_RTCDV5_EB ( BIT(7) )
258 #define BIT_EIC_RTC_EB ( BIT(6) )
259 #define BIT_AP_TMR0_RTC_EB ( BIT(5) )
260 #define BIT_AON_TMR_RTC_EB ( BIT(4) )
261 #define BIT_AP_SYST_RTC_EB ( BIT(3) )
262 #define BIT_AON_SYST_RTC_EB ( BIT(2) )
263 #define BIT_KPD_RTC_EB ( BIT(1) )
264 #define BIT_ARCH_RTC_EB ( BIT(0) )
266 /* bits definitions for register REG_AON_APB_RF_REC_26MHZ_BUF_CFG */
267 #define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
268 #define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) )
269 #define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) )
271 /* bits definitions for register REG_AON_APB_RF_SINDRV_CTRL */
272 #define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
273 #define BIT_SINDRV_CLIP_MODE ( BIT(2) )
274 #define BIT_SINDRV_ENA_SQUARE ( BIT(1) )
275 #define BIT_SINDRV_ENA ( BIT(0) )
277 /* bits definitions for register REG_AON_APB_RF_ADA_SEL_CTRL */
279 /* bits definitions for register REG_AON_APB_RF_VBC_CTRL */
280 #define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) )
281 #define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
282 #define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
283 #define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
284 #define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
285 #define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
286 #define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
287 #define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
288 #define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
289 //#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) ) /*not used*/
290 //#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) ) /*not used*/
291 //#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) ) /*not used*/
292 //#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) ) /*not used*/
294 /* bits definitions for register REG_AON_APB_RF_PWR_CTRL */
295 #define BIT_HSIC_PLL_EN ( BIT(19) )
296 #define BIT_HSIC_PHY_PD ( BIT(18) )
297 #define BIT_HSIC_PS_PD_S ( BIT(17) )
298 #define BIT_HSIC_PS_PD_L ( BIT(16) )
299 #define BIT_MIPI_DSI_PS_PD_S ( BIT(15) )
300 #define BIT_MIPI_DSI_PS_PD_L ( BIT(14) )
301 #define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) )
302 #define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) )
303 #define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) )
304 #define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) )
305 #define BIT_CA7_TS1_STOP ( BIT(9) )
306 #define BIT_CA7_TS0_STOP ( BIT(8) )
307 #define BIT_EFUSE_BIST_PWR_ON ( BIT(3) )
308 #define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) )
309 #define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) )
310 #define BIT_USB_PHY_PD ( BIT(0) )
312 /* bits definitions for register REG_AON_APB_RF_TS_CFG */
313 #define BIT_CSYSACK_TS_LP_2 ( BIT(13) )
314 #define BIT_CSYSREQ_TS_LP_2 ( BIT(12) )
315 #define BIT_CSYSACK_TS_LP_1 ( BIT(11) )
316 #define BIT_CSYSREQ_TS_LP_1 ( BIT(10) )
317 #define BIT_CSYSACK_TS_LP_0 ( BIT(9) )
318 #define BIT_CSYSREQ_TS_LP_0 ( BIT(8) )
319 #define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) )
320 #define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) )
321 #define BIT_EVENT_HALTREQ_TS01 ( BIT(0) )
323 /* bits definitions for register REG_AON_APB_RF_BOOT_MODE */
324 #define BIT_ARM_JTAG_EN ( BIT(13) )
325 #define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) )
326 #define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) )
327 #define BIT_PTEST_FUNC_MODE ( BIT(7) )
328 #define BIT_USB_DLOAD_EN ( BIT(4) )
329 #define BIT_ARM_BOOT_MD3 ( BIT(3) )
330 #define BIT_ARM_BOOT_MD2 ( BIT(2) )
331 #define BIT_ARM_BOOT_MD1 ( BIT(1) )
332 #define BIT_ARM_BOOT_MD0 ( BIT(0) )
334 /* bits definitions for register REG_AON_APB_RF_BB_BG_CTRL */
335 #define BIT_BB_CON_BG ( BIT(22) )
336 #define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
337 #define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
338 #define BIT_BB_BG_RBIAS_EN ( BIT(15) )
339 #define BIT_BB_BG_IEXT_IB_EN ( BIT(14) )
340 #define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
341 #define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) )
342 #define BIT_BB_LDO_SLP_PD_EN ( BIT(10) )
343 #define BIT_BB_LDO_FORCE_ON ( BIT(9) )
344 #define BIT_BB_LDO_FORCE_PD ( BIT(8) )
345 #define BIT_BB_BG_AUTO_PD_EN ( BIT(3) )
346 #define BIT_BB_BG_SLP_PD_EN ( BIT(2) )
347 #define BIT_BB_BG_FORCE_ON ( BIT(1) )
348 #define BIT_BB_BG_FORCE_PD ( BIT(0) )
350 /* bits definitions for register REG_AON_APB_RF_CP_ARM_JTAG_CTRL */
351 #define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
353 /* bits definitions for register REG_AON_APB_RF_PLL_SOFT_CNT_DONE */
354 #define BIT_RC1_SOFT_CNT_DONE ( BIT(13) )
355 #define BIT_RC0_SOFT_CNT_DONE ( BIT(12) )
356 #define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) )
357 #define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) )
358 #define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) )
359 #define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) )
360 #define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) )
361 #define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) )
362 #define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) )
364 /* bits definitions for register REG_AON_APB_RF_DCXO_LC_REG0 */
365 #define BIT_DCXO_LC_FLAG ( BIT(8) )
366 #define BIT_DCXO_LC_FLAG_CLR ( BIT(1) )
367 #define BIT_DCXO_LC_CNT_CLR ( BIT(0) )
369 /* bits definitions for register REG_AON_APB_RF_DCXO_LC_REG1 */
370 #define BITS_DCXO_LC_CNT(_X_) (_X_)
372 /* bits definitions for register REG_AON_APB_RF_MPLL_CFG1 */
373 #define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
374 #define BIT_MPLL_LOCK_DONE ( BIT(27) )
375 #define BIT_MPLL_DIV_S ( BIT(26) )
376 #define BIT_MPLL_MOD_EN ( BIT(25) )
377 #define BIT_MPLL_SDM_EN ( BIT(24) )
378 #define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
379 #define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
380 #define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
381 #define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
383 /* bits definitions for register REG_AON_APB_RF_MPLL_CFG2 */
384 #define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
385 #define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
387 /* bits definitions for register REG_AON_APB_RF_DPLL_CFG1 */
388 #define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
389 #define BIT_DPLL_LOCK_DONE ( BIT(27) )
390 #define BIT_DPLL_DIV_S ( BIT(26) )
391 #define BIT_DPLL_MOD_EN ( BIT(25) )
392 #define BIT_DPLL_SDM_EN ( BIT(24) )
393 #define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
394 #define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
395 #define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
396 #define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
398 /* bits definitions for register REG_AON_APB_RF_DPLL_CFG2 */
399 #define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
400 #define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
402 /* bits definitions for register REG_AON_APB_RF_TWPLL_CFG1 */
403 #define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
404 #define BIT_TWPLL_LOCK_DONE ( BIT(27) )
405 #define BIT_TWPLL_DIV_S ( BIT(26) )
406 #define BIT_TWPLL_MOD_EN ( BIT(25) )
407 #define BIT_TWPLL_SDM_EN ( BIT(24) )
408 #define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
409 #define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
410 #define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
411 #define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
413 /* bits definitions for register REG_AON_APB_RF_TWPLL_CFG2 */
414 #define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
415 #define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
417 /* bits definitions for register REG_AON_APB_RF_LTEPLL_CFG1 */
418 #define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
419 #define BIT_LTEPLL_LOCK_DONE ( BIT(27) )
420 #define BIT_LTEPLL_DIV_S ( BIT(26) )
421 #define BIT_LTEPLL_MOD_EN ( BIT(25) )
422 #define BIT_LTEPLL_SDM_EN ( BIT(24) )
423 #define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
424 #define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
425 #define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
426 #define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
428 /* bits definitions for register REG_AON_APB_RF_LTEPLL_CFG2 */
429 #define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
430 #define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
432 /* bits definitions for register REG_AON_APB_RF_LVDSDISPLL_CFG1 */
433 #define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
434 #define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) )
435 #define BIT_LVDSDISPLL_DIV_S ( BIT(26) )
436 #define BIT_LVDSDISPLL_MOD_EN ( BIT(25) )
437 #define BIT_LVDSDISPLL_SDM_EN ( BIT(24) )
438 #define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
439 #define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
440 #define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
441 #define BITS_LVDSDISPLL_POSTDIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
442 #define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
444 /* bits definitions for register REG_AON_APB_RF_LVDSDISPLL_CFG2 */
445 #define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
446 #define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
448 /* bits definitions for register REG_AON_APB_RF_AON_REG_PROT */
449 #define BIT_LDSP_CTRL_PROT ( BIT(31) )
450 #define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
452 /* bits definitions for register REG_AON_APB_RF_LDSP_BOOT_EN */
453 #define BIT_FRC_CLK_LDSP_EN ( BIT(1) )
454 #define BIT_LDSP_BOOT_EN ( BIT(0) )
456 /* bits definitions for register REG_AON_APB_RF_LDSP_BOOT_VEC */
457 #define BITS_LDSP_BOOT_VECTOR(_X_) (_X_)
459 /* bits definitions for register REG_AON_APB_RF_LDSP_RST */
460 #define BIT_LDSP_SYS_SRST ( BIT(1) )
461 #define BIT_LDSP_CORE_SRST_N ( BIT(0) )
463 /* bits definitions for register REG_AON_APB_RF_LDSP_MTX_CTRL1 */
464 #define BITS_LDSP_MTX_CTRL1(_X_) (_X_)
466 /* bits definitions for register REG_AON_APB_RF_LDSP_MTX_CTRL2 */
467 #define BITS_LDSP_MTX_CTRL2(_X_) (_X_)
469 /* bits definitions for register REG_AON_APB_RF_LDSP_MTX_CTRL3 */
470 #define BITS_LDSP_MTX_CTRL3(_X_) (_X_)
472 /* bits definitions for register REG_AON_APB_RF_AON_CGM_CFG */
473 #define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
474 #define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
475 #define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
476 #define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
477 #define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
478 #define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
479 #define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
480 #define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
482 /* bits definitions for register REG_AON_APB_RF_LACC_MTX_CTRL */
483 #define BITS_LACC_MTX_CTRL(_X_) (_X_)
485 /* bits definitions for register REG_AON_APB_RF_CORTEX_MTX_CTRL1 */
486 #define BITS_CORTEX_MTX_CTRL1(_X_) (_X_)
488 /* bits definitions for register REG_AON_APB_RF_CORTEX_MTX_CTRL2 */
489 #define BITS_CORTEX_MTX_CTRL2(_X_) (_X_)
491 /* bits definitions for register REG_AON_APB_RF_CORTEX_MTX_CTRL3 */
492 #define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
494 /* bits definitions for register REG_AON_APB_RF_CA5_TCLK_DLY_LEN */
495 #define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
497 /* bits definitions for register REG_AON_APB_RF_CCIR_RCVR_CFG */
498 #define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
499 #define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
500 #define BIT_CCIR_SE ( BIT(1) )
501 #define BIT_CCIR_IE ( BIT(0) )
503 /* bits definitions for register REG_AON_APB_PLL_BG_CFG */
504 #define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
505 #define BIT_PLL_BG_RBIAS_EN ( BIT(3) )
506 #define BIT_PLL_BG_PD ( BIT(2) )
507 #define BIT_PLL_BG_IEXT_IBEN ( BIT(1) )
508 #define BIT_PLL_CON_BG ( BIT(0) )
510 /* bits definitions for register REG_AON_APB_RF_LVDSDIS_SEL */
511 #define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
512 #define BIT_LVDSDIS_DBG_SEL ( BIT(0) )
514 /* bits definitions for register REG_AON_APB_RF_DJTAG_MUX_SEL */
515 #define BIT_DJTAG_AON_SEL ( BIT(6) )
516 #define BIT_DJTAG_PUB_SEL ( BIT(5) )
517 #define BIT_DJTAG_CP1_SEL ( BIT(4) )
518 #define BIT_DJTAG_CP0_SEL ( BIT(3) )
519 #define BIT_DJTAG_GPU_SEL ( BIT(2) )
520 #define BIT_DJTAG_MM_SEL ( BIT(1) )
521 #define BIT_DJTAG_AP_SEL ( BIT(0) )
523 /* bits definitions for register REG_AON_APB_RF_ARM7_SYS_SOFT_RST */
524 #define BIT_ARM7_SYS_SOFT_RST ( BIT(4) )
525 #define BIT_ARM7_CORE_SOFT_RST ( BIT(0) )
527 /* bits definitions for register REG_AON_APB_RF_CP1_CP0_ADDR_MSB */
528 #define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
530 /* bits definitions for register REG_AON_APB_RF_AON_DMA_INT_EN */
531 #define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) )
532 #define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) )
533 #define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) )
534 #define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) )
535 #define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) )
536 #define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) )
537 #define BIT_AON_DMA_INT_AP_EN ( BIT(0) )
539 /* bits definitions for register REG_AON_APB_RF_CP0_ADDR_REMAP_CTRL0 */
540 #define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) )
541 #define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) )
542 #define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) )
543 #define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) )
544 #define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) )
545 #define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) )
546 #define BIT_AP_EMC_AUTO_GATE_EN ( BIT(1) )
547 #define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(0) )
549 /* bits definitions for register REG_AON_APB_RF_ARM7_CFG_BUS */
550 #define BIT_FUNCTST_DMA_EB ( BIT(2) )
551 #define BIT_ARM7_FUNCTST_BUS_SLEEP ( BIT(1) )
552 #define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) )
554 /* bits definitions for register REG_AON_APB_RF_CP1_ADDR_REMAP_CTRL0 */
555 #define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
556 #define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
557 #define BIT_RTC4M0_CAL_DONE ( BIT(6) )
558 #define BIT_RTC4M0_CAL_START ( BIT(5) )
559 #define BIT_RTC4M0_CHOP_EN ( BIT(4) )
560 #define BIT_RTC4M0_FORCE_EN ( BIT(1) )
561 #define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) )
563 /* bits definitions for register REG_AON_APB_RTC4M_1_CFG */
564 #define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
565 #define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
566 #define BIT_RTC4M1_CAL_DONE ( BIT(6) )
567 #define BIT_RTC4M1_CAL_START ( BIT(5) )
568 #define BIT_RTC4M1_CHOP_EN ( BIT(4) )
569 #define BIT_RTC4M1_FORCE_EN ( BIT(1) )
570 #define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) )
572 /* bits definitions for register REG_AON_APB_RF_CP1_ADDR_REMAP_CTRL1 */
573 #define BIT_AON_DJTAG_SOFT_RST ( BIT(6) )
574 #define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) )
575 #define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) )
576 #define BIT_MM_DJTAG_SOFT_RST ( BIT(3) )
577 #define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) )
578 #define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) )
579 #define BIT_AP_DJTAG_SOFT_RST ( BIT(0) )
581 /* bits definitions for register REG_AON_APB_RF_TGDSP_BOOT_EN */
582 #define BIT_AHB_VCP1_DEEP_SLEEP_EN ( BIT(4) )
583 #define BIT_ASHB_ARMTODSP_EN ( BIT(3) )
584 #define BIT_ARM_DAHB_SLEEP_EN ( BIT(2) )
585 #define BIT_FRC_CLK_TGDSP_EN ( BIT(1) )
586 #define BIT_TGDSP_BOOT_EN ( BIT(0) )
588 /* bits definitions for register REG_AON_APB_RF_TGDSP_BOOT_VEC */
589 #define BITS_AON_APB_RF_TGDSP_BOOT_VECTOR(_X_) (_X_)
591 /* bits definitions for register REG_AON_APB_RF_TGDSP_RST */
592 #define BIT_AON_APB_RF_TGDSP_SYS_SRST ( BIT(1) )
593 #define BIT_AON_APB_RF_TGDSP_CORE_SRST_N ( BIT(0) )
595 /* bits definitions for register REG_AON_APB_RF_RFFE_CFG */
596 #define BIT_AON_APB_RF_LTE_RFFE_SEL ( BIT(1) )
597 #define BIT_AON_APB_RF_TG_RFFE_SEL ( BIT(0) )
599 /* bits definitions for register REG_AON_APB_RF_osc_ctrl */
600 #define BITS_AON_APB_RF_OSC_CTRL_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) )
601 #define BIT_AON_APB_RF_OSC_CTRL_EN ( BIT(15) )
602 #define BIT_AON_APB_RF_OSC_CTRL_START ( BIT(14) )
603 #define BIT_AON_APB_RF_OSC_CTRL_RSTN ( BIT(13) )
604 #define BITS_AON_APB_RF_OSC_CTRL_CLK_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
606 /* bits definitions for register REG_AON_APB_RF_OSC_OBS */
607 #define BIT_AON_APB_RF_OSC_OBS_OVERFLOW ( BIT(15) )
608 #define BITS_AON_APB_RF_OSC_OBS_SPEED_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
610 /* bits definitions for register REG_AON_APB_RF_CA7_SDISABLE */
611 #define BIT_AON_APB_RF_CA7_CFGSDISABLE ( BIT(4) )
612 #define BITS_AON_APB_RF_CA7_CP15SDISABLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
614 /* bits definitions for register REG_AON_APB_RF_AP_WPROT_EN1 */
615 #define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_)
617 /* bits definitions for register REG_AON_APB_RF_CP0_WPROT_EN1 */
618 #define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_)
620 /* bits definitions for register REG_AON_APB_RF_CP1_WPROT_EN1 */
621 #define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_)
623 /* bits definitions for register REG_AON_APB_RF_IO_DLY_CTRL */
624 #define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
625 #define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
626 #define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
628 /* bits definitions for register REG_AON_APB_RF_AP_WPROT_EN */
629 #define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_)
631 /* bits definitions for register REG_AON_APB_RF_CP0_WPROT_EN */
632 #define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_)
634 /* bits definitions for register REG_AON_APB_RF_CP1_WPROT_EN */
635 #define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_)
637 /* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
638 #define BITS_PMU_RST_MONITOR(_X_) (_X_)
640 /* bits definitions for register REG_AON_APB_RF_THM_RST_MONITOR */
641 #define BITS_THM_RST_MONITOR(_X_) (_X_)
643 /* bits definitions for register REG_AON_APB_RF_AP_RST_MONITOR */
644 #define BITS_AP_RST_MONITOR(_X_) (_X_)
646 /* bits definitions for register REG_AON_APB_RF_CA7_RST_MONITOR */
647 #define BITS_CA7_RST_MONITOR(_X_) (_X_)
649 /* bits definitions for register REG_AON_APB_RF_BOND_OPT0 */
650 #define BITS_BOND_OPTION0(_X_) (_X_)
652 /* bits definitions for register REG_AON_APB_RF_BOND_OPT1 */
653 #define BITS_BOND_OPTION1(_X_) (_X_)
655 /* bits definitions for register REG_AON_APB_RF_RES_REG0 */
656 #define BITS_RES_REG0(_X_) (_X_)
658 /* bits definitions for register REG_AON_APB_RF_RES_REG1 */
659 #define BITS_RES_REG1(_X_) (_X_)
661 /* bits definitions for register REG_AON_APB_RF_AON_QOS_CFG */
662 #define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
663 #define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
664 #define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
665 #define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
667 /* bits definitions for register REG_AON_APB_RF_BB_LDO_CAL_START */
668 #define BIT_BB_LDO_CAL_START ( BIT(0) )
670 /* bits definitions for register REG_AON_APB_RF_AON_MTX_PROT_CFG */
671 #define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
672 #define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
674 /* bits definitions for register REG_AON_APB_RF_LVDS_CFG */
675 #define BITS_LVDSDIS_TXIMP(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) )
676 #define BITS_LVDSDIS_TXPD(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
677 #define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
678 #define BIT_LVDSDIS_OFF_OCT ( BIT(15) )
679 #define BIT_LVDSDIS_OFF_CL ( BIT(14) )
680 #define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
681 #define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
682 #define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
683 #define BIT_LVDSDIS_CLKOUT_EN ( BIT(7) )
684 #define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
685 #define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
687 /* bits definitions for register REG_AON_APB_RF_PLL_LOCK_OUT_SEL */
688 #define BITS_DPLL_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
689 #define BITS_LPLL_DBG_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
690 #define BITS_LVDSPLL_DBG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
691 #define BITS_MPLL_DBG_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
692 #define BITS_TWPLL_DBG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
693 #define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) )
694 #define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
695 #define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
697 /* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */
698 #define BIT_RTC4M1_RC_SEL ( BIT(31) )
699 #define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
700 #define BIT_RTC4M0_RC_SEL ( BIT(15) )
701 #define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
703 /* bits definitions for register REG_AON_APB_RF_CP0_MISC_CTL0 */
704 #define BITS_ARM_FRC_STOP(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
705 #define BIT_MCU_FORCE_LIGHT_SLEEP ( BIT(5) )
706 #define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(4) )
707 #define BIT_CHIP_SLP_ARM_CLR ( BIT(3) )
708 #define BIT_ALL_CLK_EN ( BIT(2) )
709 #define BIT_WAKEUP_XTL_EN_2G ( BIT(1) )
710 #define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(0) )
712 /* bits definitions for register REG_AON_APB_RF_CP0_MCU_C2C_SEMA */
713 #define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
715 /* bits definitions for register REG_AON_APB_RF_CP0_MCU_CLK_CTL */
716 #define BIT_CLK_MCU_DBG_SEL ( BIT(4) )
717 #define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
718 #define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
720 /* bits definitions for register REG_AON_APB_RF_PROT_BUS_SECURE_EN */
721 #define BIT_BUS_SECURE_EN ( BIT(0) )
723 /* bits definitions for register REG_AON_APB_RF_PROT_ARM7_SPACE_EN */
724 #define BIT_ARM7_SPACE_EN ( BIT(0) )
726 /* bits definitions for register REG_AON_APB_RF_APB_ROM_PD_CTL */
727 #define BIT_ROM_FORCE_ON ( BIT(0) )
729 /* bits definitions for register REG_AON_APB_RF_CP0_SLP_STS */
730 #define BITS_CP0_SLP_STS(_X_) (_X_)
732 /* bits definitions for register REG_AON_APB_RF_CP0_DSP_JTAG_CTL */
733 #define BIT_CEVA_SW_JTAG_ENA ( BIT(8) )
734 #define BIT_STDO ( BIT(4) )
735 #define BIT_STCK ( BIT(3) )
736 #define BIT_STMS ( BIT(2) )
737 #define BIT_STDI ( BIT(1) )
738 #define BIT_STRTCK ( BIT(0) )
740 /* bits definitions for register REG_AON_APB_RF_ANA_PD_STS */
741 #define BITS_ANA_PD_STS(_X_) (_X_)
743 /* bits definitions for register REG_AON_APB_RF_AON_APB_RSV */
744 #define BITS_AON_APB_RSV(_X_) (_X_)
746 /* bits definitions for register REG_AON_APB_RF_AON_CHIP_ID */
747 #define BITS_AON_CHIP_ID(_X_) (_X_)
749 /* bits definitions for register REG_AON_APB_RF_AON_CHIP_ID_DIG */
750 #define BITS_AON_CHIP_ID_DIG(_X_) (_X_)
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